authorgravatar for paul.verigo@gmail.comPavel Verigo <paul.verigo@gmail.com> 2026-07-06 12:19:58+02:00
committergravatar for paul.verigo@gmail.comPavel Verigo <paul.verigo@gmail.com> 2026-07-06 20:49:08+02:00
log73f6d498fc83763054f62677f3a67871d3825136
treec69510bf6967ac6316d77e10700f453f741941c7
parentca72c56e0c93e8ebe4ab7533a8c1ae65c3767b95

compiler: use @divCeil

15 files changed, 50 insertions(+), 51 deletions(-)

src/Air.zig+3-3
......@@ -1517,7 +1517,7 @@ pub const ShuffleTwoMask = enum(u32) {
15171517/// Trailing:
15181518/// 0. `Inst.Ref` for every outputs_len
15191519/// 1. `Inst.Ref` for every inputs_len
1520/// 2. A number of u32 elements follow according to the equation `(source_len + 3) / 4`.
1520/// 2. A number of u32 elements follow according to the equation `@divCeil(source_len, 4)`.
15211521/// Memory starting at this position is reinterpreted as the source bytes.
15221522/// 3. for every outputs_len
15231523/// - constraint: memory at this position is reinterpreted as a null
......@@ -2225,7 +2225,7 @@ pub fn unwrapSwitch(air: *const Air, switch_inst: Inst.Index) UnwrappedSwitch {
22252225 }
22262226 const pl_op = inst.data.pl_op;
22272227 const extra = air.extraData(SwitchBr, pl_op.payload);
2228 const hint_bag_count = std.math.divCeil(usize, extra.data.cases_len + 1, 10) catch unreachable;
2228 const hint_bag_count = @divCeil(extra.data.cases_len + 1, 10);
22292229 return .{
22302230 .air = air,
22312231 .operand = pl_op.operand,
......@@ -2394,7 +2394,7 @@ pub const UnwrappedAsm = struct {
23942394 const name = std.mem.sliceTo(constraint_name[constraint.len + 1 ..], 0);
23952395 // This equation accounts for the fact that even if we have exactly 4 bytes
23962396 // for the string, we still use the next u32 for the null terminator.
2397 const next_offset = std.math.divCeil(usize, constraint.len + 1 + name.len + 1, @sizeOf(u32)) catch unreachable;
2397 const next_offset = @divCeil(constraint.len + 1 + name.len + 1, @sizeOf(u32));
23982398 self.constraint_names = self.constraint_names[next_offset..];
23992399
24002400 return .{
src/Air/Legalize.zig+1-1
......@@ -746,7 +746,7 @@ fn legalizeBody(l: *Legalize, body_start: usize, body_len: usize) Error!void {
746746 .switch_br, .loop_switch_br => {
747747 const pl_op = l.air_instructions.items(.data)[@intFromEnum(inst)].pl_op;
748748 const extra = l.extraData(Air.SwitchBr, pl_op.payload);
749 const hint_bag_count = std.math.divCeil(usize, extra.data.cases_len + 1, 10) catch unreachable;
749 const hint_bag_count = @divCeil(extra.data.cases_len + 1, 10);
750750 var extra_index = extra.end + hint_bag_count;
751751 for (0..extra.data.cases_len) |_| {
752752 const case_extra = l.extraData(Air.SwitchBr.Case, extra_index);
src/InternPool.zig+3-3
......@@ -3581,11 +3581,11 @@ pub fn loadStructType(ip: *const InternPool, index: Index) LoadedStructType {
35813581 .start = extra_index,
35823582 .len = extra.data.fields_len,
35833583 } else .empty;
3584 extra_index += std.math.divCeil(u32, field_aligns.len, 4) catch unreachable;
3584 extra_index += @divCeil(field_aligns.len, 4);
35853585 const field_is_comptime_bits: LoadedStructType.ComptimeBits = if (extra.data.flags.any_comptime_fields) .{
35863586 .tid = unwrapped_index.tid,
35873587 .start = extra_index,
3588 .len = std.math.divCeil(u32, extra.data.fields_len, 32) catch unreachable,
3588 .len = @divCeil(extra.data.fields_len, 32),
35893589 } else .empty;
35903590 extra_index += field_is_comptime_bits.len;
35913591 const field_runtime_order: LoadedStructType.RuntimeOrder.Slice = if (extra.data.flags.layout == .auto) .{
......@@ -3737,7 +3737,7 @@ pub fn loadUnionType(ip: *const InternPool, index: Index) LoadedUnionType {
37373737 .start = extra_index,
37383738 .len = extra.data.fields_len,
37393739 } else .empty;
3740 extra_index += std.math.divCeil(u32, field_aligns.len, 4) catch unreachable;
3740 extra_index += @divCeil(field_aligns.len, 4);
37413741
37423742 return .{
37433743 .zir_index = extra.data.zir_index,
src/Sema.zig+5-5
......@@ -10305,7 +10305,7 @@ fn finishSwitchBr(
1030510305 fn ensureUnusedCapacity(hints: *@This(), gpa_inner: Allocator, additional_count: u32) Allocator.Error!void {
1030610306 const unused_hints = hints.bags.capacity * hints_per_bag - hints.count;
1030710307 if (unused_hints >= additional_count) return;
10308 const bags_required = std.math.divCeil(u32, hints.count + additional_count, hints_per_bag) catch unreachable;
10308 const bags_required = @divCeil(hints.count + additional_count, hints_per_bag);
1030910309 return hints.bags.ensureUnusedCapacity(gpa_inner, bags_required);
1031010310 }
1031110311 fn appendAssumeCapacity(hints: *@This(), hint: std.lang.BranchHint) void {
......@@ -10321,7 +10321,7 @@ fn finishSwitchBr(
1032110321 }
1032210322 };
1032310323 var branch_hints: BranchHints = hints: {
10324 const num_bags = std.math.divCeil(u32, estimated_cases_len, BranchHints.hints_per_bag) catch unreachable;
10324 const num_bags = @divCeil(estimated_cases_len, BranchHints.hints_per_bag);
1032510325 break :hints .{ .bags = try .initCapacity(gpa, num_bags), .count = 0 };
1032610326 };
1032710327 defer branch_hints.bags.deinit(gpa);
......@@ -12212,7 +12212,7 @@ fn analyzeSwitchPayloadCaptureTaggedUnion(
1221212212 {
1221312213 // All branch hints are `.none`, so just add zero elems.
1221412214 comptime assert(@intFromEnum(std.lang.BranchHint.none) == 0);
12215 const need_elems = std.math.divCeil(usize, field_indices.len + 1, 10) catch unreachable;
12215 const need_elems = @divCeil(field_indices.len + 1, 10);
1221612216 try cases_extra.appendNTimes(gpa, 0, need_elems);
1221712217 }
1221812218
......@@ -18698,7 +18698,7 @@ fn finishStructInit(
1869818698 return sema.addConstantMaybeRef(sema.resolveValue(final_val_ref).?, is_ref);
1869918699 },
1870018700 .@"packed" => {
18701 const buf = try sema.arena.alloc(u8, @intCast((struct_ty.bitSize(zcu) + 7) / 8));
18701 const buf = try sema.arena.alloc(u8, @intCast(@divCeil(struct_ty.bitSize(zcu), 8)));
1870218702 @memset(buf, 0);
1870318703 var bit_offset: u16 = 0;
1870418704 for (field_inits) |field_init| {
......@@ -29745,7 +29745,7 @@ pub fn bitCastVal(
2974529745 if (val.isUndef(zcu)) {
2974629746 return pt.undefValue(dest_ty);
2974729747 } else {
29748 const buf = try sema.arena.alloc(u8, @intCast((bit_size + 7) / 8));
29748 const buf = try sema.arena.alloc(u8, @intCast(@divCeil(bit_size, 8)));
2974929749 @memset(buf, 0);
2975029750 val.writeToPackedMemory(zcu, buf, 0);
2975129751 return .readFromPackedMemory(dest_ty, pt, buf, 0);
src/Sema/arith.zig+7-7
......@@ -2193,12 +2193,12 @@ fn floatDivCeil(sema: *Sema, lhs: Value, rhs: Value, ty: Type) !Value {
21932193 const pt = sema.pt;
21942194 const zcu = pt.zcu;
21952195 const target = zcu.getTarget();
2196 const storage: InternPool.Key.Float.Storage = switch (ty.floatBits(target)) { // TODO
2197 16 => .{ .f16 = @ceil(lhs.toFloat(f16, zcu) / rhs.toFloat(f16, zcu)) },
2198 32 => .{ .f32 = @ceil(lhs.toFloat(f32, zcu) / rhs.toFloat(f32, zcu)) },
2199 64 => .{ .f64 = @ceil(lhs.toFloat(f64, zcu) / rhs.toFloat(f64, zcu)) },
2200 80 => .{ .f80 = @ceil(lhs.toFloat(f80, zcu) / rhs.toFloat(f80, zcu)) },
2201 128 => .{ .f128 = @ceil(lhs.toFloat(f128, zcu) / rhs.toFloat(f128, zcu)) },
2196 const storage: InternPool.Key.Float.Storage = switch (ty.floatBits(target)) {
2197 16 => .{ .f16 = @divCeil(lhs.toFloat(f16, zcu), rhs.toFloat(f16, zcu)) },
2198 32 => .{ .f32 = @divCeil(lhs.toFloat(f32, zcu), rhs.toFloat(f32, zcu)) },
2199 64 => .{ .f64 = @divCeil(lhs.toFloat(f64, zcu), rhs.toFloat(f64, zcu)) },
2200 80 => .{ .f80 = @divCeil(lhs.toFloat(f80, zcu), rhs.toFloat(f80, zcu)) },
2201 128 => .{ .f128 = @divCeil(lhs.toFloat(f128, zcu), rhs.toFloat(f128, zcu)) },
22022202 else => unreachable,
22032203 };
22042204 return .fromInterned(try pt.intern(.{ .float = .{
......@@ -2304,7 +2304,7 @@ fn intValueAa(sema: *Sema, ty: Type) !Value {
23042304 if (ty.toIntern() == .u0_type) return pt.intValue(ty, 0);
23052305 const info = ty.intInfo(zcu);
23062306
2307 const buf = try sema.arena.alloc(u8, (info.bits + 7) / 8);
2307 const buf = try sema.arena.alloc(u8, @divCeil(info.bits, 8));
23082308 @memset(buf, 0xAA);
23092309
23102310 const limbs = try sema.arena.alloc(
src/Type.zig+3-3
......@@ -968,7 +968,7 @@ pub fn abiAlignment(ty: Type, zcu: *const Zcu) Alignment {
968968 if (vector_type.len > 256 and target.cpu.has(.x86, .avx512f)) return .@"64";
969969 if (vector_type.len > 128 and target.cpu.has(.x86, .avx)) return .@"32";
970970 if (vector_type.len > 64) return .@"16";
971 const bytes = std.math.divCeil(u32, vector_type.len, 8) catch unreachable;
971 const bytes = @divCeil(vector_type.len, 8);
972972 return .fromByteUnits(std.math.ceilPowerOfTwoAssert(u32, bytes));
973973 }
974974 const elem_bytes: u32 = @intCast(Type.fromInterned(vector_type.child).abiSize(zcu));
......@@ -1111,10 +1111,10 @@ pub fn abiSize(ty: Type, zcu: *const Zcu) u64 {
11111111 .vector_type => |vec| {
11121112 const elem_ty: Type = .fromInterned(vec.child);
11131113 const bytes = switch (zcu.comp.getZigBackend()) {
1114 else => std.math.divCeil(u64, vec.len * elem_ty.bitSize(zcu), 8) catch unreachable,
1114 else => @divCeil(vec.len * elem_ty.bitSize(zcu), 8),
11151115 .stage2_c, .stage2_wasm => vec.len * elem_ty.abiSize(zcu),
11161116 .stage2_x86_64 => switch (elem_ty.toIntern()) {
1117 .bool_type => std.math.divCeil(u64, vec.len, 8) catch unreachable,
1117 .bool_type => @divCeil(vec.len, 8),
11181118 else => vec.len * elem_ty.abiSize(zcu),
11191119 },
11201120 };
src/codegen/aarch64/Select.zig+10-10
......@@ -405,11 +405,11 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {
405405 .live_registers = undefined,
406406 .repeat_list = undefined,
407407 });
408 try isel.dom.appendNTimes(gpa, 0, std.math.divCeil(usize, isel.dom_len, @bitSizeOf(DomInt)) catch unreachable);
408 try isel.dom.appendNTimes(gpa, 0, @divCeil(isel.dom_len, @bitSizeOf(DomInt)));
409409 try isel.analyze(air_body_block.body);
410410 for (
411411 isel.dom.items[initial_dom_start..].ptr,
412 isel.dom.items[isel.dom_start..][0 .. std.math.divCeil(usize, initial_dom_len, @bitSizeOf(DomInt)) catch unreachable],
412 isel.dom.items[isel.dom_start..][0..@divCeil(initial_dom_len, @bitSizeOf(DomInt))],
413413 ) |*initial_dom, loop_dom| initial_dom.* |= loop_dom;
414414 isel.dom_start = initial_dom_start;
415415 isel.dom_len = initial_dom_len;
......@@ -591,7 +591,7 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {
591591 .live_registers = undefined,
592592 .repeat_list = undefined,
593593 });
594 try isel.dom.appendNTimes(gpa, 0, std.math.divCeil(usize, isel.dom_len, @bitSizeOf(DomInt)) catch unreachable);
594 try isel.dom.appendNTimes(gpa, 0, @divCeil(isel.dom_len, @bitSizeOf(DomInt)));
595595
596596 var cases_it = switch_br.iterateCases();
597597 while (cases_it.next()) |case| try isel.analyze(case.body);
......@@ -599,7 +599,7 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {
599599
600600 for (
601601 isel.dom.items[initial_dom_start..].ptr,
602 isel.dom.items[isel.dom_start..][0 .. std.math.divCeil(usize, initial_dom_len, @bitSizeOf(DomInt)) catch unreachable],
602 isel.dom.items[isel.dom_start..][0..@divCeil(initial_dom_len, @bitSizeOf(DomInt))],
603603 ) |*initial_dom, loop_dom| initial_dom.* |= loop_dom;
604604 isel.dom_start = initial_dom_start;
605605 isel.dom_len = initial_dom_len;
......@@ -10196,7 +10196,7 @@ pub const Value = struct {
1019610196 0 => unreachable,
1019710197 1...64 => unreachable,
1019810198 65...256 => |bits| if (offset == 0 and size == ty_size) {
10199 const parts_len = std.math.divCeil(u16, bits, 64) catch unreachable;
10199 const parts_len = @divCeil(bits, 64);
1020010200 vi.setParts(isel, @intCast(parts_len));
1020110201 for (0..parts_len) |part_index| _ = vi.addPart(isel, 8 * part_index, 8);
1020210202 },
......@@ -10240,7 +10240,7 @@ pub const Value = struct {
1024010240 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;
1024110241 const array_len = array_type.lenIncludingSentinel();
1024210242 if (array_len > Value.max_parts and
10243 (std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts)
10243 (@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts)
1024410244 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});
1024510245 const alignment = vi.alignment(isel);
1024610246 const Part = struct { offset: u64, size: u64 };
......@@ -10290,7 +10290,7 @@ pub const Value = struct {
1029010290 .anyframe_type => unreachable,
1029110291 .error_union_type => |error_union_type| {
1029210292 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;
10293 if ((std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts)
10293 if ((@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts)
1029410294 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});
1029510295 const alignment = vi.alignment(isel);
1029610296 const payload_ty: ZigType = .fromInterned(error_union_type.payload_type);
......@@ -10397,7 +10397,7 @@ pub const Value = struct {
1039710397 }
1039810398 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;
1039910399 if (loaded_struct.field_types.len > Value.max_parts and
10400 (std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts)
10400 (@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts)
1040110401 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});
1040210402 const alignment = vi.alignment(isel);
1040310403 const Part = struct { offset: u64, size: u64, signedness: ?std.lang.Signedness, is_vector: bool };
......@@ -10458,7 +10458,7 @@ pub const Value = struct {
1045810458 .tuple_type => |tuple_type| {
1045910459 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;
1046010460 if (tuple_type.types.len > Value.max_parts and
10461 (std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts)
10461 (@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts)
1046210462 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});
1046310463 const alignment = vi.alignment(isel);
1046410464 const Part = struct { offset: u64, size: u64, is_vector: bool };
......@@ -10513,7 +10513,7 @@ pub const Value = struct {
1051310513 } },
1051410514 }
1051510515 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;
10516 if ((std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts)
10516 if ((@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts)
1051710517 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});
1051810518 const union_layout = ZigType.getUnionLayout(loaded_union, zcu);
1051910519 const alignment = vi.alignment(isel);
src/codegen/llvm/FuncGen.zig+2-2
......@@ -6948,7 +6948,7 @@ const ParamTypeIterator = struct {
69486948 switch (ip.indexToKey(ty.toIntern())) {
69496949 .struct_type => {
69506950 const size = ty.abiSize(zcu);
6951 assert((std.math.divCeil(u64, size, 8) catch unreachable) == types_index);
6951 assert(@divCeil(size, 8) == types_index);
69526952 if (size % 8 > 0) {
69536953 it.types_buffer[types_index - 1] =
69546954 try it.object.builder.intType(@intCast(size % 8 * 8));
......@@ -7193,7 +7193,7 @@ fn lowerSystemVFnRetTy(o: *Object, fn_info: InternPool.Key.FuncType) Allocator.E
71937193 switch (ip.indexToKey(ret_ty.toIntern())) {
71947194 .struct_type => {
71957195 const size = ret_ty.abiSize(zcu);
7196 assert((std.math.divCeil(u64, size, 8) catch unreachable) == types_index);
7196 assert(@divCeil(size, 8) == types_index);
71977197 if (size % 8 > 0) {
71987198 types_buffer[types_index - 1] = try o.builder.intType(@intCast(size % 8 * 8));
71997199 }
src/codegen/riscv64/CodeGen.zig+1-2
......@@ -2217,8 +2217,7 @@ fn airIntCast(func: *Func, inst: Air.Inst.Index) !void {
22172217 };
22182218
22192219 const dst_mcv = if (dst_int_info.bits <= src_storage_bits and
2220 math.divCeil(u16, dst_int_info.bits, 64) catch unreachable ==
2221 math.divCeil(u32, src_storage_bits, 64) catch unreachable and
2220 @divCeil(dst_int_info.bits, 64) == @divCeil(src_storage_bits, 64) and
22222221 func.reuseOperand(inst, ty_op.operand, 0, src_mcv)) src_mcv else dst: {
22232222 const dst_mcv = try func.allocRegOrMem(dst_ty, inst, true);
22242223 try func.genCopy(min_ty, dst_mcv, src_mcv);
src/codegen/spirv/Assembler.zig+1-1
......@@ -375,7 +375,7 @@ fn processGenericInstruction(ass: *Assembler) !?AsmValue {
375375 },
376376 .string => |offset| {
377377 const text = std.mem.sliceTo(ass.inst.string_bytes.items[offset..], 0);
378 const size = std.math.divCeil(usize, text.len + 1, @sizeOf(Word)) catch unreachable;
378 const size = @divCeil(text.len + 1, @sizeOf(Word));
379379 try section.ensureUnusedCapacity(cg.gpa, size);
380380 section.writeOperand(spec.LiteralString, text);
381381 },
src/codegen/spirv/Section.zig+1-1
......@@ -232,7 +232,7 @@ fn operandSize(comptime Operand: type, operand: Operand) usize {
232232 return switch (Operand) {
233233 spec.LiteralSpecConstantOpInteger => unreachable,
234234 spec.Id, spec.LiteralInteger, spec.LiteralExtInstInteger => 1,
235 spec.LiteralString => std.math.divCeil(usize, operand.len + 1, @sizeOf(Word)) catch unreachable,
235 spec.LiteralString => @divCeil(operand.len + 1, @sizeOf(Word)),
236236 spec.LiteralContextDependentNumber => switch (operand) {
237237 .int32, .uint32, .float32 => 1,
238238 .int64, .uint64, .float64 => 2,
src/codegen/wasm/CodeGen.zig+3-3
......@@ -3678,7 +3678,7 @@ fn intWrap(cg: *CodeGen, ty: IntType, operand: WValue) InnerError!WValue {
36783678
36793679 const result = try cg.allocInt(ty);
36803680
3681 const used_len = (math.divCeil(u16, ty.bits, 64) catch unreachable) * 8;
3681 const used_len = @divCeil(ty.bits, 64) * 8;
36823682
36833683 if (ty.bits % 64 != 0) {
36843684 try cg.memcpy(result, operand, .{ .imm32 = used_len - 8 });
......@@ -3744,7 +3744,7 @@ fn intMaxValue(cg: *CodeGen, int_ty: IntType) InnerError!WValue {
37443744 } else {
37453745 const result = try cg.allocInt(int_ty);
37463746 const full_len = @divExact(cg.intBackingBits(int_ty.bits), 8);
3747 const used_len = (math.divCeil(u16, int_ty.bits, 64) catch unreachable) * 8;
3747 const used_len = @divCeil(int_ty.bits, 64) * 8;
37483748
37493749 try cg.memset(Type.u8, result, .{ .imm32 = used_len - 8 }, .{ .imm32 = 0xFF });
37503750
......@@ -3778,7 +3778,7 @@ fn intMinValue(cg: *CodeGen, int_ty: IntType) InnerError!WValue {
37783778 } else {
37793779 const result = try cg.allocInt(int_ty);
37803780 const full_len = @divExact(cg.intBackingBits(int_ty.bits), 8);
3781 const used_len = (math.divCeil(u16, int_ty.bits, 64) catch unreachable) * 8;
3781 const used_len = @divCeil(int_ty.bits, 64) * 8;
37823782
37833783 try cg.memset(Type.u8, result, .{ .imm32 = used_len - 8 }, .{ .imm32 = 0 });
37843784 try cg.store(result, .{ .imm64 = ~@as(u64, 0) << @intCast(int_ty.bits - (used_len - 8) * 8 - 1) }, Type.u64, used_len - 8);
src/codegen/x86_64/CodeGen.zig+6-6
......@@ -174786,7 +174786,7 @@ fn genShiftBinOpMir(
174786174786 try self.spillEflagsIfOccupied();
174787174787
174788174788 if (abi_size > 16) {
174789 const limbs_len = std.math.divCeil(u32, abi_size, 8) catch unreachable;
174789 const limbs_len = @divCeil(abi_size, 8);
174790174790 assert(shift_abi_size >= 1 and shift_abi_size <= 2);
174791174791
174792174792 const rcx_lock: ?RegisterLock = switch (rhs_mcv) {
......@@ -179598,7 +179598,7 @@ fn genSetReg(
179598179598 if (pack_alias != sign_alias) try cg.asmRegisterRegister(.{ ._dqa, .mov }, pack_alias, sign_alias);
179599179599 try cg.asmRegisterRegister(.{ .p_b, .ackssw }, pack_alias, pack_alias);
179600179600 }
179601 mask_size = std.math.divCeil(u32, mask_size, 2) catch unreachable;
179601 mask_size = @divCeil(mask_size, 2);
179602179602 break :pack_reg pack_reg;
179603179603 },
179604179604 };
......@@ -180162,7 +180162,7 @@ fn airBitCast(self: *CodeGen, inst: Air.Inst.Index) !void {
180162180162 const bit_size = dst_ty.bitSize(zcu);
180163180163 if (abi_size * 8 <= bit_size) break :result dst_mcv;
180164180164
180165 const dst_limbs_len = std.math.divCeil(u31, @intCast(bit_size), 64) catch unreachable;
180165 const dst_limbs_len: u31 = @intCast(@divCeil(bit_size, 64));
180166180166 const high_mcv: MCValue = switch (dst_mcv) {
180167180167 .register => |dst_reg| .{ .register = dst_reg },
180168180168 .register_pair => |dst_regs| .{ .register = dst_regs[1] },
......@@ -183555,7 +183555,7 @@ const Temp = struct {
183555183555 const part_ty: Type = if (src_regs.len == 1)
183556183556 src_ty
183557183557 else if (cg.intInfo(src_ty)) |int_info| part_ty: {
183558 assert(src_regs.len == std.math.divCeil(u16, int_info.bits, 64) catch unreachable);
183558 assert(src_regs.len == @divCeil(int_info.bits, 64));
183559183559 break :part_ty .u64;
183560183560 } else part_ty: switch (ip.indexToKey(src_ty.toIntern())) {
183561183561 else => std.debug.panic("{s}: {f}\n", .{ @src().fn_name, src_ty.fmt(cg.pt) }),
......@@ -183565,7 +183565,7 @@ const Temp = struct {
183565183565 break :part_ty .usize;
183566183566 },
183567183567 .array_type => {
183568 assert(src_regs.len - part_index == std.math.divCeil(u32, src_size, 8) catch unreachable);
183568 assert(src_regs.len - part_index == @divCeil(src_size, 8));
183569183569 break :part_ty try cg.pt.intType(.unsigned, @as(u16, 8) * @min(src_size, 8));
183570183570 },
183571183571 .vector_type => |vector_type| switch (@divExact(vector_type.len, src_regs.len)) {
......@@ -183585,7 +183585,7 @@ const Temp = struct {
183585183585 },
183586183586 },
183587183587 .struct_type, .union_type => {
183588 assert(src_regs.len - part_index == std.math.divCeil(u32, src_size, 8) catch unreachable);
183588 assert(src_regs.len - part_index == @divCeil(src_size, 8));
183589183589 break :part_ty switch (src_size) {
183590183590 0, 3, 5...7 => unreachable,
183591183591 1 => .u8,
src/codegen/x86_64/Emit.zig+1-1
......@@ -772,7 +772,7 @@ fn encodeInst(emit: *Emit, lowered_inst: Instruction, reloc_info: []const RelocI
772772 const enc_length: u4 = if (is_mem) switch (lowered_inst.ops[op_index].mem.sib.base) {
773773 .rip_inst => 4,
774774 else => unreachable,
775 } else @intCast(std.math.divCeil(u7, @intCast(op.immBitSize()), 8) catch unreachable);
775 } else @intCast(@divCeil(op.immBitSize(), 8));
776776 reloc_offset -= enc_length;
777777 if (op_index == reloc.op_index) break :reloc_offset_length .{ reloc_offset, enc_length };
778778 assert(!is_mem);
src/link/Dwarf.zig+3-3
......@@ -2137,7 +2137,7 @@ pub const WipNav = struct {
21372137 .signed => DW.FORM.sdata,
21382138 .unsigned => DW.FORM.udata,
21392139 }));
2140 try wip_nav.debug_info.ensureUnusedCapacity(std.math.divCeil(usize, bits, 7) catch unreachable);
2140 try wip_nav.debug_info.ensureUnusedCapacity(@divCeil(bits, 7));
21412141 var bit: usize = 0;
21422142 var carry: u1 = 1;
21432143 while (bit < bits) {
......@@ -2158,7 +2158,7 @@ pub const WipNav = struct {
21582158 }
21592159 } else {
21602160 try diw.writeUleb128(DW.FORM.block);
2161 const bytes = @max(ty.abiSize(zcu), std.math.divCeil(usize, bits, 8) catch unreachable);
2161 const bytes = @max(ty.abiSize(zcu), @divCeil(bits, 8));
21622162 try diw.writeUleb128(bytes);
21632163 try wip_nav.debug_info.ensureUnusedCapacity(@intCast(bytes));
21642164 big_int.writeTwosComplement(
......@@ -4275,7 +4275,7 @@ fn updateConstInner(dwarf: *Dwarf, pt: Zcu.PerThread, debug_const_index: link.Co
42754275 try wip_nav.abbrevCode(.aggregate_undefined_comptime_value);
42764276 try wip_nav.refType(.fromInterned(error_union.ty));
42774277 var err_buf: [4]u8 = undefined;
4278 const err_bytes = err_buf[0 .. std.math.divCeil(u17, zcu.errorSetBits(), 8) catch unreachable];
4278 const err_bytes = err_buf[0..@divCeil(zcu.errorSetBits(), 8)];
42794279 dwarf.writeInt(err_bytes, switch (error_union.val) {
42804280 .err_name => |err_name| try pt.getErrorValue(err_name),
42814281 .payload => 0,