authorgravatar for paul.verigo@gmail.comPavel Verigo <paul.verigo@gmail.com> 2026-07-06 12:19:58+02:00
committergravatar for paul.verigo@gmail.comPavel Verigo <paul.verigo@gmail.com> 2026-07-06 20:49:08+02:00
log73f6d498fc83763054f62677f3a67871d3825136
treec69510bf6967ac6316d77e10700f453f741941c7
parentca72c56e0c93e8ebe4ab7533a8c1ae65c3767b95

compiler: use @divCeil

15 files changed, 50 insertions(+), 51 deletions(-)

src/Air.zig+3-3
...@@ -1517,7 +1517,7 @@ pub const ShuffleTwoMask = enum(u32) {...@@ -1517,7 +1517,7 @@ pub const ShuffleTwoMask = enum(u32) {
1517/// Trailing:1517/// Trailing:
1518/// 0. `Inst.Ref` for every outputs_len1518/// 0. `Inst.Ref` for every outputs_len
1519/// 1. `Inst.Ref` for every inputs_len1519/// 1. `Inst.Ref` for every inputs_len
1520/// 2. A number of u32 elements follow according to the equation `(source_len + 3) / 4`.1520/// 2. A number of u32 elements follow according to the equation `@divCeil(source_len, 4)`.
1521/// Memory starting at this position is reinterpreted as the source bytes.1521/// Memory starting at this position is reinterpreted as the source bytes.
1522/// 3. for every outputs_len1522/// 3. for every outputs_len
1523/// - constraint: memory at this position is reinterpreted as a null1523/// - constraint: memory at this position is reinterpreted as a null
...@@ -2225,7 +2225,7 @@ pub fn unwrapSwitch(air: *const Air, switch_inst: Inst.Index) UnwrappedSwitch {...@@ -2225,7 +2225,7 @@ pub fn unwrapSwitch(air: *const Air, switch_inst: Inst.Index) UnwrappedSwitch {
2225 }2225 }
2226 const pl_op = inst.data.pl_op;2226 const pl_op = inst.data.pl_op;
2227 const extra = air.extraData(SwitchBr, pl_op.payload);2227 const extra = air.extraData(SwitchBr, pl_op.payload);
2228 const hint_bag_count = std.math.divCeil(usize, extra.data.cases_len + 1, 10) catch unreachable;2228 const hint_bag_count = @divCeil(extra.data.cases_len + 1, 10);
2229 return .{2229 return .{
2230 .air = air,2230 .air = air,
2231 .operand = pl_op.operand,2231 .operand = pl_op.operand,
...@@ -2394,7 +2394,7 @@ pub const UnwrappedAsm = struct {...@@ -2394,7 +2394,7 @@ pub const UnwrappedAsm = struct {
2394 const name = std.mem.sliceTo(constraint_name[constraint.len + 1 ..], 0);2394 const name = std.mem.sliceTo(constraint_name[constraint.len + 1 ..], 0);
2395 // This equation accounts for the fact that even if we have exactly 4 bytes2395 // This equation accounts for the fact that even if we have exactly 4 bytes
2396 // for the string, we still use the next u32 for the null terminator.2396 // for the string, we still use the next u32 for the null terminator.
2397 const next_offset = std.math.divCeil(usize, constraint.len + 1 + name.len + 1, @sizeOf(u32)) catch unreachable;2397 const next_offset = @divCeil(constraint.len + 1 + name.len + 1, @sizeOf(u32));
2398 self.constraint_names = self.constraint_names[next_offset..];2398 self.constraint_names = self.constraint_names[next_offset..];
23992399
2400 return .{2400 return .{
src/Air/Legalize.zig+1-1
...@@ -746,7 +746,7 @@ fn legalizeBody(l: *Legalize, body_start: usize, body_len: usize) Error!void {...@@ -746,7 +746,7 @@ fn legalizeBody(l: *Legalize, body_start: usize, body_len: usize) Error!void {
746 .switch_br, .loop_switch_br => {746 .switch_br, .loop_switch_br => {
747 const pl_op = l.air_instructions.items(.data)[@intFromEnum(inst)].pl_op;747 const pl_op = l.air_instructions.items(.data)[@intFromEnum(inst)].pl_op;
748 const extra = l.extraData(Air.SwitchBr, pl_op.payload);748 const extra = l.extraData(Air.SwitchBr, pl_op.payload);
749 const hint_bag_count = std.math.divCeil(usize, extra.data.cases_len + 1, 10) catch unreachable;749 const hint_bag_count = @divCeil(extra.data.cases_len + 1, 10);
750 var extra_index = extra.end + hint_bag_count;750 var extra_index = extra.end + hint_bag_count;
751 for (0..extra.data.cases_len) |_| {751 for (0..extra.data.cases_len) |_| {
752 const case_extra = l.extraData(Air.SwitchBr.Case, extra_index);752 const case_extra = l.extraData(Air.SwitchBr.Case, extra_index);
src/InternPool.zig+3-3
...@@ -3581,11 +3581,11 @@ pub fn loadStructType(ip: *const InternPool, index: Index) LoadedStructType {...@@ -3581,11 +3581,11 @@ pub fn loadStructType(ip: *const InternPool, index: Index) LoadedStructType {
3581 .start = extra_index,3581 .start = extra_index,
3582 .len = extra.data.fields_len,3582 .len = extra.data.fields_len,
3583 } else .empty;3583 } else .empty;
3584 extra_index += std.math.divCeil(u32, field_aligns.len, 4) catch unreachable;3584 extra_index += @divCeil(field_aligns.len, 4);
3585 const field_is_comptime_bits: LoadedStructType.ComptimeBits = if (extra.data.flags.any_comptime_fields) .{3585 const field_is_comptime_bits: LoadedStructType.ComptimeBits = if (extra.data.flags.any_comptime_fields) .{
3586 .tid = unwrapped_index.tid,3586 .tid = unwrapped_index.tid,
3587 .start = extra_index,3587 .start = extra_index,
3588 .len = std.math.divCeil(u32, extra.data.fields_len, 32) catch unreachable,3588 .len = @divCeil(extra.data.fields_len, 32),
3589 } else .empty;3589 } else .empty;
3590 extra_index += field_is_comptime_bits.len;3590 extra_index += field_is_comptime_bits.len;
3591 const field_runtime_order: LoadedStructType.RuntimeOrder.Slice = if (extra.data.flags.layout == .auto) .{3591 const field_runtime_order: LoadedStructType.RuntimeOrder.Slice = if (extra.data.flags.layout == .auto) .{
...@@ -3737,7 +3737,7 @@ pub fn loadUnionType(ip: *const InternPool, index: Index) LoadedUnionType {...@@ -3737,7 +3737,7 @@ pub fn loadUnionType(ip: *const InternPool, index: Index) LoadedUnionType {
3737 .start = extra_index,3737 .start = extra_index,
3738 .len = extra.data.fields_len,3738 .len = extra.data.fields_len,
3739 } else .empty;3739 } else .empty;
3740 extra_index += std.math.divCeil(u32, field_aligns.len, 4) catch unreachable;3740 extra_index += @divCeil(field_aligns.len, 4);
37413741
3742 return .{3742 return .{
3743 .zir_index = extra.data.zir_index,3743 .zir_index = extra.data.zir_index,
src/Sema.zig+5-5
...@@ -10305,7 +10305,7 @@ fn finishSwitchBr(...@@ -10305,7 +10305,7 @@ fn finishSwitchBr(
10305 fn ensureUnusedCapacity(hints: *@This(), gpa_inner: Allocator, additional_count: u32) Allocator.Error!void {10305 fn ensureUnusedCapacity(hints: *@This(), gpa_inner: Allocator, additional_count: u32) Allocator.Error!void {
10306 const unused_hints = hints.bags.capacity * hints_per_bag - hints.count;10306 const unused_hints = hints.bags.capacity * hints_per_bag - hints.count;
10307 if (unused_hints >= additional_count) return;10307 if (unused_hints >= additional_count) return;
10308 const bags_required = std.math.divCeil(u32, hints.count + additional_count, hints_per_bag) catch unreachable;10308 const bags_required = @divCeil(hints.count + additional_count, hints_per_bag);
10309 return hints.bags.ensureUnusedCapacity(gpa_inner, bags_required);10309 return hints.bags.ensureUnusedCapacity(gpa_inner, bags_required);
10310 }10310 }
10311 fn appendAssumeCapacity(hints: *@This(), hint: std.lang.BranchHint) void {10311 fn appendAssumeCapacity(hints: *@This(), hint: std.lang.BranchHint) void {
...@@ -10321,7 +10321,7 @@ fn finishSwitchBr(...@@ -10321,7 +10321,7 @@ fn finishSwitchBr(
10321 }10321 }
10322 };10322 };
10323 var branch_hints: BranchHints = hints: {10323 var branch_hints: BranchHints = hints: {
10324 const num_bags = std.math.divCeil(u32, estimated_cases_len, BranchHints.hints_per_bag) catch unreachable;10324 const num_bags = @divCeil(estimated_cases_len, BranchHints.hints_per_bag);
10325 break :hints .{ .bags = try .initCapacity(gpa, num_bags), .count = 0 };10325 break :hints .{ .bags = try .initCapacity(gpa, num_bags), .count = 0 };
10326 };10326 };
10327 defer branch_hints.bags.deinit(gpa);10327 defer branch_hints.bags.deinit(gpa);
...@@ -12212,7 +12212,7 @@ fn analyzeSwitchPayloadCaptureTaggedUnion(...@@ -12212,7 +12212,7 @@ fn analyzeSwitchPayloadCaptureTaggedUnion(
12212 {12212 {
12213 // All branch hints are `.none`, so just add zero elems.12213 // All branch hints are `.none`, so just add zero elems.
12214 comptime assert(@intFromEnum(std.lang.BranchHint.none) == 0);12214 comptime assert(@intFromEnum(std.lang.BranchHint.none) == 0);
12215 const need_elems = std.math.divCeil(usize, field_indices.len + 1, 10) catch unreachable;12215 const need_elems = @divCeil(field_indices.len + 1, 10);
12216 try cases_extra.appendNTimes(gpa, 0, need_elems);12216 try cases_extra.appendNTimes(gpa, 0, need_elems);
12217 }12217 }
1221812218
...@@ -18698,7 +18698,7 @@ fn finishStructInit(...@@ -18698,7 +18698,7 @@ fn finishStructInit(
18698 return sema.addConstantMaybeRef(sema.resolveValue(final_val_ref).?, is_ref);18698 return sema.addConstantMaybeRef(sema.resolveValue(final_val_ref).?, is_ref);
18699 },18699 },
18700 .@"packed" => {18700 .@"packed" => {
18701 const buf = try sema.arena.alloc(u8, @intCast((struct_ty.bitSize(zcu) + 7) / 8));18701 const buf = try sema.arena.alloc(u8, @intCast(@divCeil(struct_ty.bitSize(zcu), 8)));
18702 @memset(buf, 0);18702 @memset(buf, 0);
18703 var bit_offset: u16 = 0;18703 var bit_offset: u16 = 0;
18704 for (field_inits) |field_init| {18704 for (field_inits) |field_init| {
...@@ -29745,7 +29745,7 @@ pub fn bitCastVal(...@@ -29745,7 +29745,7 @@ pub fn bitCastVal(
29745 if (val.isUndef(zcu)) {29745 if (val.isUndef(zcu)) {
29746 return pt.undefValue(dest_ty);29746 return pt.undefValue(dest_ty);
29747 } else {29747 } else {
29748 const buf = try sema.arena.alloc(u8, @intCast((bit_size + 7) / 8));29748 const buf = try sema.arena.alloc(u8, @intCast(@divCeil(bit_size, 8)));
29749 @memset(buf, 0);29749 @memset(buf, 0);
29750 val.writeToPackedMemory(zcu, buf, 0);29750 val.writeToPackedMemory(zcu, buf, 0);
29751 return .readFromPackedMemory(dest_ty, pt, buf, 0);29751 return .readFromPackedMemory(dest_ty, pt, buf, 0);
src/Sema/arith.zig+7-7
...@@ -2193,12 +2193,12 @@ fn floatDivCeil(sema: *Sema, lhs: Value, rhs: Value, ty: Type) !Value {...@@ -2193,12 +2193,12 @@ fn floatDivCeil(sema: *Sema, lhs: Value, rhs: Value, ty: Type) !Value {
2193 const pt = sema.pt;2193 const pt = sema.pt;
2194 const zcu = pt.zcu;2194 const zcu = pt.zcu;
2195 const target = zcu.getTarget();2195 const target = zcu.getTarget();
2196 const storage: InternPool.Key.Float.Storage = switch (ty.floatBits(target)) { // TODO2196 const storage: InternPool.Key.Float.Storage = switch (ty.floatBits(target)) {
2197 16 => .{ .f16 = @ceil(lhs.toFloat(f16, zcu) / rhs.toFloat(f16, zcu)) },2197 16 => .{ .f16 = @divCeil(lhs.toFloat(f16, zcu), rhs.toFloat(f16, zcu)) },
2198 32 => .{ .f32 = @ceil(lhs.toFloat(f32, zcu) / rhs.toFloat(f32, zcu)) },2198 32 => .{ .f32 = @divCeil(lhs.toFloat(f32, zcu), rhs.toFloat(f32, zcu)) },
2199 64 => .{ .f64 = @ceil(lhs.toFloat(f64, zcu) / rhs.toFloat(f64, zcu)) },2199 64 => .{ .f64 = @divCeil(lhs.toFloat(f64, zcu), rhs.toFloat(f64, zcu)) },
2200 80 => .{ .f80 = @ceil(lhs.toFloat(f80, zcu) / rhs.toFloat(f80, zcu)) },2200 80 => .{ .f80 = @divCeil(lhs.toFloat(f80, zcu), rhs.toFloat(f80, zcu)) },
2201 128 => .{ .f128 = @ceil(lhs.toFloat(f128, zcu) / rhs.toFloat(f128, zcu)) },2201 128 => .{ .f128 = @divCeil(lhs.toFloat(f128, zcu), rhs.toFloat(f128, zcu)) },
2202 else => unreachable,2202 else => unreachable,
2203 };2203 };
2204 return .fromInterned(try pt.intern(.{ .float = .{2204 return .fromInterned(try pt.intern(.{ .float = .{
...@@ -2304,7 +2304,7 @@ fn intValueAa(sema: *Sema, ty: Type) !Value {...@@ -2304,7 +2304,7 @@ fn intValueAa(sema: *Sema, ty: Type) !Value {
2304 if (ty.toIntern() == .u0_type) return pt.intValue(ty, 0);2304 if (ty.toIntern() == .u0_type) return pt.intValue(ty, 0);
2305 const info = ty.intInfo(zcu);2305 const info = ty.intInfo(zcu);
23062306
2307 const buf = try sema.arena.alloc(u8, (info.bits + 7) / 8);2307 const buf = try sema.arena.alloc(u8, @divCeil(info.bits, 8));
2308 @memset(buf, 0xAA);2308 @memset(buf, 0xAA);
23092309
2310 const limbs = try sema.arena.alloc(2310 const limbs = try sema.arena.alloc(
src/Type.zig+3-3
...@@ -968,7 +968,7 @@ pub fn abiAlignment(ty: Type, zcu: *const Zcu) Alignment {...@@ -968,7 +968,7 @@ pub fn abiAlignment(ty: Type, zcu: *const Zcu) Alignment {
968 if (vector_type.len > 256 and target.cpu.has(.x86, .avx512f)) return .@"64";968 if (vector_type.len > 256 and target.cpu.has(.x86, .avx512f)) return .@"64";
969 if (vector_type.len > 128 and target.cpu.has(.x86, .avx)) return .@"32";969 if (vector_type.len > 128 and target.cpu.has(.x86, .avx)) return .@"32";
970 if (vector_type.len > 64) return .@"16";970 if (vector_type.len > 64) return .@"16";
971 const bytes = std.math.divCeil(u32, vector_type.len, 8) catch unreachable;971 const bytes = @divCeil(vector_type.len, 8);
972 return .fromByteUnits(std.math.ceilPowerOfTwoAssert(u32, bytes));972 return .fromByteUnits(std.math.ceilPowerOfTwoAssert(u32, bytes));
973 }973 }
974 const elem_bytes: u32 = @intCast(Type.fromInterned(vector_type.child).abiSize(zcu));974 const elem_bytes: u32 = @intCast(Type.fromInterned(vector_type.child).abiSize(zcu));
...@@ -1111,10 +1111,10 @@ pub fn abiSize(ty: Type, zcu: *const Zcu) u64 {...@@ -1111,10 +1111,10 @@ pub fn abiSize(ty: Type, zcu: *const Zcu) u64 {
1111 .vector_type => |vec| {1111 .vector_type => |vec| {
1112 const elem_ty: Type = .fromInterned(vec.child);1112 const elem_ty: Type = .fromInterned(vec.child);
1113 const bytes = switch (zcu.comp.getZigBackend()) {1113 const bytes = switch (zcu.comp.getZigBackend()) {
1114 else => std.math.divCeil(u64, vec.len * elem_ty.bitSize(zcu), 8) catch unreachable,1114 else => @divCeil(vec.len * elem_ty.bitSize(zcu), 8),
1115 .stage2_c, .stage2_wasm => vec.len * elem_ty.abiSize(zcu),1115 .stage2_c, .stage2_wasm => vec.len * elem_ty.abiSize(zcu),
1116 .stage2_x86_64 => switch (elem_ty.toIntern()) {1116 .stage2_x86_64 => switch (elem_ty.toIntern()) {
1117 .bool_type => std.math.divCeil(u64, vec.len, 8) catch unreachable,1117 .bool_type => @divCeil(vec.len, 8),
1118 else => vec.len * elem_ty.abiSize(zcu),1118 else => vec.len * elem_ty.abiSize(zcu),
1119 },1119 },
1120 };1120 };
src/codegen/aarch64/Select.zig+10-10
...@@ -405,11 +405,11 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {...@@ -405,11 +405,11 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {
405 .live_registers = undefined,405 .live_registers = undefined,
406 .repeat_list = undefined,406 .repeat_list = undefined,
407 });407 });
408 try isel.dom.appendNTimes(gpa, 0, std.math.divCeil(usize, isel.dom_len, @bitSizeOf(DomInt)) catch unreachable);408 try isel.dom.appendNTimes(gpa, 0, @divCeil(isel.dom_len, @bitSizeOf(DomInt)));
409 try isel.analyze(air_body_block.body);409 try isel.analyze(air_body_block.body);
410 for (410 for (
411 isel.dom.items[initial_dom_start..].ptr,411 isel.dom.items[initial_dom_start..].ptr,
412 isel.dom.items[isel.dom_start..][0 .. std.math.divCeil(usize, initial_dom_len, @bitSizeOf(DomInt)) catch unreachable],412 isel.dom.items[isel.dom_start..][0..@divCeil(initial_dom_len, @bitSizeOf(DomInt))],
413 ) |*initial_dom, loop_dom| initial_dom.* |= loop_dom;413 ) |*initial_dom, loop_dom| initial_dom.* |= loop_dom;
414 isel.dom_start = initial_dom_start;414 isel.dom_start = initial_dom_start;
415 isel.dom_len = initial_dom_len;415 isel.dom_len = initial_dom_len;
...@@ -591,7 +591,7 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {...@@ -591,7 +591,7 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {
591 .live_registers = undefined,591 .live_registers = undefined,
592 .repeat_list = undefined,592 .repeat_list = undefined,
593 });593 });
594 try isel.dom.appendNTimes(gpa, 0, std.math.divCeil(usize, isel.dom_len, @bitSizeOf(DomInt)) catch unreachable);594 try isel.dom.appendNTimes(gpa, 0, @divCeil(isel.dom_len, @bitSizeOf(DomInt)));
595595
596 var cases_it = switch_br.iterateCases();596 var cases_it = switch_br.iterateCases();
597 while (cases_it.next()) |case| try isel.analyze(case.body);597 while (cases_it.next()) |case| try isel.analyze(case.body);
...@@ -599,7 +599,7 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {...@@ -599,7 +599,7 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {
599599
600 for (600 for (
601 isel.dom.items[initial_dom_start..].ptr,601 isel.dom.items[initial_dom_start..].ptr,
602 isel.dom.items[isel.dom_start..][0 .. std.math.divCeil(usize, initial_dom_len, @bitSizeOf(DomInt)) catch unreachable],602 isel.dom.items[isel.dom_start..][0..@divCeil(initial_dom_len, @bitSizeOf(DomInt))],
603 ) |*initial_dom, loop_dom| initial_dom.* |= loop_dom;603 ) |*initial_dom, loop_dom| initial_dom.* |= loop_dom;
604 isel.dom_start = initial_dom_start;604 isel.dom_start = initial_dom_start;
605 isel.dom_len = initial_dom_len;605 isel.dom_len = initial_dom_len;
...@@ -10196,7 +10196,7 @@ pub const Value = struct {...@@ -10196,7 +10196,7 @@ pub const Value = struct {
10196 0 => unreachable,10196 0 => unreachable,
10197 1...64 => unreachable,10197 1...64 => unreachable,
10198 65...256 => |bits| if (offset == 0 and size == ty_size) {10198 65...256 => |bits| if (offset == 0 and size == ty_size) {
10199 const parts_len = std.math.divCeil(u16, bits, 64) catch unreachable;10199 const parts_len = @divCeil(bits, 64);
10200 vi.setParts(isel, @intCast(parts_len));10200 vi.setParts(isel, @intCast(parts_len));
10201 for (0..parts_len) |part_index| _ = vi.addPart(isel, 8 * part_index, 8);10201 for (0..parts_len) |part_index| _ = vi.addPart(isel, 8 * part_index, 8);
10202 },10202 },
...@@ -10240,7 +10240,7 @@ pub const Value = struct {...@@ -10240,7 +10240,7 @@ pub const Value = struct {
10240 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;10240 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;
10241 const array_len = array_type.lenIncludingSentinel();10241 const array_len = array_type.lenIncludingSentinel();
10242 if (array_len > Value.max_parts and10242 if (array_len > Value.max_parts and
10243 (std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts)10243 (@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts)
10244 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});10244 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});
10245 const alignment = vi.alignment(isel);10245 const alignment = vi.alignment(isel);
10246 const Part = struct { offset: u64, size: u64 };10246 const Part = struct { offset: u64, size: u64 };
...@@ -10290,7 +10290,7 @@ pub const Value = struct {...@@ -10290,7 +10290,7 @@ pub const Value = struct {
10290 .anyframe_type => unreachable,10290 .anyframe_type => unreachable,
10291 .error_union_type => |error_union_type| {10291 .error_union_type => |error_union_type| {
10292 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;10292 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;
10293 if ((std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts)10293 if ((@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts)
10294 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});10294 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});
10295 const alignment = vi.alignment(isel);10295 const alignment = vi.alignment(isel);
10296 const payload_ty: ZigType = .fromInterned(error_union_type.payload_type);10296 const payload_ty: ZigType = .fromInterned(error_union_type.payload_type);
...@@ -10397,7 +10397,7 @@ pub const Value = struct {...@@ -10397,7 +10397,7 @@ pub const Value = struct {
10397 }10397 }
10398 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;10398 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;
10399 if (loaded_struct.field_types.len > Value.max_parts and10399 if (loaded_struct.field_types.len > Value.max_parts and
10400 (std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts)10400 (@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts)
10401 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});10401 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});
10402 const alignment = vi.alignment(isel);10402 const alignment = vi.alignment(isel);
10403 const Part = struct { offset: u64, size: u64, signedness: ?std.lang.Signedness, is_vector: bool };10403 const Part = struct { offset: u64, size: u64, signedness: ?std.lang.Signedness, is_vector: bool };
...@@ -10458,7 +10458,7 @@ pub const Value = struct {...@@ -10458,7 +10458,7 @@ pub const Value = struct {
10458 .tuple_type => |tuple_type| {10458 .tuple_type => |tuple_type| {
10459 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;10459 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;
10460 if (tuple_type.types.len > Value.max_parts and10460 if (tuple_type.types.len > Value.max_parts and
10461 (std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts)10461 (@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts)
10462 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});10462 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});
10463 const alignment = vi.alignment(isel);10463 const alignment = vi.alignment(isel);
10464 const Part = struct { offset: u64, size: u64, is_vector: bool };10464 const Part = struct { offset: u64, size: u64, is_vector: bool };
...@@ -10513,7 +10513,7 @@ pub const Value = struct {...@@ -10513,7 +10513,7 @@ pub const Value = struct {
10513 } },10513 } },
10514 }10514 }
10515 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;10515 const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0;
10516 if ((std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts)10516 if ((@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts)
10517 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});10517 return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)});
10518 const union_layout = ZigType.getUnionLayout(loaded_union, zcu);10518 const union_layout = ZigType.getUnionLayout(loaded_union, zcu);
10519 const alignment = vi.alignment(isel);10519 const alignment = vi.alignment(isel);
src/codegen/llvm/FuncGen.zig+2-2
...@@ -6948,7 +6948,7 @@ const ParamTypeIterator = struct {...@@ -6948,7 +6948,7 @@ const ParamTypeIterator = struct {
6948 switch (ip.indexToKey(ty.toIntern())) {6948 switch (ip.indexToKey(ty.toIntern())) {
6949 .struct_type => {6949 .struct_type => {
6950 const size = ty.abiSize(zcu);6950 const size = ty.abiSize(zcu);
6951 assert((std.math.divCeil(u64, size, 8) catch unreachable) == types_index);6951 assert(@divCeil(size, 8) == types_index);
6952 if (size % 8 > 0) {6952 if (size % 8 > 0) {
6953 it.types_buffer[types_index - 1] =6953 it.types_buffer[types_index - 1] =
6954 try it.object.builder.intType(@intCast(size % 8 * 8));6954 try it.object.builder.intType(@intCast(size % 8 * 8));
...@@ -7193,7 +7193,7 @@ fn lowerSystemVFnRetTy(o: *Object, fn_info: InternPool.Key.FuncType) Allocator.E...@@ -7193,7 +7193,7 @@ fn lowerSystemVFnRetTy(o: *Object, fn_info: InternPool.Key.FuncType) Allocator.E
7193 switch (ip.indexToKey(ret_ty.toIntern())) {7193 switch (ip.indexToKey(ret_ty.toIntern())) {
7194 .struct_type => {7194 .struct_type => {
7195 const size = ret_ty.abiSize(zcu);7195 const size = ret_ty.abiSize(zcu);
7196 assert((std.math.divCeil(u64, size, 8) catch unreachable) == types_index);7196 assert(@divCeil(size, 8) == types_index);
7197 if (size % 8 > 0) {7197 if (size % 8 > 0) {
7198 types_buffer[types_index - 1] = try o.builder.intType(@intCast(size % 8 * 8));7198 types_buffer[types_index - 1] = try o.builder.intType(@intCast(size % 8 * 8));
7199 }7199 }
src/codegen/riscv64/CodeGen.zig+1-2
...@@ -2217,8 +2217,7 @@ fn airIntCast(func: *Func, inst: Air.Inst.Index) !void {...@@ -2217,8 +2217,7 @@ fn airIntCast(func: *Func, inst: Air.Inst.Index) !void {
2217 };2217 };
22182218
2219 const dst_mcv = if (dst_int_info.bits <= src_storage_bits and2219 const dst_mcv = if (dst_int_info.bits <= src_storage_bits and
2220 math.divCeil(u16, dst_int_info.bits, 64) catch unreachable ==2220 @divCeil(dst_int_info.bits, 64) == @divCeil(src_storage_bits, 64) and
2221 math.divCeil(u32, src_storage_bits, 64) catch unreachable and
2222 func.reuseOperand(inst, ty_op.operand, 0, src_mcv)) src_mcv else dst: {2221 func.reuseOperand(inst, ty_op.operand, 0, src_mcv)) src_mcv else dst: {
2223 const dst_mcv = try func.allocRegOrMem(dst_ty, inst, true);2222 const dst_mcv = try func.allocRegOrMem(dst_ty, inst, true);
2224 try func.genCopy(min_ty, dst_mcv, src_mcv);2223 try func.genCopy(min_ty, dst_mcv, src_mcv);
src/codegen/spirv/Assembler.zig+1-1
...@@ -375,7 +375,7 @@ fn processGenericInstruction(ass: *Assembler) !?AsmValue {...@@ -375,7 +375,7 @@ fn processGenericInstruction(ass: *Assembler) !?AsmValue {
375 },375 },
376 .string => |offset| {376 .string => |offset| {
377 const text = std.mem.sliceTo(ass.inst.string_bytes.items[offset..], 0);377 const text = std.mem.sliceTo(ass.inst.string_bytes.items[offset..], 0);
378 const size = std.math.divCeil(usize, text.len + 1, @sizeOf(Word)) catch unreachable;378 const size = @divCeil(text.len + 1, @sizeOf(Word));
379 try section.ensureUnusedCapacity(cg.gpa, size);379 try section.ensureUnusedCapacity(cg.gpa, size);
380 section.writeOperand(spec.LiteralString, text);380 section.writeOperand(spec.LiteralString, text);
381 },381 },
src/codegen/spirv/Section.zig+1-1
...@@ -232,7 +232,7 @@ fn operandSize(comptime Operand: type, operand: Operand) usize {...@@ -232,7 +232,7 @@ fn operandSize(comptime Operand: type, operand: Operand) usize {
232 return switch (Operand) {232 return switch (Operand) {
233 spec.LiteralSpecConstantOpInteger => unreachable,233 spec.LiteralSpecConstantOpInteger => unreachable,
234 spec.Id, spec.LiteralInteger, spec.LiteralExtInstInteger => 1,234 spec.Id, spec.LiteralInteger, spec.LiteralExtInstInteger => 1,
235 spec.LiteralString => std.math.divCeil(usize, operand.len + 1, @sizeOf(Word)) catch unreachable,235 spec.LiteralString => @divCeil(operand.len + 1, @sizeOf(Word)),
236 spec.LiteralContextDependentNumber => switch (operand) {236 spec.LiteralContextDependentNumber => switch (operand) {
237 .int32, .uint32, .float32 => 1,237 .int32, .uint32, .float32 => 1,
238 .int64, .uint64, .float64 => 2,238 .int64, .uint64, .float64 => 2,
src/codegen/wasm/CodeGen.zig+3-3
...@@ -3678,7 +3678,7 @@ fn intWrap(cg: *CodeGen, ty: IntType, operand: WValue) InnerError!WValue {...@@ -3678,7 +3678,7 @@ fn intWrap(cg: *CodeGen, ty: IntType, operand: WValue) InnerError!WValue {
36783678
3679 const result = try cg.allocInt(ty);3679 const result = try cg.allocInt(ty);
36803680
3681 const used_len = (math.divCeil(u16, ty.bits, 64) catch unreachable) * 8;3681 const used_len = @divCeil(ty.bits, 64) * 8;
36823682
3683 if (ty.bits % 64 != 0) {3683 if (ty.bits % 64 != 0) {
3684 try cg.memcpy(result, operand, .{ .imm32 = used_len - 8 });3684 try cg.memcpy(result, operand, .{ .imm32 = used_len - 8 });
...@@ -3744,7 +3744,7 @@ fn intMaxValue(cg: *CodeGen, int_ty: IntType) InnerError!WValue {...@@ -3744,7 +3744,7 @@ fn intMaxValue(cg: *CodeGen, int_ty: IntType) InnerError!WValue {
3744 } else {3744 } else {
3745 const result = try cg.allocInt(int_ty);3745 const result = try cg.allocInt(int_ty);
3746 const full_len = @divExact(cg.intBackingBits(int_ty.bits), 8);3746 const full_len = @divExact(cg.intBackingBits(int_ty.bits), 8);
3747 const used_len = (math.divCeil(u16, int_ty.bits, 64) catch unreachable) * 8;3747 const used_len = @divCeil(int_ty.bits, 64) * 8;
37483748
3749 try cg.memset(Type.u8, result, .{ .imm32 = used_len - 8 }, .{ .imm32 = 0xFF });3749 try cg.memset(Type.u8, result, .{ .imm32 = used_len - 8 }, .{ .imm32 = 0xFF });
37503750
...@@ -3778,7 +3778,7 @@ fn intMinValue(cg: *CodeGen, int_ty: IntType) InnerError!WValue {...@@ -3778,7 +3778,7 @@ fn intMinValue(cg: *CodeGen, int_ty: IntType) InnerError!WValue {
3778 } else {3778 } else {
3779 const result = try cg.allocInt(int_ty);3779 const result = try cg.allocInt(int_ty);
3780 const full_len = @divExact(cg.intBackingBits(int_ty.bits), 8);3780 const full_len = @divExact(cg.intBackingBits(int_ty.bits), 8);
3781 const used_len = (math.divCeil(u16, int_ty.bits, 64) catch unreachable) * 8;3781 const used_len = @divCeil(int_ty.bits, 64) * 8;
37823782
3783 try cg.memset(Type.u8, result, .{ .imm32 = used_len - 8 }, .{ .imm32 = 0 });3783 try cg.memset(Type.u8, result, .{ .imm32 = used_len - 8 }, .{ .imm32 = 0 });
3784 try cg.store(result, .{ .imm64 = ~@as(u64, 0) << @intCast(int_ty.bits - (used_len - 8) * 8 - 1) }, Type.u64, used_len - 8);3784 try cg.store(result, .{ .imm64 = ~@as(u64, 0) << @intCast(int_ty.bits - (used_len - 8) * 8 - 1) }, Type.u64, used_len - 8);
src/codegen/x86_64/CodeGen.zig+6-6
...@@ -174786,7 +174786,7 @@ fn genShiftBinOpMir(...@@ -174786,7 +174786,7 @@ fn genShiftBinOpMir(
174786 try self.spillEflagsIfOccupied();174786 try self.spillEflagsIfOccupied();
174787174787
174788 if (abi_size > 16) {174788 if (abi_size > 16) {
174789 const limbs_len = std.math.divCeil(u32, abi_size, 8) catch unreachable;174789 const limbs_len = @divCeil(abi_size, 8);
174790 assert(shift_abi_size >= 1 and shift_abi_size <= 2);174790 assert(shift_abi_size >= 1 and shift_abi_size <= 2);
174791174791
174792 const rcx_lock: ?RegisterLock = switch (rhs_mcv) {174792 const rcx_lock: ?RegisterLock = switch (rhs_mcv) {
...@@ -179598,7 +179598,7 @@ fn genSetReg(...@@ -179598,7 +179598,7 @@ fn genSetReg(
179598 if (pack_alias != sign_alias) try cg.asmRegisterRegister(.{ ._dqa, .mov }, pack_alias, sign_alias);179598 if (pack_alias != sign_alias) try cg.asmRegisterRegister(.{ ._dqa, .mov }, pack_alias, sign_alias);
179599 try cg.asmRegisterRegister(.{ .p_b, .ackssw }, pack_alias, pack_alias);179599 try cg.asmRegisterRegister(.{ .p_b, .ackssw }, pack_alias, pack_alias);
179600 }179600 }
179601 mask_size = std.math.divCeil(u32, mask_size, 2) catch unreachable;179601 mask_size = @divCeil(mask_size, 2);
179602 break :pack_reg pack_reg;179602 break :pack_reg pack_reg;
179603 },179603 },
179604 };179604 };
...@@ -180162,7 +180162,7 @@ fn airBitCast(self: *CodeGen, inst: Air.Inst.Index) !void {...@@ -180162,7 +180162,7 @@ fn airBitCast(self: *CodeGen, inst: Air.Inst.Index) !void {
180162 const bit_size = dst_ty.bitSize(zcu);180162 const bit_size = dst_ty.bitSize(zcu);
180163 if (abi_size * 8 <= bit_size) break :result dst_mcv;180163 if (abi_size * 8 <= bit_size) break :result dst_mcv;
180164180164
180165 const dst_limbs_len = std.math.divCeil(u31, @intCast(bit_size), 64) catch unreachable;180165 const dst_limbs_len: u31 = @intCast(@divCeil(bit_size, 64));
180166 const high_mcv: MCValue = switch (dst_mcv) {180166 const high_mcv: MCValue = switch (dst_mcv) {
180167 .register => |dst_reg| .{ .register = dst_reg },180167 .register => |dst_reg| .{ .register = dst_reg },
180168 .register_pair => |dst_regs| .{ .register = dst_regs[1] },180168 .register_pair => |dst_regs| .{ .register = dst_regs[1] },
...@@ -183555,7 +183555,7 @@ const Temp = struct {...@@ -183555,7 +183555,7 @@ const Temp = struct {
183555 const part_ty: Type = if (src_regs.len == 1)183555 const part_ty: Type = if (src_regs.len == 1)
183556 src_ty183556 src_ty
183557 else if (cg.intInfo(src_ty)) |int_info| part_ty: {183557 else if (cg.intInfo(src_ty)) |int_info| part_ty: {
183558 assert(src_regs.len == std.math.divCeil(u16, int_info.bits, 64) catch unreachable);183558 assert(src_regs.len == @divCeil(int_info.bits, 64));
183559 break :part_ty .u64;183559 break :part_ty .u64;
183560 } else part_ty: switch (ip.indexToKey(src_ty.toIntern())) {183560 } else part_ty: switch (ip.indexToKey(src_ty.toIntern())) {
183561 else => std.debug.panic("{s}: {f}\n", .{ @src().fn_name, src_ty.fmt(cg.pt) }),183561 else => std.debug.panic("{s}: {f}\n", .{ @src().fn_name, src_ty.fmt(cg.pt) }),
...@@ -183565,7 +183565,7 @@ const Temp = struct {...@@ -183565,7 +183565,7 @@ const Temp = struct {
183565 break :part_ty .usize;183565 break :part_ty .usize;
183566 },183566 },
183567 .array_type => {183567 .array_type => {
183568 assert(src_regs.len - part_index == std.math.divCeil(u32, src_size, 8) catch unreachable);183568 assert(src_regs.len - part_index == @divCeil(src_size, 8));
183569 break :part_ty try cg.pt.intType(.unsigned, @as(u16, 8) * @min(src_size, 8));183569 break :part_ty try cg.pt.intType(.unsigned, @as(u16, 8) * @min(src_size, 8));
183570 },183570 },
183571 .vector_type => |vector_type| switch (@divExact(vector_type.len, src_regs.len)) {183571 .vector_type => |vector_type| switch (@divExact(vector_type.len, src_regs.len)) {
...@@ -183585,7 +183585,7 @@ const Temp = struct {...@@ -183585,7 +183585,7 @@ const Temp = struct {
183585 },183585 },
183586 },183586 },
183587 .struct_type, .union_type => {183587 .struct_type, .union_type => {
183588 assert(src_regs.len - part_index == std.math.divCeil(u32, src_size, 8) catch unreachable);183588 assert(src_regs.len - part_index == @divCeil(src_size, 8));
183589 break :part_ty switch (src_size) {183589 break :part_ty switch (src_size) {
183590 0, 3, 5...7 => unreachable,183590 0, 3, 5...7 => unreachable,
183591 1 => .u8,183591 1 => .u8,
src/codegen/x86_64/Emit.zig+1-1
...@@ -772,7 +772,7 @@ fn encodeInst(emit: *Emit, lowered_inst: Instruction, reloc_info: []const RelocI...@@ -772,7 +772,7 @@ fn encodeInst(emit: *Emit, lowered_inst: Instruction, reloc_info: []const RelocI
772 const enc_length: u4 = if (is_mem) switch (lowered_inst.ops[op_index].mem.sib.base) {772 const enc_length: u4 = if (is_mem) switch (lowered_inst.ops[op_index].mem.sib.base) {
773 .rip_inst => 4,773 .rip_inst => 4,
774 else => unreachable,774 else => unreachable,
775 } else @intCast(std.math.divCeil(u7, @intCast(op.immBitSize()), 8) catch unreachable);775 } else @intCast(@divCeil(op.immBitSize(), 8));
776 reloc_offset -= enc_length;776 reloc_offset -= enc_length;
777 if (op_index == reloc.op_index) break :reloc_offset_length .{ reloc_offset, enc_length };777 if (op_index == reloc.op_index) break :reloc_offset_length .{ reloc_offset, enc_length };
778 assert(!is_mem);778 assert(!is_mem);
src/link/Dwarf.zig+3-3
...@@ -2137,7 +2137,7 @@ pub const WipNav = struct {...@@ -2137,7 +2137,7 @@ pub const WipNav = struct {
2137 .signed => DW.FORM.sdata,2137 .signed => DW.FORM.sdata,
2138 .unsigned => DW.FORM.udata,2138 .unsigned => DW.FORM.udata,
2139 }));2139 }));
2140 try wip_nav.debug_info.ensureUnusedCapacity(std.math.divCeil(usize, bits, 7) catch unreachable);2140 try wip_nav.debug_info.ensureUnusedCapacity(@divCeil(bits, 7));
2141 var bit: usize = 0;2141 var bit: usize = 0;
2142 var carry: u1 = 1;2142 var carry: u1 = 1;
2143 while (bit < bits) {2143 while (bit < bits) {
...@@ -2158,7 +2158,7 @@ pub const WipNav = struct {...@@ -2158,7 +2158,7 @@ pub const WipNav = struct {
2158 }2158 }
2159 } else {2159 } else {
2160 try diw.writeUleb128(DW.FORM.block);2160 try diw.writeUleb128(DW.FORM.block);
2161 const bytes = @max(ty.abiSize(zcu), std.math.divCeil(usize, bits, 8) catch unreachable);2161 const bytes = @max(ty.abiSize(zcu), @divCeil(bits, 8));
2162 try diw.writeUleb128(bytes);2162 try diw.writeUleb128(bytes);
2163 try wip_nav.debug_info.ensureUnusedCapacity(@intCast(bytes));2163 try wip_nav.debug_info.ensureUnusedCapacity(@intCast(bytes));
2164 big_int.writeTwosComplement(2164 big_int.writeTwosComplement(
...@@ -4275,7 +4275,7 @@ fn updateConstInner(dwarf: *Dwarf, pt: Zcu.PerThread, debug_const_index: link.Co...@@ -4275,7 +4275,7 @@ fn updateConstInner(dwarf: *Dwarf, pt: Zcu.PerThread, debug_const_index: link.Co
4275 try wip_nav.abbrevCode(.aggregate_undefined_comptime_value);4275 try wip_nav.abbrevCode(.aggregate_undefined_comptime_value);
4276 try wip_nav.refType(.fromInterned(error_union.ty));4276 try wip_nav.refType(.fromInterned(error_union.ty));
4277 var err_buf: [4]u8 = undefined;4277 var err_buf: [4]u8 = undefined;
4278 const err_bytes = err_buf[0 .. std.math.divCeil(u17, zcu.errorSetBits(), 8) catch unreachable];4278 const err_bytes = err_buf[0..@divCeil(zcu.errorSetBits(), 8)];
4279 dwarf.writeInt(err_bytes, switch (error_union.val) {4279 dwarf.writeInt(err_bytes, switch (error_union.val) {
4280 .err_name => |err_name| try pt.getErrorValue(err_name),4280 .err_name => |err_name| try pt.getErrorValue(err_name),
4281 .payload => 0,4281 .payload => 0,