authorgravatar for spexguy070@gmail.comMartin Wickham <spexguy070@gmail.com> 2021-07-10 21:47:07-05:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-07-11 02:00:04-04:00
log75d1b113aa6adf983497a78a0a0e61ecac7aaa54
tree240b0c60d30190d94d672a6baacb5db479f9da74
parent968d1ecf17c0a0774d43965332d00d4ad39743b9

Rename IrInstSrc to Stage1ZirInst and IrInstGen to Stage1AirInst

10 files changed, 6201 insertions(+), 6201 deletions(-)

src/stage1/all_types.hpp+1096-1096
...@@ -31,14 +31,14 @@ struct BuiltinFnEntry;...@@ -31,14 +31,14 @@ struct BuiltinFnEntry;
31struct TypeStructField;31struct TypeStructField;
32struct CodeGen;32struct CodeGen;
33struct ZigValue;33struct ZigValue;
34struct IrInstSrc;34struct Stage1ZirInst;
35struct IrInstGen;35struct Stage1AirInst;
36struct IrInstGenCast;36struct Stage1AirInstCast;
37struct IrInstGenAlloca;37struct Stage1AirInstAlloca;
38struct IrInstGenCall;38struct Stage1AirInstCall;
39struct IrInstGenAwait;39struct Stage1AirInstAwait;
40struct Stage1ZirBasicBlock;40struct Stage1ZirBasicBlock;
41struct IrBasicBlockGen;41struct Stage1AirBasicBlock;
42struct ScopeDecls;42struct ScopeDecls;
43struct ZigWindowsSDK;43struct ZigWindowsSDK;
44struct Tld;44struct Tld;
...@@ -122,7 +122,7 @@ struct Stage1Zir {...@@ -122,7 +122,7 @@ struct Stage1Zir {
122};122};
123123
124struct Stage1Air {124struct Stage1Air {
125 ZigList<IrBasicBlockGen *> basic_block_list;125 ZigList<Stage1AirBasicBlock *> basic_block_list;
126 Buf *name;126 Buf *name;
127 ZigFn *name_fn;127 ZigFn *name_fn;
128 size_t mem_slot_count;128 size_t mem_slot_count;
...@@ -311,7 +311,7 @@ struct ConstErrValue {...@@ -311,7 +311,7 @@ struct ConstErrValue {
311311
312struct ConstBoundFnValue {312struct ConstBoundFnValue {
313 ZigFn *fn;313 ZigFn *fn;
314 IrInstGen *first_arg;314 Stage1AirInst *first_arg;
315 AstNode *first_arg_src;315 AstNode *first_arg_src;
316};316};
317317
...@@ -400,14 +400,14 @@ struct LazyValueAlignOf {...@@ -400,14 +400,14 @@ struct LazyValueAlignOf {
400 LazyValue base;400 LazyValue base;
401401
402 IrAnalyze *ira;402 IrAnalyze *ira;
403 IrInstGen *target_type;403 Stage1AirInst *target_type;
404};404};
405405
406struct LazyValueSizeOf {406struct LazyValueSizeOf {
407 LazyValue base;407 LazyValue base;
408408
409 IrAnalyze *ira;409 IrAnalyze *ira;
410 IrInstGen *target_type;410 Stage1AirInst *target_type;
411411
412 bool bit_size;412 bool bit_size;
413};413};
...@@ -416,9 +416,9 @@ struct LazyValueSliceType {...@@ -416,9 +416,9 @@ struct LazyValueSliceType {
416 LazyValue base;416 LazyValue base;
417417
418 IrAnalyze *ira;418 IrAnalyze *ira;
419 IrInstGen *sentinel; // can be null419 Stage1AirInst *sentinel; // can be null
420 IrInstGen *elem_type;420 Stage1AirInst *elem_type;
421 IrInstGen *align_inst; // can be null421 Stage1AirInst *align_inst; // can be null
422422
423 bool is_const;423 bool is_const;
424 bool is_volatile;424 bool is_volatile;
...@@ -429,8 +429,8 @@ struct LazyValueArrayType {...@@ -429,8 +429,8 @@ struct LazyValueArrayType {
429 LazyValue base;429 LazyValue base;
430430
431 IrAnalyze *ira;431 IrAnalyze *ira;
432 IrInstGen *sentinel; // can be null432 Stage1AirInst *sentinel; // can be null
433 IrInstGen *elem_type;433 Stage1AirInst *elem_type;
434 uint64_t length;434 uint64_t length;
435};435};
436436
...@@ -438,9 +438,9 @@ struct LazyValuePtrType {...@@ -438,9 +438,9 @@ struct LazyValuePtrType {
438 LazyValue base;438 LazyValue base;
439439
440 IrAnalyze *ira;440 IrAnalyze *ira;
441 IrInstGen *sentinel; // can be null441 Stage1AirInst *sentinel; // can be null
442 IrInstGen *elem_type;442 Stage1AirInst *elem_type;
443 IrInstGen *align_inst; // can be null443 Stage1AirInst *align_inst; // can be null
444444
445 PtrLen ptr_len;445 PtrLen ptr_len;
446 uint32_t bit_offset_in_host;446 uint32_t bit_offset_in_host;
...@@ -455,14 +455,14 @@ struct LazyValuePtrTypeSimple {...@@ -455,14 +455,14 @@ struct LazyValuePtrTypeSimple {
455 LazyValue base;455 LazyValue base;
456456
457 IrAnalyze *ira;457 IrAnalyze *ira;
458 IrInstGen *elem_type;458 Stage1AirInst *elem_type;
459};459};
460460
461struct LazyValueOptType {461struct LazyValueOptType {
462 LazyValue base;462 LazyValue base;
463463
464 IrAnalyze *ira;464 IrAnalyze *ira;
465 IrInstGen *payload_type;465 Stage1AirInst *payload_type;
466};466};
467467
468struct LazyValueFnType {468struct LazyValueFnType {
...@@ -470,9 +470,9 @@ struct LazyValueFnType {...@@ -470,9 +470,9 @@ struct LazyValueFnType {
470470
471 IrAnalyze *ira;471 IrAnalyze *ira;
472 AstNode *proto_node;472 AstNode *proto_node;
473 IrInstGen **param_types;473 Stage1AirInst **param_types;
474 IrInstGen *align_inst; // can be null474 Stage1AirInst *align_inst; // can be null
475 IrInstGen *return_type;475 Stage1AirInst *return_type;
476476
477 CallingConvention cc;477 CallingConvention cc;
478 bool is_generic;478 bool is_generic;
...@@ -482,8 +482,8 @@ struct LazyValueErrUnionType {...@@ -482,8 +482,8 @@ struct LazyValueErrUnionType {
482 LazyValue base;482 LazyValue base;
483483
484 IrAnalyze *ira;484 IrAnalyze *ira;
485 IrInstGen *err_set_type;485 Stage1AirInst *err_set_type;
486 IrInstGen *payload_type;486 Stage1AirInst *payload_type;
487 Buf *type_name;487 Buf *type_name;
488};488};
489489
...@@ -1651,13 +1651,13 @@ struct ZigFn {...@@ -1651,13 +1651,13 @@ struct ZigFn {
1651 size_t branch_quota;1651 size_t branch_quota;
1652 AstNode **param_source_nodes;1652 AstNode **param_source_nodes;
1653 Buf **param_names;1653 Buf **param_names;
1654 IrInstGen *err_code_spill;1654 Stage1AirInst *err_code_spill;
1655 AstNode *assumed_non_async;1655 AstNode *assumed_non_async;
16561656
1657 AstNode *fn_no_inline_set_node;1657 AstNode *fn_no_inline_set_node;
1658 AstNode *fn_static_eval_set_node;1658 AstNode *fn_static_eval_set_node;
16591659
1660 ZigList<IrInstGenAlloca *> alloca_gen_list;1660 ZigList<Stage1AirInstAlloca *> alloca_gen_list;
1661 ZigList<ZigVar *> variable_list;1661 ZigList<ZigVar *> variable_list;
16621662
1663 Buf *section_name;1663 Buf *section_name;
...@@ -1669,8 +1669,8 @@ struct ZigFn {...@@ -1669,8 +1669,8 @@ struct ZigFn {
1669 AstNode *non_async_node;1669 AstNode *non_async_node;
16701670
1671 ZigList<GlobalExport> export_list;1671 ZigList<GlobalExport> export_list;
1672 ZigList<IrInstGenCall *> call_list;1672 ZigList<Stage1AirInstCall *> call_list;
1673 ZigList<IrInstGenAwait *> await_list;1673 ZigList<Stage1AirInstAwait *> await_list;
16741674
1675 LLVMValueRef valgrind_client_request_array;1675 LLVMValueRef valgrind_client_request_array;
16761676
...@@ -2096,9 +2096,9 @@ struct CodeGen {...@@ -2096,9 +2096,9 @@ struct CodeGen {
2096 Buf *builtin_zig_path;2096 Buf *builtin_zig_path;
2097 Buf *zig_std_special_dir; // Cannot be overridden; derived from zig_lib_dir.2097 Buf *zig_std_special_dir; // Cannot be overridden; derived from zig_lib_dir.
20982098
2099 IrInstSrc *invalid_inst_src;2099 Stage1ZirInst *invalid_inst_src;
2100 IrInstGen *invalid_inst_gen;2100 Stage1AirInst *invalid_inst_gen;
2101 IrInstGen *unreach_instruction;2101 Stage1AirInst *unreach_instruction;
21022102
2103 ZigValue panic_msg_vals[PanicMsgIdCount];2103 ZigValue panic_msg_vals[PanicMsgIdCount];
21042104
...@@ -2165,8 +2165,8 @@ struct ZigVar {...@@ -2165,8 +2165,8 @@ struct ZigVar {
2165 ZigValue *const_value;2165 ZigValue *const_value;
2166 ZigType *var_type;2166 ZigType *var_type;
2167 LLVMValueRef value_ref;2167 LLVMValueRef value_ref;
2168 IrInstSrc *is_comptime;2168 Stage1ZirInst *is_comptime;
2169 IrInstGen *ptr_instruction;2169 Stage1AirInst *ptr_instruction;
2170 // which node is the declaration of the variable2170 // which node is the declaration of the variable
2171 AstNode *decl_node;2171 AstNode *decl_node;
2172 ZigLLVMDILocalVariable *di_loc_var;2172 ZigLLVMDILocalVariable *di_loc_var;
...@@ -2268,9 +2268,9 @@ struct ScopeBlock {...@@ -2268,9 +2268,9 @@ struct ScopeBlock {
22682268
2269 Buf *name;2269 Buf *name;
2270 Stage1ZirBasicBlock *end_block;2270 Stage1ZirBasicBlock *end_block;
2271 IrInstSrc *is_comptime;2271 Stage1ZirInst *is_comptime;
2272 ResultLocPeerParent *peer_parent;2272 ResultLocPeerParent *peer_parent;
2273 ZigList<IrInstSrc *> *incoming_values;2273 ZigList<Stage1ZirInst *> *incoming_values;
2274 ZigList<Stage1ZirBasicBlock *> *incoming_blocks;2274 ZigList<Stage1ZirBasicBlock *> *incoming_blocks;
22752275
2276 AstNode *safety_set_node;2276 AstNode *safety_set_node;
...@@ -2325,8 +2325,8 @@ struct ScopeLoop {...@@ -2325,8 +2325,8 @@ struct ScopeLoop {
2325 Buf *name;2325 Buf *name;
2326 Stage1ZirBasicBlock *break_block;2326 Stage1ZirBasicBlock *break_block;
2327 Stage1ZirBasicBlock *continue_block;2327 Stage1ZirBasicBlock *continue_block;
2328 IrInstSrc *is_comptime;2328 Stage1ZirInst *is_comptime;
2329 ZigList<IrInstSrc *> *incoming_values;2329 ZigList<Stage1ZirInst *> *incoming_values;
2330 ZigList<Stage1ZirBasicBlock *> *incoming_blocks;2330 ZigList<Stage1ZirBasicBlock *> *incoming_blocks;
2331 ResultLocPeerParent *peer_parent;2331 ResultLocPeerParent *peer_parent;
2332 ScopeExpr *spill_scope;2332 ScopeExpr *spill_scope;
...@@ -2340,7 +2340,7 @@ struct ScopeLoop {...@@ -2340,7 +2340,7 @@ struct ScopeLoop {
2340struct ScopeRuntime {2340struct ScopeRuntime {
2341 Scope base;2341 Scope base;
23422342
2343 IrInstSrc *is_comptime;2343 Stage1ZirInst *is_comptime;
2344};2344};
23452345
2346// This scope is created for a suspend block in order to have labeled2346// This scope is created for a suspend block in order to have labeled
...@@ -2439,11 +2439,11 @@ enum AtomicRmwOp {...@@ -2439,11 +2439,11 @@ enum AtomicRmwOp {
2439// Phi instructions must be first in a basic block.2439// Phi instructions must be first in a basic block.
2440// The last instruction in a basic block must be of type unreachable.2440// The last instruction in a basic block must be of type unreachable.
2441struct Stage1ZirBasicBlock {2441struct Stage1ZirBasicBlock {
2442 ZigList<IrInstSrc *> instruction_list;2442 ZigList<Stage1ZirInst *> instruction_list;
2443 IrBasicBlockGen *child;2443 Stage1AirBasicBlock *child;
2444 Scope *scope;2444 Scope *scope;
2445 const char *name_hint;2445 const char *name_hint;
2446 IrInstSrc *suspend_instruction_ref;2446 Stage1ZirInst *suspend_instruction_ref;
24472447
2448 uint32_t ref_count;2448 uint32_t ref_count;
2449 uint32_t index; // index into the basic block list2449 uint32_t index; // index into the basic block list
...@@ -2453,8 +2453,8 @@ struct Stage1ZirBasicBlock {...@@ -2453,8 +2453,8 @@ struct Stage1ZirBasicBlock {
2453 bool in_resume_stack;2453 bool in_resume_stack;
2454};2454};
24552455
2456struct IrBasicBlockGen {2456struct Stage1AirBasicBlock {
2457 ZigList<IrInstGen *> instruction_list;2457 ZigList<Stage1AirInst *> instruction_list;
2458 Scope *scope;2458 Scope *scope;
2459 const char *name_hint;2459 const char *name_hint;
2460 LLVMBasicBlockRef llvm_block;2460 LLVMBasicBlockRef llvm_block;
...@@ -2462,7 +2462,7 @@ struct IrBasicBlockGen {...@@ -2462,7 +2462,7 @@ struct IrBasicBlockGen {
2462 // The instruction that referenced this basic block and caused us to2462 // The instruction that referenced this basic block and caused us to
2463 // analyze the basic block. If the same instruction wants us to emit2463 // analyze the basic block. If the same instruction wants us to emit
2464 // the same basic block, then we re-generate it instead of saving it.2464 // the same basic block, then we re-generate it instead of saving it.
2465 IrInstSrc *ref_instruction;2465 Stage1ZirInst *ref_instruction;
2466 // When this is non-null, a branch to this basic block is only allowed2466 // When this is non-null, a branch to this basic block is only allowed
2467 // if the branch is comptime. The instruction points to the reason2467 // if the branch is comptime. The instruction points to the reason
2468 // the basic block must be comptime.2468 // the basic block must be comptime.
...@@ -2475,246 +2475,246 @@ struct IrBasicBlockGen {...@@ -2475,246 +2475,246 @@ struct IrBasicBlockGen {
2475// Src instructions are generated by ir_gen_* functions in ir.cpp from AST.2475// Src instructions are generated by ir_gen_* functions in ir.cpp from AST.
2476// ir_analyze_* functions consume Src instructions and produce Gen instructions.2476// ir_analyze_* functions consume Src instructions and produce Gen instructions.
2477// Src instructions do not have type information; Gen instructions do.2477// Src instructions do not have type information; Gen instructions do.
2478enum IrInstSrcId : uint8_t {2478enum Stage1ZirInstId : uint8_t {
2479 IrInstSrcIdInvalid,2479 Stage1ZirInstIdInvalid,
2480 IrInstSrcIdDeclVar,2480 Stage1ZirInstIdDeclVar,
2481 IrInstSrcIdBr,2481 Stage1ZirInstIdBr,
2482 IrInstSrcIdCondBr,2482 Stage1ZirInstIdCondBr,
2483 IrInstSrcIdSwitchBr,2483 Stage1ZirInstIdSwitchBr,
2484 IrInstSrcIdSwitchVar,2484 Stage1ZirInstIdSwitchVar,
2485 IrInstSrcIdSwitchElseVar,2485 Stage1ZirInstIdSwitchElseVar,
2486 IrInstSrcIdSwitchTarget,2486 Stage1ZirInstIdSwitchTarget,
2487 IrInstSrcIdPhi,2487 Stage1ZirInstIdPhi,
2488 IrInstSrcIdUnOp,2488 Stage1ZirInstIdUnOp,
2489 IrInstSrcIdBinOp,2489 Stage1ZirInstIdBinOp,
2490 IrInstSrcIdMergeErrSets,2490 Stage1ZirInstIdMergeErrSets,
2491 IrInstSrcIdLoadPtr,2491 Stage1ZirInstIdLoadPtr,
2492 IrInstSrcIdStorePtr,2492 Stage1ZirInstIdStorePtr,
2493 IrInstSrcIdFieldPtr,2493 Stage1ZirInstIdFieldPtr,
2494 IrInstSrcIdElemPtr,2494 Stage1ZirInstIdElemPtr,
2495 IrInstSrcIdVarPtr,2495 Stage1ZirInstIdVarPtr,
2496 IrInstSrcIdCall,2496 Stage1ZirInstIdCall,
2497 IrInstSrcIdCallArgs,2497 Stage1ZirInstIdCallArgs,
2498 IrInstSrcIdCallExtra,2498 Stage1ZirInstIdCallExtra,
2499 IrInstSrcIdAsyncCallExtra,2499 Stage1ZirInstIdAsyncCallExtra,
2500 IrInstSrcIdConst,2500 Stage1ZirInstIdConst,
2501 IrInstSrcIdReturn,2501 Stage1ZirInstIdReturn,
2502 IrInstSrcIdContainerInitList,2502 Stage1ZirInstIdContainerInitList,
2503 IrInstSrcIdContainerInitFields,2503 Stage1ZirInstIdContainerInitFields,
2504 IrInstSrcIdUnreachable,2504 Stage1ZirInstIdUnreachable,
2505 IrInstSrcIdTypeOf,2505 Stage1ZirInstIdTypeOf,
2506 IrInstSrcIdSetCold,2506 Stage1ZirInstIdSetCold,
2507 IrInstSrcIdSetRuntimeSafety,2507 Stage1ZirInstIdSetRuntimeSafety,
2508 IrInstSrcIdSetFloatMode,2508 Stage1ZirInstIdSetFloatMode,
2509 IrInstSrcIdArrayType,2509 Stage1ZirInstIdArrayType,
2510 IrInstSrcIdAnyFrameType,2510 Stage1ZirInstIdAnyFrameType,
2511 IrInstSrcIdSliceType,2511 Stage1ZirInstIdSliceType,
2512 IrInstSrcIdAsm,2512 Stage1ZirInstIdAsm,
2513 IrInstSrcIdSizeOf,2513 Stage1ZirInstIdSizeOf,
2514 IrInstSrcIdTestNonNull,2514 Stage1ZirInstIdTestNonNull,
2515 IrInstSrcIdOptionalUnwrapPtr,2515 Stage1ZirInstIdOptionalUnwrapPtr,
2516 IrInstSrcIdClz,2516 Stage1ZirInstIdClz,
2517 IrInstSrcIdCtz,2517 Stage1ZirInstIdCtz,
2518 IrInstSrcIdPopCount,2518 Stage1ZirInstIdPopCount,
2519 IrInstSrcIdBswap,2519 Stage1ZirInstIdBswap,
2520 IrInstSrcIdBitReverse,2520 Stage1ZirInstIdBitReverse,
2521 IrInstSrcIdImport,2521 Stage1ZirInstIdImport,
2522 IrInstSrcIdCImport,2522 Stage1ZirInstIdCImport,
2523 IrInstSrcIdCInclude,2523 Stage1ZirInstIdCInclude,
2524 IrInstSrcIdCDefine,2524 Stage1ZirInstIdCDefine,
2525 IrInstSrcIdCUndef,2525 Stage1ZirInstIdCUndef,
2526 IrInstSrcIdRef,2526 Stage1ZirInstIdRef,
2527 IrInstSrcIdCompileErr,2527 Stage1ZirInstIdCompileErr,
2528 IrInstSrcIdCompileLog,2528 Stage1ZirInstIdCompileLog,
2529 IrInstSrcIdErrName,2529 Stage1ZirInstIdErrName,
2530 IrInstSrcIdEmbedFile,2530 Stage1ZirInstIdEmbedFile,
2531 IrInstSrcIdCmpxchg,2531 Stage1ZirInstIdCmpxchg,
2532 IrInstSrcIdFence,2532 Stage1ZirInstIdFence,
2533 IrInstSrcIdReduce,2533 Stage1ZirInstIdReduce,
2534 IrInstSrcIdTruncate,2534 Stage1ZirInstIdTruncate,
2535 IrInstSrcIdIntCast,2535 Stage1ZirInstIdIntCast,
2536 IrInstSrcIdFloatCast,2536 Stage1ZirInstIdFloatCast,
2537 IrInstSrcIdIntToFloat,2537 Stage1ZirInstIdIntToFloat,
2538 IrInstSrcIdFloatToInt,2538 Stage1ZirInstIdFloatToInt,
2539 IrInstSrcIdBoolToInt,2539 Stage1ZirInstIdBoolToInt,
2540 IrInstSrcIdVectorType,2540 Stage1ZirInstIdVectorType,
2541 IrInstSrcIdShuffleVector,2541 Stage1ZirInstIdShuffleVector,
2542 IrInstSrcIdSplat,2542 Stage1ZirInstIdSplat,
2543 IrInstSrcIdBoolNot,2543 Stage1ZirInstIdBoolNot,
2544 IrInstSrcIdMemset,2544 Stage1ZirInstIdMemset,
2545 IrInstSrcIdMemcpy,2545 Stage1ZirInstIdMemcpy,
2546 IrInstSrcIdSlice,2546 Stage1ZirInstIdSlice,
2547 IrInstSrcIdBreakpoint,2547 Stage1ZirInstIdBreakpoint,
2548 IrInstSrcIdReturnAddress,2548 Stage1ZirInstIdReturnAddress,
2549 IrInstSrcIdFrameAddress,2549 Stage1ZirInstIdFrameAddress,
2550 IrInstSrcIdFrameHandle,2550 Stage1ZirInstIdFrameHandle,
2551 IrInstSrcIdFrameType,2551 Stage1ZirInstIdFrameType,
2552 IrInstSrcIdFrameSize,2552 Stage1ZirInstIdFrameSize,
2553 IrInstSrcIdAlignOf,2553 Stage1ZirInstIdAlignOf,
2554 IrInstSrcIdOverflowOp,2554 Stage1ZirInstIdOverflowOp,
2555 IrInstSrcIdTestErr,2555 Stage1ZirInstIdTestErr,
2556 IrInstSrcIdMulAdd,2556 Stage1ZirInstIdMulAdd,
2557 IrInstSrcIdFloatOp,2557 Stage1ZirInstIdFloatOp,
2558 IrInstSrcIdUnwrapErrCode,2558 Stage1ZirInstIdUnwrapErrCode,
2559 IrInstSrcIdUnwrapErrPayload,2559 Stage1ZirInstIdUnwrapErrPayload,
2560 IrInstSrcIdFnProto,2560 Stage1ZirInstIdFnProto,
2561 IrInstSrcIdTestComptime,2561 Stage1ZirInstIdTestComptime,
2562 IrInstSrcIdPtrCast,2562 Stage1ZirInstIdPtrCast,
2563 IrInstSrcIdBitCast,2563 Stage1ZirInstIdBitCast,
2564 IrInstSrcIdIntToPtr,2564 Stage1ZirInstIdIntToPtr,
2565 IrInstSrcIdPtrToInt,2565 Stage1ZirInstIdPtrToInt,
2566 IrInstSrcIdIntToEnum,2566 Stage1ZirInstIdIntToEnum,
2567 IrInstSrcIdEnumToInt,2567 Stage1ZirInstIdEnumToInt,
2568 IrInstSrcIdIntToErr,2568 Stage1ZirInstIdIntToErr,
2569 IrInstSrcIdErrToInt,2569 Stage1ZirInstIdErrToInt,
2570 IrInstSrcIdCheckSwitchProngsUnderYes,2570 Stage1ZirInstIdCheckSwitchProngsUnderYes,
2571 IrInstSrcIdCheckSwitchProngsUnderNo,2571 Stage1ZirInstIdCheckSwitchProngsUnderNo,
2572 IrInstSrcIdCheckStatementIsVoid,2572 Stage1ZirInstIdCheckStatementIsVoid,
2573 IrInstSrcIdTypeName,2573 Stage1ZirInstIdTypeName,
2574 IrInstSrcIdDeclRef,2574 Stage1ZirInstIdDeclRef,
2575 IrInstSrcIdPanic,2575 Stage1ZirInstIdPanic,
2576 IrInstSrcIdTagName,2576 Stage1ZirInstIdTagName,
2577 IrInstSrcIdFieldParentPtr,2577 Stage1ZirInstIdFieldParentPtr,
2578 IrInstSrcIdOffsetOf,2578 Stage1ZirInstIdOffsetOf,
2579 IrInstSrcIdBitOffsetOf,2579 Stage1ZirInstIdBitOffsetOf,
2580 IrInstSrcIdTypeInfo,2580 Stage1ZirInstIdTypeInfo,
2581 IrInstSrcIdType,2581 Stage1ZirInstIdType,
2582 IrInstSrcIdHasField,2582 Stage1ZirInstIdHasField,
2583 IrInstSrcIdSetEvalBranchQuota,2583 Stage1ZirInstIdSetEvalBranchQuota,
2584 IrInstSrcIdPtrType,2584 Stage1ZirInstIdPtrType,
2585 IrInstSrcIdPtrTypeSimple,2585 Stage1ZirInstIdPtrTypeSimple,
2586 IrInstSrcIdPtrTypeSimpleConst,2586 Stage1ZirInstIdPtrTypeSimpleConst,
2587 IrInstSrcIdAlignCast,2587 Stage1ZirInstIdAlignCast,
2588 IrInstSrcIdImplicitCast,2588 Stage1ZirInstIdImplicitCast,
2589 IrInstSrcIdResolveResult,2589 Stage1ZirInstIdResolveResult,
2590 IrInstSrcIdResetResult,2590 Stage1ZirInstIdResetResult,
2591 IrInstSrcIdSetAlignStack,2591 Stage1ZirInstIdSetAlignStack,
2592 IrInstSrcIdArgTypeAllowVarFalse,2592 Stage1ZirInstIdArgTypeAllowVarFalse,
2593 IrInstSrcIdArgTypeAllowVarTrue,2593 Stage1ZirInstIdArgTypeAllowVarTrue,
2594 IrInstSrcIdExport,2594 Stage1ZirInstIdExport,
2595 IrInstSrcIdExtern,2595 Stage1ZirInstIdExtern,
2596 IrInstSrcIdErrorReturnTrace,2596 Stage1ZirInstIdErrorReturnTrace,
2597 IrInstSrcIdErrorUnion,2597 Stage1ZirInstIdErrorUnion,
2598 IrInstSrcIdAtomicRmw,2598 Stage1ZirInstIdAtomicRmw,
2599 IrInstSrcIdAtomicLoad,2599 Stage1ZirInstIdAtomicLoad,
2600 IrInstSrcIdAtomicStore,2600 Stage1ZirInstIdAtomicStore,
2601 IrInstSrcIdSaveErrRetAddr,2601 Stage1ZirInstIdSaveErrRetAddr,
2602 IrInstSrcIdAddImplicitReturnType,2602 Stage1ZirInstIdAddImplicitReturnType,
2603 IrInstSrcIdErrSetCast,2603 Stage1ZirInstIdErrSetCast,
2604 IrInstSrcIdCheckRuntimeScope,2604 Stage1ZirInstIdCheckRuntimeScope,
2605 IrInstSrcIdHasDecl,2605 Stage1ZirInstIdHasDecl,
2606 IrInstSrcIdUndeclaredIdent,2606 Stage1ZirInstIdUndeclaredIdent,
2607 IrInstSrcIdAlloca,2607 Stage1ZirInstIdAlloca,
2608 IrInstSrcIdEndExpr,2608 Stage1ZirInstIdEndExpr,
2609 IrInstSrcIdUnionInitNamedField,2609 Stage1ZirInstIdUnionInitNamedField,
2610 IrInstSrcIdSuspendBegin,2610 Stage1ZirInstIdSuspendBegin,
2611 IrInstSrcIdSuspendFinish,2611 Stage1ZirInstIdSuspendFinish,
2612 IrInstSrcIdAwait,2612 Stage1ZirInstIdAwait,
2613 IrInstSrcIdResume,2613 Stage1ZirInstIdResume,
2614 IrInstSrcIdSpillBegin,2614 Stage1ZirInstIdSpillBegin,
2615 IrInstSrcIdSpillEnd,2615 Stage1ZirInstIdSpillEnd,
2616 IrInstSrcIdWasmMemorySize,2616 Stage1ZirInstIdWasmMemorySize,
2617 IrInstSrcIdWasmMemoryGrow,2617 Stage1ZirInstIdWasmMemoryGrow,
2618 IrInstSrcIdSrc,2618 Stage1ZirInstIdSrc,
2619};2619};
26202620
2621// ir_render_* functions in codegen.cpp consume Gen instructions and produce LLVM IR.2621// ir_render_* functions in codegen.cpp consume Gen instructions and produce LLVM IR.
2622// Src instructions do not have type information; Gen instructions do.2622// Src instructions do not have type information; Gen instructions do.
2623enum IrInstGenId : uint8_t {2623enum Stage1AirInstId : uint8_t {
2624 IrInstGenIdInvalid,2624 Stage1AirInstIdInvalid,
2625 IrInstGenIdDeclVar,2625 Stage1AirInstIdDeclVar,
2626 IrInstGenIdBr,2626 Stage1AirInstIdBr,
2627 IrInstGenIdCondBr,2627 Stage1AirInstIdCondBr,
2628 IrInstGenIdSwitchBr,2628 Stage1AirInstIdSwitchBr,
2629 IrInstGenIdPhi,2629 Stage1AirInstIdPhi,
2630 IrInstGenIdBinaryNot,2630 Stage1AirInstIdBinaryNot,
2631 IrInstGenIdNegation,2631 Stage1AirInstIdNegation,
2632 IrInstGenIdBinOp,2632 Stage1AirInstIdBinOp,
2633 IrInstGenIdLoadPtr,2633 Stage1AirInstIdLoadPtr,
2634 IrInstGenIdStorePtr,2634 Stage1AirInstIdStorePtr,
2635 IrInstGenIdVectorStoreElem,2635 Stage1AirInstIdVectorStoreElem,
2636 IrInstGenIdStructFieldPtr,2636 Stage1AirInstIdStructFieldPtr,
2637 IrInstGenIdUnionFieldPtr,2637 Stage1AirInstIdUnionFieldPtr,
2638 IrInstGenIdElemPtr,2638 Stage1AirInstIdElemPtr,
2639 IrInstGenIdVarPtr,2639 Stage1AirInstIdVarPtr,
2640 IrInstGenIdReturnPtr,2640 Stage1AirInstIdReturnPtr,
2641 IrInstGenIdCall,2641 Stage1AirInstIdCall,
2642 IrInstGenIdReturn,2642 Stage1AirInstIdReturn,
2643 IrInstGenIdCast,2643 Stage1AirInstIdCast,
2644 IrInstGenIdUnreachable,2644 Stage1AirInstIdUnreachable,
2645 IrInstGenIdAsm,2645 Stage1AirInstIdAsm,
2646 IrInstGenIdTestNonNull,2646 Stage1AirInstIdTestNonNull,
2647 IrInstGenIdOptionalUnwrapPtr,2647 Stage1AirInstIdOptionalUnwrapPtr,
2648 IrInstGenIdOptionalWrap,2648 Stage1AirInstIdOptionalWrap,
2649 IrInstGenIdUnionTag,2649 Stage1AirInstIdUnionTag,
2650 IrInstGenIdClz,2650 Stage1AirInstIdClz,
2651 IrInstGenIdCtz,2651 Stage1AirInstIdCtz,
2652 IrInstGenIdPopCount,2652 Stage1AirInstIdPopCount,
2653 IrInstGenIdBswap,2653 Stage1AirInstIdBswap,
2654 IrInstGenIdBitReverse,2654 Stage1AirInstIdBitReverse,
2655 IrInstGenIdRef,2655 Stage1AirInstIdRef,
2656 IrInstGenIdErrName,2656 Stage1AirInstIdErrName,
2657 IrInstGenIdCmpxchg,2657 Stage1AirInstIdCmpxchg,
2658 IrInstGenIdFence,2658 Stage1AirInstIdFence,
2659 IrInstGenIdReduce,2659 Stage1AirInstIdReduce,
2660 IrInstGenIdTruncate,2660 Stage1AirInstIdTruncate,
2661 IrInstGenIdShuffleVector,2661 Stage1AirInstIdShuffleVector,
2662 IrInstGenIdSplat,2662 Stage1AirInstIdSplat,
2663 IrInstGenIdBoolNot,2663 Stage1AirInstIdBoolNot,
2664 IrInstGenIdMemset,2664 Stage1AirInstIdMemset,
2665 IrInstGenIdMemcpy,2665 Stage1AirInstIdMemcpy,
2666 IrInstGenIdSlice,2666 Stage1AirInstIdSlice,
2667 IrInstGenIdBreakpoint,2667 Stage1AirInstIdBreakpoint,
2668 IrInstGenIdReturnAddress,2668 Stage1AirInstIdReturnAddress,
2669 IrInstGenIdFrameAddress,2669 Stage1AirInstIdFrameAddress,
2670 IrInstGenIdFrameHandle,2670 Stage1AirInstIdFrameHandle,
2671 IrInstGenIdFrameSize,2671 Stage1AirInstIdFrameSize,
2672 IrInstGenIdOverflowOp,2672 Stage1AirInstIdOverflowOp,
2673 IrInstGenIdTestErr,2673 Stage1AirInstIdTestErr,
2674 IrInstGenIdMulAdd,2674 Stage1AirInstIdMulAdd,
2675 IrInstGenIdFloatOp,2675 Stage1AirInstIdFloatOp,
2676 IrInstGenIdUnwrapErrCode,2676 Stage1AirInstIdUnwrapErrCode,
2677 IrInstGenIdUnwrapErrPayload,2677 Stage1AirInstIdUnwrapErrPayload,
2678 IrInstGenIdErrWrapCode,2678 Stage1AirInstIdErrWrapCode,
2679 IrInstGenIdErrWrapPayload,2679 Stage1AirInstIdErrWrapPayload,
2680 IrInstGenIdPtrCast,2680 Stage1AirInstIdPtrCast,
2681 IrInstGenIdBitCast,2681 Stage1AirInstIdBitCast,
2682 IrInstGenIdWidenOrShorten,2682 Stage1AirInstIdWidenOrShorten,
2683 IrInstGenIdIntToPtr,2683 Stage1AirInstIdIntToPtr,
2684 IrInstGenIdPtrToInt,2684 Stage1AirInstIdPtrToInt,
2685 IrInstGenIdIntToEnum,2685 Stage1AirInstIdIntToEnum,
2686 IrInstGenIdIntToErr,2686 Stage1AirInstIdIntToErr,
2687 IrInstGenIdErrToInt,2687 Stage1AirInstIdErrToInt,
2688 IrInstGenIdPanic,2688 Stage1AirInstIdPanic,
2689 IrInstGenIdTagName,2689 Stage1AirInstIdTagName,
2690 IrInstGenIdFieldParentPtr,2690 Stage1AirInstIdFieldParentPtr,
2691 IrInstGenIdAlignCast,2691 Stage1AirInstIdAlignCast,
2692 IrInstGenIdErrorReturnTrace,2692 Stage1AirInstIdErrorReturnTrace,
2693 IrInstGenIdAtomicRmw,2693 Stage1AirInstIdAtomicRmw,
2694 IrInstGenIdAtomicLoad,2694 Stage1AirInstIdAtomicLoad,
2695 IrInstGenIdAtomicStore,2695 Stage1AirInstIdAtomicStore,
2696 IrInstGenIdSaveErrRetAddr,2696 Stage1AirInstIdSaveErrRetAddr,
2697 IrInstGenIdVectorToArray,2697 Stage1AirInstIdVectorToArray,
2698 IrInstGenIdArrayToVector,2698 Stage1AirInstIdArrayToVector,
2699 IrInstGenIdAssertZero,2699 Stage1AirInstIdAssertZero,
2700 IrInstGenIdAssertNonNull,2700 Stage1AirInstIdAssertNonNull,
2701 IrInstGenIdPtrOfArrayToSlice,2701 Stage1AirInstIdPtrOfArrayToSlice,
2702 IrInstGenIdSuspendBegin,2702 Stage1AirInstIdSuspendBegin,
2703 IrInstGenIdSuspendFinish,2703 Stage1AirInstIdSuspendFinish,
2704 IrInstGenIdAwait,2704 Stage1AirInstIdAwait,
2705 IrInstGenIdResume,2705 Stage1AirInstIdResume,
2706 IrInstGenIdSpillBegin,2706 Stage1AirInstIdSpillBegin,
2707 IrInstGenIdSpillEnd,2707 Stage1AirInstIdSpillEnd,
2708 IrInstGenIdVectorExtractElem,2708 Stage1AirInstIdVectorExtractElem,
2709 IrInstGenIdAlloca,2709 Stage1AirInstIdAlloca,
2710 IrInstGenIdConst,2710 Stage1AirInstIdConst,
2711 IrInstGenIdWasmMemorySize,2711 Stage1AirInstIdWasmMemorySize,
2712 IrInstGenIdWasmMemoryGrow,2712 Stage1AirInstIdWasmMemoryGrow,
2713 IrInstGenIdExtern,2713 Stage1AirInstIdExtern,
2714};2714};
27152715
2716struct IrInstSrc {2716struct Stage1ZirInst {
2717 IrInstSrcId id;2717 Stage1ZirInstId id;
2718 uint16_t ref_count;2718 uint16_t ref_count;
2719 uint32_t debug_id;2719 uint32_t debug_id;
27202720
...@@ -2724,7 +2724,7 @@ struct IrInstSrc {...@@ -2724,7 +2724,7 @@ struct IrInstSrc {
2724 // When analyzing IR, instructions that point to this instruction in the "old ir"2724 // When analyzing IR, instructions that point to this instruction in the "old ir"
2725 // can find the instruction that corresponds to this value in the "new ir"2725 // can find the instruction that corresponds to this value in the "new ir"
2726 // with this child field.2726 // with this child field.
2727 IrInstGen *child;2727 Stage1AirInst *child;
2728 Stage1ZirBasicBlock *owner_bb;2728 Stage1ZirBasicBlock *owner_bb;
27292729
2730 // for debugging purposes, these are useful to call to inspect the instruction2730 // for debugging purposes, these are useful to call to inspect the instruction
...@@ -2732,8 +2732,8 @@ struct IrInstSrc {...@@ -2732,8 +2732,8 @@ struct IrInstSrc {
2732 void src();2732 void src();
2733};2733};
27342734
2735struct IrInstGen {2735struct Stage1AirInst {
2736 IrInstGenId id;2736 Stage1AirInstId id;
2737 // if ref_count is zero and the instruction has no side effects,2737 // if ref_count is zero and the instruction has no side effects,
2738 // the instruction can be omitted in codegen2738 // the instruction can be omitted in codegen
2739 uint16_t ref_count;2739 uint16_t ref_count;
...@@ -2744,130 +2744,130 @@ struct IrInstGen {...@@ -2744,130 +2744,130 @@ struct IrInstGen {
27442744
2745 LLVMValueRef llvm_value;2745 LLVMValueRef llvm_value;
2746 ZigValue *value;2746 ZigValue *value;
2747 IrBasicBlockGen *owner_bb;2747 Stage1AirBasicBlock *owner_bb;
2748 // Nearly any instruction can have to be stored as a local variable before suspending2748 // Nearly any instruction can have to be stored as a local variable before suspending
2749 // and then loaded after resuming, in case there is an expression with a suspend point2749 // and then loaded after resuming, in case there is an expression with a suspend point
2750 // in it, such as: x + await y2750 // in it, such as: x + await y
2751 IrInstGen *spill;2751 Stage1AirInst *spill;
27522752
2753 // for debugging purposes, these are useful to call to inspect the instruction2753 // for debugging purposes, these are useful to call to inspect the instruction
2754 void dump();2754 void dump();
2755 void src();2755 void src();
2756};2756};
27572757
2758struct IrInstSrcDeclVar {2758struct Stage1ZirInstDeclVar {
2759 IrInstSrc base;2759 Stage1ZirInst base;
27602760
2761 ZigVar *var;2761 ZigVar *var;
2762 IrInstSrc *var_type;2762 Stage1ZirInst *var_type;
2763 IrInstSrc *align_value;2763 Stage1ZirInst *align_value;
2764 IrInstSrc *ptr;2764 Stage1ZirInst *ptr;
2765};2765};
27662766
2767struct IrInstGenDeclVar {2767struct Stage1AirInstDeclVar {
2768 IrInstGen base;2768 Stage1AirInst base;
27692769
2770 ZigVar *var;2770 ZigVar *var;
2771 IrInstGen *var_ptr;2771 Stage1AirInst *var_ptr;
2772};2772};
27732773
2774struct IrInstSrcCondBr {2774struct Stage1ZirInstCondBr {
2775 IrInstSrc base;2775 Stage1ZirInst base;
27762776
2777 IrInstSrc *condition;2777 Stage1ZirInst *condition;
2778 Stage1ZirBasicBlock *then_block;2778 Stage1ZirBasicBlock *then_block;
2779 Stage1ZirBasicBlock *else_block;2779 Stage1ZirBasicBlock *else_block;
2780 IrInstSrc *is_comptime;2780 Stage1ZirInst *is_comptime;
2781 ResultLoc *result_loc;2781 ResultLoc *result_loc;
2782};2782};
27832783
2784struct IrInstGenCondBr {2784struct Stage1AirInstCondBr {
2785 IrInstGen base;2785 Stage1AirInst base;
27862786
2787 IrInstGen *condition;2787 Stage1AirInst *condition;
2788 IrBasicBlockGen *then_block;2788 Stage1AirBasicBlock *then_block;
2789 IrBasicBlockGen *else_block;2789 Stage1AirBasicBlock *else_block;
2790};2790};
27912791
2792struct IrInstSrcBr {2792struct Stage1ZirInstBr {
2793 IrInstSrc base;2793 Stage1ZirInst base;
27942794
2795 Stage1ZirBasicBlock *dest_block;2795 Stage1ZirBasicBlock *dest_block;
2796 IrInstSrc *is_comptime;2796 Stage1ZirInst *is_comptime;
2797};2797};
27982798
2799struct IrInstGenBr {2799struct Stage1AirInstBr {
2800 IrInstGen base;2800 Stage1AirInst base;
28012801
2802 IrBasicBlockGen *dest_block;2802 Stage1AirBasicBlock *dest_block;
2803};2803};
28042804
2805struct IrInstSrcSwitchBrCase {2805struct Stage1ZirInstSwitchBrCase {
2806 IrInstSrc *value;2806 Stage1ZirInst *value;
2807 Stage1ZirBasicBlock *block;2807 Stage1ZirBasicBlock *block;
2808};2808};
28092809
2810struct IrInstSrcSwitchBr {2810struct Stage1ZirInstSwitchBr {
2811 IrInstSrc base;2811 Stage1ZirInst base;
28122812
2813 IrInstSrc *target_value;2813 Stage1ZirInst *target_value;
2814 Stage1ZirBasicBlock *else_block;2814 Stage1ZirBasicBlock *else_block;
2815 size_t case_count;2815 size_t case_count;
2816 IrInstSrcSwitchBrCase *cases;2816 Stage1ZirInstSwitchBrCase *cases;
2817 IrInstSrc *is_comptime;2817 Stage1ZirInst *is_comptime;
2818 IrInstSrc *switch_prongs_void;2818 Stage1ZirInst *switch_prongs_void;
2819};2819};
28202820
2821struct IrInstGenSwitchBrCase {2821struct Stage1AirInstSwitchBrCase {
2822 IrInstGen *value;2822 Stage1AirInst *value;
2823 IrBasicBlockGen *block;2823 Stage1AirBasicBlock *block;
2824};2824};
28252825
2826struct IrInstGenSwitchBr {2826struct Stage1AirInstSwitchBr {
2827 IrInstGen base;2827 Stage1AirInst base;
28282828
2829 IrInstGen *target_value;2829 Stage1AirInst *target_value;
2830 IrBasicBlockGen *else_block;2830 Stage1AirBasicBlock *else_block;
2831 size_t case_count;2831 size_t case_count;
2832 IrInstGenSwitchBrCase *cases;2832 Stage1AirInstSwitchBrCase *cases;
2833};2833};
28342834
2835struct IrInstSrcSwitchVar {2835struct Stage1ZirInstSwitchVar {
2836 IrInstSrc base;2836 Stage1ZirInst base;
28372837
2838 IrInstSrc *target_value_ptr;2838 Stage1ZirInst *target_value_ptr;
2839 IrInstSrc **prongs_ptr;2839 Stage1ZirInst **prongs_ptr;
2840 size_t prongs_len;2840 size_t prongs_len;
2841};2841};
28422842
2843struct IrInstSrcSwitchElseVar {2843struct Stage1ZirInstSwitchElseVar {
2844 IrInstSrc base;2844 Stage1ZirInst base;
28452845
2846 IrInstSrc *target_value_ptr;2846 Stage1ZirInst *target_value_ptr;
2847 IrInstSrcSwitchBr *switch_br;2847 Stage1ZirInstSwitchBr *switch_br;
2848};2848};
28492849
2850struct IrInstSrcSwitchTarget {2850struct Stage1ZirInstSwitchTarget {
2851 IrInstSrc base;2851 Stage1ZirInst base;
28522852
2853 IrInstSrc *target_value_ptr;2853 Stage1ZirInst *target_value_ptr;
2854};2854};
28552855
2856struct IrInstSrcPhi {2856struct Stage1ZirInstPhi {
2857 IrInstSrc base;2857 Stage1ZirInst base;
28582858
2859 size_t incoming_count;2859 size_t incoming_count;
2860 Stage1ZirBasicBlock **incoming_blocks;2860 Stage1ZirBasicBlock **incoming_blocks;
2861 IrInstSrc **incoming_values;2861 Stage1ZirInst **incoming_values;
2862 ResultLocPeerParent *peer_parent;2862 ResultLocPeerParent *peer_parent;
2863};2863};
28642864
2865struct IrInstGenPhi {2865struct Stage1AirInstPhi {
2866 IrInstGen base;2866 Stage1AirInst base;
28672867
2868 size_t incoming_count;2868 size_t incoming_count;
2869 IrBasicBlockGen **incoming_blocks;2869 Stage1AirBasicBlock **incoming_blocks;
2870 IrInstGen **incoming_values;2870 Stage1AirInst **incoming_values;
2871};2871};
28722872
2873enum IrUnOp {2873enum IrUnOp {
...@@ -2879,23 +2879,23 @@ enum IrUnOp {...@@ -2879,23 +2879,23 @@ enum IrUnOp {
2879 IrUnOpOptional,2879 IrUnOpOptional,
2880};2880};
28812881
2882struct IrInstSrcUnOp {2882struct Stage1ZirInstUnOp {
2883 IrInstSrc base;2883 Stage1ZirInst base;
28842884
2885 IrUnOp op_id;2885 IrUnOp op_id;
2886 LVal lval;2886 LVal lval;
2887 IrInstSrc *value;2887 Stage1ZirInst *value;
2888 ResultLoc *result_loc;2888 ResultLoc *result_loc;
2889};2889};
28902890
2891struct IrInstGenBinaryNot {2891struct Stage1AirInstBinaryNot {
2892 IrInstGen base;2892 Stage1AirInst base;
2893 IrInstGen *operand;2893 Stage1AirInst *operand;
2894};2894};
28952895
2896struct IrInstGenNegation {2896struct Stage1AirInstNegation {
2897 IrInstGen base;2897 Stage1AirInst base;
2898 IrInstGen *operand;2898 Stage1AirInst *operand;
2899 bool wrapping;2899 bool wrapping;
2900};2900};
29012901
...@@ -2933,122 +2933,122 @@ enum IrBinOp {...@@ -2933,122 +2933,122 @@ enum IrBinOp {
2933 IrBinOpArrayMult,2933 IrBinOpArrayMult,
2934};2934};
29352935
2936struct IrInstSrcBinOp {2936struct Stage1ZirInstBinOp {
2937 IrInstSrc base;2937 Stage1ZirInst base;
29382938
2939 IrInstSrc *op1;2939 Stage1ZirInst *op1;
2940 IrInstSrc *op2;2940 Stage1ZirInst *op2;
2941 IrBinOp op_id;2941 IrBinOp op_id;
2942 bool safety_check_on;2942 bool safety_check_on;
2943};2943};
29442944
2945struct IrInstGenBinOp {2945struct Stage1AirInstBinOp {
2946 IrInstGen base;2946 Stage1AirInst base;
29472947
2948 IrInstGen *op1;2948 Stage1AirInst *op1;
2949 IrInstGen *op2;2949 Stage1AirInst *op2;
2950 IrBinOp op_id;2950 IrBinOp op_id;
2951 bool safety_check_on;2951 bool safety_check_on;
2952};2952};
29532953
2954struct IrInstSrcMergeErrSets {2954struct Stage1ZirInstMergeErrSets {
2955 IrInstSrc base;2955 Stage1ZirInst base;
29562956
2957 IrInstSrc *op1;2957 Stage1ZirInst *op1;
2958 IrInstSrc *op2;2958 Stage1ZirInst *op2;
2959 Buf *type_name;2959 Buf *type_name;
2960};2960};
29612961
2962struct IrInstSrcLoadPtr {2962struct Stage1ZirInstLoadPtr {
2963 IrInstSrc base;2963 Stage1ZirInst base;
29642964
2965 IrInstSrc *ptr;2965 Stage1ZirInst *ptr;
2966};2966};
29672967
2968struct IrInstGenLoadPtr {2968struct Stage1AirInstLoadPtr {
2969 IrInstGen base;2969 Stage1AirInst base;
29702970
2971 IrInstGen *ptr;2971 Stage1AirInst *ptr;
2972 IrInstGen *result_loc;2972 Stage1AirInst *result_loc;
2973};2973};
29742974
2975struct IrInstSrcStorePtr {2975struct Stage1ZirInstStorePtr {
2976 IrInstSrc base;2976 Stage1ZirInst base;
29772977
2978 IrInstSrc *ptr;2978 Stage1ZirInst *ptr;
2979 IrInstSrc *value;2979 Stage1ZirInst *value;
29802980
2981 bool allow_write_through_const;2981 bool allow_write_through_const;
2982};2982};
29832983
2984struct IrInstGenStorePtr {2984struct Stage1AirInstStorePtr {
2985 IrInstGen base;2985 Stage1AirInst base;
29862986
2987 IrInstGen *ptr;2987 Stage1AirInst *ptr;
2988 IrInstGen *value;2988 Stage1AirInst *value;
2989};2989};
29902990
2991struct IrInstGenVectorStoreElem {2991struct Stage1AirInstVectorStoreElem {
2992 IrInstGen base;2992 Stage1AirInst base;
29932993
2994 IrInstGen *vector_ptr;2994 Stage1AirInst *vector_ptr;
2995 IrInstGen *index;2995 Stage1AirInst *index;
2996 IrInstGen *value;2996 Stage1AirInst *value;
2997};2997};
29982998
2999struct IrInstSrcFieldPtr {2999struct Stage1ZirInstFieldPtr {
3000 IrInstSrc base;3000 Stage1ZirInst base;
30013001
3002 IrInstSrc *container_ptr;3002 Stage1ZirInst *container_ptr;
3003 Buf *field_name_buffer;3003 Buf *field_name_buffer;
3004 IrInstSrc *field_name_expr;3004 Stage1ZirInst *field_name_expr;
3005 bool initializing;3005 bool initializing;
3006};3006};
30073007
3008struct IrInstGenStructFieldPtr {3008struct Stage1AirInstStructFieldPtr {
3009 IrInstGen base;3009 Stage1AirInst base;
30103010
3011 IrInstGen *struct_ptr;3011 Stage1AirInst *struct_ptr;
3012 TypeStructField *field;3012 TypeStructField *field;
3013 bool is_const;3013 bool is_const;
3014};3014};
30153015
3016struct IrInstGenUnionFieldPtr {3016struct Stage1AirInstUnionFieldPtr {
3017 IrInstGen base;3017 Stage1AirInst base;
30183018
3019 IrInstGen *union_ptr;3019 Stage1AirInst *union_ptr;
3020 TypeUnionField *field;3020 TypeUnionField *field;
3021 bool safety_check_on;3021 bool safety_check_on;
3022 bool initializing;3022 bool initializing;
3023};3023};
30243024
3025struct IrInstSrcElemPtr {3025struct Stage1ZirInstElemPtr {
3026 IrInstSrc base;3026 Stage1ZirInst base;
30273027
3028 IrInstSrc *array_ptr;3028 Stage1ZirInst *array_ptr;
3029 IrInstSrc *elem_index;3029 Stage1ZirInst *elem_index;
3030 AstNode *init_array_type_source_node;3030 AstNode *init_array_type_source_node;
3031 PtrLen ptr_len;3031 PtrLen ptr_len;
3032 bool safety_check_on;3032 bool safety_check_on;
3033};3033};
30343034
3035struct IrInstGenElemPtr {3035struct Stage1AirInstElemPtr {
3036 IrInstGen base;3036 Stage1AirInst base;
30373037
3038 IrInstGen *array_ptr;3038 Stage1AirInst *array_ptr;
3039 IrInstGen *elem_index;3039 Stage1AirInst *elem_index;
3040 bool safety_check_on;3040 bool safety_check_on;
3041};3041};
30423042
3043struct IrInstSrcVarPtr {3043struct Stage1ZirInstVarPtr {
3044 IrInstSrc base;3044 Stage1ZirInst base;
30453045
3046 ZigVar *var;3046 ZigVar *var;
3047 ScopeFnDef *crossed_fndef_scope;3047 ScopeFnDef *crossed_fndef_scope;
3048};3048};
30493049
3050struct IrInstGenVarPtr {3050struct Stage1AirInstVarPtr {
3051 IrInstGen base;3051 Stage1AirInst base;
30523052
3053 ZigVar *var;3053 ZigVar *var;
3054};3054};
...@@ -3056,21 +3056,21 @@ struct IrInstGenVarPtr {...@@ -3056,21 +3056,21 @@ struct IrInstGenVarPtr {
3056// For functions that have a return type for which handle_is_ptr is true, a3056// For functions that have a return type for which handle_is_ptr is true, a
3057// result location pointer is the secret first parameter ("sret"). This3057// result location pointer is the secret first parameter ("sret"). This
3058// instruction returns that pointer.3058// instruction returns that pointer.
3059struct IrInstGenReturnPtr {3059struct Stage1AirInstReturnPtr {
3060 IrInstGen base;3060 Stage1AirInst base;
3061};3061};
30623062
3063struct IrInstSrcCall {3063struct Stage1ZirInstCall {
3064 IrInstSrc base;3064 Stage1ZirInst base;
30653065
3066 IrInstSrc *fn_ref;3066 Stage1ZirInst *fn_ref;
3067 ZigFn *fn_entry;3067 ZigFn *fn_entry;
3068 size_t arg_count;3068 size_t arg_count;
3069 IrInstSrc **args;3069 Stage1ZirInst **args;
3070 IrInstSrc *ret_ptr;3070 Stage1ZirInst *ret_ptr;
3071 ResultLoc *result_loc;3071 ResultLoc *result_loc;
30723072
3073 IrInstSrc *new_stack;3073 Stage1ZirInst *new_stack;
30743074
3075 CallModifier modifier;3075 CallModifier modifier;
3076 bool is_async_call_builtin;3076 bool is_async_call_builtin;
...@@ -3078,12 +3078,12 @@ struct IrInstSrcCall {...@@ -3078,12 +3078,12 @@ struct IrInstSrcCall {
30783078
3079// This is a pass1 instruction, used by @call when the args node is3079// This is a pass1 instruction, used by @call when the args node is
3080// a tuple or struct literal.3080// a tuple or struct literal.
3081struct IrInstSrcCallArgs {3081struct Stage1ZirInstCallArgs {
3082 IrInstSrc base;3082 Stage1ZirInst base;
30833083
3084 IrInstSrc *options;3084 Stage1ZirInst *options;
3085 IrInstSrc *fn_ref;3085 Stage1ZirInst *fn_ref;
3086 IrInstSrc **args_ptr;3086 Stage1ZirInst **args_ptr;
3087 size_t args_len;3087 size_t args_len;
3088 ResultLoc *result_loc;3088 ResultLoc *result_loc;
3089};3089};
...@@ -3091,68 +3091,68 @@ struct IrInstSrcCallArgs {...@@ -3091,68 +3091,68 @@ struct IrInstSrcCallArgs {
3091// This is a pass1 instruction, used by @call, when the args node3091// This is a pass1 instruction, used by @call, when the args node
3092// is not a literal.3092// is not a literal.
3093// `args` is expected to be either a struct or a tuple.3093// `args` is expected to be either a struct or a tuple.
3094struct IrInstSrcCallExtra {3094struct Stage1ZirInstCallExtra {
3095 IrInstSrc base;3095 Stage1ZirInst base;
30963096
3097 IrInstSrc *options;3097 Stage1ZirInst *options;
3098 IrInstSrc *fn_ref;3098 Stage1ZirInst *fn_ref;
3099 IrInstSrc *args;3099 Stage1ZirInst *args;
3100 ResultLoc *result_loc;3100 ResultLoc *result_loc;
3101};3101};
31023102
3103// This is a pass1 instruction, used by @asyncCall, when the args node3103// This is a pass1 instruction, used by @asyncCall, when the args node
3104// is not a literal.3104// is not a literal.
3105// `args` is expected to be either a struct or a tuple.3105// `args` is expected to be either a struct or a tuple.
3106struct IrInstSrcAsyncCallExtra {3106struct Stage1ZirInstAsyncCallExtra {
3107 IrInstSrc base;3107 Stage1ZirInst base;
31083108
3109 CallModifier modifier;3109 CallModifier modifier;
3110 IrInstSrc *fn_ref;3110 Stage1ZirInst *fn_ref;
3111 IrInstSrc *ret_ptr;3111 Stage1ZirInst *ret_ptr;
3112 IrInstSrc *new_stack;3112 Stage1ZirInst *new_stack;
3113 IrInstSrc *args;3113 Stage1ZirInst *args;
3114 ResultLoc *result_loc;3114 ResultLoc *result_loc;
3115};3115};
31163116
3117struct IrInstGenCall {3117struct Stage1AirInstCall {
3118 IrInstGen base;3118 Stage1AirInst base;
31193119
3120 IrInstGen *fn_ref;3120 Stage1AirInst *fn_ref;
3121 ZigFn *fn_entry;3121 ZigFn *fn_entry;
3122 size_t arg_count;3122 size_t arg_count;
3123 IrInstGen **args;3123 Stage1AirInst **args;
3124 IrInstGen *result_loc;3124 Stage1AirInst *result_loc;
3125 IrInstGen *frame_result_loc;3125 Stage1AirInst *frame_result_loc;
3126 IrInstGen *new_stack;3126 Stage1AirInst *new_stack;
31273127
3128 CallModifier modifier;3128 CallModifier modifier;
31293129
3130 bool is_async_call_builtin;3130 bool is_async_call_builtin;
3131};3131};
31323132
3133struct IrInstSrcConst {3133struct Stage1ZirInstConst {
3134 IrInstSrc base;3134 Stage1ZirInst base;
31353135
3136 ZigValue *value;3136 ZigValue *value;
3137};3137};
31383138
3139struct IrInstGenConst {3139struct Stage1AirInstConst {
3140 IrInstGen base;3140 Stage1AirInst base;
3141};3141};
31423142
3143struct IrInstSrcReturn {3143struct Stage1ZirInstReturn {
3144 IrInstSrc base;3144 Stage1ZirInst base;
31453145
3146 IrInstSrc *operand;3146 Stage1ZirInst *operand;
3147};3147};
31483148
3149// When an IrExecutable is not in a function, a return instruction means that3149// When an IrExecutable is not in a function, a return instruction means that
3150// the expression returns with that value, even though a return statement from3150// the expression returns with that value, even though a return statement from
3151// an AST perspective is invalid.3151// an AST perspective is invalid.
3152struct IrInstGenReturn {3152struct Stage1AirInstReturn {
3153 IrInstGen base;3153 Stage1AirInst base;
31543154
3155 IrInstGen *operand;3155 Stage1AirInst *operand;
3156};3156};
31573157
3158enum CastOp {3158enum CastOp {
...@@ -3167,94 +3167,94 @@ enum CastOp {...@@ -3167,94 +3167,94 @@ enum CastOp {
3167};3167};
31683168
3169// TODO get rid of this instruction, replace with instructions for each op code3169// TODO get rid of this instruction, replace with instructions for each op code
3170struct IrInstGenCast {3170struct Stage1AirInstCast {
3171 IrInstGen base;3171 Stage1AirInst base;
31723172
3173 IrInstGen *value;3173 Stage1AirInst *value;
3174 CastOp cast_op;3174 CastOp cast_op;
3175};3175};
31763176
3177struct IrInstSrcContainerInitList {3177struct Stage1ZirInstContainerInitList {
3178 IrInstSrc base;3178 Stage1ZirInst base;
31793179
3180 IrInstSrc *elem_type;3180 Stage1ZirInst *elem_type;
3181 size_t item_count;3181 size_t item_count;
3182 IrInstSrc **elem_result_loc_list;3182 Stage1ZirInst **elem_result_loc_list;
3183 IrInstSrc *result_loc;3183 Stage1ZirInst *result_loc;
3184 AstNode *init_array_type_source_node;3184 AstNode *init_array_type_source_node;
3185};3185};
31863186
3187struct IrInstSrcContainerInitFieldsField {3187struct Stage1ZirInstContainerInitFieldsField {
3188 Buf *name;3188 Buf *name;
3189 AstNode *source_node;3189 AstNode *source_node;
3190 IrInstSrc *result_loc;3190 Stage1ZirInst *result_loc;
3191};3191};
31923192
3193struct IrInstSrcContainerInitFields {3193struct Stage1ZirInstContainerInitFields {
3194 IrInstSrc base;3194 Stage1ZirInst base;
31953195
3196 size_t field_count;3196 size_t field_count;
3197 IrInstSrcContainerInitFieldsField *fields;3197 Stage1ZirInstContainerInitFieldsField *fields;
3198 IrInstSrc *result_loc;3198 Stage1ZirInst *result_loc;
3199};3199};
32003200
3201struct IrInstSrcUnreachable {3201struct Stage1ZirInstUnreachable {
3202 IrInstSrc base;3202 Stage1ZirInst base;
3203};3203};
32043204
3205struct IrInstGenUnreachable {3205struct Stage1AirInstUnreachable {
3206 IrInstGen base;3206 Stage1AirInst base;
3207};3207};
32083208
3209struct IrInstSrcTypeOf {3209struct Stage1ZirInstTypeOf {
3210 IrInstSrc base;3210 Stage1ZirInst base;
32113211
3212 union {3212 union {
3213 IrInstSrc *scalar; // value_count == 13213 Stage1ZirInst *scalar; // value_count == 1
3214 IrInstSrc **list; // value_count > 13214 Stage1ZirInst **list; // value_count > 1
3215 } value;3215 } value;
3216 size_t value_count;3216 size_t value_count;
3217};3217};
32183218
3219struct IrInstSrcSetCold {3219struct Stage1ZirInstSetCold {
3220 IrInstSrc base;3220 Stage1ZirInst base;
32213221
3222 IrInstSrc *is_cold;3222 Stage1ZirInst *is_cold;
3223};3223};
32243224
3225struct IrInstSrcSetRuntimeSafety {3225struct Stage1ZirInstSetRuntimeSafety {
3226 IrInstSrc base;3226 Stage1ZirInst base;
32273227
3228 IrInstSrc *safety_on;3228 Stage1ZirInst *safety_on;
3229};3229};
32303230
3231struct IrInstSrcSetFloatMode {3231struct Stage1ZirInstSetFloatMode {
3232 IrInstSrc base;3232 Stage1ZirInst base;
32333233
3234 IrInstSrc *scope_value;3234 Stage1ZirInst *scope_value;
3235 IrInstSrc *mode_value;3235 Stage1ZirInst *mode_value;
3236};3236};
32373237
3238struct IrInstSrcArrayType {3238struct Stage1ZirInstArrayType {
3239 IrInstSrc base;3239 Stage1ZirInst base;
32403240
3241 IrInstSrc *size;3241 Stage1ZirInst *size;
3242 IrInstSrc *sentinel;3242 Stage1ZirInst *sentinel;
3243 IrInstSrc *child_type;3243 Stage1ZirInst *child_type;
3244};3244};
32453245
3246struct IrInstSrcPtrTypeSimple {3246struct Stage1ZirInstPtrTypeSimple {
3247 IrInstSrc base;3247 Stage1ZirInst base;
32483248
3249 IrInstSrc *child_type;3249 Stage1ZirInst *child_type;
3250};3250};
32513251
3252struct IrInstSrcPtrType {3252struct Stage1ZirInstPtrType {
3253 IrInstSrc base;3253 Stage1ZirInst base;
32543254
3255 IrInstSrc *sentinel;3255 Stage1ZirInst *sentinel;
3256 IrInstSrc *align_value;3256 Stage1ZirInst *align_value;
3257 IrInstSrc *child_type;3257 Stage1ZirInst *child_type;
3258 uint32_t bit_offset_start;3258 uint32_t bit_offset_start;
3259 uint32_t host_int_bytes;3259 uint32_t host_int_bytes;
3260 PtrLen ptr_len;3260 PtrLen ptr_len;
...@@ -3263,459 +3263,459 @@ struct IrInstSrcPtrType {...@@ -3263,459 +3263,459 @@ struct IrInstSrcPtrType {
3263 bool is_allow_zero;3263 bool is_allow_zero;
3264};3264};
32653265
3266struct IrInstSrcAnyFrameType {3266struct Stage1ZirInstAnyFrameType {
3267 IrInstSrc base;3267 Stage1ZirInst base;
32683268
3269 IrInstSrc *payload_type;3269 Stage1ZirInst *payload_type;
3270};3270};
32713271
3272struct IrInstSrcSliceType {3272struct Stage1ZirInstSliceType {
3273 IrInstSrc base;3273 Stage1ZirInst base;
32743274
3275 IrInstSrc *sentinel;3275 Stage1ZirInst *sentinel;
3276 IrInstSrc *align_value;3276 Stage1ZirInst *align_value;
3277 IrInstSrc *child_type;3277 Stage1ZirInst *child_type;
3278 bool is_const;3278 bool is_const;
3279 bool is_volatile;3279 bool is_volatile;
3280 bool is_allow_zero;3280 bool is_allow_zero;
3281};3281};
32823282
3283struct IrInstSrcAsm {3283struct Stage1ZirInstAsm {
3284 IrInstSrc base;3284 Stage1ZirInst base;
32853285
3286 IrInstSrc *asm_template;3286 Stage1ZirInst *asm_template;
3287 IrInstSrc **input_list;3287 Stage1ZirInst **input_list;
3288 IrInstSrc **output_types;3288 Stage1ZirInst **output_types;
3289 ZigVar **output_vars;3289 ZigVar **output_vars;
3290 size_t return_count;3290 size_t return_count;
3291 bool has_side_effects;3291 bool has_side_effects;
3292 bool is_global;3292 bool is_global;
3293};3293};
32943294
3295struct IrInstGenAsm {3295struct Stage1AirInstAsm {
3296 IrInstGen base;3296 Stage1AirInst base;
32973297
3298 Buf *asm_template;3298 Buf *asm_template;
3299 AsmToken *token_list;3299 AsmToken *token_list;
3300 size_t token_list_len;3300 size_t token_list_len;
3301 IrInstGen **input_list;3301 Stage1AirInst **input_list;
3302 IrInstGen **output_types;3302 Stage1AirInst **output_types;
3303 ZigVar **output_vars;3303 ZigVar **output_vars;
3304 size_t return_count;3304 size_t return_count;
3305 bool has_side_effects;3305 bool has_side_effects;
3306};3306};
33073307
3308struct IrInstSrcSizeOf {3308struct Stage1ZirInstSizeOf {
3309 IrInstSrc base;3309 Stage1ZirInst base;
33103310
3311 IrInstSrc *type_value;3311 Stage1ZirInst *type_value;
3312 bool bit_size;3312 bool bit_size;
3313};3313};
33143314
3315// returns true if nonnull, returns false if null3315// returns true if nonnull, returns false if null
3316struct IrInstSrcTestNonNull {3316struct Stage1ZirInstTestNonNull {
3317 IrInstSrc base;3317 Stage1ZirInst base;
33183318
3319 IrInstSrc *value;3319 Stage1ZirInst *value;
3320};3320};
33213321
3322struct IrInstGenTestNonNull {3322struct Stage1AirInstTestNonNull {
3323 IrInstGen base;3323 Stage1AirInst base;
33243324
3325 IrInstGen *value;3325 Stage1AirInst *value;
3326};3326};
33273327
3328// Takes a pointer to an optional value, returns a pointer3328// Takes a pointer to an optional value, returns a pointer
3329// to the payload.3329// to the payload.
3330struct IrInstSrcOptionalUnwrapPtr {3330struct Stage1ZirInstOptionalUnwrapPtr {
3331 IrInstSrc base;3331 Stage1ZirInst base;
33323332
3333 IrInstSrc *base_ptr;3333 Stage1ZirInst *base_ptr;
3334 bool safety_check_on;3334 bool safety_check_on;
3335};3335};
33363336
3337struct IrInstGenOptionalUnwrapPtr {3337struct Stage1AirInstOptionalUnwrapPtr {
3338 IrInstGen base;3338 Stage1AirInst base;
33393339
3340 IrInstGen *base_ptr;3340 Stage1AirInst *base_ptr;
3341 bool safety_check_on;3341 bool safety_check_on;
3342 bool initializing;3342 bool initializing;
3343};3343};
33443344
3345struct IrInstSrcCtz {3345struct Stage1ZirInstCtz {
3346 IrInstSrc base;3346 Stage1ZirInst base;
33473347
3348 IrInstSrc *type;3348 Stage1ZirInst *type;
3349 IrInstSrc *op;3349 Stage1ZirInst *op;
3350};3350};
33513351
3352struct IrInstGenCtz {3352struct Stage1AirInstCtz {
3353 IrInstGen base;3353 Stage1AirInst base;
33543354
3355 IrInstGen *op;3355 Stage1AirInst *op;
3356};3356};
33573357
3358struct IrInstSrcClz {3358struct Stage1ZirInstClz {
3359 IrInstSrc base;3359 Stage1ZirInst base;
33603360
3361 IrInstSrc *type;3361 Stage1ZirInst *type;
3362 IrInstSrc *op;3362 Stage1ZirInst *op;
3363};3363};
33643364
3365struct IrInstGenClz {3365struct Stage1AirInstClz {
3366 IrInstGen base;3366 Stage1AirInst base;
33673367
3368 IrInstGen *op;3368 Stage1AirInst *op;
3369};3369};
33703370
3371struct IrInstSrcPopCount {3371struct Stage1ZirInstPopCount {
3372 IrInstSrc base;3372 Stage1ZirInst base;
33733373
3374 IrInstSrc *type;3374 Stage1ZirInst *type;
3375 IrInstSrc *op;3375 Stage1ZirInst *op;
3376};3376};
33773377
3378struct IrInstGenPopCount {3378struct Stage1AirInstPopCount {
3379 IrInstGen base;3379 Stage1AirInst base;
33803380
3381 IrInstGen *op;3381 Stage1AirInst *op;
3382};3382};
33833383
3384struct IrInstGenUnionTag {3384struct Stage1AirInstUnionTag {
3385 IrInstGen base;3385 Stage1AirInst base;
33863386
3387 IrInstGen *value;3387 Stage1AirInst *value;
3388};3388};
33893389
3390struct IrInstSrcImport {3390struct Stage1ZirInstImport {
3391 IrInstSrc base;3391 Stage1ZirInst base;
33923392
3393 IrInstSrc *name;3393 Stage1ZirInst *name;
3394};3394};
33953395
3396struct IrInstSrcRef {3396struct Stage1ZirInstRef {
3397 IrInstSrc base;3397 Stage1ZirInst base;
33983398
3399 IrInstSrc *value;3399 Stage1ZirInst *value;
3400};3400};
34013401
3402struct IrInstGenRef {3402struct Stage1AirInstRef {
3403 IrInstGen base;3403 Stage1AirInst base;
34043404
3405 IrInstGen *operand;3405 Stage1AirInst *operand;
3406 IrInstGen *result_loc;3406 Stage1AirInst *result_loc;
3407};3407};
34083408
3409struct IrInstSrcCompileErr {3409struct Stage1ZirInstCompileErr {
3410 IrInstSrc base;3410 Stage1ZirInst base;
34113411
3412 IrInstSrc *msg;3412 Stage1ZirInst *msg;
3413};3413};
34143414
3415struct IrInstSrcCompileLog {3415struct Stage1ZirInstCompileLog {
3416 IrInstSrc base;3416 Stage1ZirInst base;
34173417
3418 size_t msg_count;3418 size_t msg_count;
3419 IrInstSrc **msg_list;3419 Stage1ZirInst **msg_list;
3420};3420};
34213421
3422struct IrInstSrcErrName {3422struct Stage1ZirInstErrName {
3423 IrInstSrc base;3423 Stage1ZirInst base;
34243424
3425 IrInstSrc *value;3425 Stage1ZirInst *value;
3426};3426};
34273427
3428struct IrInstGenErrName {3428struct Stage1AirInstErrName {
3429 IrInstGen base;3429 Stage1AirInst base;
34303430
3431 IrInstGen *value;3431 Stage1AirInst *value;
3432};3432};
34333433
3434struct IrInstSrcCImport {3434struct Stage1ZirInstCImport {
3435 IrInstSrc base;3435 Stage1ZirInst base;
3436};3436};
34373437
3438struct IrInstSrcCInclude {3438struct Stage1ZirInstCInclude {
3439 IrInstSrc base;3439 Stage1ZirInst base;
34403440
3441 IrInstSrc *name;3441 Stage1ZirInst *name;
3442};3442};
34433443
3444struct IrInstSrcCDefine {3444struct Stage1ZirInstCDefine {
3445 IrInstSrc base;3445 Stage1ZirInst base;
34463446
3447 IrInstSrc *name;3447 Stage1ZirInst *name;
3448 IrInstSrc *value;3448 Stage1ZirInst *value;
3449};3449};
34503450
3451struct IrInstSrcCUndef {3451struct Stage1ZirInstCUndef {
3452 IrInstSrc base;3452 Stage1ZirInst base;
34533453
3454 IrInstSrc *name;3454 Stage1ZirInst *name;
3455};3455};
34563456
3457struct IrInstSrcEmbedFile {3457struct Stage1ZirInstEmbedFile {
3458 IrInstSrc base;3458 Stage1ZirInst base;
34593459
3460 IrInstSrc *name;3460 Stage1ZirInst *name;
3461};3461};
34623462
3463struct IrInstSrcCmpxchg {3463struct Stage1ZirInstCmpxchg {
3464 IrInstSrc base;3464 Stage1ZirInst base;
34653465
3466 bool is_weak;3466 bool is_weak;
3467 IrInstSrc *type_value;3467 Stage1ZirInst *type_value;
3468 IrInstSrc *ptr;3468 Stage1ZirInst *ptr;
3469 IrInstSrc *cmp_value;3469 Stage1ZirInst *cmp_value;
3470 IrInstSrc *new_value;3470 Stage1ZirInst *new_value;
3471 IrInstSrc *success_order_value;3471 Stage1ZirInst *success_order_value;
3472 IrInstSrc *failure_order_value;3472 Stage1ZirInst *failure_order_value;
3473 ResultLoc *result_loc;3473 ResultLoc *result_loc;
3474};3474};
34753475
3476struct IrInstGenCmpxchg {3476struct Stage1AirInstCmpxchg {
3477 IrInstGen base;3477 Stage1AirInst base;
34783478
3479 AtomicOrder success_order;3479 AtomicOrder success_order;
3480 AtomicOrder failure_order;3480 AtomicOrder failure_order;
3481 IrInstGen *ptr;3481 Stage1AirInst *ptr;
3482 IrInstGen *cmp_value;3482 Stage1AirInst *cmp_value;
3483 IrInstGen *new_value;3483 Stage1AirInst *new_value;
3484 IrInstGen *result_loc;3484 Stage1AirInst *result_loc;
3485 bool is_weak;3485 bool is_weak;
3486};3486};
34873487
3488struct IrInstSrcFence {3488struct Stage1ZirInstFence {
3489 IrInstSrc base;3489 Stage1ZirInst base;
34903490
3491 IrInstSrc *order;3491 Stage1ZirInst *order;
3492};3492};
34933493
3494struct IrInstGenFence {3494struct Stage1AirInstFence {
3495 IrInstGen base;3495 Stage1AirInst base;
34963496
3497 AtomicOrder order;3497 AtomicOrder order;
3498};3498};
34993499
3500struct IrInstSrcReduce {3500struct Stage1ZirInstReduce {
3501 IrInstSrc base;3501 Stage1ZirInst base;
35023502
3503 IrInstSrc *op;3503 Stage1ZirInst *op;
3504 IrInstSrc *value;3504 Stage1ZirInst *value;
3505};3505};
35063506
3507struct IrInstGenReduce {3507struct Stage1AirInstReduce {
3508 IrInstGen base;3508 Stage1AirInst base;
35093509
3510 ReduceOp op;3510 ReduceOp op;
3511 IrInstGen *value;3511 Stage1AirInst *value;
3512};3512};
35133513
3514struct IrInstSrcTruncate {3514struct Stage1ZirInstTruncate {
3515 IrInstSrc base;3515 Stage1ZirInst base;
35163516
3517 IrInstSrc *dest_type;3517 Stage1ZirInst *dest_type;
3518 IrInstSrc *target;3518 Stage1ZirInst *target;
3519};3519};
35203520
3521struct IrInstGenTruncate {3521struct Stage1AirInstTruncate {
3522 IrInstGen base;3522 Stage1AirInst base;
35233523
3524 IrInstGen *target;3524 Stage1AirInst *target;
3525};3525};
35263526
3527struct IrInstSrcIntCast {3527struct Stage1ZirInstIntCast {
3528 IrInstSrc base;3528 Stage1ZirInst base;
35293529
3530 IrInstSrc *dest_type;3530 Stage1ZirInst *dest_type;
3531 IrInstSrc *target;3531 Stage1ZirInst *target;
3532};3532};
35333533
3534struct IrInstSrcFloatCast {3534struct Stage1ZirInstFloatCast {
3535 IrInstSrc base;3535 Stage1ZirInst base;
35363536
3537 IrInstSrc *dest_type;3537 Stage1ZirInst *dest_type;
3538 IrInstSrc *target;3538 Stage1ZirInst *target;
3539};3539};
35403540
3541struct IrInstSrcErrSetCast {3541struct Stage1ZirInstErrSetCast {
3542 IrInstSrc base;3542 Stage1ZirInst base;
35433543
3544 IrInstSrc *dest_type;3544 Stage1ZirInst *dest_type;
3545 IrInstSrc *target;3545 Stage1ZirInst *target;
3546};3546};
35473547
3548struct IrInstSrcIntToFloat {3548struct Stage1ZirInstIntToFloat {
3549 IrInstSrc base;3549 Stage1ZirInst base;
35503550
3551 IrInstSrc *dest_type;3551 Stage1ZirInst *dest_type;
3552 IrInstSrc *target;3552 Stage1ZirInst *target;
3553};3553};
35543554
3555struct IrInstSrcFloatToInt {3555struct Stage1ZirInstFloatToInt {
3556 IrInstSrc base;3556 Stage1ZirInst base;
35573557
3558 IrInstSrc *dest_type;3558 Stage1ZirInst *dest_type;
3559 IrInstSrc *target;3559 Stage1ZirInst *target;
3560};3560};
35613561
3562struct IrInstSrcBoolToInt {3562struct Stage1ZirInstBoolToInt {
3563 IrInstSrc base;3563 Stage1ZirInst base;
35643564
3565 IrInstSrc *target;3565 Stage1ZirInst *target;
3566};3566};
35673567
3568struct IrInstSrcVectorType {3568struct Stage1ZirInstVectorType {
3569 IrInstSrc base;3569 Stage1ZirInst base;
35703570
3571 IrInstSrc *len;3571 Stage1ZirInst *len;
3572 IrInstSrc *elem_type;3572 Stage1ZirInst *elem_type;
3573};3573};
35743574
3575struct IrInstSrcBoolNot {3575struct Stage1ZirInstBoolNot {
3576 IrInstSrc base;3576 Stage1ZirInst base;
35773577
3578 IrInstSrc *value;3578 Stage1ZirInst *value;
3579};3579};
35803580
3581struct IrInstGenBoolNot {3581struct Stage1AirInstBoolNot {
3582 IrInstGen base;3582 Stage1AirInst base;
35833583
3584 IrInstGen *value;3584 Stage1AirInst *value;
3585};3585};
35863586
3587struct IrInstSrcMemset {3587struct Stage1ZirInstMemset {
3588 IrInstSrc base;3588 Stage1ZirInst base;
35893589
3590 IrInstSrc *dest_ptr;3590 Stage1ZirInst *dest_ptr;
3591 IrInstSrc *byte;3591 Stage1ZirInst *byte;
3592 IrInstSrc *count;3592 Stage1ZirInst *count;
3593};3593};
35943594
3595struct IrInstGenMemset {3595struct Stage1AirInstMemset {
3596 IrInstGen base;3596 Stage1AirInst base;
35973597
3598 IrInstGen *dest_ptr;3598 Stage1AirInst *dest_ptr;
3599 IrInstGen *byte;3599 Stage1AirInst *byte;
3600 IrInstGen *count;3600 Stage1AirInst *count;
3601};3601};
36023602
3603struct IrInstSrcMemcpy {3603struct Stage1ZirInstMemcpy {
3604 IrInstSrc base;3604 Stage1ZirInst base;
36053605
3606 IrInstSrc *dest_ptr;3606 Stage1ZirInst *dest_ptr;
3607 IrInstSrc *src_ptr;3607 Stage1ZirInst *src_ptr;
3608 IrInstSrc *count;3608 Stage1ZirInst *count;
3609};3609};
36103610
3611struct IrInstGenMemcpy {3611struct Stage1AirInstMemcpy {
3612 IrInstGen base;3612 Stage1AirInst base;
36133613
3614 IrInstGen *dest_ptr;3614 Stage1AirInst *dest_ptr;
3615 IrInstGen *src_ptr;3615 Stage1AirInst *src_ptr;
3616 IrInstGen *count;3616 Stage1AirInst *count;
3617};3617};
36183618
3619struct IrInstSrcWasmMemorySize {3619struct Stage1ZirInstWasmMemorySize {
3620 IrInstSrc base;3620 Stage1ZirInst base;
36213621
3622 IrInstSrc *index;3622 Stage1ZirInst *index;
3623};3623};
36243624
3625struct IrInstGenWasmMemorySize {3625struct Stage1AirInstWasmMemorySize {
3626 IrInstGen base;3626 Stage1AirInst base;
36273627
3628 IrInstGen *index;3628 Stage1AirInst *index;
3629};3629};
36303630
3631struct IrInstSrcWasmMemoryGrow {3631struct Stage1ZirInstWasmMemoryGrow {
3632 IrInstSrc base;3632 Stage1ZirInst base;
36333633
3634 IrInstSrc *index;3634 Stage1ZirInst *index;
3635 IrInstSrc *delta;3635 Stage1ZirInst *delta;
3636};3636};
36373637
3638struct IrInstGenWasmMemoryGrow {3638struct Stage1AirInstWasmMemoryGrow {
3639 IrInstGen base;3639 Stage1AirInst base;
36403640
3641 IrInstGen *index;3641 Stage1AirInst *index;
3642 IrInstGen *delta;3642 Stage1AirInst *delta;
3643};3643};
36443644
3645struct IrInstSrcSrc {3645struct Stage1ZirInstSrc {
3646 IrInstSrc base;3646 Stage1ZirInst base;
3647};3647};
36483648
3649struct IrInstSrcSlice {3649struct Stage1ZirInstSlice {
3650 IrInstSrc base;3650 Stage1ZirInst base;
36513651
3652 IrInstSrc *ptr;3652 Stage1ZirInst *ptr;
3653 IrInstSrc *start;3653 Stage1ZirInst *start;
3654 IrInstSrc *end;3654 Stage1ZirInst *end;
3655 IrInstSrc *sentinel;3655 Stage1ZirInst *sentinel;
3656 ResultLoc *result_loc;3656 ResultLoc *result_loc;
3657 bool safety_check_on;3657 bool safety_check_on;
3658};3658};
36593659
3660struct IrInstGenSlice {3660struct Stage1AirInstSlice {
3661 IrInstGen base;3661 Stage1AirInst base;
36623662
3663 IrInstGen *ptr;3663 Stage1AirInst *ptr;
3664 IrInstGen *start;3664 Stage1AirInst *start;
3665 IrInstGen *end;3665 Stage1AirInst *end;
3666 IrInstGen *result_loc;3666 Stage1AirInst *result_loc;
3667 ZigValue *sentinel;3667 ZigValue *sentinel;
3668 bool safety_check_on;3668 bool safety_check_on;
3669};3669};
36703670
3671struct IrInstSrcBreakpoint {3671struct Stage1ZirInstBreakpoint {
3672 IrInstSrc base;3672 Stage1ZirInst base;
3673};3673};
36743674
3675struct IrInstGenBreakpoint {3675struct Stage1AirInstBreakpoint {
3676 IrInstGen base;3676 Stage1AirInst base;
3677};3677};
36783678
3679struct IrInstSrcReturnAddress {3679struct Stage1ZirInstReturnAddress {
3680 IrInstSrc base;3680 Stage1ZirInst base;
3681};3681};
36823682
3683struct IrInstGenReturnAddress {3683struct Stage1AirInstReturnAddress {
3684 IrInstGen base;3684 Stage1AirInst base;
3685};3685};
36863686
3687struct IrInstSrcFrameAddress {3687struct Stage1ZirInstFrameAddress {
3688 IrInstSrc base;3688 Stage1ZirInst base;
3689};3689};
36903690
3691struct IrInstGenFrameAddress {3691struct Stage1AirInstFrameAddress {
3692 IrInstGen base;3692 Stage1AirInst base;
3693};3693};
36943694
3695struct IrInstSrcFrameHandle {3695struct Stage1ZirInstFrameHandle {
3696 IrInstSrc base;3696 Stage1ZirInst base;
3697};3697};
36983698
3699struct IrInstGenFrameHandle {3699struct Stage1AirInstFrameHandle {
3700 IrInstGen base;3700 Stage1AirInst base;
3701};3701};
37023702
3703struct IrInstSrcFrameType {3703struct Stage1ZirInstFrameType {
3704 IrInstSrc base;3704 Stage1ZirInst base;
37053705
3706 IrInstSrc *fn;3706 Stage1ZirInst *fn;
3707};3707};
37083708
3709struct IrInstSrcFrameSize {3709struct Stage1ZirInstFrameSize {
3710 IrInstSrc base;3710 Stage1ZirInst base;
37113711
3712 IrInstSrc *fn;3712 Stage1ZirInst *fn;
3713};3713};
37143714
3715struct IrInstGenFrameSize {3715struct Stage1AirInstFrameSize {
3716 IrInstGen base;3716 Stage1AirInst base;
37173717
3718 IrInstGen *fn;3718 Stage1AirInst *fn;
3719};3719};
37203720
3721enum IrOverflowOp {3721enum IrOverflowOp {
...@@ -3725,397 +3725,397 @@ enum IrOverflowOp {...@@ -3725,397 +3725,397 @@ enum IrOverflowOp {
3725 IrOverflowOpShl,3725 IrOverflowOpShl,
3726};3726};
37273727
3728struct IrInstSrcOverflowOp {3728struct Stage1ZirInstOverflowOp {
3729 IrInstSrc base;3729 Stage1ZirInst base;
37303730
3731 IrOverflowOp op;3731 IrOverflowOp op;
3732 IrInstSrc *type_value;3732 Stage1ZirInst *type_value;
3733 IrInstSrc *op1;3733 Stage1ZirInst *op1;
3734 IrInstSrc *op2;3734 Stage1ZirInst *op2;
3735 IrInstSrc *result_ptr;3735 Stage1ZirInst *result_ptr;
3736};3736};
37373737
3738struct IrInstGenOverflowOp {3738struct Stage1AirInstOverflowOp {
3739 IrInstGen base;3739 Stage1AirInst base;
37403740
3741 IrOverflowOp op;3741 IrOverflowOp op;
3742 IrInstGen *op1;3742 Stage1AirInst *op1;
3743 IrInstGen *op2;3743 Stage1AirInst *op2;
3744 IrInstGen *result_ptr;3744 Stage1AirInst *result_ptr;
37453745
3746 // TODO can this field be removed?3746 // TODO can this field be removed?
3747 ZigType *result_ptr_type;3747 ZigType *result_ptr_type;
3748};3748};
37493749
3750struct IrInstSrcMulAdd {3750struct Stage1ZirInstMulAdd {
3751 IrInstSrc base;3751 Stage1ZirInst base;
37523752
3753 IrInstSrc *type_value;3753 Stage1ZirInst *type_value;
3754 IrInstSrc *op1;3754 Stage1ZirInst *op1;
3755 IrInstSrc *op2;3755 Stage1ZirInst *op2;
3756 IrInstSrc *op3;3756 Stage1ZirInst *op3;
3757};3757};
37583758
3759struct IrInstGenMulAdd {3759struct Stage1AirInstMulAdd {
3760 IrInstGen base;3760 Stage1AirInst base;
37613761
3762 IrInstGen *op1;3762 Stage1AirInst *op1;
3763 IrInstGen *op2;3763 Stage1AirInst *op2;
3764 IrInstGen *op3;3764 Stage1AirInst *op3;
3765};3765};
37663766
3767struct IrInstSrcAlignOf {3767struct Stage1ZirInstAlignOf {
3768 IrInstSrc base;3768 Stage1ZirInst base;
37693769
3770 IrInstSrc *type_value;3770 Stage1ZirInst *type_value;
3771};3771};
37723772
3773// returns true if error, returns false if not error3773// returns true if error, returns false if not error
3774struct IrInstSrcTestErr {3774struct Stage1ZirInstTestErr {
3775 IrInstSrc base;3775 Stage1ZirInst base;
37763776
3777 IrInstSrc *base_ptr;3777 Stage1ZirInst *base_ptr;
3778 bool resolve_err_set;3778 bool resolve_err_set;
3779 bool base_ptr_is_payload;3779 bool base_ptr_is_payload;
3780};3780};
37813781
3782struct IrInstGenTestErr {3782struct Stage1AirInstTestErr {
3783 IrInstGen base;3783 Stage1AirInst base;
37843784
3785 IrInstGen *err_union;3785 Stage1AirInst *err_union;
3786};3786};
37873787
3788// Takes an error union pointer, returns a pointer to the error code.3788// Takes an error union pointer, returns a pointer to the error code.
3789struct IrInstSrcUnwrapErrCode {3789struct Stage1ZirInstUnwrapErrCode {
3790 IrInstSrc base;3790 Stage1ZirInst base;
37913791
3792 IrInstSrc *err_union_ptr;3792 Stage1ZirInst *err_union_ptr;
3793 bool initializing;3793 bool initializing;
3794};3794};
37953795
3796struct IrInstGenUnwrapErrCode {3796struct Stage1AirInstUnwrapErrCode {
3797 IrInstGen base;3797 Stage1AirInst base;
37983798
3799 IrInstGen *err_union_ptr;3799 Stage1AirInst *err_union_ptr;
3800 bool initializing;3800 bool initializing;
3801};3801};
38023802
3803struct IrInstSrcUnwrapErrPayload {3803struct Stage1ZirInstUnwrapErrPayload {
3804 IrInstSrc base;3804 Stage1ZirInst base;
38053805
3806 IrInstSrc *value;3806 Stage1ZirInst *value;
3807 bool safety_check_on;3807 bool safety_check_on;
3808 bool initializing;3808 bool initializing;
3809};3809};
38103810
3811struct IrInstGenUnwrapErrPayload {3811struct Stage1AirInstUnwrapErrPayload {
3812 IrInstGen base;3812 Stage1AirInst base;
38133813
3814 IrInstGen *value;3814 Stage1AirInst *value;
3815 bool safety_check_on;3815 bool safety_check_on;
3816 bool initializing;3816 bool initializing;
3817};3817};
38183818
3819struct IrInstGenOptionalWrap {3819struct Stage1AirInstOptionalWrap {
3820 IrInstGen base;3820 Stage1AirInst base;
38213821
3822 IrInstGen *operand;3822 Stage1AirInst *operand;
3823 IrInstGen *result_loc;3823 Stage1AirInst *result_loc;
3824};3824};
38253825
3826struct IrInstGenErrWrapPayload {3826struct Stage1AirInstErrWrapPayload {
3827 IrInstGen base;3827 Stage1AirInst base;
38283828
3829 IrInstGen *operand;3829 Stage1AirInst *operand;
3830 IrInstGen *result_loc;3830 Stage1AirInst *result_loc;
3831};3831};
38323832
3833struct IrInstGenErrWrapCode {3833struct Stage1AirInstErrWrapCode {
3834 IrInstGen base;3834 Stage1AirInst base;
38353835
3836 IrInstGen *operand;3836 Stage1AirInst *operand;
3837 IrInstGen *result_loc;3837 Stage1AirInst *result_loc;
3838};3838};
38393839
3840struct IrInstSrcFnProto {3840struct Stage1ZirInstFnProto {
3841 IrInstSrc base;3841 Stage1ZirInst base;
38423842
3843 IrInstSrc **param_types;3843 Stage1ZirInst **param_types;
3844 IrInstSrc *align_value;3844 Stage1ZirInst *align_value;
3845 IrInstSrc *callconv_value;3845 Stage1ZirInst *callconv_value;
3846 IrInstSrc *return_type;3846 Stage1ZirInst *return_type;
3847 bool is_var_args;3847 bool is_var_args;
3848};3848};
38493849
3850// true if the target value is compile time known, false otherwise3850// true if the target value is compile time known, false otherwise
3851struct IrInstSrcTestComptime {3851struct Stage1ZirInstTestComptime {
3852 IrInstSrc base;3852 Stage1ZirInst base;
38533853
3854 IrInstSrc *value;3854 Stage1ZirInst *value;
3855};3855};
38563856
3857struct IrInstSrcPtrCast {3857struct Stage1ZirInstPtrCast {
3858 IrInstSrc base;3858 Stage1ZirInst base;
38593859
3860 IrInstSrc *dest_type;3860 Stage1ZirInst *dest_type;
3861 IrInstSrc *ptr;3861 Stage1ZirInst *ptr;
3862 bool safety_check_on;3862 bool safety_check_on;
3863};3863};
38643864
3865struct IrInstGenPtrCast {3865struct Stage1AirInstPtrCast {
3866 IrInstGen base;3866 Stage1AirInst base;
38673867
3868 IrInstGen *ptr;3868 Stage1AirInst *ptr;
3869 bool safety_check_on;3869 bool safety_check_on;
3870};3870};
38713871
3872struct IrInstSrcImplicitCast {3872struct Stage1ZirInstImplicitCast {
3873 IrInstSrc base;3873 Stage1ZirInst base;
38743874
3875 IrInstSrc *operand;3875 Stage1ZirInst *operand;
3876 ResultLocCast *result_loc_cast;3876 ResultLocCast *result_loc_cast;
3877};3877};
38783878
3879struct IrInstSrcBitCast {3879struct Stage1ZirInstBitCast {
3880 IrInstSrc base;3880 Stage1ZirInst base;
38813881
3882 IrInstSrc *operand;3882 Stage1ZirInst *operand;
3883 ResultLocBitCast *result_loc_bit_cast;3883 ResultLocBitCast *result_loc_bit_cast;
3884};3884};
38853885
3886struct IrInstGenBitCast {3886struct Stage1AirInstBitCast {
3887 IrInstGen base;3887 Stage1AirInst base;
38883888
3889 IrInstGen *operand;3889 Stage1AirInst *operand;
3890};3890};
38913891
3892struct IrInstGenWidenOrShorten {3892struct Stage1AirInstWidenOrShorten {
3893 IrInstGen base;3893 Stage1AirInst base;
38943894
3895 IrInstGen *target;3895 Stage1AirInst *target;
3896};3896};
38973897
3898struct IrInstSrcPtrToInt {3898struct Stage1ZirInstPtrToInt {
3899 IrInstSrc base;3899 Stage1ZirInst base;
39003900
3901 IrInstSrc *target;3901 Stage1ZirInst *target;
3902};3902};
39033903
3904struct IrInstGenPtrToInt {3904struct Stage1AirInstPtrToInt {
3905 IrInstGen base;3905 Stage1AirInst base;
39063906
3907 IrInstGen *target;3907 Stage1AirInst *target;
3908};3908};
39093909
3910struct IrInstSrcIntToPtr {3910struct Stage1ZirInstIntToPtr {
3911 IrInstSrc base;3911 Stage1ZirInst base;
39123912
3913 IrInstSrc *dest_type;3913 Stage1ZirInst *dest_type;
3914 IrInstSrc *target;3914 Stage1ZirInst *target;
3915};3915};
39163916
3917struct IrInstGenIntToPtr {3917struct Stage1AirInstIntToPtr {
3918 IrInstGen base;3918 Stage1AirInst base;
39193919
3920 IrInstGen *target;3920 Stage1AirInst *target;
3921};3921};
39223922
3923struct IrInstSrcIntToEnum {3923struct Stage1ZirInstIntToEnum {
3924 IrInstSrc base;3924 Stage1ZirInst base;
39253925
3926 IrInstSrc *dest_type;3926 Stage1ZirInst *dest_type;
3927 IrInstSrc *target;3927 Stage1ZirInst *target;
3928};3928};
39293929
3930struct IrInstGenIntToEnum {3930struct Stage1AirInstIntToEnum {
3931 IrInstGen base;3931 Stage1AirInst base;
39323932
3933 IrInstGen *target;3933 Stage1AirInst *target;
3934};3934};
39353935
3936struct IrInstSrcEnumToInt {3936struct Stage1ZirInstEnumToInt {
3937 IrInstSrc base;3937 Stage1ZirInst base;
39383938
3939 IrInstSrc *target;3939 Stage1ZirInst *target;
3940};3940};
39413941
3942struct IrInstSrcIntToErr {3942struct Stage1ZirInstIntToErr {
3943 IrInstSrc base;3943 Stage1ZirInst base;
39443944
3945 IrInstSrc *target;3945 Stage1ZirInst *target;
3946};3946};
39473947
3948struct IrInstGenIntToErr {3948struct Stage1AirInstIntToErr {
3949 IrInstGen base;3949 Stage1AirInst base;
39503950
3951 IrInstGen *target;3951 Stage1AirInst *target;
3952};3952};
39533953
3954struct IrInstSrcErrToInt {3954struct Stage1ZirInstErrToInt {
3955 IrInstSrc base;3955 Stage1ZirInst base;
39563956
3957 IrInstSrc *target;3957 Stage1ZirInst *target;
3958};3958};
39593959
3960struct IrInstGenErrToInt {3960struct Stage1AirInstErrToInt {
3961 IrInstGen base;3961 Stage1AirInst base;
39623962
3963 IrInstGen *target;3963 Stage1AirInst *target;
3964};3964};
39653965
3966struct IrInstSrcCheckSwitchProngsRange {3966struct Stage1ZirInstCheckSwitchProngsRange {
3967 IrInstSrc *start;3967 Stage1ZirInst *start;
3968 IrInstSrc *end;3968 Stage1ZirInst *end;
3969};3969};
39703970
3971struct IrInstSrcCheckSwitchProngs {3971struct Stage1ZirInstCheckSwitchProngs {
3972 IrInstSrc base;3972 Stage1ZirInst base;
39733973
3974 IrInstSrc *target_value;3974 Stage1ZirInst *target_value;
3975 IrInstSrcCheckSwitchProngsRange *ranges;3975 Stage1ZirInstCheckSwitchProngsRange *ranges;
3976 size_t range_count;3976 size_t range_count;
3977 AstNode* else_prong;3977 AstNode* else_prong;
3978};3978};
39793979
3980struct IrInstSrcCheckStatementIsVoid {3980struct Stage1ZirInstCheckStatementIsVoid {
3981 IrInstSrc base;3981 Stage1ZirInst base;
39823982
3983 IrInstSrc *statement_value;3983 Stage1ZirInst *statement_value;
3984};3984};
39853985
3986struct IrInstSrcTypeName {3986struct Stage1ZirInstTypeName {
3987 IrInstSrc base;3987 Stage1ZirInst base;
39883988
3989 IrInstSrc *type_value;3989 Stage1ZirInst *type_value;
3990};3990};
39913991
3992struct IrInstSrcDeclRef {3992struct Stage1ZirInstDeclRef {
3993 IrInstSrc base;3993 Stage1ZirInst base;
39943994
3995 LVal lval;3995 LVal lval;
3996 Tld *tld;3996 Tld *tld;
3997};3997};
39983998
3999struct IrInstSrcPanic {3999struct Stage1ZirInstPanic {
4000 IrInstSrc base;4000 Stage1ZirInst base;
40014001
4002 IrInstSrc *msg;4002 Stage1ZirInst *msg;
4003};4003};
40044004
4005struct IrInstGenPanic {4005struct Stage1AirInstPanic {
4006 IrInstGen base;4006 Stage1AirInst base;
40074007
4008 IrInstGen *msg;4008 Stage1AirInst *msg;
4009};4009};
40104010
4011struct IrInstSrcTagName {4011struct Stage1ZirInstTagName {
4012 IrInstSrc base;4012 Stage1ZirInst base;
40134013
4014 IrInstSrc *target;4014 Stage1ZirInst *target;
4015};4015};
40164016
4017struct IrInstGenTagName {4017struct Stage1AirInstTagName {
4018 IrInstGen base;4018 Stage1AirInst base;
40194019
4020 IrInstGen *target;4020 Stage1AirInst *target;
4021};4021};
40224022
4023struct IrInstSrcFieldParentPtr {4023struct Stage1ZirInstFieldParentPtr {
4024 IrInstSrc base;4024 Stage1ZirInst base;
40254025
4026 IrInstSrc *type_value;4026 Stage1ZirInst *type_value;
4027 IrInstSrc *field_name;4027 Stage1ZirInst *field_name;
4028 IrInstSrc *field_ptr;4028 Stage1ZirInst *field_ptr;
4029};4029};
40304030
4031struct IrInstGenFieldParentPtr {4031struct Stage1AirInstFieldParentPtr {
4032 IrInstGen base;4032 Stage1AirInst base;
40334033
4034 IrInstGen *field_ptr;4034 Stage1AirInst *field_ptr;
4035 TypeStructField *field;4035 TypeStructField *field;
4036};4036};
40374037
4038struct IrInstSrcOffsetOf {4038struct Stage1ZirInstOffsetOf {
4039 IrInstSrc base;4039 Stage1ZirInst base;
40404040
4041 IrInstSrc *type_value;4041 Stage1ZirInst *type_value;
4042 IrInstSrc *field_name;4042 Stage1ZirInst *field_name;
4043};4043};
40444044
4045struct IrInstSrcBitOffsetOf {4045struct Stage1ZirInstBitOffsetOf {
4046 IrInstSrc base;4046 Stage1ZirInst base;
40474047
4048 IrInstSrc *type_value;4048 Stage1ZirInst *type_value;
4049 IrInstSrc *field_name;4049 Stage1ZirInst *field_name;
4050};4050};
40514051
4052struct IrInstSrcTypeInfo {4052struct Stage1ZirInstTypeInfo {
4053 IrInstSrc base;4053 Stage1ZirInst base;
40544054
4055 IrInstSrc *type_value;4055 Stage1ZirInst *type_value;
4056};4056};
40574057
4058struct IrInstSrcType {4058struct Stage1ZirInstType {
4059 IrInstSrc base;4059 Stage1ZirInst base;
40604060
4061 IrInstSrc *type_info;4061 Stage1ZirInst *type_info;
4062};4062};
40634063
4064struct IrInstSrcHasField {4064struct Stage1ZirInstHasField {
4065 IrInstSrc base;4065 Stage1ZirInst base;
40664066
4067 IrInstSrc *container_type;4067 Stage1ZirInst *container_type;
4068 IrInstSrc *field_name;4068 Stage1ZirInst *field_name;
4069};4069};
40704070
4071struct IrInstSrcSetEvalBranchQuota {4071struct Stage1ZirInstSetEvalBranchQuota {
4072 IrInstSrc base;4072 Stage1ZirInst base;
40734073
4074 IrInstSrc *new_quota;4074 Stage1ZirInst *new_quota;
4075};4075};
40764076
4077struct IrInstSrcAlignCast {4077struct Stage1ZirInstAlignCast {
4078 IrInstSrc base;4078 Stage1ZirInst base;
40794079
4080 IrInstSrc *align_bytes;4080 Stage1ZirInst *align_bytes;
4081 IrInstSrc *target;4081 Stage1ZirInst *target;
4082};4082};
40834083
4084struct IrInstGenAlignCast {4084struct Stage1AirInstAlignCast {
4085 IrInstGen base;4085 Stage1AirInst base;
40864086
4087 IrInstGen *target;4087 Stage1AirInst *target;
4088};4088};
40894089
4090struct IrInstSrcSetAlignStack {4090struct Stage1ZirInstSetAlignStack {
4091 IrInstSrc base;4091 Stage1ZirInst base;
40924092
4093 IrInstSrc *align_bytes;4093 Stage1ZirInst *align_bytes;
4094};4094};
40954095
4096struct IrInstSrcArgType {4096struct Stage1ZirInstArgType {
4097 IrInstSrc base;4097 Stage1ZirInst base;
40984098
4099 IrInstSrc *fn_type;4099 Stage1ZirInst *fn_type;
4100 IrInstSrc *arg_index;4100 Stage1ZirInst *arg_index;
4101};4101};
41024102
4103struct IrInstSrcExport {4103struct Stage1ZirInstExport {
4104 IrInstSrc base;4104 Stage1ZirInst base;
41054105
4106 IrInstSrc *target;4106 Stage1ZirInst *target;
4107 IrInstSrc *options;4107 Stage1ZirInst *options;
4108};4108};
41094109
4110struct IrInstSrcExtern {4110struct Stage1ZirInstExtern {
4111 IrInstSrc base;4111 Stage1ZirInst base;
41124112
4113 IrInstSrc *type;4113 Stage1ZirInst *type;
4114 IrInstSrc *options;4114 Stage1ZirInst *options;
4115};4115};
41164116
4117struct IrInstGenExtern {4117struct Stage1AirInstExtern {
4118 IrInstGen base;4118 Stage1AirInst base;
41194119
4120 Buf *name;4120 Buf *name;
4121 GlobalLinkageId linkage;4121 GlobalLinkageId linkage;
...@@ -4127,310 +4127,310 @@ enum IrInstErrorReturnTraceOptional {...@@ -4127,310 +4127,310 @@ enum IrInstErrorReturnTraceOptional {
4127 IrInstErrorReturnTraceNonNull,4127 IrInstErrorReturnTraceNonNull,
4128};4128};
41294129
4130struct IrInstSrcErrorReturnTrace {4130struct Stage1ZirInstErrorReturnTrace {
4131 IrInstSrc base;4131 Stage1ZirInst base;
41324132
4133 IrInstErrorReturnTraceOptional optional;4133 IrInstErrorReturnTraceOptional optional;
4134};4134};
41354135
4136struct IrInstGenErrorReturnTrace {4136struct Stage1AirInstErrorReturnTrace {
4137 IrInstGen base;4137 Stage1AirInst base;
41384138
4139 IrInstErrorReturnTraceOptional optional;4139 IrInstErrorReturnTraceOptional optional;
4140};4140};
41414141
4142struct IrInstSrcErrorUnion {4142struct Stage1ZirInstErrorUnion {
4143 IrInstSrc base;4143 Stage1ZirInst base;
41444144
4145 IrInstSrc *err_set;4145 Stage1ZirInst *err_set;
4146 IrInstSrc *payload;4146 Stage1ZirInst *payload;
4147 Buf *type_name;4147 Buf *type_name;
4148};4148};
41494149
4150struct IrInstSrcAtomicRmw {4150struct Stage1ZirInstAtomicRmw {
4151 IrInstSrc base;4151 Stage1ZirInst base;
41524152
4153 IrInstSrc *operand_type;4153 Stage1ZirInst *operand_type;
4154 IrInstSrc *ptr;4154 Stage1ZirInst *ptr;
4155 IrInstSrc *op;4155 Stage1ZirInst *op;
4156 IrInstSrc *operand;4156 Stage1ZirInst *operand;
4157 IrInstSrc *ordering;4157 Stage1ZirInst *ordering;
4158};4158};
41594159
4160struct IrInstGenAtomicRmw {4160struct Stage1AirInstAtomicRmw {
4161 IrInstGen base;4161 Stage1AirInst base;
41624162
4163 IrInstGen *ptr;4163 Stage1AirInst *ptr;
4164 IrInstGen *operand;4164 Stage1AirInst *operand;
4165 AtomicRmwOp op;4165 AtomicRmwOp op;
4166 AtomicOrder ordering;4166 AtomicOrder ordering;
4167};4167};
41684168
4169struct IrInstSrcAtomicLoad {4169struct Stage1ZirInstAtomicLoad {
4170 IrInstSrc base;4170 Stage1ZirInst base;
41714171
4172 IrInstSrc *operand_type;4172 Stage1ZirInst *operand_type;
4173 IrInstSrc *ptr;4173 Stage1ZirInst *ptr;
4174 IrInstSrc *ordering;4174 Stage1ZirInst *ordering;
4175};4175};
41764176
4177struct IrInstGenAtomicLoad {4177struct Stage1AirInstAtomicLoad {
4178 IrInstGen base;4178 Stage1AirInst base;
41794179
4180 IrInstGen *ptr;4180 Stage1AirInst *ptr;
4181 AtomicOrder ordering;4181 AtomicOrder ordering;
4182};4182};
41834183
4184struct IrInstSrcAtomicStore {4184struct Stage1ZirInstAtomicStore {
4185 IrInstSrc base;4185 Stage1ZirInst base;
41864186
4187 IrInstSrc *operand_type;4187 Stage1ZirInst *operand_type;
4188 IrInstSrc *ptr;4188 Stage1ZirInst *ptr;
4189 IrInstSrc *value;4189 Stage1ZirInst *value;
4190 IrInstSrc *ordering;4190 Stage1ZirInst *ordering;
4191};4191};
41924192
4193struct IrInstGenAtomicStore {4193struct Stage1AirInstAtomicStore {
4194 IrInstGen base;4194 Stage1AirInst base;
41954195
4196 IrInstGen *ptr;4196 Stage1AirInst *ptr;
4197 IrInstGen *value;4197 Stage1AirInst *value;
4198 AtomicOrder ordering;4198 AtomicOrder ordering;
4199};4199};
42004200
4201struct IrInstSrcSaveErrRetAddr {4201struct Stage1ZirInstSaveErrRetAddr {
4202 IrInstSrc base;4202 Stage1ZirInst base;
4203};4203};
42044204
4205struct IrInstGenSaveErrRetAddr {4205struct Stage1AirInstSaveErrRetAddr {
4206 IrInstGen base;4206 Stage1AirInst base;
4207};4207};
42084208
4209struct IrInstSrcAddImplicitReturnType {4209struct Stage1ZirInstAddImplicitReturnType {
4210 IrInstSrc base;4210 Stage1ZirInst base;
42114211
4212 IrInstSrc *value;4212 Stage1ZirInst *value;
4213 ResultLocReturn *result_loc_ret;4213 ResultLocReturn *result_loc_ret;
4214};4214};
42154215
4216// For float ops that take a single argument4216// For float ops that take a single argument
4217struct IrInstSrcFloatOp {4217struct Stage1ZirInstFloatOp {
4218 IrInstSrc base;4218 Stage1ZirInst base;
42194219
4220 IrInstSrc *operand;4220 Stage1ZirInst *operand;
4221 BuiltinFnId fn_id;4221 BuiltinFnId fn_id;
4222};4222};
42234223
4224struct IrInstGenFloatOp {4224struct Stage1AirInstFloatOp {
4225 IrInstGen base;4225 Stage1AirInst base;
42264226
4227 IrInstGen *operand;4227 Stage1AirInst *operand;
4228 BuiltinFnId fn_id;4228 BuiltinFnId fn_id;
4229};4229};
42304230
4231struct IrInstSrcCheckRuntimeScope {4231struct Stage1ZirInstCheckRuntimeScope {
4232 IrInstSrc base;4232 Stage1ZirInst base;
42334233
4234 IrInstSrc *scope_is_comptime;4234 Stage1ZirInst *scope_is_comptime;
4235 IrInstSrc *is_comptime;4235 Stage1ZirInst *is_comptime;
4236};4236};
42374237
4238struct IrInstSrcBswap {4238struct Stage1ZirInstBswap {
4239 IrInstSrc base;4239 Stage1ZirInst base;
42404240
4241 IrInstSrc *type;4241 Stage1ZirInst *type;
4242 IrInstSrc *op;4242 Stage1ZirInst *op;
4243};4243};
42444244
4245struct IrInstGenBswap {4245struct Stage1AirInstBswap {
4246 IrInstGen base;4246 Stage1AirInst base;
42474247
4248 IrInstGen *op;4248 Stage1AirInst *op;
4249};4249};
42504250
4251struct IrInstSrcBitReverse {4251struct Stage1ZirInstBitReverse {
4252 IrInstSrc base;4252 Stage1ZirInst base;
42534253
4254 IrInstSrc *type;4254 Stage1ZirInst *type;
4255 IrInstSrc *op;4255 Stage1ZirInst *op;
4256};4256};
42574257
4258struct IrInstGenBitReverse {4258struct Stage1AirInstBitReverse {
4259 IrInstGen base;4259 Stage1AirInst base;
42604260
4261 IrInstGen *op;4261 Stage1AirInst *op;
4262};4262};
42634263
4264struct IrInstGenArrayToVector {4264struct Stage1AirInstArrayToVector {
4265 IrInstGen base;4265 Stage1AirInst base;
42664266
4267 IrInstGen *array;4267 Stage1AirInst *array;
4268};4268};
42694269
4270struct IrInstGenVectorToArray {4270struct Stage1AirInstVectorToArray {
4271 IrInstGen base;4271 Stage1AirInst base;
42724272
4273 IrInstGen *vector;4273 Stage1AirInst *vector;
4274 IrInstGen *result_loc;4274 Stage1AirInst *result_loc;
4275};4275};
42764276
4277struct IrInstSrcShuffleVector {4277struct Stage1ZirInstShuffleVector {
4278 IrInstSrc base;4278 Stage1ZirInst base;
42794279
4280 IrInstSrc *scalar_type;4280 Stage1ZirInst *scalar_type;
4281 IrInstSrc *a;4281 Stage1ZirInst *a;
4282 IrInstSrc *b;4282 Stage1ZirInst *b;
4283 IrInstSrc *mask; // This is in zig-format, not llvm format4283 Stage1ZirInst *mask; // This is in zig-format, not llvm format
4284};4284};
42854285
4286struct IrInstGenShuffleVector {4286struct Stage1AirInstShuffleVector {
4287 IrInstGen base;4287 Stage1AirInst base;
42884288
4289 IrInstGen *a;4289 Stage1AirInst *a;
4290 IrInstGen *b;4290 Stage1AirInst *b;
4291 IrInstGen *mask; // This is in zig-format, not llvm format4291 Stage1AirInst *mask; // This is in zig-format, not llvm format
4292};4292};
42934293
4294struct IrInstSrcSplat {4294struct Stage1ZirInstSplat {
4295 IrInstSrc base;4295 Stage1ZirInst base;
42964296
4297 IrInstSrc *len;4297 Stage1ZirInst *len;
4298 IrInstSrc *scalar;4298 Stage1ZirInst *scalar;
4299};4299};
43004300
4301struct IrInstGenSplat {4301struct Stage1AirInstSplat {
4302 IrInstGen base;4302 Stage1AirInst base;
43034303
4304 IrInstGen *scalar;4304 Stage1AirInst *scalar;
4305};4305};
43064306
4307struct IrInstGenAssertZero {4307struct Stage1AirInstAssertZero {
4308 IrInstGen base;4308 Stage1AirInst base;
43094309
4310 IrInstGen *target;4310 Stage1AirInst *target;
4311};4311};
43124312
4313struct IrInstGenAssertNonNull {4313struct Stage1AirInstAssertNonNull {
4314 IrInstGen base;4314 Stage1AirInst base;
43154315
4316 IrInstGen *target;4316 Stage1AirInst *target;
4317};4317};
43184318
4319struct IrInstSrcUnionInitNamedField {4319struct Stage1ZirInstUnionInitNamedField {
4320 IrInstSrc base;4320 Stage1ZirInst base;
43214321
4322 IrInstSrc *union_type;4322 Stage1ZirInst *union_type;
4323 IrInstSrc *field_name;4323 Stage1ZirInst *field_name;
4324 IrInstSrc *field_result_loc;4324 Stage1ZirInst *field_result_loc;
4325 IrInstSrc *result_loc;4325 Stage1ZirInst *result_loc;
4326};4326};
43274327
4328struct IrInstSrcHasDecl {4328struct Stage1ZirInstHasDecl {
4329 IrInstSrc base;4329 Stage1ZirInst base;
43304330
4331 IrInstSrc *container;4331 Stage1ZirInst *container;
4332 IrInstSrc *name;4332 Stage1ZirInst *name;
4333};4333};
43344334
4335struct IrInstSrcUndeclaredIdent {4335struct Stage1ZirInstUndeclaredIdent {
4336 IrInstSrc base;4336 Stage1ZirInst base;
43374337
4338 Buf *name;4338 Buf *name;
4339};4339};
43404340
4341struct IrInstSrcAlloca {4341struct Stage1ZirInstAlloca {
4342 IrInstSrc base;4342 Stage1ZirInst base;
43434343
4344 IrInstSrc *align;4344 Stage1ZirInst *align;
4345 IrInstSrc *is_comptime;4345 Stage1ZirInst *is_comptime;
4346 const char *name_hint;4346 const char *name_hint;
4347};4347};
43484348
4349struct IrInstGenAlloca {4349struct Stage1AirInstAlloca {
4350 IrInstGen base;4350 Stage1AirInst base;
43514351
4352 uint32_t align;4352 uint32_t align;
4353 const char *name_hint;4353 const char *name_hint;
4354 size_t field_index;4354 size_t field_index;
4355};4355};
43564356
4357struct IrInstSrcEndExpr {4357struct Stage1ZirInstEndExpr {
4358 IrInstSrc base;4358 Stage1ZirInst base;
43594359
4360 IrInstSrc *value;4360 Stage1ZirInst *value;
4361 ResultLoc *result_loc;4361 ResultLoc *result_loc;
4362};4362};
43634363
4364// This one is for writing through the result pointer.4364// This one is for writing through the result pointer.
4365struct IrInstSrcResolveResult {4365struct Stage1ZirInstResolveResult {
4366 IrInstSrc base;4366 Stage1ZirInst base;
43674367
4368 ResultLoc *result_loc;4368 ResultLoc *result_loc;
4369 IrInstSrc *ty;4369 Stage1ZirInst *ty;
4370};4370};
43714371
4372struct IrInstSrcResetResult {4372struct Stage1ZirInstResetResult {
4373 IrInstSrc base;4373 Stage1ZirInst base;
43744374
4375 ResultLoc *result_loc;4375 ResultLoc *result_loc;
4376};4376};
43774377
4378struct IrInstGenPtrOfArrayToSlice {4378struct Stage1AirInstPtrOfArrayToSlice {
4379 IrInstGen base;4379 Stage1AirInst base;
43804380
4381 IrInstGen *operand;4381 Stage1AirInst *operand;
4382 IrInstGen *result_loc;4382 Stage1AirInst *result_loc;
4383};4383};
43844384
4385struct IrInstSrcSuspendBegin {4385struct Stage1ZirInstSuspendBegin {
4386 IrInstSrc base;4386 Stage1ZirInst base;
4387};4387};
43884388
4389struct IrInstGenSuspendBegin {4389struct Stage1AirInstSuspendBegin {
4390 IrInstGen base;4390 Stage1AirInst base;
43914391
4392 LLVMBasicBlockRef resume_bb;4392 LLVMBasicBlockRef resume_bb;
4393};4393};
43944394
4395struct IrInstSrcSuspendFinish {4395struct Stage1ZirInstSuspendFinish {
4396 IrInstSrc base;4396 Stage1ZirInst base;
43974397
4398 IrInstSrcSuspendBegin *begin;4398 Stage1ZirInstSuspendBegin *begin;
4399};4399};
44004400
4401struct IrInstGenSuspendFinish {4401struct Stage1AirInstSuspendFinish {
4402 IrInstGen base;4402 Stage1AirInst base;
44034403
4404 IrInstGenSuspendBegin *begin;4404 Stage1AirInstSuspendBegin *begin;
4405};4405};
44064406
4407struct IrInstSrcAwait {4407struct Stage1ZirInstAwait {
4408 IrInstSrc base;4408 Stage1ZirInst base;
44094409
4410 IrInstSrc *frame;4410 Stage1ZirInst *frame;
4411 ResultLoc *result_loc;4411 ResultLoc *result_loc;
4412 bool is_nosuspend;4412 bool is_nosuspend;
4413};4413};
44144414
4415struct IrInstGenAwait {4415struct Stage1AirInstAwait {
4416 IrInstGen base;4416 Stage1AirInst base;
44174417
4418 IrInstGen *frame;4418 Stage1AirInst *frame;
4419 IrInstGen *result_loc;4419 Stage1AirInst *result_loc;
4420 ZigFn *target_fn;4420 ZigFn *target_fn;
4421 bool is_nosuspend;4421 bool is_nosuspend;
4422};4422};
44234423
4424struct IrInstSrcResume {4424struct Stage1ZirInstResume {
4425 IrInstSrc base;4425 Stage1ZirInst base;
44264426
4427 IrInstSrc *frame;4427 Stage1ZirInst *frame;
4428};4428};
44294429
4430struct IrInstGenResume {4430struct Stage1AirInstResume {
4431 IrInstGen base;4431 Stage1AirInst base;
44324432
4433 IrInstGen *frame;4433 Stage1AirInst *frame;
4434};4434};
44354435
4436enum SpillId {4436enum SpillId {
...@@ -4438,37 +4438,37 @@ enum SpillId {...@@ -4438,37 +4438,37 @@ enum SpillId {
4438 SpillIdRetErrCode,4438 SpillIdRetErrCode,
4439};4439};
44404440
4441struct IrInstSrcSpillBegin {4441struct Stage1ZirInstSpillBegin {
4442 IrInstSrc base;4442 Stage1ZirInst base;
44434443
4444 IrInstSrc *operand;4444 Stage1ZirInst *operand;
4445 SpillId spill_id;4445 SpillId spill_id;
4446};4446};
44474447
4448struct IrInstGenSpillBegin {4448struct Stage1AirInstSpillBegin {
4449 IrInstGen base;4449 Stage1AirInst base;
44504450
4451 SpillId spill_id;4451 SpillId spill_id;
4452 IrInstGen *operand;4452 Stage1AirInst *operand;
4453};4453};
44544454
4455struct IrInstSrcSpillEnd {4455struct Stage1ZirInstSpillEnd {
4456 IrInstSrc base;4456 Stage1ZirInst base;
44574457
4458 IrInstSrcSpillBegin *begin;4458 Stage1ZirInstSpillBegin *begin;
4459};4459};
44604460
4461struct IrInstGenSpillEnd {4461struct Stage1AirInstSpillEnd {
4462 IrInstGen base;4462 Stage1AirInst base;
44634463
4464 IrInstGenSpillBegin *begin;4464 Stage1AirInstSpillBegin *begin;
4465};4465};
44664466
4467struct IrInstGenVectorExtractElem {4467struct Stage1AirInstVectorExtractElem {
4468 IrInstGen base;4468 Stage1AirInst base;
44694469
4470 IrInstGen *vector;4470 Stage1AirInst *vector;
4471 IrInstGen *index;4471 Stage1AirInst *index;
4472};4472};
44734473
4474enum ResultLocId {4474enum ResultLocId {
...@@ -4489,9 +4489,9 @@ struct ResultLoc {...@@ -4489,9 +4489,9 @@ struct ResultLoc {
4489 ResultLocId id;4489 ResultLocId id;
4490 bool written;4490 bool written;
4491 bool allow_write_through_const;4491 bool allow_write_through_const;
4492 IrInstGen *resolved_loc; // result ptr4492 Stage1AirInst *resolved_loc; // result ptr
4493 IrInstSrc *source_instruction;4493 Stage1ZirInst *source_instruction;
4494 IrInstGen *gen_instruction; // value to store to the result loc4494 Stage1AirInst *gen_instruction; // value to store to the result loc
4495 ZigType *implicit_elem_type;4495 ZigType *implicit_elem_type;
4496};4496};
44974497
...@@ -4525,7 +4525,7 @@ struct ResultLocPeerParent {...@@ -4525,7 +4525,7 @@ struct ResultLocPeerParent {
4525 ResultLoc *parent;4525 ResultLoc *parent;
4526 ZigList<ResultLocPeer *> peers;4526 ZigList<ResultLocPeer *> peers;
4527 ZigType *resolved_type;4527 ZigType *resolved_type;
4528 IrInstSrc *is_comptime;4528 Stage1ZirInst *is_comptime;
4529};4529};
45304530
4531struct ResultLocPeer {4531struct ResultLocPeer {
...@@ -4603,7 +4603,7 @@ struct FnWalkAttrs {...@@ -4603,7 +4603,7 @@ struct FnWalkAttrs {
4603struct FnWalkCall {4603struct FnWalkCall {
4604 ZigList<LLVMValueRef> *gen_param_values;4604 ZigList<LLVMValueRef> *gen_param_values;
4605 ZigList<ZigType *> *gen_param_types;4605 ZigList<ZigType *> *gen_param_types;
4606 IrInstGenCall *inst;4606 Stage1AirInstCall *inst;
4607 bool is_var_args;4607 bool is_var_args;
4608};4608};
46094609
src/stage1/analyze.cpp+23-23
...@@ -206,7 +206,7 @@ ScopeLoop *create_loop_scope(CodeGen *g, AstNode *node, Scope *parent) {...@@ -206,7 +206,7 @@ ScopeLoop *create_loop_scope(CodeGen *g, AstNode *node, Scope *parent) {
206 return scope;206 return scope;
207}207}
208208
209Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, IrInstSrc *is_comptime) {209Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, Stage1ZirInst *is_comptime) {
210 ScopeRuntime *scope = heap::c_allocator.create<ScopeRuntime>();210 ScopeRuntime *scope = heap::c_allocator.create<ScopeRuntime>();
211 scope->is_comptime = is_comptime;211 scope->is_comptime = is_comptime;
212 init_scope(g, &scope->base, ScopeIdRuntime, node, parent);212 init_scope(g, &scope->base, ScopeIdRuntime, node, parent);
...@@ -5071,7 +5071,7 @@ static void analyze_fn_async(CodeGen *g, ZigFn *fn, bool resolve_frame) {...@@ -5071,7 +5071,7 @@ static void analyze_fn_async(CodeGen *g, ZigFn *fn, bool resolve_frame) {
5071 }5071 }
50725072
5073 for (size_t i = 0; i < fn->call_list.length; i += 1) {5073 for (size_t i = 0; i < fn->call_list.length; i += 1) {
5074 IrInstGenCall *call = fn->call_list.at(i);5074 Stage1AirInstCall *call = fn->call_list.at(i);
5075 if (call->fn_entry == nullptr) {5075 if (call->fn_entry == nullptr) {
5076 // TODO function pointer call here, could be anything5076 // TODO function pointer call here, could be anything
5077 continue;5077 continue;
...@@ -5094,7 +5094,7 @@ static void analyze_fn_async(CodeGen *g, ZigFn *fn, bool resolve_frame) {...@@ -5094,7 +5094,7 @@ static void analyze_fn_async(CodeGen *g, ZigFn *fn, bool resolve_frame) {
5094 }5094 }
5095 }5095 }
5096 for (size_t i = 0; i < fn->await_list.length; i += 1) {5096 for (size_t i = 0; i < fn->await_list.length; i += 1) {
5097 IrInstGenAwait *await = fn->await_list.at(i);5097 Stage1AirInstAwait *await = fn->await_list.at(i);
5098 if (await->is_nosuspend) continue;5098 if (await->is_nosuspend) continue;
5099 switch (analyze_callee_async(g, fn, await->target_fn, await->base.source_node, must_not_be_async,5099 switch (analyze_callee_async(g, fn, await->target_fn, await->base.source_node, must_not_be_async,
5100 CallModifierNone))5100 CallModifierNone))
...@@ -6755,8 +6755,8 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {...@@ -6755,8 +6755,8 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
6755 ZigType *fn_type = get_async_fn_type(g, fn->type_entry);6755 ZigType *fn_type = get_async_fn_type(g, fn->type_entry);
67566756
6757 if (fn->analyzed_executable.need_err_code_spill) {6757 if (fn->analyzed_executable.need_err_code_spill) {
6758 IrInstGenAlloca *alloca_gen = heap::c_allocator.create<IrInstGenAlloca>();6758 Stage1AirInstAlloca *alloca_gen = heap::c_allocator.create<Stage1AirInstAlloca>();
6759 alloca_gen->base.id = IrInstGenIdAlloca;6759 alloca_gen->base.id = Stage1AirInstIdAlloca;
6760 alloca_gen->base.source_node = fn->proto_node;6760 alloca_gen->base.source_node = fn->proto_node;
6761 alloca_gen->base.scope = fn->child_scope;6761 alloca_gen->base.scope = fn->child_scope;
6762 alloca_gen->base.value = g->pass1_arena->create<ZigValue>();6762 alloca_gen->base.value = g->pass1_arena->create<ZigValue>();
...@@ -6769,11 +6769,11 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {...@@ -6769,11 +6769,11 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
67696769
6770 ZigType *largest_call_frame_type = nullptr;6770 ZigType *largest_call_frame_type = nullptr;
6771 // Later we'll change this to be largest_call_frame_type instead of void.6771 // Later we'll change this to be largest_call_frame_type instead of void.
6772 IrInstGen *all_calls_alloca = ir_create_alloca(g, &fn->fndef_scope->base, fn->body_node,6772 Stage1AirInst *all_calls_alloca = ir_create_alloca(g, &fn->fndef_scope->base, fn->body_node,
6773 fn, g->builtin_types.entry_void, "@async_call_frame");6773 fn, g->builtin_types.entry_void, "@async_call_frame");
67746774
6775 for (size_t i = 0; i < fn->call_list.length; i += 1) {6775 for (size_t i = 0; i < fn->call_list.length; i += 1) {
6776 IrInstGenCall *call = fn->call_list.at(i);6776 Stage1AirInstCall *call = fn->call_list.at(i);
6777 if (call->new_stack != nullptr) {6777 if (call->new_stack != nullptr) {
6778 // don't need to allocate a frame for this6778 // don't need to allocate a frame for this
6779 continue;6779 continue;
...@@ -6838,7 +6838,7 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {...@@ -6838,7 +6838,7 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
6838 // For example: foo() + await z6838 // For example: foo() + await z
6839 // The funtion call result of foo() must be spilled.6839 // The funtion call result of foo() must be spilled.
6840 for (size_t i = 0; i < fn->await_list.length; i += 1) {6840 for (size_t i = 0; i < fn->await_list.length; i += 1) {
6841 IrInstGenAwait *await = fn->await_list.at(i);6841 Stage1AirInstAwait *await = fn->await_list.at(i);
6842 if (await->is_nosuspend) {6842 if (await->is_nosuspend) {
6843 continue;6843 continue;
6844 }6844 }
...@@ -6875,10 +6875,10 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {...@@ -6875,10 +6875,10 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
6875 await->base.value->type, "");6875 await->base.value->type, "");
6876 }6876 }
6877 for (size_t block_i = 0; block_i < fn->analyzed_executable.basic_block_list.length; block_i += 1) {6877 for (size_t block_i = 0; block_i < fn->analyzed_executable.basic_block_list.length; block_i += 1) {
6878 IrBasicBlockGen *block = fn->analyzed_executable.basic_block_list.at(block_i);6878 Stage1AirBasicBlock *block = fn->analyzed_executable.basic_block_list.at(block_i);
6879 for (size_t instr_i = 0; instr_i < block->instruction_list.length; instr_i += 1) {6879 for (size_t instr_i = 0; instr_i < block->instruction_list.length; instr_i += 1) {
6880 IrInstGen *instruction = block->instruction_list.at(instr_i);6880 Stage1AirInst *instruction = block->instruction_list.at(instr_i);
6881 if (instruction->id == IrInstGenIdSuspendFinish) {6881 if (instruction->id == Stage1AirInstIdSuspendFinish) {
6882 mark_suspension_point(instruction->scope);6882 mark_suspension_point(instruction->scope);
6883 }6883 }
6884 }6884 }
...@@ -6886,20 +6886,20 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {...@@ -6886,20 +6886,20 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
6886 // Now that we've marked all the expr scopes that have to spill, we go over the instructions6886 // Now that we've marked all the expr scopes that have to spill, we go over the instructions
6887 // and spill the relevant ones.6887 // and spill the relevant ones.
6888 for (size_t block_i = 0; block_i < fn->analyzed_executable.basic_block_list.length; block_i += 1) {6888 for (size_t block_i = 0; block_i < fn->analyzed_executable.basic_block_list.length; block_i += 1) {
6889 IrBasicBlockGen *block = fn->analyzed_executable.basic_block_list.at(block_i);6889 Stage1AirBasicBlock *block = fn->analyzed_executable.basic_block_list.at(block_i);
6890 for (size_t instr_i = 0; instr_i < block->instruction_list.length; instr_i += 1) {6890 for (size_t instr_i = 0; instr_i < block->instruction_list.length; instr_i += 1) {
6891 IrInstGen *instruction = block->instruction_list.at(instr_i);6891 Stage1AirInst *instruction = block->instruction_list.at(instr_i);
6892 if (instruction->id == IrInstGenIdAwait ||6892 if (instruction->id == Stage1AirInstIdAwait ||
6893 instruction->id == IrInstGenIdVarPtr ||6893 instruction->id == Stage1AirInstIdVarPtr ||
6894 instruction->id == IrInstGenIdAlloca ||6894 instruction->id == Stage1AirInstIdAlloca ||
6895 instruction->id == IrInstGenIdSpillBegin ||6895 instruction->id == Stage1AirInstIdSpillBegin ||
6896 instruction->id == IrInstGenIdSpillEnd)6896 instruction->id == Stage1AirInstIdSpillEnd)
6897 {6897 {
6898 // This instruction does its own spilling specially, or otherwise doesn't need it.6898 // This instruction does its own spilling specially, or otherwise doesn't need it.
6899 continue;6899 continue;
6900 }6900 }
6901 if (instruction->id == IrInstGenIdCast &&6901 if (instruction->id == Stage1AirInstIdCast &&
6902 reinterpret_cast<IrInstGenCast *>(instruction)->cast_op == CastOpNoop)6902 reinterpret_cast<Stage1AirInstCast *>(instruction)->cast_op == CastOpNoop)
6903 {6903 {
6904 // The IR instruction exists only to change the type according to Zig. No spill needed.6904 // The IR instruction exists only to change the type according to Zig. No spill needed.
6905 continue;6905 continue;
...@@ -6964,7 +6964,7 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {...@@ -6964,7 +6964,7 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
6964 }6964 }
69656965
6966 for (size_t alloca_i = 0; alloca_i < fn->alloca_gen_list.length; alloca_i += 1) {6966 for (size_t alloca_i = 0; alloca_i < fn->alloca_gen_list.length; alloca_i += 1) {
6967 IrInstGenAlloca *instruction = fn->alloca_gen_list.at(alloca_i);6967 Stage1AirInstAlloca *instruction = fn->alloca_gen_list.at(alloca_i);
6968 instruction->field_index = SIZE_MAX;6968 instruction->field_index = SIZE_MAX;
6969 ZigType *ptr_type = instruction->base.value->type;6969 ZigType *ptr_type = instruction->base.value->type;
6970 assert(ptr_type->id == ZigTypeIdPointer);6970 assert(ptr_type->id == ZigTypeIdPointer);
...@@ -7146,8 +7146,8 @@ bool ir_get_var_is_comptime(ZigVar *var) {...@@ -7146,8 +7146,8 @@ bool ir_get_var_is_comptime(ZigVar *var) {
7146 // As an optimization, is_comptime values which are constant are allowed7146 // As an optimization, is_comptime values which are constant are allowed
7147 // to be omitted from analysis. In this case, there is no child instruction7147 // to be omitted from analysis. In this case, there is no child instruction
7148 // and we simply look at the unanalyzed const parent instruction.7148 // and we simply look at the unanalyzed const parent instruction.
7149 assert(var->is_comptime->id == IrInstSrcIdConst);7149 assert(var->is_comptime->id == Stage1ZirInstIdConst);
7150 IrInstSrcConst *const_inst = reinterpret_cast<IrInstSrcConst *>(var->is_comptime);7150 Stage1ZirInstConst *const_inst = reinterpret_cast<Stage1ZirInstConst *>(var->is_comptime);
7151 assert(const_inst->value->type->id == ZigTypeIdBool);7151 assert(const_inst->value->type->id == ZigTypeIdBool);
7152 var->is_comptime_memoized_value = const_inst->value->data.x_bool;7152 var->is_comptime_memoized_value = const_inst->value->data.x_bool;
7153 var->is_comptime = nullptr;7153 var->is_comptime = nullptr;
src/stage1/analyze.hpp+1-1
...@@ -138,7 +138,7 @@ ScopeSuspend *create_suspend_scope(CodeGen *g, AstNode *node, Scope *parent);...@@ -138,7 +138,7 @@ ScopeSuspend *create_suspend_scope(CodeGen *g, AstNode *node, Scope *parent);
138ScopeFnDef *create_fndef_scope(CodeGen *g, AstNode *node, Scope *parent, ZigFn *fn_entry);138ScopeFnDef *create_fndef_scope(CodeGen *g, AstNode *node, Scope *parent, ZigFn *fn_entry);
139Scope *create_comptime_scope(CodeGen *g, AstNode *node, Scope *parent);139Scope *create_comptime_scope(CodeGen *g, AstNode *node, Scope *parent);
140Scope *create_nosuspend_scope(CodeGen *g, AstNode *node, Scope *parent);140Scope *create_nosuspend_scope(CodeGen *g, AstNode *node, Scope *parent);
141Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, IrInstSrc *is_comptime);141Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, Stage1ZirInst *is_comptime);
142Scope *create_typeof_scope(CodeGen *g, AstNode *node, Scope *parent);142Scope *create_typeof_scope(CodeGen *g, AstNode *node, Scope *parent);
143ScopeExpr *create_expr_scope(CodeGen *g, AstNode *node, Scope *parent);143ScopeExpr *create_expr_scope(CodeGen *g, AstNode *node, Scope *parent);
144144
src/stage1/astgen.cpp+1569-1569
...@@ -21,25 +21,25 @@ struct Stage1AstGen {...@@ -21,25 +21,25 @@ struct Stage1AstGen {
21 bool in_c_import_scope;21 bool in_c_import_scope;
22};22};
2323
24static IrInstSrc *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope);24static Stage1ZirInst *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope);
25static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval,25static Stage1ZirInst *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval,
26 ResultLoc *result_loc);26 ResultLoc *result_loc);
2727
28static IrInstSrc *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *value, LVal lval,28static Stage1ZirInst *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *value, LVal lval,
29 ResultLoc *result_loc);29 ResultLoc *result_loc);
30static IrInstSrc *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *inst,30static Stage1ZirInst *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *inst,
31 ResultLoc *result_loc);31 ResultLoc *result_loc);
32static IrInstSrc *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,32static Stage1ZirInst *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
33 IrInstSrc *union_type, IrInstSrc *field_name, AstNode *expr_node,33 Stage1ZirInst *union_type, Stage1ZirInst *field_name, AstNode *expr_node,
34 LVal lval, ResultLoc *parent_result_loc);34 LVal lval, ResultLoc *parent_result_loc);
35static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, IrInstSrc *dest_type,35static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, Stage1ZirInst *dest_type,
36 ResultLoc *parent_result_loc);36 ResultLoc *parent_result_loc);
37static ZigVar *ir_create_var(Stage1AstGen *ag, AstNode *node, Scope *scope, Buf *name,37static ZigVar *ir_create_var(Stage1AstGen *ag, AstNode *node, Scope *scope, Buf *name,
38 bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime);38 bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime);
39static void build_decl_var_and_init(Stage1AstGen *ag, Scope *scope, AstNode *source_node,39static void build_decl_var_and_init(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
40 ZigVar *var, IrInstSrc *init, const char *name_hint, IrInstSrc *is_comptime);40 ZigVar *var, Stage1ZirInst *init, const char *name_hint, Stage1ZirInst *is_comptime);
4141
42static void ir_assert_impl(bool ok, IrInstSrc *source_instruction, char const *file, unsigned int line) {42static void ir_assert_impl(bool ok, Stage1ZirInst *source_instruction, char const *file, unsigned int line) {
43 if (ok) return;43 if (ok) return;
44 src_assert_impl(ok, source_instruction->source_node, file, line);44 src_assert_impl(ok, source_instruction->source_node, file, line);
45}45}
...@@ -54,299 +54,299 @@ static ErrorMsg *exec_add_error_node(CodeGen *codegen, Stage1Zir *exec, AstNode...@@ -54,299 +54,299 @@ static ErrorMsg *exec_add_error_node(CodeGen *codegen, Stage1Zir *exec, AstNode
54#define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__)54#define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__)
5555
5656
57static bool instr_is_unreachable(IrInstSrc *instruction) {57static bool instr_is_unreachable(Stage1ZirInst *instruction) {
58 switch (instruction->id) {58 switch (instruction->id) {
59 case IrInstSrcIdCondBr:59 case Stage1ZirInstIdCondBr:
60 case IrInstSrcIdReturn:60 case Stage1ZirInstIdReturn:
61 case IrInstSrcIdBr:61 case Stage1ZirInstIdBr:
62 case IrInstSrcIdUnreachable:62 case Stage1ZirInstIdUnreachable:
63 case IrInstSrcIdSwitchBr:63 case Stage1ZirInstIdSwitchBr:
64 case IrInstSrcIdPanic:64 case Stage1ZirInstIdPanic:
65 return true;65 return true;
66 default:66 default:
67 return false;67 return false;
68 }68 }
69}69}
7070
71void destroy_instruction_src(IrInstSrc *inst) {71void destroy_instruction_src(Stage1ZirInst *inst) {
72 switch (inst->id) {72 switch (inst->id) {
73 case IrInstSrcIdInvalid:73 case Stage1ZirInstIdInvalid:
74 zig_unreachable();74 zig_unreachable();
75 case IrInstSrcIdReturn:75 case Stage1ZirInstIdReturn:
76 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcReturn *>(inst));76 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstReturn *>(inst));
77 case IrInstSrcIdConst:77 case Stage1ZirInstIdConst:
78 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcConst *>(inst));78 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstConst *>(inst));
79 case IrInstSrcIdBinOp:79 case Stage1ZirInstIdBinOp:
80 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBinOp *>(inst));80 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBinOp *>(inst));
81 case IrInstSrcIdMergeErrSets:81 case Stage1ZirInstIdMergeErrSets:
82 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcMergeErrSets *>(inst));82 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstMergeErrSets *>(inst));
83 case IrInstSrcIdDeclVar:83 case Stage1ZirInstIdDeclVar:
84 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcDeclVar *>(inst));84 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstDeclVar *>(inst));
85 case IrInstSrcIdCall:85 case Stage1ZirInstIdCall:
86 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCall *>(inst));86 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCall *>(inst));
87 case IrInstSrcIdCallExtra:87 case Stage1ZirInstIdCallExtra:
88 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCallExtra *>(inst));88 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCallExtra *>(inst));
89 case IrInstSrcIdAsyncCallExtra:89 case Stage1ZirInstIdAsyncCallExtra:
90 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAsyncCallExtra *>(inst));90 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAsyncCallExtra *>(inst));
91 case IrInstSrcIdUnOp:91 case Stage1ZirInstIdUnOp:
92 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUnOp *>(inst));92 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUnOp *>(inst));
93 case IrInstSrcIdCondBr:93 case Stage1ZirInstIdCondBr:
94 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCondBr *>(inst));94 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCondBr *>(inst));
95 case IrInstSrcIdBr:95 case Stage1ZirInstIdBr:
96 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBr *>(inst));96 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBr *>(inst));
97 case IrInstSrcIdPhi:97 case Stage1ZirInstIdPhi:
98 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPhi *>(inst));98 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPhi *>(inst));
99 case IrInstSrcIdContainerInitList:99 case Stage1ZirInstIdContainerInitList:
100 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcContainerInitList *>(inst));100 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstContainerInitList *>(inst));
101 case IrInstSrcIdContainerInitFields:101 case Stage1ZirInstIdContainerInitFields:
102 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcContainerInitFields *>(inst));102 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstContainerInitFields *>(inst));
103 case IrInstSrcIdUnreachable:103 case Stage1ZirInstIdUnreachable:
104 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUnreachable *>(inst));104 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUnreachable *>(inst));
105 case IrInstSrcIdElemPtr:105 case Stage1ZirInstIdElemPtr:
106 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcElemPtr *>(inst));106 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstElemPtr *>(inst));
107 case IrInstSrcIdVarPtr:107 case Stage1ZirInstIdVarPtr:
108 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcVarPtr *>(inst));108 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstVarPtr *>(inst));
109 case IrInstSrcIdLoadPtr:109 case Stage1ZirInstIdLoadPtr:
110 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcLoadPtr *>(inst));110 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstLoadPtr *>(inst));
111 case IrInstSrcIdStorePtr:111 case Stage1ZirInstIdStorePtr:
112 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcStorePtr *>(inst));112 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstStorePtr *>(inst));
113 case IrInstSrcIdTypeOf:113 case Stage1ZirInstIdTypeOf:
114 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTypeOf *>(inst));114 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTypeOf *>(inst));
115 case IrInstSrcIdFieldPtr:115 case Stage1ZirInstIdFieldPtr:
116 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFieldPtr *>(inst));116 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFieldPtr *>(inst));
117 case IrInstSrcIdSetCold:117 case Stage1ZirInstIdSetCold:
118 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSetCold *>(inst));118 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSetCold *>(inst));
119 case IrInstSrcIdSetRuntimeSafety:119 case Stage1ZirInstIdSetRuntimeSafety:
120 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSetRuntimeSafety *>(inst));120 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSetRuntimeSafety *>(inst));
121 case IrInstSrcIdSetFloatMode:121 case Stage1ZirInstIdSetFloatMode:
122 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSetFloatMode *>(inst));122 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSetFloatMode *>(inst));
123 case IrInstSrcIdArrayType:123 case Stage1ZirInstIdArrayType:
124 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcArrayType *>(inst));124 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstArrayType *>(inst));
125 case IrInstSrcIdSliceType:125 case Stage1ZirInstIdSliceType:
126 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSliceType *>(inst));126 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSliceType *>(inst));
127 case IrInstSrcIdAnyFrameType:127 case Stage1ZirInstIdAnyFrameType:
128 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAnyFrameType *>(inst));128 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAnyFrameType *>(inst));
129 case IrInstSrcIdAsm:129 case Stage1ZirInstIdAsm:
130 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAsm *>(inst));130 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAsm *>(inst));
131 case IrInstSrcIdSizeOf:131 case Stage1ZirInstIdSizeOf:
132 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSizeOf *>(inst));132 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSizeOf *>(inst));
133 case IrInstSrcIdTestNonNull:133 case Stage1ZirInstIdTestNonNull:
134 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTestNonNull *>(inst));134 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTestNonNull *>(inst));
135 case IrInstSrcIdOptionalUnwrapPtr:135 case Stage1ZirInstIdOptionalUnwrapPtr:
136 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcOptionalUnwrapPtr *>(inst));136 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstOptionalUnwrapPtr *>(inst));
137 case IrInstSrcIdPopCount:137 case Stage1ZirInstIdPopCount:
138 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPopCount *>(inst));138 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPopCount *>(inst));
139 case IrInstSrcIdClz:139 case Stage1ZirInstIdClz:
140 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcClz *>(inst));140 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstClz *>(inst));
141 case IrInstSrcIdCtz:141 case Stage1ZirInstIdCtz:
142 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCtz *>(inst));142 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCtz *>(inst));
143 case IrInstSrcIdBswap:143 case Stage1ZirInstIdBswap:
144 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBswap *>(inst));144 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBswap *>(inst));
145 case IrInstSrcIdBitReverse:145 case Stage1ZirInstIdBitReverse:
146 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBitReverse *>(inst));146 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBitReverse *>(inst));
147 case IrInstSrcIdSwitchBr:147 case Stage1ZirInstIdSwitchBr:
148 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSwitchBr *>(inst));148 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSwitchBr *>(inst));
149 case IrInstSrcIdSwitchVar:149 case Stage1ZirInstIdSwitchVar:
150 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSwitchVar *>(inst));150 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSwitchVar *>(inst));
151 case IrInstSrcIdSwitchElseVar:151 case Stage1ZirInstIdSwitchElseVar:
152 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSwitchElseVar *>(inst));152 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSwitchElseVar *>(inst));
153 case IrInstSrcIdSwitchTarget:153 case Stage1ZirInstIdSwitchTarget:
154 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSwitchTarget *>(inst));154 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSwitchTarget *>(inst));
155 case IrInstSrcIdImport:155 case Stage1ZirInstIdImport:
156 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcImport *>(inst));156 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstImport *>(inst));
157 case IrInstSrcIdRef:157 case Stage1ZirInstIdRef:
158 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcRef *>(inst));158 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstRef *>(inst));
159 case IrInstSrcIdCompileErr:159 case Stage1ZirInstIdCompileErr:
160 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCompileErr *>(inst));160 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCompileErr *>(inst));
161 case IrInstSrcIdCompileLog:161 case Stage1ZirInstIdCompileLog:
162 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCompileLog *>(inst));162 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCompileLog *>(inst));
163 case IrInstSrcIdErrName:163 case Stage1ZirInstIdErrName:
164 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcErrName *>(inst));164 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstErrName *>(inst));
165 case IrInstSrcIdCImport:165 case Stage1ZirInstIdCImport:
166 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCImport *>(inst));166 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCImport *>(inst));
167 case IrInstSrcIdCInclude:167 case Stage1ZirInstIdCInclude:
168 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCInclude *>(inst));168 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCInclude *>(inst));
169 case IrInstSrcIdCDefine:169 case Stage1ZirInstIdCDefine:
170 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCDefine *>(inst));170 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCDefine *>(inst));
171 case IrInstSrcIdCUndef:171 case Stage1ZirInstIdCUndef:
172 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCUndef *>(inst));172 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCUndef *>(inst));
173 case IrInstSrcIdEmbedFile:173 case Stage1ZirInstIdEmbedFile:
174 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcEmbedFile *>(inst));174 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstEmbedFile *>(inst));
175 case IrInstSrcIdCmpxchg:175 case Stage1ZirInstIdCmpxchg:
176 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCmpxchg *>(inst));176 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCmpxchg *>(inst));
177 case IrInstSrcIdFence:177 case Stage1ZirInstIdFence:
178 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFence *>(inst));178 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFence *>(inst));
179 case IrInstSrcIdReduce:179 case Stage1ZirInstIdReduce:
180 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcReduce *>(inst));180 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstReduce *>(inst));
181 case IrInstSrcIdTruncate:181 case Stage1ZirInstIdTruncate:
182 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTruncate *>(inst));182 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTruncate *>(inst));
183 case IrInstSrcIdIntCast:183 case Stage1ZirInstIdIntCast:
184 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcIntCast *>(inst));184 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstIntCast *>(inst));
185 case IrInstSrcIdFloatCast:185 case Stage1ZirInstIdFloatCast:
186 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFloatCast *>(inst));186 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFloatCast *>(inst));
187 case IrInstSrcIdErrSetCast:187 case Stage1ZirInstIdErrSetCast:
188 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcErrSetCast *>(inst));188 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstErrSetCast *>(inst));
189 case IrInstSrcIdIntToFloat:189 case Stage1ZirInstIdIntToFloat:
190 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcIntToFloat *>(inst));190 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstIntToFloat *>(inst));
191 case IrInstSrcIdFloatToInt:191 case Stage1ZirInstIdFloatToInt:
192 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFloatToInt *>(inst));192 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFloatToInt *>(inst));
193 case IrInstSrcIdBoolToInt:193 case Stage1ZirInstIdBoolToInt:
194 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBoolToInt *>(inst));194 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBoolToInt *>(inst));
195 case IrInstSrcIdVectorType:195 case Stage1ZirInstIdVectorType:
196 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcVectorType *>(inst));196 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstVectorType *>(inst));
197 case IrInstSrcIdShuffleVector:197 case Stage1ZirInstIdShuffleVector:
198 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcShuffleVector *>(inst));198 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstShuffleVector *>(inst));
199 case IrInstSrcIdSplat:199 case Stage1ZirInstIdSplat:
200 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSplat *>(inst));200 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSplat *>(inst));
201 case IrInstSrcIdBoolNot:201 case Stage1ZirInstIdBoolNot:
202 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBoolNot *>(inst));202 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBoolNot *>(inst));
203 case IrInstSrcIdMemset:203 case Stage1ZirInstIdMemset:
204 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcMemset *>(inst));204 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstMemset *>(inst));
205 case IrInstSrcIdMemcpy:205 case Stage1ZirInstIdMemcpy:
206 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcMemcpy *>(inst));206 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstMemcpy *>(inst));
207 case IrInstSrcIdSlice:207 case Stage1ZirInstIdSlice:
208 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSlice *>(inst));208 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSlice *>(inst));
209 case IrInstSrcIdBreakpoint:209 case Stage1ZirInstIdBreakpoint:
210 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBreakpoint *>(inst));210 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBreakpoint *>(inst));
211 case IrInstSrcIdReturnAddress:211 case Stage1ZirInstIdReturnAddress:
212 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcReturnAddress *>(inst));212 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstReturnAddress *>(inst));
213 case IrInstSrcIdFrameAddress:213 case Stage1ZirInstIdFrameAddress:
214 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFrameAddress *>(inst));214 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFrameAddress *>(inst));
215 case IrInstSrcIdFrameHandle:215 case Stage1ZirInstIdFrameHandle:
216 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFrameHandle *>(inst));216 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFrameHandle *>(inst));
217 case IrInstSrcIdFrameType:217 case Stage1ZirInstIdFrameType:
218 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFrameType *>(inst));218 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFrameType *>(inst));
219 case IrInstSrcIdFrameSize:219 case Stage1ZirInstIdFrameSize:
220 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFrameSize *>(inst));220 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFrameSize *>(inst));
221 case IrInstSrcIdAlignOf:221 case Stage1ZirInstIdAlignOf:
222 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAlignOf *>(inst));222 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAlignOf *>(inst));
223 case IrInstSrcIdOverflowOp:223 case Stage1ZirInstIdOverflowOp:
224 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcOverflowOp *>(inst));224 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstOverflowOp *>(inst));
225 case IrInstSrcIdTestErr:225 case Stage1ZirInstIdTestErr:
226 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTestErr *>(inst));226 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTestErr *>(inst));
227 case IrInstSrcIdUnwrapErrCode:227 case Stage1ZirInstIdUnwrapErrCode:
228 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUnwrapErrCode *>(inst));228 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUnwrapErrCode *>(inst));
229 case IrInstSrcIdUnwrapErrPayload:229 case Stage1ZirInstIdUnwrapErrPayload:
230 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUnwrapErrPayload *>(inst));230 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUnwrapErrPayload *>(inst));
231 case IrInstSrcIdFnProto:231 case Stage1ZirInstIdFnProto:
232 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFnProto *>(inst));232 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFnProto *>(inst));
233 case IrInstSrcIdTestComptime:233 case Stage1ZirInstIdTestComptime:
234 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTestComptime *>(inst));234 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTestComptime *>(inst));
235 case IrInstSrcIdPtrCast:235 case Stage1ZirInstIdPtrCast:
236 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPtrCast *>(inst));236 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPtrCast *>(inst));
237 case IrInstSrcIdBitCast:237 case Stage1ZirInstIdBitCast:
238 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBitCast *>(inst));238 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBitCast *>(inst));
239 case IrInstSrcIdPtrToInt:239 case Stage1ZirInstIdPtrToInt:
240 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPtrToInt *>(inst));240 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPtrToInt *>(inst));
241 case IrInstSrcIdIntToPtr:241 case Stage1ZirInstIdIntToPtr:
242 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcIntToPtr *>(inst));242 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstIntToPtr *>(inst));
243 case IrInstSrcIdIntToEnum:243 case Stage1ZirInstIdIntToEnum:
244 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcIntToEnum *>(inst));244 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstIntToEnum *>(inst));
245 case IrInstSrcIdIntToErr:245 case Stage1ZirInstIdIntToErr:
246 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcIntToErr *>(inst));246 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstIntToErr *>(inst));
247 case IrInstSrcIdErrToInt:247 case Stage1ZirInstIdErrToInt:
248 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcErrToInt *>(inst));248 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstErrToInt *>(inst));
249 case IrInstSrcIdCheckSwitchProngsUnderNo:249 case Stage1ZirInstIdCheckSwitchProngsUnderNo:
250 case IrInstSrcIdCheckSwitchProngsUnderYes:250 case Stage1ZirInstIdCheckSwitchProngsUnderYes:
251 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCheckSwitchProngs *>(inst));251 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCheckSwitchProngs *>(inst));
252 case IrInstSrcIdCheckStatementIsVoid:252 case Stage1ZirInstIdCheckStatementIsVoid:
253 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCheckStatementIsVoid *>(inst));253 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCheckStatementIsVoid *>(inst));
254 case IrInstSrcIdTypeName:254 case Stage1ZirInstIdTypeName:
255 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTypeName *>(inst));255 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTypeName *>(inst));
256 case IrInstSrcIdTagName:256 case Stage1ZirInstIdTagName:
257 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTagName *>(inst));257 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTagName *>(inst));
258 case IrInstSrcIdPtrType:258 case Stage1ZirInstIdPtrType:
259 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPtrType *>(inst));259 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPtrType *>(inst));
260 case IrInstSrcIdPtrTypeSimple:260 case Stage1ZirInstIdPtrTypeSimple:
261 case IrInstSrcIdPtrTypeSimpleConst:261 case Stage1ZirInstIdPtrTypeSimpleConst:
262 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPtrTypeSimple *>(inst));262 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPtrTypeSimple *>(inst));
263 case IrInstSrcIdDeclRef:263 case Stage1ZirInstIdDeclRef:
264 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcDeclRef *>(inst));264 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstDeclRef *>(inst));
265 case IrInstSrcIdPanic:265 case Stage1ZirInstIdPanic:
266 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPanic *>(inst));266 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPanic *>(inst));
267 case IrInstSrcIdFieldParentPtr:267 case Stage1ZirInstIdFieldParentPtr:
268 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFieldParentPtr *>(inst));268 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFieldParentPtr *>(inst));
269 case IrInstSrcIdOffsetOf:269 case Stage1ZirInstIdOffsetOf:
270 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcOffsetOf *>(inst));270 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstOffsetOf *>(inst));
271 case IrInstSrcIdBitOffsetOf:271 case Stage1ZirInstIdBitOffsetOf:
272 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBitOffsetOf *>(inst));272 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBitOffsetOf *>(inst));
273 case IrInstSrcIdTypeInfo:273 case Stage1ZirInstIdTypeInfo:
274 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTypeInfo *>(inst));274 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTypeInfo *>(inst));
275 case IrInstSrcIdType:275 case Stage1ZirInstIdType:
276 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcType *>(inst));276 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstType *>(inst));
277 case IrInstSrcIdHasField:277 case Stage1ZirInstIdHasField:
278 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcHasField *>(inst));278 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstHasField *>(inst));
279 case IrInstSrcIdSetEvalBranchQuota:279 case Stage1ZirInstIdSetEvalBranchQuota:
280 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSetEvalBranchQuota *>(inst));280 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSetEvalBranchQuota *>(inst));
281 case IrInstSrcIdAlignCast:281 case Stage1ZirInstIdAlignCast:
282 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAlignCast *>(inst));282 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAlignCast *>(inst));
283 case IrInstSrcIdImplicitCast:283 case Stage1ZirInstIdImplicitCast:
284 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcImplicitCast *>(inst));284 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstImplicitCast *>(inst));
285 case IrInstSrcIdResolveResult:285 case Stage1ZirInstIdResolveResult:
286 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcResolveResult *>(inst));286 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstResolveResult *>(inst));
287 case IrInstSrcIdResetResult:287 case Stage1ZirInstIdResetResult:
288 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcResetResult *>(inst));288 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstResetResult *>(inst));
289 case IrInstSrcIdSetAlignStack:289 case Stage1ZirInstIdSetAlignStack:
290 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSetAlignStack *>(inst));290 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSetAlignStack *>(inst));
291 case IrInstSrcIdArgTypeAllowVarFalse:291 case Stage1ZirInstIdArgTypeAllowVarFalse:
292 case IrInstSrcIdArgTypeAllowVarTrue:292 case Stage1ZirInstIdArgTypeAllowVarTrue:
293 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcArgType *>(inst));293 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstArgType *>(inst));
294 case IrInstSrcIdExport:294 case Stage1ZirInstIdExport:
295 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcExport *>(inst));295 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstExport *>(inst));
296 case IrInstSrcIdExtern:296 case Stage1ZirInstIdExtern:
297 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcExtern *>(inst));297 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstExtern *>(inst));
298 case IrInstSrcIdErrorReturnTrace:298 case Stage1ZirInstIdErrorReturnTrace:
299 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcErrorReturnTrace *>(inst));299 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstErrorReturnTrace *>(inst));
300 case IrInstSrcIdErrorUnion:300 case Stage1ZirInstIdErrorUnion:
301 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcErrorUnion *>(inst));301 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstErrorUnion *>(inst));
302 case IrInstSrcIdAtomicRmw:302 case Stage1ZirInstIdAtomicRmw:
303 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAtomicRmw *>(inst));303 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAtomicRmw *>(inst));
304 case IrInstSrcIdSaveErrRetAddr:304 case Stage1ZirInstIdSaveErrRetAddr:
305 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSaveErrRetAddr *>(inst));305 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSaveErrRetAddr *>(inst));
306 case IrInstSrcIdAddImplicitReturnType:306 case Stage1ZirInstIdAddImplicitReturnType:
307 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAddImplicitReturnType *>(inst));307 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAddImplicitReturnType *>(inst));
308 case IrInstSrcIdFloatOp:308 case Stage1ZirInstIdFloatOp:
309 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFloatOp *>(inst));309 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFloatOp *>(inst));
310 case IrInstSrcIdMulAdd:310 case Stage1ZirInstIdMulAdd:
311 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcMulAdd *>(inst));311 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstMulAdd *>(inst));
312 case IrInstSrcIdAtomicLoad:312 case Stage1ZirInstIdAtomicLoad:
313 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAtomicLoad *>(inst));313 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAtomicLoad *>(inst));
314 case IrInstSrcIdAtomicStore:314 case Stage1ZirInstIdAtomicStore:
315 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAtomicStore *>(inst));315 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAtomicStore *>(inst));
316 case IrInstSrcIdEnumToInt:316 case Stage1ZirInstIdEnumToInt:
317 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcEnumToInt *>(inst));317 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstEnumToInt *>(inst));
318 case IrInstSrcIdCheckRuntimeScope:318 case Stage1ZirInstIdCheckRuntimeScope:
319 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCheckRuntimeScope *>(inst));319 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCheckRuntimeScope *>(inst));
320 case IrInstSrcIdHasDecl:320 case Stage1ZirInstIdHasDecl:
321 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcHasDecl *>(inst));321 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstHasDecl *>(inst));
322 case IrInstSrcIdUndeclaredIdent:322 case Stage1ZirInstIdUndeclaredIdent:
323 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUndeclaredIdent *>(inst));323 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUndeclaredIdent *>(inst));
324 case IrInstSrcIdAlloca:324 case Stage1ZirInstIdAlloca:
325 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAlloca *>(inst));325 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAlloca *>(inst));
326 case IrInstSrcIdEndExpr:326 case Stage1ZirInstIdEndExpr:
327 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcEndExpr *>(inst));327 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstEndExpr *>(inst));
328 case IrInstSrcIdUnionInitNamedField:328 case Stage1ZirInstIdUnionInitNamedField:
329 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUnionInitNamedField *>(inst));329 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUnionInitNamedField *>(inst));
330 case IrInstSrcIdSuspendBegin:330 case Stage1ZirInstIdSuspendBegin:
331 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSuspendBegin *>(inst));331 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSuspendBegin *>(inst));
332 case IrInstSrcIdSuspendFinish:332 case Stage1ZirInstIdSuspendFinish:
333 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSuspendFinish *>(inst));333 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSuspendFinish *>(inst));
334 case IrInstSrcIdResume:334 case Stage1ZirInstIdResume:
335 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcResume *>(inst));335 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstResume *>(inst));
336 case IrInstSrcIdAwait:336 case Stage1ZirInstIdAwait:
337 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAwait *>(inst));337 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAwait *>(inst));
338 case IrInstSrcIdSpillBegin:338 case Stage1ZirInstIdSpillBegin:
339 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSpillBegin *>(inst));339 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSpillBegin *>(inst));
340 case IrInstSrcIdSpillEnd:340 case Stage1ZirInstIdSpillEnd:
341 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSpillEnd *>(inst));341 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSpillEnd *>(inst));
342 case IrInstSrcIdCallArgs:342 case Stage1ZirInstIdCallArgs:
343 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCallArgs *>(inst));343 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCallArgs *>(inst));
344 case IrInstSrcIdWasmMemorySize:344 case Stage1ZirInstIdWasmMemorySize:
345 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcWasmMemorySize *>(inst));345 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstWasmMemorySize *>(inst));
346 case IrInstSrcIdWasmMemoryGrow:346 case Stage1ZirInstIdWasmMemoryGrow:
347 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcWasmMemoryGrow *>(inst));347 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstWasmMemoryGrow *>(inst));
348 case IrInstSrcIdSrc:348 case Stage1ZirInstIdSrc:
349 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSrc *>(inst));349 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSrc *>(inst));
350 }350 }
351 zig_unreachable();351 zig_unreachable();
352}352}
...@@ -368,7 +368,7 @@ bool ir_should_inline(Stage1Zir *exec, Scope *scope) {...@@ -368,7 +368,7 @@ bool ir_should_inline(Stage1Zir *exec, Scope *scope) {
368 return false;368 return false;
369}369}
370370
371static void ir_instruction_append(Stage1ZirBasicBlock *basic_block, IrInstSrc *instruction) {371static void ir_instruction_append(Stage1ZirBasicBlock *basic_block, Stage1ZirInst *instruction) {
372 assert(basic_block);372 assert(basic_block);
373 assert(instruction);373 assert(instruction);
374 basic_block->instruction_list.append(instruction);374 basic_block->instruction_list.append(instruction);
...@@ -384,11 +384,11 @@ static void ir_ref_bb(Stage1ZirBasicBlock *bb) {...@@ -384,11 +384,11 @@ static void ir_ref_bb(Stage1ZirBasicBlock *bb) {
384 bb->ref_count += 1;384 bb->ref_count += 1;
385}385}
386386
387static void ir_ref_instruction(IrInstSrc *instruction, Stage1ZirBasicBlock *cur_bb) {387static void ir_ref_instruction(Stage1ZirInst *instruction, Stage1ZirBasicBlock *cur_bb) {
388 assert(instruction->id != IrInstSrcIdInvalid);388 assert(instruction->id != Stage1ZirInstIdInvalid);
389 instruction->ref_count += 1;389 instruction->ref_count += 1;
390 if (instruction->owner_bb != cur_bb && !instr_is_unreachable(instruction)390 if (instruction->owner_bb != cur_bb && !instr_is_unreachable(instruction)
391 && instruction->id != IrInstSrcIdConst)391 && instruction->id != Stage1ZirInstIdConst)
392 {392 {
393 ir_ref_bb(instruction->owner_bb);393 ir_ref_bb(instruction->owner_bb);
394 }394 }
...@@ -403,536 +403,536 @@ static Stage1ZirBasicBlock *ir_create_basic_block(Stage1AstGen *ag, Scope *scope...@@ -403,536 +403,536 @@ static Stage1ZirBasicBlock *ir_create_basic_block(Stage1AstGen *ag, Scope *scope
403 return result;403 return result;
404}404}
405405
406static constexpr IrInstSrcId ir_inst_id(IrInstSrcDeclVar *) {406static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstDeclVar *) {
407 return IrInstSrcIdDeclVar;407 return Stage1ZirInstIdDeclVar;
408}408}
409409
410static constexpr IrInstSrcId ir_inst_id(IrInstSrcBr *) {410static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBr *) {
411 return IrInstSrcIdBr;411 return Stage1ZirInstIdBr;
412}412}
413413
414static constexpr IrInstSrcId ir_inst_id(IrInstSrcCondBr *) {414static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCondBr *) {
415 return IrInstSrcIdCondBr;415 return Stage1ZirInstIdCondBr;
416}416}
417417
418static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchBr *) {418static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchBr *) {
419 return IrInstSrcIdSwitchBr;419 return Stage1ZirInstIdSwitchBr;
420}420}
421421
422static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchVar *) {422static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchVar *) {
423 return IrInstSrcIdSwitchVar;423 return Stage1ZirInstIdSwitchVar;
424}424}
425425
426static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchElseVar *) {426static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchElseVar *) {
427 return IrInstSrcIdSwitchElseVar;427 return Stage1ZirInstIdSwitchElseVar;
428}428}
429429
430static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchTarget *) {430static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchTarget *) {
431 return IrInstSrcIdSwitchTarget;431 return Stage1ZirInstIdSwitchTarget;
432}432}
433433
434static constexpr IrInstSrcId ir_inst_id(IrInstSrcPhi *) {434static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPhi *) {
435 return IrInstSrcIdPhi;435 return Stage1ZirInstIdPhi;
436}436}
437437
438static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnOp *) {438static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnOp *) {
439 return IrInstSrcIdUnOp;439 return Stage1ZirInstIdUnOp;
440}440}
441441
442static constexpr IrInstSrcId ir_inst_id(IrInstSrcBinOp *) {442static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBinOp *) {
443 return IrInstSrcIdBinOp;443 return Stage1ZirInstIdBinOp;
444}444}
445445
446static constexpr IrInstSrcId ir_inst_id(IrInstSrcMergeErrSets *) {446static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMergeErrSets *) {
447 return IrInstSrcIdMergeErrSets;447 return Stage1ZirInstIdMergeErrSets;
448}448}
449449
450static constexpr IrInstSrcId ir_inst_id(IrInstSrcLoadPtr *) {450static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstLoadPtr *) {
451 return IrInstSrcIdLoadPtr;451 return Stage1ZirInstIdLoadPtr;
452}452}
453453
454static constexpr IrInstSrcId ir_inst_id(IrInstSrcStorePtr *) {454static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstStorePtr *) {
455 return IrInstSrcIdStorePtr;455 return Stage1ZirInstIdStorePtr;
456}456}
457457
458static constexpr IrInstSrcId ir_inst_id(IrInstSrcFieldPtr *) {458static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFieldPtr *) {
459 return IrInstSrcIdFieldPtr;459 return Stage1ZirInstIdFieldPtr;
460}460}
461461
462static constexpr IrInstSrcId ir_inst_id(IrInstSrcElemPtr *) {462static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstElemPtr *) {
463 return IrInstSrcIdElemPtr;463 return Stage1ZirInstIdElemPtr;
464}464}
465465
466static constexpr IrInstSrcId ir_inst_id(IrInstSrcVarPtr *) {466static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstVarPtr *) {
467 return IrInstSrcIdVarPtr;467 return Stage1ZirInstIdVarPtr;
468}468}
469469
470static constexpr IrInstSrcId ir_inst_id(IrInstSrcCall *) {470static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCall *) {
471 return IrInstSrcIdCall;471 return Stage1ZirInstIdCall;
472}472}
473473
474static constexpr IrInstSrcId ir_inst_id(IrInstSrcCallArgs *) {474static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCallArgs *) {
475 return IrInstSrcIdCallArgs;475 return Stage1ZirInstIdCallArgs;
476}476}
477477
478static constexpr IrInstSrcId ir_inst_id(IrInstSrcCallExtra *) {478static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCallExtra *) {
479 return IrInstSrcIdCallExtra;479 return Stage1ZirInstIdCallExtra;
480}480}
481481
482static constexpr IrInstSrcId ir_inst_id(IrInstSrcAsyncCallExtra *) {482static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAsyncCallExtra *) {
483 return IrInstSrcIdAsyncCallExtra;483 return Stage1ZirInstIdAsyncCallExtra;
484}484}
485485
486static constexpr IrInstSrcId ir_inst_id(IrInstSrcConst *) {486static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstConst *) {
487 return IrInstSrcIdConst;487 return Stage1ZirInstIdConst;
488}488}
489489
490static constexpr IrInstSrcId ir_inst_id(IrInstSrcReturn *) {490static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstReturn *) {
491 return IrInstSrcIdReturn;491 return Stage1ZirInstIdReturn;
492}492}
493493
494static constexpr IrInstSrcId ir_inst_id(IrInstSrcContainerInitList *) {494static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstContainerInitList *) {
495 return IrInstSrcIdContainerInitList;495 return Stage1ZirInstIdContainerInitList;
496}496}
497497
498static constexpr IrInstSrcId ir_inst_id(IrInstSrcContainerInitFields *) {498static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstContainerInitFields *) {
499 return IrInstSrcIdContainerInitFields;499 return Stage1ZirInstIdContainerInitFields;
500}500}
501501
502static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnreachable *) {502static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnreachable *) {
503 return IrInstSrcIdUnreachable;503 return Stage1ZirInstIdUnreachable;
504}504}
505505
506static constexpr IrInstSrcId ir_inst_id(IrInstSrcTypeOf *) {506static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTypeOf *) {
507 return IrInstSrcIdTypeOf;507 return Stage1ZirInstIdTypeOf;
508}508}
509509
510static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetCold *) {510static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetCold *) {
511 return IrInstSrcIdSetCold;511 return Stage1ZirInstIdSetCold;
512}512}
513513
514static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetRuntimeSafety *) {514static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetRuntimeSafety *) {
515 return IrInstSrcIdSetRuntimeSafety;515 return Stage1ZirInstIdSetRuntimeSafety;
516}516}
517517
518static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetFloatMode *) {518static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetFloatMode *) {
519 return IrInstSrcIdSetFloatMode;519 return Stage1ZirInstIdSetFloatMode;
520}520}
521521
522static constexpr IrInstSrcId ir_inst_id(IrInstSrcArrayType *) {522static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstArrayType *) {
523 return IrInstSrcIdArrayType;523 return Stage1ZirInstIdArrayType;
524}524}
525525
526static constexpr IrInstSrcId ir_inst_id(IrInstSrcAnyFrameType *) {526static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAnyFrameType *) {
527 return IrInstSrcIdAnyFrameType;527 return Stage1ZirInstIdAnyFrameType;
528}528}
529529
530static constexpr IrInstSrcId ir_inst_id(IrInstSrcSliceType *) {530static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSliceType *) {
531 return IrInstSrcIdSliceType;531 return Stage1ZirInstIdSliceType;
532}532}
533533
534static constexpr IrInstSrcId ir_inst_id(IrInstSrcAsm *) {534static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAsm *) {
535 return IrInstSrcIdAsm;535 return Stage1ZirInstIdAsm;
536}536}
537537
538static constexpr IrInstSrcId ir_inst_id(IrInstSrcSizeOf *) {538static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSizeOf *) {
539 return IrInstSrcIdSizeOf;539 return Stage1ZirInstIdSizeOf;
540}540}
541541
542static constexpr IrInstSrcId ir_inst_id(IrInstSrcTestNonNull *) {542static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTestNonNull *) {
543 return IrInstSrcIdTestNonNull;543 return Stage1ZirInstIdTestNonNull;
544}544}
545545
546static constexpr IrInstSrcId ir_inst_id(IrInstSrcOptionalUnwrapPtr *) {546static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstOptionalUnwrapPtr *) {
547 return IrInstSrcIdOptionalUnwrapPtr;547 return Stage1ZirInstIdOptionalUnwrapPtr;
548}548}
549549
550static constexpr IrInstSrcId ir_inst_id(IrInstSrcClz *) {550static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstClz *) {
551 return IrInstSrcIdClz;551 return Stage1ZirInstIdClz;
552}552}
553553
554static constexpr IrInstSrcId ir_inst_id(IrInstSrcCtz *) {554static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCtz *) {
555 return IrInstSrcIdCtz;555 return Stage1ZirInstIdCtz;
556}556}
557557
558static constexpr IrInstSrcId ir_inst_id(IrInstSrcPopCount *) {558static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPopCount *) {
559 return IrInstSrcIdPopCount;559 return Stage1ZirInstIdPopCount;
560}560}
561561
562static constexpr IrInstSrcId ir_inst_id(IrInstSrcBswap *) {562static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBswap *) {
563 return IrInstSrcIdBswap;563 return Stage1ZirInstIdBswap;
564}564}
565565
566static constexpr IrInstSrcId ir_inst_id(IrInstSrcBitReverse *) {566static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBitReverse *) {
567 return IrInstSrcIdBitReverse;567 return Stage1ZirInstIdBitReverse;
568}568}
569569
570static constexpr IrInstSrcId ir_inst_id(IrInstSrcImport *) {570static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstImport *) {
571 return IrInstSrcIdImport;571 return Stage1ZirInstIdImport;
572}572}
573573
574static constexpr IrInstSrcId ir_inst_id(IrInstSrcCImport *) {574static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCImport *) {
575 return IrInstSrcIdCImport;575 return Stage1ZirInstIdCImport;
576}576}
577577
578static constexpr IrInstSrcId ir_inst_id(IrInstSrcCInclude *) {578static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCInclude *) {
579 return IrInstSrcIdCInclude;579 return Stage1ZirInstIdCInclude;
580}580}
581581
582static constexpr IrInstSrcId ir_inst_id(IrInstSrcCDefine *) {582static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCDefine *) {
583 return IrInstSrcIdCDefine;583 return Stage1ZirInstIdCDefine;
584}584}
585585
586static constexpr IrInstSrcId ir_inst_id(IrInstSrcCUndef *) {586static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCUndef *) {
587 return IrInstSrcIdCUndef;587 return Stage1ZirInstIdCUndef;
588}588}
589589
590static constexpr IrInstSrcId ir_inst_id(IrInstSrcRef *) {590static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstRef *) {
591 return IrInstSrcIdRef;591 return Stage1ZirInstIdRef;
592}592}
593593
594static constexpr IrInstSrcId ir_inst_id(IrInstSrcCompileErr *) {594static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCompileErr *) {
595 return IrInstSrcIdCompileErr;595 return Stage1ZirInstIdCompileErr;
596}596}
597597
598static constexpr IrInstSrcId ir_inst_id(IrInstSrcCompileLog *) {598static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCompileLog *) {
599 return IrInstSrcIdCompileLog;599 return Stage1ZirInstIdCompileLog;
600}600}
601601
602static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrName *) {602static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrName *) {
603 return IrInstSrcIdErrName;603 return Stage1ZirInstIdErrName;
604}604}
605605
606static constexpr IrInstSrcId ir_inst_id(IrInstSrcEmbedFile *) {606static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstEmbedFile *) {
607 return IrInstSrcIdEmbedFile;607 return Stage1ZirInstIdEmbedFile;
608}608}
609609
610static constexpr IrInstSrcId ir_inst_id(IrInstSrcCmpxchg *) {610static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCmpxchg *) {
611 return IrInstSrcIdCmpxchg;611 return Stage1ZirInstIdCmpxchg;
612}612}
613613
614static constexpr IrInstSrcId ir_inst_id(IrInstSrcFence *) {614static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFence *) {
615 return IrInstSrcIdFence;615 return Stage1ZirInstIdFence;
616}616}
617617
618static constexpr IrInstSrcId ir_inst_id(IrInstSrcReduce *) {618static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstReduce *) {
619 return IrInstSrcIdReduce;619 return Stage1ZirInstIdReduce;
620}620}
621621
622static constexpr IrInstSrcId ir_inst_id(IrInstSrcTruncate *) {622static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTruncate *) {
623 return IrInstSrcIdTruncate;623 return Stage1ZirInstIdTruncate;
624}624}
625625
626static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntCast *) {626static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntCast *) {
627 return IrInstSrcIdIntCast;627 return Stage1ZirInstIdIntCast;
628}628}
629629
630static constexpr IrInstSrcId ir_inst_id(IrInstSrcFloatCast *) {630static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFloatCast *) {
631 return IrInstSrcIdFloatCast;631 return Stage1ZirInstIdFloatCast;
632}632}
633633
634static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToFloat *) {634static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToFloat *) {
635 return IrInstSrcIdIntToFloat;635 return Stage1ZirInstIdIntToFloat;
636}636}
637637
638static constexpr IrInstSrcId ir_inst_id(IrInstSrcFloatToInt *) {638static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFloatToInt *) {
639 return IrInstSrcIdFloatToInt;639 return Stage1ZirInstIdFloatToInt;
640}640}
641641
642static constexpr IrInstSrcId ir_inst_id(IrInstSrcBoolToInt *) {642static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBoolToInt *) {
643 return IrInstSrcIdBoolToInt;643 return Stage1ZirInstIdBoolToInt;
644}644}
645645
646static constexpr IrInstSrcId ir_inst_id(IrInstSrcVectorType *) {646static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstVectorType *) {
647 return IrInstSrcIdVectorType;647 return Stage1ZirInstIdVectorType;
648}648}
649649
650static constexpr IrInstSrcId ir_inst_id(IrInstSrcShuffleVector *) {650static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstShuffleVector *) {
651 return IrInstSrcIdShuffleVector;651 return Stage1ZirInstIdShuffleVector;
652}652}
653653
654static constexpr IrInstSrcId ir_inst_id(IrInstSrcSplat *) {654static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSplat *) {
655 return IrInstSrcIdSplat;655 return Stage1ZirInstIdSplat;
656}656}
657657
658static constexpr IrInstSrcId ir_inst_id(IrInstSrcBoolNot *) {658static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBoolNot *) {
659 return IrInstSrcIdBoolNot;659 return Stage1ZirInstIdBoolNot;
660}660}
661661
662static constexpr IrInstSrcId ir_inst_id(IrInstSrcMemset *) {662static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMemset *) {
663 return IrInstSrcIdMemset;663 return Stage1ZirInstIdMemset;
664}664}
665665
666static constexpr IrInstSrcId ir_inst_id(IrInstSrcMemcpy *) {666static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMemcpy *) {
667 return IrInstSrcIdMemcpy;667 return Stage1ZirInstIdMemcpy;
668}668}
669669
670static constexpr IrInstSrcId ir_inst_id(IrInstSrcSlice *) {670static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSlice *) {
671 return IrInstSrcIdSlice;671 return Stage1ZirInstIdSlice;
672}672}
673673
674static constexpr IrInstSrcId ir_inst_id(IrInstSrcBreakpoint *) {674static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBreakpoint *) {
675 return IrInstSrcIdBreakpoint;675 return Stage1ZirInstIdBreakpoint;
676}676}
677677
678static constexpr IrInstSrcId ir_inst_id(IrInstSrcReturnAddress *) {678static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstReturnAddress *) {
679 return IrInstSrcIdReturnAddress;679 return Stage1ZirInstIdReturnAddress;
680}680}
681681
682static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameAddress *) {682static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameAddress *) {
683 return IrInstSrcIdFrameAddress;683 return Stage1ZirInstIdFrameAddress;
684}684}
685685
686static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameHandle *) {686static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameHandle *) {
687 return IrInstSrcIdFrameHandle;687 return Stage1ZirInstIdFrameHandle;
688}688}
689689
690static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameType *) {690static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameType *) {
691 return IrInstSrcIdFrameType;691 return Stage1ZirInstIdFrameType;
692}692}
693693
694static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameSize *) {694static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameSize *) {
695 return IrInstSrcIdFrameSize;695 return Stage1ZirInstIdFrameSize;
696}696}
697697
698static constexpr IrInstSrcId ir_inst_id(IrInstSrcAlignOf *) {698static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAlignOf *) {
699 return IrInstSrcIdAlignOf;699 return Stage1ZirInstIdAlignOf;
700}700}
701701
702static constexpr IrInstSrcId ir_inst_id(IrInstSrcOverflowOp *) {702static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstOverflowOp *) {
703 return IrInstSrcIdOverflowOp;703 return Stage1ZirInstIdOverflowOp;
704}704}
705705
706static constexpr IrInstSrcId ir_inst_id(IrInstSrcTestErr *) {706static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTestErr *) {
707 return IrInstSrcIdTestErr;707 return Stage1ZirInstIdTestErr;
708}708}
709709
710static constexpr IrInstSrcId ir_inst_id(IrInstSrcMulAdd *) {710static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMulAdd *) {
711 return IrInstSrcIdMulAdd;711 return Stage1ZirInstIdMulAdd;
712}712}
713713
714static constexpr IrInstSrcId ir_inst_id(IrInstSrcFloatOp *) {714static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFloatOp *) {
715 return IrInstSrcIdFloatOp;715 return Stage1ZirInstIdFloatOp;
716}716}
717717
718static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnwrapErrCode *) {718static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnwrapErrCode *) {
719 return IrInstSrcIdUnwrapErrCode;719 return Stage1ZirInstIdUnwrapErrCode;
720}720}
721721
722static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnwrapErrPayload *) {722static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnwrapErrPayload *) {
723 return IrInstSrcIdUnwrapErrPayload;723 return Stage1ZirInstIdUnwrapErrPayload;
724}724}
725725
726static constexpr IrInstSrcId ir_inst_id(IrInstSrcFnProto *) {726static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFnProto *) {
727 return IrInstSrcIdFnProto;727 return Stage1ZirInstIdFnProto;
728}728}
729729
730static constexpr IrInstSrcId ir_inst_id(IrInstSrcTestComptime *) {730static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTestComptime *) {
731 return IrInstSrcIdTestComptime;731 return Stage1ZirInstIdTestComptime;
732}732}
733733
734static constexpr IrInstSrcId ir_inst_id(IrInstSrcPtrCast *) {734static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPtrCast *) {
735 return IrInstSrcIdPtrCast;735 return Stage1ZirInstIdPtrCast;
736}736}
737737
738static constexpr IrInstSrcId ir_inst_id(IrInstSrcBitCast *) {738static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBitCast *) {
739 return IrInstSrcIdBitCast;739 return Stage1ZirInstIdBitCast;
740}740}
741741
742static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToPtr *) {742static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToPtr *) {
743 return IrInstSrcIdIntToPtr;743 return Stage1ZirInstIdIntToPtr;
744}744}
745745
746static constexpr IrInstSrcId ir_inst_id(IrInstSrcPtrToInt *) {746static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPtrToInt *) {
747 return IrInstSrcIdPtrToInt;747 return Stage1ZirInstIdPtrToInt;
748}748}
749749
750static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToEnum *) {750static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToEnum *) {
751 return IrInstSrcIdIntToEnum;751 return Stage1ZirInstIdIntToEnum;
752}752}
753753
754static constexpr IrInstSrcId ir_inst_id(IrInstSrcEnumToInt *) {754static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstEnumToInt *) {
755 return IrInstSrcIdEnumToInt;755 return Stage1ZirInstIdEnumToInt;
756}756}
757757
758static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToErr *) {758static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToErr *) {
759 return IrInstSrcIdIntToErr;759 return Stage1ZirInstIdIntToErr;
760}760}
761761
762static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrToInt *) {762static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrToInt *) {
763 return IrInstSrcIdErrToInt;763 return Stage1ZirInstIdErrToInt;
764}764}
765765
766static constexpr IrInstSrcId ir_inst_id(IrInstSrcCheckStatementIsVoid *) {766static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCheckStatementIsVoid *) {
767 return IrInstSrcIdCheckStatementIsVoid;767 return Stage1ZirInstIdCheckStatementIsVoid;
768}768}
769769
770static constexpr IrInstSrcId ir_inst_id(IrInstSrcTypeName *) {770static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTypeName *) {
771 return IrInstSrcIdTypeName;771 return Stage1ZirInstIdTypeName;
772}772}
773773
774static constexpr IrInstSrcId ir_inst_id(IrInstSrcDeclRef *) {774static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstDeclRef *) {
775 return IrInstSrcIdDeclRef;775 return Stage1ZirInstIdDeclRef;
776}776}
777777
778static constexpr IrInstSrcId ir_inst_id(IrInstSrcPanic *) {778static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPanic *) {
779 return IrInstSrcIdPanic;779 return Stage1ZirInstIdPanic;
780}780}
781781
782static constexpr IrInstSrcId ir_inst_id(IrInstSrcTagName *) {782static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTagName *) {
783 return IrInstSrcIdTagName;783 return Stage1ZirInstIdTagName;
784}784}
785785
786static constexpr IrInstSrcId ir_inst_id(IrInstSrcFieldParentPtr *) {786static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFieldParentPtr *) {
787 return IrInstSrcIdFieldParentPtr;787 return Stage1ZirInstIdFieldParentPtr;
788}788}
789789
790static constexpr IrInstSrcId ir_inst_id(IrInstSrcOffsetOf *) {790static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstOffsetOf *) {
791 return IrInstSrcIdOffsetOf;791 return Stage1ZirInstIdOffsetOf;
792}792}
793793
794static constexpr IrInstSrcId ir_inst_id(IrInstSrcBitOffsetOf *) {794static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBitOffsetOf *) {
795 return IrInstSrcIdBitOffsetOf;795 return Stage1ZirInstIdBitOffsetOf;
796}796}
797797
798static constexpr IrInstSrcId ir_inst_id(IrInstSrcTypeInfo *) {798static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTypeInfo *) {
799 return IrInstSrcIdTypeInfo;799 return Stage1ZirInstIdTypeInfo;
800}800}
801801
802static constexpr IrInstSrcId ir_inst_id(IrInstSrcType *) {802static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstType *) {
803 return IrInstSrcIdType;803 return Stage1ZirInstIdType;
804}804}
805805
806static constexpr IrInstSrcId ir_inst_id(IrInstSrcHasField *) {806static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstHasField *) {
807 return IrInstSrcIdHasField;807 return Stage1ZirInstIdHasField;
808}808}
809809
810static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetEvalBranchQuota *) {810static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetEvalBranchQuota *) {
811 return IrInstSrcIdSetEvalBranchQuota;811 return Stage1ZirInstIdSetEvalBranchQuota;
812}812}
813813
814static constexpr IrInstSrcId ir_inst_id(IrInstSrcPtrType *) {814static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPtrType *) {
815 return IrInstSrcIdPtrType;815 return Stage1ZirInstIdPtrType;
816}816}
817817
818static constexpr IrInstSrcId ir_inst_id(IrInstSrcAlignCast *) {818static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAlignCast *) {
819 return IrInstSrcIdAlignCast;819 return Stage1ZirInstIdAlignCast;
820}820}
821821
822static constexpr IrInstSrcId ir_inst_id(IrInstSrcImplicitCast *) {822static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstImplicitCast *) {
823 return IrInstSrcIdImplicitCast;823 return Stage1ZirInstIdImplicitCast;
824}824}
825825
826static constexpr IrInstSrcId ir_inst_id(IrInstSrcResolveResult *) {826static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstResolveResult *) {
827 return IrInstSrcIdResolveResult;827 return Stage1ZirInstIdResolveResult;
828}828}
829829
830static constexpr IrInstSrcId ir_inst_id(IrInstSrcResetResult *) {830static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstResetResult *) {
831 return IrInstSrcIdResetResult;831 return Stage1ZirInstIdResetResult;
832}832}
833833
834static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetAlignStack *) {834static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetAlignStack *) {
835 return IrInstSrcIdSetAlignStack;835 return Stage1ZirInstIdSetAlignStack;
836}836}
837837
838static constexpr IrInstSrcId ir_inst_id(IrInstSrcExport *) {838static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstExport *) {
839 return IrInstSrcIdExport;839 return Stage1ZirInstIdExport;
840}840}
841841
842static constexpr IrInstSrcId ir_inst_id(IrInstSrcExtern *) {842static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstExtern *) {
843 return IrInstSrcIdExtern;843 return Stage1ZirInstIdExtern;
844}844}
845845
846static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrorReturnTrace *) {846static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrorReturnTrace *) {
847 return IrInstSrcIdErrorReturnTrace;847 return Stage1ZirInstIdErrorReturnTrace;
848}848}
849849
850static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrorUnion *) {850static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrorUnion *) {
851 return IrInstSrcIdErrorUnion;851 return Stage1ZirInstIdErrorUnion;
852}852}
853853
854static constexpr IrInstSrcId ir_inst_id(IrInstSrcAtomicRmw *) {854static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAtomicRmw *) {
855 return IrInstSrcIdAtomicRmw;855 return Stage1ZirInstIdAtomicRmw;
856}856}
857857
858static constexpr IrInstSrcId ir_inst_id(IrInstSrcAtomicLoad *) {858static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAtomicLoad *) {
859 return IrInstSrcIdAtomicLoad;859 return Stage1ZirInstIdAtomicLoad;
860}860}
861861
862static constexpr IrInstSrcId ir_inst_id(IrInstSrcAtomicStore *) {862static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAtomicStore *) {
863 return IrInstSrcIdAtomicStore;863 return Stage1ZirInstIdAtomicStore;
864}864}
865865
866static constexpr IrInstSrcId ir_inst_id(IrInstSrcSaveErrRetAddr *) {866static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSaveErrRetAddr *) {
867 return IrInstSrcIdSaveErrRetAddr;867 return Stage1ZirInstIdSaveErrRetAddr;
868}868}
869869
870static constexpr IrInstSrcId ir_inst_id(IrInstSrcAddImplicitReturnType *) {870static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAddImplicitReturnType *) {
871 return IrInstSrcIdAddImplicitReturnType;871 return Stage1ZirInstIdAddImplicitReturnType;
872}872}
873873
874static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrSetCast *) {874static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrSetCast *) {
875 return IrInstSrcIdErrSetCast;875 return Stage1ZirInstIdErrSetCast;
876}876}
877877
878static constexpr IrInstSrcId ir_inst_id(IrInstSrcCheckRuntimeScope *) {878static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCheckRuntimeScope *) {
879 return IrInstSrcIdCheckRuntimeScope;879 return Stage1ZirInstIdCheckRuntimeScope;
880}880}
881881
882static constexpr IrInstSrcId ir_inst_id(IrInstSrcHasDecl *) {882static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstHasDecl *) {
883 return IrInstSrcIdHasDecl;883 return Stage1ZirInstIdHasDecl;
884}884}
885885
886static constexpr IrInstSrcId ir_inst_id(IrInstSrcUndeclaredIdent *) {886static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUndeclaredIdent *) {
887 return IrInstSrcIdUndeclaredIdent;887 return Stage1ZirInstIdUndeclaredIdent;
888}888}
889889
890static constexpr IrInstSrcId ir_inst_id(IrInstSrcAlloca *) {890static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAlloca *) {
891 return IrInstSrcIdAlloca;891 return Stage1ZirInstIdAlloca;
892}892}
893893
894static constexpr IrInstSrcId ir_inst_id(IrInstSrcEndExpr *) {894static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstEndExpr *) {
895 return IrInstSrcIdEndExpr;895 return Stage1ZirInstIdEndExpr;
896}896}
897897
898static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnionInitNamedField *) {898static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnionInitNamedField *) {
899 return IrInstSrcIdUnionInitNamedField;899 return Stage1ZirInstIdUnionInitNamedField;
900}900}
901901
902static constexpr IrInstSrcId ir_inst_id(IrInstSrcSuspendBegin *) {902static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSuspendBegin *) {
903 return IrInstSrcIdSuspendBegin;903 return Stage1ZirInstIdSuspendBegin;
904}904}
905905
906static constexpr IrInstSrcId ir_inst_id(IrInstSrcSuspendFinish *) {906static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSuspendFinish *) {
907 return IrInstSrcIdSuspendFinish;907 return Stage1ZirInstIdSuspendFinish;
908}908}
909909
910static constexpr IrInstSrcId ir_inst_id(IrInstSrcAwait *) {910static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAwait *) {
911 return IrInstSrcIdAwait;911 return Stage1ZirInstIdAwait;
912}912}
913913
914static constexpr IrInstSrcId ir_inst_id(IrInstSrcResume *) {914static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstResume *) {
915 return IrInstSrcIdResume;915 return Stage1ZirInstIdResume;
916}916}
917917
918static constexpr IrInstSrcId ir_inst_id(IrInstSrcSpillBegin *) {918static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSpillBegin *) {
919 return IrInstSrcIdSpillBegin;919 return Stage1ZirInstIdSpillBegin;
920}920}
921921
922static constexpr IrInstSrcId ir_inst_id(IrInstSrcSpillEnd *) {922static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSpillEnd *) {
923 return IrInstSrcIdSpillEnd;923 return Stage1ZirInstIdSpillEnd;
924}924}
925925
926static constexpr IrInstSrcId ir_inst_id(IrInstSrcWasmMemorySize *) {926static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstWasmMemorySize *) {
927 return IrInstSrcIdWasmMemorySize;927 return Stage1ZirInstIdWasmMemorySize;
928}928}
929929
930static constexpr IrInstSrcId ir_inst_id(IrInstSrcWasmMemoryGrow *) {930static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstWasmMemoryGrow *) {
931 return IrInstSrcIdWasmMemoryGrow;931 return Stage1ZirInstIdWasmMemoryGrow;
932}932}
933933
934static constexpr IrInstSrcId ir_inst_id(IrInstSrcSrc *) {934static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSrc *) {
935 return IrInstSrcIdSrc;935 return Stage1ZirInstIdSrc;
936}936}
937937
938template<typename T>938template<typename T>
...@@ -953,10 +953,10 @@ static T *ir_build_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_n...@@ -953,10 +953,10 @@ static T *ir_build_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_n
953 return special_instruction;953 return special_instruction;
954}954}
955955
956static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *condition,956static Stage1ZirInst *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *condition,
957 Stage1ZirBasicBlock *then_block, Stage1ZirBasicBlock *else_block, IrInstSrc *is_comptime)957 Stage1ZirBasicBlock *then_block, Stage1ZirBasicBlock *else_block, Stage1ZirInst *is_comptime)
958{958{
959 IrInstSrcCondBr *inst = ir_build_instruction<IrInstSrcCondBr>(ag, scope, source_node);959 Stage1ZirInstCondBr *inst = ir_build_instruction<Stage1ZirInstCondBr>(ag, scope, source_node);
960 inst->condition = condition;960 inst->condition = condition;
961 inst->then_block = then_block;961 inst->then_block = then_block;
962 inst->else_block = else_block;962 inst->else_block = else_block;
...@@ -970,8 +970,8 @@ static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *sour...@@ -970,8 +970,8 @@ static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *sour
970 return &inst->base;970 return &inst->base;
971}971}
972972
973static IrInstSrc *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *operand) {973static Stage1ZirInst *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *operand) {
974 IrInstSrcReturn *inst = ir_build_instruction<IrInstSrcReturn>(ag, scope, source_node);974 Stage1ZirInstReturn *inst = ir_build_instruction<Stage1ZirInstReturn>(ag, scope, source_node);
975 inst->operand = operand;975 inst->operand = operand;
976976
977 if (operand != nullptr) ir_ref_instruction(operand, ag->current_basic_block);977 if (operand != nullptr) ir_ref_instruction(operand, ag->current_basic_block);
...@@ -979,23 +979,23 @@ static IrInstSrc *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -979,23 +979,23 @@ static IrInstSrc *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *s
979 return &inst->base;979 return &inst->base;
980}980}
981981
982static IrInstSrc *ir_build_const_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {982static Stage1ZirInst *ir_build_const_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
983 IrInstSrcConst *const_instruction = ir_create_instruction<IrInstSrcConst>(ag, scope, source_node);983 Stage1ZirInstConst *const_instruction = ir_create_instruction<Stage1ZirInstConst>(ag, scope, source_node);
984 ir_instruction_append(ag->current_basic_block, &const_instruction->base);984 ir_instruction_append(ag->current_basic_block, &const_instruction->base);
985 const_instruction->value = ag->codegen->intern.for_void();985 const_instruction->value = ag->codegen->intern.for_void();
986 return &const_instruction->base;986 return &const_instruction->base;
987}987}
988988
989static IrInstSrc *ir_build_const_undefined(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {989static Stage1ZirInst *ir_build_const_undefined(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
990 IrInstSrcConst *const_instruction = ir_create_instruction<IrInstSrcConst>(ag, scope, source_node);990 Stage1ZirInstConst *const_instruction = ir_create_instruction<Stage1ZirInstConst>(ag, scope, source_node);
991 ir_instruction_append(ag->current_basic_block, &const_instruction->base);991 ir_instruction_append(ag->current_basic_block, &const_instruction->base);
992 const_instruction->value = ag->codegen->intern.for_undefined();992 const_instruction->value = ag->codegen->intern.for_undefined();
993 const_instruction->value->special = ConstValSpecialUndef;993 const_instruction->value->special = ConstValSpecialUndef;
994 return &const_instruction->base;994 return &const_instruction->base;
995}995}
996996
997static IrInstSrc *ir_build_const_uint(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) {997static Stage1ZirInst *ir_build_const_uint(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) {
998 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);998 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
999 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();999 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
1000 const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_int;1000 const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_int;
1001 const_instruction->value->special = ConstValSpecialStatic;1001 const_instruction->value->special = ConstValSpecialStatic;
...@@ -1003,10 +1003,10 @@ static IrInstSrc *ir_build_const_uint(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -1003,10 +1003,10 @@ static IrInstSrc *ir_build_const_uint(Stage1AstGen *ag, Scope *scope, AstNode *s
1003 return &const_instruction->base;1003 return &const_instruction->base;
1004}1004}
10051005
1006static IrInstSrc *ir_build_const_bigint(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1006static Stage1ZirInst *ir_build_const_bigint(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1007 BigInt bigint)1007 BigInt bigint)
1008{1008{
1009 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);1009 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
1010 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();1010 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
1011 const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_int;1011 const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_int;
1012 const_instruction->value->special = ConstValSpecialStatic;1012 const_instruction->value->special = ConstValSpecialStatic;
...@@ -1014,10 +1014,10 @@ static IrInstSrc *ir_build_const_bigint(Stage1AstGen *ag, Scope *scope, AstNode...@@ -1014,10 +1014,10 @@ static IrInstSrc *ir_build_const_bigint(Stage1AstGen *ag, Scope *scope, AstNode
1014 return &const_instruction->base;1014 return &const_instruction->base;
1015}1015}
10161016
1017static IrInstSrc *ir_build_const_bigfloat(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1017static Stage1ZirInst *ir_build_const_bigfloat(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1018 BigFloat bigfloat)1018 BigFloat bigfloat)
1019{1019{
1020 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);1020 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
1021 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();1021 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
1022 const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_float;1022 const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_float;
1023 const_instruction->value->special = ConstValSpecialStatic;1023 const_instruction->value->special = ConstValSpecialStatic;
...@@ -1025,15 +1025,15 @@ static IrInstSrc *ir_build_const_bigfloat(Stage1AstGen *ag, Scope *scope, AstNod...@@ -1025,15 +1025,15 @@ static IrInstSrc *ir_build_const_bigfloat(Stage1AstGen *ag, Scope *scope, AstNod
1025 return &const_instruction->base;1025 return &const_instruction->base;
1026}1026}
10271027
1028static IrInstSrc *ir_build_const_null(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {1028static Stage1ZirInst *ir_build_const_null(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
1029 IrInstSrcConst *const_instruction = ir_create_instruction<IrInstSrcConst>(ag, scope, source_node);1029 Stage1ZirInstConst *const_instruction = ir_create_instruction<Stage1ZirInstConst>(ag, scope, source_node);
1030 ir_instruction_append(ag->current_basic_block, &const_instruction->base);1030 ir_instruction_append(ag->current_basic_block, &const_instruction->base);
1031 const_instruction->value = ag->codegen->intern.for_null();1031 const_instruction->value = ag->codegen->intern.for_null();
1032 return &const_instruction->base;1032 return &const_instruction->base;
1033}1033}
10341034
1035static IrInstSrc *ir_build_const_usize(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) {1035static Stage1ZirInst *ir_build_const_usize(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) {
1036 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);1036 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
1037 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();1037 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
1038 const_instruction->value->type = ag->codegen->builtin_types.entry_usize;1038 const_instruction->value->type = ag->codegen->builtin_types.entry_usize;
1039 const_instruction->value->special = ConstValSpecialStatic;1039 const_instruction->value->special = ConstValSpecialStatic;
...@@ -1041,10 +1041,10 @@ static IrInstSrc *ir_build_const_usize(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -1041,10 +1041,10 @@ static IrInstSrc *ir_build_const_usize(Stage1AstGen *ag, Scope *scope, AstNode *
1041 return &const_instruction->base;1041 return &const_instruction->base;
1042}1042}
10431043
1044static IrInstSrc *ir_create_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1044static Stage1ZirInst *ir_create_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1045 ZigType *type_entry)1045 ZigType *type_entry)
1046{1046{
1047 IrInstSrcConst *const_instruction = ir_create_instruction<IrInstSrcConst>(ag, scope, source_node);1047 Stage1ZirInstConst *const_instruction = ir_create_instruction<Stage1ZirInstConst>(ag, scope, source_node);
1048 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();1048 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
1049 const_instruction->value->type = ag->codegen->builtin_types.entry_type;1049 const_instruction->value->type = ag->codegen->builtin_types.entry_type;
1050 const_instruction->value->special = ConstValSpecialStatic;1050 const_instruction->value->special = ConstValSpecialStatic;
...@@ -1052,16 +1052,16 @@ static IrInstSrc *ir_create_const_type(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -1052,16 +1052,16 @@ static IrInstSrc *ir_create_const_type(Stage1AstGen *ag, Scope *scope, AstNode *
1052 return &const_instruction->base;1052 return &const_instruction->base;
1053}1053}
10541054
1055static IrInstSrc *ir_build_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1055static Stage1ZirInst *ir_build_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1056 ZigType *type_entry)1056 ZigType *type_entry)
1057{1057{
1058 IrInstSrc *instruction = ir_create_const_type(ag, scope, source_node, type_entry);1058 Stage1ZirInst *instruction = ir_create_const_type(ag, scope, source_node, type_entry);
1059 ir_instruction_append(ag->current_basic_block, instruction);1059 ir_instruction_append(ag->current_basic_block, instruction);
1060 return instruction;1060 return instruction;
1061}1061}
10621062
1063static IrInstSrc *ir_build_const_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigType *import) {1063static Stage1ZirInst *ir_build_const_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigType *import) {
1064 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);1064 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
1065 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();1065 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
1066 const_instruction->value->type = ag->codegen->builtin_types.entry_type;1066 const_instruction->value->type = ag->codegen->builtin_types.entry_type;
1067 const_instruction->value->special = ConstValSpecialStatic;1067 const_instruction->value->special = ConstValSpecialStatic;
...@@ -1069,8 +1069,8 @@ static IrInstSrc *ir_build_const_import(Stage1AstGen *ag, Scope *scope, AstNode...@@ -1069,8 +1069,8 @@ static IrInstSrc *ir_build_const_import(Stage1AstGen *ag, Scope *scope, AstNode
1069 return &const_instruction->base;1069 return &const_instruction->base;
1070}1070}
10711071
1072static IrInstSrc *ir_build_const_bool(Stage1AstGen *ag, Scope *scope, AstNode *source_node, bool value) {1072static Stage1ZirInst *ir_build_const_bool(Stage1AstGen *ag, Scope *scope, AstNode *source_node, bool value) {
1073 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);1073 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
1074 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();1074 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
1075 const_instruction->value->type = ag->codegen->builtin_types.entry_bool;1075 const_instruction->value->type = ag->codegen->builtin_types.entry_bool;
1076 const_instruction->value->special = ConstValSpecialStatic;1076 const_instruction->value->special = ConstValSpecialStatic;
...@@ -1078,8 +1078,8 @@ static IrInstSrc *ir_build_const_bool(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -1078,8 +1078,8 @@ static IrInstSrc *ir_build_const_bool(Stage1AstGen *ag, Scope *scope, AstNode *s
1078 return &const_instruction->base;1078 return &const_instruction->base;
1079}1079}
10801080
1081static IrInstSrc *ir_build_const_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) {1081static Stage1ZirInst *ir_build_const_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) {
1082 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);1082 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
1083 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();1083 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
1084 const_instruction->value->type = ag->codegen->builtin_types.entry_enum_literal;1084 const_instruction->value->type = ag->codegen->builtin_types.entry_enum_literal;
1085 const_instruction->value->special = ConstValSpecialStatic;1085 const_instruction->value->special = ConstValSpecialStatic;
...@@ -1088,8 +1088,8 @@ static IrInstSrc *ir_build_const_enum_literal(Stage1AstGen *ag, Scope *scope, As...@@ -1088,8 +1088,8 @@ static IrInstSrc *ir_build_const_enum_literal(Stage1AstGen *ag, Scope *scope, As
1088}1088}
10891089
1090// Consumes `str`.1090// Consumes `str`.
1091static IrInstSrc *ir_create_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) {1091static Stage1ZirInst *ir_create_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) {
1092 IrInstSrcConst *const_instruction = ir_create_instruction<IrInstSrcConst>(ag, scope, source_node);1092 Stage1ZirInstConst *const_instruction = ir_create_instruction<Stage1ZirInstConst>(ag, scope, source_node);
1093 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();1093 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
1094 init_const_str_lit(ag->codegen, const_instruction->value, str, true);1094 init_const_str_lit(ag->codegen, const_instruction->value, str, true);
10951095
...@@ -1097,16 +1097,16 @@ static IrInstSrc *ir_create_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNod...@@ -1097,16 +1097,16 @@ static IrInstSrc *ir_create_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNod
1097}1097}
10981098
1099// Consumes `str`.1099// Consumes `str`.
1100static IrInstSrc *ir_build_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) {1100static Stage1ZirInst *ir_build_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) {
1101 IrInstSrc *instruction = ir_create_const_str_lit(ag, scope, source_node, str);1101 Stage1ZirInst *instruction = ir_create_const_str_lit(ag, scope, source_node, str);
1102 ir_instruction_append(ag->current_basic_block, instruction);1102 ir_instruction_append(ag->current_basic_block, instruction);
1103 return instruction;1103 return instruction;
1104}1104}
11051105
1106static IrInstSrc *ir_build_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrBinOp op_id,1106static Stage1ZirInst *ir_build_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrBinOp op_id,
1107 IrInstSrc *op1, IrInstSrc *op2, bool safety_check_on)1107 Stage1ZirInst *op1, Stage1ZirInst *op2, bool safety_check_on)
1108{1108{
1109 IrInstSrcBinOp *inst = ir_build_instruction<IrInstSrcBinOp>(ag, scope, source_node);1109 Stage1ZirInstBinOp *inst = ir_build_instruction<Stage1ZirInstBinOp>(ag, scope, source_node);
1110 inst->op_id = op_id;1110 inst->op_id = op_id;
1111 inst->op1 = op1;1111 inst->op1 = op1;
1112 inst->op2 = op2;1112 inst->op2 = op2;
...@@ -1118,10 +1118,10 @@ static IrInstSrc *ir_build_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *sourc...@@ -1118,10 +1118,10 @@ static IrInstSrc *ir_build_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *sourc
1118 return &inst->base;1118 return &inst->base;
1119}1119}
11201120
1121static IrInstSrc *ir_build_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1121static Stage1ZirInst *ir_build_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1122 IrInstSrc *op1, IrInstSrc *op2, Buf *type_name)1122 Stage1ZirInst *op1, Stage1ZirInst *op2, Buf *type_name)
1123{1123{
1124 IrInstSrcMergeErrSets *inst = ir_build_instruction<IrInstSrcMergeErrSets>(ag, scope, source_node);1124 Stage1ZirInstMergeErrSets *inst = ir_build_instruction<Stage1ZirInstMergeErrSets>(ag, scope, source_node);
1125 inst->op1 = op1;1125 inst->op1 = op1;
1126 inst->op2 = op2;1126 inst->op2 = op2;
1127 inst->type_name = type_name;1127 inst->type_name = type_name;
...@@ -1132,10 +1132,10 @@ static IrInstSrc *ir_build_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNod...@@ -1132,10 +1132,10 @@ static IrInstSrc *ir_build_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNod
1132 return &inst->base;1132 return &inst->base;
1133}1133}
11341134
1135static IrInstSrc *ir_build_var_ptr_x(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var,1135static Stage1ZirInst *ir_build_var_ptr_x(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var,
1136 ScopeFnDef *crossed_fndef_scope)1136 ScopeFnDef *crossed_fndef_scope)
1137{1137{
1138 IrInstSrcVarPtr *instruction = ir_build_instruction<IrInstSrcVarPtr>(ag, scope, source_node);1138 Stage1ZirInstVarPtr *instruction = ir_build_instruction<Stage1ZirInstVarPtr>(ag, scope, source_node);
1139 instruction->var = var;1139 instruction->var = var;
1140 instruction->crossed_fndef_scope = crossed_fndef_scope;1140 instruction->crossed_fndef_scope = crossed_fndef_scope;
11411141
...@@ -1144,15 +1144,15 @@ static IrInstSrc *ir_build_var_ptr_x(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -1144,15 +1144,15 @@ static IrInstSrc *ir_build_var_ptr_x(Stage1AstGen *ag, Scope *scope, AstNode *so
1144 return &instruction->base;1144 return &instruction->base;
1145}1145}
11461146
1147static IrInstSrc *ir_build_var_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var) {1147static Stage1ZirInst *ir_build_var_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var) {
1148 return ir_build_var_ptr_x(ag, scope, source_node, var, nullptr);1148 return ir_build_var_ptr_x(ag, scope, source_node, var, nullptr);
1149}1149}
11501150
1151static IrInstSrc *ir_build_elem_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1151static Stage1ZirInst *ir_build_elem_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1152 IrInstSrc *array_ptr, IrInstSrc *elem_index, bool safety_check_on, PtrLen ptr_len,1152 Stage1ZirInst *array_ptr, Stage1ZirInst *elem_index, bool safety_check_on, PtrLen ptr_len,
1153 AstNode *init_array_type_source_node)1153 AstNode *init_array_type_source_node)
1154{1154{
1155 IrInstSrcElemPtr *instruction = ir_build_instruction<IrInstSrcElemPtr>(ag, scope, source_node);1155 Stage1ZirInstElemPtr *instruction = ir_build_instruction<Stage1ZirInstElemPtr>(ag, scope, source_node);
1156 instruction->array_ptr = array_ptr;1156 instruction->array_ptr = array_ptr;
1157 instruction->elem_index = elem_index;1157 instruction->elem_index = elem_index;
1158 instruction->safety_check_on = safety_check_on;1158 instruction->safety_check_on = safety_check_on;
...@@ -1165,10 +1165,10 @@ static IrInstSrc *ir_build_elem_ptr(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1165,10 +1165,10 @@ static IrInstSrc *ir_build_elem_ptr(Stage1AstGen *ag, Scope *scope, AstNode *sou
1165 return &instruction->base;1165 return &instruction->base;
1166}1166}
11671167
1168static IrInstSrc *ir_build_field_ptr_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1168static Stage1ZirInst *ir_build_field_ptr_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1169 IrInstSrc *container_ptr, IrInstSrc *field_name_expr, bool initializing)1169 Stage1ZirInst *container_ptr, Stage1ZirInst *field_name_expr, bool initializing)
1170{1170{
1171 IrInstSrcFieldPtr *instruction = ir_build_instruction<IrInstSrcFieldPtr>(ag, scope, source_node);1171 Stage1ZirInstFieldPtr *instruction = ir_build_instruction<Stage1ZirInstFieldPtr>(ag, scope, source_node);
1172 instruction->container_ptr = container_ptr;1172 instruction->container_ptr = container_ptr;
1173 instruction->field_name_buffer = nullptr;1173 instruction->field_name_buffer = nullptr;
1174 instruction->field_name_expr = field_name_expr;1174 instruction->field_name_expr = field_name_expr;
...@@ -1180,10 +1180,10 @@ static IrInstSrc *ir_build_field_ptr_instruction(Stage1AstGen *ag, Scope *scope,...@@ -1180,10 +1180,10 @@ static IrInstSrc *ir_build_field_ptr_instruction(Stage1AstGen *ag, Scope *scope,
1180 return &instruction->base;1180 return &instruction->base;
1181}1181}
11821182
1183static IrInstSrc *ir_build_field_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1183static Stage1ZirInst *ir_build_field_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1184 IrInstSrc *container_ptr, Buf *field_name, bool initializing)1184 Stage1ZirInst *container_ptr, Buf *field_name, bool initializing)
1185{1185{
1186 IrInstSrcFieldPtr *instruction = ir_build_instruction<IrInstSrcFieldPtr>(ag, scope, source_node);1186 Stage1ZirInstFieldPtr *instruction = ir_build_instruction<Stage1ZirInstFieldPtr>(ag, scope, source_node);
1187 instruction->container_ptr = container_ptr;1187 instruction->container_ptr = container_ptr;
1188 instruction->field_name_buffer = field_name;1188 instruction->field_name_buffer = field_name;
1189 instruction->field_name_expr = nullptr;1189 instruction->field_name_expr = nullptr;
...@@ -1194,10 +1194,10 @@ static IrInstSrc *ir_build_field_ptr(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -1194,10 +1194,10 @@ static IrInstSrc *ir_build_field_ptr(Stage1AstGen *ag, Scope *scope, AstNode *so
1194 return &instruction->base;1194 return &instruction->base;
1195}1195}
11961196
1197static IrInstSrc *ir_build_has_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1197static Stage1ZirInst *ir_build_has_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1198 IrInstSrc *container_type, IrInstSrc *field_name)1198 Stage1ZirInst *container_type, Stage1ZirInst *field_name)
1199{1199{
1200 IrInstSrcHasField *instruction = ir_build_instruction<IrInstSrcHasField>(ag, scope, source_node);1200 Stage1ZirInstHasField *instruction = ir_build_instruction<Stage1ZirInstHasField>(ag, scope, source_node);
1201 instruction->container_type = container_type;1201 instruction->container_type = container_type;
1202 instruction->field_name = field_name;1202 instruction->field_name = field_name;
12031203
...@@ -1207,10 +1207,10 @@ static IrInstSrc *ir_build_has_field(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -1207,10 +1207,10 @@ static IrInstSrc *ir_build_has_field(Stage1AstGen *ag, Scope *scope, AstNode *so
1207 return &instruction->base;1207 return &instruction->base;
1208}1208}
12091209
1210static IrInstSrc *ir_build_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1210static Stage1ZirInst *ir_build_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1211 IrInstSrc *options, IrInstSrc *fn_ref, IrInstSrc *args, ResultLoc *result_loc)1211 Stage1ZirInst *options, Stage1ZirInst *fn_ref, Stage1ZirInst *args, ResultLoc *result_loc)
1212{1212{
1213 IrInstSrcCallExtra *call_instruction = ir_build_instruction<IrInstSrcCallExtra>(ag, scope, source_node);1213 Stage1ZirInstCallExtra *call_instruction = ir_build_instruction<Stage1ZirInstCallExtra>(ag, scope, source_node);
1214 call_instruction->options = options;1214 call_instruction->options = options;
1215 call_instruction->fn_ref = fn_ref;1215 call_instruction->fn_ref = fn_ref;
1216 call_instruction->args = args;1216 call_instruction->args = args;
...@@ -1223,10 +1223,10 @@ static IrInstSrc *ir_build_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -1223,10 +1223,10 @@ static IrInstSrc *ir_build_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *s
1223 return &call_instruction->base;1223 return &call_instruction->base;
1224}1224}
12251225
1226static IrInstSrc *ir_build_async_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1226static Stage1ZirInst *ir_build_async_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1227 CallModifier modifier, IrInstSrc *fn_ref, IrInstSrc *ret_ptr, IrInstSrc *new_stack, IrInstSrc *args, ResultLoc *result_loc)1227 CallModifier modifier, Stage1ZirInst *fn_ref, Stage1ZirInst *ret_ptr, Stage1ZirInst *new_stack, Stage1ZirInst *args, ResultLoc *result_loc)
1228{1228{
1229 IrInstSrcAsyncCallExtra *call_instruction = ir_build_instruction<IrInstSrcAsyncCallExtra>(ag, scope, source_node);1229 Stage1ZirInstAsyncCallExtra *call_instruction = ir_build_instruction<Stage1ZirInstAsyncCallExtra>(ag, scope, source_node);
1230 call_instruction->modifier = modifier;1230 call_instruction->modifier = modifier;
1231 call_instruction->fn_ref = fn_ref;1231 call_instruction->fn_ref = fn_ref;
1232 call_instruction->ret_ptr = ret_ptr;1232 call_instruction->ret_ptr = ret_ptr;
...@@ -1242,11 +1242,11 @@ static IrInstSrc *ir_build_async_call_extra(Stage1AstGen *ag, Scope *scope, AstN...@@ -1242,11 +1242,11 @@ static IrInstSrc *ir_build_async_call_extra(Stage1AstGen *ag, Scope *scope, AstN
1242 return &call_instruction->base;1242 return &call_instruction->base;
1243}1243}
12441244
1245static IrInstSrc *ir_build_call_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1245static Stage1ZirInst *ir_build_call_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1246 IrInstSrc *options, IrInstSrc *fn_ref, IrInstSrc **args_ptr, size_t args_len,1246 Stage1ZirInst *options, Stage1ZirInst *fn_ref, Stage1ZirInst **args_ptr, size_t args_len,
1247 ResultLoc *result_loc)1247 ResultLoc *result_loc)
1248{1248{
1249 IrInstSrcCallArgs *call_instruction = ir_build_instruction<IrInstSrcCallArgs>(ag, scope, source_node);1249 Stage1ZirInstCallArgs *call_instruction = ir_build_instruction<Stage1ZirInstCallArgs>(ag, scope, source_node);
1250 call_instruction->options = options;1250 call_instruction->options = options;
1251 call_instruction->fn_ref = fn_ref;1251 call_instruction->fn_ref = fn_ref;
1252 call_instruction->args_ptr = args_ptr;1252 call_instruction->args_ptr = args_ptr;
...@@ -1261,12 +1261,12 @@ static IrInstSrc *ir_build_call_args(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -1261,12 +1261,12 @@ static IrInstSrc *ir_build_call_args(Stage1AstGen *ag, Scope *scope, AstNode *so
1261 return &call_instruction->base;1261 return &call_instruction->base;
1262}1262}
12631263
1264static IrInstSrc *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1264static Stage1ZirInst *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1265 ZigFn *fn_entry, IrInstSrc *fn_ref, size_t arg_count, IrInstSrc **args,1265 ZigFn *fn_entry, Stage1ZirInst *fn_ref, size_t arg_count, Stage1ZirInst **args,
1266 IrInstSrc *ret_ptr, CallModifier modifier, bool is_async_call_builtin,1266 Stage1ZirInst *ret_ptr, CallModifier modifier, bool is_async_call_builtin,
1267 IrInstSrc *new_stack, ResultLoc *result_loc)1267 Stage1ZirInst *new_stack, ResultLoc *result_loc)
1268{1268{
1269 IrInstSrcCall *call_instruction = ir_build_instruction<IrInstSrcCall>(ag, scope, source_node);1269 Stage1ZirInstCall *call_instruction = ir_build_instruction<Stage1ZirInstCall>(ag, scope, source_node);
1270 call_instruction->fn_entry = fn_entry;1270 call_instruction->fn_entry = fn_entry;
1271 call_instruction->fn_ref = fn_ref;1271 call_instruction->fn_ref = fn_ref;
1272 call_instruction->args = args;1272 call_instruction->args = args;
...@@ -1286,14 +1286,14 @@ static IrInstSrc *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1286,14 +1286,14 @@ static IrInstSrc *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *sou
1286 return &call_instruction->base;1286 return &call_instruction->base;
1287}1287}
12881288
1289static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1289static Stage1ZirInst *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1290 size_t incoming_count, Stage1ZirBasicBlock **incoming_blocks, IrInstSrc **incoming_values,1290 size_t incoming_count, Stage1ZirBasicBlock **incoming_blocks, Stage1ZirInst **incoming_values,
1291 ResultLocPeerParent *peer_parent)1291 ResultLocPeerParent *peer_parent)
1292{1292{
1293 assert(incoming_count != 0);1293 assert(incoming_count != 0);
1294 assert(incoming_count != SIZE_MAX);1294 assert(incoming_count != SIZE_MAX);
12951295
1296 IrInstSrcPhi *phi_instruction = ir_build_instruction<IrInstSrcPhi>(ag, scope, source_node);1296 Stage1ZirInstPhi *phi_instruction = ir_build_instruction<Stage1ZirInstPhi>(ag, scope, source_node);
1297 phi_instruction->incoming_count = incoming_count;1297 phi_instruction->incoming_count = incoming_count;
1298 phi_instruction->incoming_blocks = incoming_blocks;1298 phi_instruction->incoming_blocks = incoming_blocks;
1299 phi_instruction->incoming_values = incoming_values;1299 phi_instruction->incoming_values = incoming_values;
...@@ -1307,10 +1307,10 @@ static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_n...@@ -1307,10 +1307,10 @@ static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_n
1307 return &phi_instruction->base;1307 return &phi_instruction->base;
1308}1308}
13091309
1310static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1310static Stage1ZirInst *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1311 Stage1ZirBasicBlock *dest_block, IrInstSrc *is_comptime)1311 Stage1ZirBasicBlock *dest_block, Stage1ZirInst *is_comptime)
1312{1312{
1313 IrInstSrcBr *inst = ir_build_instruction<IrInstSrcBr>(ag, scope, source_node);1313 Stage1ZirInstBr *inst = ir_build_instruction<Stage1ZirInstBr>(ag, scope, source_node);
1314 inst->dest_block = dest_block;1314 inst->dest_block = dest_block;
1315 inst->is_comptime = is_comptime;1315 inst->is_comptime = is_comptime;
13161316
...@@ -1320,11 +1320,11 @@ static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_no...@@ -1320,11 +1320,11 @@ static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_no
1320 return &inst->base;1320 return &inst->base;
1321}1321}
13221322
1323static IrInstSrc *ir_build_ptr_type_simple(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1323static Stage1ZirInst *ir_build_ptr_type_simple(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1324 IrInstSrc *child_type, bool is_const)1324 Stage1ZirInst *child_type, bool is_const)
1325{1325{
1326 IrInstSrcPtrTypeSimple *inst = heap::c_allocator.create<IrInstSrcPtrTypeSimple>();1326 Stage1ZirInstPtrTypeSimple *inst = heap::c_allocator.create<Stage1ZirInstPtrTypeSimple>();
1327 inst->base.id = is_const ? IrInstSrcIdPtrTypeSimpleConst : IrInstSrcIdPtrTypeSimple;1327 inst->base.id = is_const ? Stage1ZirInstIdPtrTypeSimpleConst : Stage1ZirInstIdPtrTypeSimple;
1328 inst->base.scope = scope;1328 inst->base.scope = scope;
1329 inst->base.source_node = source_node;1329 inst->base.source_node = source_node;
1330 inst->base.debug_id = irb_next_debug_id(ag);1330 inst->base.debug_id = irb_next_debug_id(ag);
...@@ -1338,9 +1338,9 @@ static IrInstSrc *ir_build_ptr_type_simple(Stage1AstGen *ag, Scope *scope, AstNo...@@ -1338,9 +1338,9 @@ static IrInstSrc *ir_build_ptr_type_simple(Stage1AstGen *ag, Scope *scope, AstNo
1338 return &inst->base;1338 return &inst->base;
1339}1339}
13401340
1341static IrInstSrc *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1341static Stage1ZirInst *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1342 IrInstSrc *child_type, bool is_const, bool is_volatile, PtrLen ptr_len,1342 Stage1ZirInst *child_type, bool is_const, bool is_volatile, PtrLen ptr_len,
1343 IrInstSrc *sentinel, IrInstSrc *align_value,1343 Stage1ZirInst *sentinel, Stage1ZirInst *align_value,
1344 uint32_t bit_offset_start, uint32_t host_int_bytes, bool is_allow_zero)1344 uint32_t bit_offset_start, uint32_t host_int_bytes, bool is_allow_zero)
1345{1345{
1346 if (!is_volatile && ptr_len == PtrLenSingle && sentinel == nullptr && align_value == nullptr &&1346 if (!is_volatile && ptr_len == PtrLenSingle && sentinel == nullptr && align_value == nullptr &&
...@@ -1349,7 +1349,7 @@ static IrInstSrc *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1349,7 +1349,7 @@ static IrInstSrc *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *sou
1349 return ir_build_ptr_type_simple(ag, scope, source_node, child_type, is_const);1349 return ir_build_ptr_type_simple(ag, scope, source_node, child_type, is_const);
1350 }1350 }
13511351
1352 IrInstSrcPtrType *inst = ir_build_instruction<IrInstSrcPtrType>(ag, scope, source_node);1352 Stage1ZirInstPtrType *inst = ir_build_instruction<Stage1ZirInstPtrType>(ag, scope, source_node);
1353 inst->sentinel = sentinel;1353 inst->sentinel = sentinel;
1354 inst->align_value = align_value;1354 inst->align_value = align_value;
1355 inst->child_type = child_type;1355 inst->child_type = child_type;
...@@ -1367,10 +1367,10 @@ static IrInstSrc *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1367,10 +1367,10 @@ static IrInstSrc *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *sou
1367 return &inst->base;1367 return &inst->base;
1368}1368}
13691369
1370static IrInstSrc *ir_build_un_op_lval(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id,1370static Stage1ZirInst *ir_build_un_op_lval(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id,
1371 IrInstSrc *value, LVal lval, ResultLoc *result_loc)1371 Stage1ZirInst *value, LVal lval, ResultLoc *result_loc)
1372{1372{
1373 IrInstSrcUnOp *instruction = ir_build_instruction<IrInstSrcUnOp>(ag, scope, source_node);1373 Stage1ZirInstUnOp *instruction = ir_build_instruction<Stage1ZirInstUnOp>(ag, scope, source_node);
1374 instruction->op_id = op_id;1374 instruction->op_id = op_id;
1375 instruction->value = value;1375 instruction->value = value;
1376 instruction->lval = lval;1376 instruction->lval = lval;
...@@ -1381,18 +1381,18 @@ static IrInstSrc *ir_build_un_op_lval(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -1381,18 +1381,18 @@ static IrInstSrc *ir_build_un_op_lval(Stage1AstGen *ag, Scope *scope, AstNode *s
1381 return &instruction->base;1381 return &instruction->base;
1382}1382}
13831383
1384static IrInstSrc *ir_build_un_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id,1384static Stage1ZirInst *ir_build_un_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id,
1385 IrInstSrc *value)1385 Stage1ZirInst *value)
1386{1386{
1387 return ir_build_un_op_lval(ag, scope, source_node, op_id, value, LValNone, nullptr);1387 return ir_build_un_op_lval(ag, scope, source_node, op_id, value, LValNone, nullptr);
1388}1388}
13891389
1390static IrInstSrc *ir_build_container_init_list(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1390static Stage1ZirInst *ir_build_container_init_list(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1391 size_t item_count, IrInstSrc **elem_result_loc_list, IrInstSrc *result_loc,1391 size_t item_count, Stage1ZirInst **elem_result_loc_list, Stage1ZirInst *result_loc,
1392 AstNode *init_array_type_source_node)1392 AstNode *init_array_type_source_node)
1393{1393{
1394 IrInstSrcContainerInitList *container_init_list_instruction =1394 Stage1ZirInstContainerInitList *container_init_list_instruction =
1395 ir_build_instruction<IrInstSrcContainerInitList>(ag, scope, source_node);1395 ir_build_instruction<Stage1ZirInstContainerInitList>(ag, scope, source_node);
1396 container_init_list_instruction->item_count = item_count;1396 container_init_list_instruction->item_count = item_count;
1397 container_init_list_instruction->elem_result_loc_list = elem_result_loc_list;1397 container_init_list_instruction->elem_result_loc_list = elem_result_loc_list;
1398 container_init_list_instruction->result_loc = result_loc;1398 container_init_list_instruction->result_loc = result_loc;
...@@ -1406,11 +1406,11 @@ static IrInstSrc *ir_build_container_init_list(Stage1AstGen *ag, Scope *scope, A...@@ -1406,11 +1406,11 @@ static IrInstSrc *ir_build_container_init_list(Stage1AstGen *ag, Scope *scope, A
1406 return &container_init_list_instruction->base;1406 return &container_init_list_instruction->base;
1407}1407}
14081408
1409static IrInstSrc *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1409static Stage1ZirInst *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1410 size_t field_count, IrInstSrcContainerInitFieldsField *fields, IrInstSrc *result_loc)1410 size_t field_count, Stage1ZirInstContainerInitFieldsField *fields, Stage1ZirInst *result_loc)
1411{1411{
1412 IrInstSrcContainerInitFields *container_init_fields_instruction =1412 Stage1ZirInstContainerInitFields *container_init_fields_instruction =
1413 ir_build_instruction<IrInstSrcContainerInitFields>(ag, scope, source_node);1413 ir_build_instruction<Stage1ZirInstContainerInitFields>(ag, scope, source_node);
1414 container_init_fields_instruction->field_count = field_count;1414 container_init_fields_instruction->field_count = field_count;
1415 container_init_fields_instruction->fields = fields;1415 container_init_fields_instruction->fields = fields;
1416 container_init_fields_instruction->result_loc = result_loc;1416 container_init_fields_instruction->result_loc = result_loc;
...@@ -1423,15 +1423,15 @@ static IrInstSrc *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope,...@@ -1423,15 +1423,15 @@ static IrInstSrc *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope,
1423 return &container_init_fields_instruction->base;1423 return &container_init_fields_instruction->base;
1424}1424}
14251425
1426static IrInstSrc *ir_build_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {1426static Stage1ZirInst *ir_build_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
1427 IrInstSrcUnreachable *inst = ir_build_instruction<IrInstSrcUnreachable>(ag, scope, source_node);1427 Stage1ZirInstUnreachable *inst = ir_build_instruction<Stage1ZirInstUnreachable>(ag, scope, source_node);
1428 return &inst->base;1428 return &inst->base;
1429}1429}
14301430
1431static IrInstSrcStorePtr *ir_build_store_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1431static Stage1ZirInstStorePtr *ir_build_store_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1432 IrInstSrc *ptr, IrInstSrc *value)1432 Stage1ZirInst *ptr, Stage1ZirInst *value)
1433{1433{
1434 IrInstSrcStorePtr *instruction = ir_build_instruction<IrInstSrcStorePtr>(ag, scope, source_node);1434 Stage1ZirInstStorePtr *instruction = ir_build_instruction<Stage1ZirInstStorePtr>(ag, scope, source_node);
1435 instruction->ptr = ptr;1435 instruction->ptr = ptr;
1436 instruction->value = value;1436 instruction->value = value;
14371437
...@@ -1441,10 +1441,10 @@ static IrInstSrcStorePtr *ir_build_store_ptr(Stage1AstGen *ag, Scope *scope, Ast...@@ -1441,10 +1441,10 @@ static IrInstSrcStorePtr *ir_build_store_ptr(Stage1AstGen *ag, Scope *scope, Ast
1441 return instruction;1441 return instruction;
1442}1442}
14431443
1444static IrInstSrc *ir_build_var_decl_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1444static Stage1ZirInst *ir_build_var_decl_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1445 ZigVar *var, IrInstSrc *align_value, IrInstSrc *ptr)1445 ZigVar *var, Stage1ZirInst *align_value, Stage1ZirInst *ptr)
1446{1446{
1447 IrInstSrcDeclVar *inst = ir_build_instruction<IrInstSrcDeclVar>(ag, scope, source_node);1447 Stage1ZirInstDeclVar *inst = ir_build_instruction<Stage1ZirInstDeclVar>(ag, scope, source_node);
1448 inst->var = var;1448 inst->var = var;
1449 inst->align_value = align_value;1449 inst->align_value = align_value;
1450 inst->ptr = ptr;1450 inst->ptr = ptr;
...@@ -1455,10 +1455,10 @@ static IrInstSrc *ir_build_var_decl_src(Stage1AstGen *ag, Scope *scope, AstNode...@@ -1455,10 +1455,10 @@ static IrInstSrc *ir_build_var_decl_src(Stage1AstGen *ag, Scope *scope, AstNode
1455 return &inst->base;1455 return &inst->base;
1456}1456}
14571457
1458static IrInstSrc *ir_build_export(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1458static Stage1ZirInst *ir_build_export(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1459 IrInstSrc *target, IrInstSrc *options)1459 Stage1ZirInst *target, Stage1ZirInst *options)
1460{1460{
1461 IrInstSrcExport *export_instruction = ir_build_instruction<IrInstSrcExport>(1461 Stage1ZirInstExport *export_instruction = ir_build_instruction<Stage1ZirInstExport>(
1462 ag, scope, source_node);1462 ag, scope, source_node);
1463 export_instruction->target = target;1463 export_instruction->target = target;
1464 export_instruction->options = options;1464 export_instruction->options = options;
...@@ -1469,10 +1469,10 @@ static IrInstSrc *ir_build_export(Stage1AstGen *ag, Scope *scope, AstNode *sourc...@@ -1469,10 +1469,10 @@ static IrInstSrc *ir_build_export(Stage1AstGen *ag, Scope *scope, AstNode *sourc
1469 return &export_instruction->base;1469 return &export_instruction->base;
1470}1470}
14711471
1472static IrInstSrc *ir_build_extern(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1472static Stage1ZirInst *ir_build_extern(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1473 IrInstSrc *type, IrInstSrc *options)1473 Stage1ZirInst *type, Stage1ZirInst *options)
1474{1474{
1475 IrInstSrcExtern *extern_instruction = ir_build_instruction<IrInstSrcExtern>(1475 Stage1ZirInstExtern *extern_instruction = ir_build_instruction<Stage1ZirInstExtern>(
1476 ag, scope, source_node);1476 ag, scope, source_node);
1477 extern_instruction->type = type;1477 extern_instruction->type = type;
1478 extern_instruction->options = options;1478 extern_instruction->options = options;
...@@ -1483,8 +1483,8 @@ static IrInstSrc *ir_build_extern(Stage1AstGen *ag, Scope *scope, AstNode *sourc...@@ -1483,8 +1483,8 @@ static IrInstSrc *ir_build_extern(Stage1AstGen *ag, Scope *scope, AstNode *sourc
1483 return &extern_instruction->base;1483 return &extern_instruction->base;
1484}1484}
14851485
1486static IrInstSrc *ir_build_load_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *ptr) {1486static Stage1ZirInst *ir_build_load_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *ptr) {
1487 IrInstSrcLoadPtr *instruction = ir_build_instruction<IrInstSrcLoadPtr>(ag, scope, source_node);1487 Stage1ZirInstLoadPtr *instruction = ir_build_instruction<Stage1ZirInstLoadPtr>(ag, scope, source_node);
1488 instruction->ptr = ptr;1488 instruction->ptr = ptr;
14891489
1490 ir_ref_instruction(ptr, ag->current_basic_block);1490 ir_ref_instruction(ptr, ag->current_basic_block);
...@@ -1492,12 +1492,12 @@ static IrInstSrc *ir_build_load_ptr(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1492,12 +1492,12 @@ static IrInstSrc *ir_build_load_ptr(Stage1AstGen *ag, Scope *scope, AstNode *sou
1492 return &instruction->base;1492 return &instruction->base;
1493}1493}
14941494
1495static IrInstSrc *ir_build_typeof_n(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1495static Stage1ZirInst *ir_build_typeof_n(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1496 IrInstSrc **values, size_t value_count)1496 Stage1ZirInst **values, size_t value_count)
1497{1497{
1498 assert(value_count >= 2);1498 assert(value_count >= 2);
14991499
1500 IrInstSrcTypeOf *instruction = ir_build_instruction<IrInstSrcTypeOf>(ag, scope, source_node);1500 Stage1ZirInstTypeOf *instruction = ir_build_instruction<Stage1ZirInstTypeOf>(ag, scope, source_node);
1501 instruction->value.list = values;1501 instruction->value.list = values;
1502 instruction->value_count = value_count;1502 instruction->value_count = value_count;
15031503
...@@ -1507,8 +1507,8 @@ static IrInstSrc *ir_build_typeof_n(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1507,8 +1507,8 @@ static IrInstSrc *ir_build_typeof_n(Stage1AstGen *ag, Scope *scope, AstNode *sou
1507 return &instruction->base;1507 return &instruction->base;
1508}1508}
15091509
1510static IrInstSrc *ir_build_typeof_1(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) {1510static Stage1ZirInst *ir_build_typeof_1(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) {
1511 IrInstSrcTypeOf *instruction = ir_build_instruction<IrInstSrcTypeOf>(ag, scope, source_node);1511 Stage1ZirInstTypeOf *instruction = ir_build_instruction<Stage1ZirInstTypeOf>(ag, scope, source_node);
1512 instruction->value.scalar = value;1512 instruction->value.scalar = value;
15131513
1514 ir_ref_instruction(value, ag->current_basic_block);1514 ir_ref_instruction(value, ag->current_basic_block);
...@@ -1516,8 +1516,8 @@ static IrInstSrc *ir_build_typeof_1(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1516,8 +1516,8 @@ static IrInstSrc *ir_build_typeof_1(Stage1AstGen *ag, Scope *scope, AstNode *sou
1516 return &instruction->base;1516 return &instruction->base;
1517}1517}
15181518
1519static IrInstSrc *ir_build_set_cold(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *is_cold) {1519static Stage1ZirInst *ir_build_set_cold(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *is_cold) {
1520 IrInstSrcSetCold *instruction = ir_build_instruction<IrInstSrcSetCold>(ag, scope, source_node);1520 Stage1ZirInstSetCold *instruction = ir_build_instruction<Stage1ZirInstSetCold>(ag, scope, source_node);
1521 instruction->is_cold = is_cold;1521 instruction->is_cold = is_cold;
15221522
1523 ir_ref_instruction(is_cold, ag->current_basic_block);1523 ir_ref_instruction(is_cold, ag->current_basic_block);
...@@ -1525,10 +1525,10 @@ static IrInstSrc *ir_build_set_cold(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1525,10 +1525,10 @@ static IrInstSrc *ir_build_set_cold(Stage1AstGen *ag, Scope *scope, AstNode *sou
1525 return &instruction->base;1525 return &instruction->base;
1526}1526}
15271527
1528static IrInstSrc *ir_build_set_runtime_safety(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1528static Stage1ZirInst *ir_build_set_runtime_safety(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1529 IrInstSrc *safety_on)1529 Stage1ZirInst *safety_on)
1530{1530{
1531 IrInstSrcSetRuntimeSafety *inst = ir_build_instruction<IrInstSrcSetRuntimeSafety>(ag, scope, source_node);1531 Stage1ZirInstSetRuntimeSafety *inst = ir_build_instruction<Stage1ZirInstSetRuntimeSafety>(ag, scope, source_node);
1532 inst->safety_on = safety_on;1532 inst->safety_on = safety_on;
15331533
1534 ir_ref_instruction(safety_on, ag->current_basic_block);1534 ir_ref_instruction(safety_on, ag->current_basic_block);
...@@ -1536,10 +1536,10 @@ static IrInstSrc *ir_build_set_runtime_safety(Stage1AstGen *ag, Scope *scope, As...@@ -1536,10 +1536,10 @@ static IrInstSrc *ir_build_set_runtime_safety(Stage1AstGen *ag, Scope *scope, As
1536 return &inst->base;1536 return &inst->base;
1537}1537}
15381538
1539static IrInstSrc *ir_build_set_float_mode(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1539static Stage1ZirInst *ir_build_set_float_mode(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1540 IrInstSrc *mode_value)1540 Stage1ZirInst *mode_value)
1541{1541{
1542 IrInstSrcSetFloatMode *instruction = ir_build_instruction<IrInstSrcSetFloatMode>(ag, scope, source_node);1542 Stage1ZirInstSetFloatMode *instruction = ir_build_instruction<Stage1ZirInstSetFloatMode>(ag, scope, source_node);
1543 instruction->mode_value = mode_value;1543 instruction->mode_value = mode_value;
15441544
1545 ir_ref_instruction(mode_value, ag->current_basic_block);1545 ir_ref_instruction(mode_value, ag->current_basic_block);
...@@ -1547,10 +1547,10 @@ static IrInstSrc *ir_build_set_float_mode(Stage1AstGen *ag, Scope *scope, AstNod...@@ -1547,10 +1547,10 @@ static IrInstSrc *ir_build_set_float_mode(Stage1AstGen *ag, Scope *scope, AstNod
1547 return &instruction->base;1547 return &instruction->base;
1548}1548}
15491549
1550static IrInstSrc *ir_build_array_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *size,1550static Stage1ZirInst *ir_build_array_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *size,
1551 IrInstSrc *sentinel, IrInstSrc *child_type)1551 Stage1ZirInst *sentinel, Stage1ZirInst *child_type)
1552{1552{
1553 IrInstSrcArrayType *instruction = ir_build_instruction<IrInstSrcArrayType>(ag, scope, source_node);1553 Stage1ZirInstArrayType *instruction = ir_build_instruction<Stage1ZirInstArrayType>(ag, scope, source_node);
1554 instruction->size = size;1554 instruction->size = size;
1555 instruction->sentinel = sentinel;1555 instruction->sentinel = sentinel;
1556 instruction->child_type = child_type;1556 instruction->child_type = child_type;
...@@ -1562,10 +1562,10 @@ static IrInstSrc *ir_build_array_type(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -1562,10 +1562,10 @@ static IrInstSrc *ir_build_array_type(Stage1AstGen *ag, Scope *scope, AstNode *s
1562 return &instruction->base;1562 return &instruction->base;
1563}1563}
15641564
1565static IrInstSrc *ir_build_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1565static Stage1ZirInst *ir_build_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1566 IrInstSrc *payload_type)1566 Stage1ZirInst *payload_type)
1567{1567{
1568 IrInstSrcAnyFrameType *instruction = ir_build_instruction<IrInstSrcAnyFrameType>(ag, scope, source_node);1568 Stage1ZirInstAnyFrameType *instruction = ir_build_instruction<Stage1ZirInstAnyFrameType>(ag, scope, source_node);
1569 instruction->payload_type = payload_type;1569 instruction->payload_type = payload_type;
15701570
1571 if (payload_type != nullptr) ir_ref_instruction(payload_type, ag->current_basic_block);1571 if (payload_type != nullptr) ir_ref_instruction(payload_type, ag->current_basic_block);
...@@ -1573,11 +1573,11 @@ static IrInstSrc *ir_build_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode...@@ -1573,11 +1573,11 @@ static IrInstSrc *ir_build_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode
1573 return &instruction->base;1573 return &instruction->base;
1574}1574}
15751575
1576static IrInstSrc *ir_build_slice_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1576static Stage1ZirInst *ir_build_slice_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1577 IrInstSrc *child_type, bool is_const, bool is_volatile,1577 Stage1ZirInst *child_type, bool is_const, bool is_volatile,
1578 IrInstSrc *sentinel, IrInstSrc *align_value, bool is_allow_zero)1578 Stage1ZirInst *sentinel, Stage1ZirInst *align_value, bool is_allow_zero)
1579{1579{
1580 IrInstSrcSliceType *instruction = ir_build_instruction<IrInstSrcSliceType>(ag, scope, source_node);1580 Stage1ZirInstSliceType *instruction = ir_build_instruction<Stage1ZirInstSliceType>(ag, scope, source_node);
1581 instruction->is_const = is_const;1581 instruction->is_const = is_const;
1582 instruction->is_volatile = is_volatile;1582 instruction->is_volatile = is_volatile;
1583 instruction->child_type = child_type;1583 instruction->child_type = child_type;
...@@ -1592,11 +1592,11 @@ static IrInstSrc *ir_build_slice_type(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -1592,11 +1592,11 @@ static IrInstSrc *ir_build_slice_type(Stage1AstGen *ag, Scope *scope, AstNode *s
1592 return &instruction->base;1592 return &instruction->base;
1593}1593}
15941594
1595static IrInstSrc *ir_build_asm_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1595static Stage1ZirInst *ir_build_asm_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1596 IrInstSrc *asm_template, IrInstSrc **input_list, IrInstSrc **output_types,1596 Stage1ZirInst *asm_template, Stage1ZirInst **input_list, Stage1ZirInst **output_types,
1597 ZigVar **output_vars, size_t return_count, bool has_side_effects, bool is_global)1597 ZigVar **output_vars, size_t return_count, bool has_side_effects, bool is_global)
1598{1598{
1599 IrInstSrcAsm *instruction = ir_build_instruction<IrInstSrcAsm>(ag, scope, source_node);1599 Stage1ZirInstAsm *instruction = ir_build_instruction<Stage1ZirInstAsm>(ag, scope, source_node);
1600 instruction->asm_template = asm_template;1600 instruction->asm_template = asm_template;
1601 instruction->input_list = input_list;1601 instruction->input_list = input_list;
1602 instruction->output_types = output_types;1602 instruction->output_types = output_types;
...@@ -1607,22 +1607,22 @@ static IrInstSrc *ir_build_asm_src(Stage1AstGen *ag, Scope *scope, AstNode *sour...@@ -1607,22 +1607,22 @@ static IrInstSrc *ir_build_asm_src(Stage1AstGen *ag, Scope *scope, AstNode *sour
16071607
1608 assert(source_node->type == NodeTypeAsmExpr);1608 assert(source_node->type == NodeTypeAsmExpr);
1609 for (size_t i = 0; i < source_node->data.asm_expr.output_list.length; i += 1) {1609 for (size_t i = 0; i < source_node->data.asm_expr.output_list.length; i += 1) {
1610 IrInstSrc *output_type = output_types[i];1610 Stage1ZirInst *output_type = output_types[i];
1611 if (output_type) ir_ref_instruction(output_type, ag->current_basic_block);1611 if (output_type) ir_ref_instruction(output_type, ag->current_basic_block);
1612 }1612 }
16131613
1614 for (size_t i = 0; i < source_node->data.asm_expr.input_list.length; i += 1) {1614 for (size_t i = 0; i < source_node->data.asm_expr.input_list.length; i += 1) {
1615 IrInstSrc *input_value = input_list[i];1615 Stage1ZirInst *input_value = input_list[i];
1616 ir_ref_instruction(input_value, ag->current_basic_block);1616 ir_ref_instruction(input_value, ag->current_basic_block);
1617 }1617 }
16181618
1619 return &instruction->base;1619 return &instruction->base;
1620}1620}
16211621
1622static IrInstSrc *ir_build_size_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_value,1622static Stage1ZirInst *ir_build_size_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_value,
1623 bool bit_size)1623 bool bit_size)
1624{1624{
1625 IrInstSrcSizeOf *instruction = ir_build_instruction<IrInstSrcSizeOf>(ag, scope, source_node);1625 Stage1ZirInstSizeOf *instruction = ir_build_instruction<Stage1ZirInstSizeOf>(ag, scope, source_node);
1626 instruction->type_value = type_value;1626 instruction->type_value = type_value;
1627 instruction->bit_size = bit_size;1627 instruction->bit_size = bit_size;
16281628
...@@ -1631,10 +1631,10 @@ static IrInstSrc *ir_build_size_of(Stage1AstGen *ag, Scope *scope, AstNode *sour...@@ -1631,10 +1631,10 @@ static IrInstSrc *ir_build_size_of(Stage1AstGen *ag, Scope *scope, AstNode *sour
1631 return &instruction->base;1631 return &instruction->base;
1632}1632}
16331633
1634static IrInstSrc *ir_build_test_non_null_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1634static Stage1ZirInst *ir_build_test_non_null_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1635 IrInstSrc *value)1635 Stage1ZirInst *value)
1636{1636{
1637 IrInstSrcTestNonNull *instruction = ir_build_instruction<IrInstSrcTestNonNull>(ag, scope, source_node);1637 Stage1ZirInstTestNonNull *instruction = ir_build_instruction<Stage1ZirInstTestNonNull>(ag, scope, source_node);
1638 instruction->value = value;1638 instruction->value = value;
16391639
1640 ir_ref_instruction(value, ag->current_basic_block);1640 ir_ref_instruction(value, ag->current_basic_block);
...@@ -1642,10 +1642,10 @@ static IrInstSrc *ir_build_test_non_null_src(Stage1AstGen *ag, Scope *scope, Ast...@@ -1642,10 +1642,10 @@ static IrInstSrc *ir_build_test_non_null_src(Stage1AstGen *ag, Scope *scope, Ast
1642 return &instruction->base;1642 return &instruction->base;
1643}1643}
16441644
1645static IrInstSrc *ir_build_optional_unwrap_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1645static Stage1ZirInst *ir_build_optional_unwrap_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1646 IrInstSrc *base_ptr, bool safety_check_on)1646 Stage1ZirInst *base_ptr, bool safety_check_on)
1647{1647{
1648 IrInstSrcOptionalUnwrapPtr *instruction = ir_build_instruction<IrInstSrcOptionalUnwrapPtr>(ag, scope, source_node);1648 Stage1ZirInstOptionalUnwrapPtr *instruction = ir_build_instruction<Stage1ZirInstOptionalUnwrapPtr>(ag, scope, source_node);
1649 instruction->base_ptr = base_ptr;1649 instruction->base_ptr = base_ptr;
1650 instruction->safety_check_on = safety_check_on;1650 instruction->safety_check_on = safety_check_on;
16511651
...@@ -1654,10 +1654,10 @@ static IrInstSrc *ir_build_optional_unwrap_ptr(Stage1AstGen *ag, Scope *scope, A...@@ -1654,10 +1654,10 @@ static IrInstSrc *ir_build_optional_unwrap_ptr(Stage1AstGen *ag, Scope *scope, A
1654 return &instruction->base;1654 return &instruction->base;
1655}1655}
16561656
1657static IrInstSrc *ir_build_clz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type,1657static Stage1ZirInst *ir_build_clz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type,
1658 IrInstSrc *op)1658 Stage1ZirInst *op)
1659{1659{
1660 IrInstSrcClz *instruction = ir_build_instruction<IrInstSrcClz>(ag, scope, source_node);1660 Stage1ZirInstClz *instruction = ir_build_instruction<Stage1ZirInstClz>(ag, scope, source_node);
1661 instruction->type = type;1661 instruction->type = type;
1662 instruction->op = op;1662 instruction->op = op;
16631663
...@@ -1667,10 +1667,10 @@ static IrInstSrc *ir_build_clz(Stage1AstGen *ag, Scope *scope, AstNode *source_n...@@ -1667,10 +1667,10 @@ static IrInstSrc *ir_build_clz(Stage1AstGen *ag, Scope *scope, AstNode *source_n
1667 return &instruction->base;1667 return &instruction->base;
1668}1668}
16691669
1670static IrInstSrc *ir_build_ctz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type,1670static Stage1ZirInst *ir_build_ctz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type,
1671 IrInstSrc *op)1671 Stage1ZirInst *op)
1672{1672{
1673 IrInstSrcCtz *instruction = ir_build_instruction<IrInstSrcCtz>(ag, scope, source_node);1673 Stage1ZirInstCtz *instruction = ir_build_instruction<Stage1ZirInstCtz>(ag, scope, source_node);
1674 instruction->type = type;1674 instruction->type = type;
1675 instruction->op = op;1675 instruction->op = op;
16761676
...@@ -1680,10 +1680,10 @@ static IrInstSrc *ir_build_ctz(Stage1AstGen *ag, Scope *scope, AstNode *source_n...@@ -1680,10 +1680,10 @@ static IrInstSrc *ir_build_ctz(Stage1AstGen *ag, Scope *scope, AstNode *source_n
1680 return &instruction->base;1680 return &instruction->base;
1681}1681}
16821682
1683static IrInstSrc *ir_build_pop_count(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type,1683static Stage1ZirInst *ir_build_pop_count(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type,
1684 IrInstSrc *op)1684 Stage1ZirInst *op)
1685{1685{
1686 IrInstSrcPopCount *instruction = ir_build_instruction<IrInstSrcPopCount>(ag, scope, source_node);1686 Stage1ZirInstPopCount *instruction = ir_build_instruction<Stage1ZirInstPopCount>(ag, scope, source_node);
1687 instruction->type = type;1687 instruction->type = type;
1688 instruction->op = op;1688 instruction->op = op;
16891689
...@@ -1693,10 +1693,10 @@ static IrInstSrc *ir_build_pop_count(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -1693,10 +1693,10 @@ static IrInstSrc *ir_build_pop_count(Stage1AstGen *ag, Scope *scope, AstNode *so
1693 return &instruction->base;1693 return &instruction->base;
1694}1694}
16951695
1696static IrInstSrc *ir_build_bswap(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type,1696static Stage1ZirInst *ir_build_bswap(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type,
1697 IrInstSrc *op)1697 Stage1ZirInst *op)
1698{1698{
1699 IrInstSrcBswap *instruction = ir_build_instruction<IrInstSrcBswap>(ag, scope, source_node);1699 Stage1ZirInstBswap *instruction = ir_build_instruction<Stage1ZirInstBswap>(ag, scope, source_node);
1700 instruction->type = type;1700 instruction->type = type;
1701 instruction->op = op;1701 instruction->op = op;
17021702
...@@ -1706,10 +1706,10 @@ static IrInstSrc *ir_build_bswap(Stage1AstGen *ag, Scope *scope, AstNode *source...@@ -1706,10 +1706,10 @@ static IrInstSrc *ir_build_bswap(Stage1AstGen *ag, Scope *scope, AstNode *source
1706 return &instruction->base;1706 return &instruction->base;
1707}1707}
17081708
1709static IrInstSrc *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type,1709static Stage1ZirInst *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type,
1710 IrInstSrc *op)1710 Stage1ZirInst *op)
1711{1711{
1712 IrInstSrcBitReverse *instruction = ir_build_instruction<IrInstSrcBitReverse>(ag, scope, source_node);1712 Stage1ZirInstBitReverse *instruction = ir_build_instruction<Stage1ZirInstBitReverse>(ag, scope, source_node);
1713 instruction->type = type;1713 instruction->type = type;
1714 instruction->op = op;1714 instruction->op = op;
17151715
...@@ -1719,11 +1719,11 @@ static IrInstSrc *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -1719,11 +1719,11 @@ static IrInstSrc *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *
1719 return &instruction->base;1719 return &instruction->base;
1720}1720}
17211721
1722static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1722static Stage1ZirInstSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1723 IrInstSrc *target_value, Stage1ZirBasicBlock *else_block, size_t case_count, IrInstSrcSwitchBrCase *cases,1723 Stage1ZirInst *target_value, Stage1ZirBasicBlock *else_block, size_t case_count, Stage1ZirInstSwitchBrCase *cases,
1724 IrInstSrc *is_comptime, IrInstSrc *switch_prongs_void)1724 Stage1ZirInst *is_comptime, Stage1ZirInst *switch_prongs_void)
1725{1725{
1726 IrInstSrcSwitchBr *instruction = ir_build_instruction<IrInstSrcSwitchBr>(ag, scope, source_node);1726 Stage1ZirInstSwitchBr *instruction = ir_build_instruction<Stage1ZirInstSwitchBr>(ag, scope, source_node);
1727 instruction->target_value = target_value;1727 instruction->target_value = target_value;
1728 instruction->else_block = else_block;1728 instruction->else_block = else_block;
1729 instruction->case_count = case_count;1729 instruction->case_count = case_count;
...@@ -1744,10 +1744,10 @@ static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope,...@@ -1744,10 +1744,10 @@ static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope,
1744 return instruction;1744 return instruction;
1745}1745}
17461746
1747static IrInstSrc *ir_build_switch_target(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1747static Stage1ZirInst *ir_build_switch_target(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1748 IrInstSrc *target_value_ptr)1748 Stage1ZirInst *target_value_ptr)
1749{1749{
1750 IrInstSrcSwitchTarget *instruction = ir_build_instruction<IrInstSrcSwitchTarget>(ag, scope, source_node);1750 Stage1ZirInstSwitchTarget *instruction = ir_build_instruction<Stage1ZirInstSwitchTarget>(ag, scope, source_node);
1751 instruction->target_value_ptr = target_value_ptr;1751 instruction->target_value_ptr = target_value_ptr;
17521752
1753 ir_ref_instruction(target_value_ptr, ag->current_basic_block);1753 ir_ref_instruction(target_value_ptr, ag->current_basic_block);
...@@ -1755,10 +1755,10 @@ static IrInstSrc *ir_build_switch_target(Stage1AstGen *ag, Scope *scope, AstNode...@@ -1755,10 +1755,10 @@ static IrInstSrc *ir_build_switch_target(Stage1AstGen *ag, Scope *scope, AstNode
1755 return &instruction->base;1755 return &instruction->base;
1756}1756}
17571757
1758static IrInstSrc *ir_build_switch_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1758static Stage1ZirInst *ir_build_switch_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1759 IrInstSrc *target_value_ptr, IrInstSrc **prongs_ptr, size_t prongs_len)1759 Stage1ZirInst *target_value_ptr, Stage1ZirInst **prongs_ptr, size_t prongs_len)
1760{1760{
1761 IrInstSrcSwitchVar *instruction = ir_build_instruction<IrInstSrcSwitchVar>(ag, scope, source_node);1761 Stage1ZirInstSwitchVar *instruction = ir_build_instruction<Stage1ZirInstSwitchVar>(ag, scope, source_node);
1762 instruction->target_value_ptr = target_value_ptr;1762 instruction->target_value_ptr = target_value_ptr;
1763 instruction->prongs_ptr = prongs_ptr;1763 instruction->prongs_ptr = prongs_ptr;
1764 instruction->prongs_len = prongs_len;1764 instruction->prongs_len = prongs_len;
...@@ -1772,10 +1772,10 @@ static IrInstSrc *ir_build_switch_var(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -1772,10 +1772,10 @@ static IrInstSrc *ir_build_switch_var(Stage1AstGen *ag, Scope *scope, AstNode *s
1772}1772}
17731773
1774// For this instruction the switch_br must be set later.1774// For this instruction the switch_br must be set later.
1775static IrInstSrcSwitchElseVar *ir_build_switch_else_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1775static Stage1ZirInstSwitchElseVar *ir_build_switch_else_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1776 IrInstSrc *target_value_ptr)1776 Stage1ZirInst *target_value_ptr)
1777{1777{
1778 IrInstSrcSwitchElseVar *instruction = ir_build_instruction<IrInstSrcSwitchElseVar>(ag, scope, source_node);1778 Stage1ZirInstSwitchElseVar *instruction = ir_build_instruction<Stage1ZirInstSwitchElseVar>(ag, scope, source_node);
1779 instruction->target_value_ptr = target_value_ptr;1779 instruction->target_value_ptr = target_value_ptr;
17801780
1781 ir_ref_instruction(target_value_ptr, ag->current_basic_block);1781 ir_ref_instruction(target_value_ptr, ag->current_basic_block);
...@@ -1783,8 +1783,8 @@ static IrInstSrcSwitchElseVar *ir_build_switch_else_var(Stage1AstGen *ag, Scope...@@ -1783,8 +1783,8 @@ static IrInstSrcSwitchElseVar *ir_build_switch_else_var(Stage1AstGen *ag, Scope
1783 return instruction;1783 return instruction;
1784}1784}
17851785
1786static IrInstSrc *ir_build_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) {1786static Stage1ZirInst *ir_build_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) {
1787 IrInstSrcImport *instruction = ir_build_instruction<IrInstSrcImport>(ag, scope, source_node);1787 Stage1ZirInstImport *instruction = ir_build_instruction<Stage1ZirInstImport>(ag, scope, source_node);
1788 instruction->name = name;1788 instruction->name = name;
17891789
1790 ir_ref_instruction(name, ag->current_basic_block);1790 ir_ref_instruction(name, ag->current_basic_block);
...@@ -1792,8 +1792,8 @@ static IrInstSrc *ir_build_import(Stage1AstGen *ag, Scope *scope, AstNode *sourc...@@ -1792,8 +1792,8 @@ static IrInstSrc *ir_build_import(Stage1AstGen *ag, Scope *scope, AstNode *sourc
1792 return &instruction->base;1792 return &instruction->base;
1793}1793}
17941794
1795static IrInstSrc *ir_build_ref_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) {1795static Stage1ZirInst *ir_build_ref_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) {
1796 IrInstSrcRef *instruction = ir_build_instruction<IrInstSrcRef>(ag, scope, source_node);1796 Stage1ZirInstRef *instruction = ir_build_instruction<Stage1ZirInstRef>(ag, scope, source_node);
1797 instruction->value = value;1797 instruction->value = value;
17981798
1799 ir_ref_instruction(value, ag->current_basic_block);1799 ir_ref_instruction(value, ag->current_basic_block);
...@@ -1801,8 +1801,8 @@ static IrInstSrc *ir_build_ref_src(Stage1AstGen *ag, Scope *scope, AstNode *sour...@@ -1801,8 +1801,8 @@ static IrInstSrc *ir_build_ref_src(Stage1AstGen *ag, Scope *scope, AstNode *sour
1801 return &instruction->base;1801 return &instruction->base;
1802}1802}
18031803
1804static IrInstSrc *ir_build_compile_err(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *msg) {1804static Stage1ZirInst *ir_build_compile_err(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *msg) {
1805 IrInstSrcCompileErr *instruction = ir_build_instruction<IrInstSrcCompileErr>(ag, scope, source_node);1805 Stage1ZirInstCompileErr *instruction = ir_build_instruction<Stage1ZirInstCompileErr>(ag, scope, source_node);
1806 instruction->msg = msg;1806 instruction->msg = msg;
18071807
1808 ir_ref_instruction(msg, ag->current_basic_block);1808 ir_ref_instruction(msg, ag->current_basic_block);
...@@ -1810,10 +1810,10 @@ static IrInstSrc *ir_build_compile_err(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -1810,10 +1810,10 @@ static IrInstSrc *ir_build_compile_err(Stage1AstGen *ag, Scope *scope, AstNode *
1810 return &instruction->base;1810 return &instruction->base;
1811}1811}
18121812
1813static IrInstSrc *ir_build_compile_log(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1813static Stage1ZirInst *ir_build_compile_log(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1814 size_t msg_count, IrInstSrc **msg_list)1814 size_t msg_count, Stage1ZirInst **msg_list)
1815{1815{
1816 IrInstSrcCompileLog *instruction = ir_build_instruction<IrInstSrcCompileLog>(ag, scope, source_node);1816 Stage1ZirInstCompileLog *instruction = ir_build_instruction<Stage1ZirInstCompileLog>(ag, scope, source_node);
1817 instruction->msg_count = msg_count;1817 instruction->msg_count = msg_count;
1818 instruction->msg_list = msg_list;1818 instruction->msg_list = msg_list;
18191819
...@@ -1824,8 +1824,8 @@ static IrInstSrc *ir_build_compile_log(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -1824,8 +1824,8 @@ static IrInstSrc *ir_build_compile_log(Stage1AstGen *ag, Scope *scope, AstNode *
1824 return &instruction->base;1824 return &instruction->base;
1825}1825}
18261826
1827static IrInstSrc *ir_build_err_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) {1827static Stage1ZirInst *ir_build_err_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) {
1828 IrInstSrcErrName *instruction = ir_build_instruction<IrInstSrcErrName>(ag, scope, source_node);1828 Stage1ZirInstErrName *instruction = ir_build_instruction<Stage1ZirInstErrName>(ag, scope, source_node);
1829 instruction->value = value;1829 instruction->value = value;
18301830
1831 ir_ref_instruction(value, ag->current_basic_block);1831 ir_ref_instruction(value, ag->current_basic_block);
...@@ -1833,13 +1833,13 @@ static IrInstSrc *ir_build_err_name(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1833,13 +1833,13 @@ static IrInstSrc *ir_build_err_name(Stage1AstGen *ag, Scope *scope, AstNode *sou
1833 return &instruction->base;1833 return &instruction->base;
1834}1834}
18351835
1836static IrInstSrc *ir_build_c_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {1836static Stage1ZirInst *ir_build_c_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
1837 IrInstSrcCImport *instruction = ir_build_instruction<IrInstSrcCImport>(ag, scope, source_node);1837 Stage1ZirInstCImport *instruction = ir_build_instruction<Stage1ZirInstCImport>(ag, scope, source_node);
1838 return &instruction->base;1838 return &instruction->base;
1839}1839}
18401840
1841static IrInstSrc *ir_build_c_include(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) {1841static Stage1ZirInst *ir_build_c_include(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) {
1842 IrInstSrcCInclude *instruction = ir_build_instruction<IrInstSrcCInclude>(ag, scope, source_node);1842 Stage1ZirInstCInclude *instruction = ir_build_instruction<Stage1ZirInstCInclude>(ag, scope, source_node);
1843 instruction->name = name;1843 instruction->name = name;
18441844
1845 ir_ref_instruction(name, ag->current_basic_block);1845 ir_ref_instruction(name, ag->current_basic_block);
...@@ -1847,8 +1847,8 @@ static IrInstSrc *ir_build_c_include(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -1847,8 +1847,8 @@ static IrInstSrc *ir_build_c_include(Stage1AstGen *ag, Scope *scope, AstNode *so
1847 return &instruction->base;1847 return &instruction->base;
1848}1848}
18491849
1850static IrInstSrc *ir_build_c_define(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name, IrInstSrc *value) {1850static Stage1ZirInst *ir_build_c_define(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name, Stage1ZirInst *value) {
1851 IrInstSrcCDefine *instruction = ir_build_instruction<IrInstSrcCDefine>(ag, scope, source_node);1851 Stage1ZirInstCDefine *instruction = ir_build_instruction<Stage1ZirInstCDefine>(ag, scope, source_node);
1852 instruction->name = name;1852 instruction->name = name;
1853 instruction->value = value;1853 instruction->value = value;
18541854
...@@ -1858,8 +1858,8 @@ static IrInstSrc *ir_build_c_define(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1858,8 +1858,8 @@ static IrInstSrc *ir_build_c_define(Stage1AstGen *ag, Scope *scope, AstNode *sou
1858 return &instruction->base;1858 return &instruction->base;
1859}1859}
18601860
1861static IrInstSrc *ir_build_c_undef(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) {1861static Stage1ZirInst *ir_build_c_undef(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) {
1862 IrInstSrcCUndef *instruction = ir_build_instruction<IrInstSrcCUndef>(ag, scope, source_node);1862 Stage1ZirInstCUndef *instruction = ir_build_instruction<Stage1ZirInstCUndef>(ag, scope, source_node);
1863 instruction->name = name;1863 instruction->name = name;
18641864
1865 ir_ref_instruction(name, ag->current_basic_block);1865 ir_ref_instruction(name, ag->current_basic_block);
...@@ -1867,8 +1867,8 @@ static IrInstSrc *ir_build_c_undef(Stage1AstGen *ag, Scope *scope, AstNode *sour...@@ -1867,8 +1867,8 @@ static IrInstSrc *ir_build_c_undef(Stage1AstGen *ag, Scope *scope, AstNode *sour
1867 return &instruction->base;1867 return &instruction->base;
1868}1868}
18691869
1870static IrInstSrc *ir_build_embed_file(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) {1870static Stage1ZirInst *ir_build_embed_file(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) {
1871 IrInstSrcEmbedFile *instruction = ir_build_instruction<IrInstSrcEmbedFile>(ag, scope, source_node);1871 Stage1ZirInstEmbedFile *instruction = ir_build_instruction<Stage1ZirInstEmbedFile>(ag, scope, source_node);
1872 instruction->name = name;1872 instruction->name = name;
18731873
1874 ir_ref_instruction(name, ag->current_basic_block);1874 ir_ref_instruction(name, ag->current_basic_block);
...@@ -1876,11 +1876,11 @@ static IrInstSrc *ir_build_embed_file(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -1876,11 +1876,11 @@ static IrInstSrc *ir_build_embed_file(Stage1AstGen *ag, Scope *scope, AstNode *s
1876 return &instruction->base;1876 return &instruction->base;
1877}1877}
18781878
1879static IrInstSrc *ir_build_cmpxchg_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1879static Stage1ZirInst *ir_build_cmpxchg_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1880 IrInstSrc *type_value, IrInstSrc *ptr, IrInstSrc *cmp_value, IrInstSrc *new_value,1880 Stage1ZirInst *type_value, Stage1ZirInst *ptr, Stage1ZirInst *cmp_value, Stage1ZirInst *new_value,
1881 IrInstSrc *success_order_value, IrInstSrc *failure_order_value, bool is_weak, ResultLoc *result_loc)1881 Stage1ZirInst *success_order_value, Stage1ZirInst *failure_order_value, bool is_weak, ResultLoc *result_loc)
1882{1882{
1883 IrInstSrcCmpxchg *instruction = ir_build_instruction<IrInstSrcCmpxchg>(ag, scope, source_node);1883 Stage1ZirInstCmpxchg *instruction = ir_build_instruction<Stage1ZirInstCmpxchg>(ag, scope, source_node);
1884 instruction->type_value = type_value;1884 instruction->type_value = type_value;
1885 instruction->ptr = ptr;1885 instruction->ptr = ptr;
1886 instruction->cmp_value = cmp_value;1886 instruction->cmp_value = cmp_value;
...@@ -1900,8 +1900,8 @@ static IrInstSrc *ir_build_cmpxchg_src(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -1900,8 +1900,8 @@ static IrInstSrc *ir_build_cmpxchg_src(Stage1AstGen *ag, Scope *scope, AstNode *
1900 return &instruction->base;1900 return &instruction->base;
1901}1901}
19021902
1903static IrInstSrc *ir_build_fence(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *order) {1903static Stage1ZirInst *ir_build_fence(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *order) {
1904 IrInstSrcFence *instruction = ir_build_instruction<IrInstSrcFence>(ag, scope, source_node);1904 Stage1ZirInstFence *instruction = ir_build_instruction<Stage1ZirInstFence>(ag, scope, source_node);
1905 instruction->order = order;1905 instruction->order = order;
19061906
1907 ir_ref_instruction(order, ag->current_basic_block);1907 ir_ref_instruction(order, ag->current_basic_block);
...@@ -1909,8 +1909,8 @@ static IrInstSrc *ir_build_fence(Stage1AstGen *ag, Scope *scope, AstNode *source...@@ -1909,8 +1909,8 @@ static IrInstSrc *ir_build_fence(Stage1AstGen *ag, Scope *scope, AstNode *source
1909 return &instruction->base;1909 return &instruction->base;
1910}1910}
19111911
1912static IrInstSrc *ir_build_reduce(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *op, IrInstSrc *value) {1912static Stage1ZirInst *ir_build_reduce(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *op, Stage1ZirInst *value) {
1913 IrInstSrcReduce *instruction = ir_build_instruction<IrInstSrcReduce>(ag, scope, source_node);1913 Stage1ZirInstReduce *instruction = ir_build_instruction<Stage1ZirInstReduce>(ag, scope, source_node);
1914 instruction->op = op;1914 instruction->op = op;
1915 instruction->value = value;1915 instruction->value = value;
19161916
...@@ -1920,10 +1920,10 @@ static IrInstSrc *ir_build_reduce(Stage1AstGen *ag, Scope *scope, AstNode *sourc...@@ -1920,10 +1920,10 @@ static IrInstSrc *ir_build_reduce(Stage1AstGen *ag, Scope *scope, AstNode *sourc
1920 return &instruction->base;1920 return &instruction->base;
1921}1921}
19221922
1923static IrInstSrc *ir_build_truncate(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1923static Stage1ZirInst *ir_build_truncate(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1924 IrInstSrc *dest_type, IrInstSrc *target)1924 Stage1ZirInst *dest_type, Stage1ZirInst *target)
1925{1925{
1926 IrInstSrcTruncate *instruction = ir_build_instruction<IrInstSrcTruncate>(ag, scope, source_node);1926 Stage1ZirInstTruncate *instruction = ir_build_instruction<Stage1ZirInstTruncate>(ag, scope, source_node);
1927 instruction->dest_type = dest_type;1927 instruction->dest_type = dest_type;
1928 instruction->target = target;1928 instruction->target = target;
19291929
...@@ -1933,10 +1933,10 @@ static IrInstSrc *ir_build_truncate(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1933,10 +1933,10 @@ static IrInstSrc *ir_build_truncate(Stage1AstGen *ag, Scope *scope, AstNode *sou
1933 return &instruction->base;1933 return &instruction->base;
1934}1934}
19351935
1936static IrInstSrc *ir_build_int_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *dest_type,1936static Stage1ZirInst *ir_build_int_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *dest_type,
1937 IrInstSrc *target)1937 Stage1ZirInst *target)
1938{1938{
1939 IrInstSrcIntCast *instruction = ir_build_instruction<IrInstSrcIntCast>(ag, scope, source_node);1939 Stage1ZirInstIntCast *instruction = ir_build_instruction<Stage1ZirInstIntCast>(ag, scope, source_node);
1940 instruction->dest_type = dest_type;1940 instruction->dest_type = dest_type;
1941 instruction->target = target;1941 instruction->target = target;
19421942
...@@ -1946,10 +1946,10 @@ static IrInstSrc *ir_build_int_cast(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1946,10 +1946,10 @@ static IrInstSrc *ir_build_int_cast(Stage1AstGen *ag, Scope *scope, AstNode *sou
1946 return &instruction->base;1946 return &instruction->base;
1947}1947}
19481948
1949static IrInstSrc *ir_build_float_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *dest_type,1949static Stage1ZirInst *ir_build_float_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *dest_type,
1950 IrInstSrc *target)1950 Stage1ZirInst *target)
1951{1951{
1952 IrInstSrcFloatCast *instruction = ir_build_instruction<IrInstSrcFloatCast>(ag, scope, source_node);1952 Stage1ZirInstFloatCast *instruction = ir_build_instruction<Stage1ZirInstFloatCast>(ag, scope, source_node);
1953 instruction->dest_type = dest_type;1953 instruction->dest_type = dest_type;
1954 instruction->target = target;1954 instruction->target = target;
19551955
...@@ -1959,10 +1959,10 @@ static IrInstSrc *ir_build_float_cast(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -1959,10 +1959,10 @@ static IrInstSrc *ir_build_float_cast(Stage1AstGen *ag, Scope *scope, AstNode *s
1959 return &instruction->base;1959 return &instruction->base;
1960}1960}
19611961
1962static IrInstSrc *ir_build_err_set_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1962static Stage1ZirInst *ir_build_err_set_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1963 IrInstSrc *dest_type, IrInstSrc *target)1963 Stage1ZirInst *dest_type, Stage1ZirInst *target)
1964{1964{
1965 IrInstSrcErrSetCast *instruction = ir_build_instruction<IrInstSrcErrSetCast>(ag, scope, source_node);1965 Stage1ZirInstErrSetCast *instruction = ir_build_instruction<Stage1ZirInstErrSetCast>(ag, scope, source_node);
1966 instruction->dest_type = dest_type;1966 instruction->dest_type = dest_type;
1967 instruction->target = target;1967 instruction->target = target;
19681968
...@@ -1972,10 +1972,10 @@ static IrInstSrc *ir_build_err_set_cast(Stage1AstGen *ag, Scope *scope, AstNode...@@ -1972,10 +1972,10 @@ static IrInstSrc *ir_build_err_set_cast(Stage1AstGen *ag, Scope *scope, AstNode
1972 return &instruction->base;1972 return &instruction->base;
1973}1973}
19741974
1975static IrInstSrc *ir_build_int_to_float(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1975static Stage1ZirInst *ir_build_int_to_float(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1976 IrInstSrc *dest_type, IrInstSrc *target)1976 Stage1ZirInst *dest_type, Stage1ZirInst *target)
1977{1977{
1978 IrInstSrcIntToFloat *instruction = ir_build_instruction<IrInstSrcIntToFloat>(ag, scope, source_node);1978 Stage1ZirInstIntToFloat *instruction = ir_build_instruction<Stage1ZirInstIntToFloat>(ag, scope, source_node);
1979 instruction->dest_type = dest_type;1979 instruction->dest_type = dest_type;
1980 instruction->target = target;1980 instruction->target = target;
19811981
...@@ -1985,10 +1985,10 @@ static IrInstSrc *ir_build_int_to_float(Stage1AstGen *ag, Scope *scope, AstNode...@@ -1985,10 +1985,10 @@ static IrInstSrc *ir_build_int_to_float(Stage1AstGen *ag, Scope *scope, AstNode
1985 return &instruction->base;1985 return &instruction->base;
1986}1986}
19871987
1988static IrInstSrc *ir_build_float_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1988static Stage1ZirInst *ir_build_float_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1989 IrInstSrc *dest_type, IrInstSrc *target)1989 Stage1ZirInst *dest_type, Stage1ZirInst *target)
1990{1990{
1991 IrInstSrcFloatToInt *instruction = ir_build_instruction<IrInstSrcFloatToInt>(ag, scope, source_node);1991 Stage1ZirInstFloatToInt *instruction = ir_build_instruction<Stage1ZirInstFloatToInt>(ag, scope, source_node);
1992 instruction->dest_type = dest_type;1992 instruction->dest_type = dest_type;
1993 instruction->target = target;1993 instruction->target = target;
19941994
...@@ -1998,8 +1998,8 @@ static IrInstSrc *ir_build_float_to_int(Stage1AstGen *ag, Scope *scope, AstNode...@@ -1998,8 +1998,8 @@ static IrInstSrc *ir_build_float_to_int(Stage1AstGen *ag, Scope *scope, AstNode
1998 return &instruction->base;1998 return &instruction->base;
1999}1999}
20002000
2001static IrInstSrc *ir_build_bool_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *target) {2001static Stage1ZirInst *ir_build_bool_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *target) {
2002 IrInstSrcBoolToInt *instruction = ir_build_instruction<IrInstSrcBoolToInt>(ag, scope, source_node);2002 Stage1ZirInstBoolToInt *instruction = ir_build_instruction<Stage1ZirInstBoolToInt>(ag, scope, source_node);
2003 instruction->target = target;2003 instruction->target = target;
20042004
2005 ir_ref_instruction(target, ag->current_basic_block);2005 ir_ref_instruction(target, ag->current_basic_block);
...@@ -2007,10 +2007,10 @@ static IrInstSrc *ir_build_bool_to_int(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -2007,10 +2007,10 @@ static IrInstSrc *ir_build_bool_to_int(Stage1AstGen *ag, Scope *scope, AstNode *
2007 return &instruction->base;2007 return &instruction->base;
2008}2008}
20092009
2010static IrInstSrc *ir_build_vector_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *len,2010static Stage1ZirInst *ir_build_vector_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *len,
2011 IrInstSrc *elem_type)2011 Stage1ZirInst *elem_type)
2012{2012{
2013 IrInstSrcVectorType *instruction = ir_build_instruction<IrInstSrcVectorType>(ag, scope, source_node);2013 Stage1ZirInstVectorType *instruction = ir_build_instruction<Stage1ZirInstVectorType>(ag, scope, source_node);
2014 instruction->len = len;2014 instruction->len = len;
2015 instruction->elem_type = elem_type;2015 instruction->elem_type = elem_type;
20162016
...@@ -2020,10 +2020,10 @@ static IrInstSrc *ir_build_vector_type(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -2020,10 +2020,10 @@ static IrInstSrc *ir_build_vector_type(Stage1AstGen *ag, Scope *scope, AstNode *
2020 return &instruction->base;2020 return &instruction->base;
2021}2021}
20222022
2023static IrInstSrc *ir_build_shuffle_vector(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2023static Stage1ZirInst *ir_build_shuffle_vector(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2024 IrInstSrc *scalar_type, IrInstSrc *a, IrInstSrc *b, IrInstSrc *mask)2024 Stage1ZirInst *scalar_type, Stage1ZirInst *a, Stage1ZirInst *b, Stage1ZirInst *mask)
2025{2025{
2026 IrInstSrcShuffleVector *instruction = ir_build_instruction<IrInstSrcShuffleVector>(ag, scope, source_node);2026 Stage1ZirInstShuffleVector *instruction = ir_build_instruction<Stage1ZirInstShuffleVector>(ag, scope, source_node);
2027 instruction->scalar_type = scalar_type;2027 instruction->scalar_type = scalar_type;
2028 instruction->a = a;2028 instruction->a = a;
2029 instruction->b = b;2029 instruction->b = b;
...@@ -2037,10 +2037,10 @@ static IrInstSrc *ir_build_shuffle_vector(Stage1AstGen *ag, Scope *scope, AstNod...@@ -2037,10 +2037,10 @@ static IrInstSrc *ir_build_shuffle_vector(Stage1AstGen *ag, Scope *scope, AstNod
2037 return &instruction->base;2037 return &instruction->base;
2038}2038}
20392039
2040static IrInstSrc *ir_build_splat_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2040static Stage1ZirInst *ir_build_splat_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2041 IrInstSrc *len, IrInstSrc *scalar)2041 Stage1ZirInst *len, Stage1ZirInst *scalar)
2042{2042{
2043 IrInstSrcSplat *instruction = ir_build_instruction<IrInstSrcSplat>(ag, scope, source_node);2043 Stage1ZirInstSplat *instruction = ir_build_instruction<Stage1ZirInstSplat>(ag, scope, source_node);
2044 instruction->len = len;2044 instruction->len = len;
2045 instruction->scalar = scalar;2045 instruction->scalar = scalar;
20462046
...@@ -2050,8 +2050,8 @@ static IrInstSrc *ir_build_splat_src(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -2050,8 +2050,8 @@ static IrInstSrc *ir_build_splat_src(Stage1AstGen *ag, Scope *scope, AstNode *so
2050 return &instruction->base;2050 return &instruction->base;
2051}2051}
20522052
2053static IrInstSrc *ir_build_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) {2053static Stage1ZirInst *ir_build_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) {
2054 IrInstSrcBoolNot *instruction = ir_build_instruction<IrInstSrcBoolNot>(ag, scope, source_node);2054 Stage1ZirInstBoolNot *instruction = ir_build_instruction<Stage1ZirInstBoolNot>(ag, scope, source_node);
2055 instruction->value = value;2055 instruction->value = value;
20562056
2057 ir_ref_instruction(value, ag->current_basic_block);2057 ir_ref_instruction(value, ag->current_basic_block);
...@@ -2059,10 +2059,10 @@ static IrInstSrc *ir_build_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -2059,10 +2059,10 @@ static IrInstSrc *ir_build_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *sou
2059 return &instruction->base;2059 return &instruction->base;
2060}2060}
20612061
2062static IrInstSrc *ir_build_memset_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2062static Stage1ZirInst *ir_build_memset_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2063 IrInstSrc *dest_ptr, IrInstSrc *byte, IrInstSrc *count)2063 Stage1ZirInst *dest_ptr, Stage1ZirInst *byte, Stage1ZirInst *count)
2064{2064{
2065 IrInstSrcMemset *instruction = ir_build_instruction<IrInstSrcMemset>(ag, scope, source_node);2065 Stage1ZirInstMemset *instruction = ir_build_instruction<Stage1ZirInstMemset>(ag, scope, source_node);
2066 instruction->dest_ptr = dest_ptr;2066 instruction->dest_ptr = dest_ptr;
2067 instruction->byte = byte;2067 instruction->byte = byte;
2068 instruction->count = count;2068 instruction->count = count;
...@@ -2074,10 +2074,10 @@ static IrInstSrc *ir_build_memset_src(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -2074,10 +2074,10 @@ static IrInstSrc *ir_build_memset_src(Stage1AstGen *ag, Scope *scope, AstNode *s
2074 return &instruction->base;2074 return &instruction->base;
2075}2075}
20762076
2077static IrInstSrc *ir_build_memcpy_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2077static Stage1ZirInst *ir_build_memcpy_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2078 IrInstSrc *dest_ptr, IrInstSrc *src_ptr, IrInstSrc *count)2078 Stage1ZirInst *dest_ptr, Stage1ZirInst *src_ptr, Stage1ZirInst *count)
2079{2079{
2080 IrInstSrcMemcpy *instruction = ir_build_instruction<IrInstSrcMemcpy>(ag, scope, source_node);2080 Stage1ZirInstMemcpy *instruction = ir_build_instruction<Stage1ZirInstMemcpy>(ag, scope, source_node);
2081 instruction->dest_ptr = dest_ptr;2081 instruction->dest_ptr = dest_ptr;
2082 instruction->src_ptr = src_ptr;2082 instruction->src_ptr = src_ptr;
2083 instruction->count = count;2083 instruction->count = count;
...@@ -2089,11 +2089,11 @@ static IrInstSrc *ir_build_memcpy_src(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -2089,11 +2089,11 @@ static IrInstSrc *ir_build_memcpy_src(Stage1AstGen *ag, Scope *scope, AstNode *s
2089 return &instruction->base;2089 return &instruction->base;
2090}2090}
20912091
2092static IrInstSrc *ir_build_slice_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2092static Stage1ZirInst *ir_build_slice_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2093 IrInstSrc *ptr, IrInstSrc *start, IrInstSrc *end, IrInstSrc *sentinel,2093 Stage1ZirInst *ptr, Stage1ZirInst *start, Stage1ZirInst *end, Stage1ZirInst *sentinel,
2094 bool safety_check_on, ResultLoc *result_loc)2094 bool safety_check_on, ResultLoc *result_loc)
2095{2095{
2096 IrInstSrcSlice *instruction = ir_build_instruction<IrInstSrcSlice>(ag, scope, source_node);2096 Stage1ZirInstSlice *instruction = ir_build_instruction<Stage1ZirInstSlice>(ag, scope, source_node);
2097 instruction->ptr = ptr;2097 instruction->ptr = ptr;
2098 instruction->start = start;2098 instruction->start = start;
2099 instruction->end = end;2099 instruction->end = end;
...@@ -2109,28 +2109,28 @@ static IrInstSrc *ir_build_slice_src(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -2109,28 +2109,28 @@ static IrInstSrc *ir_build_slice_src(Stage1AstGen *ag, Scope *scope, AstNode *so
2109 return &instruction->base;2109 return &instruction->base;
2110}2110}
21112111
2112static IrInstSrc *ir_build_breakpoint(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {2112static Stage1ZirInst *ir_build_breakpoint(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2113 IrInstSrcBreakpoint *instruction = ir_build_instruction<IrInstSrcBreakpoint>(ag, scope, source_node);2113 Stage1ZirInstBreakpoint *instruction = ir_build_instruction<Stage1ZirInstBreakpoint>(ag, scope, source_node);
2114 return &instruction->base;2114 return &instruction->base;
2115}2115}
21162116
2117static IrInstSrc *ir_build_return_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {2117static Stage1ZirInst *ir_build_return_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2118 IrInstSrcReturnAddress *instruction = ir_build_instruction<IrInstSrcReturnAddress>(ag, scope, source_node);2118 Stage1ZirInstReturnAddress *instruction = ir_build_instruction<Stage1ZirInstReturnAddress>(ag, scope, source_node);
2119 return &instruction->base;2119 return &instruction->base;
2120}2120}
21212121
2122static IrInstSrc *ir_build_frame_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {2122static Stage1ZirInst *ir_build_frame_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2123 IrInstSrcFrameAddress *inst = ir_build_instruction<IrInstSrcFrameAddress>(ag, scope, source_node);2123 Stage1ZirInstFrameAddress *inst = ir_build_instruction<Stage1ZirInstFrameAddress>(ag, scope, source_node);
2124 return &inst->base;2124 return &inst->base;
2125}2125}
21262126
2127static IrInstSrc *ir_build_handle_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {2127static Stage1ZirInst *ir_build_handle_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2128 IrInstSrcFrameHandle *inst = ir_build_instruction<IrInstSrcFrameHandle>(ag, scope, source_node);2128 Stage1ZirInstFrameHandle *inst = ir_build_instruction<Stage1ZirInstFrameHandle>(ag, scope, source_node);
2129 return &inst->base;2129 return &inst->base;
2130}2130}
21312131
2132static IrInstSrc *ir_build_frame_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *fn) {2132static Stage1ZirInst *ir_build_frame_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *fn) {
2133 IrInstSrcFrameType *inst = ir_build_instruction<IrInstSrcFrameType>(ag, scope, source_node);2133 Stage1ZirInstFrameType *inst = ir_build_instruction<Stage1ZirInstFrameType>(ag, scope, source_node);
2134 inst->fn = fn;2134 inst->fn = fn;
21352135
2136 ir_ref_instruction(fn, ag->current_basic_block);2136 ir_ref_instruction(fn, ag->current_basic_block);
...@@ -2138,8 +2138,8 @@ static IrInstSrc *ir_build_frame_type(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -2138,8 +2138,8 @@ static IrInstSrc *ir_build_frame_type(Stage1AstGen *ag, Scope *scope, AstNode *s
2138 return &inst->base;2138 return &inst->base;
2139}2139}
21402140
2141static IrInstSrc *ir_build_frame_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *fn) {2141static Stage1ZirInst *ir_build_frame_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *fn) {
2142 IrInstSrcFrameSize *inst = ir_build_instruction<IrInstSrcFrameSize>(ag, scope, source_node);2142 Stage1ZirInstFrameSize *inst = ir_build_instruction<Stage1ZirInstFrameSize>(ag, scope, source_node);
2143 inst->fn = fn;2143 inst->fn = fn;
21442144
2145 ir_ref_instruction(fn, ag->current_basic_block);2145 ir_ref_instruction(fn, ag->current_basic_block);
...@@ -2147,10 +2147,10 @@ static IrInstSrc *ir_build_frame_size_src(Stage1AstGen *ag, Scope *scope, AstNod...@@ -2147,10 +2147,10 @@ static IrInstSrc *ir_build_frame_size_src(Stage1AstGen *ag, Scope *scope, AstNod
2147 return &inst->base;2147 return &inst->base;
2148}2148}
21492149
2150static IrInstSrc *ir_build_overflow_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2150static Stage1ZirInst *ir_build_overflow_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2151 IrOverflowOp op, IrInstSrc *type_value, IrInstSrc *op1, IrInstSrc *op2, IrInstSrc *result_ptr)2151 IrOverflowOp op, Stage1ZirInst *type_value, Stage1ZirInst *op1, Stage1ZirInst *op2, Stage1ZirInst *result_ptr)
2152{2152{
2153 IrInstSrcOverflowOp *instruction = ir_build_instruction<IrInstSrcOverflowOp>(ag, scope, source_node);2153 Stage1ZirInstOverflowOp *instruction = ir_build_instruction<Stage1ZirInstOverflowOp>(ag, scope, source_node);
2154 instruction->op = op;2154 instruction->op = op;
2155 instruction->type_value = type_value;2155 instruction->type_value = type_value;
2156 instruction->op1 = op1;2156 instruction->op1 = op1;
...@@ -2165,10 +2165,10 @@ static IrInstSrc *ir_build_overflow_op_src(Stage1AstGen *ag, Scope *scope, AstNo...@@ -2165,10 +2165,10 @@ static IrInstSrc *ir_build_overflow_op_src(Stage1AstGen *ag, Scope *scope, AstNo
2165 return &instruction->base;2165 return &instruction->base;
2166}2166}
21672167
2168static IrInstSrc *ir_build_float_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *operand,2168static Stage1ZirInst *ir_build_float_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *operand,
2169 BuiltinFnId fn_id)2169 BuiltinFnId fn_id)
2170{2170{
2171 IrInstSrcFloatOp *instruction = ir_build_instruction<IrInstSrcFloatOp>(ag, scope, source_node);2171 Stage1ZirInstFloatOp *instruction = ir_build_instruction<Stage1ZirInstFloatOp>(ag, scope, source_node);
2172 instruction->operand = operand;2172 instruction->operand = operand;
2173 instruction->fn_id = fn_id;2173 instruction->fn_id = fn_id;
21742174
...@@ -2177,10 +2177,10 @@ static IrInstSrc *ir_build_float_op_src(Stage1AstGen *ag, Scope *scope, AstNode...@@ -2177,10 +2177,10 @@ static IrInstSrc *ir_build_float_op_src(Stage1AstGen *ag, Scope *scope, AstNode
2177 return &instruction->base;2177 return &instruction->base;
2178}2178}
21792179
2180static IrInstSrc *ir_build_mul_add_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2180static Stage1ZirInst *ir_build_mul_add_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2181 IrInstSrc *type_value, IrInstSrc *op1, IrInstSrc *op2, IrInstSrc *op3)2181 Stage1ZirInst *type_value, Stage1ZirInst *op1, Stage1ZirInst *op2, Stage1ZirInst *op3)
2182{2182{
2183 IrInstSrcMulAdd *instruction = ir_build_instruction<IrInstSrcMulAdd>(ag, scope, source_node);2183 Stage1ZirInstMulAdd *instruction = ir_build_instruction<Stage1ZirInstMulAdd>(ag, scope, source_node);
2184 instruction->type_value = type_value;2184 instruction->type_value = type_value;
2185 instruction->op1 = op1;2185 instruction->op1 = op1;
2186 instruction->op2 = op2;2186 instruction->op2 = op2;
...@@ -2194,8 +2194,8 @@ static IrInstSrc *ir_build_mul_add_src(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -2194,8 +2194,8 @@ static IrInstSrc *ir_build_mul_add_src(Stage1AstGen *ag, Scope *scope, AstNode *
2194 return &instruction->base;2194 return &instruction->base;
2195}2195}
21962196
2197static IrInstSrc *ir_build_align_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_value) {2197static Stage1ZirInst *ir_build_align_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_value) {
2198 IrInstSrcAlignOf *instruction = ir_build_instruction<IrInstSrcAlignOf>(ag, scope, source_node);2198 Stage1ZirInstAlignOf *instruction = ir_build_instruction<Stage1ZirInstAlignOf>(ag, scope, source_node);
2199 instruction->type_value = type_value;2199 instruction->type_value = type_value;
22002200
2201 ir_ref_instruction(type_value, ag->current_basic_block);2201 ir_ref_instruction(type_value, ag->current_basic_block);
...@@ -2203,10 +2203,10 @@ static IrInstSrc *ir_build_align_of(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -2203,10 +2203,10 @@ static IrInstSrc *ir_build_align_of(Stage1AstGen *ag, Scope *scope, AstNode *sou
2203 return &instruction->base;2203 return &instruction->base;
2204}2204}
22052205
2206static IrInstSrc *ir_build_test_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2206static Stage1ZirInst *ir_build_test_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2207 IrInstSrc *base_ptr, bool resolve_err_set, bool base_ptr_is_payload)2207 Stage1ZirInst *base_ptr, bool resolve_err_set, bool base_ptr_is_payload)
2208{2208{
2209 IrInstSrcTestErr *instruction = ir_build_instruction<IrInstSrcTestErr>(ag, scope, source_node);2209 Stage1ZirInstTestErr *instruction = ir_build_instruction<Stage1ZirInstTestErr>(ag, scope, source_node);
2210 instruction->base_ptr = base_ptr;2210 instruction->base_ptr = base_ptr;
2211 instruction->resolve_err_set = resolve_err_set;2211 instruction->resolve_err_set = resolve_err_set;
2212 instruction->base_ptr_is_payload = base_ptr_is_payload;2212 instruction->base_ptr_is_payload = base_ptr_is_payload;
...@@ -2216,10 +2216,10 @@ static IrInstSrc *ir_build_test_err_src(Stage1AstGen *ag, Scope *scope, AstNode...@@ -2216,10 +2216,10 @@ static IrInstSrc *ir_build_test_err_src(Stage1AstGen *ag, Scope *scope, AstNode
2216 return &instruction->base;2216 return &instruction->base;
2217}2217}
22182218
2219static IrInstSrc *ir_build_unwrap_err_code_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2219static Stage1ZirInst *ir_build_unwrap_err_code_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2220 IrInstSrc *err_union_ptr)2220 Stage1ZirInst *err_union_ptr)
2221{2221{
2222 IrInstSrcUnwrapErrCode *inst = ir_build_instruction<IrInstSrcUnwrapErrCode>(ag, scope, source_node);2222 Stage1ZirInstUnwrapErrCode *inst = ir_build_instruction<Stage1ZirInstUnwrapErrCode>(ag, scope, source_node);
2223 inst->err_union_ptr = err_union_ptr;2223 inst->err_union_ptr = err_union_ptr;
22242224
2225 ir_ref_instruction(err_union_ptr, ag->current_basic_block);2225 ir_ref_instruction(err_union_ptr, ag->current_basic_block);
...@@ -2227,10 +2227,10 @@ static IrInstSrc *ir_build_unwrap_err_code_src(Stage1AstGen *ag, Scope *scope, A...@@ -2227,10 +2227,10 @@ static IrInstSrc *ir_build_unwrap_err_code_src(Stage1AstGen *ag, Scope *scope, A
2227 return &inst->base;2227 return &inst->base;
2228}2228}
22292229
2230static IrInstSrc *ir_build_unwrap_err_payload_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2230static Stage1ZirInst *ir_build_unwrap_err_payload_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2231 IrInstSrc *value, bool safety_check_on, bool initializing)2231 Stage1ZirInst *value, bool safety_check_on, bool initializing)
2232{2232{
2233 IrInstSrcUnwrapErrPayload *inst = ir_build_instruction<IrInstSrcUnwrapErrPayload>(ag, scope, source_node);2233 Stage1ZirInstUnwrapErrPayload *inst = ir_build_instruction<Stage1ZirInstUnwrapErrPayload>(ag, scope, source_node);
2234 inst->value = value;2234 inst->value = value;
2235 inst->safety_check_on = safety_check_on;2235 inst->safety_check_on = safety_check_on;
2236 inst->initializing = initializing;2236 inst->initializing = initializing;
...@@ -2240,11 +2240,11 @@ static IrInstSrc *ir_build_unwrap_err_payload_src(Stage1AstGen *ag, Scope *scope...@@ -2240,11 +2240,11 @@ static IrInstSrc *ir_build_unwrap_err_payload_src(Stage1AstGen *ag, Scope *scope
2240 return &inst->base;2240 return &inst->base;
2241}2241}
22422242
2243static IrInstSrc *ir_build_fn_proto(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2243static Stage1ZirInst *ir_build_fn_proto(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2244 IrInstSrc **param_types, IrInstSrc *align_value, IrInstSrc *callconv_value,2244 Stage1ZirInst **param_types, Stage1ZirInst *align_value, Stage1ZirInst *callconv_value,
2245 IrInstSrc *return_type, bool is_var_args)2245 Stage1ZirInst *return_type, bool is_var_args)
2246{2246{
2247 IrInstSrcFnProto *instruction = ir_build_instruction<IrInstSrcFnProto>(ag, scope, source_node);2247 Stage1ZirInstFnProto *instruction = ir_build_instruction<Stage1ZirInstFnProto>(ag, scope, source_node);
2248 instruction->param_types = param_types;2248 instruction->param_types = param_types;
2249 instruction->align_value = align_value;2249 instruction->align_value = align_value;
2250 instruction->callconv_value = callconv_value;2250 instruction->callconv_value = callconv_value;
...@@ -2264,8 +2264,8 @@ static IrInstSrc *ir_build_fn_proto(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -2264,8 +2264,8 @@ static IrInstSrc *ir_build_fn_proto(Stage1AstGen *ag, Scope *scope, AstNode *sou
2264 return &instruction->base;2264 return &instruction->base;
2265}2265}
22662266
2267static IrInstSrc *ir_build_test_comptime(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) {2267static Stage1ZirInst *ir_build_test_comptime(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) {
2268 IrInstSrcTestComptime *instruction = ir_build_instruction<IrInstSrcTestComptime>(ag, scope, source_node);2268 Stage1ZirInstTestComptime *instruction = ir_build_instruction<Stage1ZirInstTestComptime>(ag, scope, source_node);
2269 instruction->value = value;2269 instruction->value = value;
22702270
2271 ir_ref_instruction(value, ag->current_basic_block);2271 ir_ref_instruction(value, ag->current_basic_block);
...@@ -2273,10 +2273,10 @@ static IrInstSrc *ir_build_test_comptime(Stage1AstGen *ag, Scope *scope, AstNode...@@ -2273,10 +2273,10 @@ static IrInstSrc *ir_build_test_comptime(Stage1AstGen *ag, Scope *scope, AstNode
2273 return &instruction->base;2273 return &instruction->base;
2274}2274}
22752275
2276static IrInstSrc *ir_build_ptr_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2276static Stage1ZirInst *ir_build_ptr_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2277 IrInstSrc *dest_type, IrInstSrc *ptr, bool safety_check_on)2277 Stage1ZirInst *dest_type, Stage1ZirInst *ptr, bool safety_check_on)
2278{2278{
2279 IrInstSrcPtrCast *instruction = ir_build_instruction<IrInstSrcPtrCast>(2279 Stage1ZirInstPtrCast *instruction = ir_build_instruction<Stage1ZirInstPtrCast>(
2280 ag, scope, source_node);2280 ag, scope, source_node);
2281 instruction->dest_type = dest_type;2281 instruction->dest_type = dest_type;
2282 instruction->ptr = ptr;2282 instruction->ptr = ptr;
...@@ -2288,10 +2288,10 @@ static IrInstSrc *ir_build_ptr_cast_src(Stage1AstGen *ag, Scope *scope, AstNode...@@ -2288,10 +2288,10 @@ static IrInstSrc *ir_build_ptr_cast_src(Stage1AstGen *ag, Scope *scope, AstNode
2288 return &instruction->base;2288 return &instruction->base;
2289}2289}
22902290
2291static IrInstSrc *ir_build_implicit_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2291static Stage1ZirInst *ir_build_implicit_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2292 IrInstSrc *operand, ResultLocCast *result_loc_cast)2292 Stage1ZirInst *operand, ResultLocCast *result_loc_cast)
2293{2293{
2294 IrInstSrcImplicitCast *instruction = ir_build_instruction<IrInstSrcImplicitCast>(ag, scope, source_node);2294 Stage1ZirInstImplicitCast *instruction = ir_build_instruction<Stage1ZirInstImplicitCast>(ag, scope, source_node);
2295 instruction->operand = operand;2295 instruction->operand = operand;
2296 instruction->result_loc_cast = result_loc_cast;2296 instruction->result_loc_cast = result_loc_cast;
22972297
...@@ -2300,10 +2300,10 @@ static IrInstSrc *ir_build_implicit_cast(Stage1AstGen *ag, Scope *scope, AstNode...@@ -2300,10 +2300,10 @@ static IrInstSrc *ir_build_implicit_cast(Stage1AstGen *ag, Scope *scope, AstNode
2300 return &instruction->base;2300 return &instruction->base;
2301}2301}
23022302
2303static IrInstSrc *ir_build_bit_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2303static Stage1ZirInst *ir_build_bit_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2304 IrInstSrc *operand, ResultLocBitCast *result_loc_bit_cast)2304 Stage1ZirInst *operand, ResultLocBitCast *result_loc_bit_cast)
2305{2305{
2306 IrInstSrcBitCast *instruction = ir_build_instruction<IrInstSrcBitCast>(ag, scope, source_node);2306 Stage1ZirInstBitCast *instruction = ir_build_instruction<Stage1ZirInstBitCast>(ag, scope, source_node);
2307 instruction->operand = operand;2307 instruction->operand = operand;
2308 instruction->result_loc_bit_cast = result_loc_bit_cast;2308 instruction->result_loc_bit_cast = result_loc_bit_cast;
23092309
...@@ -2312,10 +2312,10 @@ static IrInstSrc *ir_build_bit_cast_src(Stage1AstGen *ag, Scope *scope, AstNode...@@ -2312,10 +2312,10 @@ static IrInstSrc *ir_build_bit_cast_src(Stage1AstGen *ag, Scope *scope, AstNode
2312 return &instruction->base;2312 return &instruction->base;
2313}2313}
23142314
2315static IrInstSrc *ir_build_int_to_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2315static Stage1ZirInst *ir_build_int_to_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2316 IrInstSrc *dest_type, IrInstSrc *target)2316 Stage1ZirInst *dest_type, Stage1ZirInst *target)
2317{2317{
2318 IrInstSrcIntToPtr *instruction = ir_build_instruction<IrInstSrcIntToPtr>(ag, scope, source_node);2318 Stage1ZirInstIntToPtr *instruction = ir_build_instruction<Stage1ZirInstIntToPtr>(ag, scope, source_node);
2319 instruction->dest_type = dest_type;2319 instruction->dest_type = dest_type;
2320 instruction->target = target;2320 instruction->target = target;
23212321
...@@ -2325,10 +2325,10 @@ static IrInstSrc *ir_build_int_to_ptr_src(Stage1AstGen *ag, Scope *scope, AstNod...@@ -2325,10 +2325,10 @@ static IrInstSrc *ir_build_int_to_ptr_src(Stage1AstGen *ag, Scope *scope, AstNod
2325 return &instruction->base;2325 return &instruction->base;
2326}2326}
23272327
2328static IrInstSrc *ir_build_ptr_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2328static Stage1ZirInst *ir_build_ptr_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2329 IrInstSrc *target)2329 Stage1ZirInst *target)
2330{2330{
2331 IrInstSrcPtrToInt *inst = ir_build_instruction<IrInstSrcPtrToInt>(ag, scope, source_node);2331 Stage1ZirInstPtrToInt *inst = ir_build_instruction<Stage1ZirInstPtrToInt>(ag, scope, source_node);
2332 inst->target = target;2332 inst->target = target;
23332333
2334 ir_ref_instruction(target, ag->current_basic_block);2334 ir_ref_instruction(target, ag->current_basic_block);
...@@ -2336,10 +2336,10 @@ static IrInstSrc *ir_build_ptr_to_int_src(Stage1AstGen *ag, Scope *scope, AstNod...@@ -2336,10 +2336,10 @@ static IrInstSrc *ir_build_ptr_to_int_src(Stage1AstGen *ag, Scope *scope, AstNod
2336 return &inst->base;2336 return &inst->base;
2337}2337}
23382338
2339static IrInstSrc *ir_build_int_to_enum_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2339static Stage1ZirInst *ir_build_int_to_enum_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2340 IrInstSrc *dest_type, IrInstSrc *target)2340 Stage1ZirInst *dest_type, Stage1ZirInst *target)
2341{2341{
2342 IrInstSrcIntToEnum *instruction = ir_build_instruction<IrInstSrcIntToEnum>(ag, scope, source_node);2342 Stage1ZirInstIntToEnum *instruction = ir_build_instruction<Stage1ZirInstIntToEnum>(ag, scope, source_node);
2343 instruction->dest_type = dest_type;2343 instruction->dest_type = dest_type;
2344 instruction->target = target;2344 instruction->target = target;
23452345
...@@ -2349,10 +2349,10 @@ static IrInstSrc *ir_build_int_to_enum_src(Stage1AstGen *ag, Scope *scope, AstNo...@@ -2349,10 +2349,10 @@ static IrInstSrc *ir_build_int_to_enum_src(Stage1AstGen *ag, Scope *scope, AstNo
2349 return &instruction->base;2349 return &instruction->base;
2350}2350}
23512351
2352static IrInstSrc *ir_build_enum_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2352static Stage1ZirInst *ir_build_enum_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2353 IrInstSrc *target)2353 Stage1ZirInst *target)
2354{2354{
2355 IrInstSrcEnumToInt *instruction = ir_build_instruction<IrInstSrcEnumToInt>(2355 Stage1ZirInstEnumToInt *instruction = ir_build_instruction<Stage1ZirInstEnumToInt>(
2356 ag, scope, source_node);2356 ag, scope, source_node);
2357 instruction->target = target;2357 instruction->target = target;
23582358
...@@ -2361,10 +2361,10 @@ static IrInstSrc *ir_build_enum_to_int(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -2361,10 +2361,10 @@ static IrInstSrc *ir_build_enum_to_int(Stage1AstGen *ag, Scope *scope, AstNode *
2361 return &instruction->base;2361 return &instruction->base;
2362}2362}
23632363
2364static IrInstSrc *ir_build_int_to_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2364static Stage1ZirInst *ir_build_int_to_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2365 IrInstSrc *target)2365 Stage1ZirInst *target)
2366{2366{
2367 IrInstSrcIntToErr *instruction = ir_build_instruction<IrInstSrcIntToErr>(ag, scope, source_node);2367 Stage1ZirInstIntToErr *instruction = ir_build_instruction<Stage1ZirInstIntToErr>(ag, scope, source_node);
2368 instruction->target = target;2368 instruction->target = target;
23692369
2370 ir_ref_instruction(target, ag->current_basic_block);2370 ir_ref_instruction(target, ag->current_basic_block);
...@@ -2372,10 +2372,10 @@ static IrInstSrc *ir_build_int_to_err_src(Stage1AstGen *ag, Scope *scope, AstNod...@@ -2372,10 +2372,10 @@ static IrInstSrc *ir_build_int_to_err_src(Stage1AstGen *ag, Scope *scope, AstNod
2372 return &instruction->base;2372 return &instruction->base;
2373}2373}
23742374
2375static IrInstSrc *ir_build_err_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2375static Stage1ZirInst *ir_build_err_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2376 IrInstSrc *target)2376 Stage1ZirInst *target)
2377{2377{
2378 IrInstSrcErrToInt *instruction = ir_build_instruction<IrInstSrcErrToInt>(2378 Stage1ZirInstErrToInt *instruction = ir_build_instruction<Stage1ZirInstErrToInt>(
2379 ag, scope, source_node);2379 ag, scope, source_node);
2380 instruction->target = target;2380 instruction->target = target;
23812381
...@@ -2384,13 +2384,13 @@ static IrInstSrc *ir_build_err_to_int_src(Stage1AstGen *ag, Scope *scope, AstNod...@@ -2384,13 +2384,13 @@ static IrInstSrc *ir_build_err_to_int_src(Stage1AstGen *ag, Scope *scope, AstNod
2384 return &instruction->base;2384 return &instruction->base;
2385}2385}
23862386
2387static IrInstSrc *ir_build_check_switch_prongs(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2387static Stage1ZirInst *ir_build_check_switch_prongs(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2388 IrInstSrc *target_value, IrInstSrcCheckSwitchProngsRange *ranges, size_t range_count,2388 Stage1ZirInst *target_value, Stage1ZirInstCheckSwitchProngsRange *ranges, size_t range_count,
2389 AstNode* else_prong, bool have_underscore_prong)2389 AstNode* else_prong, bool have_underscore_prong)
2390{2390{
2391 IrInstSrcCheckSwitchProngs *instruction = heap::c_allocator.create<IrInstSrcCheckSwitchProngs>();2391 Stage1ZirInstCheckSwitchProngs *instruction = heap::c_allocator.create<Stage1ZirInstCheckSwitchProngs>();
2392 instruction->base.id = have_underscore_prong ?2392 instruction->base.id = have_underscore_prong ?
2393 IrInstSrcIdCheckSwitchProngsUnderYes : IrInstSrcIdCheckSwitchProngsUnderNo;2393 Stage1ZirInstIdCheckSwitchProngsUnderYes : Stage1ZirInstIdCheckSwitchProngsUnderNo;
2394 instruction->base.scope = scope;2394 instruction->base.scope = scope;
2395 instruction->base.source_node = source_node;2395 instruction->base.source_node = source_node;
2396 instruction->base.debug_id = irb_next_debug_id(ag);2396 instruction->base.debug_id = irb_next_debug_id(ag);
...@@ -2411,10 +2411,10 @@ static IrInstSrc *ir_build_check_switch_prongs(Stage1AstGen *ag, Scope *scope, A...@@ -2411,10 +2411,10 @@ static IrInstSrc *ir_build_check_switch_prongs(Stage1AstGen *ag, Scope *scope, A
2411 return &instruction->base;2411 return &instruction->base;
2412}2412}
24132413
2414static IrInstSrc *ir_build_check_statement_is_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2414static Stage1ZirInst *ir_build_check_statement_is_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2415 IrInstSrc* statement_value)2415 Stage1ZirInst* statement_value)
2416{2416{
2417 IrInstSrcCheckStatementIsVoid *instruction = ir_build_instruction<IrInstSrcCheckStatementIsVoid>(2417 Stage1ZirInstCheckStatementIsVoid *instruction = ir_build_instruction<Stage1ZirInstCheckStatementIsVoid>(
2418 ag, scope, source_node);2418 ag, scope, source_node);
2419 instruction->statement_value = statement_value;2419 instruction->statement_value = statement_value;
24202420
...@@ -2423,10 +2423,10 @@ static IrInstSrc *ir_build_check_statement_is_void(Stage1AstGen *ag, Scope *scop...@@ -2423,10 +2423,10 @@ static IrInstSrc *ir_build_check_statement_is_void(Stage1AstGen *ag, Scope *scop
2423 return &instruction->base;2423 return &instruction->base;
2424}2424}
24252425
2426static IrInstSrc *ir_build_type_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2426static Stage1ZirInst *ir_build_type_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2427 IrInstSrc *type_value)2427 Stage1ZirInst *type_value)
2428{2428{
2429 IrInstSrcTypeName *instruction = ir_build_instruction<IrInstSrcTypeName>(ag, scope, source_node);2429 Stage1ZirInstTypeName *instruction = ir_build_instruction<Stage1ZirInstTypeName>(ag, scope, source_node);
2430 instruction->type_value = type_value;2430 instruction->type_value = type_value;
24312431
2432 ir_ref_instruction(type_value, ag->current_basic_block);2432 ir_ref_instruction(type_value, ag->current_basic_block);
...@@ -2434,16 +2434,16 @@ static IrInstSrc *ir_build_type_name(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -2434,16 +2434,16 @@ static IrInstSrc *ir_build_type_name(Stage1AstGen *ag, Scope *scope, AstNode *so
2434 return &instruction->base;2434 return &instruction->base;
2435}2435}
24362436
2437static IrInstSrc *ir_build_decl_ref(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Tld *tld, LVal lval) {2437static Stage1ZirInst *ir_build_decl_ref(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Tld *tld, LVal lval) {
2438 IrInstSrcDeclRef *instruction = ir_build_instruction<IrInstSrcDeclRef>(ag, scope, source_node);2438 Stage1ZirInstDeclRef *instruction = ir_build_instruction<Stage1ZirInstDeclRef>(ag, scope, source_node);
2439 instruction->tld = tld;2439 instruction->tld = tld;
2440 instruction->lval = lval;2440 instruction->lval = lval;
24412441
2442 return &instruction->base;2442 return &instruction->base;
2443}2443}
24442444
2445static IrInstSrc *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *msg) {2445static Stage1ZirInst *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *msg) {
2446 IrInstSrcPanic *instruction = ir_build_instruction<IrInstSrcPanic>(ag, scope, source_node);2446 Stage1ZirInstPanic *instruction = ir_build_instruction<Stage1ZirInstPanic>(ag, scope, source_node);
2447 instruction->msg = msg;2447 instruction->msg = msg;
24482448
2449 ir_ref_instruction(msg, ag->current_basic_block);2449 ir_ref_instruction(msg, ag->current_basic_block);
...@@ -2451,8 +2451,8 @@ static IrInstSrc *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -2451,8 +2451,8 @@ static IrInstSrc *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *so
2451 return &instruction->base;2451 return &instruction->base;
2452}2452}
24532453
2454static IrInstSrc *ir_build_tag_name_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *target) {2454static Stage1ZirInst *ir_build_tag_name_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *target) {
2455 IrInstSrcTagName *instruction = ir_build_instruction<IrInstSrcTagName>(ag, scope, source_node);2455 Stage1ZirInstTagName *instruction = ir_build_instruction<Stage1ZirInstTagName>(ag, scope, source_node);
2456 instruction->target = target;2456 instruction->target = target;
24572457
2458 ir_ref_instruction(target, ag->current_basic_block);2458 ir_ref_instruction(target, ag->current_basic_block);
...@@ -2460,10 +2460,10 @@ static IrInstSrc *ir_build_tag_name_src(Stage1AstGen *ag, Scope *scope, AstNode...@@ -2460,10 +2460,10 @@ static IrInstSrc *ir_build_tag_name_src(Stage1AstGen *ag, Scope *scope, AstNode
2460 return &instruction->base;2460 return &instruction->base;
2461}2461}
24622462
2463static IrInstSrc *ir_build_field_parent_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2463static Stage1ZirInst *ir_build_field_parent_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2464 IrInstSrc *type_value, IrInstSrc *field_name, IrInstSrc *field_ptr)2464 Stage1ZirInst *type_value, Stage1ZirInst *field_name, Stage1ZirInst *field_ptr)
2465{2465{
2466 IrInstSrcFieldParentPtr *inst = ir_build_instruction<IrInstSrcFieldParentPtr>(2466 Stage1ZirInstFieldParentPtr *inst = ir_build_instruction<Stage1ZirInstFieldParentPtr>(
2467 ag, scope, source_node);2467 ag, scope, source_node);
2468 inst->type_value = type_value;2468 inst->type_value = type_value;
2469 inst->field_name = field_name;2469 inst->field_name = field_name;
...@@ -2476,10 +2476,10 @@ static IrInstSrc *ir_build_field_parent_ptr_src(Stage1AstGen *ag, Scope *scope,...@@ -2476,10 +2476,10 @@ static IrInstSrc *ir_build_field_parent_ptr_src(Stage1AstGen *ag, Scope *scope,
2476 return &inst->base;2476 return &inst->base;
2477}2477}
24782478
2479static IrInstSrc *ir_build_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2479static Stage1ZirInst *ir_build_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2480 IrInstSrc *type_value, IrInstSrc *field_name)2480 Stage1ZirInst *type_value, Stage1ZirInst *field_name)
2481{2481{
2482 IrInstSrcOffsetOf *instruction = ir_build_instruction<IrInstSrcOffsetOf>(ag, scope, source_node);2482 Stage1ZirInstOffsetOf *instruction = ir_build_instruction<Stage1ZirInstOffsetOf>(ag, scope, source_node);
2483 instruction->type_value = type_value;2483 instruction->type_value = type_value;
2484 instruction->field_name = field_name;2484 instruction->field_name = field_name;
24852485
...@@ -2489,10 +2489,10 @@ static IrInstSrc *ir_build_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -2489,10 +2489,10 @@ static IrInstSrc *ir_build_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *so
2489 return &instruction->base;2489 return &instruction->base;
2490}2490}
24912491
2492static IrInstSrc *ir_build_bit_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2492static Stage1ZirInst *ir_build_bit_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2493 IrInstSrc *type_value, IrInstSrc *field_name)2493 Stage1ZirInst *type_value, Stage1ZirInst *field_name)
2494{2494{
2495 IrInstSrcBitOffsetOf *instruction = ir_build_instruction<IrInstSrcBitOffsetOf>(ag, scope, source_node);2495 Stage1ZirInstBitOffsetOf *instruction = ir_build_instruction<Stage1ZirInstBitOffsetOf>(ag, scope, source_node);
2496 instruction->type_value = type_value;2496 instruction->type_value = type_value;
2497 instruction->field_name = field_name;2497 instruction->field_name = field_name;
24982498
...@@ -2502,8 +2502,8 @@ static IrInstSrc *ir_build_bit_offset_of(Stage1AstGen *ag, Scope *scope, AstNode...@@ -2502,8 +2502,8 @@ static IrInstSrc *ir_build_bit_offset_of(Stage1AstGen *ag, Scope *scope, AstNode
2502 return &instruction->base;2502 return &instruction->base;
2503}2503}
25042504
2505static IrInstSrc *ir_build_type_info(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_value) {2505static Stage1ZirInst *ir_build_type_info(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_value) {
2506 IrInstSrcTypeInfo *instruction = ir_build_instruction<IrInstSrcTypeInfo>(ag, scope, source_node);2506 Stage1ZirInstTypeInfo *instruction = ir_build_instruction<Stage1ZirInstTypeInfo>(ag, scope, source_node);
2507 instruction->type_value = type_value;2507 instruction->type_value = type_value;
25082508
2509 ir_ref_instruction(type_value, ag->current_basic_block);2509 ir_ref_instruction(type_value, ag->current_basic_block);
...@@ -2511,8 +2511,8 @@ static IrInstSrc *ir_build_type_info(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -2511,8 +2511,8 @@ static IrInstSrc *ir_build_type_info(Stage1AstGen *ag, Scope *scope, AstNode *so
2511 return &instruction->base;2511 return &instruction->base;
2512}2512}
25132513
2514static IrInstSrc *ir_build_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_info) {2514static Stage1ZirInst *ir_build_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_info) {
2515 IrInstSrcType *instruction = ir_build_instruction<IrInstSrcType>(ag, scope, source_node);2515 Stage1ZirInstType *instruction = ir_build_instruction<Stage1ZirInstType>(ag, scope, source_node);
2516 instruction->type_info = type_info;2516 instruction->type_info = type_info;
25172517
2518 ir_ref_instruction(type_info, ag->current_basic_block);2518 ir_ref_instruction(type_info, ag->current_basic_block);
...@@ -2520,10 +2520,10 @@ static IrInstSrc *ir_build_type(Stage1AstGen *ag, Scope *scope, AstNode *source_...@@ -2520,10 +2520,10 @@ static IrInstSrc *ir_build_type(Stage1AstGen *ag, Scope *scope, AstNode *source_
2520 return &instruction->base;2520 return &instruction->base;
2521}2521}
25222522
2523static IrInstSrc *ir_build_set_eval_branch_quota(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2523static Stage1ZirInst *ir_build_set_eval_branch_quota(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2524 IrInstSrc *new_quota)2524 Stage1ZirInst *new_quota)
2525{2525{
2526 IrInstSrcSetEvalBranchQuota *instruction = ir_build_instruction<IrInstSrcSetEvalBranchQuota>(ag, scope, source_node);2526 Stage1ZirInstSetEvalBranchQuota *instruction = ir_build_instruction<Stage1ZirInstSetEvalBranchQuota>(ag, scope, source_node);
2527 instruction->new_quota = new_quota;2527 instruction->new_quota = new_quota;
25282528
2529 ir_ref_instruction(new_quota, ag->current_basic_block);2529 ir_ref_instruction(new_quota, ag->current_basic_block);
...@@ -2531,10 +2531,10 @@ static IrInstSrc *ir_build_set_eval_branch_quota(Stage1AstGen *ag, Scope *scope,...@@ -2531,10 +2531,10 @@ static IrInstSrc *ir_build_set_eval_branch_quota(Stage1AstGen *ag, Scope *scope,
2531 return &instruction->base;2531 return &instruction->base;
2532}2532}
25332533
2534static IrInstSrc *ir_build_align_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2534static Stage1ZirInst *ir_build_align_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2535 IrInstSrc *align_bytes, IrInstSrc *target)2535 Stage1ZirInst *align_bytes, Stage1ZirInst *target)
2536{2536{
2537 IrInstSrcAlignCast *instruction = ir_build_instruction<IrInstSrcAlignCast>(ag, scope, source_node);2537 Stage1ZirInstAlignCast *instruction = ir_build_instruction<Stage1ZirInstAlignCast>(ag, scope, source_node);
2538 instruction->align_bytes = align_bytes;2538 instruction->align_bytes = align_bytes;
2539 instruction->target = target;2539 instruction->target = target;
25402540
...@@ -2544,10 +2544,10 @@ static IrInstSrc *ir_build_align_cast_src(Stage1AstGen *ag, Scope *scope, AstNod...@@ -2544,10 +2544,10 @@ static IrInstSrc *ir_build_align_cast_src(Stage1AstGen *ag, Scope *scope, AstNod
2544 return &instruction->base;2544 return &instruction->base;
2545}2545}
25462546
2547static IrInstSrc *ir_build_resolve_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2547static Stage1ZirInst *ir_build_resolve_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2548 ResultLoc *result_loc, IrInstSrc *ty)2548 ResultLoc *result_loc, Stage1ZirInst *ty)
2549{2549{
2550 IrInstSrcResolveResult *instruction = ir_build_instruction<IrInstSrcResolveResult>(ag, scope, source_node);2550 Stage1ZirInstResolveResult *instruction = ir_build_instruction<Stage1ZirInstResolveResult>(ag, scope, source_node);
2551 instruction->result_loc = result_loc;2551 instruction->result_loc = result_loc;
2552 instruction->ty = ty;2552 instruction->ty = ty;
25532553
...@@ -2556,19 +2556,19 @@ static IrInstSrc *ir_build_resolve_result(Stage1AstGen *ag, Scope *scope, AstNod...@@ -2556,19 +2556,19 @@ static IrInstSrc *ir_build_resolve_result(Stage1AstGen *ag, Scope *scope, AstNod
2556 return &instruction->base;2556 return &instruction->base;
2557}2557}
25582558
2559static IrInstSrc *ir_build_reset_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2559static Stage1ZirInst *ir_build_reset_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2560 ResultLoc *result_loc)2560 ResultLoc *result_loc)
2561{2561{
2562 IrInstSrcResetResult *instruction = ir_build_instruction<IrInstSrcResetResult>(ag, scope, source_node);2562 Stage1ZirInstResetResult *instruction = ir_build_instruction<Stage1ZirInstResetResult>(ag, scope, source_node);
2563 instruction->result_loc = result_loc;2563 instruction->result_loc = result_loc;
25642564
2565 return &instruction->base;2565 return &instruction->base;
2566}2566}
25672567
2568static IrInstSrc *ir_build_set_align_stack(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2568static Stage1ZirInst *ir_build_set_align_stack(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2569 IrInstSrc *align_bytes)2569 Stage1ZirInst *align_bytes)
2570{2570{
2571 IrInstSrcSetAlignStack *instruction = ir_build_instruction<IrInstSrcSetAlignStack>(ag, scope, source_node);2571 Stage1ZirInstSetAlignStack *instruction = ir_build_instruction<Stage1ZirInstSetAlignStack>(ag, scope, source_node);
2572 instruction->align_bytes = align_bytes;2572 instruction->align_bytes = align_bytes;
25732573
2574 ir_ref_instruction(align_bytes, ag->current_basic_block);2574 ir_ref_instruction(align_bytes, ag->current_basic_block);
...@@ -2576,12 +2576,12 @@ static IrInstSrc *ir_build_set_align_stack(Stage1AstGen *ag, Scope *scope, AstNo...@@ -2576,12 +2576,12 @@ static IrInstSrc *ir_build_set_align_stack(Stage1AstGen *ag, Scope *scope, AstNo
2576 return &instruction->base;2576 return &instruction->base;
2577}2577}
25782578
2579static IrInstSrc *ir_build_arg_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2579static Stage1ZirInst *ir_build_arg_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2580 IrInstSrc *fn_type, IrInstSrc *arg_index, bool allow_var)2580 Stage1ZirInst *fn_type, Stage1ZirInst *arg_index, bool allow_var)
2581{2581{
2582 IrInstSrcArgType *instruction = heap::c_allocator.create<IrInstSrcArgType>();2582 Stage1ZirInstArgType *instruction = heap::c_allocator.create<Stage1ZirInstArgType>();
2583 instruction->base.id = allow_var ?2583 instruction->base.id = allow_var ?
2584 IrInstSrcIdArgTypeAllowVarTrue : IrInstSrcIdArgTypeAllowVarFalse;2584 Stage1ZirInstIdArgTypeAllowVarTrue : Stage1ZirInstIdArgTypeAllowVarFalse;
2585 instruction->base.scope = scope;2585 instruction->base.scope = scope;
2586 instruction->base.source_node = source_node;2586 instruction->base.source_node = source_node;
2587 instruction->base.debug_id = irb_next_debug_id(ag);2587 instruction->base.debug_id = irb_next_debug_id(ag);
...@@ -2597,19 +2597,19 @@ static IrInstSrc *ir_build_arg_type(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -2597,19 +2597,19 @@ static IrInstSrc *ir_build_arg_type(Stage1AstGen *ag, Scope *scope, AstNode *sou
2597 return &instruction->base;2597 return &instruction->base;
2598}2598}
25992599
2600static IrInstSrc *ir_build_error_return_trace_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2600static Stage1ZirInst *ir_build_error_return_trace_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2601 IrInstErrorReturnTraceOptional optional)2601 IrInstErrorReturnTraceOptional optional)
2602{2602{
2603 IrInstSrcErrorReturnTrace *inst = ir_build_instruction<IrInstSrcErrorReturnTrace>(ag, scope, source_node);2603 Stage1ZirInstErrorReturnTrace *inst = ir_build_instruction<Stage1ZirInstErrorReturnTrace>(ag, scope, source_node);
2604 inst->optional = optional;2604 inst->optional = optional;
26052605
2606 return &inst->base;2606 return &inst->base;
2607}2607}
26082608
2609static IrInstSrc *ir_build_error_union(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2609static Stage1ZirInst *ir_build_error_union(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2610 IrInstSrc *err_set, IrInstSrc *payload)2610 Stage1ZirInst *err_set, Stage1ZirInst *payload)
2611{2611{
2612 IrInstSrcErrorUnion *instruction = ir_build_instruction<IrInstSrcErrorUnion>(ag, scope, source_node);2612 Stage1ZirInstErrorUnion *instruction = ir_build_instruction<Stage1ZirInstErrorUnion>(ag, scope, source_node);
2613 instruction->err_set = err_set;2613 instruction->err_set = err_set;
2614 instruction->payload = payload;2614 instruction->payload = payload;
26152615
...@@ -2619,11 +2619,11 @@ static IrInstSrc *ir_build_error_union(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -2619,11 +2619,11 @@ static IrInstSrc *ir_build_error_union(Stage1AstGen *ag, Scope *scope, AstNode *
2619 return &instruction->base;2619 return &instruction->base;
2620}2620}
26212621
2622static IrInstSrc *ir_build_atomic_rmw_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2622static Stage1ZirInst *ir_build_atomic_rmw_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2623 IrInstSrc *operand_type, IrInstSrc *ptr, IrInstSrc *op, IrInstSrc *operand,2623 Stage1ZirInst *operand_type, Stage1ZirInst *ptr, Stage1ZirInst *op, Stage1ZirInst *operand,
2624 IrInstSrc *ordering)2624 Stage1ZirInst *ordering)
2625{2625{
2626 IrInstSrcAtomicRmw *instruction = ir_build_instruction<IrInstSrcAtomicRmw>(ag, scope, source_node);2626 Stage1ZirInstAtomicRmw *instruction = ir_build_instruction<Stage1ZirInstAtomicRmw>(ag, scope, source_node);
2627 instruction->operand_type = operand_type;2627 instruction->operand_type = operand_type;
2628 instruction->ptr = ptr;2628 instruction->ptr = ptr;
2629 instruction->op = op;2629 instruction->op = op;
...@@ -2639,10 +2639,10 @@ static IrInstSrc *ir_build_atomic_rmw_src(Stage1AstGen *ag, Scope *scope, AstNod...@@ -2639,10 +2639,10 @@ static IrInstSrc *ir_build_atomic_rmw_src(Stage1AstGen *ag, Scope *scope, AstNod
2639 return &instruction->base;2639 return &instruction->base;
2640}2640}
26412641
2642static IrInstSrc *ir_build_atomic_load_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2642static Stage1ZirInst *ir_build_atomic_load_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2643 IrInstSrc *operand_type, IrInstSrc *ptr, IrInstSrc *ordering)2643 Stage1ZirInst *operand_type, Stage1ZirInst *ptr, Stage1ZirInst *ordering)
2644{2644{
2645 IrInstSrcAtomicLoad *instruction = ir_build_instruction<IrInstSrcAtomicLoad>(ag, scope, source_node);2645 Stage1ZirInstAtomicLoad *instruction = ir_build_instruction<Stage1ZirInstAtomicLoad>(ag, scope, source_node);
2646 instruction->operand_type = operand_type;2646 instruction->operand_type = operand_type;
2647 instruction->ptr = ptr;2647 instruction->ptr = ptr;
2648 instruction->ordering = ordering;2648 instruction->ordering = ordering;
...@@ -2654,10 +2654,10 @@ static IrInstSrc *ir_build_atomic_load_src(Stage1AstGen *ag, Scope *scope, AstNo...@@ -2654,10 +2654,10 @@ static IrInstSrc *ir_build_atomic_load_src(Stage1AstGen *ag, Scope *scope, AstNo
2654 return &instruction->base;2654 return &instruction->base;
2655}2655}
26562656
2657static IrInstSrc *ir_build_atomic_store_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2657static Stage1ZirInst *ir_build_atomic_store_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2658 IrInstSrc *operand_type, IrInstSrc *ptr, IrInstSrc *value, IrInstSrc *ordering)2658 Stage1ZirInst *operand_type, Stage1ZirInst *ptr, Stage1ZirInst *value, Stage1ZirInst *ordering)
2659{2659{
2660 IrInstSrcAtomicStore *instruction = ir_build_instruction<IrInstSrcAtomicStore>(ag, scope, source_node);2660 Stage1ZirInstAtomicStore *instruction = ir_build_instruction<Stage1ZirInstAtomicStore>(ag, scope, source_node);
2661 instruction->operand_type = operand_type;2661 instruction->operand_type = operand_type;
2662 instruction->ptr = ptr;2662 instruction->ptr = ptr;
2663 instruction->value = value;2663 instruction->value = value;
...@@ -2671,15 +2671,15 @@ static IrInstSrc *ir_build_atomic_store_src(Stage1AstGen *ag, Scope *scope, AstN...@@ -2671,15 +2671,15 @@ static IrInstSrc *ir_build_atomic_store_src(Stage1AstGen *ag, Scope *scope, AstN
2671 return &instruction->base;2671 return &instruction->base;
2672}2672}
26732673
2674static IrInstSrc *ir_build_save_err_ret_addr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {2674static Stage1ZirInst *ir_build_save_err_ret_addr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2675 IrInstSrcSaveErrRetAddr *inst = ir_build_instruction<IrInstSrcSaveErrRetAddr>(ag, scope, source_node);2675 Stage1ZirInstSaveErrRetAddr *inst = ir_build_instruction<Stage1ZirInstSaveErrRetAddr>(ag, scope, source_node);
2676 return &inst->base;2676 return &inst->base;
2677}2677}
26782678
2679static IrInstSrc *ir_build_add_implicit_return_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2679static Stage1ZirInst *ir_build_add_implicit_return_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2680 IrInstSrc *value, ResultLocReturn *result_loc_ret)2680 Stage1ZirInst *value, ResultLocReturn *result_loc_ret)
2681{2681{
2682 IrInstSrcAddImplicitReturnType *inst = ir_build_instruction<IrInstSrcAddImplicitReturnType>(ag, scope, source_node);2682 Stage1ZirInstAddImplicitReturnType *inst = ir_build_instruction<Stage1ZirInstAddImplicitReturnType>(ag, scope, source_node);
2683 inst->value = value;2683 inst->value = value;
2684 inst->result_loc_ret = result_loc_ret;2684 inst->result_loc_ret = result_loc_ret;
26852685
...@@ -2688,10 +2688,10 @@ static IrInstSrc *ir_build_add_implicit_return_type(Stage1AstGen *ag, Scope *sco...@@ -2688,10 +2688,10 @@ static IrInstSrc *ir_build_add_implicit_return_type(Stage1AstGen *ag, Scope *sco
2688 return &inst->base;2688 return &inst->base;
2689}2689}
26902690
2691static IrInstSrc *ir_build_has_decl(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2691static Stage1ZirInst *ir_build_has_decl(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2692 IrInstSrc *container, IrInstSrc *name)2692 Stage1ZirInst *container, Stage1ZirInst *name)
2693{2693{
2694 IrInstSrcHasDecl *instruction = ir_build_instruction<IrInstSrcHasDecl>(ag, scope, source_node);2694 Stage1ZirInstHasDecl *instruction = ir_build_instruction<Stage1ZirInstHasDecl>(ag, scope, source_node);
2695 instruction->container = container;2695 instruction->container = container;
2696 instruction->name = name;2696 instruction->name = name;
26972697
...@@ -2701,15 +2701,15 @@ static IrInstSrc *ir_build_has_decl(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -2701,15 +2701,15 @@ static IrInstSrc *ir_build_has_decl(Stage1AstGen *ag, Scope *scope, AstNode *sou
2701 return &instruction->base;2701 return &instruction->base;
2702}2702}
27032703
2704static IrInstSrc *ir_build_undeclared_identifier(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) {2704static Stage1ZirInst *ir_build_undeclared_identifier(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) {
2705 IrInstSrcUndeclaredIdent *instruction = ir_build_instruction<IrInstSrcUndeclaredIdent>(ag, scope, source_node);2705 Stage1ZirInstUndeclaredIdent *instruction = ir_build_instruction<Stage1ZirInstUndeclaredIdent>(ag, scope, source_node);
2706 instruction->name = name;2706 instruction->name = name;
27072707
2708 return &instruction->base;2708 return &instruction->base;
2709}2709}
27102710
2711static IrInstSrc *ir_build_check_runtime_scope(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *scope_is_comptime, IrInstSrc *is_comptime) {2711static Stage1ZirInst *ir_build_check_runtime_scope(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *scope_is_comptime, Stage1ZirInst *is_comptime) {
2712 IrInstSrcCheckRuntimeScope *instruction = ir_build_instruction<IrInstSrcCheckRuntimeScope>(ag, scope, source_node);2712 Stage1ZirInstCheckRuntimeScope *instruction = ir_build_instruction<Stage1ZirInstCheckRuntimeScope>(ag, scope, source_node);
2713 instruction->scope_is_comptime = scope_is_comptime;2713 instruction->scope_is_comptime = scope_is_comptime;
2714 instruction->is_comptime = is_comptime;2714 instruction->is_comptime = is_comptime;
27152715
...@@ -2719,10 +2719,10 @@ static IrInstSrc *ir_build_check_runtime_scope(Stage1AstGen *ag, Scope *scope, A...@@ -2719,10 +2719,10 @@ static IrInstSrc *ir_build_check_runtime_scope(Stage1AstGen *ag, Scope *scope, A
2719 return &instruction->base;2719 return &instruction->base;
2720}2720}
27212721
2722static IrInstSrc *ir_build_union_init_named_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2722static Stage1ZirInst *ir_build_union_init_named_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2723 IrInstSrc *union_type, IrInstSrc *field_name, IrInstSrc *field_result_loc, IrInstSrc *result_loc)2723 Stage1ZirInst *union_type, Stage1ZirInst *field_name, Stage1ZirInst *field_result_loc, Stage1ZirInst *result_loc)
2724{2724{
2725 IrInstSrcUnionInitNamedField *instruction = ir_build_instruction<IrInstSrcUnionInitNamedField>(ag, scope, source_node);2725 Stage1ZirInstUnionInitNamedField *instruction = ir_build_instruction<Stage1ZirInstUnionInitNamedField>(ag, scope, source_node);
2726 instruction->union_type = union_type;2726 instruction->union_type = union_type;
2727 instruction->field_name = field_name;2727 instruction->field_name = field_name;
2728 instruction->field_result_loc = field_result_loc;2728 instruction->field_result_loc = field_result_loc;
...@@ -2736,10 +2736,10 @@ static IrInstSrc *ir_build_union_init_named_field(Stage1AstGen *ag, Scope *scope...@@ -2736,10 +2736,10 @@ static IrInstSrc *ir_build_union_init_named_field(Stage1AstGen *ag, Scope *scope
2736 return &instruction->base;2736 return &instruction->base;
2737}2737}
27382738
2739static IrInstSrc *ir_build_alloca_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2739static Stage1ZirInst *ir_build_alloca_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2740 IrInstSrc *align, const char *name_hint, IrInstSrc *is_comptime)2740 Stage1ZirInst *align, const char *name_hint, Stage1ZirInst *is_comptime)
2741{2741{
2742 IrInstSrcAlloca *instruction = ir_build_instruction<IrInstSrcAlloca>(ag, scope, source_node);2742 Stage1ZirInstAlloca *instruction = ir_build_instruction<Stage1ZirInstAlloca>(ag, scope, source_node);
2743 instruction->align = align;2743 instruction->align = align;
2744 instruction->name_hint = name_hint;2744 instruction->name_hint = name_hint;
2745 instruction->is_comptime = is_comptime;2745 instruction->is_comptime = is_comptime;
...@@ -2750,10 +2750,10 @@ static IrInstSrc *ir_build_alloca_src(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -2750,10 +2750,10 @@ static IrInstSrc *ir_build_alloca_src(Stage1AstGen *ag, Scope *scope, AstNode *s
2750 return &instruction->base;2750 return &instruction->base;
2751}2751}
27522752
2753static IrInstSrc *ir_build_end_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2753static Stage1ZirInst *ir_build_end_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2754 IrInstSrc *value, ResultLoc *result_loc)2754 Stage1ZirInst *value, ResultLoc *result_loc)
2755{2755{
2756 IrInstSrcEndExpr *instruction = ir_build_instruction<IrInstSrcEndExpr>(ag, scope, source_node);2756 Stage1ZirInstEndExpr *instruction = ir_build_instruction<Stage1ZirInstEndExpr>(ag, scope, source_node);
2757 instruction->value = value;2757 instruction->value = value;
2758 instruction->result_loc = result_loc;2758 instruction->result_loc = result_loc;
27592759
...@@ -2762,14 +2762,14 @@ static IrInstSrc *ir_build_end_expr(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -2762,14 +2762,14 @@ static IrInstSrc *ir_build_end_expr(Stage1AstGen *ag, Scope *scope, AstNode *sou
2762 return &instruction->base;2762 return &instruction->base;
2763}2763}
27642764
2765static IrInstSrcSuspendBegin *ir_build_suspend_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {2765static Stage1ZirInstSuspendBegin *ir_build_suspend_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2766 return ir_build_instruction<IrInstSrcSuspendBegin>(ag, scope, source_node);2766 return ir_build_instruction<Stage1ZirInstSuspendBegin>(ag, scope, source_node);
2767}2767}
27682768
2769static IrInstSrc *ir_build_suspend_finish_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2769static Stage1ZirInst *ir_build_suspend_finish_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2770 IrInstSrcSuspendBegin *begin)2770 Stage1ZirInstSuspendBegin *begin)
2771{2771{
2772 IrInstSrcSuspendFinish *inst = ir_build_instruction<IrInstSrcSuspendFinish>(ag, scope, source_node);2772 Stage1ZirInstSuspendFinish *inst = ir_build_instruction<Stage1ZirInstSuspendFinish>(ag, scope, source_node);
2773 inst->begin = begin;2773 inst->begin = begin;
27742774
2775 ir_ref_instruction(&begin->base, ag->current_basic_block);2775 ir_ref_instruction(&begin->base, ag->current_basic_block);
...@@ -2777,10 +2777,10 @@ static IrInstSrc *ir_build_suspend_finish_src(Stage1AstGen *ag, Scope *scope, As...@@ -2777,10 +2777,10 @@ static IrInstSrc *ir_build_suspend_finish_src(Stage1AstGen *ag, Scope *scope, As
2777 return &inst->base;2777 return &inst->base;
2778}2778}
27792779
2780static IrInstSrc *ir_build_await_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2780static Stage1ZirInst *ir_build_await_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2781 IrInstSrc *frame, ResultLoc *result_loc, bool is_nosuspend)2781 Stage1ZirInst *frame, ResultLoc *result_loc, bool is_nosuspend)
2782{2782{
2783 IrInstSrcAwait *instruction = ir_build_instruction<IrInstSrcAwait>(ag, scope, source_node);2783 Stage1ZirInstAwait *instruction = ir_build_instruction<Stage1ZirInstAwait>(ag, scope, source_node);
2784 instruction->frame = frame;2784 instruction->frame = frame;
2785 instruction->result_loc = result_loc;2785 instruction->result_loc = result_loc;
2786 instruction->is_nosuspend = is_nosuspend;2786 instruction->is_nosuspend = is_nosuspend;
...@@ -2790,8 +2790,8 @@ static IrInstSrc *ir_build_await_src(Stage1AstGen *ag, Scope *scope, AstNode *so...@@ -2790,8 +2790,8 @@ static IrInstSrc *ir_build_await_src(Stage1AstGen *ag, Scope *scope, AstNode *so
2790 return &instruction->base;2790 return &instruction->base;
2791}2791}
27922792
2793static IrInstSrc *ir_build_resume_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *frame) {2793static Stage1ZirInst *ir_build_resume_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *frame) {
2794 IrInstSrcResume *instruction = ir_build_instruction<IrInstSrcResume>(ag, scope, source_node);2794 Stage1ZirInstResume *instruction = ir_build_instruction<Stage1ZirInstResume>(ag, scope, source_node);
2795 instruction->frame = frame;2795 instruction->frame = frame;
27962796
2797 ir_ref_instruction(frame, ag->current_basic_block);2797 ir_ref_instruction(frame, ag->current_basic_block);
...@@ -2799,10 +2799,10 @@ static IrInstSrc *ir_build_resume_src(Stage1AstGen *ag, Scope *scope, AstNode *s...@@ -2799,10 +2799,10 @@ static IrInstSrc *ir_build_resume_src(Stage1AstGen *ag, Scope *scope, AstNode *s
2799 return &instruction->base;2799 return &instruction->base;
2800}2800}
28012801
2802static IrInstSrcSpillBegin *ir_build_spill_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2802static Stage1ZirInstSpillBegin *ir_build_spill_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2803 IrInstSrc *operand, SpillId spill_id)2803 Stage1ZirInst *operand, SpillId spill_id)
2804{2804{
2805 IrInstSrcSpillBegin *instruction = ir_build_instruction<IrInstSrcSpillBegin>(ag, scope, source_node);2805 Stage1ZirInstSpillBegin *instruction = ir_build_instruction<Stage1ZirInstSpillBegin>(ag, scope, source_node);
2806 instruction->operand = operand;2806 instruction->operand = operand;
2807 instruction->spill_id = spill_id;2807 instruction->spill_id = spill_id;
28082808
...@@ -2811,10 +2811,10 @@ static IrInstSrcSpillBegin *ir_build_spill_begin_src(Stage1AstGen *ag, Scope *sc...@@ -2811,10 +2811,10 @@ static IrInstSrcSpillBegin *ir_build_spill_begin_src(Stage1AstGen *ag, Scope *sc
2811 return instruction;2811 return instruction;
2812}2812}
28132813
2814static IrInstSrc *ir_build_spill_end_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,2814static Stage1ZirInst *ir_build_spill_end_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2815 IrInstSrcSpillBegin *begin)2815 Stage1ZirInstSpillBegin *begin)
2816{2816{
2817 IrInstSrcSpillEnd *instruction = ir_build_instruction<IrInstSrcSpillEnd>(ag, scope, source_node);2817 Stage1ZirInstSpillEnd *instruction = ir_build_instruction<Stage1ZirInstSpillEnd>(ag, scope, source_node);
2818 instruction->begin = begin;2818 instruction->begin = begin;
28192819
2820 ir_ref_instruction(&begin->base, ag->current_basic_block);2820 ir_ref_instruction(&begin->base, ag->current_basic_block);
...@@ -2822,8 +2822,8 @@ static IrInstSrc *ir_build_spill_end_src(Stage1AstGen *ag, Scope *scope, AstNode...@@ -2822,8 +2822,8 @@ static IrInstSrc *ir_build_spill_end_src(Stage1AstGen *ag, Scope *scope, AstNode
2822 return &instruction->base;2822 return &instruction->base;
2823}2823}
28242824
2825static IrInstSrc *ir_build_wasm_memory_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *index) {2825static Stage1ZirInst *ir_build_wasm_memory_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *index) {
2826 IrInstSrcWasmMemorySize *instruction = ir_build_instruction<IrInstSrcWasmMemorySize>(ag, scope, source_node);2826 Stage1ZirInstWasmMemorySize *instruction = ir_build_instruction<Stage1ZirInstWasmMemorySize>(ag, scope, source_node);
2827 instruction->index = index;2827 instruction->index = index;
28282828
2829 ir_ref_instruction(index, ag->current_basic_block);2829 ir_ref_instruction(index, ag->current_basic_block);
...@@ -2831,8 +2831,8 @@ static IrInstSrc *ir_build_wasm_memory_size_src(Stage1AstGen *ag, Scope *scope,...@@ -2831,8 +2831,8 @@ static IrInstSrc *ir_build_wasm_memory_size_src(Stage1AstGen *ag, Scope *scope,
2831 return &instruction->base;2831 return &instruction->base;
2832}2832}
28332833
2834static IrInstSrc *ir_build_wasm_memory_grow_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *index, IrInstSrc *delta) {2834static Stage1ZirInst *ir_build_wasm_memory_grow_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *index, Stage1ZirInst *delta) {
2835 IrInstSrcWasmMemoryGrow *instruction = ir_build_instruction<IrInstSrcWasmMemoryGrow>(ag, scope, source_node);2835 Stage1ZirInstWasmMemoryGrow *instruction = ir_build_instruction<Stage1ZirInstWasmMemoryGrow>(ag, scope, source_node);
2836 instruction->index = index;2836 instruction->index = index;
2837 instruction->delta = delta;2837 instruction->delta = delta;
28382838
...@@ -2842,8 +2842,8 @@ static IrInstSrc *ir_build_wasm_memory_grow_src(Stage1AstGen *ag, Scope *scope,...@@ -2842,8 +2842,8 @@ static IrInstSrc *ir_build_wasm_memory_grow_src(Stage1AstGen *ag, Scope *scope,
2842 return &instruction->base;2842 return &instruction->base;
2843}2843}
28442844
2845static IrInstSrc *ir_build_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {2845static Stage1ZirInst *ir_build_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2846 IrInstSrcSrc *instruction = ir_build_instruction<IrInstSrcSrc>(ag, scope, source_node);2846 Stage1ZirInstSrc *instruction = ir_build_instruction<Stage1ZirInstSrc>(ag, scope, source_node);
28472847
2848 return &instruction->base;2848 return &instruction->base;
2849}2849}
...@@ -2886,7 +2886,7 @@ static void ir_count_defers(Stage1AstGen *ag, Scope *inner_scope, Scope *outer_s...@@ -2886,7 +2886,7 @@ static void ir_count_defers(Stage1AstGen *ag, Scope *inner_scope, Scope *outer_s
2886 }2886 }
2887}2887}
28882888
2889static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope *outer_scope, bool *is_noreturn, IrInstSrc *err_value) {2889static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope *outer_scope, bool *is_noreturn, Stage1ZirInst *err_value) {
2890 Scope *scope = inner_scope;2890 Scope *scope = inner_scope;
2891 if (is_noreturn != nullptr) *is_noreturn = false;2891 if (is_noreturn != nullptr) *is_noreturn = false;
2892 while (scope != outer_scope) {2892 while (scope != outer_scope) {
...@@ -2920,7 +2920,7 @@ static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope...@@ -2920,7 +2920,7 @@ static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope
2920 return false;2920 return false;
2921 }2921 }
29222922
2923 IrInstSrc *is_comptime;2923 Stage1ZirInst *is_comptime;
2924 if (ir_should_inline(ag->exec, defer_expr_scope)) {2924 if (ir_should_inline(ag->exec, defer_expr_scope)) {
2925 is_comptime = ir_build_const_bool(ag, defer_expr_scope,2925 is_comptime = ir_build_const_bool(ag, defer_expr_scope,
2926 defer_expr_node, true);2926 defer_expr_node, true);
...@@ -2937,7 +2937,7 @@ static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope...@@ -2937,7 +2937,7 @@ static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope
2937 defer_expr_scope = err_var->child_scope;2937 defer_expr_scope = err_var->child_scope;
2938 }2938 }
29392939
2940 IrInstSrc *defer_expr_value = astgen_node(ag, defer_expr_node, defer_expr_scope);2940 Stage1ZirInst *defer_expr_value = astgen_node(ag, defer_expr_node, defer_expr_scope);
2941 if (defer_expr_value == ag->codegen->invalid_inst_src)2941 if (defer_expr_value == ag->codegen->invalid_inst_src)
2942 return ag->codegen->invalid_inst_src;2942 return ag->codegen->invalid_inst_src;
29432943
...@@ -3007,7 +3007,7 @@ static ScopeDeferExpr *get_scope_defer_expr(Scope *scope) {...@@ -3007,7 +3007,7 @@ static ScopeDeferExpr *get_scope_defer_expr(Scope *scope) {
3007 return nullptr;3007 return nullptr;
3008}3008}
30093009
3010static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {3010static Stage1ZirInst *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {
3011 assert(node->type == NodeTypeReturnExpr);3011 assert(node->type == NodeTypeReturnExpr);
30123012
3013 ScopeDeferExpr *scope_defer_expr = get_scope_defer_expr(scope);3013 ScopeDeferExpr *scope_defer_expr = get_scope_defer_expr(scope);
...@@ -3029,7 +3029,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L...@@ -3029,7 +3029,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
3029 result_loc_ret->base.id = ResultLocIdReturn;3029 result_loc_ret->base.id = ResultLocIdReturn;
3030 ir_build_reset_result(ag, scope, node, &result_loc_ret->base);3030 ir_build_reset_result(ag, scope, node, &result_loc_ret->base);
30313031
3032 IrInstSrc *return_value;3032 Stage1ZirInst *return_value;
3033 if (expr_node) {3033 if (expr_node) {
3034 // Temporarily set this so that if we return a type it gets the name of the function3034 // Temporarily set this so that if we return a type it gets the name of the function
3035 ZigFn *prev_name_fn = ag->exec->name_fn;3035 ZigFn *prev_name_fn = ag->exec->name_fn;
...@@ -3052,7 +3052,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L...@@ -3052,7 +3052,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
3052 // only generate unconditional defers3052 // only generate unconditional defers
3053 if (!astgen_defers_for_block(ag, scope, outer_scope, nullptr, nullptr))3053 if (!astgen_defers_for_block(ag, scope, outer_scope, nullptr, nullptr))
3054 return ag->codegen->invalid_inst_src;3054 return ag->codegen->invalid_inst_src;
3055 IrInstSrc *result = ir_build_return_src(ag, scope, node, nullptr);3055 Stage1ZirInst *result = ir_build_return_src(ag, scope, node, nullptr);
3056 result_loc_ret->base.source_instruction = result;3056 result_loc_ret->base.source_instruction = result;
3057 return result;3057 return result;
3058 }3058 }
...@@ -3061,9 +3061,9 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L...@@ -3061,9 +3061,9 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
3061 Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, scope, "ErrRetErr");3061 Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, scope, "ErrRetErr");
3062 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "ErrRetOk");3062 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "ErrRetOk");
30633063
3064 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, return_value, false, true);3064 Stage1ZirInst *is_err = ir_build_test_err_src(ag, scope, node, return_value, false, true);
30653065
3066 IrInstSrc *is_comptime;3066 Stage1ZirInst *is_comptime;
3067 if (should_inline) {3067 if (should_inline) {
3068 is_comptime = ir_build_const_bool(ag, scope, node, should_inline);3068 is_comptime = ir_build_const_bool(ag, scope, node, should_inline);
3069 } else {3069 } else {
...@@ -3087,21 +3087,21 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L...@@ -3087,21 +3087,21 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
3087 ir_build_br(ag, scope, node, ret_stmt_block, is_comptime);3087 ir_build_br(ag, scope, node, ret_stmt_block, is_comptime);
30883088
3089 ir_set_cursor_at_end_and_append_block(ag, ret_stmt_block);3089 ir_set_cursor_at_end_and_append_block(ag, ret_stmt_block);
3090 IrInstSrc *result = ir_build_return_src(ag, scope, node, nullptr);3090 Stage1ZirInst *result = ir_build_return_src(ag, scope, node, nullptr);
3091 result_loc_ret->base.source_instruction = result;3091 result_loc_ret->base.source_instruction = result;
3092 return result;3092 return result;
3093 }3093 }
3094 case ReturnKindError:3094 case ReturnKindError:
3095 {3095 {
3096 assert(expr_node);3096 assert(expr_node);
3097 IrInstSrc *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);3097 Stage1ZirInst *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
3098 if (err_union_ptr == ag->codegen->invalid_inst_src)3098 if (err_union_ptr == ag->codegen->invalid_inst_src)
3099 return ag->codegen->invalid_inst_src;3099 return ag->codegen->invalid_inst_src;
3100 IrInstSrc *is_err_val = ir_build_test_err_src(ag, scope, node, err_union_ptr, true, false);3100 Stage1ZirInst *is_err_val = ir_build_test_err_src(ag, scope, node, err_union_ptr, true, false);
31013101
3102 Stage1ZirBasicBlock *return_block = ir_create_basic_block(ag, scope, "ErrRetReturn");3102 Stage1ZirBasicBlock *return_block = ir_create_basic_block(ag, scope, "ErrRetReturn");
3103 Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, scope, "ErrRetContinue");3103 Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, scope, "ErrRetContinue");
3104 IrInstSrc *is_comptime;3104 Stage1ZirInst *is_comptime;
3105 bool should_inline = ir_should_inline(ag->exec, scope);3105 bool should_inline = ir_should_inline(ag->exec, scope);
3106 if (should_inline) {3106 if (should_inline) {
3107 is_comptime = ir_build_const_bool(ag, scope, node, true);3107 is_comptime = ir_build_const_bool(ag, scope, node, true);
...@@ -3111,10 +3111,10 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L...@@ -3111,10 +3111,10 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
3111 ir_build_cond_br(ag, scope, node, is_err_val, return_block, continue_block, is_comptime);3111 ir_build_cond_br(ag, scope, node, is_err_val, return_block, continue_block, is_comptime);
31123112
3113 ir_set_cursor_at_end_and_append_block(ag, return_block);3113 ir_set_cursor_at_end_and_append_block(ag, return_block);
3114 IrInstSrc *err_val_ptr = ir_build_unwrap_err_code_src(ag, scope, node, err_union_ptr);3114 Stage1ZirInst *err_val_ptr = ir_build_unwrap_err_code_src(ag, scope, node, err_union_ptr);
3115 IrInstSrc *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr);3115 Stage1ZirInst *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr);
3116 ir_build_add_implicit_return_type(ag, scope, node, err_val, nullptr);3116 ir_build_add_implicit_return_type(ag, scope, node, err_val, nullptr);
3117 IrInstSrcSpillBegin *spill_begin = ir_build_spill_begin_src(ag, scope, node, err_val,3117 Stage1ZirInstSpillBegin *spill_begin = ir_build_spill_begin_src(ag, scope, node, err_val,
3118 SpillIdRetErrCode);3118 SpillIdRetErrCode);
3119 ResultLocReturn *result_loc_ret = heap::c_allocator.create<ResultLocReturn>();3119 ResultLocReturn *result_loc_ret = heap::c_allocator.create<ResultLocReturn>();
3120 result_loc_ret->base.id = ResultLocIdReturn;3120 result_loc_ret->base.id = ResultLocIdReturn;
...@@ -3130,12 +3130,12 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L...@@ -3130,12 +3130,12 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
3130 ir_build_save_err_ret_addr_src(ag, scope, node);3130 ir_build_save_err_ret_addr_src(ag, scope, node);
3131 }3131 }
3132 err_val = ir_build_spill_end_src(ag, scope, node, spill_begin);3132 err_val = ir_build_spill_end_src(ag, scope, node, spill_begin);
3133 IrInstSrc *ret_inst = ir_build_return_src(ag, scope, node, err_val);3133 Stage1ZirInst *ret_inst = ir_build_return_src(ag, scope, node, err_val);
3134 result_loc_ret->base.source_instruction = ret_inst;3134 result_loc_ret->base.source_instruction = ret_inst;
3135 }3135 }
31363136
3137 ir_set_cursor_at_end_and_append_block(ag, continue_block);3137 ir_set_cursor_at_end_and_append_block(ag, continue_block);
3138 IrInstSrc *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, scope, node, err_union_ptr, false, false);3138 Stage1ZirInst *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, scope, node, err_union_ptr, false, false);
3139 if (lval == LValPtr)3139 if (lval == LValPtr)
3140 return unwrapped_ptr;3140 return unwrapped_ptr;
3141 else3141 else
...@@ -3146,7 +3146,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L...@@ -3146,7 +3146,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
3146}3146}
31473147
3148ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope,3148ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope,
3149 Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime,3149 Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime,
3150 bool skip_name_check)3150 bool skip_name_check)
3151{3151{
3152 ZigVar *variable_entry = heap::c_allocator.create<ZigVar>();3152 ZigVar *variable_entry = heap::c_allocator.create<ZigVar>();
...@@ -3218,7 +3218,7 @@ ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope,...@@ -3218,7 +3218,7 @@ ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope,
3218// Set name to nullptr to make the variable anonymous (not visible to programmer).3218// Set name to nullptr to make the variable anonymous (not visible to programmer).
3219// After you call this function var->child_scope has the variable in scope3219// After you call this function var->child_scope has the variable in scope
3220static ZigVar *ir_create_var(Stage1AstGen *ag, AstNode *node, Scope *scope, Buf *name,3220static ZigVar *ir_create_var(Stage1AstGen *ag, AstNode *node, Scope *scope, Buf *name,
3221 bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime)3221 bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime)
3222{3222{
3223 bool is_underscored = name ? buf_eql_str(name, "_") : false;3223 bool is_underscored = name ? buf_eql_str(name, "_") : false;
3224 ZigVar *var = create_local_var(ag->codegen, node, scope,3224 ZigVar *var = create_local_var(ag->codegen, node, scope,
...@@ -3256,12 +3256,12 @@ static bool is_duplicate_label(CodeGen *g, Scope *scope, AstNode *node, Buf *nam...@@ -3256,12 +3256,12 @@ static bool is_duplicate_label(CodeGen *g, Scope *scope, AstNode *node, Buf *nam
3256 return false;3256 return false;
3257}3257}
32583258
3259static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *block_node, LVal lval,3259static Stage1ZirInst *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *block_node, LVal lval,
3260 ResultLoc *result_loc)3260 ResultLoc *result_loc)
3261{3261{
3262 assert(block_node->type == NodeTypeBlock);3262 assert(block_node->type == NodeTypeBlock);
32633263
3264 ZigList<IrInstSrc *> incoming_values = {0};3264 ZigList<Stage1ZirInst *> incoming_values = {0};
3265 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};3265 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
32663266
3267 if (is_duplicate_label(ag->codegen, parent_scope, block_node, block_node->data.block.name))3267 if (is_duplicate_label(ag->codegen, parent_scope, block_node, block_node->data.block.name))
...@@ -3305,11 +3305,11 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b...@@ -3305,11 +3305,11 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
33053305
3306 bool is_continuation_unreachable = false;3306 bool is_continuation_unreachable = false;
3307 bool found_invalid_inst = false;3307 bool found_invalid_inst = false;
3308 IrInstSrc *noreturn_return_value = nullptr;3308 Stage1ZirInst *noreturn_return_value = nullptr;
3309 for (size_t i = 0; i < block_node->data.block.statements.length; i += 1) {3309 for (size_t i = 0; i < block_node->data.block.statements.length; i += 1) {
3310 AstNode *statement_node = block_node->data.block.statements.at(i);3310 AstNode *statement_node = block_node->data.block.statements.at(i);
33113311
3312 IrInstSrc *statement_value = astgen_node(ag, statement_node, child_scope);3312 Stage1ZirInst *statement_value = astgen_node(ag, statement_node, child_scope);
3313 if (statement_value == ag->codegen->invalid_inst_src) {3313 if (statement_value == ag->codegen->invalid_inst_src) {
3314 // keep generating all the elements of the block in case of error,3314 // keep generating all the elements of the block in case of error,
3315 // we want to collect other compile errors3315 // we want to collect other compile errors
...@@ -3328,9 +3328,9 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b...@@ -3328,9 +3328,9 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
3328 // defer starts a new scope3328 // defer starts a new scope
3329 child_scope = statement_node->data.defer.child_scope;3329 child_scope = statement_node->data.defer.child_scope;
3330 assert(child_scope);3330 assert(child_scope);
3331 } else if (statement_value->id == IrInstSrcIdDeclVar) {3331 } else if (statement_value->id == Stage1ZirInstIdDeclVar) {
3332 // variable declarations start a new scope3332 // variable declarations start a new scope
3333 IrInstSrcDeclVar *decl_var_instruction = (IrInstSrcDeclVar *)statement_value;3333 Stage1ZirInstDeclVar *decl_var_instruction = (Stage1ZirInstDeclVar *)statement_value;
3334 child_scope = decl_var_instruction->var->child_scope;3334 child_scope = decl_var_instruction->var->child_scope;
3335 } else if (!is_continuation_unreachable) {3335 } else if (!is_continuation_unreachable) {
3336 // this statement's value must be void3336 // this statement's value must be void
...@@ -3355,12 +3355,12 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b...@@ -3355,12 +3355,12 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
3355 scope_block->peer_parent->peers.last()->next_bb = scope_block->end_block;3355 scope_block->peer_parent->peers.last()->next_bb = scope_block->end_block;
3356 }3356 }
3357 ir_set_cursor_at_end_and_append_block(ag, scope_block->end_block);3357 ir_set_cursor_at_end_and_append_block(ag, scope_block->end_block);
3358 IrInstSrc *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length,3358 Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length,
3359 incoming_blocks.items, incoming_values.items, scope_block->peer_parent);3359 incoming_blocks.items, incoming_values.items, scope_block->peer_parent);
3360 return ir_expr_wrap(ag, parent_scope, phi, result_loc);3360 return ir_expr_wrap(ag, parent_scope, phi, result_loc);
3361 } else {3361 } else {
3362 incoming_blocks.append(ag->current_basic_block);3362 incoming_blocks.append(ag->current_basic_block);
3363 IrInstSrc *else_expr_result = ir_build_const_void(ag, parent_scope, block_node);3363 Stage1ZirInst *else_expr_result = ir_build_const_void(ag, parent_scope, block_node);
33643364
3365 if (scope_block->peer_parent != nullptr) {3365 if (scope_block->peer_parent != nullptr) {
3366 ResultLocPeer *peer_result = create_peer_result(scope_block->peer_parent);3366 ResultLocPeer *peer_result = create_peer_result(scope_block->peer_parent);
...@@ -3381,15 +3381,15 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b...@@ -3381,15 +3381,15 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
3381 return ag->codegen->invalid_inst_src;3381 return ag->codegen->invalid_inst_src;
3382 }3382 }
33833383
3384 IrInstSrc *result;3384 Stage1ZirInst *result;
3385 if (block_node->data.block.name != nullptr) {3385 if (block_node->data.block.name != nullptr) {
3386 ir_build_br(ag, parent_scope, block_node, scope_block->end_block, scope_block->is_comptime);3386 ir_build_br(ag, parent_scope, block_node, scope_block->end_block, scope_block->is_comptime);
3387 ir_set_cursor_at_end_and_append_block(ag, scope_block->end_block);3387 ir_set_cursor_at_end_and_append_block(ag, scope_block->end_block);
3388 IrInstSrc *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length,3388 Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length,
3389 incoming_blocks.items, incoming_values.items, scope_block->peer_parent);3389 incoming_blocks.items, incoming_values.items, scope_block->peer_parent);
3390 result = ir_expr_wrap(ag, parent_scope, phi, result_loc);3390 result = ir_expr_wrap(ag, parent_scope, phi, result_loc);
3391 } else {3391 } else {
3392 IrInstSrc *void_inst = ir_build_const_void(ag, child_scope, block_node);3392 Stage1ZirInst *void_inst = ir_build_const_void(ag, child_scope, block_node);
3393 result = ir_lval_wrap(ag, parent_scope, void_inst, lval, result_loc);3393 result = ir_lval_wrap(ag, parent_scope, void_inst, lval, result_loc);
3394 }3394 }
3395 if (!is_return_from_fn)3395 if (!is_return_from_fn)
...@@ -3408,14 +3408,14 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b...@@ -3408,14 +3408,14 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
3408 return ir_build_return_src(ag, child_scope, result->source_node, result);3408 return ir_build_return_src(ag, child_scope, result->source_node, result);
3409}3409}
34103410
3411static IrInstSrc *astgen_bin_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) {3411static Stage1ZirInst *astgen_bin_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) {
3412 Scope *inner_scope = scope;3412 Scope *inner_scope = scope;
3413 if (op_id == IrBinOpArrayCat || op_id == IrBinOpArrayMult) {3413 if (op_id == IrBinOpArrayCat || op_id == IrBinOpArrayMult) {
3414 inner_scope = create_comptime_scope(ag->codegen, node, scope);3414 inner_scope = create_comptime_scope(ag->codegen, node, scope);
3415 }3415 }
34163416
3417 IrInstSrc *op1 = astgen_node(ag, node->data.bin_op_expr.op1, inner_scope);3417 Stage1ZirInst *op1 = astgen_node(ag, node->data.bin_op_expr.op1, inner_scope);
3418 IrInstSrc *op2 = astgen_node(ag, node->data.bin_op_expr.op2, inner_scope);3418 Stage1ZirInst *op2 = astgen_node(ag, node->data.bin_op_expr.op2, inner_scope);
34193419
3420 if (op1 == ag->codegen->invalid_inst_src || op2 == ag->codegen->invalid_inst_src)3420 if (op1 == ag->codegen->invalid_inst_src || op2 == ag->codegen->invalid_inst_src)
3421 return ag->codegen->invalid_inst_src;3421 return ag->codegen->invalid_inst_src;
...@@ -3423,9 +3423,9 @@ static IrInstSrc *astgen_bin_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node...@@ -3423,9 +3423,9 @@ static IrInstSrc *astgen_bin_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node
3423 return ir_build_bin_op(ag, scope, node, op_id, op1, op2, true);3423 return ir_build_bin_op(ag, scope, node, op_id, op1, op2, true);
3424}3424}
34253425
3426static IrInstSrc *astgen_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *node) {3426static Stage1ZirInst *astgen_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3427 IrInstSrc *op1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);3427 Stage1ZirInst *op1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);
3428 IrInstSrc *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);3428 Stage1ZirInst *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
34293429
3430 if (op1 == ag->codegen->invalid_inst_src || op2 == ag->codegen->invalid_inst_src)3430 if (op1 == ag->codegen->invalid_inst_src || op2 == ag->codegen->invalid_inst_src)
3431 return ag->codegen->invalid_inst_src;3431 return ag->codegen->invalid_inst_src;
...@@ -3437,8 +3437,8 @@ static IrInstSrc *astgen_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode...@@ -3437,8 +3437,8 @@ static IrInstSrc *astgen_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode
3437 return ir_build_merge_err_sets(ag, scope, node, op1, op2, type_name);3437 return ir_build_merge_err_sets(ag, scope, node, op1, op2, type_name);
3438}3438}
34393439
3440static IrInstSrc *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) {3440static Stage1ZirInst *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3441 IrInstSrc *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr);3441 Stage1ZirInst *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr);
3442 if (lvalue == ag->codegen->invalid_inst_src)3442 if (lvalue == ag->codegen->invalid_inst_src)
3443 return ag->codegen->invalid_inst_src;3443 return ag->codegen->invalid_inst_src;
34443444
...@@ -3448,7 +3448,7 @@ static IrInstSrc *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) {...@@ -3448,7 +3448,7 @@ static IrInstSrc *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3448 ir_ref_instruction(lvalue, ag->current_basic_block);3448 ir_ref_instruction(lvalue, ag->current_basic_block);
3449 ir_build_reset_result(ag, scope, node, &result_loc_inst->base);3449 ir_build_reset_result(ag, scope, node, &result_loc_inst->base);
34503450
3451 IrInstSrc *rvalue = astgen_node_extra(ag, node->data.bin_op_expr.op2, scope, LValNone,3451 Stage1ZirInst *rvalue = astgen_node_extra(ag, node->data.bin_op_expr.op2, scope, LValNone,
3452 &result_loc_inst->base);3452 &result_loc_inst->base);
3453 if (rvalue == ag->codegen->invalid_inst_src)3453 if (rvalue == ag->codegen->invalid_inst_src)
3454 return ag->codegen->invalid_inst_src;3454 return ag->codegen->invalid_inst_src;
...@@ -3456,28 +3456,28 @@ static IrInstSrc *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) {...@@ -3456,28 +3456,28 @@ static IrInstSrc *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3456 return ir_build_const_void(ag, scope, node);3456 return ir_build_const_void(ag, scope, node);
3457}3457}
34583458
3459static IrInstSrc *astgen_assign_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) {3459static Stage1ZirInst *astgen_assign_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) {
3460 IrInstSrc *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr);3460 Stage1ZirInst *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr);
3461 if (lvalue == ag->codegen->invalid_inst_src)3461 if (lvalue == ag->codegen->invalid_inst_src)
3462 return lvalue;3462 return lvalue;
3463 IrInstSrc *op1 = ir_build_load_ptr(ag, scope, node->data.bin_op_expr.op1, lvalue);3463 Stage1ZirInst *op1 = ir_build_load_ptr(ag, scope, node->data.bin_op_expr.op1, lvalue);
3464 IrInstSrc *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);3464 Stage1ZirInst *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
3465 if (op2 == ag->codegen->invalid_inst_src)3465 if (op2 == ag->codegen->invalid_inst_src)
3466 return op2;3466 return op2;
3467 IrInstSrc *result = ir_build_bin_op(ag, scope, node, op_id, op1, op2, true);3467 Stage1ZirInst *result = ir_build_bin_op(ag, scope, node, op_id, op1, op2, true);
3468 ir_build_store_ptr(ag, scope, node, lvalue, result);3468 ir_build_store_ptr(ag, scope, node, lvalue, result);
3469 return ir_build_const_void(ag, scope, node);3469 return ir_build_const_void(ag, scope, node);
3470}3470}
34713471
3472static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node) {3472static Stage1ZirInst *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3473 assert(node->type == NodeTypeBinOpExpr);3473 assert(node->type == NodeTypeBinOpExpr);
34743474
3475 IrInstSrc *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);3475 Stage1ZirInst *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);
3476 if (val1 == ag->codegen->invalid_inst_src)3476 if (val1 == ag->codegen->invalid_inst_src)
3477 return ag->codegen->invalid_inst_src;3477 return ag->codegen->invalid_inst_src;
3478 Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block;3478 Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block;
34793479
3480 IrInstSrc *is_comptime;3480 Stage1ZirInst *is_comptime;
3481 if (ir_should_inline(ag->exec, scope)) {3481 if (ir_should_inline(ag->exec, scope)) {
3482 is_comptime = ir_build_const_bool(ag, scope, node, true);3482 is_comptime = ir_build_const_bool(ag, scope, node, true);
3483 } else {3483 } else {
...@@ -3492,7 +3492,7 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3492,7 +3492,7 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
3492 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);3492 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);
34933493
3494 ir_set_cursor_at_end_and_append_block(ag, false_block);3494 ir_set_cursor_at_end_and_append_block(ag, false_block);
3495 IrInstSrc *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);3495 Stage1ZirInst *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
3496 if (val2 == ag->codegen->invalid_inst_src)3496 if (val2 == ag->codegen->invalid_inst_src)
3497 return ag->codegen->invalid_inst_src;3497 return ag->codegen->invalid_inst_src;
3498 Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block;3498 Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block;
...@@ -3501,7 +3501,7 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3501,7 +3501,7 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
35013501
3502 ir_set_cursor_at_end_and_append_block(ag, true_block);3502 ir_set_cursor_at_end_and_append_block(ag, true_block);
35033503
3504 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);3504 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
3505 incoming_values[0] = val1;3505 incoming_values[0] = val1;
3506 incoming_values[1] = val2;3506 incoming_values[1] = val2;
3507 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);3507 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
...@@ -3511,15 +3511,15 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3511,15 +3511,15 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
3511 return ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, nullptr);3511 return ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, nullptr);
3512}3512}
35133513
3514static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node) {3514static Stage1ZirInst *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3515 assert(node->type == NodeTypeBinOpExpr);3515 assert(node->type == NodeTypeBinOpExpr);
35163516
3517 IrInstSrc *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);3517 Stage1ZirInst *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);
3518 if (val1 == ag->codegen->invalid_inst_src)3518 if (val1 == ag->codegen->invalid_inst_src)
3519 return ag->codegen->invalid_inst_src;3519 return ag->codegen->invalid_inst_src;
3520 Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block;3520 Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block;
35213521
3522 IrInstSrc *is_comptime;3522 Stage1ZirInst *is_comptime;
3523 if (ir_should_inline(ag->exec, scope)) {3523 if (ir_should_inline(ag->exec, scope)) {
3524 is_comptime = ir_build_const_bool(ag, scope, node, true);3524 is_comptime = ir_build_const_bool(ag, scope, node, true);
3525 } else {3525 } else {
...@@ -3534,7 +3534,7 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3534,7 +3534,7 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
3534 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);3534 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);
35353535
3536 ir_set_cursor_at_end_and_append_block(ag, true_block);3536 ir_set_cursor_at_end_and_append_block(ag, true_block);
3537 IrInstSrc *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);3537 Stage1ZirInst *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
3538 if (val2 == ag->codegen->invalid_inst_src)3538 if (val2 == ag->codegen->invalid_inst_src)
3539 return ag->codegen->invalid_inst_src;3539 return ag->codegen->invalid_inst_src;
3540 Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block;3540 Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block;
...@@ -3543,7 +3543,7 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3543,7 +3543,7 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
35433543
3544 ir_set_cursor_at_end_and_append_block(ag, false_block);3544 ir_set_cursor_at_end_and_append_block(ag, false_block);
35453545
3546 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);3546 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
3547 incoming_values[0] = val1;3547 incoming_values[0] = val1;
3548 incoming_values[1] = val2;3548 incoming_values[1] = val2;
3549 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);3549 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
...@@ -3553,8 +3553,8 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3553,8 +3553,8 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
3553 return ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, nullptr);3553 return ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, nullptr);
3554}3554}
35553555
3556static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst,3556static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, Stage1ZirInst *cond_br_inst,
3557 Stage1ZirBasicBlock *end_block, ResultLoc *parent, IrInstSrc *is_comptime)3557 Stage1ZirBasicBlock *end_block, ResultLoc *parent, Stage1ZirInst *is_comptime)
3558{3558{
3559 ResultLocPeerParent *peer_parent = heap::c_allocator.create<ResultLocPeerParent>();3559 ResultLocPeerParent *peer_parent = heap::c_allocator.create<ResultLocPeerParent>();
3560 peer_parent->base.id = ResultLocIdPeerParent;3560 peer_parent->base.id = ResultLocIdPeerParent;
...@@ -3564,7 +3564,7 @@ static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *c...@@ -3564,7 +3564,7 @@ static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *c
3564 peer_parent->is_comptime = is_comptime;3564 peer_parent->is_comptime = is_comptime;
3565 peer_parent->parent = parent;3565 peer_parent->parent = parent;
35663566
3567 IrInstSrc *popped_inst = ag->current_basic_block->instruction_list.pop();3567 Stage1ZirInst *popped_inst = ag->current_basic_block->instruction_list.pop();
3568 ir_assert(popped_inst == cond_br_inst, cond_br_inst);3568 ir_assert(popped_inst == cond_br_inst, cond_br_inst);
35693569
3570 ir_build_reset_result(ag, cond_br_inst->scope, cond_br_inst->source_node, &peer_parent->base);3570 ir_build_reset_result(ag, cond_br_inst->scope, cond_br_inst->source_node, &peer_parent->base);
...@@ -3573,8 +3573,8 @@ static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *c...@@ -3573,8 +3573,8 @@ static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *c
3573 return peer_parent;3573 return peer_parent;
3574}3574}
35753575
3576static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst,3576static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, Stage1ZirInst *cond_br_inst,
3577 Stage1ZirBasicBlock *else_block, Stage1ZirBasicBlock *end_block, ResultLoc *parent, IrInstSrc *is_comptime)3577 Stage1ZirBasicBlock *else_block, Stage1ZirBasicBlock *end_block, ResultLoc *parent, Stage1ZirInst *is_comptime)
3578{3578{
3579 ResultLocPeerParent *peer_parent = ir_build_result_peers(ag, cond_br_inst, end_block, parent, is_comptime);3579 ResultLocPeerParent *peer_parent = ir_build_result_peers(ag, cond_br_inst, end_block, parent, is_comptime);
35803580
...@@ -3587,7 +3587,7 @@ static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, IrIns...@@ -3587,7 +3587,7 @@ static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, IrIns
3587 return peer_parent;3587 return peer_parent;
3588}3588}
35893589
3590static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,3590static Stage1ZirInst *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,
3591 ResultLoc *result_loc)3591 ResultLoc *result_loc)
3592{3592{
3593 assert(node->type == NodeTypeBinOpExpr);3593 assert(node->type == NodeTypeBinOpExpr);
...@@ -3595,14 +3595,14 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *...@@ -3595,14 +3595,14 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
3595 AstNode *op1_node = node->data.bin_op_expr.op1;3595 AstNode *op1_node = node->data.bin_op_expr.op1;
3596 AstNode *op2_node = node->data.bin_op_expr.op2;3596 AstNode *op2_node = node->data.bin_op_expr.op2;
35973597
3598 IrInstSrc *maybe_ptr = astgen_node_extra(ag, op1_node, parent_scope, LValPtr, nullptr);3598 Stage1ZirInst *maybe_ptr = astgen_node_extra(ag, op1_node, parent_scope, LValPtr, nullptr);
3599 if (maybe_ptr == ag->codegen->invalid_inst_src)3599 if (maybe_ptr == ag->codegen->invalid_inst_src)
3600 return ag->codegen->invalid_inst_src;3600 return ag->codegen->invalid_inst_src;
36013601
3602 IrInstSrc *maybe_val = ir_build_load_ptr(ag, parent_scope, node, maybe_ptr);3602 Stage1ZirInst *maybe_val = ir_build_load_ptr(ag, parent_scope, node, maybe_ptr);
3603 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, parent_scope, node, maybe_val);3603 Stage1ZirInst *is_non_null = ir_build_test_non_null_src(ag, parent_scope, node, maybe_val);
36043604
3605 IrInstSrc *is_comptime;3605 Stage1ZirInst *is_comptime;
3606 if (ir_should_inline(ag->exec, parent_scope)) {3606 if (ir_should_inline(ag->exec, parent_scope)) {
3607 is_comptime = ir_build_const_bool(ag, parent_scope, node, true);3607 is_comptime = ir_build_const_bool(ag, parent_scope, node, true);
3608 } else {3608 } else {
...@@ -3612,13 +3612,13 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *...@@ -3612,13 +3612,13 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
3612 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "OptionalNonNull");3612 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "OptionalNonNull");
3613 Stage1ZirBasicBlock *null_block = ir_create_basic_block(ag, parent_scope, "OptionalNull");3613 Stage1ZirBasicBlock *null_block = ir_create_basic_block(ag, parent_scope, "OptionalNull");
3614 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "OptionalEnd");3614 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "OptionalEnd");
3615 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_non_null, ok_block, null_block, is_comptime);3615 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_non_null, ok_block, null_block, is_comptime);
36163616
3617 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block,3617 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block,
3618 result_loc, is_comptime);3618 result_loc, is_comptime);
36193619
3620 ir_set_cursor_at_end_and_append_block(ag, null_block);3620 ir_set_cursor_at_end_and_append_block(ag, null_block);
3621 IrInstSrc *null_result = astgen_node_extra(ag, op2_node, parent_scope, LValNone,3621 Stage1ZirInst *null_result = astgen_node_extra(ag, op2_node, parent_scope, LValNone,
3622 &peer_parent->peers.at(0)->base);3622 &peer_parent->peers.at(0)->base);
3623 if (null_result == ag->codegen->invalid_inst_src)3623 if (null_result == ag->codegen->invalid_inst_src)
3624 return ag->codegen->invalid_inst_src;3624 return ag->codegen->invalid_inst_src;
...@@ -3627,41 +3627,41 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *...@@ -3627,41 +3627,41 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
3627 ir_build_br(ag, parent_scope, node, end_block, is_comptime);3627 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
36283628
3629 ir_set_cursor_at_end_and_append_block(ag, ok_block);3629 ir_set_cursor_at_end_and_append_block(ag, ok_block);
3630 IrInstSrc *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, parent_scope, node, maybe_ptr, false);3630 Stage1ZirInst *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, parent_scope, node, maybe_ptr, false);
3631 IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);3631 Stage1ZirInst *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);
3632 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);3632 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);
3633 Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block;3633 Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block;
3634 ir_build_br(ag, parent_scope, node, end_block, is_comptime);3634 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
36353635
3636 ir_set_cursor_at_end_and_append_block(ag, end_block);3636 ir_set_cursor_at_end_and_append_block(ag, end_block);
3637 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);3637 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
3638 incoming_values[0] = null_result;3638 incoming_values[0] = null_result;
3639 incoming_values[1] = unwrapped_payload;3639 incoming_values[1] = unwrapped_payload;
3640 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);3640 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
3641 incoming_blocks[0] = after_null_block;3641 incoming_blocks[0] = after_null_block;
3642 incoming_blocks[1] = after_ok_block;3642 incoming_blocks[1] = after_ok_block;
3643 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);3643 Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);
3644 return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc);3644 return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc);
3645}3645}
36463646
3647static IrInstSrc *astgen_error_union(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {3647static Stage1ZirInst *astgen_error_union(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
3648 assert(node->type == NodeTypeBinOpExpr);3648 assert(node->type == NodeTypeBinOpExpr);
36493649
3650 AstNode *op1_node = node->data.bin_op_expr.op1;3650 AstNode *op1_node = node->data.bin_op_expr.op1;
3651 AstNode *op2_node = node->data.bin_op_expr.op2;3651 AstNode *op2_node = node->data.bin_op_expr.op2;
36523652
3653 IrInstSrc *err_set = astgen_node(ag, op1_node, parent_scope);3653 Stage1ZirInst *err_set = astgen_node(ag, op1_node, parent_scope);
3654 if (err_set == ag->codegen->invalid_inst_src)3654 if (err_set == ag->codegen->invalid_inst_src)
3655 return ag->codegen->invalid_inst_src;3655 return ag->codegen->invalid_inst_src;
36563656
3657 IrInstSrc *payload = astgen_node(ag, op2_node, parent_scope);3657 Stage1ZirInst *payload = astgen_node(ag, op2_node, parent_scope);
3658 if (payload == ag->codegen->invalid_inst_src)3658 if (payload == ag->codegen->invalid_inst_src)
3659 return ag->codegen->invalid_inst_src;3659 return ag->codegen->invalid_inst_src;
36603660
3661 return ir_build_error_union(ag, parent_scope, node, err_set, payload);3661 return ir_build_error_union(ag, parent_scope, node, err_set, payload);
3662}3662}
36633663
3664static IrInstSrc *astgen_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {3664static Stage1ZirInst *astgen_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {
3665 assert(node->type == NodeTypeBinOpExpr);3665 assert(node->type == NodeTypeBinOpExpr);
36663666
3667 BinOpType bin_op_type = node->data.bin_op_expr.bin_op;3667 BinOpType bin_op_type = node->data.bin_op_expr.bin_op;
...@@ -3752,7 +3752,7 @@ static IrInstSrc *astgen_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *node, L...@@ -3752,7 +3752,7 @@ static IrInstSrc *astgen_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *node, L
3752 zig_unreachable();3752 zig_unreachable();
3753}3753}
37543754
3755static IrInstSrc *astgen_int_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {3755static Stage1ZirInst *astgen_int_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3756 assert(node->type == NodeTypeIntLiteral);3756 assert(node->type == NodeTypeIntLiteral);
37573757
3758 RootStruct *root_struct = node->owner->data.structure.root_struct;3758 RootStruct *root_struct = node->owner->data.structure.root_struct;
...@@ -3761,7 +3761,7 @@ static IrInstSrc *astgen_int_lit(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3761,7 +3761,7 @@ static IrInstSrc *astgen_int_lit(Stage1AstGen *ag, Scope *scope, AstNode *node)
3761 return ir_build_const_bigint(ag, scope, node, bigint);3761 return ir_build_const_bigint(ag, scope, node, bigint);
3762}3762}
37633763
3764static IrInstSrc *astgen_float_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {3764static Stage1ZirInst *astgen_float_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3765 Error err;3765 Error err;
3766 assert(node->type == NodeTypeFloatLiteral);3766 assert(node->type == NodeTypeFloatLiteral);
37673767
...@@ -3778,7 +3778,7 @@ static IrInstSrc *astgen_float_lit(Stage1AstGen *ag, Scope *scope, AstNode *node...@@ -3778,7 +3778,7 @@ static IrInstSrc *astgen_float_lit(Stage1AstGen *ag, Scope *scope, AstNode *node
3778 return ir_build_const_bigfloat(ag, scope, node, bigfloat);3778 return ir_build_const_bigfloat(ag, scope, node, bigfloat);
3779}3779}
37803780
3781static IrInstSrc *astgen_char_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {3781static Stage1ZirInst *astgen_char_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3782 Error err;3782 Error err;
3783 assert(node->type == NodeTypeCharLiteral);3783 assert(node->type == NodeTypeCharLiteral);
37843784
...@@ -3798,13 +3798,13 @@ static IrInstSrc *astgen_char_lit(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3798,13 +3798,13 @@ static IrInstSrc *astgen_char_lit(Stage1AstGen *ag, Scope *scope, AstNode *node)
3798 return ir_build_const_uint(ag, scope, node, codepoint);3798 return ir_build_const_uint(ag, scope, node, codepoint);
3799}3799}
38003800
3801static IrInstSrc *astgen_null_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {3801static Stage1ZirInst *astgen_null_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3802 assert(node->type == NodeTypeNullLiteral);3802 assert(node->type == NodeTypeNullLiteral);
38033803
3804 return ir_build_const_null(ag, scope, node);3804 return ir_build_const_null(ag, scope, node);
3805}3805}
38063806
3807static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,3807static Stage1ZirInst *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
3808 ResultLoc *result_loc)3808 ResultLoc *result_loc)
3809{3809{
3810 Error err;3810 Error err;
...@@ -3814,7 +3814,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -3814,7 +3814,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod
38143814
3815 if (buf_eql_str(variable_name, "_")) {3815 if (buf_eql_str(variable_name, "_")) {
3816 if (lval == LValAssign) {3816 if (lval == LValAssign) {
3817 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, node);3817 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, node);
3818 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();3818 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
3819 const_instruction->value->type = get_pointer_to_type(ag->codegen,3819 const_instruction->value->type = get_pointer_to_type(ag->codegen,
3820 ag->codegen->builtin_types.entry_void, false);3820 ag->codegen->builtin_types.entry_void, false);
...@@ -3837,7 +3837,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -3837,7 +3837,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod
3837 }3837 }
3838 assert(err == ErrorPrimitiveTypeNotFound);3838 assert(err == ErrorPrimitiveTypeNotFound);
3839 } else {3839 } else {
3840 IrInstSrc *value = ir_build_const_type(ag, scope, node, primitive_type);3840 Stage1ZirInst *value = ir_build_const_type(ag, scope, node, primitive_type);
3841 if (lval == LValPtr || lval == LValAssign) {3841 if (lval == LValPtr || lval == LValAssign) {
3842 return ir_build_ref_src(ag, scope, node, value);3842 return ir_build_ref_src(ag, scope, node, value);
3843 } else {3843 } else {
...@@ -3848,7 +3848,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -3848,7 +3848,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod
3848 ScopeFnDef *crossed_fndef_scope;3848 ScopeFnDef *crossed_fndef_scope;
3849 ZigVar *var = find_variable(ag->codegen, scope, variable_name, &crossed_fndef_scope);3849 ZigVar *var = find_variable(ag->codegen, scope, variable_name, &crossed_fndef_scope);
3850 if (var) {3850 if (var) {
3851 IrInstSrc *var_ptr = ir_build_var_ptr_x(ag, scope, node, var, crossed_fndef_scope);3851 Stage1ZirInst *var_ptr = ir_build_var_ptr_x(ag, scope, node, var, crossed_fndef_scope);
3852 if (lval == LValPtr || lval == LValAssign) {3852 if (lval == LValPtr || lval == LValAssign) {
3853 return var_ptr;3853 return var_ptr;
3854 } else {3854 } else {
...@@ -3858,7 +3858,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -3858,7 +3858,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod
38583858
3859 Tld *tld = find_decl(ag->codegen, scope, variable_name);3859 Tld *tld = find_decl(ag->codegen, scope, variable_name);
3860 if (tld) {3860 if (tld) {
3861 IrInstSrc *decl_ref = ir_build_decl_ref(ag, scope, node, tld, lval);3861 Stage1ZirInst *decl_ref = ir_build_decl_ref(ag, scope, node, tld, lval);
3862 if (lval == LValPtr || lval == LValAssign) {3862 if (lval == LValPtr || lval == LValAssign) {
3863 return decl_ref;3863 return decl_ref;
3864 } else {3864 } else {
...@@ -3875,52 +3875,52 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -3875,52 +3875,52 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod
3875 return ir_build_undeclared_identifier(ag, scope, node, variable_name);3875 return ir_build_undeclared_identifier(ag, scope, node, variable_name);
3876}3876}
38773877
3878static IrInstSrc *astgen_array_access(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,3878static Stage1ZirInst *astgen_array_access(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
3879 ResultLoc *result_loc)3879 ResultLoc *result_loc)
3880{3880{
3881 assert(node->type == NodeTypeArrayAccessExpr);3881 assert(node->type == NodeTypeArrayAccessExpr);
38823882
3883 AstNode *array_ref_node = node->data.array_access_expr.array_ref_expr;3883 AstNode *array_ref_node = node->data.array_access_expr.array_ref_expr;
3884 IrInstSrc *array_ref_instruction = astgen_node_extra(ag, array_ref_node, scope, LValPtr, nullptr);3884 Stage1ZirInst *array_ref_instruction = astgen_node_extra(ag, array_ref_node, scope, LValPtr, nullptr);
3885 if (array_ref_instruction == ag->codegen->invalid_inst_src)3885 if (array_ref_instruction == ag->codegen->invalid_inst_src)
3886 return array_ref_instruction;3886 return array_ref_instruction;
38873887
3888 // Create an usize-typed result location to hold the subscript value, this3888 // Create an usize-typed result location to hold the subscript value, this
3889 // makes it possible for the compiler to infer the subscript expression type3889 // makes it possible for the compiler to infer the subscript expression type
3890 // if needed3890 // if needed
3891 IrInstSrc *usize_type_inst = ir_build_const_type(ag, scope, node, ag->codegen->builtin_types.entry_usize);3891 Stage1ZirInst *usize_type_inst = ir_build_const_type(ag, scope, node, ag->codegen->builtin_types.entry_usize);
3892 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, usize_type_inst, no_result_loc());3892 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, usize_type_inst, no_result_loc());
38933893
3894 AstNode *subscript_node = node->data.array_access_expr.subscript;3894 AstNode *subscript_node = node->data.array_access_expr.subscript;
3895 IrInstSrc *subscript_value = astgen_node_extra(ag, subscript_node, scope, LValNone, &result_loc_cast->base);3895 Stage1ZirInst *subscript_value = astgen_node_extra(ag, subscript_node, scope, LValNone, &result_loc_cast->base);
3896 if (subscript_value == ag->codegen->invalid_inst_src)3896 if (subscript_value == ag->codegen->invalid_inst_src)
3897 return ag->codegen->invalid_inst_src;3897 return ag->codegen->invalid_inst_src;
38983898
3899 IrInstSrc *subscript_instruction = ir_build_implicit_cast(ag, scope, subscript_node, subscript_value, result_loc_cast);3899 Stage1ZirInst *subscript_instruction = ir_build_implicit_cast(ag, scope, subscript_node, subscript_value, result_loc_cast);
39003900
3901 IrInstSrc *ptr_instruction = ir_build_elem_ptr(ag, scope, node, array_ref_instruction,3901 Stage1ZirInst *ptr_instruction = ir_build_elem_ptr(ag, scope, node, array_ref_instruction,
3902 subscript_instruction, true, PtrLenSingle, nullptr);3902 subscript_instruction, true, PtrLenSingle, nullptr);
3903 if (lval == LValPtr || lval == LValAssign)3903 if (lval == LValPtr || lval == LValAssign)
3904 return ptr_instruction;3904 return ptr_instruction;
39053905
3906 IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);3906 Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);
3907 return ir_expr_wrap(ag, scope, load_ptr, result_loc);3907 return ir_expr_wrap(ag, scope, load_ptr, result_loc);
3908}3908}
39093909
3910static IrInstSrc *astgen_field_access(Stage1AstGen *ag, Scope *scope, AstNode *node) {3910static Stage1ZirInst *astgen_field_access(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3911 assert(node->type == NodeTypeFieldAccessExpr);3911 assert(node->type == NodeTypeFieldAccessExpr);
39123912
3913 AstNode *container_ref_node = node->data.field_access_expr.struct_expr;3913 AstNode *container_ref_node = node->data.field_access_expr.struct_expr;
3914 Buf *field_name = node->data.field_access_expr.field_name;3914 Buf *field_name = node->data.field_access_expr.field_name;
39153915
3916 IrInstSrc *container_ref_instruction = astgen_node_extra(ag, container_ref_node, scope, LValPtr, nullptr);3916 Stage1ZirInst *container_ref_instruction = astgen_node_extra(ag, container_ref_node, scope, LValPtr, nullptr);
3917 if (container_ref_instruction == ag->codegen->invalid_inst_src)3917 if (container_ref_instruction == ag->codegen->invalid_inst_src)
3918 return container_ref_instruction;3918 return container_ref_instruction;
39193919
3920 return ir_build_field_ptr(ag, scope, node, container_ref_instruction, field_name, false);3920 return ir_build_field_ptr(ag, scope, node, container_ref_instruction, field_name, false);
3921}3921}
39223922
3923static IrInstSrc *astgen_overflow_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrOverflowOp op) {3923static Stage1ZirInst *astgen_overflow_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrOverflowOp op) {
3924 assert(node->type == NodeTypeFnCallExpr);3924 assert(node->type == NodeTypeFnCallExpr);
39253925
3926 AstNode *type_node = node->data.fn_call_expr.params.at(0);3926 AstNode *type_node = node->data.fn_call_expr.params.at(0);
...@@ -3929,26 +3929,26 @@ static IrInstSrc *astgen_overflow_op(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -3929,26 +3929,26 @@ static IrInstSrc *astgen_overflow_op(Stage1AstGen *ag, Scope *scope, AstNode *no
3929 AstNode *result_ptr_node = node->data.fn_call_expr.params.at(3);3929 AstNode *result_ptr_node = node->data.fn_call_expr.params.at(3);
39303930
39313931
3932 IrInstSrc *type_value = astgen_node(ag, type_node, scope);3932 Stage1ZirInst *type_value = astgen_node(ag, type_node, scope);
3933 if (type_value == ag->codegen->invalid_inst_src)3933 if (type_value == ag->codegen->invalid_inst_src)
3934 return ag->codegen->invalid_inst_src;3934 return ag->codegen->invalid_inst_src;
39353935
3936 IrInstSrc *op1 = astgen_node(ag, op1_node, scope);3936 Stage1ZirInst *op1 = astgen_node(ag, op1_node, scope);
3937 if (op1 == ag->codegen->invalid_inst_src)3937 if (op1 == ag->codegen->invalid_inst_src)
3938 return ag->codegen->invalid_inst_src;3938 return ag->codegen->invalid_inst_src;
39393939
3940 IrInstSrc *op2 = astgen_node(ag, op2_node, scope);3940 Stage1ZirInst *op2 = astgen_node(ag, op2_node, scope);
3941 if (op2 == ag->codegen->invalid_inst_src)3941 if (op2 == ag->codegen->invalid_inst_src)
3942 return ag->codegen->invalid_inst_src;3942 return ag->codegen->invalid_inst_src;
39433943
3944 IrInstSrc *result_ptr = astgen_node(ag, result_ptr_node, scope);3944 Stage1ZirInst *result_ptr = astgen_node(ag, result_ptr_node, scope);
3945 if (result_ptr == ag->codegen->invalid_inst_src)3945 if (result_ptr == ag->codegen->invalid_inst_src)
3946 return ag->codegen->invalid_inst_src;3946 return ag->codegen->invalid_inst_src;
39473947
3948 return ir_build_overflow_op_src(ag, scope, node, op, type_value, op1, op2, result_ptr);3948 return ir_build_overflow_op_src(ag, scope, node, op, type_value, op1, op2, result_ptr);
3949}3949}
39503950
3951static IrInstSrc *astgen_mul_add(Stage1AstGen *ag, Scope *scope, AstNode *node) {3951static Stage1ZirInst *astgen_mul_add(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3952 assert(node->type == NodeTypeFnCallExpr);3952 assert(node->type == NodeTypeFnCallExpr);
39533953
3954 AstNode *type_node = node->data.fn_call_expr.params.at(0);3954 AstNode *type_node = node->data.fn_call_expr.params.at(0);
...@@ -3956,26 +3956,26 @@ static IrInstSrc *astgen_mul_add(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3956,26 +3956,26 @@ static IrInstSrc *astgen_mul_add(Stage1AstGen *ag, Scope *scope, AstNode *node)
3956 AstNode *op2_node = node->data.fn_call_expr.params.at(2);3956 AstNode *op2_node = node->data.fn_call_expr.params.at(2);
3957 AstNode *op3_node = node->data.fn_call_expr.params.at(3);3957 AstNode *op3_node = node->data.fn_call_expr.params.at(3);
39583958
3959 IrInstSrc *type_value = astgen_node(ag, type_node, scope);3959 Stage1ZirInst *type_value = astgen_node(ag, type_node, scope);
3960 if (type_value == ag->codegen->invalid_inst_src)3960 if (type_value == ag->codegen->invalid_inst_src)
3961 return ag->codegen->invalid_inst_src;3961 return ag->codegen->invalid_inst_src;
39623962
3963 IrInstSrc *op1 = astgen_node(ag, op1_node, scope);3963 Stage1ZirInst *op1 = astgen_node(ag, op1_node, scope);
3964 if (op1 == ag->codegen->invalid_inst_src)3964 if (op1 == ag->codegen->invalid_inst_src)
3965 return ag->codegen->invalid_inst_src;3965 return ag->codegen->invalid_inst_src;
39663966
3967 IrInstSrc *op2 = astgen_node(ag, op2_node, scope);3967 Stage1ZirInst *op2 = astgen_node(ag, op2_node, scope);
3968 if (op2 == ag->codegen->invalid_inst_src)3968 if (op2 == ag->codegen->invalid_inst_src)
3969 return ag->codegen->invalid_inst_src;3969 return ag->codegen->invalid_inst_src;
39703970
3971 IrInstSrc *op3 = astgen_node(ag, op3_node, scope);3971 Stage1ZirInst *op3 = astgen_node(ag, op3_node, scope);
3972 if (op3 == ag->codegen->invalid_inst_src)3972 if (op3 == ag->codegen->invalid_inst_src)
3973 return ag->codegen->invalid_inst_src;3973 return ag->codegen->invalid_inst_src;
39743974
3975 return ir_build_mul_add_src(ag, scope, node, type_value, op1, op2, op3);3975 return ir_build_mul_add_src(ag, scope, node, type_value, op1, op2, op3);
3976}3976}
39773977
3978static IrInstSrc *astgen_this(Stage1AstGen *ag, Scope *orig_scope, AstNode *node) {3978static Stage1ZirInst *astgen_this(Stage1AstGen *ag, Scope *orig_scope, AstNode *node) {
3979 for (Scope *it_scope = orig_scope; it_scope != nullptr; it_scope = it_scope->parent) {3979 for (Scope *it_scope = orig_scope; it_scope != nullptr; it_scope = it_scope->parent) {
3980 if (it_scope->id == ScopeIdDecls) {3980 if (it_scope->id == ScopeIdDecls) {
3981 ScopeDecls *decls_scope = (ScopeDecls *)it_scope;3981 ScopeDecls *decls_scope = (ScopeDecls *)it_scope;
...@@ -3990,7 +3990,7 @@ static IrInstSrc *astgen_this(Stage1AstGen *ag, Scope *orig_scope, AstNode *node...@@ -3990,7 +3990,7 @@ static IrInstSrc *astgen_this(Stage1AstGen *ag, Scope *orig_scope, AstNode *node
3990 zig_unreachable();3990 zig_unreachable();
3991}3991}
39923992
3993static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *await_node, AstNode *call_node,3993static Stage1ZirInst *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *await_node, AstNode *call_node,
3994 LVal lval, ResultLoc *result_loc)3994 LVal lval, ResultLoc *result_loc)
3995{3995{
3996 if (call_node->data.fn_call_expr.params.length != 4) {3996 if (call_node->data.fn_call_expr.params.length != 4) {
...@@ -4001,17 +4001,17 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa...@@ -4001,17 +4001,17 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa
4001 }4001 }
40024002
4003 AstNode *bytes_node = call_node->data.fn_call_expr.params.at(0);4003 AstNode *bytes_node = call_node->data.fn_call_expr.params.at(0);
4004 IrInstSrc *bytes = astgen_node(ag, bytes_node, scope);4004 Stage1ZirInst *bytes = astgen_node(ag, bytes_node, scope);
4005 if (bytes == ag->codegen->invalid_inst_src)4005 if (bytes == ag->codegen->invalid_inst_src)
4006 return bytes;4006 return bytes;
40074007
4008 AstNode *ret_ptr_node = call_node->data.fn_call_expr.params.at(1);4008 AstNode *ret_ptr_node = call_node->data.fn_call_expr.params.at(1);
4009 IrInstSrc *ret_ptr = astgen_node(ag, ret_ptr_node, scope);4009 Stage1ZirInst *ret_ptr = astgen_node(ag, ret_ptr_node, scope);
4010 if (ret_ptr == ag->codegen->invalid_inst_src)4010 if (ret_ptr == ag->codegen->invalid_inst_src)
4011 return ret_ptr;4011 return ret_ptr;
40124012
4013 AstNode *fn_ref_node = call_node->data.fn_call_expr.params.at(2);4013 AstNode *fn_ref_node = call_node->data.fn_call_expr.params.at(2);
4014 IrInstSrc *fn_ref = astgen_node(ag, fn_ref_node, scope);4014 Stage1ZirInst *fn_ref = astgen_node(ag, fn_ref_node, scope);
4015 if (fn_ref == ag->codegen->invalid_inst_src)4015 if (fn_ref == ag->codegen->invalid_inst_src)
4016 return fn_ref;4016 return fn_ref;
40174017
...@@ -4023,16 +4023,16 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa...@@ -4023,16 +4023,16 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa
4023 args_node->data.container_init_expr.entries.length == 0)4023 args_node->data.container_init_expr.entries.length == 0)
4024 {4024 {
4025 size_t arg_count = args_node->data.container_init_expr.entries.length;4025 size_t arg_count = args_node->data.container_init_expr.entries.length;
4026 IrInstSrc **args = heap::c_allocator.allocate<IrInstSrc*>(arg_count);4026 Stage1ZirInst **args = heap::c_allocator.allocate<Stage1ZirInst*>(arg_count);
4027 for (size_t i = 0; i < arg_count; i += 1) {4027 for (size_t i = 0; i < arg_count; i += 1) {
4028 AstNode *arg_node = args_node->data.container_init_expr.entries.at(i);4028 AstNode *arg_node = args_node->data.container_init_expr.entries.at(i);
4029 IrInstSrc *arg = astgen_node(ag, arg_node, scope);4029 Stage1ZirInst *arg = astgen_node(ag, arg_node, scope);
4030 if (arg == ag->codegen->invalid_inst_src)4030 if (arg == ag->codegen->invalid_inst_src)
4031 return arg;4031 return arg;
4032 args[i] = arg;4032 args[i] = arg;
4033 }4033 }
40344034
4035 IrInstSrc *call = ir_build_call_src(ag, scope, call_node, nullptr, fn_ref, arg_count, args,4035 Stage1ZirInst *call = ir_build_call_src(ag, scope, call_node, nullptr, fn_ref, arg_count, args,
4036 ret_ptr, modifier, is_async_call_builtin, bytes, result_loc);4036 ret_ptr, modifier, is_async_call_builtin, bytes, result_loc);
4037 return ir_lval_wrap(ag, scope, call, lval, result_loc);4037 return ir_lval_wrap(ag, scope, call, lval, result_loc);
4038 } else {4038 } else {
...@@ -4041,42 +4041,42 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa...@@ -4041,42 +4041,42 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa
4041 return ag->codegen->invalid_inst_src;4041 return ag->codegen->invalid_inst_src;
4042 }4042 }
4043 }4043 }
4044 IrInstSrc *args = astgen_node(ag, args_node, scope);4044 Stage1ZirInst *args = astgen_node(ag, args_node, scope);
4045 if (args == ag->codegen->invalid_inst_src)4045 if (args == ag->codegen->invalid_inst_src)
4046 return args;4046 return args;
40474047
4048 IrInstSrc *call = ir_build_async_call_extra(ag, scope, call_node, modifier, fn_ref, ret_ptr, bytes, args, result_loc);4048 Stage1ZirInst *call = ir_build_async_call_extra(ag, scope, call_node, modifier, fn_ref, ret_ptr, bytes, args, result_loc);
4049 return ir_lval_wrap(ag, scope, call, lval, result_loc);4049 return ir_lval_wrap(ag, scope, call, lval, result_loc);
4050}4050}
40514051
4052static IrInstSrc *astgen_fn_call_with_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node,4052static Stage1ZirInst *astgen_fn_call_with_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
4053 AstNode *fn_ref_node, CallModifier modifier, IrInstSrc *options,4053 AstNode *fn_ref_node, CallModifier modifier, Stage1ZirInst *options,
4054 AstNode **args_ptr, size_t args_len, LVal lval, ResultLoc *result_loc)4054 AstNode **args_ptr, size_t args_len, LVal lval, ResultLoc *result_loc)
4055{4055{
4056 IrInstSrc *fn_ref = astgen_node(ag, fn_ref_node, scope);4056 Stage1ZirInst *fn_ref = astgen_node(ag, fn_ref_node, scope);
4057 if (fn_ref == ag->codegen->invalid_inst_src)4057 if (fn_ref == ag->codegen->invalid_inst_src)
4058 return fn_ref;4058 return fn_ref;
40594059
4060 IrInstSrc *fn_type = ir_build_typeof_1(ag, scope, source_node, fn_ref);4060 Stage1ZirInst *fn_type = ir_build_typeof_1(ag, scope, source_node, fn_ref);
40614061
4062 IrInstSrc **args = heap::c_allocator.allocate<IrInstSrc*>(args_len);4062 Stage1ZirInst **args = heap::c_allocator.allocate<Stage1ZirInst*>(args_len);
4063 for (size_t i = 0; i < args_len; i += 1) {4063 for (size_t i = 0; i < args_len; i += 1) {
4064 AstNode *arg_node = args_ptr[i];4064 AstNode *arg_node = args_ptr[i];
40654065
4066 IrInstSrc *arg_index = ir_build_const_usize(ag, scope, arg_node, i);4066 Stage1ZirInst *arg_index = ir_build_const_usize(ag, scope, arg_node, i);
4067 IrInstSrc *arg_type = ir_build_arg_type(ag, scope, source_node, fn_type, arg_index, true);4067 Stage1ZirInst *arg_type = ir_build_arg_type(ag, scope, source_node, fn_type, arg_index, true);
4068 ResultLoc *no_result = no_result_loc();4068 ResultLoc *no_result = no_result_loc();
4069 ir_build_reset_result(ag, scope, source_node, no_result);4069 ir_build_reset_result(ag, scope, source_node, no_result);
4070 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, arg_type, no_result);4070 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, arg_type, no_result);
40714071
4072 IrInstSrc *arg = astgen_node_extra(ag, arg_node, scope, LValNone, &result_loc_cast->base);4072 Stage1ZirInst *arg = astgen_node_extra(ag, arg_node, scope, LValNone, &result_loc_cast->base);
4073 if (arg == ag->codegen->invalid_inst_src)4073 if (arg == ag->codegen->invalid_inst_src)
4074 return arg;4074 return arg;
40754075
4076 args[i] = ir_build_implicit_cast(ag, scope, arg_node, arg, result_loc_cast);4076 args[i] = ir_build_implicit_cast(ag, scope, arg_node, arg, result_loc_cast);
4077 }4077 }
40784078
4079 IrInstSrc *fn_call;4079 Stage1ZirInst *fn_call;
4080 if (options != nullptr) {4080 if (options != nullptr) {
4081 fn_call = ir_build_call_args(ag, scope, source_node, options, fn_ref, args, args_len, result_loc);4081 fn_call = ir_build_call_args(ag, scope, source_node, options, fn_ref, args, args_len, result_loc);
4082 } else {4082 } else {
...@@ -4086,7 +4086,7 @@ static IrInstSrc *astgen_fn_call_with_args(Stage1AstGen *ag, Scope *scope, AstNo...@@ -4086,7 +4086,7 @@ static IrInstSrc *astgen_fn_call_with_args(Stage1AstGen *ag, Scope *scope, AstNo
4086 return ir_lval_wrap(ag, scope, fn_call, lval, result_loc);4086 return ir_lval_wrap(ag, scope, fn_call, lval, result_loc);
4087}4087}
40884088
4089static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,4089static Stage1ZirInst *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
4090 ResultLoc *result_loc)4090 ResultLoc *result_loc)
4091{4091{
4092 assert(node->type == NodeTypeFnCallExpr);4092 assert(node->type == NodeTypeFnCallExpr);
...@@ -4120,7 +4120,7 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4120,7 +4120,7 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
41204120
4121 size_t arg_count = node->data.fn_call_expr.params.length;4121 size_t arg_count = node->data.fn_call_expr.params.length;
41224122
4123 IrInstSrc *type_of;4123 Stage1ZirInst *type_of;
41244124
4125 if (arg_count == 0) {4125 if (arg_count == 0) {
4126 add_node_error(ag->codegen, node,4126 add_node_error(ag->codegen, node,
...@@ -4128,16 +4128,16 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4128,16 +4128,16 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4128 return ag->codegen->invalid_inst_src;4128 return ag->codegen->invalid_inst_src;
4129 } else if (arg_count == 1) {4129 } else if (arg_count == 1) {
4130 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4130 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4131 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, sub_scope);4131 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, sub_scope);
4132 if (arg0_value == ag->codegen->invalid_inst_src)4132 if (arg0_value == ag->codegen->invalid_inst_src)
4133 return arg0_value;4133 return arg0_value;
41344134
4135 type_of = ir_build_typeof_1(ag, scope, node, arg0_value);4135 type_of = ir_build_typeof_1(ag, scope, node, arg0_value);
4136 } else {4136 } else {
4137 IrInstSrc **args = heap::c_allocator.allocate<IrInstSrc*>(arg_count);4137 Stage1ZirInst **args = heap::c_allocator.allocate<Stage1ZirInst*>(arg_count);
4138 for (size_t i = 0; i < arg_count; i += 1) {4138 for (size_t i = 0; i < arg_count; i += 1) {
4139 AstNode *arg_node = node->data.fn_call_expr.params.at(i);4139 AstNode *arg_node = node->data.fn_call_expr.params.at(i);
4140 IrInstSrc *arg = astgen_node(ag, arg_node, sub_scope);4140 Stage1ZirInst *arg = astgen_node(ag, arg_node, sub_scope);
4141 if (arg == ag->codegen->invalid_inst_src)4141 if (arg == ag->codegen->invalid_inst_src)
4142 return ag->codegen->invalid_inst_src;4142 return ag->codegen->invalid_inst_src;
4143 args[i] = arg;4143 args[i] = arg;
...@@ -4150,63 +4150,63 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4150,63 +4150,63 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4150 case BuiltinFnIdSetCold:4150 case BuiltinFnIdSetCold:
4151 {4151 {
4152 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4152 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4153 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4153 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4154 if (arg0_value == ag->codegen->invalid_inst_src)4154 if (arg0_value == ag->codegen->invalid_inst_src)
4155 return arg0_value;4155 return arg0_value;
41564156
4157 IrInstSrc *set_cold = ir_build_set_cold(ag, scope, node, arg0_value);4157 Stage1ZirInst *set_cold = ir_build_set_cold(ag, scope, node, arg0_value);
4158 return ir_lval_wrap(ag, scope, set_cold, lval, result_loc);4158 return ir_lval_wrap(ag, scope, set_cold, lval, result_loc);
4159 }4159 }
4160 case BuiltinFnIdSetRuntimeSafety:4160 case BuiltinFnIdSetRuntimeSafety:
4161 {4161 {
4162 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4162 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4163 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4163 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4164 if (arg0_value == ag->codegen->invalid_inst_src)4164 if (arg0_value == ag->codegen->invalid_inst_src)
4165 return arg0_value;4165 return arg0_value;
41664166
4167 IrInstSrc *set_safety = ir_build_set_runtime_safety(ag, scope, node, arg0_value);4167 Stage1ZirInst *set_safety = ir_build_set_runtime_safety(ag, scope, node, arg0_value);
4168 return ir_lval_wrap(ag, scope, set_safety, lval, result_loc);4168 return ir_lval_wrap(ag, scope, set_safety, lval, result_loc);
4169 }4169 }
4170 case BuiltinFnIdSetFloatMode:4170 case BuiltinFnIdSetFloatMode:
4171 {4171 {
4172 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4172 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4173 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4173 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4174 if (arg0_value == ag->codegen->invalid_inst_src)4174 if (arg0_value == ag->codegen->invalid_inst_src)
4175 return arg0_value;4175 return arg0_value;
41764176
4177 IrInstSrc *set_float_mode = ir_build_set_float_mode(ag, scope, node, arg0_value);4177 Stage1ZirInst *set_float_mode = ir_build_set_float_mode(ag, scope, node, arg0_value);
4178 return ir_lval_wrap(ag, scope, set_float_mode, lval, result_loc);4178 return ir_lval_wrap(ag, scope, set_float_mode, lval, result_loc);
4179 }4179 }
4180 case BuiltinFnIdSizeof:4180 case BuiltinFnIdSizeof:
4181 case BuiltinFnIdBitSizeof:4181 case BuiltinFnIdBitSizeof:
4182 {4182 {
4183 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4183 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4184 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4184 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4185 if (arg0_value == ag->codegen->invalid_inst_src)4185 if (arg0_value == ag->codegen->invalid_inst_src)
4186 return arg0_value;4186 return arg0_value;
41874187
4188 IrInstSrc *size_of = ir_build_size_of(ag, scope, node, arg0_value, builtin_fn->id == BuiltinFnIdBitSizeof);4188 Stage1ZirInst *size_of = ir_build_size_of(ag, scope, node, arg0_value, builtin_fn->id == BuiltinFnIdBitSizeof);
4189 return ir_lval_wrap(ag, scope, size_of, lval, result_loc);4189 return ir_lval_wrap(ag, scope, size_of, lval, result_loc);
4190 }4190 }
4191 case BuiltinFnIdImport:4191 case BuiltinFnIdImport:
4192 {4192 {
4193 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4193 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4194 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4194 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4195 if (arg0_value == ag->codegen->invalid_inst_src)4195 if (arg0_value == ag->codegen->invalid_inst_src)
4196 return arg0_value;4196 return arg0_value;
41974197
4198 IrInstSrc *import = ir_build_import(ag, scope, node, arg0_value);4198 Stage1ZirInst *import = ir_build_import(ag, scope, node, arg0_value);
4199 return ir_lval_wrap(ag, scope, import, lval, result_loc);4199 return ir_lval_wrap(ag, scope, import, lval, result_loc);
4200 }4200 }
4201 case BuiltinFnIdCImport:4201 case BuiltinFnIdCImport:
4202 {4202 {
4203 IrInstSrc *c_import = ir_build_c_import(ag, scope, node);4203 Stage1ZirInst *c_import = ir_build_c_import(ag, scope, node);
4204 return ir_lval_wrap(ag, scope, c_import, lval, result_loc);4204 return ir_lval_wrap(ag, scope, c_import, lval, result_loc);
4205 }4205 }
4206 case BuiltinFnIdCInclude:4206 case BuiltinFnIdCInclude:
4207 {4207 {
4208 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4208 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4209 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4209 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4210 if (arg0_value == ag->codegen->invalid_inst_src)4210 if (arg0_value == ag->codegen->invalid_inst_src)
4211 return arg0_value;4211 return arg0_value;
42124212
...@@ -4215,18 +4215,18 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4215,18 +4215,18 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4215 return ag->codegen->invalid_inst_src;4215 return ag->codegen->invalid_inst_src;
4216 }4216 }
42174217
4218 IrInstSrc *c_include = ir_build_c_include(ag, scope, node, arg0_value);4218 Stage1ZirInst *c_include = ir_build_c_include(ag, scope, node, arg0_value);
4219 return ir_lval_wrap(ag, scope, c_include, lval, result_loc);4219 return ir_lval_wrap(ag, scope, c_include, lval, result_loc);
4220 }4220 }
4221 case BuiltinFnIdCDefine:4221 case BuiltinFnIdCDefine:
4222 {4222 {
4223 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4223 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4224 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4224 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4225 if (arg0_value == ag->codegen->invalid_inst_src)4225 if (arg0_value == ag->codegen->invalid_inst_src)
4226 return arg0_value;4226 return arg0_value;
42274227
4228 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4228 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4229 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4229 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4230 if (arg1_value == ag->codegen->invalid_inst_src)4230 if (arg1_value == ag->codegen->invalid_inst_src)
4231 return arg1_value;4231 return arg1_value;
42324232
...@@ -4235,13 +4235,13 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4235,13 +4235,13 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4235 return ag->codegen->invalid_inst_src;4235 return ag->codegen->invalid_inst_src;
4236 }4236 }
42374237
4238 IrInstSrc *c_define = ir_build_c_define(ag, scope, node, arg0_value, arg1_value);4238 Stage1ZirInst *c_define = ir_build_c_define(ag, scope, node, arg0_value, arg1_value);
4239 return ir_lval_wrap(ag, scope, c_define, lval, result_loc);4239 return ir_lval_wrap(ag, scope, c_define, lval, result_loc);
4240 }4240 }
4241 case BuiltinFnIdCUndef:4241 case BuiltinFnIdCUndef:
4242 {4242 {
4243 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4243 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4244 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4244 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4245 if (arg0_value == ag->codegen->invalid_inst_src)4245 if (arg0_value == ag->codegen->invalid_inst_src)
4246 return arg0_value;4246 return arg0_value;
42474247
...@@ -4250,22 +4250,22 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4250,22 +4250,22 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4250 return ag->codegen->invalid_inst_src;4250 return ag->codegen->invalid_inst_src;
4251 }4251 }
42524252
4253 IrInstSrc *c_undef = ir_build_c_undef(ag, scope, node, arg0_value);4253 Stage1ZirInst *c_undef = ir_build_c_undef(ag, scope, node, arg0_value);
4254 return ir_lval_wrap(ag, scope, c_undef, lval, result_loc);4254 return ir_lval_wrap(ag, scope, c_undef, lval, result_loc);
4255 }4255 }
4256 case BuiltinFnIdCompileErr:4256 case BuiltinFnIdCompileErr:
4257 {4257 {
4258 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4258 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4259 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4259 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4260 if (arg0_value == ag->codegen->invalid_inst_src)4260 if (arg0_value == ag->codegen->invalid_inst_src)
4261 return arg0_value;4261 return arg0_value;
42624262
4263 IrInstSrc *compile_err = ir_build_compile_err(ag, scope, node, arg0_value);4263 Stage1ZirInst *compile_err = ir_build_compile_err(ag, scope, node, arg0_value);
4264 return ir_lval_wrap(ag, scope, compile_err, lval, result_loc);4264 return ir_lval_wrap(ag, scope, compile_err, lval, result_loc);
4265 }4265 }
4266 case BuiltinFnIdCompileLog:4266 case BuiltinFnIdCompileLog:
4267 {4267 {
4268 IrInstSrc **args = heap::c_allocator.allocate<IrInstSrc*>(actual_param_count);4268 Stage1ZirInst **args = heap::c_allocator.allocate<Stage1ZirInst*>(actual_param_count);
42694269
4270 for (size_t i = 0; i < actual_param_count; i += 1) {4270 for (size_t i = 0; i < actual_param_count; i += 1) {
4271 AstNode *arg_node = node->data.fn_call_expr.params.at(i);4271 AstNode *arg_node = node->data.fn_call_expr.params.at(i);
...@@ -4274,63 +4274,63 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4274,63 +4274,63 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4274 return ag->codegen->invalid_inst_src;4274 return ag->codegen->invalid_inst_src;
4275 }4275 }
42764276
4277 IrInstSrc *compile_log = ir_build_compile_log(ag, scope, node, actual_param_count, args);4277 Stage1ZirInst *compile_log = ir_build_compile_log(ag, scope, node, actual_param_count, args);
4278 return ir_lval_wrap(ag, scope, compile_log, lval, result_loc);4278 return ir_lval_wrap(ag, scope, compile_log, lval, result_loc);
4279 }4279 }
4280 case BuiltinFnIdErrName:4280 case BuiltinFnIdErrName:
4281 {4281 {
4282 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4282 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4283 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4283 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4284 if (arg0_value == ag->codegen->invalid_inst_src)4284 if (arg0_value == ag->codegen->invalid_inst_src)
4285 return arg0_value;4285 return arg0_value;
42864286
4287 IrInstSrc *err_name = ir_build_err_name(ag, scope, node, arg0_value);4287 Stage1ZirInst *err_name = ir_build_err_name(ag, scope, node, arg0_value);
4288 return ir_lval_wrap(ag, scope, err_name, lval, result_loc);4288 return ir_lval_wrap(ag, scope, err_name, lval, result_loc);
4289 }4289 }
4290 case BuiltinFnIdEmbedFile:4290 case BuiltinFnIdEmbedFile:
4291 {4291 {
4292 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4292 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4293 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4293 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4294 if (arg0_value == ag->codegen->invalid_inst_src)4294 if (arg0_value == ag->codegen->invalid_inst_src)
4295 return arg0_value;4295 return arg0_value;
42964296
4297 IrInstSrc *embed_file = ir_build_embed_file(ag, scope, node, arg0_value);4297 Stage1ZirInst *embed_file = ir_build_embed_file(ag, scope, node, arg0_value);
4298 return ir_lval_wrap(ag, scope, embed_file, lval, result_loc);4298 return ir_lval_wrap(ag, scope, embed_file, lval, result_loc);
4299 }4299 }
4300 case BuiltinFnIdCmpxchgWeak:4300 case BuiltinFnIdCmpxchgWeak:
4301 case BuiltinFnIdCmpxchgStrong:4301 case BuiltinFnIdCmpxchgStrong:
4302 {4302 {
4303 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4303 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4304 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4304 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4305 if (arg0_value == ag->codegen->invalid_inst_src)4305 if (arg0_value == ag->codegen->invalid_inst_src)
4306 return arg0_value;4306 return arg0_value;
43074307
4308 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4308 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4309 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4309 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4310 if (arg1_value == ag->codegen->invalid_inst_src)4310 if (arg1_value == ag->codegen->invalid_inst_src)
4311 return arg1_value;4311 return arg1_value;
43124312
4313 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);4313 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
4314 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);4314 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
4315 if (arg2_value == ag->codegen->invalid_inst_src)4315 if (arg2_value == ag->codegen->invalid_inst_src)
4316 return arg2_value;4316 return arg2_value;
43174317
4318 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);4318 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);
4319 IrInstSrc *arg3_value = astgen_node(ag, arg3_node, scope);4319 Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, scope);
4320 if (arg3_value == ag->codegen->invalid_inst_src)4320 if (arg3_value == ag->codegen->invalid_inst_src)
4321 return arg3_value;4321 return arg3_value;
43224322
4323 AstNode *arg4_node = node->data.fn_call_expr.params.at(4);4323 AstNode *arg4_node = node->data.fn_call_expr.params.at(4);
4324 IrInstSrc *arg4_value = astgen_node(ag, arg4_node, scope);4324 Stage1ZirInst *arg4_value = astgen_node(ag, arg4_node, scope);
4325 if (arg4_value == ag->codegen->invalid_inst_src)4325 if (arg4_value == ag->codegen->invalid_inst_src)
4326 return arg4_value;4326 return arg4_value;
43274327
4328 AstNode *arg5_node = node->data.fn_call_expr.params.at(5);4328 AstNode *arg5_node = node->data.fn_call_expr.params.at(5);
4329 IrInstSrc *arg5_value = astgen_node(ag, arg5_node, scope);4329 Stage1ZirInst *arg5_value = astgen_node(ag, arg5_node, scope);
4330 if (arg5_value == ag->codegen->invalid_inst_src)4330 if (arg5_value == ag->codegen->invalid_inst_src)
4331 return arg5_value;4331 return arg5_value;
43324332
4333 IrInstSrc *cmpxchg = ir_build_cmpxchg_src(ag, scope, node, arg0_value, arg1_value,4333 Stage1ZirInst *cmpxchg = ir_build_cmpxchg_src(ag, scope, node, arg0_value, arg1_value,
4334 arg2_value, arg3_value, arg4_value, arg5_value, (builtin_fn->id == BuiltinFnIdCmpxchgWeak),4334 arg2_value, arg3_value, arg4_value, arg5_value, (builtin_fn->id == BuiltinFnIdCmpxchgWeak),
4335 result_loc);4335 result_loc);
4336 return ir_lval_wrap(ag, scope, cmpxchg, lval, result_loc);4336 return ir_lval_wrap(ag, scope, cmpxchg, lval, result_loc);
...@@ -4338,101 +4338,101 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4338,101 +4338,101 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4338 case BuiltinFnIdFence:4338 case BuiltinFnIdFence:
4339 {4339 {
4340 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4340 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4341 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4341 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4342 if (arg0_value == ag->codegen->invalid_inst_src)4342 if (arg0_value == ag->codegen->invalid_inst_src)
4343 return arg0_value;4343 return arg0_value;
43444344
4345 IrInstSrc *fence = ir_build_fence(ag, scope, node, arg0_value);4345 Stage1ZirInst *fence = ir_build_fence(ag, scope, node, arg0_value);
4346 return ir_lval_wrap(ag, scope, fence, lval, result_loc);4346 return ir_lval_wrap(ag, scope, fence, lval, result_loc);
4347 }4347 }
4348 case BuiltinFnIdReduce:4348 case BuiltinFnIdReduce:
4349 {4349 {
4350 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4350 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4351 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4351 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4352 if (arg0_value == ag->codegen->invalid_inst_src)4352 if (arg0_value == ag->codegen->invalid_inst_src)
4353 return arg0_value;4353 return arg0_value;
43544354
4355 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4355 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4356 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4356 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4357 if (arg1_value == ag->codegen->invalid_inst_src)4357 if (arg1_value == ag->codegen->invalid_inst_src)
4358 return arg1_value;4358 return arg1_value;
43594359
4360 IrInstSrc *reduce = ir_build_reduce(ag, scope, node, arg0_value, arg1_value);4360 Stage1ZirInst *reduce = ir_build_reduce(ag, scope, node, arg0_value, arg1_value);
4361 return ir_lval_wrap(ag, scope, reduce, lval, result_loc);4361 return ir_lval_wrap(ag, scope, reduce, lval, result_loc);
4362 }4362 }
4363 case BuiltinFnIdDivExact:4363 case BuiltinFnIdDivExact:
4364 {4364 {
4365 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4365 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4366 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4366 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4367 if (arg0_value == ag->codegen->invalid_inst_src)4367 if (arg0_value == ag->codegen->invalid_inst_src)
4368 return arg0_value;4368 return arg0_value;
43694369
4370 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4370 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4371 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4371 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4372 if (arg1_value == ag->codegen->invalid_inst_src)4372 if (arg1_value == ag->codegen->invalid_inst_src)
4373 return arg1_value;4373 return arg1_value;
43744374
4375 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivExact, arg0_value, arg1_value, true);4375 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivExact, arg0_value, arg1_value, true);
4376 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);4376 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
4377 }4377 }
4378 case BuiltinFnIdDivTrunc:4378 case BuiltinFnIdDivTrunc:
4379 {4379 {
4380 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4380 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4381 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4381 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4382 if (arg0_value == ag->codegen->invalid_inst_src)4382 if (arg0_value == ag->codegen->invalid_inst_src)
4383 return arg0_value;4383 return arg0_value;
43844384
4385 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4385 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4386 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4386 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4387 if (arg1_value == ag->codegen->invalid_inst_src)4387 if (arg1_value == ag->codegen->invalid_inst_src)
4388 return arg1_value;4388 return arg1_value;
43894389
4390 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivTrunc, arg0_value, arg1_value, true);4390 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivTrunc, arg0_value, arg1_value, true);
4391 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);4391 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
4392 }4392 }
4393 case BuiltinFnIdDivFloor:4393 case BuiltinFnIdDivFloor:
4394 {4394 {
4395 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4395 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4396 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4396 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4397 if (arg0_value == ag->codegen->invalid_inst_src)4397 if (arg0_value == ag->codegen->invalid_inst_src)
4398 return arg0_value;4398 return arg0_value;
43994399
4400 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4400 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4401 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4401 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4402 if (arg1_value == ag->codegen->invalid_inst_src)4402 if (arg1_value == ag->codegen->invalid_inst_src)
4403 return arg1_value;4403 return arg1_value;
44044404
4405 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivFloor, arg0_value, arg1_value, true);4405 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivFloor, arg0_value, arg1_value, true);
4406 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);4406 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
4407 }4407 }
4408 case BuiltinFnIdRem:4408 case BuiltinFnIdRem:
4409 {4409 {
4410 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4410 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4411 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4411 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4412 if (arg0_value == ag->codegen->invalid_inst_src)4412 if (arg0_value == ag->codegen->invalid_inst_src)
4413 return arg0_value;4413 return arg0_value;
44144414
4415 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4415 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4416 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4416 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4417 if (arg1_value == ag->codegen->invalid_inst_src)4417 if (arg1_value == ag->codegen->invalid_inst_src)
4418 return arg1_value;4418 return arg1_value;
44194419
4420 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemRem, arg0_value, arg1_value, true);4420 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemRem, arg0_value, arg1_value, true);
4421 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);4421 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
4422 }4422 }
4423 case BuiltinFnIdMod:4423 case BuiltinFnIdMod:
4424 {4424 {
4425 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4425 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4426 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4426 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4427 if (arg0_value == ag->codegen->invalid_inst_src)4427 if (arg0_value == ag->codegen->invalid_inst_src)
4428 return arg0_value;4428 return arg0_value;
44294429
4430 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4430 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4431 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4431 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4432 if (arg1_value == ag->codegen->invalid_inst_src)4432 if (arg1_value == ag->codegen->invalid_inst_src)
4433 return arg1_value;4433 return arg1_value;
44344434
4435 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemMod, arg0_value, arg1_value, true);4435 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemMod, arg0_value, arg1_value, true);
4436 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);4436 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
4437 }4437 }
4438 case BuiltinFnIdSqrt:4438 case BuiltinFnIdSqrt:
...@@ -4451,146 +4451,146 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4451,146 +4451,146 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4451 case BuiltinFnIdRound:4451 case BuiltinFnIdRound:
4452 {4452 {
4453 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4453 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4454 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4454 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4455 if (arg0_value == ag->codegen->invalid_inst_src)4455 if (arg0_value == ag->codegen->invalid_inst_src)
4456 return arg0_value;4456 return arg0_value;
44574457
4458 IrInstSrc *inst = ir_build_float_op_src(ag, scope, node, arg0_value, builtin_fn->id);4458 Stage1ZirInst *inst = ir_build_float_op_src(ag, scope, node, arg0_value, builtin_fn->id);
4459 return ir_lval_wrap(ag, scope, inst, lval, result_loc);4459 return ir_lval_wrap(ag, scope, inst, lval, result_loc);
4460 }4460 }
4461 case BuiltinFnIdTruncate:4461 case BuiltinFnIdTruncate:
4462 {4462 {
4463 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4463 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4464 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4464 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4465 if (arg0_value == ag->codegen->invalid_inst_src)4465 if (arg0_value == ag->codegen->invalid_inst_src)
4466 return arg0_value;4466 return arg0_value;
44674467
4468 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4468 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4469 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4469 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4470 if (arg1_value == ag->codegen->invalid_inst_src)4470 if (arg1_value == ag->codegen->invalid_inst_src)
4471 return arg1_value;4471 return arg1_value;
44724472
4473 IrInstSrc *truncate = ir_build_truncate(ag, scope, node, arg0_value, arg1_value);4473 Stage1ZirInst *truncate = ir_build_truncate(ag, scope, node, arg0_value, arg1_value);
4474 return ir_lval_wrap(ag, scope, truncate, lval, result_loc);4474 return ir_lval_wrap(ag, scope, truncate, lval, result_loc);
4475 }4475 }
4476 case BuiltinFnIdIntCast:4476 case BuiltinFnIdIntCast:
4477 {4477 {
4478 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4478 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4479 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4479 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4480 if (arg0_value == ag->codegen->invalid_inst_src)4480 if (arg0_value == ag->codegen->invalid_inst_src)
4481 return arg0_value;4481 return arg0_value;
44824482
4483 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4483 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4484 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4484 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4485 if (arg1_value == ag->codegen->invalid_inst_src)4485 if (arg1_value == ag->codegen->invalid_inst_src)
4486 return arg1_value;4486 return arg1_value;
44874487
4488 IrInstSrc *result = ir_build_int_cast(ag, scope, node, arg0_value, arg1_value);4488 Stage1ZirInst *result = ir_build_int_cast(ag, scope, node, arg0_value, arg1_value);
4489 return ir_lval_wrap(ag, scope, result, lval, result_loc);4489 return ir_lval_wrap(ag, scope, result, lval, result_loc);
4490 }4490 }
4491 case BuiltinFnIdFloatCast:4491 case BuiltinFnIdFloatCast:
4492 {4492 {
4493 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4493 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4494 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4494 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4495 if (arg0_value == ag->codegen->invalid_inst_src)4495 if (arg0_value == ag->codegen->invalid_inst_src)
4496 return arg0_value;4496 return arg0_value;
44974497
4498 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4498 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4499 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4499 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4500 if (arg1_value == ag->codegen->invalid_inst_src)4500 if (arg1_value == ag->codegen->invalid_inst_src)
4501 return arg1_value;4501 return arg1_value;
45024502
4503 IrInstSrc *result = ir_build_float_cast(ag, scope, node, arg0_value, arg1_value);4503 Stage1ZirInst *result = ir_build_float_cast(ag, scope, node, arg0_value, arg1_value);
4504 return ir_lval_wrap(ag, scope, result, lval, result_loc);4504 return ir_lval_wrap(ag, scope, result, lval, result_loc);
4505 }4505 }
4506 case BuiltinFnIdErrSetCast:4506 case BuiltinFnIdErrSetCast:
4507 {4507 {
4508 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4508 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4509 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4509 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4510 if (arg0_value == ag->codegen->invalid_inst_src)4510 if (arg0_value == ag->codegen->invalid_inst_src)
4511 return arg0_value;4511 return arg0_value;
45124512
4513 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4513 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4514 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4514 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4515 if (arg1_value == ag->codegen->invalid_inst_src)4515 if (arg1_value == ag->codegen->invalid_inst_src)
4516 return arg1_value;4516 return arg1_value;
45174517
4518 IrInstSrc *result = ir_build_err_set_cast(ag, scope, node, arg0_value, arg1_value);4518 Stage1ZirInst *result = ir_build_err_set_cast(ag, scope, node, arg0_value, arg1_value);
4519 return ir_lval_wrap(ag, scope, result, lval, result_loc);4519 return ir_lval_wrap(ag, scope, result, lval, result_loc);
4520 }4520 }
4521 case BuiltinFnIdIntToFloat:4521 case BuiltinFnIdIntToFloat:
4522 {4522 {
4523 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4523 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4524 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4524 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4525 if (arg0_value == ag->codegen->invalid_inst_src)4525 if (arg0_value == ag->codegen->invalid_inst_src)
4526 return arg0_value;4526 return arg0_value;
45274527
4528 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4528 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4529 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4529 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4530 if (arg1_value == ag->codegen->invalid_inst_src)4530 if (arg1_value == ag->codegen->invalid_inst_src)
4531 return arg1_value;4531 return arg1_value;
45324532
4533 IrInstSrc *result = ir_build_int_to_float(ag, scope, node, arg0_value, arg1_value);4533 Stage1ZirInst *result = ir_build_int_to_float(ag, scope, node, arg0_value, arg1_value);
4534 return ir_lval_wrap(ag, scope, result, lval, result_loc);4534 return ir_lval_wrap(ag, scope, result, lval, result_loc);
4535 }4535 }
4536 case BuiltinFnIdFloatToInt:4536 case BuiltinFnIdFloatToInt:
4537 {4537 {
4538 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4538 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4539 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4539 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4540 if (arg0_value == ag->codegen->invalid_inst_src)4540 if (arg0_value == ag->codegen->invalid_inst_src)
4541 return arg0_value;4541 return arg0_value;
45424542
4543 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4543 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4544 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4544 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4545 if (arg1_value == ag->codegen->invalid_inst_src)4545 if (arg1_value == ag->codegen->invalid_inst_src)
4546 return arg1_value;4546 return arg1_value;
45474547
4548 IrInstSrc *result = ir_build_float_to_int(ag, scope, node, arg0_value, arg1_value);4548 Stage1ZirInst *result = ir_build_float_to_int(ag, scope, node, arg0_value, arg1_value);
4549 return ir_lval_wrap(ag, scope, result, lval, result_loc);4549 return ir_lval_wrap(ag, scope, result, lval, result_loc);
4550 }4550 }
4551 case BuiltinFnIdErrToInt:4551 case BuiltinFnIdErrToInt:
4552 {4552 {
4553 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4553 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4554 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4554 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4555 if (arg0_value == ag->codegen->invalid_inst_src)4555 if (arg0_value == ag->codegen->invalid_inst_src)
4556 return arg0_value;4556 return arg0_value;
45574557
4558 IrInstSrc *result = ir_build_err_to_int_src(ag, scope, node, arg0_value);4558 Stage1ZirInst *result = ir_build_err_to_int_src(ag, scope, node, arg0_value);
4559 return ir_lval_wrap(ag, scope, result, lval, result_loc);4559 return ir_lval_wrap(ag, scope, result, lval, result_loc);
4560 }4560 }
4561 case BuiltinFnIdIntToErr:4561 case BuiltinFnIdIntToErr:
4562 {4562 {
4563 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4563 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4564 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4564 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4565 if (arg0_value == ag->codegen->invalid_inst_src)4565 if (arg0_value == ag->codegen->invalid_inst_src)
4566 return arg0_value;4566 return arg0_value;
45674567
4568 IrInstSrc *result = ir_build_int_to_err_src(ag, scope, node, arg0_value);4568 Stage1ZirInst *result = ir_build_int_to_err_src(ag, scope, node, arg0_value);
4569 return ir_lval_wrap(ag, scope, result, lval, result_loc);4569 return ir_lval_wrap(ag, scope, result, lval, result_loc);
4570 }4570 }
4571 case BuiltinFnIdBoolToInt:4571 case BuiltinFnIdBoolToInt:
4572 {4572 {
4573 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4573 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4574 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4574 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4575 if (arg0_value == ag->codegen->invalid_inst_src)4575 if (arg0_value == ag->codegen->invalid_inst_src)
4576 return arg0_value;4576 return arg0_value;
45774577
4578 IrInstSrc *result = ir_build_bool_to_int(ag, scope, node, arg0_value);4578 Stage1ZirInst *result = ir_build_bool_to_int(ag, scope, node, arg0_value);
4579 return ir_lval_wrap(ag, scope, result, lval, result_loc);4579 return ir_lval_wrap(ag, scope, result, lval, result_loc);
4580 }4580 }
4581 case BuiltinFnIdVectorType:4581 case BuiltinFnIdVectorType:
4582 {4582 {
4583 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4583 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4584 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4584 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4585 if (arg0_value == ag->codegen->invalid_inst_src)4585 if (arg0_value == ag->codegen->invalid_inst_src)
4586 return arg0_value;4586 return arg0_value;
45874587
4588 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4588 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4589 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4589 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4590 if (arg1_value == ag->codegen->invalid_inst_src)4590 if (arg1_value == ag->codegen->invalid_inst_src)
4591 return arg1_value;4591 return arg1_value;
45924592
4593 IrInstSrc *vector_type = ir_build_vector_type(ag, scope, node, arg0_value, arg1_value);4593 Stage1ZirInst *vector_type = ir_build_vector_type(ag, scope, node, arg0_value, arg1_value);
4594 return ir_lval_wrap(ag, scope, vector_type, lval, result_loc);4594 return ir_lval_wrap(ag, scope, vector_type, lval, result_loc);
4595 }4595 }
4596 case BuiltinFnIdShuffle:4596 case BuiltinFnIdShuffle:
...@@ -4599,164 +4599,164 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4599,164 +4599,164 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4599 Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope);4599 Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope);
46004600
4601 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4601 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4602 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, comptime_scope);4602 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, comptime_scope);
4603 if (arg0_value == ag->codegen->invalid_inst_src)4603 if (arg0_value == ag->codegen->invalid_inst_src)
4604 return arg0_value;4604 return arg0_value;
46054605
4606 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4606 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4607 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4607 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4608 if (arg1_value == ag->codegen->invalid_inst_src)4608 if (arg1_value == ag->codegen->invalid_inst_src)
4609 return arg1_value;4609 return arg1_value;
46104610
4611 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);4611 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
4612 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);4612 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
4613 if (arg2_value == ag->codegen->invalid_inst_src)4613 if (arg2_value == ag->codegen->invalid_inst_src)
4614 return arg2_value;4614 return arg2_value;
46154615
4616 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);4616 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);
4617 IrInstSrc *arg3_value = astgen_node(ag, arg3_node, comptime_scope);4617 Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, comptime_scope);
4618 if (arg3_value == ag->codegen->invalid_inst_src)4618 if (arg3_value == ag->codegen->invalid_inst_src)
4619 return arg3_value;4619 return arg3_value;
46204620
4621 IrInstSrc *shuffle_vector = ir_build_shuffle_vector(ag, scope, node,4621 Stage1ZirInst *shuffle_vector = ir_build_shuffle_vector(ag, scope, node,
4622 arg0_value, arg1_value, arg2_value, arg3_value);4622 arg0_value, arg1_value, arg2_value, arg3_value);
4623 return ir_lval_wrap(ag, scope, shuffle_vector, lval, result_loc);4623 return ir_lval_wrap(ag, scope, shuffle_vector, lval, result_loc);
4624 }4624 }
4625 case BuiltinFnIdSplat:4625 case BuiltinFnIdSplat:
4626 {4626 {
4627 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4627 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4628 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4628 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4629 if (arg0_value == ag->codegen->invalid_inst_src)4629 if (arg0_value == ag->codegen->invalid_inst_src)
4630 return arg0_value;4630 return arg0_value;
46314631
4632 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4632 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4633 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4633 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4634 if (arg1_value == ag->codegen->invalid_inst_src)4634 if (arg1_value == ag->codegen->invalid_inst_src)
4635 return arg1_value;4635 return arg1_value;
46364636
4637 IrInstSrc *splat = ir_build_splat_src(ag, scope, node,4637 Stage1ZirInst *splat = ir_build_splat_src(ag, scope, node,
4638 arg0_value, arg1_value);4638 arg0_value, arg1_value);
4639 return ir_lval_wrap(ag, scope, splat, lval, result_loc);4639 return ir_lval_wrap(ag, scope, splat, lval, result_loc);
4640 }4640 }
4641 case BuiltinFnIdMemcpy:4641 case BuiltinFnIdMemcpy:
4642 {4642 {
4643 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4643 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4644 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4644 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4645 if (arg0_value == ag->codegen->invalid_inst_src)4645 if (arg0_value == ag->codegen->invalid_inst_src)
4646 return arg0_value;4646 return arg0_value;
46474647
4648 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4648 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4649 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4649 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4650 if (arg1_value == ag->codegen->invalid_inst_src)4650 if (arg1_value == ag->codegen->invalid_inst_src)
4651 return arg1_value;4651 return arg1_value;
46524652
4653 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);4653 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
4654 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);4654 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
4655 if (arg2_value == ag->codegen->invalid_inst_src)4655 if (arg2_value == ag->codegen->invalid_inst_src)
4656 return arg2_value;4656 return arg2_value;
46574657
4658 IrInstSrc *ir_memcpy = ir_build_memcpy_src(ag, scope, node, arg0_value, arg1_value, arg2_value);4658 Stage1ZirInst *ir_memcpy = ir_build_memcpy_src(ag, scope, node, arg0_value, arg1_value, arg2_value);
4659 return ir_lval_wrap(ag, scope, ir_memcpy, lval, result_loc);4659 return ir_lval_wrap(ag, scope, ir_memcpy, lval, result_loc);
4660 }4660 }
4661 case BuiltinFnIdMemset:4661 case BuiltinFnIdMemset:
4662 {4662 {
4663 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4663 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4664 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4664 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4665 if (arg0_value == ag->codegen->invalid_inst_src)4665 if (arg0_value == ag->codegen->invalid_inst_src)
4666 return arg0_value;4666 return arg0_value;
46674667
4668 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4668 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4669 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4669 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4670 if (arg1_value == ag->codegen->invalid_inst_src)4670 if (arg1_value == ag->codegen->invalid_inst_src)
4671 return arg1_value;4671 return arg1_value;
46724672
4673 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);4673 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
4674 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);4674 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
4675 if (arg2_value == ag->codegen->invalid_inst_src)4675 if (arg2_value == ag->codegen->invalid_inst_src)
4676 return arg2_value;4676 return arg2_value;
46774677
4678 IrInstSrc *ir_memset = ir_build_memset_src(ag, scope, node, arg0_value, arg1_value, arg2_value);4678 Stage1ZirInst *ir_memset = ir_build_memset_src(ag, scope, node, arg0_value, arg1_value, arg2_value);
4679 return ir_lval_wrap(ag, scope, ir_memset, lval, result_loc);4679 return ir_lval_wrap(ag, scope, ir_memset, lval, result_loc);
4680 }4680 }
4681 case BuiltinFnIdWasmMemorySize:4681 case BuiltinFnIdWasmMemorySize:
4682 {4682 {
4683 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4683 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4684 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4684 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4685 if (arg0_value == ag->codegen->invalid_inst_src)4685 if (arg0_value == ag->codegen->invalid_inst_src)
4686 return arg0_value;4686 return arg0_value;
46874687
4688 IrInstSrc *ir_wasm_memory_size = ir_build_wasm_memory_size_src(ag, scope, node, arg0_value);4688 Stage1ZirInst *ir_wasm_memory_size = ir_build_wasm_memory_size_src(ag, scope, node, arg0_value);
4689 return ir_lval_wrap(ag, scope, ir_wasm_memory_size, lval, result_loc);4689 return ir_lval_wrap(ag, scope, ir_wasm_memory_size, lval, result_loc);
4690 }4690 }
4691 case BuiltinFnIdWasmMemoryGrow:4691 case BuiltinFnIdWasmMemoryGrow:
4692 {4692 {
4693 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4693 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4694 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4694 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4695 if (arg0_value == ag->codegen->invalid_inst_src)4695 if (arg0_value == ag->codegen->invalid_inst_src)
4696 return arg0_value;4696 return arg0_value;
46974697
4698 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4698 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4699 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4699 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4700 if (arg1_value == ag->codegen->invalid_inst_src)4700 if (arg1_value == ag->codegen->invalid_inst_src)
4701 return arg1_value;4701 return arg1_value;
47024702
4703 IrInstSrc *ir_wasm_memory_grow = ir_build_wasm_memory_grow_src(ag, scope, node, arg0_value, arg1_value);4703 Stage1ZirInst *ir_wasm_memory_grow = ir_build_wasm_memory_grow_src(ag, scope, node, arg0_value, arg1_value);
4704 return ir_lval_wrap(ag, scope, ir_wasm_memory_grow, lval, result_loc);4704 return ir_lval_wrap(ag, scope, ir_wasm_memory_grow, lval, result_loc);
4705 }4705 }
4706 case BuiltinFnIdField:4706 case BuiltinFnIdField:
4707 {4707 {
4708 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4708 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4709 IrInstSrc *arg0_value = astgen_node_extra(ag, arg0_node, scope, LValPtr, nullptr);4709 Stage1ZirInst *arg0_value = astgen_node_extra(ag, arg0_node, scope, LValPtr, nullptr);
4710 if (arg0_value == ag->codegen->invalid_inst_src)4710 if (arg0_value == ag->codegen->invalid_inst_src)
4711 return arg0_value;4711 return arg0_value;
47124712
4713 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4713 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4714 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4714 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4715 if (arg1_value == ag->codegen->invalid_inst_src)4715 if (arg1_value == ag->codegen->invalid_inst_src)
4716 return arg1_value;4716 return arg1_value;
47174717
4718 IrInstSrc *ptr_instruction = ir_build_field_ptr_instruction(ag, scope, node,4718 Stage1ZirInst *ptr_instruction = ir_build_field_ptr_instruction(ag, scope, node,
4719 arg0_value, arg1_value, false);4719 arg0_value, arg1_value, false);
47204720
4721 if (lval == LValPtr || lval == LValAssign)4721 if (lval == LValPtr || lval == LValAssign)
4722 return ptr_instruction;4722 return ptr_instruction;
47234723
4724 IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);4724 Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);
4725 return ir_expr_wrap(ag, scope, load_ptr, result_loc);4725 return ir_expr_wrap(ag, scope, load_ptr, result_loc);
4726 }4726 }
4727 case BuiltinFnIdHasField:4727 case BuiltinFnIdHasField:
4728 {4728 {
4729 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4729 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4730 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4730 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4731 if (arg0_value == ag->codegen->invalid_inst_src)4731 if (arg0_value == ag->codegen->invalid_inst_src)
4732 return arg0_value;4732 return arg0_value;
47334733
4734 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4734 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4735 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4735 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4736 if (arg1_value == ag->codegen->invalid_inst_src)4736 if (arg1_value == ag->codegen->invalid_inst_src)
4737 return arg1_value;4737 return arg1_value;
47384738
4739 IrInstSrc *type_info = ir_build_has_field(ag, scope, node, arg0_value, arg1_value);4739 Stage1ZirInst *type_info = ir_build_has_field(ag, scope, node, arg0_value, arg1_value);
4740 return ir_lval_wrap(ag, scope, type_info, lval, result_loc);4740 return ir_lval_wrap(ag, scope, type_info, lval, result_loc);
4741 }4741 }
4742 case BuiltinFnIdTypeInfo:4742 case BuiltinFnIdTypeInfo:
4743 {4743 {
4744 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4744 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4745 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4745 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4746 if (arg0_value == ag->codegen->invalid_inst_src)4746 if (arg0_value == ag->codegen->invalid_inst_src)
4747 return arg0_value;4747 return arg0_value;
47484748
4749 IrInstSrc *type_info = ir_build_type_info(ag, scope, node, arg0_value);4749 Stage1ZirInst *type_info = ir_build_type_info(ag, scope, node, arg0_value);
4750 return ir_lval_wrap(ag, scope, type_info, lval, result_loc);4750 return ir_lval_wrap(ag, scope, type_info, lval, result_loc);
4751 }4751 }
4752 case BuiltinFnIdType:4752 case BuiltinFnIdType:
4753 {4753 {
4754 AstNode *arg_node = node->data.fn_call_expr.params.at(0);4754 AstNode *arg_node = node->data.fn_call_expr.params.at(0);
4755 IrInstSrc *arg = astgen_node(ag, arg_node, scope);4755 Stage1ZirInst *arg = astgen_node(ag, arg_node, scope);
4756 if (arg == ag->codegen->invalid_inst_src)4756 if (arg == ag->codegen->invalid_inst_src)
4757 return arg;4757 return arg;
47584758
4759 IrInstSrc *type = ir_build_type(ag, scope, node, arg);4759 Stage1ZirInst *type = ir_build_type(ag, scope, node, arg);
4760 return ir_lval_wrap(ag, scope, type, lval, result_loc);4760 return ir_lval_wrap(ag, scope, type, lval, result_loc);
4761 }4761 }
4762 case BuiltinFnIdBreakpoint:4762 case BuiltinFnIdBreakpoint:
...@@ -4774,30 +4774,30 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4774,30 +4774,30 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4774 return ir_lval_wrap(ag, scope, ir_build_handle_src(ag, scope, node), lval, result_loc);4774 return ir_lval_wrap(ag, scope, ir_build_handle_src(ag, scope, node), lval, result_loc);
4775 case BuiltinFnIdFrameType: {4775 case BuiltinFnIdFrameType: {
4776 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4776 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4777 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4777 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4778 if (arg0_value == ag->codegen->invalid_inst_src)4778 if (arg0_value == ag->codegen->invalid_inst_src)
4779 return arg0_value;4779 return arg0_value;
47804780
4781 IrInstSrc *frame_type = ir_build_frame_type(ag, scope, node, arg0_value);4781 Stage1ZirInst *frame_type = ir_build_frame_type(ag, scope, node, arg0_value);
4782 return ir_lval_wrap(ag, scope, frame_type, lval, result_loc);4782 return ir_lval_wrap(ag, scope, frame_type, lval, result_loc);
4783 }4783 }
4784 case BuiltinFnIdFrameSize: {4784 case BuiltinFnIdFrameSize: {
4785 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4785 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4786 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4786 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4787 if (arg0_value == ag->codegen->invalid_inst_src)4787 if (arg0_value == ag->codegen->invalid_inst_src)
4788 return arg0_value;4788 return arg0_value;
47894789
4790 IrInstSrc *frame_size = ir_build_frame_size_src(ag, scope, node, arg0_value);4790 Stage1ZirInst *frame_size = ir_build_frame_size_src(ag, scope, node, arg0_value);
4791 return ir_lval_wrap(ag, scope, frame_size, lval, result_loc);4791 return ir_lval_wrap(ag, scope, frame_size, lval, result_loc);
4792 }4792 }
4793 case BuiltinFnIdAlignOf:4793 case BuiltinFnIdAlignOf:
4794 {4794 {
4795 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4795 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4796 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4796 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4797 if (arg0_value == ag->codegen->invalid_inst_src)4797 if (arg0_value == ag->codegen->invalid_inst_src)
4798 return arg0_value;4798 return arg0_value;
47994799
4800 IrInstSrc *align_of = ir_build_align_of(ag, scope, node, arg0_value);4800 Stage1ZirInst *align_of = ir_build_align_of(ag, scope, node, arg0_value);
4801 return ir_lval_wrap(ag, scope, align_of, lval, result_loc);4801 return ir_lval_wrap(ag, scope, align_of, lval, result_loc);
4802 }4802 }
4803 case BuiltinFnIdAddWithOverflow:4803 case BuiltinFnIdAddWithOverflow:
...@@ -4813,42 +4813,42 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4813,42 +4813,42 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4813 case BuiltinFnIdTypeName:4813 case BuiltinFnIdTypeName:
4814 {4814 {
4815 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4815 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4816 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4816 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4817 if (arg0_value == ag->codegen->invalid_inst_src)4817 if (arg0_value == ag->codegen->invalid_inst_src)
4818 return arg0_value;4818 return arg0_value;
48194819
4820 IrInstSrc *type_name = ir_build_type_name(ag, scope, node, arg0_value);4820 Stage1ZirInst *type_name = ir_build_type_name(ag, scope, node, arg0_value);
4821 return ir_lval_wrap(ag, scope, type_name, lval, result_loc);4821 return ir_lval_wrap(ag, scope, type_name, lval, result_loc);
4822 }4822 }
4823 case BuiltinFnIdPanic:4823 case BuiltinFnIdPanic:
4824 {4824 {
4825 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4825 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4826 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4826 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4827 if (arg0_value == ag->codegen->invalid_inst_src)4827 if (arg0_value == ag->codegen->invalid_inst_src)
4828 return arg0_value;4828 return arg0_value;
48294829
4830 IrInstSrc *panic = ir_build_panic_src(ag, scope, node, arg0_value);4830 Stage1ZirInst *panic = ir_build_panic_src(ag, scope, node, arg0_value);
4831 return ir_lval_wrap(ag, scope, panic, lval, result_loc);4831 return ir_lval_wrap(ag, scope, panic, lval, result_loc);
4832 }4832 }
4833 case BuiltinFnIdPtrCast:4833 case BuiltinFnIdPtrCast:
4834 {4834 {
4835 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4835 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4836 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4836 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4837 if (arg0_value == ag->codegen->invalid_inst_src)4837 if (arg0_value == ag->codegen->invalid_inst_src)
4838 return arg0_value;4838 return arg0_value;
48394839
4840 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4840 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4841 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4841 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4842 if (arg1_value == ag->codegen->invalid_inst_src)4842 if (arg1_value == ag->codegen->invalid_inst_src)
4843 return arg1_value;4843 return arg1_value;
48444844
4845 IrInstSrc *ptr_cast = ir_build_ptr_cast_src(ag, scope, node, arg0_value, arg1_value, true);4845 Stage1ZirInst *ptr_cast = ir_build_ptr_cast_src(ag, scope, node, arg0_value, arg1_value, true);
4846 return ir_lval_wrap(ag, scope, ptr_cast, lval, result_loc);4846 return ir_lval_wrap(ag, scope, ptr_cast, lval, result_loc);
4847 }4847 }
4848 case BuiltinFnIdBitCast:4848 case BuiltinFnIdBitCast:
4849 {4849 {
4850 AstNode *dest_type_node = node->data.fn_call_expr.params.at(0);4850 AstNode *dest_type_node = node->data.fn_call_expr.params.at(0);
4851 IrInstSrc *dest_type = astgen_node(ag, dest_type_node, scope);4851 Stage1ZirInst *dest_type = astgen_node(ag, dest_type_node, scope);
4852 if (dest_type == ag->codegen->invalid_inst_src)4852 if (dest_type == ag->codegen->invalid_inst_src)
4853 return dest_type;4853 return dest_type;
48544854
...@@ -4862,130 +4862,130 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -4862,130 +4862,130 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
4862 ir_build_reset_result(ag, scope, node, &result_loc_bit_cast->base);4862 ir_build_reset_result(ag, scope, node, &result_loc_bit_cast->base);
48634863
4864 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4864 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4865 IrInstSrc *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone,4865 Stage1ZirInst *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone,
4866 &result_loc_bit_cast->base);4866 &result_loc_bit_cast->base);
4867 if (arg1_value == ag->codegen->invalid_inst_src)4867 if (arg1_value == ag->codegen->invalid_inst_src)
4868 return arg1_value;4868 return arg1_value;
48694869
4870 IrInstSrc *bitcast = ir_build_bit_cast_src(ag, scope, arg1_node, arg1_value, result_loc_bit_cast);4870 Stage1ZirInst *bitcast = ir_build_bit_cast_src(ag, scope, arg1_node, arg1_value, result_loc_bit_cast);
4871 return ir_lval_wrap(ag, scope, bitcast, lval, result_loc);4871 return ir_lval_wrap(ag, scope, bitcast, lval, result_loc);
4872 }4872 }
4873 case BuiltinFnIdAs:4873 case BuiltinFnIdAs:
4874 {4874 {
4875 AstNode *dest_type_node = node->data.fn_call_expr.params.at(0);4875 AstNode *dest_type_node = node->data.fn_call_expr.params.at(0);
4876 IrInstSrc *dest_type = astgen_node(ag, dest_type_node, scope);4876 Stage1ZirInst *dest_type = astgen_node(ag, dest_type_node, scope);
4877 if (dest_type == ag->codegen->invalid_inst_src)4877 if (dest_type == ag->codegen->invalid_inst_src)
4878 return dest_type;4878 return dest_type;
48794879
4880 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, dest_type, result_loc);4880 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, dest_type, result_loc);
48814881
4882 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4882 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4883 IrInstSrc *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone,4883 Stage1ZirInst *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone,
4884 &result_loc_cast->base);4884 &result_loc_cast->base);
4885 if (arg1_value == ag->codegen->invalid_inst_src)4885 if (arg1_value == ag->codegen->invalid_inst_src)
4886 return arg1_value;4886 return arg1_value;
48874887
4888 IrInstSrc *result = ir_build_implicit_cast(ag, scope, node, arg1_value, result_loc_cast);4888 Stage1ZirInst *result = ir_build_implicit_cast(ag, scope, node, arg1_value, result_loc_cast);
4889 return ir_lval_wrap(ag, scope, result, lval, result_loc);4889 return ir_lval_wrap(ag, scope, result, lval, result_loc);
4890 }4890 }
4891 case BuiltinFnIdIntToPtr:4891 case BuiltinFnIdIntToPtr:
4892 {4892 {
4893 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4893 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4894 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4894 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4895 if (arg0_value == ag->codegen->invalid_inst_src)4895 if (arg0_value == ag->codegen->invalid_inst_src)
4896 return arg0_value;4896 return arg0_value;
48974897
4898 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4898 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4899 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4899 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4900 if (arg1_value == ag->codegen->invalid_inst_src)4900 if (arg1_value == ag->codegen->invalid_inst_src)
4901 return arg1_value;4901 return arg1_value;
49024902
4903 IrInstSrc *int_to_ptr = ir_build_int_to_ptr_src(ag, scope, node, arg0_value, arg1_value);4903 Stage1ZirInst *int_to_ptr = ir_build_int_to_ptr_src(ag, scope, node, arg0_value, arg1_value);
4904 return ir_lval_wrap(ag, scope, int_to_ptr, lval, result_loc);4904 return ir_lval_wrap(ag, scope, int_to_ptr, lval, result_loc);
4905 }4905 }
4906 case BuiltinFnIdPtrToInt:4906 case BuiltinFnIdPtrToInt:
4907 {4907 {
4908 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4908 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4909 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4909 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4910 if (arg0_value == ag->codegen->invalid_inst_src)4910 if (arg0_value == ag->codegen->invalid_inst_src)
4911 return arg0_value;4911 return arg0_value;
49124912
4913 IrInstSrc *ptr_to_int = ir_build_ptr_to_int_src(ag, scope, node, arg0_value);4913 Stage1ZirInst *ptr_to_int = ir_build_ptr_to_int_src(ag, scope, node, arg0_value);
4914 return ir_lval_wrap(ag, scope, ptr_to_int, lval, result_loc);4914 return ir_lval_wrap(ag, scope, ptr_to_int, lval, result_loc);
4915 }4915 }
4916 case BuiltinFnIdTagName:4916 case BuiltinFnIdTagName:
4917 {4917 {
4918 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4918 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4919 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4919 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4920 if (arg0_value == ag->codegen->invalid_inst_src)4920 if (arg0_value == ag->codegen->invalid_inst_src)
4921 return arg0_value;4921 return arg0_value;
49224922
4923 IrInstSrc *tag_name = ir_build_tag_name_src(ag, scope, node, arg0_value);4923 Stage1ZirInst *tag_name = ir_build_tag_name_src(ag, scope, node, arg0_value);
4924 return ir_lval_wrap(ag, scope, tag_name, lval, result_loc);4924 return ir_lval_wrap(ag, scope, tag_name, lval, result_loc);
4925 }4925 }
4926 case BuiltinFnIdFieldParentPtr:4926 case BuiltinFnIdFieldParentPtr:
4927 {4927 {
4928 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4928 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4929 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4929 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4930 if (arg0_value == ag->codegen->invalid_inst_src)4930 if (arg0_value == ag->codegen->invalid_inst_src)
4931 return arg0_value;4931 return arg0_value;
49324932
4933 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4933 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4934 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4934 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4935 if (arg1_value == ag->codegen->invalid_inst_src)4935 if (arg1_value == ag->codegen->invalid_inst_src)
4936 return arg1_value;4936 return arg1_value;
49374937
4938 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);4938 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
4939 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);4939 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
4940 if (arg2_value == ag->codegen->invalid_inst_src)4940 if (arg2_value == ag->codegen->invalid_inst_src)
4941 return arg2_value;4941 return arg2_value;
49424942
4943 IrInstSrc *field_parent_ptr = ir_build_field_parent_ptr_src(ag, scope, node,4943 Stage1ZirInst *field_parent_ptr = ir_build_field_parent_ptr_src(ag, scope, node,
4944 arg0_value, arg1_value, arg2_value);4944 arg0_value, arg1_value, arg2_value);
4945 return ir_lval_wrap(ag, scope, field_parent_ptr, lval, result_loc);4945 return ir_lval_wrap(ag, scope, field_parent_ptr, lval, result_loc);
4946 }4946 }
4947 case BuiltinFnIdOffsetOf:4947 case BuiltinFnIdOffsetOf:
4948 {4948 {
4949 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4949 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4950 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4950 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4951 if (arg0_value == ag->codegen->invalid_inst_src)4951 if (arg0_value == ag->codegen->invalid_inst_src)
4952 return arg0_value;4952 return arg0_value;
49534953
4954 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4954 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4955 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4955 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4956 if (arg1_value == ag->codegen->invalid_inst_src)4956 if (arg1_value == ag->codegen->invalid_inst_src)
4957 return arg1_value;4957 return arg1_value;
49584958
4959 IrInstSrc *offset_of = ir_build_offset_of(ag, scope, node, arg0_value, arg1_value);4959 Stage1ZirInst *offset_of = ir_build_offset_of(ag, scope, node, arg0_value, arg1_value);
4960 return ir_lval_wrap(ag, scope, offset_of, lval, result_loc);4960 return ir_lval_wrap(ag, scope, offset_of, lval, result_loc);
4961 }4961 }
4962 case BuiltinFnIdBitOffsetOf:4962 case BuiltinFnIdBitOffsetOf:
4963 {4963 {
4964 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);4964 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4965 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);4965 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
4966 if (arg0_value == ag->codegen->invalid_inst_src)4966 if (arg0_value == ag->codegen->invalid_inst_src)
4967 return arg0_value;4967 return arg0_value;
49684968
4969 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);4969 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4970 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);4970 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
4971 if (arg1_value == ag->codegen->invalid_inst_src)4971 if (arg1_value == ag->codegen->invalid_inst_src)
4972 return arg1_value;4972 return arg1_value;
49734973
4974 IrInstSrc *offset_of = ir_build_bit_offset_of(ag, scope, node, arg0_value, arg1_value);4974 Stage1ZirInst *offset_of = ir_build_bit_offset_of(ag, scope, node, arg0_value, arg1_value);
4975 return ir_lval_wrap(ag, scope, offset_of, lval, result_loc);4975 return ir_lval_wrap(ag, scope, offset_of, lval, result_loc);
4976 }4976 }
4977 case BuiltinFnIdCall: {4977 case BuiltinFnIdCall: {
4978 // Cast the options parameter to the options type4978 // Cast the options parameter to the options type
4979 ZigType *options_type = get_builtin_type(ag->codegen, "CallOptions");4979 ZigType *options_type = get_builtin_type(ag->codegen, "CallOptions");
4980 IrInstSrc *options_type_inst = ir_build_const_type(ag, scope, node, options_type);4980 Stage1ZirInst *options_type_inst = ir_build_const_type(ag, scope, node, options_type);
4981 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc());4981 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc());
49824982
4983 AstNode *options_node = node->data.fn_call_expr.params.at(0);4983 AstNode *options_node = node->data.fn_call_expr.params.at(0);
4984 IrInstSrc *options_inner = astgen_node_extra(ag, options_node, scope,4984 Stage1ZirInst *options_inner = astgen_node_extra(ag, options_node, scope,
4985 LValNone, &result_loc_cast->base);4985 LValNone, &result_loc_cast->base);
4986 if (options_inner == ag->codegen->invalid_inst_src)4986 if (options_inner == ag->codegen->invalid_inst_src)
4987 return options_inner;4987 return options_inner;
4988 IrInstSrc *options = ir_build_implicit_cast(ag, scope, options_node, options_inner, result_loc_cast);4988 Stage1ZirInst *options = ir_build_implicit_cast(ag, scope, options_node, options_inner, result_loc_cast);
49894989
4990 AstNode *fn_ref_node = node->data.fn_call_expr.params.at(1);4990 AstNode *fn_ref_node = node->data.fn_call_expr.params.at(1);
4991 AstNode *args_node = node->data.fn_call_expr.params.at(2);4991 AstNode *args_node = node->data.fn_call_expr.params.at(2);
...@@ -5004,15 +5004,15 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -5004,15 +5004,15 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
5004 return ag->codegen->invalid_inst_src;5004 return ag->codegen->invalid_inst_src;
5005 }5005 }
5006 } else {5006 } else {
5007 IrInstSrc *fn_ref = astgen_node(ag, fn_ref_node, scope);5007 Stage1ZirInst *fn_ref = astgen_node(ag, fn_ref_node, scope);
5008 if (fn_ref == ag->codegen->invalid_inst_src)5008 if (fn_ref == ag->codegen->invalid_inst_src)
5009 return fn_ref;5009 return fn_ref;
50105010
5011 IrInstSrc *args = astgen_node(ag, args_node, scope);5011 Stage1ZirInst *args = astgen_node(ag, args_node, scope);
5012 if (args == ag->codegen->invalid_inst_src)5012 if (args == ag->codegen->invalid_inst_src)
5013 return args;5013 return args;
50145014
5015 IrInstSrc *call = ir_build_call_extra(ag, scope, node, options, fn_ref, args, result_loc);5015 Stage1ZirInst *call = ir_build_call_extra(ag, scope, node, options, fn_ref, args, result_loc);
5016 return ir_lval_wrap(ag, scope, call, lval, result_loc);5016 return ir_lval_wrap(ag, scope, call, lval, result_loc);
5017 }5017 }
5018 }5018 }
...@@ -5021,227 +5021,227 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -5021,227 +5021,227 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
5021 case BuiltinFnIdShlExact:5021 case BuiltinFnIdShlExact:
5022 {5022 {
5023 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5023 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5024 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5024 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5025 if (arg0_value == ag->codegen->invalid_inst_src)5025 if (arg0_value == ag->codegen->invalid_inst_src)
5026 return arg0_value;5026 return arg0_value;
50275027
5028 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);5028 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5029 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);5029 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
5030 if (arg1_value == ag->codegen->invalid_inst_src)5030 if (arg1_value == ag->codegen->invalid_inst_src)
5031 return arg1_value;5031 return arg1_value;
50325032
5033 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftLeftExact, arg0_value, arg1_value, true);5033 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftLeftExact, arg0_value, arg1_value, true);
5034 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);5034 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
5035 }5035 }
5036 case BuiltinFnIdShrExact:5036 case BuiltinFnIdShrExact:
5037 {5037 {
5038 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5038 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5039 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5039 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5040 if (arg0_value == ag->codegen->invalid_inst_src)5040 if (arg0_value == ag->codegen->invalid_inst_src)
5041 return arg0_value;5041 return arg0_value;
50425042
5043 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);5043 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5044 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);5044 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
5045 if (arg1_value == ag->codegen->invalid_inst_src)5045 if (arg1_value == ag->codegen->invalid_inst_src)
5046 return arg1_value;5046 return arg1_value;
50475047
5048 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftRightExact, arg0_value, arg1_value, true);5048 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftRightExact, arg0_value, arg1_value, true);
5049 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);5049 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
5050 }5050 }
5051 case BuiltinFnIdSetEvalBranchQuota:5051 case BuiltinFnIdSetEvalBranchQuota:
5052 {5052 {
5053 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5053 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5054 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5054 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5055 if (arg0_value == ag->codegen->invalid_inst_src)5055 if (arg0_value == ag->codegen->invalid_inst_src)
5056 return arg0_value;5056 return arg0_value;
50575057
5058 IrInstSrc *set_eval_branch_quota = ir_build_set_eval_branch_quota(ag, scope, node, arg0_value);5058 Stage1ZirInst *set_eval_branch_quota = ir_build_set_eval_branch_quota(ag, scope, node, arg0_value);
5059 return ir_lval_wrap(ag, scope, set_eval_branch_quota, lval, result_loc);5059 return ir_lval_wrap(ag, scope, set_eval_branch_quota, lval, result_loc);
5060 }5060 }
5061 case BuiltinFnIdAlignCast:5061 case BuiltinFnIdAlignCast:
5062 {5062 {
5063 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5063 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5064 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5064 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5065 if (arg0_value == ag->codegen->invalid_inst_src)5065 if (arg0_value == ag->codegen->invalid_inst_src)
5066 return arg0_value;5066 return arg0_value;
50675067
5068 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);5068 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5069 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);5069 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
5070 if (arg1_value == ag->codegen->invalid_inst_src)5070 if (arg1_value == ag->codegen->invalid_inst_src)
5071 return arg1_value;5071 return arg1_value;
50725072
5073 IrInstSrc *align_cast = ir_build_align_cast_src(ag, scope, node, arg0_value, arg1_value);5073 Stage1ZirInst *align_cast = ir_build_align_cast_src(ag, scope, node, arg0_value, arg1_value);
5074 return ir_lval_wrap(ag, scope, align_cast, lval, result_loc);5074 return ir_lval_wrap(ag, scope, align_cast, lval, result_loc);
5075 }5075 }
5076 case BuiltinFnIdThis:5076 case BuiltinFnIdThis:
5077 {5077 {
5078 IrInstSrc *this_inst = astgen_this(ag, scope, node);5078 Stage1ZirInst *this_inst = astgen_this(ag, scope, node);
5079 return ir_lval_wrap(ag, scope, this_inst, lval, result_loc);5079 return ir_lval_wrap(ag, scope, this_inst, lval, result_loc);
5080 }5080 }
5081 case BuiltinFnIdSetAlignStack:5081 case BuiltinFnIdSetAlignStack:
5082 {5082 {
5083 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5083 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5084 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5084 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5085 if (arg0_value == ag->codegen->invalid_inst_src)5085 if (arg0_value == ag->codegen->invalid_inst_src)
5086 return arg0_value;5086 return arg0_value;
50875087
5088 IrInstSrc *set_align_stack = ir_build_set_align_stack(ag, scope, node, arg0_value);5088 Stage1ZirInst *set_align_stack = ir_build_set_align_stack(ag, scope, node, arg0_value);
5089 return ir_lval_wrap(ag, scope, set_align_stack, lval, result_loc);5089 return ir_lval_wrap(ag, scope, set_align_stack, lval, result_loc);
5090 }5090 }
5091 case BuiltinFnIdExport:5091 case BuiltinFnIdExport:
5092 {5092 {
5093 // Cast the options parameter to the options type5093 // Cast the options parameter to the options type
5094 ZigType *options_type = get_builtin_type(ag->codegen, "ExportOptions");5094 ZigType *options_type = get_builtin_type(ag->codegen, "ExportOptions");
5095 IrInstSrc *options_type_inst = ir_build_const_type(ag, scope, node, options_type);5095 Stage1ZirInst *options_type_inst = ir_build_const_type(ag, scope, node, options_type);
5096 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc());5096 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc());
50975097
5098 AstNode *target_node = node->data.fn_call_expr.params.at(0);5098 AstNode *target_node = node->data.fn_call_expr.params.at(0);
5099 IrInstSrc *target_value = astgen_node(ag, target_node, scope);5099 Stage1ZirInst *target_value = astgen_node(ag, target_node, scope);
5100 if (target_value == ag->codegen->invalid_inst_src)5100 if (target_value == ag->codegen->invalid_inst_src)
5101 return target_value;5101 return target_value;
51025102
5103 AstNode *options_node = node->data.fn_call_expr.params.at(1);5103 AstNode *options_node = node->data.fn_call_expr.params.at(1);
5104 IrInstSrc *options_value = astgen_node_extra(ag, options_node,5104 Stage1ZirInst *options_value = astgen_node_extra(ag, options_node,
5105 scope, LValNone, &result_loc_cast->base);5105 scope, LValNone, &result_loc_cast->base);
5106 if (options_value == ag->codegen->invalid_inst_src)5106 if (options_value == ag->codegen->invalid_inst_src)
5107 return options_value;5107 return options_value;
51085108
5109 IrInstSrc *casted_options_value = ir_build_implicit_cast(5109 Stage1ZirInst *casted_options_value = ir_build_implicit_cast(
5110 ag, scope, options_node, options_value, result_loc_cast);5110 ag, scope, options_node, options_value, result_loc_cast);
51115111
5112 IrInstSrc *ir_export = ir_build_export(ag, scope, node, target_value, casted_options_value);5112 Stage1ZirInst *ir_export = ir_build_export(ag, scope, node, target_value, casted_options_value);
5113 return ir_lval_wrap(ag, scope, ir_export, lval, result_loc);5113 return ir_lval_wrap(ag, scope, ir_export, lval, result_loc);
5114 }5114 }
5115 case BuiltinFnIdExtern:5115 case BuiltinFnIdExtern:
5116 {5116 {
5117 // Cast the options parameter to the options type5117 // Cast the options parameter to the options type
5118 ZigType *options_type = get_builtin_type(ag->codegen, "ExternOptions");5118 ZigType *options_type = get_builtin_type(ag->codegen, "ExternOptions");
5119 IrInstSrc *options_type_inst = ir_build_const_type(ag, scope, node, options_type);5119 Stage1ZirInst *options_type_inst = ir_build_const_type(ag, scope, node, options_type);
5120 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc());5120 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc());
51215121
5122 AstNode *type_node = node->data.fn_call_expr.params.at(0);5122 AstNode *type_node = node->data.fn_call_expr.params.at(0);
5123 IrInstSrc *type_value = astgen_node(ag, type_node, scope);5123 Stage1ZirInst *type_value = astgen_node(ag, type_node, scope);
5124 if (type_value == ag->codegen->invalid_inst_src)5124 if (type_value == ag->codegen->invalid_inst_src)
5125 return type_value;5125 return type_value;
51265126
5127 AstNode *options_node = node->data.fn_call_expr.params.at(1);5127 AstNode *options_node = node->data.fn_call_expr.params.at(1);
5128 IrInstSrc *options_value = astgen_node_extra(ag, options_node,5128 Stage1ZirInst *options_value = astgen_node_extra(ag, options_node,
5129 scope, LValNone, &result_loc_cast->base);5129 scope, LValNone, &result_loc_cast->base);
5130 if (options_value == ag->codegen->invalid_inst_src)5130 if (options_value == ag->codegen->invalid_inst_src)
5131 return options_value;5131 return options_value;
51325132
5133 IrInstSrc *casted_options_value = ir_build_implicit_cast(5133 Stage1ZirInst *casted_options_value = ir_build_implicit_cast(
5134 ag, scope, options_node, options_value, result_loc_cast);5134 ag, scope, options_node, options_value, result_loc_cast);
51355135
5136 IrInstSrc *ir_extern = ir_build_extern(ag, scope, node, type_value, casted_options_value);5136 Stage1ZirInst *ir_extern = ir_build_extern(ag, scope, node, type_value, casted_options_value);
5137 return ir_lval_wrap(ag, scope, ir_extern, lval, result_loc);5137 return ir_lval_wrap(ag, scope, ir_extern, lval, result_loc);
5138 }5138 }
5139 case BuiltinFnIdErrorReturnTrace:5139 case BuiltinFnIdErrorReturnTrace:
5140 {5140 {
5141 IrInstSrc *error_return_trace = ir_build_error_return_trace_src(ag, scope, node,5141 Stage1ZirInst *error_return_trace = ir_build_error_return_trace_src(ag, scope, node,
5142 IrInstErrorReturnTraceNull);5142 IrInstErrorReturnTraceNull);
5143 return ir_lval_wrap(ag, scope, error_return_trace, lval, result_loc);5143 return ir_lval_wrap(ag, scope, error_return_trace, lval, result_loc);
5144 }5144 }
5145 case BuiltinFnIdAtomicRmw:5145 case BuiltinFnIdAtomicRmw:
5146 {5146 {
5147 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5147 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5148 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5148 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5149 if (arg0_value == ag->codegen->invalid_inst_src)5149 if (arg0_value == ag->codegen->invalid_inst_src)
5150 return arg0_value;5150 return arg0_value;
51515151
5152 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);5152 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5153 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);5153 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
5154 if (arg1_value == ag->codegen->invalid_inst_src)5154 if (arg1_value == ag->codegen->invalid_inst_src)
5155 return arg1_value;5155 return arg1_value;
51565156
5157 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);5157 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
5158 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);5158 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
5159 if (arg2_value == ag->codegen->invalid_inst_src)5159 if (arg2_value == ag->codegen->invalid_inst_src)
5160 return arg2_value;5160 return arg2_value;
51615161
5162 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);5162 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);
5163 IrInstSrc *arg3_value = astgen_node(ag, arg3_node, scope);5163 Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, scope);
5164 if (arg3_value == ag->codegen->invalid_inst_src)5164 if (arg3_value == ag->codegen->invalid_inst_src)
5165 return arg3_value;5165 return arg3_value;
51665166
5167 AstNode *arg4_node = node->data.fn_call_expr.params.at(4);5167 AstNode *arg4_node = node->data.fn_call_expr.params.at(4);
5168 IrInstSrc *arg4_value = astgen_node(ag, arg4_node, scope);5168 Stage1ZirInst *arg4_value = astgen_node(ag, arg4_node, scope);
5169 if (arg4_value == ag->codegen->invalid_inst_src)5169 if (arg4_value == ag->codegen->invalid_inst_src)
5170 return arg4_value;5170 return arg4_value;
51715171
5172 IrInstSrc *inst = ir_build_atomic_rmw_src(ag, scope, node,5172 Stage1ZirInst *inst = ir_build_atomic_rmw_src(ag, scope, node,
5173 arg0_value, arg1_value, arg2_value, arg3_value, arg4_value);5173 arg0_value, arg1_value, arg2_value, arg3_value, arg4_value);
5174 return ir_lval_wrap(ag, scope, inst, lval, result_loc);5174 return ir_lval_wrap(ag, scope, inst, lval, result_loc);
5175 }5175 }
5176 case BuiltinFnIdAtomicLoad:5176 case BuiltinFnIdAtomicLoad:
5177 {5177 {
5178 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5178 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5179 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5179 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5180 if (arg0_value == ag->codegen->invalid_inst_src)5180 if (arg0_value == ag->codegen->invalid_inst_src)
5181 return arg0_value;5181 return arg0_value;
51825182
5183 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);5183 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5184 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);5184 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
5185 if (arg1_value == ag->codegen->invalid_inst_src)5185 if (arg1_value == ag->codegen->invalid_inst_src)
5186 return arg1_value;5186 return arg1_value;
51875187
5188 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);5188 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
5189 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);5189 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
5190 if (arg2_value == ag->codegen->invalid_inst_src)5190 if (arg2_value == ag->codegen->invalid_inst_src)
5191 return arg2_value;5191 return arg2_value;
51925192
5193 IrInstSrc *inst = ir_build_atomic_load_src(ag, scope, node, arg0_value, arg1_value, arg2_value);5193 Stage1ZirInst *inst = ir_build_atomic_load_src(ag, scope, node, arg0_value, arg1_value, arg2_value);
5194 return ir_lval_wrap(ag, scope, inst, lval, result_loc);5194 return ir_lval_wrap(ag, scope, inst, lval, result_loc);
5195 }5195 }
5196 case BuiltinFnIdAtomicStore:5196 case BuiltinFnIdAtomicStore:
5197 {5197 {
5198 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5198 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5199 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5199 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5200 if (arg0_value == ag->codegen->invalid_inst_src)5200 if (arg0_value == ag->codegen->invalid_inst_src)
5201 return arg0_value;5201 return arg0_value;
52025202
5203 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);5203 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5204 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);5204 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
5205 if (arg1_value == ag->codegen->invalid_inst_src)5205 if (arg1_value == ag->codegen->invalid_inst_src)
5206 return arg1_value;5206 return arg1_value;
52075207
5208 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);5208 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
5209 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);5209 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
5210 if (arg2_value == ag->codegen->invalid_inst_src)5210 if (arg2_value == ag->codegen->invalid_inst_src)
5211 return arg2_value;5211 return arg2_value;
52125212
5213 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);5213 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);
5214 IrInstSrc *arg3_value = astgen_node(ag, arg3_node, scope);5214 Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, scope);
5215 if (arg3_value == ag->codegen->invalid_inst_src)5215 if (arg3_value == ag->codegen->invalid_inst_src)
5216 return arg3_value;5216 return arg3_value;
52175217
5218 IrInstSrc *inst = ir_build_atomic_store_src(ag, scope, node, arg0_value, arg1_value,5218 Stage1ZirInst *inst = ir_build_atomic_store_src(ag, scope, node, arg0_value, arg1_value,
5219 arg2_value, arg3_value);5219 arg2_value, arg3_value);
5220 return ir_lval_wrap(ag, scope, inst, lval, result_loc);5220 return ir_lval_wrap(ag, scope, inst, lval, result_loc);
5221 }5221 }
5222 case BuiltinFnIdIntToEnum:5222 case BuiltinFnIdIntToEnum:
5223 {5223 {
5224 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5224 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5225 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5225 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5226 if (arg0_value == ag->codegen->invalid_inst_src)5226 if (arg0_value == ag->codegen->invalid_inst_src)
5227 return arg0_value;5227 return arg0_value;
52285228
5229 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);5229 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5230 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);5230 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
5231 if (arg1_value == ag->codegen->invalid_inst_src)5231 if (arg1_value == ag->codegen->invalid_inst_src)
5232 return arg1_value;5232 return arg1_value;
52335233
5234 IrInstSrc *result = ir_build_int_to_enum_src(ag, scope, node, arg0_value, arg1_value);5234 Stage1ZirInst *result = ir_build_int_to_enum_src(ag, scope, node, arg0_value, arg1_value);
5235 return ir_lval_wrap(ag, scope, result, lval, result_loc);5235 return ir_lval_wrap(ag, scope, result, lval, result_loc);
5236 }5236 }
5237 case BuiltinFnIdEnumToInt:5237 case BuiltinFnIdEnumToInt:
5238 {5238 {
5239 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5239 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5240 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5240 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5241 if (arg0_value == ag->codegen->invalid_inst_src)5241 if (arg0_value == ag->codegen->invalid_inst_src)
5242 return arg0_value;5242 return arg0_value;
52435243
5244 IrInstSrc *result = ir_build_enum_to_int(ag, scope, node, arg0_value);5244 Stage1ZirInst *result = ir_build_enum_to_int(ag, scope, node, arg0_value);
5245 return ir_lval_wrap(ag, scope, result, lval, result_loc);5245 return ir_lval_wrap(ag, scope, result, lval, result_loc);
5246 }5246 }
5247 case BuiltinFnIdCtz:5247 case BuiltinFnIdCtz:
...@@ -5251,16 +5251,16 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -5251,16 +5251,16 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
5251 case BuiltinFnIdBitReverse:5251 case BuiltinFnIdBitReverse:
5252 {5252 {
5253 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5253 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5254 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5254 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5255 if (arg0_value == ag->codegen->invalid_inst_src)5255 if (arg0_value == ag->codegen->invalid_inst_src)
5256 return arg0_value;5256 return arg0_value;
52575257
5258 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);5258 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5259 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);5259 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
5260 if (arg1_value == ag->codegen->invalid_inst_src)5260 if (arg1_value == ag->codegen->invalid_inst_src)
5261 return arg1_value;5261 return arg1_value;
52625262
5263 IrInstSrc *result;5263 Stage1ZirInst *result;
5264 switch (builtin_fn->id) {5264 switch (builtin_fn->id) {
5265 case BuiltinFnIdCtz:5265 case BuiltinFnIdCtz:
5266 result = ir_build_ctz(ag, scope, node, arg0_value, arg1_value);5266 result = ir_build_ctz(ag, scope, node, arg0_value, arg1_value);
...@@ -5285,27 +5285,27 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -5285,27 +5285,27 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
5285 case BuiltinFnIdHasDecl:5285 case BuiltinFnIdHasDecl:
5286 {5286 {
5287 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);5287 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5288 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);5288 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
5289 if (arg0_value == ag->codegen->invalid_inst_src)5289 if (arg0_value == ag->codegen->invalid_inst_src)
5290 return arg0_value;5290 return arg0_value;
52915291
5292 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);5292 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5293 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);5293 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
5294 if (arg1_value == ag->codegen->invalid_inst_src)5294 if (arg1_value == ag->codegen->invalid_inst_src)
5295 return arg1_value;5295 return arg1_value;
52965296
5297 IrInstSrc *has_decl = ir_build_has_decl(ag, scope, node, arg0_value, arg1_value);5297 Stage1ZirInst *has_decl = ir_build_has_decl(ag, scope, node, arg0_value, arg1_value);
5298 return ir_lval_wrap(ag, scope, has_decl, lval, result_loc);5298 return ir_lval_wrap(ag, scope, has_decl, lval, result_loc);
5299 }5299 }
5300 case BuiltinFnIdUnionInit:5300 case BuiltinFnIdUnionInit:
5301 {5301 {
5302 AstNode *union_type_node = node->data.fn_call_expr.params.at(0);5302 AstNode *union_type_node = node->data.fn_call_expr.params.at(0);
5303 IrInstSrc *union_type_inst = astgen_node(ag, union_type_node, scope);5303 Stage1ZirInst *union_type_inst = astgen_node(ag, union_type_node, scope);
5304 if (union_type_inst == ag->codegen->invalid_inst_src)5304 if (union_type_inst == ag->codegen->invalid_inst_src)
5305 return union_type_inst;5305 return union_type_inst;
53065306
5307 AstNode *name_node = node->data.fn_call_expr.params.at(1);5307 AstNode *name_node = node->data.fn_call_expr.params.at(1);
5308 IrInstSrc *name_inst = astgen_node(ag, name_node, scope);5308 Stage1ZirInst *name_inst = astgen_node(ag, name_node, scope);
5309 if (name_inst == ag->codegen->invalid_inst_src)5309 if (name_inst == ag->codegen->invalid_inst_src)
5310 return name_inst;5310 return name_inst;
53115311
...@@ -5316,7 +5316,7 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode...@@ -5316,7 +5316,7 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
5316 }5316 }
5317 case BuiltinFnIdSrc:5317 case BuiltinFnIdSrc:
5318 {5318 {
5319 IrInstSrc *src_inst = ir_build_src(ag, scope, node);5319 Stage1ZirInst *src_inst = ir_build_src(ag, scope, node);
5320 return ir_lval_wrap(ag, scope, src_inst, lval, result_loc);5320 return ir_lval_wrap(ag, scope, src_inst, lval, result_loc);
5321 }5321 }
5322 }5322 }
...@@ -5335,7 +5335,7 @@ static ScopeNoSuspend *get_scope_nosuspend(Scope *scope) {...@@ -5335,7 +5335,7 @@ static ScopeNoSuspend *get_scope_nosuspend(Scope *scope) {
5335 return nullptr;5335 return nullptr;
5336}5336}
53375337
5338static IrInstSrc *astgen_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,5338static Stage1ZirInst *astgen_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
5339 ResultLoc *result_loc)5339 ResultLoc *result_loc)
5340{5340{
5341 assert(node->type == NodeTypeFnCallExpr);5341 assert(node->type == NodeTypeFnCallExpr);
...@@ -5354,16 +5354,16 @@ static IrInstSrc *astgen_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node,...@@ -5354,16 +5354,16 @@ static IrInstSrc *astgen_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node,
5354 nullptr, node->data.fn_call_expr.params.items, node->data.fn_call_expr.params.length, lval, result_loc);5354 nullptr, node->data.fn_call_expr.params.items, node->data.fn_call_expr.params.length, lval, result_loc);
5355}5355}
53565356
5357static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,5357static Stage1ZirInst *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
5358 ResultLoc *result_loc)5358 ResultLoc *result_loc)
5359{5359{
5360 assert(node->type == NodeTypeIfBoolExpr);5360 assert(node->type == NodeTypeIfBoolExpr);
53615361
5362 IrInstSrc *condition = astgen_node(ag, node->data.if_bool_expr.condition, scope);5362 Stage1ZirInst *condition = astgen_node(ag, node->data.if_bool_expr.condition, scope);
5363 if (condition == ag->codegen->invalid_inst_src)5363 if (condition == ag->codegen->invalid_inst_src)
5364 return ag->codegen->invalid_inst_src;5364 return ag->codegen->invalid_inst_src;
53655365
5366 IrInstSrc *is_comptime;5366 Stage1ZirInst *is_comptime;
5367 if (ir_should_inline(ag->exec, scope)) {5367 if (ir_should_inline(ag->exec, scope)) {
5368 is_comptime = ir_build_const_bool(ag, scope, node, true);5368 is_comptime = ir_build_const_bool(ag, scope, node, true);
5369 } else {5369 } else {
...@@ -5377,7 +5377,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5377,7 +5377,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
5377 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "Else");5377 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "Else");
5378 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "EndIf");5378 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "EndIf");
53795379
5380 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, condition,5380 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, scope, node, condition,
5381 then_block, else_block, is_comptime);5381 then_block, else_block, is_comptime);
5382 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block,5382 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block,
5383 result_loc, is_comptime);5383 result_loc, is_comptime);
...@@ -5385,7 +5385,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5385,7 +5385,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
5385 ir_set_cursor_at_end_and_append_block(ag, then_block);5385 ir_set_cursor_at_end_and_append_block(ag, then_block);
53865386
5387 Scope *subexpr_scope = create_runtime_scope(ag->codegen, node, scope, is_comptime);5387 Scope *subexpr_scope = create_runtime_scope(ag->codegen, node, scope, is_comptime);
5388 IrInstSrc *then_expr_result = astgen_node_extra(ag, then_node, subexpr_scope, lval,5388 Stage1ZirInst *then_expr_result = astgen_node_extra(ag, then_node, subexpr_scope, lval,
5389 &peer_parent->peers.at(0)->base);5389 &peer_parent->peers.at(0)->base);
5390 if (then_expr_result == ag->codegen->invalid_inst_src)5390 if (then_expr_result == ag->codegen->invalid_inst_src)
5391 return ag->codegen->invalid_inst_src;5391 return ag->codegen->invalid_inst_src;
...@@ -5394,7 +5394,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5394,7 +5394,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
5394 ir_build_br(ag, scope, node, endif_block, is_comptime);5394 ir_build_br(ag, scope, node, endif_block, is_comptime);
53955395
5396 ir_set_cursor_at_end_and_append_block(ag, else_block);5396 ir_set_cursor_at_end_and_append_block(ag, else_block);
5397 IrInstSrc *else_expr_result;5397 Stage1ZirInst *else_expr_result;
5398 if (else_node) {5398 if (else_node) {
5399 else_expr_result = astgen_node_extra(ag, else_node, subexpr_scope, lval, &peer_parent->peers.at(1)->base);5399 else_expr_result = astgen_node_extra(ag, else_node, subexpr_scope, lval, &peer_parent->peers.at(1)->base);
5400 if (else_expr_result == ag->codegen->invalid_inst_src)5400 if (else_expr_result == ag->codegen->invalid_inst_src)
...@@ -5408,39 +5408,39 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5408,39 +5408,39 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
5408 ir_build_br(ag, scope, node, endif_block, is_comptime);5408 ir_build_br(ag, scope, node, endif_block, is_comptime);
54095409
5410 ir_set_cursor_at_end_and_append_block(ag, endif_block);5410 ir_set_cursor_at_end_and_append_block(ag, endif_block);
5411 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);5411 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
5412 incoming_values[0] = then_expr_result;5412 incoming_values[0] = then_expr_result;
5413 incoming_values[1] = else_expr_result;5413 incoming_values[1] = else_expr_result;
5414 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);5414 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
5415 incoming_blocks[0] = after_then_block;5415 incoming_blocks[0] = after_then_block;
5416 incoming_blocks[1] = after_else_block;5416 incoming_blocks[1] = after_else_block;
54175417
5418 IrInstSrc *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);5418 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);
5419 return ir_expr_wrap(ag, scope, phi, result_loc);5419 return ir_expr_wrap(ag, scope, phi, result_loc);
5420}5420}
54215421
5422static IrInstSrc *astgen_prefix_op_id_lval(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id, LVal lval) {5422static Stage1ZirInst *astgen_prefix_op_id_lval(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id, LVal lval) {
5423 assert(node->type == NodeTypePrefixOpExpr);5423 assert(node->type == NodeTypePrefixOpExpr);
5424 AstNode *expr_node = node->data.prefix_op_expr.primary_expr;5424 AstNode *expr_node = node->data.prefix_op_expr.primary_expr;
54255425
5426 IrInstSrc *value = astgen_node_extra(ag, expr_node, scope, lval, nullptr);5426 Stage1ZirInst *value = astgen_node_extra(ag, expr_node, scope, lval, nullptr);
5427 if (value == ag->codegen->invalid_inst_src)5427 if (value == ag->codegen->invalid_inst_src)
5428 return value;5428 return value;
54295429
5430 return ir_build_un_op(ag, scope, node, op_id, value);5430 return ir_build_un_op(ag, scope, node, op_id, value);
5431}5431}
54325432
5433static IrInstSrc *astgen_prefix_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id) {5433static Stage1ZirInst *astgen_prefix_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id) {
5434 return astgen_prefix_op_id_lval(ag, scope, node, op_id, LValNone);5434 return astgen_prefix_op_id_lval(ag, scope, node, op_id, LValNone);
5435}5435}
54365436
5437static IrInstSrc *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *inst, ResultLoc *result_loc) {5437static Stage1ZirInst *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *inst, ResultLoc *result_loc) {
5438 if (inst == ag->codegen->invalid_inst_src) return inst;5438 if (inst == ag->codegen->invalid_inst_src) return inst;
5439 ir_build_end_expr(ag, scope, inst->source_node, inst, result_loc);5439 ir_build_end_expr(ag, scope, inst->source_node, inst, result_loc);
5440 return inst;5440 return inst;
5441}5441}
54425442
5443static IrInstSrc *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *value, LVal lval,5443static Stage1ZirInst *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *value, LVal lval,
5444 ResultLoc *result_loc)5444 ResultLoc *result_loc)
5445{5445{
5446 // This logic must be kept in sync with5446 // This logic must be kept in sync with
...@@ -5448,7 +5448,7 @@ static IrInstSrc *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *value,...@@ -5448,7 +5448,7 @@ static IrInstSrc *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *value,
5448 if (value == ag->codegen->invalid_inst_src ||5448 if (value == ag->codegen->invalid_inst_src ||
5449 instr_is_unreachable(value) ||5449 instr_is_unreachable(value) ||
5450 value->source_node->type == NodeTypeDefer ||5450 value->source_node->type == NodeTypeDefer ||
5451 value->id == IrInstSrcIdDeclVar)5451 value->id == Stage1ZirInstIdDeclVar)
5452 {5452 {
5453 return value;5453 return value;
5454 }5454 }
...@@ -5500,7 +5500,7 @@ static Error token_number_literal_u32(Stage1AstGen *ag, AstNode *source_node,...@@ -5500,7 +5500,7 @@ static Error token_number_literal_u32(Stage1AstGen *ag, AstNode *source_node,
55005500
5501}5501}
55025502
5503static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {5503static Stage1ZirInst *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
5504 Error err;5504 Error err;
5505 assert(node->type == NodeTypePointerType);5505 assert(node->type == NodeTypePointerType);
55065506
...@@ -5515,7 +5515,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5515,7 +5515,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n
5515 AstNode *expr_node = node->data.pointer_type.op_expr;5515 AstNode *expr_node = node->data.pointer_type.op_expr;
5516 AstNode *align_expr = node->data.pointer_type.align_expr;5516 AstNode *align_expr = node->data.pointer_type.align_expr;
55175517
5518 IrInstSrc *sentinel;5518 Stage1ZirInst *sentinel;
5519 if (sentinel_expr != nullptr) {5519 if (sentinel_expr != nullptr) {
5520 sentinel = astgen_node(ag, sentinel_expr, scope);5520 sentinel = astgen_node(ag, sentinel_expr, scope);
5521 if (sentinel == ag->codegen->invalid_inst_src)5521 if (sentinel == ag->codegen->invalid_inst_src)
...@@ -5524,7 +5524,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5524,7 +5524,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n
5524 sentinel = nullptr;5524 sentinel = nullptr;
5525 }5525 }
55265526
5527 IrInstSrc *align_value;5527 Stage1ZirInst *align_value;
5528 if (align_expr != nullptr) {5528 if (align_expr != nullptr) {
5529 align_value = astgen_node(ag, align_expr, scope);5529 align_value = astgen_node(ag, align_expr, scope);
5530 if (align_value == ag->codegen->invalid_inst_src)5530 if (align_value == ag->codegen->invalid_inst_src)
...@@ -5533,7 +5533,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5533,7 +5533,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n
5533 align_value = nullptr;5533 align_value = nullptr;
5534 }5534 }
55355535
5536 IrInstSrc *child_type = astgen_node(ag, expr_node, scope);5536 Stage1ZirInst *child_type = astgen_node(ag, expr_node, scope);
5537 if (child_type == ag->codegen->invalid_inst_src)5537 if (child_type == ag->codegen->invalid_inst_src)
5538 return child_type;5538 return child_type;
55395539
...@@ -5565,36 +5565,36 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5565,36 +5565,36 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n
5565 ptr_len, sentinel, align_value, bit_offset_start, host_int_bytes, is_allow_zero);5565 ptr_len, sentinel, align_value, bit_offset_start, host_int_bytes, is_allow_zero);
5566}5566}
55675567
5568static IrInstSrc *astgen_catch_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node,5568static Stage1ZirInst *astgen_catch_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
5569 AstNode *expr_node, LVal lval, ResultLoc *result_loc)5569 AstNode *expr_node, LVal lval, ResultLoc *result_loc)
5570{5570{
5571 IrInstSrc *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);5571 Stage1ZirInst *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
5572 if (err_union_ptr == ag->codegen->invalid_inst_src)5572 if (err_union_ptr == ag->codegen->invalid_inst_src)
5573 return ag->codegen->invalid_inst_src;5573 return ag->codegen->invalid_inst_src;
55745574
5575 IrInstSrc *payload_ptr = ir_build_unwrap_err_payload_src(ag, scope, source_node, err_union_ptr, true, false);5575 Stage1ZirInst *payload_ptr = ir_build_unwrap_err_payload_src(ag, scope, source_node, err_union_ptr, true, false);
5576 if (payload_ptr == ag->codegen->invalid_inst_src)5576 if (payload_ptr == ag->codegen->invalid_inst_src)
5577 return ag->codegen->invalid_inst_src;5577 return ag->codegen->invalid_inst_src;
55785578
5579 if (lval == LValPtr)5579 if (lval == LValPtr)
5580 return payload_ptr;5580 return payload_ptr;
55815581
5582 IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, source_node, payload_ptr);5582 Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, source_node, payload_ptr);
5583 return ir_expr_wrap(ag, scope, load_ptr, result_loc);5583 return ir_expr_wrap(ag, scope, load_ptr, result_loc);
5584}5584}
55855585
5586static IrInstSrc *astgen_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *node) {5586static Stage1ZirInst *astgen_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *node) {
5587 assert(node->type == NodeTypePrefixOpExpr);5587 assert(node->type == NodeTypePrefixOpExpr);
5588 AstNode *expr_node = node->data.prefix_op_expr.primary_expr;5588 AstNode *expr_node = node->data.prefix_op_expr.primary_expr;
55895589
5590 IrInstSrc *value = astgen_node(ag, expr_node, scope);5590 Stage1ZirInst *value = astgen_node(ag, expr_node, scope);
5591 if (value == ag->codegen->invalid_inst_src)5591 if (value == ag->codegen->invalid_inst_src)
5592 return ag->codegen->invalid_inst_src;5592 return ag->codegen->invalid_inst_src;
55935593
5594 return ir_build_bool_not(ag, scope, node, value);5594 return ir_build_bool_not(ag, scope, node, value);
5595}5595}
55965596
5597static IrInstSrc *astgen_prefix_op_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,5597static Stage1ZirInst *astgen_prefix_op_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
5598 ResultLoc *result_loc)5598 ResultLoc *result_loc)
5599{5599{
5600 assert(node->type == NodeTypePrefixOpExpr);5600 assert(node->type == NodeTypePrefixOpExpr);
...@@ -5622,12 +5622,12 @@ static IrInstSrc *astgen_prefix_op_expr(Stage1AstGen *ag, Scope *scope, AstNode...@@ -5622,12 +5622,12 @@ static IrInstSrc *astgen_prefix_op_expr(Stage1AstGen *ag, Scope *scope, AstNode
5622 zig_unreachable();5622 zig_unreachable();
5623}5623}
56245624
5625static IrInstSrc *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,5625static Stage1ZirInst *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
5626 IrInstSrc *union_type, IrInstSrc *field_name, AstNode *expr_node,5626 Stage1ZirInst *union_type, Stage1ZirInst *field_name, AstNode *expr_node,
5627 LVal lval, ResultLoc *parent_result_loc)5627 LVal lval, ResultLoc *parent_result_loc)
5628{5628{
5629 IrInstSrc *container_ptr = ir_build_resolve_result(ag, scope, source_node, parent_result_loc, union_type);5629 Stage1ZirInst *container_ptr = ir_build_resolve_result(ag, scope, source_node, parent_result_loc, union_type);
5630 IrInstSrc *field_ptr = ir_build_field_ptr_instruction(ag, scope, source_node, container_ptr,5630 Stage1ZirInst *field_ptr = ir_build_field_ptr_instruction(ag, scope, source_node, container_ptr,
5631 field_name, true);5631 field_name, true);
56325632
5633 ResultLocInstruction *result_loc_inst = heap::c_allocator.create<ResultLocInstruction>();5633 ResultLocInstruction *result_loc_inst = heap::c_allocator.create<ResultLocInstruction>();
...@@ -5636,18 +5636,18 @@ static IrInstSrc *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode...@@ -5636,18 +5636,18 @@ static IrInstSrc *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode
5636 ir_ref_instruction(field_ptr, ag->current_basic_block);5636 ir_ref_instruction(field_ptr, ag->current_basic_block);
5637 ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base);5637 ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base);
56385638
5639 IrInstSrc *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,5639 Stage1ZirInst *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,
5640 &result_loc_inst->base);5640 &result_loc_inst->base);
5641 if (expr_value == ag->codegen->invalid_inst_src)5641 if (expr_value == ag->codegen->invalid_inst_src)
5642 return expr_value;5642 return expr_value;
56435643
5644 IrInstSrc *init_union = ir_build_union_init_named_field(ag, scope, source_node, union_type,5644 Stage1ZirInst *init_union = ir_build_union_init_named_field(ag, scope, source_node, union_type,
5645 field_name, field_ptr, container_ptr);5645 field_name, field_ptr, container_ptr);
56465646
5647 return ir_lval_wrap(ag, scope, init_union, lval, parent_result_loc);5647 return ir_lval_wrap(ag, scope, init_union, lval, parent_result_loc);
5648}5648}
56495649
5650static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,5650static Stage1ZirInst *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
5651 ResultLoc *parent_result_loc)5651 ResultLoc *parent_result_loc)
5652{5652{
5653 assert(node->type == NodeTypeContainerInitExpr);5653 assert(node->type == NodeTypeContainerInitExpr);
...@@ -5659,14 +5659,14 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast...@@ -5659,14 +5659,14 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
5659 ResultLoc *child_result_loc;5659 ResultLoc *child_result_loc;
5660 AstNode *init_array_type_source_node;5660 AstNode *init_array_type_source_node;
5661 if (container_init_expr->type != nullptr) {5661 if (container_init_expr->type != nullptr) {
5662 IrInstSrc *container_type;5662 Stage1ZirInst *container_type;
5663 if (container_init_expr->type->type == NodeTypeInferredArrayType) {5663 if (container_init_expr->type->type == NodeTypeInferredArrayType) {
5664 if (kind == ContainerInitKindStruct) {5664 if (kind == ContainerInitKindStruct) {
5665 add_node_error(ag->codegen, container_init_expr->type,5665 add_node_error(ag->codegen, container_init_expr->type,
5666 buf_sprintf("initializing array with struct syntax"));5666 buf_sprintf("initializing array with struct syntax"));
5667 return ag->codegen->invalid_inst_src;5667 return ag->codegen->invalid_inst_src;
5668 }5668 }
5669 IrInstSrc *sentinel;5669 Stage1ZirInst *sentinel;
5670 if (container_init_expr->type->data.inferred_array_type.sentinel != nullptr) {5670 if (container_init_expr->type->data.inferred_array_type.sentinel != nullptr) {
5671 sentinel = astgen_node(ag, container_init_expr->type->data.inferred_array_type.sentinel, scope);5671 sentinel = astgen_node(ag, container_init_expr->type->data.inferred_array_type.sentinel, scope);
5672 if (sentinel == ag->codegen->invalid_inst_src)5672 if (sentinel == ag->codegen->invalid_inst_src)
...@@ -5675,12 +5675,12 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast...@@ -5675,12 +5675,12 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
5675 sentinel = nullptr;5675 sentinel = nullptr;
5676 }5676 }
56775677
5678 IrInstSrc *elem_type = astgen_node(ag,5678 Stage1ZirInst *elem_type = astgen_node(ag,
5679 container_init_expr->type->data.inferred_array_type.child_type, scope);5679 container_init_expr->type->data.inferred_array_type.child_type, scope);
5680 if (elem_type == ag->codegen->invalid_inst_src)5680 if (elem_type == ag->codegen->invalid_inst_src)
5681 return elem_type;5681 return elem_type;
5682 size_t item_count = container_init_expr->entries.length;5682 size_t item_count = container_init_expr->entries.length;
5683 IrInstSrc *item_count_inst = ir_build_const_usize(ag, scope, node, item_count);5683 Stage1ZirInst *item_count_inst = ir_build_const_usize(ag, scope, node, item_count);
5684 container_type = ir_build_array_type(ag, scope, node, item_count_inst, sentinel, elem_type);5684 container_type = ir_build_array_type(ag, scope, node, item_count_inst, sentinel, elem_type);
5685 } else {5685 } else {
5686 container_type = astgen_node(ag, container_init_expr->type, scope);5686 container_type = astgen_node(ag, container_init_expr->type, scope);
...@@ -5702,11 +5702,11 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast...@@ -5702,11 +5702,11 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
57025702
5703 switch (kind) {5703 switch (kind) {
5704 case ContainerInitKindStruct: {5704 case ContainerInitKindStruct: {
5705 IrInstSrc *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc,5705 Stage1ZirInst *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc,
5706 nullptr);5706 nullptr);
57075707
5708 size_t field_count = container_init_expr->entries.length;5708 size_t field_count = container_init_expr->entries.length;
5709 IrInstSrcContainerInitFieldsField *fields = heap::c_allocator.allocate<IrInstSrcContainerInitFieldsField>(field_count);5709 Stage1ZirInstContainerInitFieldsField *fields = heap::c_allocator.allocate<Stage1ZirInstContainerInitFieldsField>(field_count);
5710 for (size_t i = 0; i < field_count; i += 1) {5710 for (size_t i = 0; i < field_count; i += 1) {
5711 AstNode *entry_node = container_init_expr->entries.at(i);5711 AstNode *entry_node = container_init_expr->entries.at(i);
5712 assert(entry_node->type == NodeTypeStructValueField);5712 assert(entry_node->type == NodeTypeStructValueField);
...@@ -5714,7 +5714,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast...@@ -5714,7 +5714,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
5714 Buf *name = entry_node->data.struct_val_field.name;5714 Buf *name = entry_node->data.struct_val_field.name;
5715 AstNode *expr_node = entry_node->data.struct_val_field.expr;5715 AstNode *expr_node = entry_node->data.struct_val_field.expr;
57165716
5717 IrInstSrc *field_ptr = ir_build_field_ptr(ag, scope, entry_node, container_ptr, name, true);5717 Stage1ZirInst *field_ptr = ir_build_field_ptr(ag, scope, entry_node, container_ptr, name, true);
5718 ResultLocInstruction *result_loc_inst = heap::c_allocator.create<ResultLocInstruction>();5718 ResultLocInstruction *result_loc_inst = heap::c_allocator.create<ResultLocInstruction>();
5719 result_loc_inst->base.id = ResultLocIdInstruction;5719 result_loc_inst->base.id = ResultLocIdInstruction;
5720 result_loc_inst->base.source_instruction = field_ptr;5720 result_loc_inst->base.source_instruction = field_ptr;
...@@ -5722,7 +5722,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast...@@ -5722,7 +5722,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
5722 ir_ref_instruction(field_ptr, ag->current_basic_block);5722 ir_ref_instruction(field_ptr, ag->current_basic_block);
5723 ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base);5723 ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base);
57245724
5725 IrInstSrc *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,5725 Stage1ZirInst *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,
5726 &result_loc_inst->base);5726 &result_loc_inst->base);
5727 if (expr_value == ag->codegen->invalid_inst_src)5727 if (expr_value == ag->codegen->invalid_inst_src)
5728 return expr_value;5728 return expr_value;
...@@ -5731,7 +5731,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast...@@ -5731,7 +5731,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
5731 fields[i].source_node = entry_node;5731 fields[i].source_node = entry_node;
5732 fields[i].result_loc = field_ptr;5732 fields[i].result_loc = field_ptr;
5733 }5733 }
5734 IrInstSrc *result = ir_build_container_init_fields(ag, scope, node, field_count,5734 Stage1ZirInst *result = ir_build_container_init_fields(ag, scope, node, field_count,
5735 fields, container_ptr);5735 fields, container_ptr);
57365736
5737 if (result_loc_cast != nullptr) {5737 if (result_loc_cast != nullptr) {
...@@ -5742,15 +5742,15 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast...@@ -5742,15 +5742,15 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
5742 case ContainerInitKindArray: {5742 case ContainerInitKindArray: {
5743 size_t item_count = container_init_expr->entries.length;5743 size_t item_count = container_init_expr->entries.length;
57445744
5745 IrInstSrc *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc,5745 Stage1ZirInst *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc,
5746 nullptr);5746 nullptr);
57475747
5748 IrInstSrc **result_locs = heap::c_allocator.allocate<IrInstSrc *>(item_count);5748 Stage1ZirInst **result_locs = heap::c_allocator.allocate<Stage1ZirInst *>(item_count);
5749 for (size_t i = 0; i < item_count; i += 1) {5749 for (size_t i = 0; i < item_count; i += 1) {
5750 AstNode *expr_node = container_init_expr->entries.at(i);5750 AstNode *expr_node = container_init_expr->entries.at(i);
57515751
5752 IrInstSrc *elem_index = ir_build_const_usize(ag, scope, expr_node, i);5752 Stage1ZirInst *elem_index = ir_build_const_usize(ag, scope, expr_node, i);
5753 IrInstSrc *elem_ptr = ir_build_elem_ptr(ag, scope, expr_node, container_ptr,5753 Stage1ZirInst *elem_ptr = ir_build_elem_ptr(ag, scope, expr_node, container_ptr,
5754 elem_index, false, PtrLenSingle, init_array_type_source_node);5754 elem_index, false, PtrLenSingle, init_array_type_source_node);
5755 ResultLocInstruction *result_loc_inst = heap::c_allocator.create<ResultLocInstruction>();5755 ResultLocInstruction *result_loc_inst = heap::c_allocator.create<ResultLocInstruction>();
5756 result_loc_inst->base.id = ResultLocIdInstruction;5756 result_loc_inst->base.id = ResultLocIdInstruction;
...@@ -5759,14 +5759,14 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast...@@ -5759,14 +5759,14 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
5759 ir_ref_instruction(elem_ptr, ag->current_basic_block);5759 ir_ref_instruction(elem_ptr, ag->current_basic_block);
5760 ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base);5760 ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base);
57615761
5762 IrInstSrc *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,5762 Stage1ZirInst *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,
5763 &result_loc_inst->base);5763 &result_loc_inst->base);
5764 if (expr_value == ag->codegen->invalid_inst_src)5764 if (expr_value == ag->codegen->invalid_inst_src)
5765 return expr_value;5765 return expr_value;
57665766
5767 result_locs[i] = elem_ptr;5767 result_locs[i] = elem_ptr;
5768 }5768 }
5769 IrInstSrc *result = ir_build_container_init_list(ag, scope, node, item_count,5769 Stage1ZirInst *result = ir_build_container_init_list(ag, scope, node, item_count,
5770 result_locs, container_ptr, init_array_type_source_node);5770 result_locs, container_ptr, init_array_type_source_node);
5771 if (result_loc_cast != nullptr) {5771 if (result_loc_cast != nullptr) {
5772 result = ir_build_implicit_cast(ag, scope, node, result, result_loc_cast);5772 result = ir_build_implicit_cast(ag, scope, node, result, result_loc_cast);
...@@ -5777,7 +5777,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast...@@ -5777,7 +5777,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
5777 zig_unreachable();5777 zig_unreachable();
5778}5778}
57795779
5780static ResultLocVar *ir_build_var_result_loc(Stage1AstGen *ag, IrInstSrc *alloca, ZigVar *var) {5780static ResultLocVar *ir_build_var_result_loc(Stage1AstGen *ag, Stage1ZirInst *alloca, ZigVar *var) {
5781 ResultLocVar *result_loc_var = heap::c_allocator.create<ResultLocVar>();5781 ResultLocVar *result_loc_var = heap::c_allocator.create<ResultLocVar>();
5782 result_loc_var->base.id = ResultLocIdVar;5782 result_loc_var->base.id = ResultLocIdVar;
5783 result_loc_var->base.source_instruction = alloca;5783 result_loc_var->base.source_instruction = alloca;
...@@ -5789,7 +5789,7 @@ static ResultLocVar *ir_build_var_result_loc(Stage1AstGen *ag, IrInstSrc *alloca...@@ -5789,7 +5789,7 @@ static ResultLocVar *ir_build_var_result_loc(Stage1AstGen *ag, IrInstSrc *alloca
5789 return result_loc_var;5789 return result_loc_var;
5790}5790}
57915791
5792static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, IrInstSrc *dest_type,5792static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, Stage1ZirInst *dest_type,
5793 ResultLoc *parent_result_loc)5793 ResultLoc *parent_result_loc)
5794{5794{
5795 ResultLocCast *result_loc_cast = heap::c_allocator.create<ResultLocCast>();5795 ResultLocCast *result_loc_cast = heap::c_allocator.create<ResultLocCast>();
...@@ -5805,15 +5805,15 @@ static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, IrInstSrc *dest...@@ -5805,15 +5805,15 @@ static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, IrInstSrc *dest
5805}5805}
58065806
5807static void build_decl_var_and_init(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var,5807static void build_decl_var_and_init(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var,
5808 IrInstSrc *init, const char *name_hint, IrInstSrc *is_comptime)5808 Stage1ZirInst *init, const char *name_hint, Stage1ZirInst *is_comptime)
5809{5809{
5810 IrInstSrc *alloca = ir_build_alloca_src(ag, scope, source_node, nullptr, name_hint, is_comptime);5810 Stage1ZirInst *alloca = ir_build_alloca_src(ag, scope, source_node, nullptr, name_hint, is_comptime);
5811 ResultLocVar *var_result_loc = ir_build_var_result_loc(ag, alloca, var);5811 ResultLocVar *var_result_loc = ir_build_var_result_loc(ag, alloca, var);
5812 ir_build_end_expr(ag, scope, source_node, init, &var_result_loc->base);5812 ir_build_end_expr(ag, scope, source_node, init, &var_result_loc->base);
5813 ir_build_var_decl_src(ag, scope, source_node, var, nullptr, alloca);5813 ir_build_var_decl_src(ag, scope, source_node, var, nullptr, alloca);
5814}5814}
58155815
5816static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) {5816static Stage1ZirInst *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) {
5817 assert(node->type == NodeTypeVariableDeclaration);5817 assert(node->type == NodeTypeVariableDeclaration);
58185818
5819 AstNodeVariableDeclaration *variable_declaration = &node->data.variable_declaration;5819 AstNodeVariableDeclaration *variable_declaration = &node->data.variable_declaration;
...@@ -5826,7 +5826,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -5826,7 +5826,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
5826 // Used for the type expr and the align expr5826 // Used for the type expr and the align expr
5827 Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope);5827 Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope);
58285828
5829 IrInstSrc *type_instruction;5829 Stage1ZirInst *type_instruction;
5830 if (variable_declaration->type != nullptr) {5830 if (variable_declaration->type != nullptr) {
5831 type_instruction = astgen_node(ag, variable_declaration->type, comptime_scope);5831 type_instruction = astgen_node(ag, variable_declaration->type, comptime_scope);
5832 if (type_instruction == ag->codegen->invalid_inst_src)5832 if (type_instruction == ag->codegen->invalid_inst_src)
...@@ -5840,10 +5840,10 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -5840,10 +5840,10 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
5840 bool is_extern = variable_declaration->is_extern;5840 bool is_extern = variable_declaration->is_extern;
58415841
5842 bool is_comptime_scalar = ir_should_inline(ag->exec, scope) || variable_declaration->is_comptime;5842 bool is_comptime_scalar = ir_should_inline(ag->exec, scope) || variable_declaration->is_comptime;
5843 IrInstSrc *is_comptime = ir_build_const_bool(ag, scope, node, is_comptime_scalar);5843 Stage1ZirInst *is_comptime = ir_build_const_bool(ag, scope, node, is_comptime_scalar);
5844 ZigVar *var = ir_create_var(ag, node, scope, variable_declaration->symbol,5844 ZigVar *var = ir_create_var(ag, node, scope, variable_declaration->symbol,
5845 is_const, is_const, is_shadowable, is_comptime);5845 is_const, is_const, is_shadowable, is_comptime);
5846 // we detect IrInstSrcDeclVar in gen_block to make sure the next node5846 // we detect Stage1ZirInstDeclVar in gen_block to make sure the next node
5847 // is inside var->child_scope5847 // is inside var->child_scope
58485848
5849 if (!is_extern && !variable_declaration->expr) {5849 if (!is_extern && !variable_declaration->expr) {
...@@ -5852,7 +5852,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -5852,7 +5852,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
5852 return ag->codegen->invalid_inst_src;5852 return ag->codegen->invalid_inst_src;
5853 }5853 }
58545854
5855 IrInstSrc *align_value = nullptr;5855 Stage1ZirInst *align_value = nullptr;
5856 if (variable_declaration->align_expr != nullptr) {5856 if (variable_declaration->align_expr != nullptr) {
5857 align_value = astgen_node(ag, variable_declaration->align_expr, comptime_scope);5857 align_value = astgen_node(ag, variable_declaration->align_expr, comptime_scope);
5858 if (align_value == ag->codegen->invalid_inst_src)5858 if (align_value == ag->codegen->invalid_inst_src)
...@@ -5867,7 +5867,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -5867,7 +5867,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
5867 // Parser should ensure that this never happens5867 // Parser should ensure that this never happens
5868 assert(variable_declaration->threadlocal_tok == 0);5868 assert(variable_declaration->threadlocal_tok == 0);
58695869
5870 IrInstSrc *alloca = ir_build_alloca_src(ag, scope, node, align_value,5870 Stage1ZirInst *alloca = ir_build_alloca_src(ag, scope, node, align_value,
5871 buf_ptr(variable_declaration->symbol), is_comptime);5871 buf_ptr(variable_declaration->symbol), is_comptime);
58725872
5873 // Create a result location for the initialization expression.5873 // Create a result location for the initialization expression.
...@@ -5889,7 +5889,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -5889,7 +5889,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
5889 // so that the struct or enum from the init expression inherits the name.5889 // so that the struct or enum from the init expression inherits the name.
5890 Buf *old_exec_name = ag->exec->name;5890 Buf *old_exec_name = ag->exec->name;
5891 ag->exec->name = variable_declaration->symbol;5891 ag->exec->name = variable_declaration->symbol;
5892 IrInstSrc *init_value = astgen_node_extra(ag, variable_declaration->expr, init_scope,5892 Stage1ZirInst *init_value = astgen_node_extra(ag, variable_declaration->expr, init_scope,
5893 LValNone, init_result_loc);5893 LValNone, init_result_loc);
5894 ag->exec->name = old_exec_name;5894 ag->exec->name = old_exec_name;
58955895
...@@ -5897,7 +5897,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -5897,7 +5897,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
5897 return ag->codegen->invalid_inst_src;5897 return ag->codegen->invalid_inst_src;
58985898
5899 if (result_loc_cast != nullptr) {5899 if (result_loc_cast != nullptr) {
5900 IrInstSrc *implicit_cast = ir_build_implicit_cast(ag, scope, init_value->source_node,5900 Stage1ZirInst *implicit_cast = ir_build_implicit_cast(ag, scope, init_value->source_node,
5901 init_value, result_loc_cast);5901 init_value, result_loc_cast);
5902 ir_build_end_expr(ag, scope, node, implicit_cast, &result_loc_var->base);5902 ir_build_end_expr(ag, scope, node, implicit_cast, &result_loc_var->base);
5903 }5903 }
...@@ -5905,7 +5905,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -5905,7 +5905,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
5905 return ir_build_var_decl_src(ag, scope, node, var, align_value, alloca);5905 return ir_build_var_decl_src(ag, scope, node, var, align_value, alloca);
5906}5906}
59075907
5908static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,5908static Stage1ZirInst *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
5909 ResultLoc *result_loc)5909 ResultLoc *result_loc)
5910{5910{
5911 assert(node->type == NodeTypeWhileExpr);5911 assert(node->type == NodeTypeWhileExpr);
...@@ -5921,7 +5921,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -5921,7 +5921,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
5921 Stage1ZirBasicBlock *else_block = else_node ?5921 Stage1ZirBasicBlock *else_block = else_node ?
5922 ir_create_basic_block(ag, scope, "WhileElse") : end_block;5922 ir_create_basic_block(ag, scope, "WhileElse") : end_block;
59235923
5924 IrInstSrc *is_comptime = ir_build_const_bool(ag, scope, node,5924 Stage1ZirInst *is_comptime = ir_build_const_bool(ag, scope, node,
5925 ir_should_inline(ag->exec, scope) || node->data.while_expr.is_inline);5925 ir_should_inline(ag->exec, scope) || node->data.while_expr.is_inline);
5926 ir_build_br(ag, scope, node, cond_block, is_comptime);5926 ir_build_br(ag, scope, node, cond_block, is_comptime);
59275927
...@@ -5943,15 +5943,15 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -5943,15 +5943,15 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
5943 payload_scope = subexpr_scope;5943 payload_scope = subexpr_scope;
5944 }5944 }
5945 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, payload_scope);5945 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, payload_scope);
5946 IrInstSrc *err_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope,5946 Stage1ZirInst *err_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope,
5947 LValPtr, nullptr);5947 LValPtr, nullptr);
5948 if (err_val_ptr == ag->codegen->invalid_inst_src)5948 if (err_val_ptr == ag->codegen->invalid_inst_src)
5949 return err_val_ptr;5949 return err_val_ptr;
5950 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node->data.while_expr.condition, err_val_ptr,5950 Stage1ZirInst *is_err = ir_build_test_err_src(ag, scope, node->data.while_expr.condition, err_val_ptr,
5951 true, false);5951 true, false);
5952 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;5952 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
5953 IrInstSrc *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);5953 Stage1ZirInst *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);
5954 IrInstSrc *cond_br_inst;5954 Stage1ZirInst *cond_br_inst;
5955 if (!instr_is_unreachable(is_err)) {5955 if (!instr_is_unreachable(is_err)) {
5956 cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, is_err,5956 cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, is_err,
5957 else_block, body_block, is_comptime);5957 else_block, body_block, is_comptime);
...@@ -5965,14 +5965,14 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -5965,14 +5965,14 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
59655965
5966 ir_set_cursor_at_end_and_append_block(ag, body_block);5966 ir_set_cursor_at_end_and_append_block(ag, body_block);
5967 if (var_symbol) {5967 if (var_symbol) {
5968 IrInstSrc *payload_ptr = ir_build_unwrap_err_payload_src(ag, &spill_scope->base, symbol_node,5968 Stage1ZirInst *payload_ptr = ir_build_unwrap_err_payload_src(ag, &spill_scope->base, symbol_node,
5969 err_val_ptr, false, false);5969 err_val_ptr, false, false);
5970 IrInstSrc *var_value = node->data.while_expr.var_is_ptr ?5970 Stage1ZirInst *var_value = node->data.while_expr.var_is_ptr ?
5971 payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, symbol_node, payload_ptr);5971 payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, symbol_node, payload_ptr);
5972 build_decl_var_and_init(ag, payload_scope, symbol_node, payload_var, var_value, buf_ptr(var_symbol), is_comptime);5972 build_decl_var_and_init(ag, payload_scope, symbol_node, payload_var, var_value, buf_ptr(var_symbol), is_comptime);
5973 }5973 }
59745974
5975 ZigList<IrInstSrc *> incoming_values = {0};5975 ZigList<Stage1ZirInst *> incoming_values = {0};
5976 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};5976 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
59775977
5978 if (is_duplicate_label(ag->codegen, payload_scope, node, node->data.while_expr.name))5978 if (is_duplicate_label(ag->codegen, payload_scope, node, node->data.while_expr.name))
...@@ -5991,7 +5991,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -5991,7 +5991,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
5991 // Note the body block of the loop is not the place that lval and result_loc are used -5991 // Note the body block of the loop is not the place that lval and result_loc are used -
5992 // it's actually in break statements, handled similarly to return statements.5992 // it's actually in break statements, handled similarly to return statements.
5993 // That is why we set those values in loop_scope above and not in this astgen_node call.5993 // That is why we set those values in loop_scope above and not in this astgen_node call.
5994 IrInstSrc *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);5994 Stage1ZirInst *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);
5995 if (body_result == ag->codegen->invalid_inst_src)5995 if (body_result == ag->codegen->invalid_inst_src)
5996 return body_result;5996 return body_result;
59975997
...@@ -6006,7 +6006,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6006,7 +6006,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
60066006
6007 if (continue_expr_node) {6007 if (continue_expr_node) {
6008 ir_set_cursor_at_end_and_append_block(ag, continue_block);6008 ir_set_cursor_at_end_and_append_block(ag, continue_block);
6009 IrInstSrc *expr_result = astgen_node(ag, continue_expr_node, payload_scope);6009 Stage1ZirInst *expr_result = astgen_node(ag, continue_expr_node, payload_scope);
6010 if (expr_result == ag->codegen->invalid_inst_src)6010 if (expr_result == ag->codegen->invalid_inst_src)
6011 return expr_result;6011 return expr_result;
6012 if (!instr_is_unreachable(expr_result)) {6012 if (!instr_is_unreachable(expr_result)) {
...@@ -6023,8 +6023,8 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6023,8 +6023,8 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6023 ZigVar *err_var = ir_create_var(ag, err_symbol_node, scope, err_symbol,6023 ZigVar *err_var = ir_create_var(ag, err_symbol_node, scope, err_symbol,
6024 true, false, false, is_comptime);6024 true, false, false, is_comptime);
6025 Scope *err_scope = err_var->child_scope;6025 Scope *err_scope = err_var->child_scope;
6026 IrInstSrc *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, err_symbol_node, err_val_ptr);6026 Stage1ZirInst *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, err_symbol_node, err_val_ptr);
6027 IrInstSrc *err_value = ir_build_load_ptr(ag, err_scope, err_symbol_node, err_ptr);6027 Stage1ZirInst *err_value = ir_build_load_ptr(ag, err_scope, err_symbol_node, err_ptr);
6028 build_decl_var_and_init(ag, err_scope, err_symbol_node, err_var, err_value, buf_ptr(err_symbol), is_comptime);6028 build_decl_var_and_init(ag, err_scope, err_symbol_node, err_var, err_value, buf_ptr(err_symbol), is_comptime);
60296029
6030 if (peer_parent->peers.length != 0) {6030 if (peer_parent->peers.length != 0) {
...@@ -6032,7 +6032,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6032,7 +6032,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6032 }6032 }
6033 ResultLocPeer *peer_result = create_peer_result(peer_parent);6033 ResultLocPeer *peer_result = create_peer_result(peer_parent);
6034 peer_parent->peers.append(peer_result);6034 peer_parent->peers.append(peer_result);
6035 IrInstSrc *else_result = astgen_node_extra(ag, else_node, err_scope, lval, &peer_result->base);6035 Stage1ZirInst *else_result = astgen_node_extra(ag, else_node, err_scope, lval, &peer_result->base);
6036 if (else_result == ag->codegen->invalid_inst_src)6036 if (else_result == ag->codegen->invalid_inst_src)
6037 return else_result;6037 return else_result;
6038 if (!instr_is_unreachable(else_result))6038 if (!instr_is_unreachable(else_result))
...@@ -6050,7 +6050,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6050,7 +6050,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6050 peer_parent->peers.last()->next_bb = end_block;6050 peer_parent->peers.last()->next_bb = end_block;
6051 }6051 }
60526052
6053 IrInstSrc *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,6053 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,
6054 incoming_blocks.items, incoming_values.items, peer_parent);6054 incoming_blocks.items, incoming_values.items, peer_parent);
6055 return ir_expr_wrap(ag, scope, phi, result_loc);6055 return ir_expr_wrap(ag, scope, phi, result_loc);
6056 } else if (var_symbol != nullptr) {6056 } else if (var_symbol != nullptr) {
...@@ -6063,15 +6063,15 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6063,15 +6063,15 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6063 true, false, false, is_comptime);6063 true, false, false, is_comptime);
6064 Scope *child_scope = payload_var->child_scope;6064 Scope *child_scope = payload_var->child_scope;
6065 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, child_scope);6065 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, child_scope);
6066 IrInstSrc *maybe_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope,6066 Stage1ZirInst *maybe_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope,
6067 LValPtr, nullptr);6067 LValPtr, nullptr);
6068 if (maybe_val_ptr == ag->codegen->invalid_inst_src)6068 if (maybe_val_ptr == ag->codegen->invalid_inst_src)
6069 return maybe_val_ptr;6069 return maybe_val_ptr;
6070 IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node->data.while_expr.condition, maybe_val_ptr);6070 Stage1ZirInst *maybe_val = ir_build_load_ptr(ag, scope, node->data.while_expr.condition, maybe_val_ptr);
6071 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node->data.while_expr.condition, maybe_val);6071 Stage1ZirInst *is_non_null = ir_build_test_non_null_src(ag, scope, node->data.while_expr.condition, maybe_val);
6072 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;6072 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
6073 IrInstSrc *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);6073 Stage1ZirInst *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);
6074 IrInstSrc *cond_br_inst;6074 Stage1ZirInst *cond_br_inst;
6075 if (!instr_is_unreachable(is_non_null)) {6075 if (!instr_is_unreachable(is_non_null)) {
6076 cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, is_non_null,6076 cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, is_non_null,
6077 body_block, else_block, is_comptime);6077 body_block, else_block, is_comptime);
...@@ -6084,12 +6084,12 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6084,12 +6084,12 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6084 is_comptime);6084 is_comptime);
60856085
6086 ir_set_cursor_at_end_and_append_block(ag, body_block);6086 ir_set_cursor_at_end_and_append_block(ag, body_block);
6087 IrInstSrc *payload_ptr = ir_build_optional_unwrap_ptr(ag, &spill_scope->base, symbol_node, maybe_val_ptr, false);6087 Stage1ZirInst *payload_ptr = ir_build_optional_unwrap_ptr(ag, &spill_scope->base, symbol_node, maybe_val_ptr, false);
6088 IrInstSrc *var_value = node->data.while_expr.var_is_ptr ?6088 Stage1ZirInst *var_value = node->data.while_expr.var_is_ptr ?
6089 payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, symbol_node, payload_ptr);6089 payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, symbol_node, payload_ptr);
6090 build_decl_var_and_init(ag, child_scope, symbol_node, payload_var, var_value, buf_ptr(var_symbol), is_comptime);6090 build_decl_var_and_init(ag, child_scope, symbol_node, payload_var, var_value, buf_ptr(var_symbol), is_comptime);
60916091
6092 ZigList<IrInstSrc *> incoming_values = {0};6092 ZigList<Stage1ZirInst *> incoming_values = {0};
6093 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};6093 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
60946094
6095 if (is_duplicate_label(ag->codegen, child_scope, node, node->data.while_expr.name))6095 if (is_duplicate_label(ag->codegen, child_scope, node, node->data.while_expr.name))
...@@ -6108,7 +6108,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6108,7 +6108,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6108 // Note the body block of the loop is not the place that lval and result_loc are used -6108 // Note the body block of the loop is not the place that lval and result_loc are used -
6109 // it's actually in break statements, handled similarly to return statements.6109 // it's actually in break statements, handled similarly to return statements.
6110 // That is why we set those values in loop_scope above and not in this astgen_node call.6110 // That is why we set those values in loop_scope above and not in this astgen_node call.
6111 IrInstSrc *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);6111 Stage1ZirInst *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);
6112 if (body_result == ag->codegen->invalid_inst_src)6112 if (body_result == ag->codegen->invalid_inst_src)
6113 return body_result;6113 return body_result;
61146114
...@@ -6123,7 +6123,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6123,7 +6123,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
61236123
6124 if (continue_expr_node) {6124 if (continue_expr_node) {
6125 ir_set_cursor_at_end_and_append_block(ag, continue_block);6125 ir_set_cursor_at_end_and_append_block(ag, continue_block);
6126 IrInstSrc *expr_result = astgen_node(ag, continue_expr_node, child_scope);6126 Stage1ZirInst *expr_result = astgen_node(ag, continue_expr_node, child_scope);
6127 if (expr_result == ag->codegen->invalid_inst_src)6127 if (expr_result == ag->codegen->invalid_inst_src)
6128 return expr_result;6128 return expr_result;
6129 if (!instr_is_unreachable(expr_result)) {6129 if (!instr_is_unreachable(expr_result)) {
...@@ -6132,7 +6132,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6132,7 +6132,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6132 }6132 }
6133 }6133 }
61346134
6135 IrInstSrc *else_result = nullptr;6135 Stage1ZirInst *else_result = nullptr;
6136 if (else_node) {6136 if (else_node) {
6137 ir_set_cursor_at_end_and_append_block(ag, else_block);6137 ir_set_cursor_at_end_and_append_block(ag, else_block);
61386138
...@@ -6160,17 +6160,17 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6160,17 +6160,17 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6160 peer_parent->peers.last()->next_bb = end_block;6160 peer_parent->peers.last()->next_bb = end_block;
6161 }6161 }
61626162
6163 IrInstSrc *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,6163 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,
6164 incoming_blocks.items, incoming_values.items, peer_parent);6164 incoming_blocks.items, incoming_values.items, peer_parent);
6165 return ir_expr_wrap(ag, scope, phi, result_loc);6165 return ir_expr_wrap(ag, scope, phi, result_loc);
6166 } else {6166 } else {
6167 ir_set_cursor_at_end_and_append_block(ag, cond_block);6167 ir_set_cursor_at_end_and_append_block(ag, cond_block);
6168 IrInstSrc *cond_val = astgen_node(ag, node->data.while_expr.condition, scope);6168 Stage1ZirInst *cond_val = astgen_node(ag, node->data.while_expr.condition, scope);
6169 if (cond_val == ag->codegen->invalid_inst_src)6169 if (cond_val == ag->codegen->invalid_inst_src)
6170 return cond_val;6170 return cond_val;
6171 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;6171 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
6172 IrInstSrc *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);6172 Stage1ZirInst *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);
6173 IrInstSrc *cond_br_inst;6173 Stage1ZirInst *cond_br_inst;
6174 if (!instr_is_unreachable(cond_val)) {6174 if (!instr_is_unreachable(cond_val)) {
6175 cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, cond_val,6175 cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, cond_val,
6176 body_block, else_block, is_comptime);6176 body_block, else_block, is_comptime);
...@@ -6183,7 +6183,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6183,7 +6183,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6183 is_comptime);6183 is_comptime);
6184 ir_set_cursor_at_end_and_append_block(ag, body_block);6184 ir_set_cursor_at_end_and_append_block(ag, body_block);
61856185
6186 ZigList<IrInstSrc *> incoming_values = {0};6186 ZigList<Stage1ZirInst *> incoming_values = {0};
6187 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};6187 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
61886188
6189 Scope *subexpr_scope = create_runtime_scope(ag->codegen, node, scope, is_comptime);6189 Scope *subexpr_scope = create_runtime_scope(ag->codegen, node, scope, is_comptime);
...@@ -6203,7 +6203,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6203,7 +6203,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6203 // Note the body block of the loop is not the place that lval and result_loc are used -6203 // Note the body block of the loop is not the place that lval and result_loc are used -
6204 // it's actually in break statements, handled similarly to return statements.6204 // it's actually in break statements, handled similarly to return statements.
6205 // That is why we set those values in loop_scope above and not in this astgen_node call.6205 // That is why we set those values in loop_scope above and not in this astgen_node call.
6206 IrInstSrc *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);6206 Stage1ZirInst *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);
6207 if (body_result == ag->codegen->invalid_inst_src)6207 if (body_result == ag->codegen->invalid_inst_src)
6208 return body_result;6208 return body_result;
62096209
...@@ -6218,7 +6218,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6218,7 +6218,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
62186218
6219 if (continue_expr_node) {6219 if (continue_expr_node) {
6220 ir_set_cursor_at_end_and_append_block(ag, continue_block);6220 ir_set_cursor_at_end_and_append_block(ag, continue_block);
6221 IrInstSrc *expr_result = astgen_node(ag, continue_expr_node, subexpr_scope);6221 Stage1ZirInst *expr_result = astgen_node(ag, continue_expr_node, subexpr_scope);
6222 if (expr_result == ag->codegen->invalid_inst_src)6222 if (expr_result == ag->codegen->invalid_inst_src)
6223 return expr_result;6223 return expr_result;
6224 if (!instr_is_unreachable(expr_result)) {6224 if (!instr_is_unreachable(expr_result)) {
...@@ -6227,7 +6227,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6227,7 +6227,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6227 }6227 }
6228 }6228 }
62296229
6230 IrInstSrc *else_result = nullptr;6230 Stage1ZirInst *else_result = nullptr;
6231 if (else_node) {6231 if (else_node) {
6232 ir_set_cursor_at_end_and_append_block(ag, else_block);6232 ir_set_cursor_at_end_and_append_block(ag, else_block);
62336233
...@@ -6256,13 +6256,13 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6256,13 +6256,13 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6256 peer_parent->peers.last()->next_bb = end_block;6256 peer_parent->peers.last()->next_bb = end_block;
6257 }6257 }
62586258
6259 IrInstSrc *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,6259 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,
6260 incoming_blocks.items, incoming_values.items, peer_parent);6260 incoming_blocks.items, incoming_values.items, peer_parent);
6261 return ir_expr_wrap(ag, scope, phi, result_loc);6261 return ir_expr_wrap(ag, scope, phi, result_loc);
6262 }6262 }
6263}6263}
62646264
6265static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,6265static Stage1ZirInst *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,
6266 ResultLoc *result_loc)6266 ResultLoc *result_loc)
6267{6267{
6268 assert(node->type == NodeTypeForExpr);6268 assert(node->type == NodeTypeForExpr);
...@@ -6281,11 +6281,11 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -6281,11 +6281,11 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
62816281
6282 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, parent_scope);6282 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, parent_scope);
62836283
6284 IrInstSrc *array_val_ptr = astgen_node_extra(ag, array_node, &spill_scope->base, LValPtr, nullptr);6284 Stage1ZirInst *array_val_ptr = astgen_node_extra(ag, array_node, &spill_scope->base, LValPtr, nullptr);
6285 if (array_val_ptr == ag->codegen->invalid_inst_src)6285 if (array_val_ptr == ag->codegen->invalid_inst_src)
6286 return array_val_ptr;6286 return array_val_ptr;
62876287
6288 IrInstSrc *is_comptime = ir_build_const_bool(ag, parent_scope, node,6288 Stage1ZirInst *is_comptime = ir_build_const_bool(ag, parent_scope, node,
6289 ir_should_inline(ag->exec, parent_scope) || node->data.for_expr.is_inline);6289 ir_should_inline(ag->exec, parent_scope) || node->data.for_expr.is_inline);
62906290
6291 AstNode *index_var_source_node;6291 AstNode *index_var_source_node;
...@@ -6302,12 +6302,12 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -6302,12 +6302,12 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
6302 index_var_name = "i";6302 index_var_name = "i";
6303 }6303 }
63046304
6305 IrInstSrc *zero = ir_build_const_usize(ag, parent_scope, node, 0);6305 Stage1ZirInst *zero = ir_build_const_usize(ag, parent_scope, node, 0);
6306 build_decl_var_and_init(ag, parent_scope, index_var_source_node, index_var, zero, index_var_name, is_comptime);6306 build_decl_var_and_init(ag, parent_scope, index_var_source_node, index_var, zero, index_var_name, is_comptime);
6307 parent_scope = index_var->child_scope;6307 parent_scope = index_var->child_scope;
63086308
6309 IrInstSrc *one = ir_build_const_usize(ag, parent_scope, node, 1);6309 Stage1ZirInst *one = ir_build_const_usize(ag, parent_scope, node, 1);
6310 IrInstSrc *index_ptr = ir_build_var_ptr(ag, parent_scope, node, index_var);6310 Stage1ZirInst *index_ptr = ir_build_var_ptr(ag, parent_scope, node, index_var);
63116311
63126312
6313 Stage1ZirBasicBlock *cond_block = ir_create_basic_block(ag, parent_scope, "ForCond");6313 Stage1ZirBasicBlock *cond_block = ir_create_basic_block(ag, parent_scope, "ForCond");
...@@ -6317,36 +6317,36 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -6317,36 +6317,36 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
6317 Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, parent_scope, "ForContinue");6317 Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, parent_scope, "ForContinue");
63186318
6319 Buf *len_field_name = buf_create_from_str("len");6319 Buf *len_field_name = buf_create_from_str("len");
6320 IrInstSrc *len_ref = ir_build_field_ptr(ag, parent_scope, node, array_val_ptr, len_field_name, false);6320 Stage1ZirInst *len_ref = ir_build_field_ptr(ag, parent_scope, node, array_val_ptr, len_field_name, false);
6321 IrInstSrc *len_val = ir_build_load_ptr(ag, &spill_scope->base, node, len_ref);6321 Stage1ZirInst *len_val = ir_build_load_ptr(ag, &spill_scope->base, node, len_ref);
6322 ir_build_br(ag, parent_scope, node, cond_block, is_comptime);6322 ir_build_br(ag, parent_scope, node, cond_block, is_comptime);
63236323
6324 ir_set_cursor_at_end_and_append_block(ag, cond_block);6324 ir_set_cursor_at_end_and_append_block(ag, cond_block);
6325 IrInstSrc *index_val = ir_build_load_ptr(ag, &spill_scope->base, node, index_ptr);6325 Stage1ZirInst *index_val = ir_build_load_ptr(ag, &spill_scope->base, node, index_ptr);
6326 IrInstSrc *cond = ir_build_bin_op(ag, parent_scope, node, IrBinOpCmpLessThan, index_val, len_val, false);6326 Stage1ZirInst *cond = ir_build_bin_op(ag, parent_scope, node, IrBinOpCmpLessThan, index_val, len_val, false);
6327 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;6327 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
6328 IrInstSrc *void_else_value = else_node ? nullptr : ir_build_const_void(ag, parent_scope, node);6328 Stage1ZirInst *void_else_value = else_node ? nullptr : ir_build_const_void(ag, parent_scope, node);
6329 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, cond,6329 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, cond,
6330 body_block, else_block, is_comptime);6330 body_block, else_block, is_comptime);
63316331
6332 ResultLocPeerParent *peer_parent = ir_build_result_peers(ag, cond_br_inst, end_block, result_loc, is_comptime);6332 ResultLocPeerParent *peer_parent = ir_build_result_peers(ag, cond_br_inst, end_block, result_loc, is_comptime);
63336333
6334 ir_set_cursor_at_end_and_append_block(ag, body_block);6334 ir_set_cursor_at_end_and_append_block(ag, body_block);
6335 IrInstSrc *elem_ptr = ir_build_elem_ptr(ag, &spill_scope->base, node, array_val_ptr, index_val,6335 Stage1ZirInst *elem_ptr = ir_build_elem_ptr(ag, &spill_scope->base, node, array_val_ptr, index_val,
6336 false, PtrLenSingle, nullptr);6336 false, PtrLenSingle, nullptr);
6337 // TODO make it an error to write to element variable or i variable.6337 // TODO make it an error to write to element variable or i variable.
6338 Buf *elem_var_name = node_identifier_buf(elem_node);6338 Buf *elem_var_name = node_identifier_buf(elem_node);
6339 ZigVar *elem_var = ir_create_var(ag, elem_node, parent_scope, elem_var_name, true, false, false, is_comptime);6339 ZigVar *elem_var = ir_create_var(ag, elem_node, parent_scope, elem_var_name, true, false, false, is_comptime);
6340 Scope *child_scope = elem_var->child_scope;6340 Scope *child_scope = elem_var->child_scope;
63416341
6342 IrInstSrc *elem_value = node->data.for_expr.elem_is_ptr ?6342 Stage1ZirInst *elem_value = node->data.for_expr.elem_is_ptr ?
6343 elem_ptr : ir_build_load_ptr(ag, &spill_scope->base, elem_node, elem_ptr);6343 elem_ptr : ir_build_load_ptr(ag, &spill_scope->base, elem_node, elem_ptr);
6344 build_decl_var_and_init(ag, parent_scope, elem_node, elem_var, elem_value, buf_ptr(elem_var_name), is_comptime);6344 build_decl_var_and_init(ag, parent_scope, elem_node, elem_var, elem_value, buf_ptr(elem_var_name), is_comptime);
63456345
6346 if (is_duplicate_label(ag->codegen, child_scope, node, node->data.for_expr.name))6346 if (is_duplicate_label(ag->codegen, child_scope, node, node->data.for_expr.name))
6347 return ag->codegen->invalid_inst_src;6347 return ag->codegen->invalid_inst_src;
63486348
6349 ZigList<IrInstSrc *> incoming_values = {0};6349 ZigList<Stage1ZirInst *> incoming_values = {0};
6350 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};6350 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
6351 ScopeLoop *loop_scope = create_loop_scope(ag->codegen, node, child_scope);6351 ScopeLoop *loop_scope = create_loop_scope(ag->codegen, node, child_scope);
6352 loop_scope->break_block = end_block;6352 loop_scope->break_block = end_block;
...@@ -6361,7 +6361,7 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -6361,7 +6361,7 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
6361 // Note the body block of the loop is not the place that lval and result_loc are used -6361 // Note the body block of the loop is not the place that lval and result_loc are used -
6362 // it's actually in break statements, handled similarly to return statements.6362 // it's actually in break statements, handled similarly to return statements.
6363 // That is why we set those values in loop_scope above and not in this astgen_node call.6363 // That is why we set those values in loop_scope above and not in this astgen_node call.
6364 IrInstSrc *body_result = astgen_node(ag, body_node, &loop_scope->base);6364 Stage1ZirInst *body_result = astgen_node(ag, body_node, &loop_scope->base);
6365 if (body_result == ag->codegen->invalid_inst_src)6365 if (body_result == ag->codegen->invalid_inst_src)
6366 return ag->codegen->invalid_inst_src;6366 return ag->codegen->invalid_inst_src;
63676367
...@@ -6375,11 +6375,11 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -6375,11 +6375,11 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
6375 }6375 }
63766376
6377 ir_set_cursor_at_end_and_append_block(ag, continue_block);6377 ir_set_cursor_at_end_and_append_block(ag, continue_block);
6378 IrInstSrc *new_index_val = ir_build_bin_op(ag, child_scope, node, IrBinOpAdd, index_val, one, false);6378 Stage1ZirInst *new_index_val = ir_build_bin_op(ag, child_scope, node, IrBinOpAdd, index_val, one, false);
6379 ir_build_store_ptr(ag, child_scope, node, index_ptr, new_index_val)->allow_write_through_const = true;6379 ir_build_store_ptr(ag, child_scope, node, index_ptr, new_index_val)->allow_write_through_const = true;
6380 ir_build_br(ag, child_scope, node, cond_block, is_comptime);6380 ir_build_br(ag, child_scope, node, cond_block, is_comptime);
63816381
6382 IrInstSrc *else_result = nullptr;6382 Stage1ZirInst *else_result = nullptr;
6383 if (else_node) {6383 if (else_node) {
6384 ir_set_cursor_at_end_and_append_block(ag, else_block);6384 ir_set_cursor_at_end_and_append_block(ag, else_block);
63856385
...@@ -6408,17 +6408,17 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -6408,17 +6408,17 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
6408 peer_parent->peers.last()->next_bb = end_block;6408 peer_parent->peers.last()->next_bb = end_block;
6409 }6409 }
64106410
6411 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, incoming_blocks.length,6411 Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, node, incoming_blocks.length,
6412 incoming_blocks.items, incoming_values.items, peer_parent);6412 incoming_blocks.items, incoming_values.items, peer_parent);
6413 return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc);6413 return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc);
6414}6414}
64156415
6416static IrInstSrc *astgen_bool_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {6416static Stage1ZirInst *astgen_bool_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6417 assert(node->type == NodeTypeBoolLiteral);6417 assert(node->type == NodeTypeBoolLiteral);
6418 return ir_build_const_bool(ag, scope, node, node->data.bool_literal.value);6418 return ir_build_const_bool(ag, scope, node, node->data.bool_literal.value);
6419}6419}
64206420
6421static IrInstSrc *astgen_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {6421static Stage1ZirInst *astgen_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6422 assert(node->type == NodeTypeEnumLiteral);6422 assert(node->type == NodeTypeEnumLiteral);
6423 // Currently, stage1 runs astgen for every comptime function call,6423 // Currently, stage1 runs astgen for every comptime function call,
6424 // resulting the allocation here wasting memory. As a workaround until6424 // resulting the allocation here wasting memory. As a workaround until
...@@ -6431,7 +6431,7 @@ static IrInstSrc *astgen_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -6431,7 +6431,7 @@ static IrInstSrc *astgen_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *n
6431 return ir_build_const_enum_literal(ag, scope, node, node->data.enum_literal.name);6431 return ir_build_const_enum_literal(ag, scope, node, node->data.enum_literal.name);
6432}6432}
64336433
6434static IrInstSrc *astgen_string_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {6434static Stage1ZirInst *astgen_string_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6435 Error err;6435 Error err;
6436 assert(node->type == NodeTypeStringLiteral);6436 assert(node->type == NodeTypeStringLiteral);
64376437
...@@ -6473,7 +6473,7 @@ static IrInstSrc *astgen_string_literal(Stage1AstGen *ag, Scope *scope, AstNode...@@ -6473,7 +6473,7 @@ static IrInstSrc *astgen_string_literal(Stage1AstGen *ag, Scope *scope, AstNode
6473 return ir_build_const_str_lit(ag, scope, node, str);6473 return ir_build_const_str_lit(ag, scope, node, str);
6474}6474}
64756475
6476static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {6476static Stage1ZirInst *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6477 assert(node->type == NodeTypeArrayType);6477 assert(node->type == NodeTypeArrayType);
64786478
6479 AstNode *size_node = node->data.array_type.size;6479 AstNode *size_node = node->data.array_type.size;
...@@ -6486,7 +6486,7 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6486,7 +6486,7 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod
64866486
6487 Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope);6487 Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope);
64886488
6489 IrInstSrc *sentinel;6489 Stage1ZirInst *sentinel;
6490 if (sentinel_expr != nullptr) {6490 if (sentinel_expr != nullptr) {
6491 sentinel = astgen_node(ag, sentinel_expr, comptime_scope);6491 sentinel = astgen_node(ag, sentinel_expr, comptime_scope);
6492 if (sentinel == ag->codegen->invalid_inst_src)6492 if (sentinel == ag->codegen->invalid_inst_src)
...@@ -6513,17 +6513,17 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6513,17 +6513,17 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod
6513 return ag->codegen->invalid_inst_src;6513 return ag->codegen->invalid_inst_src;
6514 }6514 }
65156515
6516 IrInstSrc *size_value = astgen_node(ag, size_node, comptime_scope);6516 Stage1ZirInst *size_value = astgen_node(ag, size_node, comptime_scope);
6517 if (size_value == ag->codegen->invalid_inst_src)6517 if (size_value == ag->codegen->invalid_inst_src)
6518 return size_value;6518 return size_value;
65196519
6520 IrInstSrc *child_type = astgen_node(ag, child_type_node, comptime_scope);6520 Stage1ZirInst *child_type = astgen_node(ag, child_type_node, comptime_scope);
6521 if (child_type == ag->codegen->invalid_inst_src)6521 if (child_type == ag->codegen->invalid_inst_src)
6522 return child_type;6522 return child_type;
65236523
6524 return ir_build_array_type(ag, scope, node, size_value, sentinel, child_type);6524 return ir_build_array_type(ag, scope, node, size_value, sentinel, child_type);
6525 } else {6525 } else {
6526 IrInstSrc *align_value;6526 Stage1ZirInst *align_value;
6527 if (align_expr != nullptr) {6527 if (align_expr != nullptr) {
6528 align_value = astgen_node(ag, align_expr, comptime_scope);6528 align_value = astgen_node(ag, align_expr, comptime_scope);
6529 if (align_value == ag->codegen->invalid_inst_src)6529 if (align_value == ag->codegen->invalid_inst_src)
...@@ -6532,7 +6532,7 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6532,7 +6532,7 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod
6532 align_value = nullptr;6532 align_value = nullptr;
6533 }6533 }
65346534
6535 IrInstSrc *child_type = astgen_node(ag, child_type_node, comptime_scope);6535 Stage1ZirInst *child_type = astgen_node(ag, child_type_node, comptime_scope);
6536 if (child_type == ag->codegen->invalid_inst_src)6536 if (child_type == ag->codegen->invalid_inst_src)
6537 return child_type;6537 return child_type;
65386538
...@@ -6541,11 +6541,11 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6541,11 +6541,11 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod
6541 }6541 }
6542}6542}
65436543
6544static IrInstSrc *astgen_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {6544static Stage1ZirInst *astgen_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6545 assert(node->type == NodeTypeAnyFrameType);6545 assert(node->type == NodeTypeAnyFrameType);
65466546
6547 AstNode *payload_type_node = node->data.anyframe_type.payload_type;6547 AstNode *payload_type_node = node->data.anyframe_type.payload_type;
6548 IrInstSrc *payload_type_value = nullptr;6548 Stage1ZirInst *payload_type_value = nullptr;
65496549
6550 if (payload_type_node != nullptr) {6550 if (payload_type_node != nullptr) {
6551 payload_type_value = astgen_node(ag, payload_type_node, scope);6551 payload_type_value = astgen_node(ag, payload_type_node, scope);
...@@ -6557,16 +6557,16 @@ static IrInstSrc *astgen_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -6557,16 +6557,16 @@ static IrInstSrc *astgen_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *
6557 return ir_build_anyframe_type(ag, scope, node, payload_type_value);6557 return ir_build_anyframe_type(ag, scope, node, payload_type_value);
6558}6558}
65596559
6560static IrInstSrc *astgen_undefined_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {6560static Stage1ZirInst *astgen_undefined_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6561 assert(node->type == NodeTypeUndefinedLiteral);6561 assert(node->type == NodeTypeUndefinedLiteral);
6562 return ir_build_const_undefined(ag, scope, node);6562 return ir_build_const_undefined(ag, scope, node);
6563}6563}
65646564
6565static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node) {6565static Stage1ZirInst *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6566 assert(node->type == NodeTypeAsmExpr);6566 assert(node->type == NodeTypeAsmExpr);
6567 AstNodeAsmExpr *asm_expr = &node->data.asm_expr;6567 AstNodeAsmExpr *asm_expr = &node->data.asm_expr;
65686568
6569 IrInstSrc *asm_template = astgen_node(ag, asm_expr->asm_template, scope);6569 Stage1ZirInst *asm_template = astgen_node(ag, asm_expr->asm_template, scope);
6570 if (asm_template == ag->codegen->invalid_inst_src)6570 if (asm_template == ag->codegen->invalid_inst_src)
6571 return ag->codegen->invalid_inst_src;6571 return ag->codegen->invalid_inst_src;
65726572
...@@ -6592,8 +6592,8 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -6592,8 +6592,8 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)
6592 nullptr, 0, is_volatile, true);6592 nullptr, 0, is_volatile, true);
6593 }6593 }
65946594
6595 IrInstSrc **input_list = heap::c_allocator.allocate<IrInstSrc *>(asm_expr->input_list.length);6595 Stage1ZirInst **input_list = heap::c_allocator.allocate<Stage1ZirInst *>(asm_expr->input_list.length);
6596 IrInstSrc **output_types = heap::c_allocator.allocate<IrInstSrc *>(asm_expr->output_list.length);6596 Stage1ZirInst **output_types = heap::c_allocator.allocate<Stage1ZirInst *>(asm_expr->output_list.length);
6597 ZigVar **output_vars = heap::c_allocator.allocate<ZigVar *>(asm_expr->output_list.length);6597 ZigVar **output_vars = heap::c_allocator.allocate<ZigVar *>(asm_expr->output_list.length);
6598 size_t return_count = 0;6598 size_t return_count = 0;
6599 if (!is_volatile && asm_expr->output_list.length == 0) {6599 if (!is_volatile && asm_expr->output_list.length == 0) {
...@@ -6606,7 +6606,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -6606,7 +6606,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)
6606 if (asm_output->return_type) {6606 if (asm_output->return_type) {
6607 return_count += 1;6607 return_count += 1;
66086608
6609 IrInstSrc *return_type = astgen_node(ag, asm_output->return_type, scope);6609 Stage1ZirInst *return_type = astgen_node(ag, asm_output->return_type, scope);
6610 if (return_type == ag->codegen->invalid_inst_src)6610 if (return_type == ag->codegen->invalid_inst_src)
6611 return ag->codegen->invalid_inst_src;6611 return ag->codegen->invalid_inst_src;
6612 if (return_count > 1) {6612 if (return_count > 1) {
...@@ -6640,7 +6640,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -6640,7 +6640,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)
6640 }6640 }
6641 for (size_t i = 0; i < asm_expr->input_list.length; i += 1) {6641 for (size_t i = 0; i < asm_expr->input_list.length; i += 1) {
6642 AsmInput *asm_input = asm_expr->input_list.at(i);6642 AsmInput *asm_input = asm_expr->input_list.at(i);
6643 IrInstSrc *input_value = astgen_node(ag, asm_input->expr, scope);6643 Stage1ZirInst *input_value = astgen_node(ag, asm_input->expr, scope);
6644 if (input_value == ag->codegen->invalid_inst_src)6644 if (input_value == ag->codegen->invalid_inst_src)
6645 return ag->codegen->invalid_inst_src;6645 return ag->codegen->invalid_inst_src;
66466646
...@@ -6651,7 +6651,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -6651,7 +6651,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)
6651 output_vars, return_count, is_volatile, false);6651 output_vars, return_count, is_volatile, false);
6652}6652}
66536653
6654static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,6654static Stage1ZirInst *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
6655 ResultLoc *result_loc)6655 ResultLoc *result_loc)
6656{6656{
6657 assert(node->type == NodeTypeIfOptional);6657 assert(node->type == NodeTypeIfOptional);
...@@ -6665,24 +6665,24 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod...@@ -6665,24 +6665,24 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
6665 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, expr_node, scope);6665 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, expr_node, scope);
6666 spill_scope->spill_harder = true;6666 spill_scope->spill_harder = true;
66676667
6668 IrInstSrc *maybe_val_ptr = astgen_node_extra(ag, expr_node, &spill_scope->base, LValPtr, nullptr);6668 Stage1ZirInst *maybe_val_ptr = astgen_node_extra(ag, expr_node, &spill_scope->base, LValPtr, nullptr);
6669 if (maybe_val_ptr == ag->codegen->invalid_inst_src)6669 if (maybe_val_ptr == ag->codegen->invalid_inst_src)
6670 return maybe_val_ptr;6670 return maybe_val_ptr;
66716671
6672 IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node, maybe_val_ptr);6672 Stage1ZirInst *maybe_val = ir_build_load_ptr(ag, scope, node, maybe_val_ptr);
6673 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node, maybe_val);6673 Stage1ZirInst *is_non_null = ir_build_test_non_null_src(ag, scope, node, maybe_val);
66746674
6675 Stage1ZirBasicBlock *then_block = ir_create_basic_block(ag, scope, "OptionalThen");6675 Stage1ZirBasicBlock *then_block = ir_create_basic_block(ag, scope, "OptionalThen");
6676 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "OptionalElse");6676 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "OptionalElse");
6677 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "OptionalEndIf");6677 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "OptionalEndIf");
66786678
6679 IrInstSrc *is_comptime;6679 Stage1ZirInst *is_comptime;
6680 if (ir_should_inline(ag->exec, scope)) {6680 if (ir_should_inline(ag->exec, scope)) {
6681 is_comptime = ir_build_const_bool(ag, scope, node, true);6681 is_comptime = ir_build_const_bool(ag, scope, node, true);
6682 } else {6682 } else {
6683 is_comptime = ir_build_test_comptime(ag, scope, node, is_non_null);6683 is_comptime = ir_build_test_comptime(ag, scope, node, is_non_null);
6684 }6684 }
6685 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, is_non_null,6685 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, scope, node, is_non_null,
6686 then_block, else_block, is_comptime);6686 then_block, else_block, is_comptime);
66876687
6688 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block,6688 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block,
...@@ -6698,15 +6698,15 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod...@@ -6698,15 +6698,15 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
6698 ZigVar *var = ir_create_var(ag, node, subexpr_scope,6698 ZigVar *var = ir_create_var(ag, node, subexpr_scope,
6699 var_symbol, is_const, is_const, is_shadowable, is_comptime);6699 var_symbol, is_const, is_const, is_shadowable, is_comptime);
67006700
6701 IrInstSrc *payload_ptr = ir_build_optional_unwrap_ptr(ag, subexpr_scope, node, maybe_val_ptr, false);6701 Stage1ZirInst *payload_ptr = ir_build_optional_unwrap_ptr(ag, subexpr_scope, node, maybe_val_ptr, false);
6702 IrInstSrc *var_value = var_is_ptr ?6702 Stage1ZirInst *var_value = var_is_ptr ?
6703 payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, node, payload_ptr);6703 payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, node, payload_ptr);
6704 build_decl_var_and_init(ag, subexpr_scope, node, var, var_value, buf_ptr(var_symbol), is_comptime);6704 build_decl_var_and_init(ag, subexpr_scope, node, var, var_value, buf_ptr(var_symbol), is_comptime);
6705 var_scope = var->child_scope;6705 var_scope = var->child_scope;
6706 } else {6706 } else {
6707 var_scope = subexpr_scope;6707 var_scope = subexpr_scope;
6708 }6708 }
6709 IrInstSrc *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval,6709 Stage1ZirInst *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval,
6710 &peer_parent->peers.at(0)->base);6710 &peer_parent->peers.at(0)->base);
6711 if (then_expr_result == ag->codegen->invalid_inst_src)6711 if (then_expr_result == ag->codegen->invalid_inst_src)
6712 return then_expr_result;6712 return then_expr_result;
...@@ -6715,7 +6715,7 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod...@@ -6715,7 +6715,7 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
6715 ir_build_br(ag, scope, node, endif_block, is_comptime);6715 ir_build_br(ag, scope, node, endif_block, is_comptime);
67166716
6717 ir_set_cursor_at_end_and_append_block(ag, else_block);6717 ir_set_cursor_at_end_and_append_block(ag, else_block);
6718 IrInstSrc *else_expr_result;6718 Stage1ZirInst *else_expr_result;
6719 if (else_node) {6719 if (else_node) {
6720 else_expr_result = astgen_node_extra(ag, else_node, subexpr_scope, lval, &peer_parent->peers.at(1)->base);6720 else_expr_result = astgen_node_extra(ag, else_node, subexpr_scope, lval, &peer_parent->peers.at(1)->base);
6721 if (else_expr_result == ag->codegen->invalid_inst_src)6721 if (else_expr_result == ag->codegen->invalid_inst_src)
...@@ -6729,18 +6729,18 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod...@@ -6729,18 +6729,18 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
6729 ir_build_br(ag, scope, node, endif_block, is_comptime);6729 ir_build_br(ag, scope, node, endif_block, is_comptime);
67306730
6731 ir_set_cursor_at_end_and_append_block(ag, endif_block);6731 ir_set_cursor_at_end_and_append_block(ag, endif_block);
6732 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);6732 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
6733 incoming_values[0] = then_expr_result;6733 incoming_values[0] = then_expr_result;
6734 incoming_values[1] = else_expr_result;6734 incoming_values[1] = else_expr_result;
6735 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);6735 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
6736 incoming_blocks[0] = after_then_block;6736 incoming_blocks[0] = after_then_block;
6737 incoming_blocks[1] = after_else_block;6737 incoming_blocks[1] = after_else_block;
67386738
6739 IrInstSrc *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);6739 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);
6740 return ir_expr_wrap(ag, scope, phi, result_loc);6740 return ir_expr_wrap(ag, scope, phi, result_loc);
6741}6741}
67426742
6743static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,6743static Stage1ZirInst *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
6744 ResultLoc *result_loc)6744 ResultLoc *result_loc)
6745{6745{
6746 assert(node->type == NodeTypeIfErrorExpr);6746 assert(node->type == NodeTypeIfErrorExpr);
...@@ -6753,20 +6753,20 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6753,20 +6753,20 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6753 Buf *var_symbol = node->data.if_err_expr.var_symbol;6753 Buf *var_symbol = node->data.if_err_expr.var_symbol;
6754 Buf *err_symbol = node->data.if_err_expr.err_symbol;6754 Buf *err_symbol = node->data.if_err_expr.err_symbol;
67556755
6756 IrInstSrc *err_val_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr);6756 Stage1ZirInst *err_val_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr);
6757 if (err_val_ptr == ag->codegen->invalid_inst_src)6757 if (err_val_ptr == ag->codegen->invalid_inst_src)
6758 return err_val_ptr;6758 return err_val_ptr;
67596759
6760 IrInstSrc *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr);6760 Stage1ZirInst *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr);
6761 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, err_val_ptr, true, false);6761 Stage1ZirInst *is_err = ir_build_test_err_src(ag, scope, node, err_val_ptr, true, false);
67626762
6763 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "TryOk");6763 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "TryOk");
6764 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "TryElse");6764 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "TryElse");
6765 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "TryEnd");6765 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "TryEnd");
67666766
6767 bool force_comptime = ir_should_inline(ag->exec, scope);6767 bool force_comptime = ir_should_inline(ag->exec, scope);
6768 IrInstSrc *is_comptime = force_comptime ? ir_build_const_bool(ag, scope, node, true) : ir_build_test_comptime(ag, scope, node, is_err);6768 Stage1ZirInst *is_comptime = force_comptime ? ir_build_const_bool(ag, scope, node, true) : ir_build_test_comptime(ag, scope, node, is_err);
6769 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, is_err, else_block, ok_block, is_comptime);6769 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, scope, node, is_err, else_block, ok_block, is_comptime);
67706770
6771 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block,6771 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block,
6772 result_loc, is_comptime);6772 result_loc, is_comptime);
...@@ -6777,19 +6777,19 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6777,19 +6777,19 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6777 Scope *var_scope;6777 Scope *var_scope;
6778 if (var_symbol) {6778 if (var_symbol) {
6779 bool is_shadowable = false;6779 bool is_shadowable = false;
6780 IrInstSrc *var_is_comptime = force_comptime ? ir_build_const_bool(ag, subexpr_scope, node, true) : ir_build_test_comptime(ag, subexpr_scope, node, err_val);6780 Stage1ZirInst *var_is_comptime = force_comptime ? ir_build_const_bool(ag, subexpr_scope, node, true) : ir_build_test_comptime(ag, subexpr_scope, node, err_val);
6781 ZigVar *var = ir_create_var(ag, node, subexpr_scope,6781 ZigVar *var = ir_create_var(ag, node, subexpr_scope,
6782 var_symbol, var_is_const, var_is_const, is_shadowable, var_is_comptime);6782 var_symbol, var_is_const, var_is_const, is_shadowable, var_is_comptime);
67836783
6784 IrInstSrc *payload_ptr = ir_build_unwrap_err_payload_src(ag, subexpr_scope, node, err_val_ptr, false, false);6784 Stage1ZirInst *payload_ptr = ir_build_unwrap_err_payload_src(ag, subexpr_scope, node, err_val_ptr, false, false);
6785 IrInstSrc *var_value = var_is_ptr ?6785 Stage1ZirInst *var_value = var_is_ptr ?
6786 payload_ptr : ir_build_load_ptr(ag, subexpr_scope, node, payload_ptr);6786 payload_ptr : ir_build_load_ptr(ag, subexpr_scope, node, payload_ptr);
6787 build_decl_var_and_init(ag, subexpr_scope, node, var, var_value, buf_ptr(var_symbol), var_is_comptime);6787 build_decl_var_and_init(ag, subexpr_scope, node, var, var_value, buf_ptr(var_symbol), var_is_comptime);
6788 var_scope = var->child_scope;6788 var_scope = var->child_scope;
6789 } else {6789 } else {
6790 var_scope = subexpr_scope;6790 var_scope = subexpr_scope;
6791 }6791 }
6792 IrInstSrc *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval,6792 Stage1ZirInst *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval,
6793 &peer_parent->peers.at(0)->base);6793 &peer_parent->peers.at(0)->base);
6794 if (then_expr_result == ag->codegen->invalid_inst_src)6794 if (then_expr_result == ag->codegen->invalid_inst_src)
6795 return then_expr_result;6795 return then_expr_result;
...@@ -6799,7 +6799,7 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6799,7 +6799,7 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
67996799
6800 ir_set_cursor_at_end_and_append_block(ag, else_block);6800 ir_set_cursor_at_end_and_append_block(ag, else_block);
68016801
6802 IrInstSrc *else_expr_result;6802 Stage1ZirInst *else_expr_result;
6803 if (else_node) {6803 if (else_node) {
6804 Scope *err_var_scope;6804 Scope *err_var_scope;
6805 if (err_symbol) {6805 if (err_symbol) {
...@@ -6808,8 +6808,8 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6808,8 +6808,8 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6808 ZigVar *var = ir_create_var(ag, node, subexpr_scope,6808 ZigVar *var = ir_create_var(ag, node, subexpr_scope,
6809 err_symbol, is_const, is_const, is_shadowable, is_comptime);6809 err_symbol, is_const, is_const, is_shadowable, is_comptime);
68106810
6811 IrInstSrc *err_ptr = ir_build_unwrap_err_code_src(ag, subexpr_scope, node, err_val_ptr);6811 Stage1ZirInst *err_ptr = ir_build_unwrap_err_code_src(ag, subexpr_scope, node, err_val_ptr);
6812 IrInstSrc *err_value = ir_build_load_ptr(ag, subexpr_scope, node, err_ptr);6812 Stage1ZirInst *err_value = ir_build_load_ptr(ag, subexpr_scope, node, err_ptr);
6813 build_decl_var_and_init(ag, subexpr_scope, node, var, err_value, buf_ptr(err_symbol), is_comptime);6813 build_decl_var_and_init(ag, subexpr_scope, node, var, err_value, buf_ptr(err_symbol), is_comptime);
6814 err_var_scope = var->child_scope;6814 err_var_scope = var->child_scope;
6815 } else {6815 } else {
...@@ -6827,22 +6827,22 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6827,22 +6827,22 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6827 ir_build_br(ag, scope, node, endif_block, is_comptime);6827 ir_build_br(ag, scope, node, endif_block, is_comptime);
68286828
6829 ir_set_cursor_at_end_and_append_block(ag, endif_block);6829 ir_set_cursor_at_end_and_append_block(ag, endif_block);
6830 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);6830 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
6831 incoming_values[0] = then_expr_result;6831 incoming_values[0] = then_expr_result;
6832 incoming_values[1] = else_expr_result;6832 incoming_values[1] = else_expr_result;
6833 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);6833 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
6834 incoming_blocks[0] = after_then_block;6834 incoming_blocks[0] = after_then_block;
6835 incoming_blocks[1] = after_else_block;6835 incoming_blocks[1] = after_else_block;
68366836
6837 IrInstSrc *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);6837 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);
6838 return ir_expr_wrap(ag, scope, phi, result_loc);6838 return ir_expr_wrap(ag, scope, phi, result_loc);
6839}6839}
68406840
6841static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *switch_node, AstNode *prong_node,6841static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *switch_node, AstNode *prong_node,
6842 Stage1ZirBasicBlock *end_block, IrInstSrc *is_comptime, IrInstSrc *var_is_comptime,6842 Stage1ZirBasicBlock *end_block, Stage1ZirInst *is_comptime, Stage1ZirInst *var_is_comptime,
6843 IrInstSrc *target_value_ptr, IrInstSrc **prong_values, size_t prong_values_len,6843 Stage1ZirInst *target_value_ptr, Stage1ZirInst **prong_values, size_t prong_values_len,
6844 ZigList<Stage1ZirBasicBlock *> *incoming_blocks, ZigList<IrInstSrc *> *incoming_values,6844 ZigList<Stage1ZirBasicBlock *> *incoming_blocks, ZigList<Stage1ZirInst *> *incoming_values,
6845 IrInstSrcSwitchElseVar **out_switch_else_var, LVal lval, ResultLoc *result_loc)6845 Stage1ZirInstSwitchElseVar **out_switch_else_var, LVal lval, ResultLoc *result_loc)
6846{6846{
6847 assert(switch_node->type == NodeTypeSwitchExpr);6847 assert(switch_node->type == NodeTypeSwitchExpr);
6848 assert(prong_node->type == NodeTypeSwitchProng);6848 assert(prong_node->type == NodeTypeSwitchProng);
...@@ -6860,16 +6860,16 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw...@@ -6860,16 +6860,16 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw
6860 ZigVar *var = ir_create_var(ag, var_symbol_node, scope,6860 ZigVar *var = ir_create_var(ag, var_symbol_node, scope,
6861 var_name, is_const, is_const, is_shadowable, var_is_comptime);6861 var_name, is_const, is_const, is_shadowable, var_is_comptime);
6862 child_scope = var->child_scope;6862 child_scope = var->child_scope;
6863 IrInstSrc *var_value;6863 Stage1ZirInst *var_value;
6864 if (out_switch_else_var != nullptr) {6864 if (out_switch_else_var != nullptr) {
6865 IrInstSrcSwitchElseVar *switch_else_var = ir_build_switch_else_var(ag, scope, var_symbol_node,6865 Stage1ZirInstSwitchElseVar *switch_else_var = ir_build_switch_else_var(ag, scope, var_symbol_node,
6866 target_value_ptr);6866 target_value_ptr);
6867 *out_switch_else_var = switch_else_var;6867 *out_switch_else_var = switch_else_var;
6868 IrInstSrc *payload_ptr = &switch_else_var->base;6868 Stage1ZirInst *payload_ptr = &switch_else_var->base;
6869 var_value = var_is_ptr ?6869 var_value = var_is_ptr ?
6870 payload_ptr : ir_build_load_ptr(ag, scope, var_symbol_node, payload_ptr);6870 payload_ptr : ir_build_load_ptr(ag, scope, var_symbol_node, payload_ptr);
6871 } else if (prong_values != nullptr) {6871 } else if (prong_values != nullptr) {
6872 IrInstSrc *payload_ptr = ir_build_switch_var(ag, scope, var_symbol_node, target_value_ptr,6872 Stage1ZirInst *payload_ptr = ir_build_switch_var(ag, scope, var_symbol_node, target_value_ptr,
6873 prong_values, prong_values_len);6873 prong_values, prong_values_len);
6874 var_value = var_is_ptr ?6874 var_value = var_is_ptr ?
6875 payload_ptr : ir_build_load_ptr(ag, scope, var_symbol_node, payload_ptr);6875 payload_ptr : ir_build_load_ptr(ag, scope, var_symbol_node, payload_ptr);
...@@ -6882,7 +6882,7 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw...@@ -6882,7 +6882,7 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw
6882 child_scope = scope;6882 child_scope = scope;
6883 }6883 }
68846884
6885 IrInstSrc *expr_result = astgen_node_extra(ag, expr_node, child_scope, lval, result_loc);6885 Stage1ZirInst *expr_result = astgen_node_extra(ag, expr_node, child_scope, lval, result_loc);
6886 if (expr_result == ag->codegen->invalid_inst_src)6886 if (expr_result == ag->codegen->invalid_inst_src)
6887 return false;6887 return false;
6888 if (!instr_is_unreachable(expr_result))6888 if (!instr_is_unreachable(expr_result))
...@@ -6892,25 +6892,25 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw...@@ -6892,25 +6892,25 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw
6892 return true;6892 return true;
6893}6893}
68946894
6895static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,6895static Stage1ZirInst *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
6896 ResultLoc *result_loc)6896 ResultLoc *result_loc)
6897{6897{
6898 assert(node->type == NodeTypeSwitchExpr);6898 assert(node->type == NodeTypeSwitchExpr);
68996899
6900 AstNode *target_node = node->data.switch_expr.expr;6900 AstNode *target_node = node->data.switch_expr.expr;
6901 IrInstSrc *target_value_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr);6901 Stage1ZirInst *target_value_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr);
6902 if (target_value_ptr == ag->codegen->invalid_inst_src)6902 if (target_value_ptr == ag->codegen->invalid_inst_src)
6903 return target_value_ptr;6903 return target_value_ptr;
6904 IrInstSrc *target_value = ir_build_switch_target(ag, scope, node, target_value_ptr);6904 Stage1ZirInst *target_value = ir_build_switch_target(ag, scope, node, target_value_ptr);
69056905
6906 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "SwitchElse");6906 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "SwitchElse");
6907 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, scope, "SwitchEnd");6907 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, scope, "SwitchEnd");
69086908
6909 size_t prong_count = node->data.switch_expr.prongs.length;6909 size_t prong_count = node->data.switch_expr.prongs.length;
6910 ZigList<IrInstSrcSwitchBrCase> cases = {0};6910 ZigList<Stage1ZirInstSwitchBrCase> cases = {0};
69116911
6912 IrInstSrc *is_comptime;6912 Stage1ZirInst *is_comptime;
6913 IrInstSrc *var_is_comptime;6913 Stage1ZirInst *var_is_comptime;
6914 if (ir_should_inline(ag->exec, scope)) {6914 if (ir_should_inline(ag->exec, scope)) {
6915 is_comptime = ir_build_const_bool(ag, scope, node, true);6915 is_comptime = ir_build_const_bool(ag, scope, node, true);
6916 var_is_comptime = is_comptime;6916 var_is_comptime = is_comptime;
...@@ -6919,11 +6919,11 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6919,11 +6919,11 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6919 var_is_comptime = ir_build_test_comptime(ag, scope, node, target_value_ptr);6919 var_is_comptime = ir_build_test_comptime(ag, scope, node, target_value_ptr);
6920 }6920 }
69216921
6922 ZigList<IrInstSrc *> incoming_values = {0};6922 ZigList<Stage1ZirInst *> incoming_values = {0};
6923 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};6923 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
6924 ZigList<IrInstSrcCheckSwitchProngsRange> check_ranges = {0};6924 ZigList<Stage1ZirInstCheckSwitchProngsRange> check_ranges = {0};
69256925
6926 IrInstSrcSwitchElseVar *switch_else_var = nullptr;6926 Stage1ZirInstSwitchElseVar *switch_else_var = nullptr;
69276927
6928 ResultLocPeerParent *peer_parent = heap::c_allocator.create<ResultLocPeerParent>();6928 ResultLocPeerParent *peer_parent = heap::c_allocator.create<ResultLocPeerParent>();
6929 peer_parent->base.id = ResultLocIdPeerParent;6929 peer_parent->base.id = ResultLocIdPeerParent;
...@@ -6945,7 +6945,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6945,7 +6945,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6945 if (prong_node->data.switch_prong.any_items_are_range) {6945 if (prong_node->data.switch_prong.any_items_are_range) {
6946 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);6946 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);
69476947
6948 IrInstSrc *ok_bit = nullptr;6948 Stage1ZirInst *ok_bit = nullptr;
6949 AstNode *last_item_node = nullptr;6949 AstNode *last_item_node = nullptr;
6950 for (size_t item_i = 0; item_i < prong_item_count; item_i += 1) {6950 for (size_t item_i = 0; item_i < prong_item_count; item_i += 1) {
6951 AstNode *item_node = prong_node->data.switch_prong.items.at(item_i);6951 AstNode *item_node = prong_node->data.switch_prong.items.at(item_i);
...@@ -6954,23 +6954,23 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6954,23 +6954,23 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6954 AstNode *start_node = item_node->data.switch_range.start;6954 AstNode *start_node = item_node->data.switch_range.start;
6955 AstNode *end_node = item_node->data.switch_range.end;6955 AstNode *end_node = item_node->data.switch_range.end;
69566956
6957 IrInstSrc *start_value = astgen_node(ag, start_node, comptime_scope);6957 Stage1ZirInst *start_value = astgen_node(ag, start_node, comptime_scope);
6958 if (start_value == ag->codegen->invalid_inst_src)6958 if (start_value == ag->codegen->invalid_inst_src)
6959 return ag->codegen->invalid_inst_src;6959 return ag->codegen->invalid_inst_src;
69606960
6961 IrInstSrc *end_value = astgen_node(ag, end_node, comptime_scope);6961 Stage1ZirInst *end_value = astgen_node(ag, end_node, comptime_scope);
6962 if (end_value == ag->codegen->invalid_inst_src)6962 if (end_value == ag->codegen->invalid_inst_src)
6963 return ag->codegen->invalid_inst_src;6963 return ag->codegen->invalid_inst_src;
69646964
6965 IrInstSrcCheckSwitchProngsRange *check_range = check_ranges.add_one();6965 Stage1ZirInstCheckSwitchProngsRange *check_range = check_ranges.add_one();
6966 check_range->start = start_value;6966 check_range->start = start_value;
6967 check_range->end = end_value;6967 check_range->end = end_value;
69686968
6969 IrInstSrc *lower_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpGreaterOrEq,6969 Stage1ZirInst *lower_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpGreaterOrEq,
6970 target_value, start_value, false);6970 target_value, start_value, false);
6971 IrInstSrc *upper_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpLessOrEq,6971 Stage1ZirInst *upper_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpLessOrEq,
6972 target_value, end_value, false);6972 target_value, end_value, false);
6973 IrInstSrc *both_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolAnd,6973 Stage1ZirInst *both_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolAnd,
6974 lower_range_ok, upper_range_ok, false);6974 lower_range_ok, upper_range_ok, false);
6975 if (ok_bit) {6975 if (ok_bit) {
6976 ok_bit = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolOr, both_ok, ok_bit, false);6976 ok_bit = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolOr, both_ok, ok_bit, false);
...@@ -6978,15 +6978,15 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6978,15 +6978,15 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6978 ok_bit = both_ok;6978 ok_bit = both_ok;
6979 }6979 }
6980 } else {6980 } else {
6981 IrInstSrc *item_value = astgen_node(ag, item_node, comptime_scope);6981 Stage1ZirInst *item_value = astgen_node(ag, item_node, comptime_scope);
6982 if (item_value == ag->codegen->invalid_inst_src)6982 if (item_value == ag->codegen->invalid_inst_src)
6983 return ag->codegen->invalid_inst_src;6983 return ag->codegen->invalid_inst_src;
69846984
6985 IrInstSrcCheckSwitchProngsRange *check_range = check_ranges.add_one();6985 Stage1ZirInstCheckSwitchProngsRange *check_range = check_ranges.add_one();
6986 check_range->start = item_value;6986 check_range->start = item_value;
6987 check_range->end = item_value;6987 check_range->end = item_value;
69886988
6989 IrInstSrc *cmp_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpEq,6989 Stage1ZirInst *cmp_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpEq,
6990 item_value, target_value, false);6990 item_value, target_value, false);
6991 if (ok_bit) {6991 if (ok_bit) {
6992 ok_bit = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolOr, cmp_ok, ok_bit, false);6992 ok_bit = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolOr, cmp_ok, ok_bit, false);
...@@ -7001,7 +7001,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -7001,7 +7001,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
70017001
7002 assert(ok_bit);7002 assert(ok_bit);
7003 assert(last_item_node);7003 assert(last_item_node);
7004 IrInstSrc *br_inst = ir_build_cond_br(ag, scope, last_item_node, ok_bit,7004 Stage1ZirInst *br_inst = ir_build_cond_br(ag, scope, last_item_node, ok_bit,
7005 range_block_yes, range_block_no, is_comptime);7005 range_block_yes, range_block_no, is_comptime);
7006 if (peer_parent->base.source_instruction == nullptr) {7006 if (peer_parent->base.source_instruction == nullptr) {
7007 peer_parent->base.source_instruction = br_inst;7007 peer_parent->base.source_instruction = br_inst;
...@@ -7087,21 +7087,21 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -7087,21 +7087,21 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
7087 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);7087 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);
70887088
7089 Stage1ZirBasicBlock *prong_block = ir_create_basic_block(ag, scope, "SwitchProng");7089 Stage1ZirBasicBlock *prong_block = ir_create_basic_block(ag, scope, "SwitchProng");
7090 IrInstSrc **items = heap::c_allocator.allocate<IrInstSrc *>(prong_item_count);7090 Stage1ZirInst **items = heap::c_allocator.allocate<Stage1ZirInst *>(prong_item_count);
70917091
7092 for (size_t item_i = 0; item_i < prong_item_count; item_i += 1) {7092 for (size_t item_i = 0; item_i < prong_item_count; item_i += 1) {
7093 AstNode *item_node = prong_node->data.switch_prong.items.at(item_i);7093 AstNode *item_node = prong_node->data.switch_prong.items.at(item_i);
7094 assert(item_node->type != NodeTypeSwitchRange);7094 assert(item_node->type != NodeTypeSwitchRange);
70957095
7096 IrInstSrc *item_value = astgen_node(ag, item_node, comptime_scope);7096 Stage1ZirInst *item_value = astgen_node(ag, item_node, comptime_scope);
7097 if (item_value == ag->codegen->invalid_inst_src)7097 if (item_value == ag->codegen->invalid_inst_src)
7098 return ag->codegen->invalid_inst_src;7098 return ag->codegen->invalid_inst_src;
70997099
7100 IrInstSrcCheckSwitchProngsRange *check_range = check_ranges.add_one();7100 Stage1ZirInstCheckSwitchProngsRange *check_range = check_ranges.add_one();
7101 check_range->start = item_value;7101 check_range->start = item_value;
7102 check_range->end = item_value;7102 check_range->end = item_value;
71037103
7104 IrInstSrcSwitchBrCase *this_case = cases.add_one();7104 Stage1ZirInstSwitchBrCase *this_case = cases.add_one();
7105 this_case->value = item_value;7105 this_case->value = item_value;
7106 this_case->block = prong_block;7106 this_case->block = prong_block;
71077107
...@@ -7125,14 +7125,14 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -7125,14 +7125,14 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
71257125
7126 }7126 }
71277127
7128 IrInstSrc *switch_prongs_void = ir_build_check_switch_prongs(ag, scope, node, target_value,7128 Stage1ZirInst *switch_prongs_void = ir_build_check_switch_prongs(ag, scope, node, target_value,
7129 check_ranges.items, check_ranges.length, else_prong, underscore_prong != nullptr);7129 check_ranges.items, check_ranges.length, else_prong, underscore_prong != nullptr);
71307130
7131 IrInstSrc *br_instruction;7131 Stage1ZirInst *br_instruction;
7132 if (cases.length == 0) {7132 if (cases.length == 0) {
7133 br_instruction = ir_build_br(ag, scope, node, else_block, is_comptime);7133 br_instruction = ir_build_br(ag, scope, node, else_block, is_comptime);
7134 } else {7134 } else {
7135 IrInstSrcSwitchBr *switch_br = ir_build_switch_br_src(ag, scope, node, target_value, else_block,7135 Stage1ZirInstSwitchBr *switch_br = ir_build_switch_br_src(ag, scope, node, target_value, else_block,
7136 cases.length, cases.items, is_comptime, switch_prongs_void);7136 cases.length, cases.items, is_comptime, switch_prongs_void);
7137 if (switch_else_var != nullptr) {7137 if (switch_else_var != nullptr) {
7138 switch_else_var->switch_br = switch_br;7138 switch_else_var->switch_br = switch_br;
...@@ -7160,7 +7160,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -7160,7 +7160,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
71607160
7161 ir_set_cursor_at_end_and_append_block(ag, end_block);7161 ir_set_cursor_at_end_and_append_block(ag, end_block);
7162 assert(incoming_blocks.length == incoming_values.length);7162 assert(incoming_blocks.length == incoming_values.length);
7163 IrInstSrc *result_instruction;7163 Stage1ZirInst *result_instruction;
7164 if (incoming_blocks.length == 0) {7164 if (incoming_blocks.length == 0) {
7165 result_instruction = ir_build_const_void(ag, scope, node);7165 result_instruction = ir_build_const_void(ag, scope, node);
7166 } else {7166 } else {
...@@ -7170,7 +7170,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -7170,7 +7170,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
7170 return ir_lval_wrap(ag, scope, result_instruction, lval, result_loc);7170 return ir_lval_wrap(ag, scope, result_instruction, lval, result_loc);
7171}7171}
71727172
7173static IrInstSrc *astgen_comptime(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) {7173static Stage1ZirInst *astgen_comptime(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) {
7174 assert(node->type == NodeTypeCompTime);7174 assert(node->type == NodeTypeCompTime);
71757175
7176 Scope *child_scope = create_comptime_scope(ag->codegen, node, parent_scope);7176 Scope *child_scope = create_comptime_scope(ag->codegen, node, parent_scope);
...@@ -7178,7 +7178,7 @@ static IrInstSrc *astgen_comptime(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -7178,7 +7178,7 @@ static IrInstSrc *astgen_comptime(Stage1AstGen *ag, Scope *parent_scope, AstNode
7178 return astgen_node_extra(ag, node->data.comptime_expr.expr, child_scope, lval, nullptr);7178 return astgen_node_extra(ag, node->data.comptime_expr.expr, child_scope, lval, nullptr);
7179}7179}
71807180
7181static IrInstSrc *astgen_nosuspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) {7181static Stage1ZirInst *astgen_nosuspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) {
7182 assert(node->type == NodeTypeNoSuspend);7182 assert(node->type == NodeTypeNoSuspend);
71837183
7184 Scope *child_scope = create_nosuspend_scope(ag->codegen, node, parent_scope);7184 Scope *child_scope = create_nosuspend_scope(ag->codegen, node, parent_scope);
...@@ -7186,15 +7186,15 @@ static IrInstSrc *astgen_nosuspend(Stage1AstGen *ag, Scope *parent_scope, AstNod...@@ -7186,15 +7186,15 @@ static IrInstSrc *astgen_nosuspend(Stage1AstGen *ag, Scope *parent_scope, AstNod
7186 return astgen_node_extra(ag, node->data.nosuspend_expr.expr, child_scope, lval, nullptr);7186 return astgen_node_extra(ag, node->data.nosuspend_expr.expr, child_scope, lval, nullptr);
7187}7187}
71887188
7189static IrInstSrc *astgen_return_from_block(Stage1AstGen *ag, Scope *break_scope, AstNode *node, ScopeBlock *block_scope) {7189static Stage1ZirInst *astgen_return_from_block(Stage1AstGen *ag, Scope *break_scope, AstNode *node, ScopeBlock *block_scope) {
7190 IrInstSrc *is_comptime;7190 Stage1ZirInst *is_comptime;
7191 if (ir_should_inline(ag->exec, break_scope)) {7191 if (ir_should_inline(ag->exec, break_scope)) {
7192 is_comptime = ir_build_const_bool(ag, break_scope, node, true);7192 is_comptime = ir_build_const_bool(ag, break_scope, node, true);
7193 } else {7193 } else {
7194 is_comptime = block_scope->is_comptime;7194 is_comptime = block_scope->is_comptime;
7195 }7195 }
71967196
7197 IrInstSrc *result_value;7197 Stage1ZirInst *result_value;
7198 if (node->data.break_expr.expr) {7198 if (node->data.break_expr.expr) {
7199 ResultLocPeer *peer_result = create_peer_result(block_scope->peer_parent);7199 ResultLocPeer *peer_result = create_peer_result(block_scope->peer_parent);
7200 block_scope->peer_parent->peers.append(peer_result);7200 block_scope->peer_parent->peers.append(peer_result);
...@@ -7216,7 +7216,7 @@ static IrInstSrc *astgen_return_from_block(Stage1AstGen *ag, Scope *break_scope,...@@ -7216,7 +7216,7 @@ static IrInstSrc *astgen_return_from_block(Stage1AstGen *ag, Scope *break_scope,
7216 return ir_build_br(ag, break_scope, node, dest_block, is_comptime);7216 return ir_build_br(ag, break_scope, node, dest_block, is_comptime);
7217}7217}
72187218
7219static IrInstSrc *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *node) {7219static Stage1ZirInst *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *node) {
7220 assert(node->type == NodeTypeBreak);7220 assert(node->type == NodeTypeBreak);
72217221
7222 // Search up the scope. We'll find one of these things first:7222 // Search up the scope. We'll find one of these things first:
...@@ -7264,14 +7264,14 @@ static IrInstSrc *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *no...@@ -7264,14 +7264,14 @@ static IrInstSrc *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *no
7264 search_scope = search_scope->parent;7264 search_scope = search_scope->parent;
7265 }7265 }
72667266
7267 IrInstSrc *is_comptime;7267 Stage1ZirInst *is_comptime;
7268 if (ir_should_inline(ag->exec, break_scope)) {7268 if (ir_should_inline(ag->exec, break_scope)) {
7269 is_comptime = ir_build_const_bool(ag, break_scope, node, true);7269 is_comptime = ir_build_const_bool(ag, break_scope, node, true);
7270 } else {7270 } else {
7271 is_comptime = loop_scope->is_comptime;7271 is_comptime = loop_scope->is_comptime;
7272 }7272 }
72737273
7274 IrInstSrc *result_value;7274 Stage1ZirInst *result_value;
7275 if (node->data.break_expr.expr) {7275 if (node->data.break_expr.expr) {
7276 ResultLocPeer *peer_result = create_peer_result(loop_scope->peer_parent);7276 ResultLocPeer *peer_result = create_peer_result(loop_scope->peer_parent);
7277 loop_scope->peer_parent->peers.append(peer_result);7277 loop_scope->peer_parent->peers.append(peer_result);
...@@ -7293,7 +7293,7 @@ static IrInstSrc *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *no...@@ -7293,7 +7293,7 @@ static IrInstSrc *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *no
7293 return ir_build_br(ag, break_scope, node, dest_block, is_comptime);7293 return ir_build_br(ag, break_scope, node, dest_block, is_comptime);
7294}7294}
72957295
7296static IrInstSrc *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNode *node) {7296static Stage1ZirInst *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNode *node) {
7297 assert(node->type == NodeTypeContinue);7297 assert(node->type == NodeTypeContinue);
72987298
7299 // Search up the scope. We'll find one of these things first:7299 // Search up the scope. We'll find one of these things first:
...@@ -7333,7 +7333,7 @@ static IrInstSrc *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNo...@@ -7333,7 +7333,7 @@ static IrInstSrc *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNo
7333 search_scope = search_scope->parent;7333 search_scope = search_scope->parent;
7334 }7334 }
73357335
7336 IrInstSrc *is_comptime;7336 Stage1ZirInst *is_comptime;
7337 if (ir_should_inline(ag->exec, continue_scope)) {7337 if (ir_should_inline(ag->exec, continue_scope)) {
7338 is_comptime = ir_build_const_bool(ag, continue_scope, node, true);7338 is_comptime = ir_build_const_bool(ag, continue_scope, node, true);
7339 } else {7339 } else {
...@@ -7352,12 +7352,12 @@ static IrInstSrc *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNo...@@ -7352,12 +7352,12 @@ static IrInstSrc *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNo
7352 return ir_build_br(ag, continue_scope, node, dest_block, is_comptime);7352 return ir_build_br(ag, continue_scope, node, dest_block, is_comptime);
7353}7353}
73547354
7355static IrInstSrc *astgen_error_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {7355static Stage1ZirInst *astgen_error_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
7356 assert(node->type == NodeTypeErrorType);7356 assert(node->type == NodeTypeErrorType);
7357 return ir_build_const_type(ag, scope, node, ag->codegen->builtin_types.entry_global_error_set);7357 return ir_build_const_type(ag, scope, node, ag->codegen->builtin_types.entry_global_error_set);
7358}7358}
73597359
7360static IrInstSrc *astgen_defer(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {7360static Stage1ZirInst *astgen_defer(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
7361 assert(node->type == NodeTypeDefer);7361 assert(node->type == NodeTypeDefer);
73627362
7363 ScopeDefer *defer_child_scope = create_defer_scope(ag->codegen, node, parent_scope);7363 ScopeDefer *defer_child_scope = create_defer_scope(ag->codegen, node, parent_scope);
...@@ -7369,7 +7369,7 @@ static IrInstSrc *astgen_defer(Stage1AstGen *ag, Scope *parent_scope, AstNode *n...@@ -7369,7 +7369,7 @@ static IrInstSrc *astgen_defer(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
7369 return ir_build_const_void(ag, parent_scope, node);7369 return ir_build_const_void(ag, parent_scope, node);
7370}7370}
73717371
7372static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {7372static Stage1ZirInst *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {
7373 assert(node->type == NodeTypeSliceExpr);7373 assert(node->type == NodeTypeSliceExpr);
73747374
7375 AstNodeSliceExpr *slice_expr = &node->data.slice_expr;7375 AstNodeSliceExpr *slice_expr = &node->data.slice_expr;
...@@ -7378,15 +7378,15 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV...@@ -7378,15 +7378,15 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV
7378 AstNode *end_node = slice_expr->end;7378 AstNode *end_node = slice_expr->end;
7379 AstNode *sentinel_node = slice_expr->sentinel;7379 AstNode *sentinel_node = slice_expr->sentinel;
73807380
7381 IrInstSrc *ptr_value = astgen_node_extra(ag, array_node, scope, LValPtr, nullptr);7381 Stage1ZirInst *ptr_value = astgen_node_extra(ag, array_node, scope, LValPtr, nullptr);
7382 if (ptr_value == ag->codegen->invalid_inst_src)7382 if (ptr_value == ag->codegen->invalid_inst_src)
7383 return ag->codegen->invalid_inst_src;7383 return ag->codegen->invalid_inst_src;
73847384
7385 IrInstSrc *start_value = astgen_node(ag, start_node, scope);7385 Stage1ZirInst *start_value = astgen_node(ag, start_node, scope);
7386 if (start_value == ag->codegen->invalid_inst_src)7386 if (start_value == ag->codegen->invalid_inst_src)
7387 return ag->codegen->invalid_inst_src;7387 return ag->codegen->invalid_inst_src;
73887388
7389 IrInstSrc *end_value;7389 Stage1ZirInst *end_value;
7390 if (end_node) {7390 if (end_node) {
7391 end_value = astgen_node(ag, end_node, scope);7391 end_value = astgen_node(ag, end_node, scope);
7392 if (end_value == ag->codegen->invalid_inst_src)7392 if (end_value == ag->codegen->invalid_inst_src)
...@@ -7395,7 +7395,7 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV...@@ -7395,7 +7395,7 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV
7395 end_value = nullptr;7395 end_value = nullptr;
7396 }7396 }
73977397
7398 IrInstSrc *sentinel_value;7398 Stage1ZirInst *sentinel_value;
7399 if (sentinel_node) {7399 if (sentinel_node) {
7400 sentinel_value = astgen_node(ag, sentinel_node, scope);7400 sentinel_value = astgen_node(ag, sentinel_node, scope);
7401 if (sentinel_value == ag->codegen->invalid_inst_src)7401 if (sentinel_value == ag->codegen->invalid_inst_src)
...@@ -7404,12 +7404,12 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV...@@ -7404,12 +7404,12 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV
7404 sentinel_value = nullptr;7404 sentinel_value = nullptr;
7405 }7405 }
74067406
7407 IrInstSrc *slice = ir_build_slice_src(ag, scope, node, ptr_value, start_value, end_value,7407 Stage1ZirInst *slice = ir_build_slice_src(ag, scope, node, ptr_value, start_value, end_value,
7408 sentinel_value, true, result_loc);7408 sentinel_value, true, result_loc);
7409 return ir_lval_wrap(ag, scope, slice, lval, result_loc);7409 return ir_lval_wrap(ag, scope, slice, lval, result_loc);
7410}7410}
74117411
7412static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,7412static Stage1ZirInst *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,
7413 ResultLoc *result_loc)7413 ResultLoc *result_loc)
7414{7414{
7415 assert(node->type == NodeTypeCatchExpr);7415 assert(node->type == NodeTypeCatchExpr);
...@@ -7432,13 +7432,13 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n...@@ -7432,13 +7432,13 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
7432 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, op1_node, parent_scope);7432 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, op1_node, parent_scope);
7433 spill_scope->spill_harder = true;7433 spill_scope->spill_harder = true;
74347434
7435 IrInstSrc *err_union_ptr = astgen_node_extra(ag, op1_node, &spill_scope->base, LValPtr, nullptr);7435 Stage1ZirInst *err_union_ptr = astgen_node_extra(ag, op1_node, &spill_scope->base, LValPtr, nullptr);
7436 if (err_union_ptr == ag->codegen->invalid_inst_src)7436 if (err_union_ptr == ag->codegen->invalid_inst_src)
7437 return ag->codegen->invalid_inst_src;7437 return ag->codegen->invalid_inst_src;
74387438
7439 IrInstSrc *is_err = ir_build_test_err_src(ag, parent_scope, node, err_union_ptr, true, false);7439 Stage1ZirInst *is_err = ir_build_test_err_src(ag, parent_scope, node, err_union_ptr, true, false);
74407440
7441 IrInstSrc *is_comptime;7441 Stage1ZirInst *is_comptime;
7442 if (ir_should_inline(ag->exec, parent_scope)) {7442 if (ir_should_inline(ag->exec, parent_scope)) {
7443 is_comptime = ir_build_const_bool(ag, parent_scope, node, true);7443 is_comptime = ir_build_const_bool(ag, parent_scope, node, true);
7444 } else {7444 } else {
...@@ -7448,7 +7448,7 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n...@@ -7448,7 +7448,7 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
7448 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrOk");7448 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrOk");
7449 Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrError");7449 Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrError");
7450 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrEnd");7450 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrEnd");
7451 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_err, err_block, ok_block, is_comptime);7451 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_err, err_block, ok_block, is_comptime);
74527452
7453 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block, result_loc,7453 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block, result_loc,
7454 is_comptime);7454 is_comptime);
...@@ -7464,13 +7464,13 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n...@@ -7464,13 +7464,13 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
7464 ZigVar *var = ir_create_var(ag, node, subexpr_scope, var_name,7464 ZigVar *var = ir_create_var(ag, node, subexpr_scope, var_name,
7465 is_const, is_const, is_shadowable, is_comptime);7465 is_const, is_const, is_shadowable, is_comptime);
7466 err_scope = var->child_scope;7466 err_scope = var->child_scope;
7467 IrInstSrc *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, node, err_union_ptr);7467 Stage1ZirInst *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, node, err_union_ptr);
7468 IrInstSrc *err_value = ir_build_load_ptr(ag, err_scope, var_node, err_ptr);7468 Stage1ZirInst *err_value = ir_build_load_ptr(ag, err_scope, var_node, err_ptr);
7469 build_decl_var_and_init(ag, err_scope, var_node, var, err_value, buf_ptr(var_name), is_comptime);7469 build_decl_var_and_init(ag, err_scope, var_node, var, err_value, buf_ptr(var_name), is_comptime);
7470 } else {7470 } else {
7471 err_scope = subexpr_scope;7471 err_scope = subexpr_scope;
7472 }7472 }
7473 IrInstSrc *err_result = astgen_node_extra(ag, op2_node, err_scope, LValNone, &peer_parent->peers.at(0)->base);7473 Stage1ZirInst *err_result = astgen_node_extra(ag, op2_node, err_scope, LValNone, &peer_parent->peers.at(0)->base);
7474 if (err_result == ag->codegen->invalid_inst_src)7474 if (err_result == ag->codegen->invalid_inst_src)
7475 return ag->codegen->invalid_inst_src;7475 return ag->codegen->invalid_inst_src;
7476 Stage1ZirBasicBlock *after_err_block = ag->current_basic_block;7476 Stage1ZirBasicBlock *after_err_block = ag->current_basic_block;
...@@ -7478,20 +7478,20 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n...@@ -7478,20 +7478,20 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
7478 ir_build_br(ag, parent_scope, node, end_block, is_comptime);7478 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
74797479
7480 ir_set_cursor_at_end_and_append_block(ag, ok_block);7480 ir_set_cursor_at_end_and_append_block(ag, ok_block);
7481 IrInstSrc *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, parent_scope, node, err_union_ptr, false, false);7481 Stage1ZirInst *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, parent_scope, node, err_union_ptr, false, false);
7482 IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);7482 Stage1ZirInst *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);
7483 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);7483 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);
7484 Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block;7484 Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block;
7485 ir_build_br(ag, parent_scope, node, end_block, is_comptime);7485 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
74867486
7487 ir_set_cursor_at_end_and_append_block(ag, end_block);7487 ir_set_cursor_at_end_and_append_block(ag, end_block);
7488 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);7488 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
7489 incoming_values[0] = err_result;7489 incoming_values[0] = err_result;
7490 incoming_values[1] = unwrapped_payload;7490 incoming_values[1] = unwrapped_payload;
7491 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);7491 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
7492 incoming_blocks[0] = after_err_block;7492 incoming_blocks[0] = after_err_block;
7493 incoming_blocks[1] = after_ok_block;7493 incoming_blocks[1] = after_ok_block;
7494 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);7494 Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);
7495 return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc);7495 return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc);
7496}7496}
74977497
...@@ -7540,7 +7540,7 @@ Buf *get_anon_type_name(CodeGen *codegen, Stage1Zir *exec, const char *kind_name...@@ -7540,7 +7540,7 @@ Buf *get_anon_type_name(CodeGen *codegen, Stage1Zir *exec, const char *kind_name
7540 }7540 }
7541}7541}
75427542
7543static IrInstSrc *astgen_container_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {7543static Stage1ZirInst *astgen_container_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
7544 assert(node->type == NodeTypeContainerDecl);7544 assert(node->type == NodeTypeContainerDecl);
75457545
7546 ContainerKind kind = node->data.container_decl.kind;7546 ContainerKind kind = node->data.container_decl.kind;
...@@ -7569,7 +7569,7 @@ static IrInstSrc *astgen_container_decl(Stage1AstGen *ag, Scope *parent_scope, A...@@ -7569,7 +7569,7 @@ static IrInstSrc *astgen_container_decl(Stage1AstGen *ag, Scope *parent_scope, A
7569 return ir_build_const_type(ag, parent_scope, node, container_type);7569 return ir_build_const_type(ag, parent_scope, node, container_type);
7570}7570}
75717571
7572static IrInstSrc *astgen_err_set_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {7572static Stage1ZirInst *astgen_err_set_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
7573 assert(node->type == NodeTypeErrorSetDecl);7573 assert(node->type == NodeTypeErrorSetDecl);
75747574
7575 uint32_t err_count = node->data.err_set_decl.decls.length;7575 uint32_t err_count = node->data.err_set_decl.decls.length;
...@@ -7620,11 +7620,11 @@ static IrInstSrc *astgen_err_set_decl(Stage1AstGen *ag, Scope *parent_scope, Ast...@@ -7620,11 +7620,11 @@ static IrInstSrc *astgen_err_set_decl(Stage1AstGen *ag, Scope *parent_scope, Ast
7620 return ir_build_const_type(ag, parent_scope, node, err_set_type);7620 return ir_build_const_type(ag, parent_scope, node, err_set_type);
7621}7621}
76227622
7623static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {7623static Stage1ZirInst *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
7624 assert(node->type == NodeTypeFnProto);7624 assert(node->type == NodeTypeFnProto);
76257625
7626 size_t param_count = node->data.fn_proto.params.length;7626 size_t param_count = node->data.fn_proto.params.length;
7627 IrInstSrc **param_types = heap::c_allocator.allocate<IrInstSrc*>(param_count);7627 Stage1ZirInst **param_types = heap::c_allocator.allocate<Stage1ZirInst*>(param_count);
76287628
7629 bool is_var_args = false;7629 bool is_var_args = false;
7630 for (size_t i = 0; i < param_count; i += 1) {7630 for (size_t i = 0; i < param_count; i += 1) {
...@@ -7635,7 +7635,7 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -7635,7 +7635,7 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode
7635 }7635 }
7636 if (param_node->data.param_decl.anytype_token == 0) {7636 if (param_node->data.param_decl.anytype_token == 0) {
7637 AstNode *type_node = param_node->data.param_decl.type;7637 AstNode *type_node = param_node->data.param_decl.type;
7638 IrInstSrc *type_value = astgen_node(ag, type_node, parent_scope);7638 Stage1ZirInst *type_value = astgen_node(ag, type_node, parent_scope);
7639 if (type_value == ag->codegen->invalid_inst_src)7639 if (type_value == ag->codegen->invalid_inst_src)
7640 return ag->codegen->invalid_inst_src;7640 return ag->codegen->invalid_inst_src;
7641 param_types[i] = type_value;7641 param_types[i] = type_value;
...@@ -7644,21 +7644,21 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -7644,21 +7644,21 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode
7644 }7644 }
7645 }7645 }
76467646
7647 IrInstSrc *align_value = nullptr;7647 Stage1ZirInst *align_value = nullptr;
7648 if (node->data.fn_proto.align_expr != nullptr) {7648 if (node->data.fn_proto.align_expr != nullptr) {
7649 align_value = astgen_node(ag, node->data.fn_proto.align_expr, parent_scope);7649 align_value = astgen_node(ag, node->data.fn_proto.align_expr, parent_scope);
7650 if (align_value == ag->codegen->invalid_inst_src)7650 if (align_value == ag->codegen->invalid_inst_src)
7651 return ag->codegen->invalid_inst_src;7651 return ag->codegen->invalid_inst_src;
7652 }7652 }
76537653
7654 IrInstSrc *callconv_value = nullptr;7654 Stage1ZirInst *callconv_value = nullptr;
7655 if (node->data.fn_proto.callconv_expr != nullptr) {7655 if (node->data.fn_proto.callconv_expr != nullptr) {
7656 callconv_value = astgen_node(ag, node->data.fn_proto.callconv_expr, parent_scope);7656 callconv_value = astgen_node(ag, node->data.fn_proto.callconv_expr, parent_scope);
7657 if (callconv_value == ag->codegen->invalid_inst_src)7657 if (callconv_value == ag->codegen->invalid_inst_src)
7658 return ag->codegen->invalid_inst_src;7658 return ag->codegen->invalid_inst_src;
7659 }7659 }
76607660
7661 IrInstSrc *return_type;7661 Stage1ZirInst *return_type;
7662 if (node->data.fn_proto.return_type == nullptr) {7662 if (node->data.fn_proto.return_type == nullptr) {
7663 return_type = ir_build_const_type(ag, parent_scope, node, ag->codegen->builtin_types.entry_void);7663 return_type = ir_build_const_type(ag, parent_scope, node, ag->codegen->builtin_types.entry_void);
7664 } else {7664 } else {
...@@ -7670,17 +7670,17 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -7670,17 +7670,17 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode
7670 return ir_build_fn_proto(ag, parent_scope, node, param_types, align_value, callconv_value, return_type, is_var_args);7670 return ir_build_fn_proto(ag, parent_scope, node, param_types, align_value, callconv_value, return_type, is_var_args);
7671}7671}
76727672
7673static IrInstSrc *astgen_resume(Stage1AstGen *ag, Scope *scope, AstNode *node) {7673static Stage1ZirInst *astgen_resume(Stage1AstGen *ag, Scope *scope, AstNode *node) {
7674 assert(node->type == NodeTypeResume);7674 assert(node->type == NodeTypeResume);
76757675
7676 IrInstSrc *target_inst = astgen_node_extra(ag, node->data.resume_expr.expr, scope, LValPtr, nullptr);7676 Stage1ZirInst *target_inst = astgen_node_extra(ag, node->data.resume_expr.expr, scope, LValPtr, nullptr);
7677 if (target_inst == ag->codegen->invalid_inst_src)7677 if (target_inst == ag->codegen->invalid_inst_src)
7678 return ag->codegen->invalid_inst_src;7678 return ag->codegen->invalid_inst_src;
76797679
7680 return ir_build_resume_src(ag, scope, node, target_inst);7680 return ir_build_resume_src(ag, scope, node, target_inst);
7681}7681}
76827682
7683static IrInstSrc *astgen_await_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,7683static Stage1ZirInst *astgen_await_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
7684 ResultLoc *result_loc)7684 ResultLoc *result_loc)
7685{7685{
7686 assert(node->type == NodeTypeAwaitExpr);7686 assert(node->type == NodeTypeAwaitExpr);
...@@ -7714,15 +7714,15 @@ static IrInstSrc *astgen_await_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -7714,15 +7714,15 @@ static IrInstSrc *astgen_await_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
7714 return ag->codegen->invalid_inst_src;7714 return ag->codegen->invalid_inst_src;
7715 }7715 }
77167716
7717 IrInstSrc *target_inst = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);7717 Stage1ZirInst *target_inst = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
7718 if (target_inst == ag->codegen->invalid_inst_src)7718 if (target_inst == ag->codegen->invalid_inst_src)
7719 return ag->codegen->invalid_inst_src;7719 return ag->codegen->invalid_inst_src;
77207720
7721 IrInstSrc *await_inst = ir_build_await_src(ag, scope, node, target_inst, result_loc, is_nosuspend);7721 Stage1ZirInst *await_inst = ir_build_await_src(ag, scope, node, target_inst, result_loc, is_nosuspend);
7722 return ir_lval_wrap(ag, scope, await_inst, lval, result_loc);7722 return ir_lval_wrap(ag, scope, await_inst, lval, result_loc);
7723}7723}
77247724
7725static IrInstSrc *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {7725static Stage1ZirInst *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
7726 assert(node->type == NodeTypeSuspend);7726 assert(node->type == NodeTypeSuspend);
77277727
7728 if (!ag->fn) {7728 if (!ag->fn) {
...@@ -7744,10 +7744,10 @@ static IrInstSrc *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -7744,10 +7744,10 @@ static IrInstSrc *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode
7744 return ag->codegen->invalid_inst_src;7744 return ag->codegen->invalid_inst_src;
7745 }7745 }
77467746
7747 IrInstSrcSuspendBegin *begin = ir_build_suspend_begin_src(ag, parent_scope, node);7747 Stage1ZirInstSuspendBegin *begin = ir_build_suspend_begin_src(ag, parent_scope, node);
7748 ScopeSuspend *suspend_scope = create_suspend_scope(ag->codegen, node, parent_scope);7748 ScopeSuspend *suspend_scope = create_suspend_scope(ag->codegen, node, parent_scope);
7749 Scope *child_scope = &suspend_scope->base;7749 Scope *child_scope = &suspend_scope->base;
7750 IrInstSrc *susp_res = astgen_node(ag, node->data.suspend.block, child_scope);7750 Stage1ZirInst *susp_res = astgen_node(ag, node->data.suspend.block, child_scope);
7751 if (susp_res == ag->codegen->invalid_inst_src)7751 if (susp_res == ag->codegen->invalid_inst_src)
7752 return ag->codegen->invalid_inst_src;7752 return ag->codegen->invalid_inst_src;
7753 ir_build_check_statement_is_void(ag, child_scope, node->data.suspend.block, susp_res);7753 ir_build_check_statement_is_void(ag, child_scope, node->data.suspend.block, susp_res);
...@@ -7755,7 +7755,7 @@ static IrInstSrc *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -7755,7 +7755,7 @@ static IrInstSrc *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode
7755 return ir_build_suspend_finish_src(ag, parent_scope, node, begin);7755 return ir_build_suspend_finish_src(ag, parent_scope, node, begin);
7756}7756}
77577757
7758static IrInstSrc *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope,7758static Stage1ZirInst *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope,
7759 LVal lval, ResultLoc *result_loc)7759 LVal lval, ResultLoc *result_loc)
7760{7760{
7761 assert(scope);7761 assert(scope);
...@@ -7804,13 +7804,13 @@ static IrInstSrc *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope,...@@ -7804,13 +7804,13 @@ static IrInstSrc *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope,
7804 return astgen_return(ag, scope, node, lval, result_loc);7804 return astgen_return(ag, scope, node, lval, result_loc);
7805 case NodeTypeFieldAccessExpr:7805 case NodeTypeFieldAccessExpr:
7806 {7806 {
7807 IrInstSrc *ptr_instruction = astgen_field_access(ag, scope, node);7807 Stage1ZirInst *ptr_instruction = astgen_field_access(ag, scope, node);
7808 if (ptr_instruction == ag->codegen->invalid_inst_src)7808 if (ptr_instruction == ag->codegen->invalid_inst_src)
7809 return ptr_instruction;7809 return ptr_instruction;
7810 if (lval == LValPtr || lval == LValAssign)7810 if (lval == LValPtr || lval == LValAssign)
7811 return ptr_instruction;7811 return ptr_instruction;
78127812
7813 IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);7813 Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);
7814 return ir_expr_wrap(ag, scope, load_ptr, result_loc);7814 return ir_expr_wrap(ag, scope, load_ptr, result_loc);
7815 }7815 }
7816 case NodeTypePtrDeref: {7816 case NodeTypePtrDeref: {
...@@ -7820,28 +7820,28 @@ static IrInstSrc *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope,...@@ -7820,28 +7820,28 @@ static IrInstSrc *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope,
7820 if (child_lval == LValAssign)7820 if (child_lval == LValAssign)
7821 child_lval = LValPtr;7821 child_lval = LValPtr;
78227822
7823 IrInstSrc *value = astgen_node_extra(ag, expr_node, scope, child_lval, nullptr);7823 Stage1ZirInst *value = astgen_node_extra(ag, expr_node, scope, child_lval, nullptr);
7824 if (value == ag->codegen->invalid_inst_src)7824 if (value == ag->codegen->invalid_inst_src)
7825 return value;7825 return value;
78267826
7827 // We essentially just converted any lvalue from &(x.*) to (&x).*;7827 // We essentially just converted any lvalue from &(x.*) to (&x).*;
7828 // this inhibits checking that x is a pointer later, so we directly7828 // this inhibits checking that x is a pointer later, so we directly
7829 // record whether the pointer check is needed7829 // record whether the pointer check is needed
7830 IrInstSrc *un_op = ir_build_un_op_lval(ag, scope, node, IrUnOpDereference, value, lval, result_loc);7830 Stage1ZirInst *un_op = ir_build_un_op_lval(ag, scope, node, IrUnOpDereference, value, lval, result_loc);
7831 return ir_expr_wrap(ag, scope, un_op, result_loc);7831 return ir_expr_wrap(ag, scope, un_op, result_loc);
7832 }7832 }
7833 case NodeTypeUnwrapOptional: {7833 case NodeTypeUnwrapOptional: {
7834 AstNode *expr_node = node->data.unwrap_optional.expr;7834 AstNode *expr_node = node->data.unwrap_optional.expr;
78357835
7836 IrInstSrc *maybe_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);7836 Stage1ZirInst *maybe_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
7837 if (maybe_ptr == ag->codegen->invalid_inst_src)7837 if (maybe_ptr == ag->codegen->invalid_inst_src)
7838 return ag->codegen->invalid_inst_src;7838 return ag->codegen->invalid_inst_src;
78397839
7840 IrInstSrc *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, scope, node, maybe_ptr, true );7840 Stage1ZirInst *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, scope, node, maybe_ptr, true );
7841 if (lval == LValPtr || lval == LValAssign)7841 if (lval == LValPtr || lval == LValAssign)
7842 return unwrapped_ptr;7842 return unwrapped_ptr;
78437843
7844 IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, unwrapped_ptr);7844 Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, unwrapped_ptr);
7845 return ir_expr_wrap(ag, scope, load_ptr, result_loc);7845 return ir_expr_wrap(ag, scope, load_ptr, result_loc);
7846 }7846 }
7847 case NodeTypeBoolLiteral:7847 case NodeTypeBoolLiteral:
...@@ -7915,7 +7915,7 @@ ResultLoc *no_result_loc(void) {...@@ -7915,7 +7915,7 @@ ResultLoc *no_result_loc(void) {
7915 return &result_loc_none->base;7915 return &result_loc_none->base;
7916}7916}
79177917
7918static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval,7918static Stage1ZirInst *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval,
7919 ResultLoc *result_loc)7919 ResultLoc *result_loc)
7920{7920{
7921 if (lval == LValAssign) {7921 if (lval == LValAssign) {
...@@ -8023,7 +8023,7 @@ static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scop...@@ -8023,7 +8023,7 @@ static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scop
8023 } else {8023 } else {
8024 child_scope = &create_expr_scope(ag->codegen, node, scope)->base;8024 child_scope = &create_expr_scope(ag->codegen, node, scope)->base;
8025 }8025 }
8026 IrInstSrc *result = astgen_node_raw(ag, node, child_scope, lval, result_loc);8026 Stage1ZirInst *result = astgen_node_raw(ag, node, child_scope, lval, result_loc);
8027 if (result == ag->codegen->invalid_inst_src) {8027 if (result == ag->codegen->invalid_inst_src) {
8028 if (ag->exec->first_err_trace_msg == nullptr) {8028 if (ag->exec->first_err_trace_msg == nullptr) {
8029 ag->exec->first_err_trace_msg = ag->codegen->trace_err;8029 ag->exec->first_err_trace_msg = ag->codegen->trace_err;
...@@ -8032,7 +8032,7 @@ static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scop...@@ -8032,7 +8032,7 @@ static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scop
8032 return result;8032 return result;
8033}8033}
80348034
8035static IrInstSrc *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope) {8035static Stage1ZirInst *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope) {
8036 return astgen_node_extra(ag, node, scope, LValNone, nullptr);8036 return astgen_node_extra(ag, node, scope, LValNone, nullptr);
8037}8037}
80388038
...@@ -8055,7 +8055,7 @@ bool stage1_astgen(CodeGen *codegen, AstNode *node, Scope *scope, Stage1Zir *sta...@@ -8055,7 +8055,7 @@ bool stage1_astgen(CodeGen *codegen, AstNode *node, Scope *scope, Stage1Zir *sta
8055 // Entry block gets a reference because we enter it to begin.8055 // Entry block gets a reference because we enter it to begin.
8056 ir_ref_bb(ag->current_basic_block);8056 ir_ref_bb(ag->current_basic_block);
80578057
8058 IrInstSrc *result = astgen_node_extra(ag, node, scope, LValNone, nullptr);8058 Stage1ZirInst *result = astgen_node_extra(ag, node, scope, LValNone, nullptr);
80598059
8060 if (result == ag->codegen->invalid_inst_src)8060 if (result == ag->codegen->invalid_inst_src)
8061 return false;8061 return false;
...@@ -8113,8 +8113,8 @@ void ir_add_call_stack_errors_gen(CodeGen *codegen, Stage1Air *exec, ErrorMsg *e...@@ -8113,8 +8113,8 @@ void ir_add_call_stack_errors_gen(CodeGen *codegen, Stage1Air *exec, ErrorMsg *e
8113 ir_add_call_stack_errors_gen(codegen, exec->parent_exec, err_msg, limit - 1);8113 ir_add_call_stack_errors_gen(codegen, exec->parent_exec, err_msg, limit - 1);
8114}8114}
81158115
8116void IrInstSrc::src() {8116void Stage1ZirInst::src() {
8117 IrInstSrc *inst = this;8117 Stage1ZirInst *inst = this;
8118 if (inst->source_node != nullptr) {8118 if (inst->source_node != nullptr) {
8119 inst->source_node->src();8119 inst->source_node->src();
8120 } else {8120 } else {
src/stage1/astgen.hpp+3-3
...@@ -14,10 +14,10 @@ bool stage1_astgen(CodeGen *g, AstNode *node, Scope *scope, Stage1Zir *stage1_zi...@@ -14,10 +14,10 @@ bool stage1_astgen(CodeGen *g, AstNode *node, Scope *scope, Stage1Zir *stage1_zi
14 ZigFn *fn, bool in_c_import_scope);14 ZigFn *fn, bool in_c_import_scope);
15bool stage1_astgen_fn(CodeGen *g, ZigFn *fn_entry);15bool stage1_astgen_fn(CodeGen *g, ZigFn *fn_entry);
1616
17bool ir_inst_src_has_side_effects(IrInstSrc *inst);17bool ir_inst_src_has_side_effects(Stage1ZirInst *inst);
1818
19ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope,19ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope,
20 Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime,20 Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime,
21 bool skip_name_check);21 bool skip_name_check);
2222
23ResultLoc *no_result_loc(void);23ResultLoc *no_result_loc(void);
...@@ -28,7 +28,7 @@ AstNode *ast_field_to_symbol_node(AstNode *err_set_field_node);...@@ -28,7 +28,7 @@ AstNode *ast_field_to_symbol_node(AstNode *err_set_field_node);
28void ir_add_call_stack_errors_gen(CodeGen *codegen, Stage1Air *exec, ErrorMsg *err_msg,28void ir_add_call_stack_errors_gen(CodeGen *codegen, Stage1Air *exec, ErrorMsg *err_msg,
29 int limit);29 int limit);
3030
31void destroy_instruction_src(IrInstSrc *inst);31void destroy_instruction_src(Stage1ZirInst *inst);
3232
33bool ir_should_inline(Stage1Zir *exec, Scope *scope);33bool ir_should_inline(Stage1Zir *exec, Scope *scope);
34Buf *get_anon_type_name(CodeGen *codegen, Stage1Zir *exec, const char *kind_name,34Buf *get_anon_type_name(CodeGen *codegen, Stage1Zir *exec, const char *kind_name,
src/stage1/codegen.cpp+301-301
...@@ -84,7 +84,7 @@ static void generate_error_name_table(CodeGen *g);...@@ -84,7 +84,7 @@ static void generate_error_name_table(CodeGen *g);
84static bool value_is_all_undef(CodeGen *g, ZigValue *const_val);84static bool value_is_all_undef(CodeGen *g, ZigValue *const_val);
85static void gen_undef_init(CodeGen *g, ZigType *ptr_type, ZigType *value_type, LLVMValueRef ptr);85static void gen_undef_init(CodeGen *g, ZigType *ptr_type, ZigType *value_type, LLVMValueRef ptr);
86static LLVMValueRef build_alloca(CodeGen *g, ZigType *type_entry, const char *name, uint32_t alignment);86static LLVMValueRef build_alloca(CodeGen *g, ZigType *type_entry, const char *name, uint32_t alignment);
87static LLVMValueRef gen_await_early_return(CodeGen *g, IrInstGen *source_instr,87static LLVMValueRef gen_await_early_return(CodeGen *g, Stage1AirInst *source_instr,
88 LLVMValueRef target_frame_ptr, ZigType *result_type, ZigType *ptr_result_type,88 LLVMValueRef target_frame_ptr, ZigType *result_type, ZigType *ptr_result_type,
89 LLVMValueRef result_loc, bool non_async);89 LLVMValueRef result_loc, bool non_async);
9090
...@@ -906,14 +906,14 @@ static LLVMValueRef get_handle_value(CodeGen *g, LLVMValueRef ptr, ZigType *type...@@ -906,14 +906,14 @@ static LLVMValueRef get_handle_value(CodeGen *g, LLVMValueRef ptr, ZigType *type
906 }906 }
907}907}
908908
909static void ir_assert_impl(bool ok, IrInstGen *source_instruction, const char *file, unsigned int line) {909static void ir_assert_impl(bool ok, Stage1AirInst *source_instruction, const char *file, unsigned int line) {
910 if (ok) return;910 if (ok) return;
911 src_assert_impl(ok, source_instruction->source_node, file, line);911 src_assert_impl(ok, source_instruction->source_node, file, line);
912}912}
913913
914#define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__)914#define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__)
915915
916static bool ir_want_fast_math(CodeGen *g, IrInstGen *instruction) {916static bool ir_want_fast_math(CodeGen *g, Stage1AirInst *instruction) {
917 // TODO memoize917 // TODO memoize
918 Scope *scope = instruction->scope;918 Scope *scope = instruction->scope;
919 while (scope) {919 while (scope) {
...@@ -950,7 +950,7 @@ static bool ir_want_runtime_safety_scope(CodeGen *g, Scope *scope) {...@@ -950,7 +950,7 @@ static bool ir_want_runtime_safety_scope(CodeGen *g, Scope *scope) {
950 g->build_mode != BuildModeSmallRelease);950 g->build_mode != BuildModeSmallRelease);
951}951}
952952
953static bool ir_want_runtime_safety(CodeGen *g, IrInstGen *instruction) {953static bool ir_want_runtime_safety(CodeGen *g, Stage1AirInst *instruction) {
954 return ir_want_runtime_safety_scope(g, instruction->scope);954 return ir_want_runtime_safety_scope(g, instruction->scope);
955}955}
956956
...@@ -1077,7 +1077,7 @@ static void gen_assertion_scope(CodeGen *g, PanicMsgId msg_id, Scope *source_sco...@@ -1077,7 +1077,7 @@ static void gen_assertion_scope(CodeGen *g, PanicMsgId msg_id, Scope *source_sco
1077 }1077 }
1078}1078}
10791079
1080static void gen_assertion(CodeGen *g, PanicMsgId msg_id, IrInstGen *source_instruction) {1080static void gen_assertion(CodeGen *g, PanicMsgId msg_id, Stage1AirInst *source_instruction) {
1081 return gen_assertion_scope(g, msg_id, source_instruction->scope);1081 return gen_assertion_scope(g, msg_id, source_instruction->scope);
1082}1082}
10831083
...@@ -1816,7 +1816,7 @@ static void gen_var_debug_decl(CodeGen *g, ZigVar *var) {...@@ -1816,7 +1816,7 @@ static void gen_var_debug_decl(CodeGen *g, ZigVar *var) {
1816 LLVMGetInsertBlock(g->builder));1816 LLVMGetInsertBlock(g->builder));
1817}1817}
18181818
1819static LLVMValueRef ir_llvm_value(CodeGen *g, IrInstGen *instruction) {1819static LLVMValueRef ir_llvm_value(CodeGen *g, Stage1AirInst *instruction) {
1820 Error err;1820 Error err;
18211821
1822 bool value_has_bits;1822 bool value_has_bits;
...@@ -1827,8 +1827,8 @@ static LLVMValueRef ir_llvm_value(CodeGen *g, IrInstGen *instruction) {...@@ -1827,8 +1827,8 @@ static LLVMValueRef ir_llvm_value(CodeGen *g, IrInstGen *instruction) {
1827 return nullptr;1827 return nullptr;
18281828
1829 if (!instruction->llvm_value) {1829 if (!instruction->llvm_value) {
1830 if (instruction->id == IrInstGenIdAwait) {1830 if (instruction->id == Stage1AirInstIdAwait) {
1831 IrInstGenAwait *await = reinterpret_cast<IrInstGenAwait*>(instruction);1831 Stage1AirInstAwait *await = reinterpret_cast<Stage1AirInstAwait*>(instruction);
1832 if (await->result_loc != nullptr) {1832 if (await->result_loc != nullptr) {
1833 return get_handle_value(g, ir_llvm_value(g, await->result_loc),1833 return get_handle_value(g, ir_llvm_value(g, await->result_loc),
1834 await->result_loc->value->type->data.pointer.child_type, await->result_loc->value->type);1834 await->result_loc->value->type->data.pointer.child_type, await->result_loc->value->type);
...@@ -1921,7 +1921,7 @@ static bool iter_function_params_c_abi(CodeGen *g, ZigType *fn_type, FnWalk *fn_...@@ -1921,7 +1921,7 @@ static bool iter_function_params_c_abi(CodeGen *g, ZigType *fn_type, FnWalk *fn_
1921 case FnWalkIdCall: {1921 case FnWalkIdCall: {
1922 if (src_i >= fn_walk->data.call.inst->arg_count)1922 if (src_i >= fn_walk->data.call.inst->arg_count)
1923 return false;1923 return false;
1924 IrInstGen *arg = fn_walk->data.call.inst->args[src_i];1924 Stage1AirInst *arg = fn_walk->data.call.inst->args[src_i];
1925 ty = arg->value->type;1925 ty = arg->value->type;
1926 source_node = arg->source_node;1926 source_node = arg->source_node;
1927 val = ir_llvm_value(g, arg);1927 val = ir_llvm_value(g, arg);
...@@ -2228,10 +2228,10 @@ void walk_function_params(CodeGen *g, ZigType *fn_type, FnWalk *fn_walk) {...@@ -2228,10 +2228,10 @@ void walk_function_params(CodeGen *g, ZigType *fn_type, FnWalk *fn_walk) {
2228 return;2228 return;
2229 }2229 }
2230 if (fn_walk->id == FnWalkIdCall) {2230 if (fn_walk->id == FnWalkIdCall) {
2231 IrInstGenCall *instruction = fn_walk->data.call.inst;2231 Stage1AirInstCall *instruction = fn_walk->data.call.inst;
2232 bool is_var_args = fn_walk->data.call.is_var_args;2232 bool is_var_args = fn_walk->data.call.is_var_args;
2233 for (size_t call_i = 0; call_i < instruction->arg_count; call_i += 1) {2233 for (size_t call_i = 0; call_i < instruction->arg_count; call_i += 1) {
2234 IrInstGen *param_instruction = instruction->args[call_i];2234 Stage1AirInst *param_instruction = instruction->args[call_i];
2235 ZigType *param_type = param_instruction->value->type;2235 ZigType *param_type = param_instruction->value->type;
2236 if (is_var_args || type_has_bits(g, param_type)) {2236 if (is_var_args || type_has_bits(g, param_type)) {
2237 LLVMValueRef param_value = ir_llvm_value(g, param_instruction);2237 LLVMValueRef param_value = ir_llvm_value(g, param_instruction);
...@@ -2445,7 +2445,7 @@ static LLVMValueRef get_merge_err_ret_traces_fn_val(CodeGen *g) {...@@ -2445,7 +2445,7 @@ static LLVMValueRef get_merge_err_ret_traces_fn_val(CodeGen *g) {
24452445
2446}2446}
2447static LLVMValueRef ir_render_save_err_ret_addr(CodeGen *g, Stage1Air *executable,2447static LLVMValueRef ir_render_save_err_ret_addr(CodeGen *g, Stage1Air *executable,
2448 IrInstGenSaveErrRetAddr *save_err_ret_addr_instruction)2448 Stage1AirInstSaveErrRetAddr *save_err_ret_addr_instruction)
2449{2449{
2450 assert(g->have_err_ret_tracing);2450 assert(g->have_err_ret_tracing);
24512451
...@@ -2466,7 +2466,7 @@ static LLVMValueRef ir_render_save_err_ret_addr(CodeGen *g, Stage1Air *executabl...@@ -2466,7 +2466,7 @@ static LLVMValueRef ir_render_save_err_ret_addr(CodeGen *g, Stage1Air *executabl
2466 return nullptr;2466 return nullptr;
2467}2467}
24682468
2469static void gen_assert_resume_id(CodeGen *g, IrInstGen *source_instr, ResumeId resume_id, PanicMsgId msg_id,2469static void gen_assert_resume_id(CodeGen *g, Stage1AirInst *source_instr, ResumeId resume_id, PanicMsgId msg_id,
2470 LLVMBasicBlockRef end_bb)2470 LLVMBasicBlockRef end_bb)
2471{2471{
2472 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;2472 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;
...@@ -2543,7 +2543,7 @@ static LLVMValueRef gen_maybe_atomic_op(CodeGen *g, LLVMAtomicRMWBinOp op, LLVMV...@@ -2543,7 +2543,7 @@ static LLVMValueRef gen_maybe_atomic_op(CodeGen *g, LLVMAtomicRMWBinOp op, LLVMV
2543 }2543 }
2544}2544}
25452545
2546static void gen_async_return(CodeGen *g, IrInstGenReturn *instruction) {2546static void gen_async_return(CodeGen *g, Stage1AirInstReturn *instruction) {
2547 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;2547 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;
25482548
2549 ZigType *operand_type = (instruction->operand != nullptr) ? instruction->operand->value->type : nullptr;2549 ZigType *operand_type = (instruction->operand != nullptr) ? instruction->operand->value->type : nullptr;
...@@ -2637,7 +2637,7 @@ static void gen_async_return(CodeGen *g, IrInstGenReturn *instruction) {...@@ -2637,7 +2637,7 @@ static void gen_async_return(CodeGen *g, IrInstGenReturn *instruction) {
2637 LLVMBuildRetVoid(g->builder);2637 LLVMBuildRetVoid(g->builder);
2638}2638}
26392639
2640static LLVMValueRef ir_render_return(CodeGen *g, Stage1Air *executable, IrInstGenReturn *instruction) {2640static LLVMValueRef ir_render_return(CodeGen *g, Stage1Air *executable, Stage1AirInstReturn *instruction) {
2641 if (fn_is_async(g->cur_fn)) {2641 if (fn_is_async(g->cur_fn)) {
2642 gen_async_return(g, instruction);2642 gen_async_return(g, instruction);
2643 return nullptr;2643 return nullptr;
...@@ -3063,11 +3063,11 @@ static void gen_shift_rhs_check(CodeGen *g, ZigType *lhs_type, ZigType *rhs_type...@@ -3063,11 +3063,11 @@ static void gen_shift_rhs_check(CodeGen *g, ZigType *lhs_type, ZigType *rhs_type
3063}3063}
30643064
3065static LLVMValueRef ir_render_bin_op(CodeGen *g, Stage1Air *executable,3065static LLVMValueRef ir_render_bin_op(CodeGen *g, Stage1Air *executable,
3066 IrInstGenBinOp *bin_op_instruction)3066 Stage1AirInstBinOp *bin_op_instruction)
3067{3067{
3068 IrBinOp op_id = bin_op_instruction->op_id;3068 IrBinOp op_id = bin_op_instruction->op_id;
3069 IrInstGen *op1 = bin_op_instruction->op1;3069 Stage1AirInst *op1 = bin_op_instruction->op1;
3070 IrInstGen *op2 = bin_op_instruction->op2;3070 Stage1AirInst *op2 = bin_op_instruction->op2;
30713071
3072 ZigType *operand_type = op1->value->type;3072 ZigType *operand_type = op1->value->type;
3073 ZigType *scalar_type = (operand_type->id == ZigTypeIdVector) ? operand_type->data.vector.elem_type : operand_type;3073 ZigType *scalar_type = (operand_type->id == ZigTypeIdVector) ? operand_type->data.vector.elem_type : operand_type;
...@@ -3285,7 +3285,7 @@ static void add_error_range_check(CodeGen *g, ZigType *err_set_type, ZigType *in...@@ -3285,7 +3285,7 @@ static void add_error_range_check(CodeGen *g, ZigType *err_set_type, ZigType *in
3285}3285}
32863286
3287static LLVMValueRef ir_render_cast(CodeGen *g, Stage1Air *executable,3287static LLVMValueRef ir_render_cast(CodeGen *g, Stage1Air *executable,
3288 IrInstGenCast *cast_instruction)3288 Stage1AirInstCast *cast_instruction)
3289{3289{
3290 Error err;3290 Error err;
3291 ZigType *actual_type = cast_instruction->value->value->type;3291 ZigType *actual_type = cast_instruction->value->value->type;
...@@ -3369,7 +3369,7 @@ static LLVMValueRef ir_render_cast(CodeGen *g, Stage1Air *executable,...@@ -3369,7 +3369,7 @@ static LLVMValueRef ir_render_cast(CodeGen *g, Stage1Air *executable,
3369}3369}
33703370
3371static LLVMValueRef ir_render_ptr_of_array_to_slice(CodeGen *g, Stage1Air *executable,3371static LLVMValueRef ir_render_ptr_of_array_to_slice(CodeGen *g, Stage1Air *executable,
3372 IrInstGenPtrOfArrayToSlice *instruction)3372 Stage1AirInstPtrOfArrayToSlice *instruction)
3373{3373{
3374 ZigType *actual_type = instruction->operand->value->type;3374 ZigType *actual_type = instruction->operand->value->type;
3375 ZigType *slice_type = instruction->base.value->type;3375 ZigType *slice_type = instruction->base.value->type;
...@@ -3406,7 +3406,7 @@ static LLVMValueRef ir_render_ptr_of_array_to_slice(CodeGen *g, Stage1Air *execu...@@ -3406,7 +3406,7 @@ static LLVMValueRef ir_render_ptr_of_array_to_slice(CodeGen *g, Stage1Air *execu
3406}3406}
34073407
3408static LLVMValueRef ir_render_ptr_cast(CodeGen *g, Stage1Air *executable,3408static LLVMValueRef ir_render_ptr_cast(CodeGen *g, Stage1Air *executable,
3409 IrInstGenPtrCast *instruction)3409 Stage1AirInstPtrCast *instruction)
3410{3410{
3411 ZigType *wanted_type = instruction->base.value->type;3411 ZigType *wanted_type = instruction->base.value->type;
3412 if (!type_has_bits(g, wanted_type)) {3412 if (!type_has_bits(g, wanted_type)) {
...@@ -3432,7 +3432,7 @@ static LLVMValueRef ir_render_ptr_cast(CodeGen *g, Stage1Air *executable,...@@ -3432,7 +3432,7 @@ static LLVMValueRef ir_render_ptr_cast(CodeGen *g, Stage1Air *executable,
3432}3432}
34333433
3434static LLVMValueRef ir_render_bit_cast(CodeGen *g, Stage1Air *executable,3434static LLVMValueRef ir_render_bit_cast(CodeGen *g, Stage1Air *executable,
3435 IrInstGenBitCast *instruction)3435 Stage1AirInstBitCast *instruction)
3436{3436{
3437 ZigType *wanted_type = instruction->base.value->type;3437 ZigType *wanted_type = instruction->base.value->type;
3438 ZigType *actual_type = instruction->operand->value->type;3438 ZigType *actual_type = instruction->operand->value->type;
...@@ -3460,7 +3460,7 @@ static LLVMValueRef ir_render_bit_cast(CodeGen *g, Stage1Air *executable,...@@ -3460,7 +3460,7 @@ static LLVMValueRef ir_render_bit_cast(CodeGen *g, Stage1Air *executable,
3460}3460}
34613461
3462static LLVMValueRef ir_render_widen_or_shorten(CodeGen *g, Stage1Air *executable,3462static LLVMValueRef ir_render_widen_or_shorten(CodeGen *g, Stage1Air *executable,
3463 IrInstGenWidenOrShorten *instruction)3463 Stage1AirInstWidenOrShorten *instruction)
3464{3464{
3465 ZigType *actual_type = instruction->target->value->type;3465 ZigType *actual_type = instruction->target->value->type;
3466 // TODO instead of this logic, use the Noop instruction to change the type from3466 // TODO instead of this logic, use the Noop instruction to change the type from
...@@ -3476,7 +3476,7 @@ static LLVMValueRef ir_render_widen_or_shorten(CodeGen *g, Stage1Air *executable...@@ -3476,7 +3476,7 @@ static LLVMValueRef ir_render_widen_or_shorten(CodeGen *g, Stage1Air *executable
3476 instruction->base.value->type, target_val);3476 instruction->base.value->type, target_val);
3477}3477}
34783478
3479static LLVMValueRef ir_render_int_to_ptr(CodeGen *g, Stage1Air *executable, IrInstGenIntToPtr *instruction) {3479static LLVMValueRef ir_render_int_to_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstIntToPtr *instruction) {
3480 ZigType *wanted_type = instruction->base.value->type;3480 ZigType *wanted_type = instruction->base.value->type;
3481 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);3481 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);
3482 const uint32_t align_bytes = get_ptr_align(g, wanted_type);3482 const uint32_t align_bytes = get_ptr_align(g, wanted_type);
...@@ -3514,13 +3514,13 @@ static LLVMValueRef ir_render_int_to_ptr(CodeGen *g, Stage1Air *executable, IrIn...@@ -3514,13 +3514,13 @@ static LLVMValueRef ir_render_int_to_ptr(CodeGen *g, Stage1Air *executable, IrIn
3514 return LLVMBuildIntToPtr(g->builder, target_val, get_llvm_type(g, wanted_type), "");3514 return LLVMBuildIntToPtr(g->builder, target_val, get_llvm_type(g, wanted_type), "");
3515}3515}
35163516
3517static LLVMValueRef ir_render_ptr_to_int(CodeGen *g, Stage1Air *executable, IrInstGenPtrToInt *instruction) {3517static LLVMValueRef ir_render_ptr_to_int(CodeGen *g, Stage1Air *executable, Stage1AirInstPtrToInt *instruction) {
3518 ZigType *wanted_type = instruction->base.value->type;3518 ZigType *wanted_type = instruction->base.value->type;
3519 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);3519 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);
3520 return LLVMBuildPtrToInt(g->builder, target_val, get_llvm_type(g, wanted_type), "");3520 return LLVMBuildPtrToInt(g->builder, target_val, get_llvm_type(g, wanted_type), "");
3521}3521}
35223522
3523static LLVMValueRef ir_render_int_to_enum(CodeGen *g, Stage1Air *executable, IrInstGenIntToEnum *instruction) {3523static LLVMValueRef ir_render_int_to_enum(CodeGen *g, Stage1Air *executable, Stage1AirInstIntToEnum *instruction) {
3524 ZigType *wanted_type = instruction->base.value->type;3524 ZigType *wanted_type = instruction->base.value->type;
3525 assert(wanted_type->id == ZigTypeIdEnum);3525 assert(wanted_type->id == ZigTypeIdEnum);
3526 ZigType *tag_int_type = wanted_type->data.enumeration.tag_int_type;3526 ZigType *tag_int_type = wanted_type->data.enumeration.tag_int_type;
...@@ -3560,7 +3560,7 @@ static LLVMValueRef ir_render_int_to_enum(CodeGen *g, Stage1Air *executable, IrI...@@ -3560,7 +3560,7 @@ static LLVMValueRef ir_render_int_to_enum(CodeGen *g, Stage1Air *executable, IrI
3560 return tag_int_value;3560 return tag_int_value;
3561}3561}
35623562
3563static LLVMValueRef ir_render_int_to_err(CodeGen *g, Stage1Air *executable, IrInstGenIntToErr *instruction) {3563static LLVMValueRef ir_render_int_to_err(CodeGen *g, Stage1Air *executable, Stage1AirInstIntToErr *instruction) {
3564 ZigType *wanted_type = instruction->base.value->type;3564 ZigType *wanted_type = instruction->base.value->type;
3565 assert(wanted_type->id == ZigTypeIdErrorSet);3565 assert(wanted_type->id == ZigTypeIdErrorSet);
35663566
...@@ -3577,7 +3577,7 @@ static LLVMValueRef ir_render_int_to_err(CodeGen *g, Stage1Air *executable, IrIn...@@ -3577,7 +3577,7 @@ static LLVMValueRef ir_render_int_to_err(CodeGen *g, Stage1Air *executable, IrIn
3577 return gen_widen_or_shorten(g, false, actual_type, g->err_tag_type, target_val);3577 return gen_widen_or_shorten(g, false, actual_type, g->err_tag_type, target_val);
3578}3578}
35793579
3580static LLVMValueRef ir_render_err_to_int(CodeGen *g, Stage1Air *executable, IrInstGenErrToInt *instruction) {3580static LLVMValueRef ir_render_err_to_int(CodeGen *g, Stage1Air *executable, Stage1AirInstErrToInt *instruction) {
3581 ZigType *wanted_type = instruction->base.value->type;3581 ZigType *wanted_type = instruction->base.value->type;
3582 assert(wanted_type->id == ZigTypeIdInt);3582 assert(wanted_type->id == ZigTypeIdInt);
3583 assert(!wanted_type->data.integral.is_signed);3583 assert(!wanted_type->data.integral.is_signed);
...@@ -3604,7 +3604,7 @@ static LLVMValueRef ir_render_err_to_int(CodeGen *g, Stage1Air *executable, IrIn...@@ -3604,7 +3604,7 @@ static LLVMValueRef ir_render_err_to_int(CodeGen *g, Stage1Air *executable, IrIn
3604}3604}
36053605
3606static LLVMValueRef ir_render_unreachable(CodeGen *g, Stage1Air *executable,3606static LLVMValueRef ir_render_unreachable(CodeGen *g, Stage1Air *executable,
3607 IrInstGenUnreachable *unreachable_instruction)3607 Stage1AirInstUnreachable *unreachable_instruction)
3608{3608{
3609 if (ir_want_runtime_safety(g, &unreachable_instruction->base)) {3609 if (ir_want_runtime_safety(g, &unreachable_instruction->base)) {
3610 gen_safety_crash(g, PanicMsgIdUnreachable);3610 gen_safety_crash(g, PanicMsgIdUnreachable);
...@@ -3615,7 +3615,7 @@ static LLVMValueRef ir_render_unreachable(CodeGen *g, Stage1Air *executable,...@@ -3615,7 +3615,7 @@ static LLVMValueRef ir_render_unreachable(CodeGen *g, Stage1Air *executable,
3615}3615}
36163616
3617static LLVMValueRef ir_render_cond_br(CodeGen *g, Stage1Air *executable,3617static LLVMValueRef ir_render_cond_br(CodeGen *g, Stage1Air *executable,
3618 IrInstGenCondBr *cond_br_instruction)3618 Stage1AirInstCondBr *cond_br_instruction)
3619{3619{
3620 LLVMBuildCondBr(g->builder,3620 LLVMBuildCondBr(g->builder,
3621 ir_llvm_value(g, cond_br_instruction->condition),3621 ir_llvm_value(g, cond_br_instruction->condition),
...@@ -3624,19 +3624,19 @@ static LLVMValueRef ir_render_cond_br(CodeGen *g, Stage1Air *executable,...@@ -3624,19 +3624,19 @@ static LLVMValueRef ir_render_cond_br(CodeGen *g, Stage1Air *executable,
3624 return nullptr;3624 return nullptr;
3625}3625}
36263626
3627static LLVMValueRef ir_render_br(CodeGen *g, Stage1Air *executable, IrInstGenBr *br_instruction) {3627static LLVMValueRef ir_render_br(CodeGen *g, Stage1Air *executable, Stage1AirInstBr *br_instruction) {
3628 LLVMBuildBr(g->builder, br_instruction->dest_block->llvm_block);3628 LLVMBuildBr(g->builder, br_instruction->dest_block->llvm_block);
3629 return nullptr;3629 return nullptr;
3630}3630}
36313631
3632static LLVMValueRef ir_render_binary_not(CodeGen *g, Stage1Air *executable,3632static LLVMValueRef ir_render_binary_not(CodeGen *g, Stage1Air *executable,
3633 IrInstGenBinaryNot *inst)3633 Stage1AirInstBinaryNot *inst)
3634{3634{
3635 LLVMValueRef operand = ir_llvm_value(g, inst->operand);3635 LLVMValueRef operand = ir_llvm_value(g, inst->operand);
3636 return LLVMBuildNot(g->builder, operand, "");3636 return LLVMBuildNot(g->builder, operand, "");
3637}3637}
36383638
3639static LLVMValueRef ir_gen_negation(CodeGen *g, IrInstGen *inst, IrInstGen *operand, bool wrapping) {3639static LLVMValueRef ir_gen_negation(CodeGen *g, Stage1AirInst *inst, Stage1AirInst *operand, bool wrapping) {
3640 LLVMValueRef llvm_operand = ir_llvm_value(g, operand);3640 LLVMValueRef llvm_operand = ir_llvm_value(g, operand);
3641 ZigType *operand_type = operand->value->type;3641 ZigType *operand_type = operand->value->type;
3642 ZigType *scalar_type = (operand_type->id == ZigTypeIdVector) ?3642 ZigType *scalar_type = (operand_type->id == ZigTypeIdVector) ?
...@@ -3662,12 +3662,12 @@ static LLVMValueRef ir_gen_negation(CodeGen *g, IrInstGen *inst, IrInstGen *oper...@@ -3662,12 +3662,12 @@ static LLVMValueRef ir_gen_negation(CodeGen *g, IrInstGen *inst, IrInstGen *oper
3662}3662}
36633663
3664static LLVMValueRef ir_render_negation(CodeGen *g, Stage1Air *executable,3664static LLVMValueRef ir_render_negation(CodeGen *g, Stage1Air *executable,
3665 IrInstGenNegation *inst)3665 Stage1AirInstNegation *inst)
3666{3666{
3667 return ir_gen_negation(g, &inst->base, inst->operand, inst->wrapping);3667 return ir_gen_negation(g, &inst->base, inst->operand, inst->wrapping);
3668}3668}
36693669
3670static LLVMValueRef ir_render_bool_not(CodeGen *g, Stage1Air *executable, IrInstGenBoolNot *instruction) {3670static LLVMValueRef ir_render_bool_not(CodeGen *g, Stage1Air *executable, Stage1AirInstBoolNot *instruction) {
3671 LLVMValueRef value = ir_llvm_value(g, instruction->value);3671 LLVMValueRef value = ir_llvm_value(g, instruction->value);
3672 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(value));3672 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(value));
3673 return LLVMBuildICmp(g->builder, LLVMIntEQ, value, zero, "");3673 return LLVMBuildICmp(g->builder, LLVMIntEQ, value, zero, "");
...@@ -3681,7 +3681,7 @@ static void render_decl_var(CodeGen *g, ZigVar *var) {...@@ -3681,7 +3681,7 @@ static void render_decl_var(CodeGen *g, ZigVar *var) {
3681 gen_var_debug_decl(g, var);3681 gen_var_debug_decl(g, var);
3682}3682}
36833683
3684static LLVMValueRef ir_render_decl_var(CodeGen *g, Stage1Air *executable, IrInstGenDeclVar *instruction) {3684static LLVMValueRef ir_render_decl_var(CodeGen *g, Stage1Air *executable, Stage1AirInstDeclVar *instruction) {
3685 instruction->var->ptr_instruction = instruction->var_ptr;3685 instruction->var->ptr_instruction = instruction->var_ptr;
3686 instruction->var->did_the_decl_codegen = true;3686 instruction->var->did_the_decl_codegen = true;
3687 render_decl_var(g, instruction->var);3687 render_decl_var(g, instruction->var);
...@@ -3689,7 +3689,7 @@ static LLVMValueRef ir_render_decl_var(CodeGen *g, Stage1Air *executable, IrInst...@@ -3689,7 +3689,7 @@ static LLVMValueRef ir_render_decl_var(CodeGen *g, Stage1Air *executable, IrInst
3689}3689}
36903690
3691static LLVMValueRef ir_render_load_ptr(CodeGen *g, Stage1Air *executable,3691static LLVMValueRef ir_render_load_ptr(CodeGen *g, Stage1Air *executable,
3692 IrInstGenLoadPtr *instruction)3692 Stage1AirInstLoadPtr *instruction)
3693{3693{
3694 ZigType *child_type = instruction->base.value->type;3694 ZigType *child_type = instruction->base.value->type;
3695 if (!type_has_bits(g, child_type))3695 if (!type_has_bits(g, child_type))
...@@ -3896,7 +3896,7 @@ static void gen_undef_init(CodeGen *g, ZigType *ptr_type, ZigType *value_type, L...@@ -3896,7 +3896,7 @@ static void gen_undef_init(CodeGen *g, ZigType *ptr_type, ZigType *value_type, L
3896 gen_assign_raw(g, ptr, ptr_type, zero);3896 gen_assign_raw(g, ptr, ptr_type, zero);
3897}3897}
38983898
3899static LLVMValueRef ir_render_store_ptr(CodeGen *g, Stage1Air *executable, IrInstGenStorePtr *instruction) {3899static LLVMValueRef ir_render_store_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstStorePtr *instruction) {
3900 Error err;3900 Error err;
39013901
3902 ZigType *ptr_type = instruction->ptr->value->type;3902 ZigType *ptr_type = instruction->ptr->value->type;
...@@ -3929,7 +3929,7 @@ static LLVMValueRef ir_render_store_ptr(CodeGen *g, Stage1Air *executable, IrIns...@@ -3929,7 +3929,7 @@ static LLVMValueRef ir_render_store_ptr(CodeGen *g, Stage1Air *executable, IrIns
3929}3929}
39303930
3931static LLVMValueRef ir_render_vector_store_elem(CodeGen *g, Stage1Air *executable,3931static LLVMValueRef ir_render_vector_store_elem(CodeGen *g, Stage1Air *executable,
3932 IrInstGenVectorStoreElem *instruction)3932 Stage1AirInstVectorStoreElem *instruction)
3933{3933{
3934 LLVMValueRef vector_ptr = ir_llvm_value(g, instruction->vector_ptr);3934 LLVMValueRef vector_ptr = ir_llvm_value(g, instruction->vector_ptr);
3935 LLVMValueRef index = ir_llvm_value(g, instruction->index);3935 LLVMValueRef index = ir_llvm_value(g, instruction->index);
...@@ -3941,7 +3941,7 @@ static LLVMValueRef ir_render_vector_store_elem(CodeGen *g, Stage1Air *executabl...@@ -3941,7 +3941,7 @@ static LLVMValueRef ir_render_vector_store_elem(CodeGen *g, Stage1Air *executabl
3941 return nullptr;3941 return nullptr;
3942}3942}
39433943
3944static LLVMValueRef ir_render_var_ptr(CodeGen *g, Stage1Air *executable, IrInstGenVarPtr *instruction) {3944static LLVMValueRef ir_render_var_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstVarPtr *instruction) {
3945 Error err;3945 Error err;
39463946
3947 ZigType *ptr_type = instruction->base.value->type;3947 ZigType *ptr_type = instruction->base.value->type;
...@@ -3969,7 +3969,7 @@ static LLVMValueRef ir_render_var_ptr(CodeGen *g, Stage1Air *executable, IrInstG...@@ -3969,7 +3969,7 @@ static LLVMValueRef ir_render_var_ptr(CodeGen *g, Stage1Air *executable, IrInstG
3969}3969}
39703970
3971static LLVMValueRef ir_render_return_ptr(CodeGen *g, Stage1Air *executable,3971static LLVMValueRef ir_render_return_ptr(CodeGen *g, Stage1Air *executable,
3972 IrInstGenReturnPtr *instruction)3972 Stage1AirInstReturnPtr *instruction)
3973{3973{
3974 if (!type_has_bits(g, instruction->base.value->type))3974 if (!type_has_bits(g, instruction->base.value->type))
3975 return nullptr;3975 return nullptr;
...@@ -3977,7 +3977,7 @@ static LLVMValueRef ir_render_return_ptr(CodeGen *g, Stage1Air *executable,...@@ -3977,7 +3977,7 @@ static LLVMValueRef ir_render_return_ptr(CodeGen *g, Stage1Air *executable,
3977 return g->cur_ret_ptr;3977 return g->cur_ret_ptr;
3978}3978}
39793979
3980static LLVMValueRef ir_render_elem_ptr(CodeGen *g, Stage1Air *executable, IrInstGenElemPtr *instruction) {3980static LLVMValueRef ir_render_elem_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstElemPtr *instruction) {
3981 LLVMValueRef array_ptr_ptr = ir_llvm_value(g, instruction->array_ptr);3981 LLVMValueRef array_ptr_ptr = ir_llvm_value(g, instruction->array_ptr);
3982 ZigType *array_ptr_type = instruction->array_ptr->value->type;3982 ZigType *array_ptr_type = instruction->array_ptr->value->type;
3983 assert(array_ptr_type->id == ZigTypeIdPointer);3983 assert(array_ptr_type->id == ZigTypeIdPointer);
...@@ -4152,7 +4152,7 @@ static void render_async_spills(CodeGen *g) {...@@ -4152,7 +4152,7 @@ static void render_async_spills(CodeGen *g) {
4152 ZigType *frame_type = g->cur_fn->frame_type->data.frame.locals_struct;4152 ZigType *frame_type = g->cur_fn->frame_type->data.frame.locals_struct;
41534153
4154 for (size_t alloca_i = 0; alloca_i < g->cur_fn->alloca_gen_list.length; alloca_i += 1) {4154 for (size_t alloca_i = 0; alloca_i < g->cur_fn->alloca_gen_list.length; alloca_i += 1) {
4155 IrInstGenAlloca *instruction = g->cur_fn->alloca_gen_list.at(alloca_i);4155 Stage1AirInstAlloca *instruction = g->cur_fn->alloca_gen_list.at(alloca_i);
4156 if (instruction->field_index == SIZE_MAX)4156 if (instruction->field_index == SIZE_MAX)
4157 continue;4157 continue;
41584158
...@@ -4229,7 +4229,7 @@ static void gen_init_stack_trace(CodeGen *g, LLVMValueRef trace_field_ptr, LLVMV...@@ -4229,7 +4229,7 @@ static void gen_init_stack_trace(CodeGen *g, LLVMValueRef trace_field_ptr, LLVMV
4229 LLVMBuildStore(g->builder, LLVMConstInt(usize_type_ref, stack_trace_ptr_count, false), addrs_len_ptr);4229 LLVMBuildStore(g->builder, LLVMConstInt(usize_type_ref, stack_trace_ptr_count, false), addrs_len_ptr);
4230}4230}
42314231
4232static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, IrInstGenCall *instruction) {4232static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, Stage1AirInstCall *instruction) {
4233 Error err;4233 Error err;
42344234
4235 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;4235 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;
...@@ -4579,7 +4579,7 @@ static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, IrInstGenC...@@ -4579,7 +4579,7 @@ static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, IrInstGenC
4579 return nullptr;4579 return nullptr;
45804580
4581 if (result_loc != nullptr) {4581 if (result_loc != nullptr) {
4582 if (instruction->result_loc->id == IrInstGenIdReturnPtr) {4582 if (instruction->result_loc->id == Stage1AirInstIdReturnPtr) {
4583 instruction->base.spill = nullptr;4583 instruction->base.spill = nullptr;
4584 return g->cur_ret_ptr;4584 return g->cur_ret_ptr;
4585 } else {4585 } else {
...@@ -4650,7 +4650,7 @@ static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, IrInstGenC...@@ -4650,7 +4650,7 @@ static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, IrInstGenC
4650}4650}
46514651
4652static LLVMValueRef ir_render_struct_field_ptr(CodeGen *g, Stage1Air *executable,4652static LLVMValueRef ir_render_struct_field_ptr(CodeGen *g, Stage1Air *executable,
4653 IrInstGenStructFieldPtr *instruction)4653 Stage1AirInstStructFieldPtr *instruction)
4654{4654{
4655 Error err;4655 Error err;
46564656
...@@ -4701,7 +4701,7 @@ static LLVMValueRef ir_render_struct_field_ptr(CodeGen *g, Stage1Air *executable...@@ -4701,7 +4701,7 @@ static LLVMValueRef ir_render_struct_field_ptr(CodeGen *g, Stage1Air *executable
4701}4701}
47024702
4703static LLVMValueRef ir_render_union_field_ptr(CodeGen *g, Stage1Air *executable,4703static LLVMValueRef ir_render_union_field_ptr(CodeGen *g, Stage1Air *executable,
4704 IrInstGenUnionFieldPtr *instruction)4704 Stage1AirInstUnionFieldPtr *instruction)
4705{4705{
4706 if (instruction->base.value->special != ConstValSpecialRuntime)4706 if (instruction->base.value->special != ConstValSpecialRuntime)
4707 return nullptr;4707 return nullptr;
...@@ -4800,7 +4800,7 @@ static size_t find_asm_index(CodeGen *g, AstNode *node, AsmToken *tok, Buf *src_...@@ -4800,7 +4800,7 @@ static size_t find_asm_index(CodeGen *g, AstNode *node, AsmToken *tok, Buf *src_
4800 return SIZE_MAX;4800 return SIZE_MAX;
4801}4801}
48024802
4803static LLVMValueRef ir_render_asm_gen(CodeGen *g, Stage1Air *executable, IrInstGenAsm *instruction) {4803static LLVMValueRef ir_render_asm_gen(CodeGen *g, Stage1Air *executable, Stage1AirInstAsm *instruction) {
4804 AstNode *asm_node = instruction->base.source_node;4804 AstNode *asm_node = instruction->base.source_node;
4805 assert(asm_node->type == NodeTypeAsmExpr);4805 assert(asm_node->type == NodeTypeAsmExpr);
4806 AstNodeAsmExpr *asm_expr = &asm_node->data.asm_expr;4806 AstNodeAsmExpr *asm_expr = &asm_node->data.asm_expr;
...@@ -4885,7 +4885,7 @@ static LLVMValueRef ir_render_asm_gen(CodeGen *g, Stage1Air *executable, IrInstG...@@ -4885,7 +4885,7 @@ static LLVMValueRef ir_render_asm_gen(CodeGen *g, Stage1Air *executable, IrInstG
4885 for (size_t i = 0; i < asm_expr->input_list.length; i += 1, total_index += 1, param_index += 1) {4885 for (size_t i = 0; i < asm_expr->input_list.length; i += 1, total_index += 1, param_index += 1) {
4886 AsmInput *asm_input = asm_expr->input_list.at(i);4886 AsmInput *asm_input = asm_expr->input_list.at(i);
4887 buf_replace(asm_input->constraint, ',', '|');4887 buf_replace(asm_input->constraint, ',', '|');
4888 IrInstGen *ir_input = instruction->input_list[i];4888 Stage1AirInst *ir_input = instruction->input_list[i];
4889 buf_append_buf(&constraint_buf, asm_input->constraint);4889 buf_append_buf(&constraint_buf, asm_input->constraint);
4890 if (total_index + 1 < total_constraint_count) {4890 if (total_index + 1 < total_constraint_count) {
4891 buf_append_char(&constraint_buf, ',');4891 buf_append_char(&constraint_buf, ',');
...@@ -4978,13 +4978,13 @@ static LLVMValueRef gen_non_null_bit(CodeGen *g, ZigType *maybe_type, LLVMValueR...@@ -4978,13 +4978,13 @@ static LLVMValueRef gen_non_null_bit(CodeGen *g, ZigType *maybe_type, LLVMValueR
4978}4978}
49794979
4980static LLVMValueRef ir_render_test_non_null(CodeGen *g, Stage1Air *executable,4980static LLVMValueRef ir_render_test_non_null(CodeGen *g, Stage1Air *executable,
4981 IrInstGenTestNonNull *instruction)4981 Stage1AirInstTestNonNull *instruction)
4982{4982{
4983 return gen_non_null_bit(g, instruction->value->value->type, ir_llvm_value(g, instruction->value));4983 return gen_non_null_bit(g, instruction->value->value->type, ir_llvm_value(g, instruction->value));
4984}4984}
49854985
4986static LLVMValueRef ir_render_optional_unwrap_ptr(CodeGen *g, Stage1Air *executable,4986static LLVMValueRef ir_render_optional_unwrap_ptr(CodeGen *g, Stage1Air *executable,
4987 IrInstGenOptionalUnwrapPtr *instruction)4987 Stage1AirInstOptionalUnwrapPtr *instruction)
4988{4988{
4989 if (instruction->base.value->special != ConstValSpecialRuntime)4989 if (instruction->base.value->special != ConstValSpecialRuntime)
4990 return nullptr;4990 return nullptr;
...@@ -5090,7 +5090,7 @@ static LLVMValueRef get_int_builtin_fn(CodeGen *g, ZigType *expr_type, BuiltinFn...@@ -5090,7 +5090,7 @@ static LLVMValueRef get_int_builtin_fn(CodeGen *g, ZigType *expr_type, BuiltinFn
5090 return fn_val;5090 return fn_val;
5091}5091}
50925092
5093static LLVMValueRef ir_render_clz(CodeGen *g, Stage1Air *executable, IrInstGenClz *instruction) {5093static LLVMValueRef ir_render_clz(CodeGen *g, Stage1Air *executable, Stage1AirInstClz *instruction) {
5094 ZigType *int_type = instruction->op->value->type;5094 ZigType *int_type = instruction->op->value->type;
5095 LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdClz);5095 LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdClz);
5096 LLVMValueRef operand = ir_llvm_value(g, instruction->op);5096 LLVMValueRef operand = ir_llvm_value(g, instruction->op);
...@@ -5102,7 +5102,7 @@ static LLVMValueRef ir_render_clz(CodeGen *g, Stage1Air *executable, IrInstGenCl...@@ -5102,7 +5102,7 @@ static LLVMValueRef ir_render_clz(CodeGen *g, Stage1Air *executable, IrInstGenCl
5102 return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int);5102 return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int);
5103}5103}
51045104
5105static LLVMValueRef ir_render_ctz(CodeGen *g, Stage1Air *executable, IrInstGenCtz *instruction) {5105static LLVMValueRef ir_render_ctz(CodeGen *g, Stage1Air *executable, Stage1AirInstCtz *instruction) {
5106 ZigType *int_type = instruction->op->value->type;5106 ZigType *int_type = instruction->op->value->type;
5107 LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdCtz);5107 LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdCtz);
5108 LLVMValueRef operand = ir_llvm_value(g, instruction->op);5108 LLVMValueRef operand = ir_llvm_value(g, instruction->op);
...@@ -5114,7 +5114,7 @@ static LLVMValueRef ir_render_ctz(CodeGen *g, Stage1Air *executable, IrInstGenCt...@@ -5114,7 +5114,7 @@ static LLVMValueRef ir_render_ctz(CodeGen *g, Stage1Air *executable, IrInstGenCt
5114 return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int);5114 return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int);
5115}5115}
51165116
5117static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable, IrInstGenShuffleVector *instruction) {5117static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable, Stage1AirInstShuffleVector *instruction) {
5118 uint64_t len_a = instruction->a->value->type->data.vector.len;5118 uint64_t len_a = instruction->a->value->type->data.vector.len;
5119 uint64_t len_mask = instruction->mask->value->type->data.vector.len;5119 uint64_t len_mask = instruction->mask->value->type->data.vector.len;
51205120
...@@ -5123,7 +5123,7 @@ static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable,...@@ -5123,7 +5123,7 @@ static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable,
5123 // when changing code, so Zig uses negative numbers to index the5123 // when changing code, so Zig uses negative numbers to index the
5124 // second vector. These start at -1 and go down, and are easiest to use5124 // second vector. These start at -1 and go down, and are easiest to use
5125 // with the ~ operator. Here we convert between the two formats.5125 // with the ~ operator. Here we convert between the two formats.
5126 IrInstGen *mask = instruction->mask;5126 Stage1AirInst *mask = instruction->mask;
5127 LLVMValueRef *values = heap::c_allocator.allocate<LLVMValueRef>(len_mask);5127 LLVMValueRef *values = heap::c_allocator.allocate<LLVMValueRef>(len_mask);
5128 for (uint64_t i = 0; i < len_mask; i++) {5128 for (uint64_t i = 0; i < len_mask; i++) {
5129 if (mask->value->data.x_array.data.s_none.elements[i].special == ConstValSpecialUndef) {5129 if (mask->value->data.x_array.data.s_none.elements[i].special == ConstValSpecialUndef) {
...@@ -5144,7 +5144,7 @@ static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable,...@@ -5144,7 +5144,7 @@ static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable,
5144 llvm_mask_value, "");5144 llvm_mask_value, "");
5145}5145}
51465146
5147static LLVMValueRef ir_render_splat(CodeGen *g, Stage1Air *executable, IrInstGenSplat *instruction) {5147static LLVMValueRef ir_render_splat(CodeGen *g, Stage1Air *executable, Stage1AirInstSplat *instruction) {
5148 ZigType *result_type = instruction->base.value->type;5148 ZigType *result_type = instruction->base.value->type;
5149 ir_assert(result_type->id == ZigTypeIdVector, &instruction->base);5149 ir_assert(result_type->id == ZigTypeIdVector, &instruction->base);
5150 uint32_t len = result_type->data.vector.len;5150 uint32_t len = result_type->data.vector.len;
...@@ -5156,7 +5156,7 @@ static LLVMValueRef ir_render_splat(CodeGen *g, Stage1Air *executable, IrInstGen...@@ -5156,7 +5156,7 @@ static LLVMValueRef ir_render_splat(CodeGen *g, Stage1Air *executable, IrInstGen
5156 return LLVMBuildShuffleVector(g->builder, op_vector, undef_vector, LLVMConstNull(mask_llvm_type), "");5156 return LLVMBuildShuffleVector(g->builder, op_vector, undef_vector, LLVMConstNull(mask_llvm_type), "");
5157}5157}
51585158
5159static LLVMValueRef ir_render_pop_count(CodeGen *g, Stage1Air *executable, IrInstGenPopCount *instruction) {5159static LLVMValueRef ir_render_pop_count(CodeGen *g, Stage1Air *executable, Stage1AirInstPopCount *instruction) {
5160 ZigType *int_type = instruction->op->value->type;5160 ZigType *int_type = instruction->op->value->type;
5161 LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdPopCount);5161 LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdPopCount);
5162 LLVMValueRef operand = ir_llvm_value(g, instruction->op);5162 LLVMValueRef operand = ir_llvm_value(g, instruction->op);
...@@ -5164,7 +5164,7 @@ static LLVMValueRef ir_render_pop_count(CodeGen *g, Stage1Air *executable, IrIns...@@ -5164,7 +5164,7 @@ static LLVMValueRef ir_render_pop_count(CodeGen *g, Stage1Air *executable, IrIns
5164 return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int);5164 return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int);
5165}5165}
51665166
5167static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, IrInstGenSwitchBr *instruction) {5167static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, Stage1AirInstSwitchBr *instruction) {
5168 ZigType *target_type = instruction->target_value->value->type;5168 ZigType *target_type = instruction->target_value->value->type;
5169 LLVMBasicBlockRef else_block = instruction->else_block->llvm_block;5169 LLVMBasicBlockRef else_block = instruction->else_block->llvm_block;
51705170
...@@ -5178,7 +5178,7 @@ static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, IrIns...@@ -5178,7 +5178,7 @@ static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, IrIns
5178 (unsigned)instruction->case_count);5178 (unsigned)instruction->case_count);
51795179
5180 for (size_t i = 0; i < instruction->case_count; i += 1) {5180 for (size_t i = 0; i < instruction->case_count; i += 1) {
5181 IrInstGenSwitchBrCase *this_case = &instruction->cases[i];5181 Stage1AirInstSwitchBrCase *this_case = &instruction->cases[i];
51825182
5183 LLVMValueRef case_value = ir_llvm_value(g, this_case->value);5183 LLVMValueRef case_value = ir_llvm_value(g, this_case->value);
5184 if (target_type->id == ZigTypeIdPointer) {5184 if (target_type->id == ZigTypeIdPointer) {
...@@ -5192,7 +5192,7 @@ static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, IrIns...@@ -5192,7 +5192,7 @@ static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, IrIns
5192 return nullptr;5192 return nullptr;
5193}5193}
51945194
5195static LLVMValueRef ir_render_phi(CodeGen *g, Stage1Air *executable, IrInstGenPhi *instruction) {5195static LLVMValueRef ir_render_phi(CodeGen *g, Stage1Air *executable, Stage1AirInstPhi *instruction) {
5196 if (!type_has_bits(g, instruction->base.value->type))5196 if (!type_has_bits(g, instruction->base.value->type))
5197 return nullptr;5197 return nullptr;
51985198
...@@ -5216,12 +5216,12 @@ static LLVMValueRef ir_render_phi(CodeGen *g, Stage1Air *executable, IrInstGenPh...@@ -5216,12 +5216,12 @@ static LLVMValueRef ir_render_phi(CodeGen *g, Stage1Air *executable, IrInstGenPh
5216 return phi;5216 return phi;
5217}5217}
52185218
5219static LLVMValueRef ir_render_ref(CodeGen *g, Stage1Air *executable, IrInstGenRef *instruction) {5219static LLVMValueRef ir_render_ref(CodeGen *g, Stage1Air *executable, Stage1AirInstRef *instruction) {
5220 if (!type_has_bits(g, instruction->base.value->type)) {5220 if (!type_has_bits(g, instruction->base.value->type)) {
5221 return nullptr;5221 return nullptr;
5222 }5222 }
5223 if (instruction->operand->id == IrInstGenIdCall) {5223 if (instruction->operand->id == Stage1AirInstIdCall) {
5224 IrInstGenCall *call = reinterpret_cast<IrInstGenCall *>(instruction->operand);5224 Stage1AirInstCall *call = reinterpret_cast<Stage1AirInstCall *>(instruction->operand);
5225 if (call->result_loc != nullptr) {5225 if (call->result_loc != nullptr) {
5226 return ir_llvm_value(g, call->result_loc);5226 return ir_llvm_value(g, call->result_loc);
5227 }5227 }
...@@ -5236,7 +5236,7 @@ static LLVMValueRef ir_render_ref(CodeGen *g, Stage1Air *executable, IrInstGenRe...@@ -5236,7 +5236,7 @@ static LLVMValueRef ir_render_ref(CodeGen *g, Stage1Air *executable, IrInstGenRe
5236 }5236 }
5237}5237}
52385238
5239static LLVMValueRef ir_render_err_name(CodeGen *g, Stage1Air *executable, IrInstGenErrName *instruction) {5239static LLVMValueRef ir_render_err_name(CodeGen *g, Stage1Air *executable, Stage1AirInstErrName *instruction) {
5240 assert(g->generate_error_name_table);5240 assert(g->generate_error_name_table);
5241 assert(g->errors_by_index.length > 0);5241 assert(g->errors_by_index.length > 0);
52425242
...@@ -5363,7 +5363,7 @@ static LLVMValueRef get_enum_tag_name_function(CodeGen *g, ZigType *enum_type) {...@@ -5363,7 +5363,7 @@ static LLVMValueRef get_enum_tag_name_function(CodeGen *g, ZigType *enum_type) {
5363}5363}
53645364
5365static LLVMValueRef ir_render_enum_tag_name(CodeGen *g, Stage1Air *executable,5365static LLVMValueRef ir_render_enum_tag_name(CodeGen *g, Stage1Air *executable,
5366 IrInstGenTagName *instruction)5366 Stage1AirInstTagName *instruction)
5367{5367{
5368 ZigType *enum_type = instruction->target->value->type;5368 ZigType *enum_type = instruction->target->value->type;
5369 assert(enum_type->id == ZigTypeIdEnum);5369 assert(enum_type->id == ZigTypeIdEnum);
...@@ -5376,7 +5376,7 @@ static LLVMValueRef ir_render_enum_tag_name(CodeGen *g, Stage1Air *executable,...@@ -5376,7 +5376,7 @@ static LLVMValueRef ir_render_enum_tag_name(CodeGen *g, Stage1Air *executable,
5376}5376}
53775377
5378static LLVMValueRef ir_render_field_parent_ptr(CodeGen *g, Stage1Air *executable,5378static LLVMValueRef ir_render_field_parent_ptr(CodeGen *g, Stage1Air *executable,
5379 IrInstGenFieldParentPtr *instruction)5379 Stage1AirInstFieldParentPtr *instruction)
5380{5380{
5381 ZigType *container_ptr_type = instruction->base.value->type;5381 ZigType *container_ptr_type = instruction->base.value->type;
5382 assert(container_ptr_type->id == ZigTypeIdPointer);5382 assert(container_ptr_type->id == ZigTypeIdPointer);
...@@ -5402,7 +5402,7 @@ static LLVMValueRef ir_render_field_parent_ptr(CodeGen *g, Stage1Air *executable...@@ -5402,7 +5402,7 @@ static LLVMValueRef ir_render_field_parent_ptr(CodeGen *g, Stage1Air *executable
5402 }5402 }
5403}5403}
54045404
5405static LLVMValueRef ir_render_align_cast(CodeGen *g, Stage1Air *executable, IrInstGenAlignCast *instruction) {5405static LLVMValueRef ir_render_align_cast(CodeGen *g, Stage1Air *executable, Stage1AirInstAlignCast *instruction) {
5406 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);5406 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);
5407 assert(target_val);5407 assert(target_val);
54085408
...@@ -5466,7 +5466,7 @@ static LLVMValueRef ir_render_align_cast(CodeGen *g, Stage1Air *executable, IrIn...@@ -5466,7 +5466,7 @@ static LLVMValueRef ir_render_align_cast(CodeGen *g, Stage1Air *executable, IrIn
5466}5466}
54675467
5468static LLVMValueRef ir_render_error_return_trace(CodeGen *g, Stage1Air *executable,5468static LLVMValueRef ir_render_error_return_trace(CodeGen *g, Stage1Air *executable,
5469 IrInstGenErrorReturnTrace *instruction)5469 Stage1AirInstErrorReturnTrace *instruction)
5470{5470{
5471 bool is_llvm_alloca;5471 bool is_llvm_alloca;
5472 LLVMValueRef cur_err_ret_trace_val = get_cur_err_ret_trace_val(g, instruction->base.scope, &is_llvm_alloca);5472 LLVMValueRef cur_err_ret_trace_val = get_cur_err_ret_trace_val(g, instruction->base.scope, &is_llvm_alloca);
...@@ -5507,7 +5507,7 @@ static enum ZigLLVM_AtomicRMWBinOp to_ZigLLVMAtomicRMWBinOp(AtomicRmwOp op, bool...@@ -5507,7 +5507,7 @@ static enum ZigLLVM_AtomicRMWBinOp to_ZigLLVMAtomicRMWBinOp(AtomicRmwOp op, bool
5507 zig_unreachable();5507 zig_unreachable();
5508}5508}
55095509
5510static LLVMTypeRef get_atomic_abi_type(CodeGen *g, IrInstGen *instruction, bool RMWXchg) {5510static LLVMTypeRef get_atomic_abi_type(CodeGen *g, Stage1AirInst *instruction, bool RMWXchg) {
5511 // If the operand type of an atomic operation is not byte sized we need to5511 // If the operand type of an atomic operation is not byte sized we need to
5512 // widen it before using it and then truncate the result.5512 // widen it before using it and then truncate the result.
5513 // RMW exchange of floating-point values is bitcasted to same-sized integer5513 // RMW exchange of floating-point values is bitcasted to same-sized integer
...@@ -5538,7 +5538,7 @@ static LLVMTypeRef get_atomic_abi_type(CodeGen *g, IrInstGen *instruction, bool...@@ -5538,7 +5538,7 @@ static LLVMTypeRef get_atomic_abi_type(CodeGen *g, IrInstGen *instruction, bool
5538 }5538 }
5539}5539}
55405540
5541static LLVMValueRef ir_render_cmpxchg(CodeGen *g, Stage1Air *executable, IrInstGenCmpxchg *instruction) {5541static LLVMValueRef ir_render_cmpxchg(CodeGen *g, Stage1Air *executable, Stage1AirInstCmpxchg *instruction) {
5542 LLVMValueRef ptr_val = ir_llvm_value(g, instruction->ptr);5542 LLVMValueRef ptr_val = ir_llvm_value(g, instruction->ptr);
5543 LLVMValueRef cmp_val = ir_llvm_value(g, instruction->cmp_value);5543 LLVMValueRef cmp_val = ir_llvm_value(g, instruction->cmp_value);
5544 LLVMValueRef new_val = ir_llvm_value(g, instruction->new_value);5544 LLVMValueRef new_val = ir_llvm_value(g, instruction->new_value);
...@@ -5600,7 +5600,7 @@ static LLVMValueRef ir_render_cmpxchg(CodeGen *g, Stage1Air *executable, IrInstG...@@ -5600,7 +5600,7 @@ static LLVMValueRef ir_render_cmpxchg(CodeGen *g, Stage1Air *executable, IrInstG
5600 return result_loc;5600 return result_loc;
5601}5601}
56025602
5603static LLVMValueRef ir_render_reduce(CodeGen *g, Stage1Air *executable, IrInstGenReduce *instruction) {5603static LLVMValueRef ir_render_reduce(CodeGen *g, Stage1Air *executable, Stage1AirInstReduce *instruction) {
5604 LLVMValueRef value = ir_llvm_value(g, instruction->value);5604 LLVMValueRef value = ir_llvm_value(g, instruction->value);
56055605
5606 ZigType *value_type = instruction->value->value->type;5606 ZigType *value_type = instruction->value->value->type;
...@@ -5664,13 +5664,13 @@ static LLVMValueRef ir_render_reduce(CodeGen *g, Stage1Air *executable, IrInstGe...@@ -5664,13 +5664,13 @@ static LLVMValueRef ir_render_reduce(CodeGen *g, Stage1Air *executable, IrInstGe
5664 return result_val;5664 return result_val;
5665}5665}
56665666
5667static LLVMValueRef ir_render_fence(CodeGen *g, Stage1Air *executable, IrInstGenFence *instruction) {5667static LLVMValueRef ir_render_fence(CodeGen *g, Stage1Air *executable, Stage1AirInstFence *instruction) {
5668 LLVMAtomicOrdering atomic_order = to_LLVMAtomicOrdering(instruction->order);5668 LLVMAtomicOrdering atomic_order = to_LLVMAtomicOrdering(instruction->order);
5669 LLVMBuildFence(g->builder, atomic_order, false, "");5669 LLVMBuildFence(g->builder, atomic_order, false, "");
5670 return nullptr;5670 return nullptr;
5671}5671}
56725672
5673static LLVMValueRef ir_render_truncate(CodeGen *g, Stage1Air *executable, IrInstGenTruncate *instruction) {5673static LLVMValueRef ir_render_truncate(CodeGen *g, Stage1Air *executable, Stage1AirInstTruncate *instruction) {
5674 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);5674 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);
5675 ZigType *dest_type = instruction->base.value->type;5675 ZigType *dest_type = instruction->base.value->type;
5676 ZigType *src_type = instruction->target->value->type;5676 ZigType *src_type = instruction->target->value->type;
...@@ -5685,7 +5685,7 @@ static LLVMValueRef ir_render_truncate(CodeGen *g, Stage1Air *executable, IrInst...@@ -5685,7 +5685,7 @@ static LLVMValueRef ir_render_truncate(CodeGen *g, Stage1Air *executable, IrInst
5685 }5685 }
5686}5686}
56875687
5688static LLVMValueRef ir_render_memset(CodeGen *g, Stage1Air *executable, IrInstGenMemset *instruction) {5688static LLVMValueRef ir_render_memset(CodeGen *g, Stage1Air *executable, Stage1AirInstMemset *instruction) {
5689 LLVMValueRef dest_ptr = ir_llvm_value(g, instruction->dest_ptr);5689 LLVMValueRef dest_ptr = ir_llvm_value(g, instruction->dest_ptr);
5690 LLVMValueRef len_val = ir_llvm_value(g, instruction->count);5690 LLVMValueRef len_val = ir_llvm_value(g, instruction->count);
56915691
...@@ -5715,7 +5715,7 @@ static LLVMValueRef ir_render_memset(CodeGen *g, Stage1Air *executable, IrInstGe...@@ -5715,7 +5715,7 @@ static LLVMValueRef ir_render_memset(CodeGen *g, Stage1Air *executable, IrInstGe
5715 return nullptr;5715 return nullptr;
5716}5716}
57175717
5718static LLVMValueRef ir_render_memcpy(CodeGen *g, Stage1Air *executable, IrInstGenMemcpy *instruction) {5718static LLVMValueRef ir_render_memcpy(CodeGen *g, Stage1Air *executable, Stage1AirInstMemcpy *instruction) {
5719 LLVMValueRef dest_ptr = ir_llvm_value(g, instruction->dest_ptr);5719 LLVMValueRef dest_ptr = ir_llvm_value(g, instruction->dest_ptr);
5720 LLVMValueRef src_ptr = ir_llvm_value(g, instruction->src_ptr);5720 LLVMValueRef src_ptr = ir_llvm_value(g, instruction->src_ptr);
5721 LLVMValueRef len_val = ir_llvm_value(g, instruction->count);5721 LLVMValueRef len_val = ir_llvm_value(g, instruction->count);
...@@ -5737,14 +5737,14 @@ static LLVMValueRef ir_render_memcpy(CodeGen *g, Stage1Air *executable, IrInstGe...@@ -5737,14 +5737,14 @@ static LLVMValueRef ir_render_memcpy(CodeGen *g, Stage1Air *executable, IrInstGe
5737 return nullptr;5737 return nullptr;
5738}5738}
57395739
5740static LLVMValueRef ir_render_wasm_memory_size(CodeGen *g, Stage1Air *executable, IrInstGenWasmMemorySize *instruction) {5740static LLVMValueRef ir_render_wasm_memory_size(CodeGen *g, Stage1Air *executable, Stage1AirInstWasmMemorySize *instruction) {
5741 // TODO adjust for wasm645741 // TODO adjust for wasm64
5742 LLVMValueRef param = ir_llvm_value(g, instruction->index);5742 LLVMValueRef param = ir_llvm_value(g, instruction->index);
5743 LLVMValueRef val = LLVMBuildCall(g->builder, gen_wasm_memory_size(g), &param, 1, "");5743 LLVMValueRef val = LLVMBuildCall(g->builder, gen_wasm_memory_size(g), &param, 1, "");
5744 return val;5744 return val;
5745}5745}
57465746
5747static LLVMValueRef ir_render_wasm_memory_grow(CodeGen *g, Stage1Air *executable, IrInstGenWasmMemoryGrow *instruction) {5747static LLVMValueRef ir_render_wasm_memory_grow(CodeGen *g, Stage1Air *executable, Stage1AirInstWasmMemoryGrow *instruction) {
5748 // TODO adjust for wasm645748 // TODO adjust for wasm64
5749 LLVMValueRef params[] = {5749 LLVMValueRef params[] = {
5750 ir_llvm_value(g, instruction->index),5750 ir_llvm_value(g, instruction->index),
...@@ -5754,7 +5754,7 @@ static LLVMValueRef ir_render_wasm_memory_grow(CodeGen *g, Stage1Air *executable...@@ -5754,7 +5754,7 @@ static LLVMValueRef ir_render_wasm_memory_grow(CodeGen *g, Stage1Air *executable
5754 return val;5754 return val;
5755}5755}
57565756
5757static LLVMValueRef ir_render_slice(CodeGen *g, Stage1Air *executable, IrInstGenSlice *instruction) {5757static LLVMValueRef ir_render_slice(CodeGen *g, Stage1Air *executable, Stage1AirInstSlice *instruction) {
5758 Error err;5758 Error err;
57595759
5760 LLVMValueRef array_ptr_ptr = ir_llvm_value(g, instruction->ptr);5760 LLVMValueRef array_ptr_ptr = ir_llvm_value(g, instruction->ptr);
...@@ -5991,13 +5991,13 @@ static LLVMValueRef get_trap_fn_val(CodeGen *g) {...@@ -5991,13 +5991,13 @@ static LLVMValueRef get_trap_fn_val(CodeGen *g) {
5991}5991}
59925992
59935993
5994static LLVMValueRef ir_render_breakpoint(CodeGen *g, Stage1Air *executable, IrInstGenBreakpoint *instruction) {5994static LLVMValueRef ir_render_breakpoint(CodeGen *g, Stage1Air *executable, Stage1AirInstBreakpoint *instruction) {
5995 LLVMBuildCall(g->builder, get_trap_fn_val(g), nullptr, 0, "");5995 LLVMBuildCall(g->builder, get_trap_fn_val(g), nullptr, 0, "");
5996 return nullptr;5996 return nullptr;
5997}5997}
59985998
5999static LLVMValueRef ir_render_return_address(CodeGen *g, Stage1Air *executable,5999static LLVMValueRef ir_render_return_address(CodeGen *g, Stage1Air *executable,
6000 IrInstGenReturnAddress *instruction)6000 Stage1AirInstReturnAddress *instruction)
6001{6001{
6002 if (target_is_wasm(g->zig_target) && g->zig_target->os != OsEmscripten) {6002 if (target_is_wasm(g->zig_target) && g->zig_target->os != OsEmscripten) {
6003 // I got this error from LLVM 10:6003 // I got this error from LLVM 10:
...@@ -6025,18 +6025,18 @@ static LLVMValueRef get_frame_address_fn_val(CodeGen *g) {...@@ -6025,18 +6025,18 @@ static LLVMValueRef get_frame_address_fn_val(CodeGen *g) {
6025}6025}
60266026
6027static LLVMValueRef ir_render_frame_address(CodeGen *g, Stage1Air *executable,6027static LLVMValueRef ir_render_frame_address(CodeGen *g, Stage1Air *executable,
6028 IrInstGenFrameAddress *instruction)6028 Stage1AirInstFrameAddress *instruction)
6029{6029{
6030 LLVMValueRef zero = LLVMConstNull(g->builtin_types.entry_i32->llvm_type);6030 LLVMValueRef zero = LLVMConstNull(g->builtin_types.entry_i32->llvm_type);
6031 LLVMValueRef ptr_val = LLVMBuildCall(g->builder, get_frame_address_fn_val(g), &zero, 1, "");6031 LLVMValueRef ptr_val = LLVMBuildCall(g->builder, get_frame_address_fn_val(g), &zero, 1, "");
6032 return LLVMBuildPtrToInt(g->builder, ptr_val, g->builtin_types.entry_usize->llvm_type, "");6032 return LLVMBuildPtrToInt(g->builder, ptr_val, g->builtin_types.entry_usize->llvm_type, "");
6033}6033}
60346034
6035static LLVMValueRef ir_render_handle(CodeGen *g, Stage1Air *executable, IrInstGenFrameHandle *instruction) {6035static LLVMValueRef ir_render_handle(CodeGen *g, Stage1Air *executable, Stage1AirInstFrameHandle *instruction) {
6036 return g->cur_frame_ptr;6036 return g->cur_frame_ptr;
6037}6037}
60386038
6039static LLVMValueRef render_shl_with_overflow(CodeGen *g, IrInstGenOverflowOp *instruction) {6039static LLVMValueRef render_shl_with_overflow(CodeGen *g, Stage1AirInstOverflowOp *instruction) {
6040 ZigType *int_type = instruction->result_ptr_type;6040 ZigType *int_type = instruction->result_ptr_type;
6041 assert(int_type->id == ZigTypeIdInt);6041 assert(int_type->id == ZigTypeIdInt);
60426042
...@@ -6061,7 +6061,7 @@ static LLVMValueRef render_shl_with_overflow(CodeGen *g, IrInstGenOverflowOp *in...@@ -6061,7 +6061,7 @@ static LLVMValueRef render_shl_with_overflow(CodeGen *g, IrInstGenOverflowOp *in
6061 return overflow_bit;6061 return overflow_bit;
6062}6062}
60636063
6064static LLVMValueRef ir_render_overflow_op(CodeGen *g, Stage1Air *executable, IrInstGenOverflowOp *instruction) {6064static LLVMValueRef ir_render_overflow_op(CodeGen *g, Stage1Air *executable, Stage1AirInstOverflowOp *instruction) {
6065 AddSubMul add_sub_mul;6065 AddSubMul add_sub_mul;
6066 switch (instruction->op) {6066 switch (instruction->op) {
6067 case IrOverflowOpAdd:6067 case IrOverflowOpAdd:
...@@ -6099,7 +6099,7 @@ static LLVMValueRef ir_render_overflow_op(CodeGen *g, Stage1Air *executable, IrI...@@ -6099,7 +6099,7 @@ static LLVMValueRef ir_render_overflow_op(CodeGen *g, Stage1Air *executable, IrI
6099 return overflow_bit;6099 return overflow_bit;
6100}6100}
61016101
6102static LLVMValueRef ir_render_test_err(CodeGen *g, Stage1Air *executable, IrInstGenTestErr *instruction) {6102static LLVMValueRef ir_render_test_err(CodeGen *g, Stage1Air *executable, Stage1AirInstTestErr *instruction) {
6103 ZigType *err_union_type = instruction->err_union->value->type;6103 ZigType *err_union_type = instruction->err_union->value->type;
6104 ZigType *payload_type = err_union_type->data.error_union.payload_type;6104 ZigType *payload_type = err_union_type->data.error_union.payload_type;
6105 LLVMValueRef err_union_handle = ir_llvm_value(g, instruction->err_union);6105 LLVMValueRef err_union_handle = ir_llvm_value(g, instruction->err_union);
...@@ -6117,7 +6117,7 @@ static LLVMValueRef ir_render_test_err(CodeGen *g, Stage1Air *executable, IrInst...@@ -6117,7 +6117,7 @@ static LLVMValueRef ir_render_test_err(CodeGen *g, Stage1Air *executable, IrInst
6117}6117}
61186118
6119static LLVMValueRef ir_render_unwrap_err_code(CodeGen *g, Stage1Air *executable,6119static LLVMValueRef ir_render_unwrap_err_code(CodeGen *g, Stage1Air *executable,
6120 IrInstGenUnwrapErrCode *instruction)6120 Stage1AirInstUnwrapErrCode *instruction)
6121{6121{
6122 if (instruction->base.value->special != ConstValSpecialRuntime)6122 if (instruction->base.value->special != ConstValSpecialRuntime)
6123 return nullptr;6123 return nullptr;
...@@ -6137,7 +6137,7 @@ static LLVMValueRef ir_render_unwrap_err_code(CodeGen *g, Stage1Air *executable,...@@ -6137,7 +6137,7 @@ static LLVMValueRef ir_render_unwrap_err_code(CodeGen *g, Stage1Air *executable,
6137}6137}
61386138
6139static LLVMValueRef ir_render_unwrap_err_payload(CodeGen *g, Stage1Air *executable,6139static LLVMValueRef ir_render_unwrap_err_payload(CodeGen *g, Stage1Air *executable,
6140 IrInstGenUnwrapErrPayload *instruction)6140 Stage1AirInstUnwrapErrPayload *instruction)
6141{6141{
6142 Error err;6142 Error err;
61436143
...@@ -6205,7 +6205,7 @@ static LLVMValueRef ir_render_unwrap_err_payload(CodeGen *g, Stage1Air *executab...@@ -6205,7 +6205,7 @@ static LLVMValueRef ir_render_unwrap_err_payload(CodeGen *g, Stage1Air *executab
6205 }6205 }
6206}6206}
62076207
6208static LLVMValueRef ir_render_optional_wrap(CodeGen *g, Stage1Air *executable, IrInstGenOptionalWrap *instruction) {6208static LLVMValueRef ir_render_optional_wrap(CodeGen *g, Stage1Air *executable, Stage1AirInstOptionalWrap *instruction) {
6209 ZigType *wanted_type = instruction->base.value->type;6209 ZigType *wanted_type = instruction->base.value->type;
62106210
6211 assert(wanted_type->id == ZigTypeIdOptional);6211 assert(wanted_type->id == ZigTypeIdOptional);
...@@ -6241,7 +6241,7 @@ static LLVMValueRef ir_render_optional_wrap(CodeGen *g, Stage1Air *executable, I...@@ -6241,7 +6241,7 @@ static LLVMValueRef ir_render_optional_wrap(CodeGen *g, Stage1Air *executable, I
6241 return result_loc;6241 return result_loc;
6242}6242}
62436243
6244static LLVMValueRef ir_render_err_wrap_code(CodeGen *g, Stage1Air *executable, IrInstGenErrWrapCode *instruction) {6244static LLVMValueRef ir_render_err_wrap_code(CodeGen *g, Stage1Air *executable, Stage1AirInstErrWrapCode *instruction) {
6245 ZigType *wanted_type = instruction->base.value->type;6245 ZigType *wanted_type = instruction->base.value->type;
62466246
6247 assert(wanted_type->id == ZigTypeIdErrorUnion);6247 assert(wanted_type->id == ZigTypeIdErrorUnion);
...@@ -6261,7 +6261,7 @@ static LLVMValueRef ir_render_err_wrap_code(CodeGen *g, Stage1Air *executable, I...@@ -6261,7 +6261,7 @@ static LLVMValueRef ir_render_err_wrap_code(CodeGen *g, Stage1Air *executable, I
6261 return result_loc;6261 return result_loc;
6262}6262}
62636263
6264static LLVMValueRef ir_render_err_wrap_payload(CodeGen *g, Stage1Air *executable, IrInstGenErrWrapPayload *instruction) {6264static LLVMValueRef ir_render_err_wrap_payload(CodeGen *g, Stage1Air *executable, Stage1AirInstErrWrapPayload *instruction) {
6265 ZigType *wanted_type = instruction->base.value->type;6265 ZigType *wanted_type = instruction->base.value->type;
62666266
6267 assert(wanted_type->id == ZigTypeIdErrorUnion);6267 assert(wanted_type->id == ZigTypeIdErrorUnion);
...@@ -6292,7 +6292,7 @@ static LLVMValueRef ir_render_err_wrap_payload(CodeGen *g, Stage1Air *executable...@@ -6292,7 +6292,7 @@ static LLVMValueRef ir_render_err_wrap_payload(CodeGen *g, Stage1Air *executable
6292 return result_loc;6292 return result_loc;
6293}6293}
62946294
6295static LLVMValueRef ir_render_union_tag(CodeGen *g, Stage1Air *executable, IrInstGenUnionTag *instruction) {6295static LLVMValueRef ir_render_union_tag(CodeGen *g, Stage1Air *executable, Stage1AirInstUnionTag *instruction) {
6296 ZigType *union_type = instruction->value->value->type;6296 ZigType *union_type = instruction->value->value->type;
62976297
6298 ZigType *tag_type = union_type->data.unionation.tag_type;6298 ZigType *tag_type = union_type->data.unionation.tag_type;
...@@ -6310,7 +6310,7 @@ static LLVMValueRef ir_render_union_tag(CodeGen *g, Stage1Air *executable, IrIns...@@ -6310,7 +6310,7 @@ static LLVMValueRef ir_render_union_tag(CodeGen *g, Stage1Air *executable, IrIns
6310 return get_handle_value(g, tag_field_ptr, tag_type, ptr_type);6310 return get_handle_value(g, tag_field_ptr, tag_type, ptr_type);
6311}6311}
63126312
6313static LLVMValueRef ir_render_panic(CodeGen *g, Stage1Air *executable, IrInstGenPanic *instruction) {6313static LLVMValueRef ir_render_panic(CodeGen *g, Stage1Air *executable, Stage1AirInstPanic *instruction) {
6314 bool is_llvm_alloca;6314 bool is_llvm_alloca;
6315 LLVMValueRef err_ret_trace_val = get_cur_err_ret_trace_val(g, instruction->base.scope, &is_llvm_alloca);6315 LLVMValueRef err_ret_trace_val = get_cur_err_ret_trace_val(g, instruction->base.scope, &is_llvm_alloca);
6316 gen_panic(g, ir_llvm_value(g, instruction->msg), err_ret_trace_val, is_llvm_alloca);6316 gen_panic(g, ir_llvm_value(g, instruction->msg), err_ret_trace_val, is_llvm_alloca);
...@@ -6318,7 +6318,7 @@ static LLVMValueRef ir_render_panic(CodeGen *g, Stage1Air *executable, IrInstGen...@@ -6318,7 +6318,7 @@ static LLVMValueRef ir_render_panic(CodeGen *g, Stage1Air *executable, IrInstGen
6318}6318}
63196319
6320static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, Stage1Air *executable,6320static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, Stage1Air *executable,
6321 IrInstGenAtomicRmw *instruction)6321 Stage1AirInstAtomicRmw *instruction)
6322{6322{
6323 bool is_signed;6323 bool is_signed;
6324 ZigType *operand_type = instruction->operand->value->type;6324 ZigType *operand_type = instruction->operand->value->type;
...@@ -6370,7 +6370,7 @@ static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, Stage1Air *executable,...@@ -6370,7 +6370,7 @@ static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, Stage1Air *executable,
6370}6370}
63716371
6372static LLVMValueRef ir_render_atomic_load(CodeGen *g, Stage1Air *executable,6372static LLVMValueRef ir_render_atomic_load(CodeGen *g, Stage1Air *executable,
6373 IrInstGenAtomicLoad *instruction)6373 Stage1AirInstAtomicLoad *instruction)
6374{6374{
6375 LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->ordering);6375 LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->ordering);
6376 LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr);6376 LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr);
...@@ -6391,7 +6391,7 @@ static LLVMValueRef ir_render_atomic_load(CodeGen *g, Stage1Air *executable,...@@ -6391,7 +6391,7 @@ static LLVMValueRef ir_render_atomic_load(CodeGen *g, Stage1Air *executable,
6391}6391}
63926392
6393static LLVMValueRef ir_render_atomic_store(CodeGen *g, Stage1Air *executable,6393static LLVMValueRef ir_render_atomic_store(CodeGen *g, Stage1Air *executable,
6394 IrInstGenAtomicStore *instruction)6394 Stage1AirInstAtomicStore *instruction)
6395{6395{
6396 LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->ordering);6396 LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->ordering);
6397 LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr);6397 LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr);
...@@ -6413,13 +6413,13 @@ static LLVMValueRef ir_render_atomic_store(CodeGen *g, Stage1Air *executable,...@@ -6413,13 +6413,13 @@ static LLVMValueRef ir_render_atomic_store(CodeGen *g, Stage1Air *executable,
6413 return nullptr;6413 return nullptr;
6414}6414}
64156415
6416static LLVMValueRef ir_render_float_op(CodeGen *g, Stage1Air *executable, IrInstGenFloatOp *instruction) {6416static LLVMValueRef ir_render_float_op(CodeGen *g, Stage1Air *executable, Stage1AirInstFloatOp *instruction) {
6417 LLVMValueRef operand = ir_llvm_value(g, instruction->operand);6417 LLVMValueRef operand = ir_llvm_value(g, instruction->operand);
6418 LLVMValueRef fn_val = get_float_fn(g, instruction->base.value->type, ZigLLVMFnIdFloatOp, instruction->fn_id);6418 LLVMValueRef fn_val = get_float_fn(g, instruction->base.value->type, ZigLLVMFnIdFloatOp, instruction->fn_id);
6419 return LLVMBuildCall(g->builder, fn_val, &operand, 1, "");6419 return LLVMBuildCall(g->builder, fn_val, &operand, 1, "");
6420}6420}
64216421
6422static LLVMValueRef ir_render_mul_add(CodeGen *g, Stage1Air *executable, IrInstGenMulAdd *instruction) {6422static LLVMValueRef ir_render_mul_add(CodeGen *g, Stage1Air *executable, Stage1AirInstMulAdd *instruction) {
6423 LLVMValueRef op1 = ir_llvm_value(g, instruction->op1);6423 LLVMValueRef op1 = ir_llvm_value(g, instruction->op1);
6424 LLVMValueRef op2 = ir_llvm_value(g, instruction->op2);6424 LLVMValueRef op2 = ir_llvm_value(g, instruction->op2);
6425 LLVMValueRef op3 = ir_llvm_value(g, instruction->op3);6425 LLVMValueRef op3 = ir_llvm_value(g, instruction->op3);
...@@ -6434,7 +6434,7 @@ static LLVMValueRef ir_render_mul_add(CodeGen *g, Stage1Air *executable, IrInstG...@@ -6434,7 +6434,7 @@ static LLVMValueRef ir_render_mul_add(CodeGen *g, Stage1Air *executable, IrInstG
6434 return LLVMBuildCall(g->builder, fn_val, args, 3, "");6434 return LLVMBuildCall(g->builder, fn_val, args, 3, "");
6435}6435}
64366436
6437static LLVMValueRef ir_render_bswap(CodeGen *g, Stage1Air *executable, IrInstGenBswap *instruction) {6437static LLVMValueRef ir_render_bswap(CodeGen *g, Stage1Air *executable, Stage1AirInstBswap *instruction) {
6438 LLVMValueRef op = ir_llvm_value(g, instruction->op);6438 LLVMValueRef op = ir_llvm_value(g, instruction->op);
6439 ZigType *expr_type = instruction->base.value->type;6439 ZigType *expr_type = instruction->base.value->type;
6440 bool is_vector = expr_type->id == ZigTypeIdVector;6440 bool is_vector = expr_type->id == ZigTypeIdVector;
...@@ -6469,7 +6469,7 @@ static LLVMValueRef ir_render_bswap(CodeGen *g, Stage1Air *executable, IrInstGen...@@ -6469,7 +6469,7 @@ static LLVMValueRef ir_render_bswap(CodeGen *g, Stage1Air *executable, IrInstGen
6469}6469}
64706470
6471static LLVMValueRef ir_render_extern(CodeGen *g, Stage1Air *executable,6471static LLVMValueRef ir_render_extern(CodeGen *g, Stage1Air *executable,
6472 IrInstGenExtern *instruction)6472 Stage1AirInstExtern *instruction)
6473{6473{
6474 ZigType *expr_type = instruction->base.value->type;6474 ZigType *expr_type = instruction->base.value->type;
6475 assert(get_src_ptr_type(expr_type));6475 assert(get_src_ptr_type(expr_type));
...@@ -6492,7 +6492,7 @@ static LLVMValueRef ir_render_extern(CodeGen *g, Stage1Air *executable,...@@ -6492,7 +6492,7 @@ static LLVMValueRef ir_render_extern(CodeGen *g, Stage1Air *executable,
6492 return LLVMBuildBitCast(g->builder, global_value, get_llvm_type(g, expr_type), "");6492 return LLVMBuildBitCast(g->builder, global_value, get_llvm_type(g, expr_type), "");
6493}6493}
64946494
6495static LLVMValueRef ir_render_bit_reverse(CodeGen *g, Stage1Air *executable, IrInstGenBitReverse *instruction) {6495static LLVMValueRef ir_render_bit_reverse(CodeGen *g, Stage1Air *executable, Stage1AirInstBitReverse *instruction) {
6496 LLVMValueRef op = ir_llvm_value(g, instruction->op);6496 LLVMValueRef op = ir_llvm_value(g, instruction->op);
6497 ZigType *int_type = instruction->base.value->type;6497 ZigType *int_type = instruction->base.value->type;
6498 assert(int_type->id == ZigTypeIdInt);6498 assert(int_type->id == ZigTypeIdInt);
...@@ -6501,7 +6501,7 @@ static LLVMValueRef ir_render_bit_reverse(CodeGen *g, Stage1Air *executable, IrI...@@ -6501,7 +6501,7 @@ static LLVMValueRef ir_render_bit_reverse(CodeGen *g, Stage1Air *executable, IrI
6501}6501}
65026502
6503static LLVMValueRef ir_render_vector_to_array(CodeGen *g, Stage1Air *executable,6503static LLVMValueRef ir_render_vector_to_array(CodeGen *g, Stage1Air *executable,
6504 IrInstGenVectorToArray *instruction)6504 Stage1AirInstVectorToArray *instruction)
6505{6505{
6506 ZigType *array_type = instruction->base.value->type;6506 ZigType *array_type = instruction->base.value->type;
6507 assert(array_type->id == ZigTypeIdArray);6507 assert(array_type->id == ZigTypeIdArray);
...@@ -6535,7 +6535,7 @@ static LLVMValueRef ir_render_vector_to_array(CodeGen *g, Stage1Air *executable,...@@ -6535,7 +6535,7 @@ static LLVMValueRef ir_render_vector_to_array(CodeGen *g, Stage1Air *executable,
6535}6535}
65366536
6537static LLVMValueRef ir_render_array_to_vector(CodeGen *g, Stage1Air *executable,6537static LLVMValueRef ir_render_array_to_vector(CodeGen *g, Stage1Air *executable,
6538 IrInstGenArrayToVector *instruction)6538 Stage1AirInstArrayToVector *instruction)
6539{6539{
6540 ZigType *vector_type = instruction->base.value->type;6540 ZigType *vector_type = instruction->base.value->type;
6541 assert(vector_type->id == ZigTypeIdVector);6541 assert(vector_type->id == ZigTypeIdVector);
...@@ -6572,7 +6572,7 @@ static LLVMValueRef ir_render_array_to_vector(CodeGen *g, Stage1Air *executable,...@@ -6572,7 +6572,7 @@ static LLVMValueRef ir_render_array_to_vector(CodeGen *g, Stage1Air *executable,
6572}6572}
65736573
6574static LLVMValueRef ir_render_assert_zero(CodeGen *g, Stage1Air *executable,6574static LLVMValueRef ir_render_assert_zero(CodeGen *g, Stage1Air *executable,
6575 IrInstGenAssertZero *instruction)6575 Stage1AirInstAssertZero *instruction)
6576{6576{
6577 LLVMValueRef target = ir_llvm_value(g, instruction->target);6577 LLVMValueRef target = ir_llvm_value(g, instruction->target);
6578 ZigType *int_type = instruction->target->value->type;6578 ZigType *int_type = instruction->target->value->type;
...@@ -6583,7 +6583,7 @@ static LLVMValueRef ir_render_assert_zero(CodeGen *g, Stage1Air *executable,...@@ -6583,7 +6583,7 @@ static LLVMValueRef ir_render_assert_zero(CodeGen *g, Stage1Air *executable,
6583}6583}
65846584
6585static LLVMValueRef ir_render_assert_non_null(CodeGen *g, Stage1Air *executable,6585static LLVMValueRef ir_render_assert_non_null(CodeGen *g, Stage1Air *executable,
6586 IrInstGenAssertNonNull *instruction)6586 Stage1AirInstAssertNonNull *instruction)
6587{6587{
6588 LLVMValueRef target = ir_llvm_value(g, instruction->target);6588 LLVMValueRef target = ir_llvm_value(g, instruction->target);
6589 ZigType *target_type = instruction->target->value->type;6589 ZigType *target_type = instruction->target->value->type;
...@@ -6608,7 +6608,7 @@ static LLVMValueRef ir_render_assert_non_null(CodeGen *g, Stage1Air *executable,...@@ -6608,7 +6608,7 @@ static LLVMValueRef ir_render_assert_non_null(CodeGen *g, Stage1Air *executable,
6608}6608}
66096609
6610static LLVMValueRef ir_render_suspend_begin(CodeGen *g, Stage1Air *executable,6610static LLVMValueRef ir_render_suspend_begin(CodeGen *g, Stage1Air *executable,
6611 IrInstGenSuspendBegin *instruction)6611 Stage1AirInstSuspendBegin *instruction)
6612{6612{
6613 if (fn_is_async(g->cur_fn)) {6613 if (fn_is_async(g->cur_fn)) {
6614 instruction->resume_bb = gen_suspend_begin(g, "SuspendResume");6614 instruction->resume_bb = gen_suspend_begin(g, "SuspendResume");
...@@ -6617,7 +6617,7 @@ static LLVMValueRef ir_render_suspend_begin(CodeGen *g, Stage1Air *executable,...@@ -6617,7 +6617,7 @@ static LLVMValueRef ir_render_suspend_begin(CodeGen *g, Stage1Air *executable,
6617}6617}
66186618
6619static LLVMValueRef ir_render_suspend_finish(CodeGen *g, Stage1Air *executable,6619static LLVMValueRef ir_render_suspend_finish(CodeGen *g, Stage1Air *executable,
6620 IrInstGenSuspendFinish *instruction)6620 Stage1AirInstSuspendFinish *instruction)
6621{6621{
6622 LLVMBuildRetVoid(g->builder);6622 LLVMBuildRetVoid(g->builder);
66236623
...@@ -6629,7 +6629,7 @@ static LLVMValueRef ir_render_suspend_finish(CodeGen *g, Stage1Air *executable,...@@ -6629,7 +6629,7 @@ static LLVMValueRef ir_render_suspend_finish(CodeGen *g, Stage1Air *executable,
6629 return nullptr;6629 return nullptr;
6630}6630}
66316631
6632static LLVMValueRef gen_await_early_return(CodeGen *g, IrInstGen *source_instr,6632static LLVMValueRef gen_await_early_return(CodeGen *g, Stage1AirInst *source_instr,
6633 LLVMValueRef target_frame_ptr, ZigType *result_type, ZigType *ptr_result_type,6633 LLVMValueRef target_frame_ptr, ZigType *result_type, ZigType *ptr_result_type,
6634 LLVMValueRef result_loc, bool non_async)6634 LLVMValueRef result_loc, bool non_async)
6635{6635{
...@@ -6668,7 +6668,7 @@ static LLVMValueRef gen_await_early_return(CodeGen *g, IrInstGen *source_instr,...@@ -6668,7 +6668,7 @@ static LLVMValueRef gen_await_early_return(CodeGen *g, IrInstGen *source_instr,
6668 }6668 }
6669}6669}
66706670
6671static LLVMValueRef ir_render_await(CodeGen *g, Stage1Air *executable, IrInstGenAwait *instruction) {6671static LLVMValueRef ir_render_await(CodeGen *g, Stage1Air *executable, Stage1AirInstAwait *instruction) {
6672 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;6672 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;
6673 LLVMValueRef zero = LLVMConstNull(usize_type_ref);6673 LLVMValueRef zero = LLVMConstNull(usize_type_ref);
6674 LLVMValueRef target_frame_ptr = ir_llvm_value(g, instruction->frame);6674 LLVMValueRef target_frame_ptr = ir_llvm_value(g, instruction->frame);
...@@ -6755,7 +6755,7 @@ static LLVMValueRef ir_render_await(CodeGen *g, Stage1Air *executable, IrInstGen...@@ -6755,7 +6755,7 @@ static LLVMValueRef ir_render_await(CodeGen *g, Stage1Air *executable, IrInstGen
6755 return nullptr;6755 return nullptr;
6756}6756}
67576757
6758static LLVMValueRef ir_render_resume(CodeGen *g, Stage1Air *executable, IrInstGenResume *instruction) {6758static LLVMValueRef ir_render_resume(CodeGen *g, Stage1Air *executable, Stage1AirInstResume *instruction) {
6759 LLVMValueRef frame = ir_llvm_value(g, instruction->frame);6759 LLVMValueRef frame = ir_llvm_value(g, instruction->frame);
6760 ZigType *frame_type = instruction->frame->value->type;6760 ZigType *frame_type = instruction->frame->value->type;
6761 assert(frame_type->id == ZigTypeIdAnyFrame);6761 assert(frame_type->id == ZigTypeIdAnyFrame);
...@@ -6765,14 +6765,14 @@ static LLVMValueRef ir_render_resume(CodeGen *g, Stage1Air *executable, IrInstGe...@@ -6765,14 +6765,14 @@ static LLVMValueRef ir_render_resume(CodeGen *g, Stage1Air *executable, IrInstGe
6765}6765}
67666766
6767static LLVMValueRef ir_render_frame_size(CodeGen *g, Stage1Air *executable,6767static LLVMValueRef ir_render_frame_size(CodeGen *g, Stage1Air *executable,
6768 IrInstGenFrameSize *instruction)6768 Stage1AirInstFrameSize *instruction)
6769{6769{
6770 LLVMValueRef fn_val = ir_llvm_value(g, instruction->fn);6770 LLVMValueRef fn_val = ir_llvm_value(g, instruction->fn);
6771 return gen_frame_size(g, fn_val);6771 return gen_frame_size(g, fn_val);
6772}6772}
67736773
6774static LLVMValueRef ir_render_spill_begin(CodeGen *g, Stage1Air *executable,6774static LLVMValueRef ir_render_spill_begin(CodeGen *g, Stage1Air *executable,
6775 IrInstGenSpillBegin *instruction)6775 Stage1AirInstSpillBegin *instruction)
6776{6776{
6777 if (!fn_is_async(g->cur_fn))6777 if (!fn_is_async(g->cur_fn))
6778 return nullptr;6778 return nullptr;
...@@ -6791,7 +6791,7 @@ static LLVMValueRef ir_render_spill_begin(CodeGen *g, Stage1Air *executable,...@@ -6791,7 +6791,7 @@ static LLVMValueRef ir_render_spill_begin(CodeGen *g, Stage1Air *executable,
6791 zig_unreachable();6791 zig_unreachable();
6792}6792}
67936793
6794static LLVMValueRef ir_render_spill_end(CodeGen *g, Stage1Air *executable, IrInstGenSpillEnd *instruction) {6794static LLVMValueRef ir_render_spill_end(CodeGen *g, Stage1Air *executable, Stage1AirInstSpillEnd *instruction) {
6795 if (!fn_is_async(g->cur_fn))6795 if (!fn_is_async(g->cur_fn))
6796 return ir_llvm_value(g, instruction->begin->operand);6796 return ir_llvm_value(g, instruction->begin->operand);
67976797
...@@ -6808,14 +6808,14 @@ static LLVMValueRef ir_render_spill_end(CodeGen *g, Stage1Air *executable, IrIns...@@ -6808,14 +6808,14 @@ static LLVMValueRef ir_render_spill_end(CodeGen *g, Stage1Air *executable, IrIns
6808}6808}
68096809
6810static LLVMValueRef ir_render_vector_extract_elem(CodeGen *g, Stage1Air *executable,6810static LLVMValueRef ir_render_vector_extract_elem(CodeGen *g, Stage1Air *executable,
6811 IrInstGenVectorExtractElem *instruction)6811 Stage1AirInstVectorExtractElem *instruction)
6812{6812{
6813 LLVMValueRef vector = ir_llvm_value(g, instruction->vector);6813 LLVMValueRef vector = ir_llvm_value(g, instruction->vector);
6814 LLVMValueRef index = ir_llvm_value(g, instruction->index);6814 LLVMValueRef index = ir_llvm_value(g, instruction->index);
6815 return LLVMBuildExtractElement(g->builder, vector, index, "");6815 return LLVMBuildExtractElement(g->builder, vector, index, "");
6816}6816}
68176817
6818static void set_debug_location(CodeGen *g, IrInstGen *instruction) {6818static void set_debug_location(CodeGen *g, Stage1AirInst *instruction) {
6819 AstNode *source_node = instruction->source_node;6819 AstNode *source_node = instruction->source_node;
6820 Scope *scope = instruction->scope;6820 Scope *scope = instruction->scope;
68216821
...@@ -6826,187 +6826,187 @@ static void set_debug_location(CodeGen *g, IrInstGen *instruction) {...@@ -6826,187 +6826,187 @@ static void set_debug_location(CodeGen *g, IrInstGen *instruction) {
6826 node_column_onebased(source_node), get_di_scope(g, scope));6826 node_column_onebased(source_node), get_di_scope(g, scope));
6827}6827}
68286828
6829static LLVMValueRef ir_render_instruction(CodeGen *g, Stage1Air *executable, IrInstGen *instruction) {6829static LLVMValueRef ir_render_instruction(CodeGen *g, Stage1Air *executable, Stage1AirInst *instruction) {
6830 switch (instruction->id) {6830 switch (instruction->id) {
6831 case IrInstGenIdInvalid:6831 case Stage1AirInstIdInvalid:
6832 case IrInstGenIdConst:6832 case Stage1AirInstIdConst:
6833 case IrInstGenIdAlloca:6833 case Stage1AirInstIdAlloca:
6834 zig_unreachable();6834 zig_unreachable();
68356835
6836 case IrInstGenIdDeclVar:6836 case Stage1AirInstIdDeclVar:
6837 return ir_render_decl_var(g, executable, (IrInstGenDeclVar *)instruction);6837 return ir_render_decl_var(g, executable, (Stage1AirInstDeclVar *)instruction);
6838 case IrInstGenIdReturn:6838 case Stage1AirInstIdReturn:
6839 return ir_render_return(g, executable, (IrInstGenReturn *)instruction);6839 return ir_render_return(g, executable, (Stage1AirInstReturn *)instruction);
6840 case IrInstGenIdBinOp:6840 case Stage1AirInstIdBinOp:
6841 return ir_render_bin_op(g, executable, (IrInstGenBinOp *)instruction);6841 return ir_render_bin_op(g, executable, (Stage1AirInstBinOp *)instruction);
6842 case IrInstGenIdCast:6842 case Stage1AirInstIdCast:
6843 return ir_render_cast(g, executable, (IrInstGenCast *)instruction);6843 return ir_render_cast(g, executable, (Stage1AirInstCast *)instruction);
6844 case IrInstGenIdUnreachable:6844 case Stage1AirInstIdUnreachable:
6845 return ir_render_unreachable(g, executable, (IrInstGenUnreachable *)instruction);6845 return ir_render_unreachable(g, executable, (Stage1AirInstUnreachable *)instruction);
6846 case IrInstGenIdCondBr:6846 case Stage1AirInstIdCondBr:
6847 return ir_render_cond_br(g, executable, (IrInstGenCondBr *)instruction);6847 return ir_render_cond_br(g, executable, (Stage1AirInstCondBr *)instruction);
6848 case IrInstGenIdBr:6848 case Stage1AirInstIdBr:
6849 return ir_render_br(g, executable, (IrInstGenBr *)instruction);6849 return ir_render_br(g, executable, (Stage1AirInstBr *)instruction);
6850 case IrInstGenIdBinaryNot:6850 case Stage1AirInstIdBinaryNot:
6851 return ir_render_binary_not(g, executable, (IrInstGenBinaryNot *)instruction);6851 return ir_render_binary_not(g, executable, (Stage1AirInstBinaryNot *)instruction);
6852 case IrInstGenIdNegation:6852 case Stage1AirInstIdNegation:
6853 return ir_render_negation(g, executable, (IrInstGenNegation *)instruction);6853 return ir_render_negation(g, executable, (Stage1AirInstNegation *)instruction);
6854 case IrInstGenIdLoadPtr:6854 case Stage1AirInstIdLoadPtr:
6855 return ir_render_load_ptr(g, executable, (IrInstGenLoadPtr *)instruction);6855 return ir_render_load_ptr(g, executable, (Stage1AirInstLoadPtr *)instruction);
6856 case IrInstGenIdStorePtr:6856 case Stage1AirInstIdStorePtr:
6857 return ir_render_store_ptr(g, executable, (IrInstGenStorePtr *)instruction);6857 return ir_render_store_ptr(g, executable, (Stage1AirInstStorePtr *)instruction);
6858 case IrInstGenIdVectorStoreElem:6858 case Stage1AirInstIdVectorStoreElem:
6859 return ir_render_vector_store_elem(g, executable, (IrInstGenVectorStoreElem *)instruction);6859 return ir_render_vector_store_elem(g, executable, (Stage1AirInstVectorStoreElem *)instruction);
6860 case IrInstGenIdVarPtr:6860 case Stage1AirInstIdVarPtr:
6861 return ir_render_var_ptr(g, executable, (IrInstGenVarPtr *)instruction);6861 return ir_render_var_ptr(g, executable, (Stage1AirInstVarPtr *)instruction);
6862 case IrInstGenIdReturnPtr:6862 case Stage1AirInstIdReturnPtr:
6863 return ir_render_return_ptr(g, executable, (IrInstGenReturnPtr *)instruction);6863 return ir_render_return_ptr(g, executable, (Stage1AirInstReturnPtr *)instruction);
6864 case IrInstGenIdElemPtr:6864 case Stage1AirInstIdElemPtr:
6865 return ir_render_elem_ptr(g, executable, (IrInstGenElemPtr *)instruction);6865 return ir_render_elem_ptr(g, executable, (Stage1AirInstElemPtr *)instruction);
6866 case IrInstGenIdCall:6866 case Stage1AirInstIdCall:
6867 return ir_render_call(g, executable, (IrInstGenCall *)instruction);6867 return ir_render_call(g, executable, (Stage1AirInstCall *)instruction);
6868 case IrInstGenIdStructFieldPtr:6868 case Stage1AirInstIdStructFieldPtr:
6869 return ir_render_struct_field_ptr(g, executable, (IrInstGenStructFieldPtr *)instruction);6869 return ir_render_struct_field_ptr(g, executable, (Stage1AirInstStructFieldPtr *)instruction);
6870 case IrInstGenIdUnionFieldPtr:6870 case Stage1AirInstIdUnionFieldPtr:
6871 return ir_render_union_field_ptr(g, executable, (IrInstGenUnionFieldPtr *)instruction);6871 return ir_render_union_field_ptr(g, executable, (Stage1AirInstUnionFieldPtr *)instruction);
6872 case IrInstGenIdAsm:6872 case Stage1AirInstIdAsm:
6873 return ir_render_asm_gen(g, executable, (IrInstGenAsm *)instruction);6873 return ir_render_asm_gen(g, executable, (Stage1AirInstAsm *)instruction);
6874 case IrInstGenIdTestNonNull:6874 case Stage1AirInstIdTestNonNull:
6875 return ir_render_test_non_null(g, executable, (IrInstGenTestNonNull *)instruction);6875 return ir_render_test_non_null(g, executable, (Stage1AirInstTestNonNull *)instruction);
6876 case IrInstGenIdOptionalUnwrapPtr:6876 case Stage1AirInstIdOptionalUnwrapPtr:
6877 return ir_render_optional_unwrap_ptr(g, executable, (IrInstGenOptionalUnwrapPtr *)instruction);6877 return ir_render_optional_unwrap_ptr(g, executable, (Stage1AirInstOptionalUnwrapPtr *)instruction);
6878 case IrInstGenIdClz:6878 case Stage1AirInstIdClz:
6879 return ir_render_clz(g, executable, (IrInstGenClz *)instruction);6879 return ir_render_clz(g, executable, (Stage1AirInstClz *)instruction);
6880 case IrInstGenIdCtz:6880 case Stage1AirInstIdCtz:
6881 return ir_render_ctz(g, executable, (IrInstGenCtz *)instruction);6881 return ir_render_ctz(g, executable, (Stage1AirInstCtz *)instruction);
6882 case IrInstGenIdPopCount:6882 case Stage1AirInstIdPopCount:
6883 return ir_render_pop_count(g, executable, (IrInstGenPopCount *)instruction);6883 return ir_render_pop_count(g, executable, (Stage1AirInstPopCount *)instruction);
6884 case IrInstGenIdSwitchBr:6884 case Stage1AirInstIdSwitchBr:
6885 return ir_render_switch_br(g, executable, (IrInstGenSwitchBr *)instruction);6885 return ir_render_switch_br(g, executable, (Stage1AirInstSwitchBr *)instruction);
6886 case IrInstGenIdBswap:6886 case Stage1AirInstIdBswap:
6887 return ir_render_bswap(g, executable, (IrInstGenBswap *)instruction);6887 return ir_render_bswap(g, executable, (Stage1AirInstBswap *)instruction);
6888 case IrInstGenIdBitReverse:6888 case Stage1AirInstIdBitReverse:
6889 return ir_render_bit_reverse(g, executable, (IrInstGenBitReverse *)instruction);6889 return ir_render_bit_reverse(g, executable, (Stage1AirInstBitReverse *)instruction);
6890 case IrInstGenIdPhi:6890 case Stage1AirInstIdPhi:
6891 return ir_render_phi(g, executable, (IrInstGenPhi *)instruction);6891 return ir_render_phi(g, executable, (Stage1AirInstPhi *)instruction);
6892 case IrInstGenIdRef:6892 case Stage1AirInstIdRef:
6893 return ir_render_ref(g, executable, (IrInstGenRef *)instruction);6893 return ir_render_ref(g, executable, (Stage1AirInstRef *)instruction);
6894 case IrInstGenIdErrName:6894 case Stage1AirInstIdErrName:
6895 return ir_render_err_name(g, executable, (IrInstGenErrName *)instruction);6895 return ir_render_err_name(g, executable, (Stage1AirInstErrName *)instruction);
6896 case IrInstGenIdCmpxchg:6896 case Stage1AirInstIdCmpxchg:
6897 return ir_render_cmpxchg(g, executable, (IrInstGenCmpxchg *)instruction);6897 return ir_render_cmpxchg(g, executable, (Stage1AirInstCmpxchg *)instruction);
6898 case IrInstGenIdFence:6898 case Stage1AirInstIdFence:
6899 return ir_render_fence(g, executable, (IrInstGenFence *)instruction);6899 return ir_render_fence(g, executable, (Stage1AirInstFence *)instruction);
6900 case IrInstGenIdReduce:6900 case Stage1AirInstIdReduce:
6901 return ir_render_reduce(g, executable, (IrInstGenReduce *)instruction);6901 return ir_render_reduce(g, executable, (Stage1AirInstReduce *)instruction);
6902 case IrInstGenIdTruncate:6902 case Stage1AirInstIdTruncate:
6903 return ir_render_truncate(g, executable, (IrInstGenTruncate *)instruction);6903 return ir_render_truncate(g, executable, (Stage1AirInstTruncate *)instruction);
6904 case IrInstGenIdBoolNot:6904 case Stage1AirInstIdBoolNot:
6905 return ir_render_bool_not(g, executable, (IrInstGenBoolNot *)instruction);6905 return ir_render_bool_not(g, executable, (Stage1AirInstBoolNot *)instruction);
6906 case IrInstGenIdMemset:6906 case Stage1AirInstIdMemset:
6907 return ir_render_memset(g, executable, (IrInstGenMemset *)instruction);6907 return ir_render_memset(g, executable, (Stage1AirInstMemset *)instruction);
6908 case IrInstGenIdMemcpy:6908 case Stage1AirInstIdMemcpy:
6909 return ir_render_memcpy(g, executable, (IrInstGenMemcpy *)instruction);6909 return ir_render_memcpy(g, executable, (Stage1AirInstMemcpy *)instruction);
6910 case IrInstGenIdSlice:6910 case Stage1AirInstIdSlice:
6911 return ir_render_slice(g, executable, (IrInstGenSlice *)instruction);6911 return ir_render_slice(g, executable, (Stage1AirInstSlice *)instruction);
6912 case IrInstGenIdBreakpoint:6912 case Stage1AirInstIdBreakpoint:
6913 return ir_render_breakpoint(g, executable, (IrInstGenBreakpoint *)instruction);6913 return ir_render_breakpoint(g, executable, (Stage1AirInstBreakpoint *)instruction);
6914 case IrInstGenIdReturnAddress:6914 case Stage1AirInstIdReturnAddress:
6915 return ir_render_return_address(g, executable, (IrInstGenReturnAddress *)instruction);6915 return ir_render_return_address(g, executable, (Stage1AirInstReturnAddress *)instruction);
6916 case IrInstGenIdFrameAddress:6916 case Stage1AirInstIdFrameAddress:
6917 return ir_render_frame_address(g, executable, (IrInstGenFrameAddress *)instruction);6917 return ir_render_frame_address(g, executable, (Stage1AirInstFrameAddress *)instruction);
6918 case IrInstGenIdFrameHandle:6918 case Stage1AirInstIdFrameHandle:
6919 return ir_render_handle(g, executable, (IrInstGenFrameHandle *)instruction);6919 return ir_render_handle(g, executable, (Stage1AirInstFrameHandle *)instruction);
6920 case IrInstGenIdOverflowOp:6920 case Stage1AirInstIdOverflowOp:
6921 return ir_render_overflow_op(g, executable, (IrInstGenOverflowOp *)instruction);6921 return ir_render_overflow_op(g, executable, (Stage1AirInstOverflowOp *)instruction);
6922 case IrInstGenIdTestErr:6922 case Stage1AirInstIdTestErr:
6923 return ir_render_test_err(g, executable, (IrInstGenTestErr *)instruction);6923 return ir_render_test_err(g, executable, (Stage1AirInstTestErr *)instruction);
6924 case IrInstGenIdUnwrapErrCode:6924 case Stage1AirInstIdUnwrapErrCode:
6925 return ir_render_unwrap_err_code(g, executable, (IrInstGenUnwrapErrCode *)instruction);6925 return ir_render_unwrap_err_code(g, executable, (Stage1AirInstUnwrapErrCode *)instruction);
6926 case IrInstGenIdUnwrapErrPayload:6926 case Stage1AirInstIdUnwrapErrPayload:
6927 return ir_render_unwrap_err_payload(g, executable, (IrInstGenUnwrapErrPayload *)instruction);6927 return ir_render_unwrap_err_payload(g, executable, (Stage1AirInstUnwrapErrPayload *)instruction);
6928 case IrInstGenIdOptionalWrap:6928 case Stage1AirInstIdOptionalWrap:
6929 return ir_render_optional_wrap(g, executable, (IrInstGenOptionalWrap *)instruction);6929 return ir_render_optional_wrap(g, executable, (Stage1AirInstOptionalWrap *)instruction);
6930 case IrInstGenIdErrWrapCode:6930 case Stage1AirInstIdErrWrapCode:
6931 return ir_render_err_wrap_code(g, executable, (IrInstGenErrWrapCode *)instruction);6931 return ir_render_err_wrap_code(g, executable, (Stage1AirInstErrWrapCode *)instruction);
6932 case IrInstGenIdErrWrapPayload:6932 case Stage1AirInstIdErrWrapPayload:
6933 return ir_render_err_wrap_payload(g, executable, (IrInstGenErrWrapPayload *)instruction);6933 return ir_render_err_wrap_payload(g, executable, (Stage1AirInstErrWrapPayload *)instruction);
6934 case IrInstGenIdUnionTag:6934 case Stage1AirInstIdUnionTag:
6935 return ir_render_union_tag(g, executable, (IrInstGenUnionTag *)instruction);6935 return ir_render_union_tag(g, executable, (Stage1AirInstUnionTag *)instruction);
6936 case IrInstGenIdPtrCast:6936 case Stage1AirInstIdPtrCast:
6937 return ir_render_ptr_cast(g, executable, (IrInstGenPtrCast *)instruction);6937 return ir_render_ptr_cast(g, executable, (Stage1AirInstPtrCast *)instruction);
6938 case IrInstGenIdBitCast:6938 case Stage1AirInstIdBitCast:
6939 return ir_render_bit_cast(g, executable, (IrInstGenBitCast *)instruction);6939 return ir_render_bit_cast(g, executable, (Stage1AirInstBitCast *)instruction);
6940 case IrInstGenIdWidenOrShorten:6940 case Stage1AirInstIdWidenOrShorten:
6941 return ir_render_widen_or_shorten(g, executable, (IrInstGenWidenOrShorten *)instruction);6941 return ir_render_widen_or_shorten(g, executable, (Stage1AirInstWidenOrShorten *)instruction);
6942 case IrInstGenIdPtrToInt:6942 case Stage1AirInstIdPtrToInt:
6943 return ir_render_ptr_to_int(g, executable, (IrInstGenPtrToInt *)instruction);6943 return ir_render_ptr_to_int(g, executable, (Stage1AirInstPtrToInt *)instruction);
6944 case IrInstGenIdIntToPtr:6944 case Stage1AirInstIdIntToPtr:
6945 return ir_render_int_to_ptr(g, executable, (IrInstGenIntToPtr *)instruction);6945 return ir_render_int_to_ptr(g, executable, (Stage1AirInstIntToPtr *)instruction);
6946 case IrInstGenIdIntToEnum:6946 case Stage1AirInstIdIntToEnum:
6947 return ir_render_int_to_enum(g, executable, (IrInstGenIntToEnum *)instruction);6947 return ir_render_int_to_enum(g, executable, (Stage1AirInstIntToEnum *)instruction);
6948 case IrInstGenIdIntToErr:6948 case Stage1AirInstIdIntToErr:
6949 return ir_render_int_to_err(g, executable, (IrInstGenIntToErr *)instruction);6949 return ir_render_int_to_err(g, executable, (Stage1AirInstIntToErr *)instruction);
6950 case IrInstGenIdErrToInt:6950 case Stage1AirInstIdErrToInt:
6951 return ir_render_err_to_int(g, executable, (IrInstGenErrToInt *)instruction);6951 return ir_render_err_to_int(g, executable, (Stage1AirInstErrToInt *)instruction);
6952 case IrInstGenIdPanic:6952 case Stage1AirInstIdPanic:
6953 return ir_render_panic(g, executable, (IrInstGenPanic *)instruction);6953 return ir_render_panic(g, executable, (Stage1AirInstPanic *)instruction);
6954 case IrInstGenIdTagName:6954 case Stage1AirInstIdTagName:
6955 return ir_render_enum_tag_name(g, executable, (IrInstGenTagName *)instruction);6955 return ir_render_enum_tag_name(g, executable, (Stage1AirInstTagName *)instruction);
6956 case IrInstGenIdFieldParentPtr:6956 case Stage1AirInstIdFieldParentPtr:
6957 return ir_render_field_parent_ptr(g, executable, (IrInstGenFieldParentPtr *)instruction);6957 return ir_render_field_parent_ptr(g, executable, (Stage1AirInstFieldParentPtr *)instruction);
6958 case IrInstGenIdAlignCast:6958 case Stage1AirInstIdAlignCast:
6959 return ir_render_align_cast(g, executable, (IrInstGenAlignCast *)instruction);6959 return ir_render_align_cast(g, executable, (Stage1AirInstAlignCast *)instruction);
6960 case IrInstGenIdErrorReturnTrace:6960 case Stage1AirInstIdErrorReturnTrace:
6961 return ir_render_error_return_trace(g, executable, (IrInstGenErrorReturnTrace *)instruction);6961 return ir_render_error_return_trace(g, executable, (Stage1AirInstErrorReturnTrace *)instruction);
6962 case IrInstGenIdAtomicRmw:6962 case Stage1AirInstIdAtomicRmw:
6963 return ir_render_atomic_rmw(g, executable, (IrInstGenAtomicRmw *)instruction);6963 return ir_render_atomic_rmw(g, executable, (Stage1AirInstAtomicRmw *)instruction);
6964 case IrInstGenIdAtomicLoad:6964 case Stage1AirInstIdAtomicLoad:
6965 return ir_render_atomic_load(g, executable, (IrInstGenAtomicLoad *)instruction);6965 return ir_render_atomic_load(g, executable, (Stage1AirInstAtomicLoad *)instruction);
6966 case IrInstGenIdAtomicStore:6966 case Stage1AirInstIdAtomicStore:
6967 return ir_render_atomic_store(g, executable, (IrInstGenAtomicStore *)instruction);6967 return ir_render_atomic_store(g, executable, (Stage1AirInstAtomicStore *)instruction);
6968 case IrInstGenIdSaveErrRetAddr:6968 case Stage1AirInstIdSaveErrRetAddr:
6969 return ir_render_save_err_ret_addr(g, executable, (IrInstGenSaveErrRetAddr *)instruction);6969 return ir_render_save_err_ret_addr(g, executable, (Stage1AirInstSaveErrRetAddr *)instruction);
6970 case IrInstGenIdFloatOp:6970 case Stage1AirInstIdFloatOp:
6971 return ir_render_float_op(g, executable, (IrInstGenFloatOp *)instruction);6971 return ir_render_float_op(g, executable, (Stage1AirInstFloatOp *)instruction);
6972 case IrInstGenIdMulAdd:6972 case Stage1AirInstIdMulAdd:
6973 return ir_render_mul_add(g, executable, (IrInstGenMulAdd *)instruction);6973 return ir_render_mul_add(g, executable, (Stage1AirInstMulAdd *)instruction);
6974 case IrInstGenIdArrayToVector:6974 case Stage1AirInstIdArrayToVector:
6975 return ir_render_array_to_vector(g, executable, (IrInstGenArrayToVector *)instruction);6975 return ir_render_array_to_vector(g, executable, (Stage1AirInstArrayToVector *)instruction);
6976 case IrInstGenIdVectorToArray:6976 case Stage1AirInstIdVectorToArray:
6977 return ir_render_vector_to_array(g, executable, (IrInstGenVectorToArray *)instruction);6977 return ir_render_vector_to_array(g, executable, (Stage1AirInstVectorToArray *)instruction);
6978 case IrInstGenIdAssertZero:6978 case Stage1AirInstIdAssertZero:
6979 return ir_render_assert_zero(g, executable, (IrInstGenAssertZero *)instruction);6979 return ir_render_assert_zero(g, executable, (Stage1AirInstAssertZero *)instruction);
6980 case IrInstGenIdAssertNonNull:6980 case Stage1AirInstIdAssertNonNull:
6981 return ir_render_assert_non_null(g, executable, (IrInstGenAssertNonNull *)instruction);6981 return ir_render_assert_non_null(g, executable, (Stage1AirInstAssertNonNull *)instruction);
6982 case IrInstGenIdPtrOfArrayToSlice:6982 case Stage1AirInstIdPtrOfArrayToSlice:
6983 return ir_render_ptr_of_array_to_slice(g, executable, (IrInstGenPtrOfArrayToSlice *)instruction);6983 return ir_render_ptr_of_array_to_slice(g, executable, (Stage1AirInstPtrOfArrayToSlice *)instruction);
6984 case IrInstGenIdSuspendBegin:6984 case Stage1AirInstIdSuspendBegin:
6985 return ir_render_suspend_begin(g, executable, (IrInstGenSuspendBegin *)instruction);6985 return ir_render_suspend_begin(g, executable, (Stage1AirInstSuspendBegin *)instruction);
6986 case IrInstGenIdSuspendFinish:6986 case Stage1AirInstIdSuspendFinish:
6987 return ir_render_suspend_finish(g, executable, (IrInstGenSuspendFinish *)instruction);6987 return ir_render_suspend_finish(g, executable, (Stage1AirInstSuspendFinish *)instruction);
6988 case IrInstGenIdResume:6988 case Stage1AirInstIdResume:
6989 return ir_render_resume(g, executable, (IrInstGenResume *)instruction);6989 return ir_render_resume(g, executable, (Stage1AirInstResume *)instruction);
6990 case IrInstGenIdFrameSize:6990 case Stage1AirInstIdFrameSize:
6991 return ir_render_frame_size(g, executable, (IrInstGenFrameSize *)instruction);6991 return ir_render_frame_size(g, executable, (Stage1AirInstFrameSize *)instruction);
6992 case IrInstGenIdAwait:6992 case Stage1AirInstIdAwait:
6993 return ir_render_await(g, executable, (IrInstGenAwait *)instruction);6993 return ir_render_await(g, executable, (Stage1AirInstAwait *)instruction);
6994 case IrInstGenIdSpillBegin:6994 case Stage1AirInstIdSpillBegin:
6995 return ir_render_spill_begin(g, executable, (IrInstGenSpillBegin *)instruction);6995 return ir_render_spill_begin(g, executable, (Stage1AirInstSpillBegin *)instruction);
6996 case IrInstGenIdSpillEnd:6996 case Stage1AirInstIdSpillEnd:
6997 return ir_render_spill_end(g, executable, (IrInstGenSpillEnd *)instruction);6997 return ir_render_spill_end(g, executable, (Stage1AirInstSpillEnd *)instruction);
6998 case IrInstGenIdShuffleVector:6998 case Stage1AirInstIdShuffleVector:
6999 return ir_render_shuffle_vector(g, executable, (IrInstGenShuffleVector *) instruction);6999 return ir_render_shuffle_vector(g, executable, (Stage1AirInstShuffleVector *) instruction);
7000 case IrInstGenIdSplat:7000 case Stage1AirInstIdSplat:
7001 return ir_render_splat(g, executable, (IrInstGenSplat *) instruction);7001 return ir_render_splat(g, executable, (Stage1AirInstSplat *) instruction);
7002 case IrInstGenIdVectorExtractElem:7002 case Stage1AirInstIdVectorExtractElem:
7003 return ir_render_vector_extract_elem(g, executable, (IrInstGenVectorExtractElem *) instruction);7003 return ir_render_vector_extract_elem(g, executable, (Stage1AirInstVectorExtractElem *) instruction);
7004 case IrInstGenIdWasmMemorySize:7004 case Stage1AirInstIdWasmMemorySize:
7005 return ir_render_wasm_memory_size(g, executable, (IrInstGenWasmMemorySize *) instruction);7005 return ir_render_wasm_memory_size(g, executable, (Stage1AirInstWasmMemorySize *) instruction);
7006 case IrInstGenIdWasmMemoryGrow:7006 case Stage1AirInstIdWasmMemoryGrow:
7007 return ir_render_wasm_memory_grow(g, executable, (IrInstGenWasmMemoryGrow *) instruction);7007 return ir_render_wasm_memory_grow(g, executable, (Stage1AirInstWasmMemoryGrow *) instruction);
7008 case IrInstGenIdExtern:7008 case Stage1AirInstIdExtern:
7009 return ir_render_extern(g, executable, (IrInstGenExtern *) instruction);7009 return ir_render_extern(g, executable, (Stage1AirInstExtern *) instruction);
7010 }7010 }
7011 zig_unreachable();7011 zig_unreachable();
7012}7012}
...@@ -7018,14 +7018,14 @@ static void ir_render(CodeGen *g, ZigFn *fn_entry) {...@@ -7018,14 +7018,14 @@ static void ir_render(CodeGen *g, ZigFn *fn_entry) {
7018 assert(executable->basic_block_list.length > 0);7018 assert(executable->basic_block_list.length > 0);
70197019
7020 for (size_t block_i = 0; block_i < executable->basic_block_list.length; block_i += 1) {7020 for (size_t block_i = 0; block_i < executable->basic_block_list.length; block_i += 1) {
7021 IrBasicBlockGen *current_block = executable->basic_block_list.at(block_i);7021 Stage1AirBasicBlock *current_block = executable->basic_block_list.at(block_i);
7022 if (get_scope_typeof(current_block->scope) != nullptr) {7022 if (get_scope_typeof(current_block->scope) != nullptr) {
7023 LLVMBuildBr(g->builder, current_block->llvm_block);7023 LLVMBuildBr(g->builder, current_block->llvm_block);
7024 }7024 }
7025 assert(current_block->llvm_block);7025 assert(current_block->llvm_block);
7026 LLVMPositionBuilderAtEnd(g->builder, current_block->llvm_block);7026 LLVMPositionBuilderAtEnd(g->builder, current_block->llvm_block);
7027 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {7027 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {
7028 IrInstGen *instruction = current_block->instruction_list.at(instr_i);7028 Stage1AirInst *instruction = current_block->instruction_list.at(instr_i);
7029 if (instruction->ref_count == 0 && !ir_inst_gen_has_side_effects(instruction))7029 if (instruction->ref_count == 0 && !ir_inst_gen_has_side_effects(instruction))
7030 continue;7030 continue;
7031 if (get_scope_typeof(instruction->scope) != nullptr)7031 if (get_scope_typeof(instruction->scope) != nullptr)
...@@ -8021,7 +8021,7 @@ static void build_all_basic_blocks(CodeGen *g, ZigFn *fn) {...@@ -8021,7 +8021,7 @@ static void build_all_basic_blocks(CodeGen *g, ZigFn *fn) {
8021 g->cur_preamble_llvm_block = first_bb;8021 g->cur_preamble_llvm_block = first_bb;
8022 }8022 }
8023 for (size_t block_i = 0; block_i < executable->basic_block_list.length; block_i += 1) {8023 for (size_t block_i = 0; block_i < executable->basic_block_list.length; block_i += 1) {
8024 IrBasicBlockGen *bb = executable->basic_block_list.at(block_i);8024 Stage1AirBasicBlock *bb = executable->basic_block_list.at(block_i);
8025 bb->llvm_block = LLVMAppendBasicBlock(fn_val, bb->name_hint);8025 bb->llvm_block = LLVMAppendBasicBlock(fn_val, bb->name_hint);
8026 }8026 }
8027 if (first_bb == nullptr) {8027 if (first_bb == nullptr) {
...@@ -8243,10 +8243,10 @@ static void do_code_gen(CodeGen *g) {...@@ -8243,10 +8243,10 @@ static void do_code_gen(CodeGen *g) {
8243 if (!is_async) {8243 if (!is_async) {
8244 // allocate async frames for nosuspend calls & awaits to async functions8244 // allocate async frames for nosuspend calls & awaits to async functions
8245 ZigType *largest_call_frame_type = nullptr;8245 ZigType *largest_call_frame_type = nullptr;
8246 IrInstGen *all_calls_alloca = ir_create_alloca(g, &fn_table_entry->fndef_scope->base,8246 Stage1AirInst *all_calls_alloca = ir_create_alloca(g, &fn_table_entry->fndef_scope->base,
8247 fn_table_entry->body_node, fn_table_entry, g->builtin_types.entry_void, "@async_call_frame");8247 fn_table_entry->body_node, fn_table_entry, g->builtin_types.entry_void, "@async_call_frame");
8248 for (size_t i = 0; i < fn_table_entry->call_list.length; i += 1) {8248 for (size_t i = 0; i < fn_table_entry->call_list.length; i += 1) {
8249 IrInstGenCall *call = fn_table_entry->call_list.at(i);8249 Stage1AirInstCall *call = fn_table_entry->call_list.at(i);
8250 if (call->fn_entry == nullptr)8250 if (call->fn_entry == nullptr)
8251 continue;8251 continue;
8252 if (!fn_is_async(call->fn_entry))8252 if (!fn_is_async(call->fn_entry))
...@@ -8268,7 +8268,7 @@ static void do_code_gen(CodeGen *g) {...@@ -8268,7 +8268,7 @@ static void do_code_gen(CodeGen *g) {
8268 }8268 }
8269 // allocate temporary stack data8269 // allocate temporary stack data
8270 for (size_t alloca_i = 0; alloca_i < fn_table_entry->alloca_gen_list.length; alloca_i += 1) {8270 for (size_t alloca_i = 0; alloca_i < fn_table_entry->alloca_gen_list.length; alloca_i += 1) {
8271 IrInstGenAlloca *instruction = fn_table_entry->alloca_gen_list.at(alloca_i);8271 Stage1AirInstAlloca *instruction = fn_table_entry->alloca_gen_list.at(alloca_i);
8272 ZigType *ptr_type = instruction->base.value->type;8272 ZigType *ptr_type = instruction->base.value->type;
8273 assert(ptr_type->id == ZigTypeIdPointer);8273 assert(ptr_type->id == ZigTypeIdPointer);
8274 ZigType *child_type = ptr_type->data.pointer.child_type;8274 ZigType *child_type = ptr_type->data.pointer.child_type;
...@@ -8422,7 +8422,7 @@ static void do_code_gen(CodeGen *g) {...@@ -8422,7 +8422,7 @@ static void do_code_gen(CodeGen *g) {
8422 g->cur_async_switch_instr = switch_instr;8422 g->cur_async_switch_instr = switch_instr;
84238423
8424 LLVMValueRef zero = LLVMConstNull(usize_type_ref);8424 LLVMValueRef zero = LLVMConstNull(usize_type_ref);
8425 IrBasicBlockGen *entry_block = executable->basic_block_list.at(0);8425 Stage1AirBasicBlock *entry_block = executable->basic_block_list.at(0);
8426 LLVMAddCase(switch_instr, zero, entry_block->llvm_block);8426 LLVMAddCase(switch_instr, zero, entry_block->llvm_block);
8427 g->cur_resume_block_count += 1;8427 g->cur_resume_block_count += 1;
84288428
...@@ -9379,7 +9379,7 @@ static void init(CodeGen *g) {...@@ -9379,7 +9379,7 @@ static void init(CodeGen *g) {
9379 define_builtin_types(g);9379 define_builtin_types(g);
9380 define_intern_values(g);9380 define_intern_values(g);
93819381
9382 IrInstGen *sentinel_instructions = heap::c_allocator.allocate<IrInstGen>(2);9382 Stage1AirInst *sentinel_instructions = heap::c_allocator.allocate<Stage1AirInst>(2);
9383 g->invalid_inst_gen = &sentinel_instructions[0];9383 g->invalid_inst_gen = &sentinel_instructions[0];
9384 g->invalid_inst_gen->value = g->pass1_arena->create<ZigValue>();9384 g->invalid_inst_gen->value = g->pass1_arena->create<ZigValue>();
9385 g->invalid_inst_gen->value->type = g->builtin_types.entry_invalid;9385 g->invalid_inst_gen->value->type = g->builtin_types.entry_invalid;
...@@ -9388,7 +9388,7 @@ static void init(CodeGen *g) {...@@ -9388,7 +9388,7 @@ static void init(CodeGen *g) {
9388 g->unreach_instruction->value = g->pass1_arena->create<ZigValue>();9388 g->unreach_instruction->value = g->pass1_arena->create<ZigValue>();
9389 g->unreach_instruction->value->type = g->builtin_types.entry_unreachable;9389 g->unreach_instruction->value->type = g->builtin_types.entry_unreachable;
93909390
9391 g->invalid_inst_src = heap::c_allocator.create<IrInstSrc>();9391 g->invalid_inst_src = heap::c_allocator.create<Stage1ZirInst>();
93929392
9393 define_builtin_fns(g);9393 define_builtin_fns(g);
9394 Error err;9394 Error err;
src/stage1/ir.cpp+2246-2246
...@@ -25,10 +25,10 @@...@@ -25,10 +25,10 @@
25struct IrBuilderGen {25struct IrBuilderGen {
26 CodeGen *codegen;26 CodeGen *codegen;
27 Stage1Air *exec;27 Stage1Air *exec;
28 IrBasicBlockGen *current_basic_block;28 Stage1AirBasicBlock *current_basic_block;
2929
30 // track for immediate post-analysis destruction30 // track for immediate post-analysis destruction
31 mem::List<IrInstGenConst *> constants;31 mem::List<Stage1AirInstConst *> constants;
32};32};
3333
34struct IrAnalyze {34struct IrAnalyze {
...@@ -40,17 +40,17 @@ struct IrAnalyze {...@@ -40,17 +40,17 @@ struct IrAnalyze {
40 size_t instruction_index;40 size_t instruction_index;
41 ZigType *explicit_return_type;41 ZigType *explicit_return_type;
42 AstNode *explicit_return_type_source_node;42 AstNode *explicit_return_type_source_node;
43 ZigList<IrInstGen *> src_implicit_return_type_list;43 ZigList<Stage1AirInst *> src_implicit_return_type_list;
44 ZigList<IrSuspendPosition> resume_stack;44 ZigList<IrSuspendPosition> resume_stack;
45 Stage1ZirBasicBlock *const_predecessor_bb;45 Stage1ZirBasicBlock *const_predecessor_bb;
46 size_t ref_count;46 size_t ref_count;
47 size_t break_debug_id; // for debugging purposes47 size_t break_debug_id; // for debugging purposes
48 IrInstGen *return_ptr;48 Stage1AirInst *return_ptr;
49 Stage1Air *parent_exec;49 Stage1Air *parent_exec;
50 size_t *backward_branch_count;50 size_t *backward_branch_count;
51 size_t *backward_branch_quota;51 size_t *backward_branch_quota;
52 ZigFn *fn;52 ZigFn *fn;
53 IrInstSrc *suspend_source_instr;53 Stage1ZirInst *suspend_source_instr;
5454
55 // For the purpose of using in a debugger55 // For the purpose of using in a debugger
56 void dump();56 void dump();
...@@ -216,16 +216,16 @@ struct DbgIrBreakPoint {...@@ -216,16 +216,16 @@ struct DbgIrBreakPoint {
216 uint32_t line;216 uint32_t line;
217};217};
218218
219static IrInstGen *ir_implicit_cast(IrAnalyze *ira, IrInstGen *value, ZigType *expected_type);219static Stage1AirInst *ir_implicit_cast(IrAnalyze *ira, Stage1AirInst *value, ZigType *expected_type);
220static IrInstGen *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node,220static Stage1AirInst *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node,
221 IrInstGen *value, ZigType *expected_type);221 Stage1AirInst *value, ZigType *expected_type);
222static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *ptr,222static Stage1AirInst *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *ptr,
223 ResultLoc *result_loc);223 ResultLoc *result_loc);
224static IrInstGen *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name,224static Stage1AirInst *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name,
225 Scope *scope, AstNode *source_node, IrInstGen *container_ptr, AstNode *container_ptr_src,225 Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, AstNode *container_ptr_src,
226 ZigType *container_type, bool initializing);226 ZigType *container_type, bool initializing);
227static IrInstGen *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var);227static Stage1AirInst *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var);
228static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstGen *op);228static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, Stage1AirInst *op);
229static ZigType *adjust_ptr_align(CodeGen *g, ZigType *ptr_type, uint32_t new_align);229static ZigType *adjust_ptr_align(CodeGen *g, ZigType *ptr_type, uint32_t new_align);
230static ZigType *adjust_ptr_const(CodeGen *g, ZigType *ptr_type, bool is_const);230static ZigType *adjust_ptr_const(CodeGen *g, ZigType *ptr_type, bool is_const);
231static ZigType *adjust_slice_align(CodeGen *g, ZigType *slice_type, uint32_t new_align);231static ZigType *adjust_slice_align(CodeGen *g, ZigType *slice_type, uint32_t new_align);
...@@ -233,40 +233,40 @@ static Error buf_read_value_bytes(IrAnalyze *ira, CodeGen *codegen, AstNode *sou...@@ -233,40 +233,40 @@ static Error buf_read_value_bytes(IrAnalyze *ira, CodeGen *codegen, AstNode *sou
233static void buf_write_value_bytes(CodeGen *codegen, uint8_t *buf, ZigValue *val);233static void buf_write_value_bytes(CodeGen *codegen, uint8_t *buf, ZigValue *val);
234static Error ir_read_const_ptr(IrAnalyze *ira, CodeGen *codegen, AstNode *source_node,234static Error ir_read_const_ptr(IrAnalyze *ira, CodeGen *codegen, AstNode *source_node,
235 ZigValue *out_val, ZigValue *ptr_val);235 ZigValue *out_val, ZigValue *ptr_val);
236static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,236static Stage1AirInst *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
237 IrInstGen *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src,237 Stage1AirInst *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src,
238 bool safety_check_on, bool keep_bigger_alignment);238 bool safety_check_on, bool keep_bigger_alignment);
239static ZigValue *ir_resolve_const(IrAnalyze *ira, IrInstGen *value, UndefAllowed undef_allowed);239static ZigValue *ir_resolve_const(IrAnalyze *ira, Stage1AirInst *value, UndefAllowed undef_allowed);
240static Error resolve_ptr_align(IrAnalyze *ira, ZigType *ty, uint32_t *result_align);240static Error resolve_ptr_align(IrAnalyze *ira, ZigType *ty, uint32_t *result_align);
241static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,241static Stage1AirInst *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
242 ZigType *ptr_type);242 ZigType *ptr_type);
243static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,243static Stage1AirInst *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
244 ZigType *dest_type);244 ZigType *dest_type);
245static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_source_instr,245static Stage1AirInst *ir_resolve_result_raw(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr,
246 ResultLoc *result_loc, ZigType *value_type, IrInstGen *value, bool force_runtime, bool allow_discard);246 ResultLoc *result_loc, ZigType *value_type, Stage1AirInst *value, bool force_runtime, bool allow_discard);
247static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_instr,247static Stage1AirInst *ir_resolve_result(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr,
248 ResultLoc *result_loc, ZigType *value_type, IrInstGen *value, bool force_runtime, bool allow_discard);248 ResultLoc *result_loc, ZigType *value_type, Stage1AirInst *value, bool force_runtime, bool allow_discard);
249static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,249static Stage1AirInst *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
250 IrInstGen *base_ptr, bool safety_check_on, bool initializing);250 Stage1AirInst *base_ptr, bool safety_check_on, bool initializing);
251static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,251static Stage1AirInst *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
252 IrInstGen *base_ptr, bool safety_check_on, bool initializing);252 Stage1AirInst *base_ptr, bool safety_check_on, bool initializing);
253static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,253static Stage1AirInst *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,
254 IrInstGen *base_ptr, bool initializing);254 Stage1AirInst *base_ptr, bool initializing);
255static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,255static Stage1AirInst *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
256 IrInstGen *ptr, IrInstGen *uncasted_value, bool allow_write_through_const);256 Stage1AirInst *ptr, Stage1AirInst *uncasted_value, bool allow_write_through_const);
257static void ir_reset_result(ResultLoc *result_loc);257static void ir_reset_result(ResultLoc *result_loc);
258static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,258static Stage1AirInst *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
259 TypeStructField *field, IrInstGen *struct_ptr, ZigType *struct_type, bool initializing);259 TypeStructField *field, Stage1AirInst *struct_ptr, ZigType *struct_type, bool initializing);
260static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,260static Stage1AirInst *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,
261 Scope *scope, AstNode *source_node, IrInstGen *container_ptr, ZigType *container_type);261 Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, ZigType *container_type);
262static IrInstGen *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value);262static Stage1AirInst *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value);
263static IrInstGen *ir_error_dependency_loop(IrAnalyze *ira, AstNode *source_node);263static Stage1AirInst *ir_error_dependency_loop(IrAnalyze *ira, AstNode *source_node);
264static IrInstGen *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty);264static Stage1AirInst *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty);
265static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node,265static Stage1AirInst *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node,
266 AstNode *field_source_node, ZigType *union_type, Buf *field_name, IrInstGen *field_result_loc,266 AstNode *field_source_node, ZigType *union_type, Buf *field_name, Stage1AirInst *field_result_loc,
267 IrInstGen *result_loc);267 Stage1AirInst *result_loc);
268static IrInstGen *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,268static Stage1AirInst *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,
269 IrInstGen *struct_operand, TypeStructField *field);269 Stage1AirInst *struct_operand, TypeStructField *field);
270static bool value_cmp_numeric_val_any(ZigValue *left, Cmp predicate, ZigValue *right);270static bool value_cmp_numeric_val_any(ZigValue *left, Cmp predicate, ZigValue *right);
271static bool value_cmp_numeric_val_all(ZigValue *left, Cmp predicate, ZigValue *right);271static bool value_cmp_numeric_val_all(ZigValue *left, Cmp predicate, ZigValue *right);
272static void memoize_field_init_val(CodeGen *codegen, ZigType *container_type, TypeStructField *field);272static void memoize_field_init_val(CodeGen *codegen, ZigType *container_type, TypeStructField *field);
...@@ -276,195 +276,195 @@ static Error ir_resolve_lazy_recurse(AstNode *source_node, ZigValue *val);...@@ -276,195 +276,195 @@ static Error ir_resolve_lazy_recurse(AstNode *source_node, ZigValue *val);
276static Error ir_resolve_lazy_recurse_array(AstNode *source_node, ZigValue *val, size_t len);276static Error ir_resolve_lazy_recurse_array(AstNode *source_node, ZigValue *val, size_t len);
277277
278278
279static void ir_assert_impl(bool ok, IrInstGen *source_instruction, char const *file, unsigned int line) {279static void ir_assert_impl(bool ok, Stage1AirInst *source_instruction, char const *file, unsigned int line) {
280 if (ok) return;280 if (ok) return;
281 src_assert_impl(ok, source_instruction->source_node, file, line);281 src_assert_impl(ok, source_instruction->source_node, file, line);
282}282}
283283
284#define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__)284#define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__)
285285
286void destroy_instruction_gen(IrInstGen *inst) {286void destroy_instruction_gen(Stage1AirInst *inst) {
287 switch (inst->id) {287 switch (inst->id) {
288 case IrInstGenIdInvalid:288 case Stage1AirInstIdInvalid:
289 zig_unreachable();289 zig_unreachable();
290 case IrInstGenIdReturn:290 case Stage1AirInstIdReturn:
291 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenReturn *>(inst));291 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstReturn *>(inst));
292 case IrInstGenIdConst:292 case Stage1AirInstIdConst:
293 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenConst *>(inst));293 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstConst *>(inst));
294 case IrInstGenIdBinOp:294 case Stage1AirInstIdBinOp:
295 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBinOp *>(inst));295 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBinOp *>(inst));
296 case IrInstGenIdCast:296 case Stage1AirInstIdCast:
297 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenCast *>(inst));297 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstCast *>(inst));
298 case IrInstGenIdCall:298 case Stage1AirInstIdCall:
299 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenCall *>(inst));299 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstCall *>(inst));
300 case IrInstGenIdCondBr:300 case Stage1AirInstIdCondBr:
301 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenCondBr *>(inst));301 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstCondBr *>(inst));
302 case IrInstGenIdBr:302 case Stage1AirInstIdBr:
303 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBr *>(inst));303 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBr *>(inst));
304 case IrInstGenIdPhi:304 case Stage1AirInstIdPhi:
305 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPhi *>(inst));305 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPhi *>(inst));
306 case IrInstGenIdUnreachable:306 case Stage1AirInstIdUnreachable:
307 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenUnreachable *>(inst));307 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstUnreachable *>(inst));
308 case IrInstGenIdElemPtr:308 case Stage1AirInstIdElemPtr:
309 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenElemPtr *>(inst));309 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstElemPtr *>(inst));
310 case IrInstGenIdVarPtr:310 case Stage1AirInstIdVarPtr:
311 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenVarPtr *>(inst));311 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstVarPtr *>(inst));
312 case IrInstGenIdReturnPtr:312 case Stage1AirInstIdReturnPtr:
313 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenReturnPtr *>(inst));313 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstReturnPtr *>(inst));
314 case IrInstGenIdLoadPtr:314 case Stage1AirInstIdLoadPtr:
315 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenLoadPtr *>(inst));315 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstLoadPtr *>(inst));
316 case IrInstGenIdStorePtr:316 case Stage1AirInstIdStorePtr:
317 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenStorePtr *>(inst));317 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstStorePtr *>(inst));
318 case IrInstGenIdVectorStoreElem:318 case Stage1AirInstIdVectorStoreElem:
319 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenVectorStoreElem *>(inst));319 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstVectorStoreElem *>(inst));
320 case IrInstGenIdStructFieldPtr:320 case Stage1AirInstIdStructFieldPtr:
321 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenStructFieldPtr *>(inst));321 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstStructFieldPtr *>(inst));
322 case IrInstGenIdUnionFieldPtr:322 case Stage1AirInstIdUnionFieldPtr:
323 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenUnionFieldPtr *>(inst));323 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstUnionFieldPtr *>(inst));
324 case IrInstGenIdAsm:324 case Stage1AirInstIdAsm:
325 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAsm *>(inst));325 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAsm *>(inst));
326 case IrInstGenIdTestNonNull:326 case Stage1AirInstIdTestNonNull:
327 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenTestNonNull *>(inst));327 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstTestNonNull *>(inst));
328 case IrInstGenIdOptionalUnwrapPtr:328 case Stage1AirInstIdOptionalUnwrapPtr:
329 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenOptionalUnwrapPtr *>(inst));329 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstOptionalUnwrapPtr *>(inst));
330 case IrInstGenIdPopCount:330 case Stage1AirInstIdPopCount:
331 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPopCount *>(inst));331 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPopCount *>(inst));
332 case IrInstGenIdClz:332 case Stage1AirInstIdClz:
333 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenClz *>(inst));333 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstClz *>(inst));
334 case IrInstGenIdCtz:334 case Stage1AirInstIdCtz:
335 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenCtz *>(inst));335 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstCtz *>(inst));
336 case IrInstGenIdBswap:336 case Stage1AirInstIdBswap:
337 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBswap *>(inst));337 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBswap *>(inst));
338 case IrInstGenIdBitReverse:338 case Stage1AirInstIdBitReverse:
339 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBitReverse *>(inst));339 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBitReverse *>(inst));
340 case IrInstGenIdSwitchBr:340 case Stage1AirInstIdSwitchBr:
341 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSwitchBr *>(inst));341 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSwitchBr *>(inst));
342 case IrInstGenIdUnionTag:342 case Stage1AirInstIdUnionTag:
343 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenUnionTag *>(inst));343 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstUnionTag *>(inst));
344 case IrInstGenIdRef:344 case Stage1AirInstIdRef:
345 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenRef *>(inst));345 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstRef *>(inst));
346 case IrInstGenIdErrName:346 case Stage1AirInstIdErrName:
347 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenErrName *>(inst));347 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstErrName *>(inst));
348 case IrInstGenIdCmpxchg:348 case Stage1AirInstIdCmpxchg:
349 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenCmpxchg *>(inst));349 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstCmpxchg *>(inst));
350 case IrInstGenIdFence:350 case Stage1AirInstIdFence:
351 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFence *>(inst));351 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFence *>(inst));
352 case IrInstGenIdReduce:352 case Stage1AirInstIdReduce:
353 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenReduce *>(inst));353 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstReduce *>(inst));
354 case IrInstGenIdTruncate:354 case Stage1AirInstIdTruncate:
355 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenTruncate *>(inst));355 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstTruncate *>(inst));
356 case IrInstGenIdShuffleVector:356 case Stage1AirInstIdShuffleVector:
357 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenShuffleVector *>(inst));357 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstShuffleVector *>(inst));
358 case IrInstGenIdSplat:358 case Stage1AirInstIdSplat:
359 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSplat *>(inst));359 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSplat *>(inst));
360 case IrInstGenIdBoolNot:360 case Stage1AirInstIdBoolNot:
361 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBoolNot *>(inst));361 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBoolNot *>(inst));
362 case IrInstGenIdMemset:362 case Stage1AirInstIdMemset:
363 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenMemset *>(inst));363 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstMemset *>(inst));
364 case IrInstGenIdMemcpy:364 case Stage1AirInstIdMemcpy:
365 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenMemcpy *>(inst));365 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstMemcpy *>(inst));
366 case IrInstGenIdSlice:366 case Stage1AirInstIdSlice:
367 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSlice *>(inst));367 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSlice *>(inst));
368 case IrInstGenIdBreakpoint:368 case Stage1AirInstIdBreakpoint:
369 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBreakpoint *>(inst));369 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBreakpoint *>(inst));
370 case IrInstGenIdReturnAddress:370 case Stage1AirInstIdReturnAddress:
371 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenReturnAddress *>(inst));371 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstReturnAddress *>(inst));
372 case IrInstGenIdFrameAddress:372 case Stage1AirInstIdFrameAddress:
373 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFrameAddress *>(inst));373 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFrameAddress *>(inst));
374 case IrInstGenIdFrameHandle:374 case Stage1AirInstIdFrameHandle:
375 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFrameHandle *>(inst));375 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFrameHandle *>(inst));
376 case IrInstGenIdFrameSize:376 case Stage1AirInstIdFrameSize:
377 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFrameSize *>(inst));377 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFrameSize *>(inst));
378 case IrInstGenIdOverflowOp:378 case Stage1AirInstIdOverflowOp:
379 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenOverflowOp *>(inst));379 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstOverflowOp *>(inst));
380 case IrInstGenIdTestErr:380 case Stage1AirInstIdTestErr:
381 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenTestErr *>(inst));381 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstTestErr *>(inst));
382 case IrInstGenIdUnwrapErrCode:382 case Stage1AirInstIdUnwrapErrCode:
383 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenUnwrapErrCode *>(inst));383 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstUnwrapErrCode *>(inst));
384 case IrInstGenIdUnwrapErrPayload:384 case Stage1AirInstIdUnwrapErrPayload:
385 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenUnwrapErrPayload *>(inst));385 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstUnwrapErrPayload *>(inst));
386 case IrInstGenIdOptionalWrap:386 case Stage1AirInstIdOptionalWrap:
387 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenOptionalWrap *>(inst));387 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstOptionalWrap *>(inst));
388 case IrInstGenIdErrWrapCode:388 case Stage1AirInstIdErrWrapCode:
389 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenErrWrapCode *>(inst));389 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstErrWrapCode *>(inst));
390 case IrInstGenIdErrWrapPayload:390 case Stage1AirInstIdErrWrapPayload:
391 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenErrWrapPayload *>(inst));391 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstErrWrapPayload *>(inst));
392 case IrInstGenIdPtrCast:392 case Stage1AirInstIdPtrCast:
393 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPtrCast *>(inst));393 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPtrCast *>(inst));
394 case IrInstGenIdBitCast:394 case Stage1AirInstIdBitCast:
395 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBitCast *>(inst));395 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBitCast *>(inst));
396 case IrInstGenIdWidenOrShorten:396 case Stage1AirInstIdWidenOrShorten:
397 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenWidenOrShorten *>(inst));397 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstWidenOrShorten *>(inst));
398 case IrInstGenIdPtrToInt:398 case Stage1AirInstIdPtrToInt:
399 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPtrToInt *>(inst));399 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPtrToInt *>(inst));
400 case IrInstGenIdIntToPtr:400 case Stage1AirInstIdIntToPtr:
401 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenIntToPtr *>(inst));401 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstIntToPtr *>(inst));
402 case IrInstGenIdIntToEnum:402 case Stage1AirInstIdIntToEnum:
403 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenIntToEnum *>(inst));403 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstIntToEnum *>(inst));
404 case IrInstGenIdIntToErr:404 case Stage1AirInstIdIntToErr:
405 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenIntToErr *>(inst));405 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstIntToErr *>(inst));
406 case IrInstGenIdErrToInt:406 case Stage1AirInstIdErrToInt:
407 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenErrToInt *>(inst));407 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstErrToInt *>(inst));
408 case IrInstGenIdTagName:408 case Stage1AirInstIdTagName:
409 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenTagName *>(inst));409 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstTagName *>(inst));
410 case IrInstGenIdPanic:410 case Stage1AirInstIdPanic:
411 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPanic *>(inst));411 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPanic *>(inst));
412 case IrInstGenIdFieldParentPtr:412 case Stage1AirInstIdFieldParentPtr:
413 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFieldParentPtr *>(inst));413 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFieldParentPtr *>(inst));
414 case IrInstGenIdAlignCast:414 case Stage1AirInstIdAlignCast:
415 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAlignCast *>(inst));415 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAlignCast *>(inst));
416 case IrInstGenIdErrorReturnTrace:416 case Stage1AirInstIdErrorReturnTrace:
417 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenErrorReturnTrace *>(inst));417 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstErrorReturnTrace *>(inst));
418 case IrInstGenIdAtomicRmw:418 case Stage1AirInstIdAtomicRmw:
419 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAtomicRmw *>(inst));419 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAtomicRmw *>(inst));
420 case IrInstGenIdSaveErrRetAddr:420 case Stage1AirInstIdSaveErrRetAddr:
421 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSaveErrRetAddr *>(inst));421 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSaveErrRetAddr *>(inst));
422 case IrInstGenIdFloatOp:422 case Stage1AirInstIdFloatOp:
423 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFloatOp *>(inst));423 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFloatOp *>(inst));
424 case IrInstGenIdMulAdd:424 case Stage1AirInstIdMulAdd:
425 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenMulAdd *>(inst));425 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstMulAdd *>(inst));
426 case IrInstGenIdAtomicLoad:426 case Stage1AirInstIdAtomicLoad:
427 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAtomicLoad *>(inst));427 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAtomicLoad *>(inst));
428 case IrInstGenIdAtomicStore:428 case Stage1AirInstIdAtomicStore:
429 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAtomicStore *>(inst));429 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAtomicStore *>(inst));
430 case IrInstGenIdDeclVar:430 case Stage1AirInstIdDeclVar:
431 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenDeclVar *>(inst));431 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstDeclVar *>(inst));
432 case IrInstGenIdArrayToVector:432 case Stage1AirInstIdArrayToVector:
433 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenArrayToVector *>(inst));433 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstArrayToVector *>(inst));
434 case IrInstGenIdVectorToArray:434 case Stage1AirInstIdVectorToArray:
435 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenVectorToArray *>(inst));435 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstVectorToArray *>(inst));
436 case IrInstGenIdPtrOfArrayToSlice:436 case Stage1AirInstIdPtrOfArrayToSlice:
437 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPtrOfArrayToSlice *>(inst));437 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPtrOfArrayToSlice *>(inst));
438 case IrInstGenIdAssertZero:438 case Stage1AirInstIdAssertZero:
439 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAssertZero *>(inst));439 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAssertZero *>(inst));
440 case IrInstGenIdAssertNonNull:440 case Stage1AirInstIdAssertNonNull:
441 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAssertNonNull *>(inst));441 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAssertNonNull *>(inst));
442 case IrInstGenIdAlloca:442 case Stage1AirInstIdAlloca:
443 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAlloca *>(inst));443 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAlloca *>(inst));
444 case IrInstGenIdSuspendBegin:444 case Stage1AirInstIdSuspendBegin:
445 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSuspendBegin *>(inst));445 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSuspendBegin *>(inst));
446 case IrInstGenIdSuspendFinish:446 case Stage1AirInstIdSuspendFinish:
447 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSuspendFinish *>(inst));447 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSuspendFinish *>(inst));
448 case IrInstGenIdResume:448 case Stage1AirInstIdResume:
449 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenResume *>(inst));449 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstResume *>(inst));
450 case IrInstGenIdAwait:450 case Stage1AirInstIdAwait:
451 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAwait *>(inst));451 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAwait *>(inst));
452 case IrInstGenIdSpillBegin:452 case Stage1AirInstIdSpillBegin:
453 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSpillBegin *>(inst));453 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSpillBegin *>(inst));
454 case IrInstGenIdSpillEnd:454 case Stage1AirInstIdSpillEnd:
455 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSpillEnd *>(inst));455 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSpillEnd *>(inst));
456 case IrInstGenIdVectorExtractElem:456 case Stage1AirInstIdVectorExtractElem:
457 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenVectorExtractElem *>(inst));457 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstVectorExtractElem *>(inst));
458 case IrInstGenIdBinaryNot:458 case Stage1AirInstIdBinaryNot:
459 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBinaryNot *>(inst));459 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBinaryNot *>(inst));
460 case IrInstGenIdNegation:460 case Stage1AirInstIdNegation:
461 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenNegation *>(inst));461 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstNegation *>(inst));
462 case IrInstGenIdWasmMemorySize:462 case Stage1AirInstIdWasmMemorySize:
463 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenWasmMemorySize *>(inst));463 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstWasmMemorySize *>(inst));
464 case IrInstGenIdWasmMemoryGrow:464 case Stage1AirInstIdWasmMemoryGrow:
465 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenWasmMemoryGrow *>(inst));465 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstWasmMemoryGrow *>(inst));
466 case IrInstGenIdExtern:466 case Stage1AirInstIdExtern:
467 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenExtern *>(inst));467 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstExtern *>(inst));
468 }468 }
469 zig_unreachable();469 zig_unreachable();
470}470}
...@@ -476,7 +476,7 @@ static void ira_deref(IrAnalyze *ira) {...@@ -476,7 +476,7 @@ static void ira_deref(IrAnalyze *ira) {
476 if (ira->ref_count > 1) {476 if (ira->ref_count > 1) {
477 ira->ref_count -= 1;477 ira->ref_count -= 1;
478478
479 // immediate destruction of dangling IrInstGenConst is not possible479 // immediate destruction of dangling Stage1AirInstConst is not possible
480 // free tracking memory because it will never be used480 // free tracking memory because it will never be used
481 ira->new_irb.constants.deinit(&heap::c_allocator);481 ira->new_irb.constants.deinit(&heap::c_allocator);
482 return;482 return;
...@@ -486,7 +486,7 @@ static void ira_deref(IrAnalyze *ira) {...@@ -486,7 +486,7 @@ static void ira_deref(IrAnalyze *ira) {
486 for (size_t bb_i = 0; bb_i < ira->zir->basic_block_list.length; bb_i += 1) {486 for (size_t bb_i = 0; bb_i < ira->zir->basic_block_list.length; bb_i += 1) {
487 Stage1ZirBasicBlock *pass1_bb = ira->zir->basic_block_list.items[bb_i];487 Stage1ZirBasicBlock *pass1_bb = ira->zir->basic_block_list.items[bb_i];
488 for (size_t inst_i = 0; inst_i < pass1_bb->instruction_list.length; inst_i += 1) {488 for (size_t inst_i = 0; inst_i < pass1_bb->instruction_list.length; inst_i += 1) {
489 IrInstSrc *pass1_inst = pass1_bb->instruction_list.items[inst_i];489 Stage1ZirInst *pass1_inst = pass1_bb->instruction_list.items[inst_i];
490 destroy_instruction_src(pass1_inst);490 destroy_instruction_src(pass1_inst);
491 }491 }
492 heap::c_allocator.destroy(pass1_bb);492 heap::c_allocator.destroy(pass1_bb);
...@@ -497,7 +497,7 @@ static void ira_deref(IrAnalyze *ira) {...@@ -497,7 +497,7 @@ static void ira_deref(IrAnalyze *ira) {
497 ira->src_implicit_return_type_list.deinit();497 ira->src_implicit_return_type_list.deinit();
498 ira->resume_stack.deinit();498 ira->resume_stack.deinit();
499499
500 // destroy dangling IrInstGenConst500 // destroy dangling Stage1AirInstConst
501 for (size_t i = 0; i < ira->new_irb.constants.length; i += 1) {501 for (size_t i = 0; i < ira->new_irb.constants.length; i += 1) {
502 auto constant = ira->new_irb.constants.items[i];502 auto constant = ira->new_irb.constants.items[i];
503 if (constant->base.ref_count == 0 && !ir_inst_gen_has_side_effects(&constant->base))503 if (constant->base.ref_count == 0 && !ir_inst_gen_has_side_effects(&constant->base))
...@@ -675,7 +675,7 @@ static bool types_have_same_zig_comptime_repr(CodeGen *codegen, ZigType *expecte...@@ -675,7 +675,7 @@ static bool types_have_same_zig_comptime_repr(CodeGen *codegen, ZigType *expecte
675 zig_unreachable();675 zig_unreachable();
676}676}
677677
678static void ir_inst_gen_append(IrBasicBlockGen *basic_block, IrInstGen *instruction) {678static void ir_inst_gen_append(Stage1AirBasicBlock *basic_block, Stage1AirInst *instruction) {
679 assert(basic_block);679 assert(basic_block);
680 assert(instruction);680 assert(instruction);
681 basic_block->instruction_list.append(instruction);681 basic_block->instruction_list.append(instruction);
...@@ -691,12 +691,12 @@ static bool value_is_comptime(ZigValue *const_val) {...@@ -691,12 +691,12 @@ static bool value_is_comptime(ZigValue *const_val) {
691 return const_val->special != ConstValSpecialRuntime;691 return const_val->special != ConstValSpecialRuntime;
692}692}
693693
694static bool instr_is_comptime(IrInstGen *instruction) {694static bool instr_is_comptime(Stage1AirInst *instruction) {
695 return value_is_comptime(instruction->value);695 return value_is_comptime(instruction->value);
696}696}
697697
698static void ir_ref_inst_gen(IrInstGen *instruction) {698static void ir_ref_inst_gen(Stage1AirInst *instruction) {
699 assert(instruction->id != IrInstGenIdInvalid);699 assert(instruction->id != Stage1AirInstIdInvalid);
700 instruction->ref_count += 1;700 instruction->ref_count += 1;
701}701}
702702
...@@ -739,374 +739,374 @@ ZigType *ir_analyze_type_expr(IrAnalyze *ira, Scope *scope, AstNode *node) {...@@ -739,374 +739,374 @@ ZigType *ir_analyze_type_expr(IrAnalyze *ira, Scope *scope, AstNode *node) {
739 return res_type;739 return res_type;
740}740}
741741
742static IrBasicBlockGen *ir_create_basic_block_gen(IrAnalyze *ira, Scope *scope, const char *name_hint) {742static Stage1AirBasicBlock *ir_create_basic_block_gen(IrAnalyze *ira, Scope *scope, const char *name_hint) {
743 IrBasicBlockGen *result = heap::c_allocator.create<IrBasicBlockGen>();743 Stage1AirBasicBlock *result = heap::c_allocator.create<Stage1AirBasicBlock>();
744 result->scope = scope;744 result->scope = scope;
745 result->name_hint = name_hint;745 result->name_hint = name_hint;
746 result->debug_id = exec_next_debug_id_gen(ira->new_irb.exec);746 result->debug_id = exec_next_debug_id_gen(ira->new_irb.exec);
747 return result;747 return result;
748}748}
749749
750static IrBasicBlockGen *ir_build_bb_from(IrAnalyze *ira, Stage1ZirBasicBlock *other_bb) {750static Stage1AirBasicBlock *ir_build_bb_from(IrAnalyze *ira, Stage1ZirBasicBlock *other_bb) {
751 IrBasicBlockGen *new_bb = ir_create_basic_block_gen(ira, other_bb->scope, other_bb->name_hint);751 Stage1AirBasicBlock *new_bb = ir_create_basic_block_gen(ira, other_bb->scope, other_bb->name_hint);
752 other_bb->child = new_bb;752 other_bb->child = new_bb;
753 return new_bb;753 return new_bb;
754}754}
755755
756static constexpr IrInstGenId ir_inst_id(IrInstGenDeclVar *) {756static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstDeclVar *) {
757 return IrInstGenIdDeclVar;757 return Stage1AirInstIdDeclVar;
758}758}
759759
760static constexpr IrInstGenId ir_inst_id(IrInstGenBr *) {760static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBr *) {
761 return IrInstGenIdBr;761 return Stage1AirInstIdBr;
762}762}
763763
764static constexpr IrInstGenId ir_inst_id(IrInstGenCondBr *) {764static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCondBr *) {
765 return IrInstGenIdCondBr;765 return Stage1AirInstIdCondBr;
766}766}
767767
768static constexpr IrInstGenId ir_inst_id(IrInstGenSwitchBr *) {768static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSwitchBr *) {
769 return IrInstGenIdSwitchBr;769 return Stage1AirInstIdSwitchBr;
770}770}
771771
772static constexpr IrInstGenId ir_inst_id(IrInstGenPhi *) {772static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPhi *) {
773 return IrInstGenIdPhi;773 return Stage1AirInstIdPhi;
774}774}
775775
776static constexpr IrInstGenId ir_inst_id(IrInstGenBinaryNot *) {776static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBinaryNot *) {
777 return IrInstGenIdBinaryNot;777 return Stage1AirInstIdBinaryNot;
778}778}
779779
780static constexpr IrInstGenId ir_inst_id(IrInstGenNegation *) {780static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstNegation *) {
781 return IrInstGenIdNegation;781 return Stage1AirInstIdNegation;
782}782}
783783
784static constexpr IrInstGenId ir_inst_id(IrInstGenBinOp *) {784static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBinOp *) {
785 return IrInstGenIdBinOp;785 return Stage1AirInstIdBinOp;
786}786}
787787
788static constexpr IrInstGenId ir_inst_id(IrInstGenLoadPtr *) {788static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstLoadPtr *) {
789 return IrInstGenIdLoadPtr;789 return Stage1AirInstIdLoadPtr;
790}790}
791791
792static constexpr IrInstGenId ir_inst_id(IrInstGenStorePtr *) {792static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstStorePtr *) {
793 return IrInstGenIdStorePtr;793 return Stage1AirInstIdStorePtr;
794}794}
795795
796static constexpr IrInstGenId ir_inst_id(IrInstGenVectorStoreElem *) {796static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVectorStoreElem *) {
797 return IrInstGenIdVectorStoreElem;797 return Stage1AirInstIdVectorStoreElem;
798}798}
799799
800static constexpr IrInstGenId ir_inst_id(IrInstGenStructFieldPtr *) {800static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstStructFieldPtr *) {
801 return IrInstGenIdStructFieldPtr;801 return Stage1AirInstIdStructFieldPtr;
802}802}
803803
804static constexpr IrInstGenId ir_inst_id(IrInstGenUnionFieldPtr *) {804static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnionFieldPtr *) {
805 return IrInstGenIdUnionFieldPtr;805 return Stage1AirInstIdUnionFieldPtr;
806}806}
807807
808static constexpr IrInstGenId ir_inst_id(IrInstGenElemPtr *) {808static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstElemPtr *) {
809 return IrInstGenIdElemPtr;809 return Stage1AirInstIdElemPtr;
810}810}
811811
812static constexpr IrInstGenId ir_inst_id(IrInstGenVarPtr *) {812static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVarPtr *) {
813 return IrInstGenIdVarPtr;813 return Stage1AirInstIdVarPtr;
814}814}
815815
816static constexpr IrInstGenId ir_inst_id(IrInstGenReturnPtr *) {816static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReturnPtr *) {
817 return IrInstGenIdReturnPtr;817 return Stage1AirInstIdReturnPtr;
818}818}
819819
820static constexpr IrInstGenId ir_inst_id(IrInstGenCall *) {820static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCall *) {
821 return IrInstGenIdCall;821 return Stage1AirInstIdCall;
822}822}
823823
824static constexpr IrInstGenId ir_inst_id(IrInstGenReturn *) {824static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReturn *) {
825 return IrInstGenIdReturn;825 return Stage1AirInstIdReturn;
826}826}
827827
828static constexpr IrInstGenId ir_inst_id(IrInstGenCast *) {828static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCast *) {
829 return IrInstGenIdCast;829 return Stage1AirInstIdCast;
830}830}
831831
832static constexpr IrInstGenId ir_inst_id(IrInstGenUnreachable *) {832static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnreachable *) {
833 return IrInstGenIdUnreachable;833 return Stage1AirInstIdUnreachable;
834}834}
835835
836static constexpr IrInstGenId ir_inst_id(IrInstGenAsm *) {836static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAsm *) {
837 return IrInstGenIdAsm;837 return Stage1AirInstIdAsm;
838}838}
839839
840static constexpr IrInstGenId ir_inst_id(IrInstGenTestNonNull *) {840static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTestNonNull *) {
841 return IrInstGenIdTestNonNull;841 return Stage1AirInstIdTestNonNull;
842}842}
843843
844static constexpr IrInstGenId ir_inst_id(IrInstGenOptionalUnwrapPtr *) {844static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstOptionalUnwrapPtr *) {
845 return IrInstGenIdOptionalUnwrapPtr;845 return Stage1AirInstIdOptionalUnwrapPtr;
846}846}
847847
848static constexpr IrInstGenId ir_inst_id(IrInstGenOptionalWrap *) {848static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstOptionalWrap *) {
849 return IrInstGenIdOptionalWrap;849 return Stage1AirInstIdOptionalWrap;
850}850}
851851
852static constexpr IrInstGenId ir_inst_id(IrInstGenUnionTag *) {852static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnionTag *) {
853 return IrInstGenIdUnionTag;853 return Stage1AirInstIdUnionTag;
854}854}
855855
856static constexpr IrInstGenId ir_inst_id(IrInstGenClz *) {856static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstClz *) {
857 return IrInstGenIdClz;857 return Stage1AirInstIdClz;
858}858}
859859
860static constexpr IrInstGenId ir_inst_id(IrInstGenCtz *) {860static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCtz *) {
861 return IrInstGenIdCtz;861 return Stage1AirInstIdCtz;
862}862}
863863
864static constexpr IrInstGenId ir_inst_id(IrInstGenPopCount *) {864static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPopCount *) {
865 return IrInstGenIdPopCount;865 return Stage1AirInstIdPopCount;
866}866}
867867
868static constexpr IrInstGenId ir_inst_id(IrInstGenBswap *) {868static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBswap *) {
869 return IrInstGenIdBswap;869 return Stage1AirInstIdBswap;
870}870}
871871
872static constexpr IrInstGenId ir_inst_id(IrInstGenBitReverse *) {872static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBitReverse *) {
873 return IrInstGenIdBitReverse;873 return Stage1AirInstIdBitReverse;
874}874}
875875
876static constexpr IrInstGenId ir_inst_id(IrInstGenRef *) {876static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstRef *) {
877 return IrInstGenIdRef;877 return Stage1AirInstIdRef;
878}878}
879879
880static constexpr IrInstGenId ir_inst_id(IrInstGenErrName *) {880static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrName *) {
881 return IrInstGenIdErrName;881 return Stage1AirInstIdErrName;
882}882}
883883
884static constexpr IrInstGenId ir_inst_id(IrInstGenCmpxchg *) {884static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCmpxchg *) {
885 return IrInstGenIdCmpxchg;885 return Stage1AirInstIdCmpxchg;
886}886}
887887
888static constexpr IrInstGenId ir_inst_id(IrInstGenFence *) {888static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFence *) {
889 return IrInstGenIdFence;889 return Stage1AirInstIdFence;
890}890}
891891
892static constexpr IrInstGenId ir_inst_id(IrInstGenReduce *) {892static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReduce *) {
893 return IrInstGenIdReduce;893 return Stage1AirInstIdReduce;
894}894}
895895
896static constexpr IrInstGenId ir_inst_id(IrInstGenTruncate *) {896static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTruncate *) {
897 return IrInstGenIdTruncate;897 return Stage1AirInstIdTruncate;
898}898}
899899
900static constexpr IrInstGenId ir_inst_id(IrInstGenShuffleVector *) {900static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstShuffleVector *) {
901 return IrInstGenIdShuffleVector;901 return Stage1AirInstIdShuffleVector;
902}902}
903903
904static constexpr IrInstGenId ir_inst_id(IrInstGenSplat *) {904static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSplat *) {
905 return IrInstGenIdSplat;905 return Stage1AirInstIdSplat;
906}906}
907907
908static constexpr IrInstGenId ir_inst_id(IrInstGenBoolNot *) {908static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBoolNot *) {
909 return IrInstGenIdBoolNot;909 return Stage1AirInstIdBoolNot;
910}910}
911911
912static constexpr IrInstGenId ir_inst_id(IrInstGenMemset *) {912static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstMemset *) {
913 return IrInstGenIdMemset;913 return Stage1AirInstIdMemset;
914}914}
915915
916static constexpr IrInstGenId ir_inst_id(IrInstGenMemcpy *) {916static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstMemcpy *) {
917 return IrInstGenIdMemcpy;917 return Stage1AirInstIdMemcpy;
918}918}
919919
920static constexpr IrInstGenId ir_inst_id(IrInstGenSlice *) {920static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSlice *) {
921 return IrInstGenIdSlice;921 return Stage1AirInstIdSlice;
922}922}
923923
924static constexpr IrInstGenId ir_inst_id(IrInstGenBreakpoint *) {924static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBreakpoint *) {
925 return IrInstGenIdBreakpoint;925 return Stage1AirInstIdBreakpoint;
926}926}
927927
928static constexpr IrInstGenId ir_inst_id(IrInstGenReturnAddress *) {928static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReturnAddress *) {
929 return IrInstGenIdReturnAddress;929 return Stage1AirInstIdReturnAddress;
930}930}
931931
932static constexpr IrInstGenId ir_inst_id(IrInstGenFrameAddress *) {932static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFrameAddress *) {
933 return IrInstGenIdFrameAddress;933 return Stage1AirInstIdFrameAddress;
934}934}
935935
936static constexpr IrInstGenId ir_inst_id(IrInstGenFrameHandle *) {936static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFrameHandle *) {
937 return IrInstGenIdFrameHandle;937 return Stage1AirInstIdFrameHandle;
938}938}
939939
940static constexpr IrInstGenId ir_inst_id(IrInstGenFrameSize *) {940static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFrameSize *) {
941 return IrInstGenIdFrameSize;941 return Stage1AirInstIdFrameSize;
942}942}
943943
944static constexpr IrInstGenId ir_inst_id(IrInstGenOverflowOp *) {944static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstOverflowOp *) {
945 return IrInstGenIdOverflowOp;945 return Stage1AirInstIdOverflowOp;
946}946}
947947
948static constexpr IrInstGenId ir_inst_id(IrInstGenTestErr *) {948static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTestErr *) {
949 return IrInstGenIdTestErr;949 return Stage1AirInstIdTestErr;
950}950}
951951
952static constexpr IrInstGenId ir_inst_id(IrInstGenMulAdd *) {952static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstMulAdd *) {
953 return IrInstGenIdMulAdd;953 return Stage1AirInstIdMulAdd;
954}954}
955955
956static constexpr IrInstGenId ir_inst_id(IrInstGenFloatOp *) {956static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFloatOp *) {
957 return IrInstGenIdFloatOp;957 return Stage1AirInstIdFloatOp;
958}958}
959959
960static constexpr IrInstGenId ir_inst_id(IrInstGenUnwrapErrCode *) {960static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnwrapErrCode *) {
961 return IrInstGenIdUnwrapErrCode;961 return Stage1AirInstIdUnwrapErrCode;
962}962}
963963
964static constexpr IrInstGenId ir_inst_id(IrInstGenUnwrapErrPayload *) {964static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnwrapErrPayload *) {
965 return IrInstGenIdUnwrapErrPayload;965 return Stage1AirInstIdUnwrapErrPayload;
966}966}
967967
968static constexpr IrInstGenId ir_inst_id(IrInstGenErrWrapCode *) {968static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrWrapCode *) {
969 return IrInstGenIdErrWrapCode;969 return Stage1AirInstIdErrWrapCode;
970}970}
971971
972static constexpr IrInstGenId ir_inst_id(IrInstGenErrWrapPayload *) {972static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrWrapPayload *) {
973 return IrInstGenIdErrWrapPayload;973 return Stage1AirInstIdErrWrapPayload;
974}974}
975975
976static constexpr IrInstGenId ir_inst_id(IrInstGenPtrCast *) {976static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPtrCast *) {
977 return IrInstGenIdPtrCast;977 return Stage1AirInstIdPtrCast;
978}978}
979979
980static constexpr IrInstGenId ir_inst_id(IrInstGenBitCast *) {980static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBitCast *) {
981 return IrInstGenIdBitCast;981 return Stage1AirInstIdBitCast;
982}982}
983983
984static constexpr IrInstGenId ir_inst_id(IrInstGenWidenOrShorten *) {984static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstWidenOrShorten *) {
985 return IrInstGenIdWidenOrShorten;985 return Stage1AirInstIdWidenOrShorten;
986}986}
987987
988static constexpr IrInstGenId ir_inst_id(IrInstGenIntToPtr *) {988static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstIntToPtr *) {
989 return IrInstGenIdIntToPtr;989 return Stage1AirInstIdIntToPtr;
990}990}
991991
992static constexpr IrInstGenId ir_inst_id(IrInstGenPtrToInt *) {992static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPtrToInt *) {
993 return IrInstGenIdPtrToInt;993 return Stage1AirInstIdPtrToInt;
994}994}
995995
996static constexpr IrInstGenId ir_inst_id(IrInstGenIntToEnum *) {996static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstIntToEnum *) {
997 return IrInstGenIdIntToEnum;997 return Stage1AirInstIdIntToEnum;
998}998}
999999
1000static constexpr IrInstGenId ir_inst_id(IrInstGenIntToErr *) {1000static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstIntToErr *) {
1001 return IrInstGenIdIntToErr;1001 return Stage1AirInstIdIntToErr;
1002}1002}
10031003
1004static constexpr IrInstGenId ir_inst_id(IrInstGenErrToInt *) {1004static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrToInt *) {
1005 return IrInstGenIdErrToInt;1005 return Stage1AirInstIdErrToInt;
1006}1006}
10071007
1008static constexpr IrInstGenId ir_inst_id(IrInstGenPanic *) {1008static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPanic *) {
1009 return IrInstGenIdPanic;1009 return Stage1AirInstIdPanic;
1010}1010}
10111011
1012static constexpr IrInstGenId ir_inst_id(IrInstGenTagName *) {1012static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTagName *) {
1013 return IrInstGenIdTagName;1013 return Stage1AirInstIdTagName;
1014}1014}
10151015
1016static constexpr IrInstGenId ir_inst_id(IrInstGenFieldParentPtr *) {1016static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFieldParentPtr *) {
1017 return IrInstGenIdFieldParentPtr;1017 return Stage1AirInstIdFieldParentPtr;
1018}1018}
10191019
1020static constexpr IrInstGenId ir_inst_id(IrInstGenAlignCast *) {1020static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAlignCast *) {
1021 return IrInstGenIdAlignCast;1021 return Stage1AirInstIdAlignCast;
1022}1022}
10231023
1024static constexpr IrInstGenId ir_inst_id(IrInstGenErrorReturnTrace *) {1024static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrorReturnTrace *) {
1025 return IrInstGenIdErrorReturnTrace;1025 return Stage1AirInstIdErrorReturnTrace;
1026}1026}
10271027
1028static constexpr IrInstGenId ir_inst_id(IrInstGenAtomicRmw *) {1028static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAtomicRmw *) {
1029 return IrInstGenIdAtomicRmw;1029 return Stage1AirInstIdAtomicRmw;
1030}1030}
10311031
1032static constexpr IrInstGenId ir_inst_id(IrInstGenAtomicLoad *) {1032static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAtomicLoad *) {
1033 return IrInstGenIdAtomicLoad;1033 return Stage1AirInstIdAtomicLoad;
1034}1034}
10351035
1036static constexpr IrInstGenId ir_inst_id(IrInstGenAtomicStore *) {1036static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAtomicStore *) {
1037 return IrInstGenIdAtomicStore;1037 return Stage1AirInstIdAtomicStore;
1038}1038}
10391039
1040static constexpr IrInstGenId ir_inst_id(IrInstGenSaveErrRetAddr *) {1040static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSaveErrRetAddr *) {
1041 return IrInstGenIdSaveErrRetAddr;1041 return Stage1AirInstIdSaveErrRetAddr;
1042}1042}
10431043
1044static constexpr IrInstGenId ir_inst_id(IrInstGenVectorToArray *) {1044static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVectorToArray *) {
1045 return IrInstGenIdVectorToArray;1045 return Stage1AirInstIdVectorToArray;
1046}1046}
10471047
1048static constexpr IrInstGenId ir_inst_id(IrInstGenArrayToVector *) {1048static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstArrayToVector *) {
1049 return IrInstGenIdArrayToVector;1049 return Stage1AirInstIdArrayToVector;
1050}1050}
10511051
1052static constexpr IrInstGenId ir_inst_id(IrInstGenAssertZero *) {1052static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAssertZero *) {
1053 return IrInstGenIdAssertZero;1053 return Stage1AirInstIdAssertZero;
1054}1054}
10551055
1056static constexpr IrInstGenId ir_inst_id(IrInstGenAssertNonNull *) {1056static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAssertNonNull *) {
1057 return IrInstGenIdAssertNonNull;1057 return Stage1AirInstIdAssertNonNull;
1058}1058}
10591059
1060static constexpr IrInstGenId ir_inst_id(IrInstGenPtrOfArrayToSlice *) {1060static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPtrOfArrayToSlice *) {
1061 return IrInstGenIdPtrOfArrayToSlice;1061 return Stage1AirInstIdPtrOfArrayToSlice;
1062}1062}
10631063
1064static constexpr IrInstGenId ir_inst_id(IrInstGenSuspendBegin *) {1064static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSuspendBegin *) {
1065 return IrInstGenIdSuspendBegin;1065 return Stage1AirInstIdSuspendBegin;
1066}1066}
10671067
1068static constexpr IrInstGenId ir_inst_id(IrInstGenSuspendFinish *) {1068static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSuspendFinish *) {
1069 return IrInstGenIdSuspendFinish;1069 return Stage1AirInstIdSuspendFinish;
1070}1070}
10711071
1072static constexpr IrInstGenId ir_inst_id(IrInstGenAwait *) {1072static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAwait *) {
1073 return IrInstGenIdAwait;1073 return Stage1AirInstIdAwait;
1074}1074}
10751075
1076static constexpr IrInstGenId ir_inst_id(IrInstGenResume *) {1076static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstResume *) {
1077 return IrInstGenIdResume;1077 return Stage1AirInstIdResume;
1078}1078}
10791079
1080static constexpr IrInstGenId ir_inst_id(IrInstGenSpillBegin *) {1080static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSpillBegin *) {
1081 return IrInstGenIdSpillBegin;1081 return Stage1AirInstIdSpillBegin;
1082}1082}
10831083
1084static constexpr IrInstGenId ir_inst_id(IrInstGenSpillEnd *) {1084static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSpillEnd *) {
1085 return IrInstGenIdSpillEnd;1085 return Stage1AirInstIdSpillEnd;
1086}1086}
10871087
1088static constexpr IrInstGenId ir_inst_id(IrInstGenVectorExtractElem *) {1088static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVectorExtractElem *) {
1089 return IrInstGenIdVectorExtractElem;1089 return Stage1AirInstIdVectorExtractElem;
1090}1090}
10911091
1092static constexpr IrInstGenId ir_inst_id(IrInstGenAlloca *) {1092static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAlloca *) {
1093 return IrInstGenIdAlloca;1093 return Stage1AirInstIdAlloca;
1094}1094}
10951095
1096static constexpr IrInstGenId ir_inst_id(IrInstGenConst *) {1096static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstConst *) {
1097 return IrInstGenIdConst;1097 return Stage1AirInstIdConst;
1098}1098}
10991099
1100static constexpr IrInstGenId ir_inst_id(IrInstGenWasmMemorySize *) {1100static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstWasmMemorySize *) {
1101 return IrInstGenIdWasmMemorySize;1101 return Stage1AirInstIdWasmMemorySize;
1102}1102}
11031103
1104static constexpr IrInstGenId ir_inst_id(IrInstGenWasmMemoryGrow *) {1104static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstWasmMemoryGrow *) {
1105 return IrInstGenIdWasmMemoryGrow;1105 return Stage1AirInstIdWasmMemoryGrow;
1106}1106}
11071107
1108static constexpr IrInstGenId ir_inst_id(IrInstGenExtern *) {1108static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstExtern *) {
1109 return IrInstGenIdExtern;1109 return Stage1AirInstIdExtern;
1110}1110}
11111111
1112template<typename T>1112template<typename T>
...@@ -1155,11 +1155,11 @@ static T *ir_build_inst_void(IrBuilderGen *irb, Scope *scope, AstNode *source_no...@@ -1155,11 +1155,11 @@ static T *ir_build_inst_void(IrBuilderGen *irb, Scope *scope, AstNode *source_no
1155 return special_instruction;1155 return special_instruction;
1156}1156}
11571157
1158IrInstGen *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn,1158Stage1AirInst *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn,
1159 ZigType *var_type, const char *name_hint)1159 ZigType *var_type, const char *name_hint)
1160{1160{
1161 IrInstGenAlloca *alloca_gen = heap::c_allocator.create<IrInstGenAlloca>();1161 Stage1AirInstAlloca *alloca_gen = heap::c_allocator.create<Stage1AirInstAlloca>();
1162 alloca_gen->base.id = IrInstGenIdAlloca;1162 alloca_gen->base.id = Stage1AirInstIdAlloca;
1163 alloca_gen->base.source_node = source_node;1163 alloca_gen->base.source_node = source_node;
1164 alloca_gen->base.scope = scope;1164 alloca_gen->base.scope = scope;
1165 alloca_gen->base.value = g->pass1_arena->create<ZigValue>();1165 alloca_gen->base.value = g->pass1_arena->create<ZigValue>();
...@@ -1170,10 +1170,10 @@ IrInstGen *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigF...@@ -1170,10 +1170,10 @@ IrInstGen *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigF
1170 return &alloca_gen->base;1170 return &alloca_gen->base;
1171}1171}
11721172
1173static IrInstGen *ir_build_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,1173static Stage1AirInst *ir_build_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1174 ZigType *dest_type, IrInstGen *value, CastOp cast_op)1174 ZigType *dest_type, Stage1AirInst *value, CastOp cast_op)
1175{1175{
1176 IrInstGenCast *inst = ir_build_inst_gen<IrInstGenCast>(&ira->new_irb, scope, source_node);1176 Stage1AirInstCast *inst = ir_build_inst_gen<Stage1AirInstCast>(&ira->new_irb, scope, source_node);
1177 inst->base.value->type = dest_type;1177 inst->base.value->type = dest_type;
1178 inst->value = value;1178 inst->value = value;
1179 inst->cast_op = cast_op;1179 inst->cast_op = cast_op;
...@@ -1183,10 +1183,10 @@ static IrInstGen *ir_build_cast(IrAnalyze *ira, Scope *scope, AstNode *source_no...@@ -1183,10 +1183,10 @@ static IrInstGen *ir_build_cast(IrAnalyze *ira, Scope *scope, AstNode *source_no
1183 return &inst->base;1183 return &inst->base;
1184}1184}
11851185
1186static IrInstGen *ir_build_cond_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *condition,1186static Stage1AirInst *ir_build_cond_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *condition,
1187 IrBasicBlockGen *then_block, IrBasicBlockGen *else_block)1187 Stage1AirBasicBlock *then_block, Stage1AirBasicBlock *else_block)
1188{1188{
1189 IrInstGenCondBr *inst = ir_build_inst_noreturn<IrInstGenCondBr>(&ira->new_irb, scope, source_node);1189 Stage1AirInstCondBr *inst = ir_build_inst_noreturn<Stage1AirInstCondBr>(&ira->new_irb, scope, source_node);
1190 inst->condition = condition;1190 inst->condition = condition;
1191 inst->then_block = then_block;1191 inst->then_block = then_block;
1192 inst->else_block = else_block;1192 inst->else_block = else_block;
...@@ -1196,8 +1196,8 @@ static IrInstGen *ir_build_cond_br_gen(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -1196,8 +1196,8 @@ static IrInstGen *ir_build_cond_br_gen(IrAnalyze *ira, Scope *scope, AstNode *so
1196 return &inst->base;1196 return &inst->base;
1197}1197}
11981198
1199static IrInstGen *ir_build_return_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand) {1199static Stage1AirInst *ir_build_return_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand) {
1200 IrInstGenReturn *inst = ir_build_inst_noreturn<IrInstGenReturn>(&ira->new_irb, scope, source_node);1200 Stage1AirInstReturn *inst = ir_build_inst_noreturn<Stage1AirInstReturn>(&ira->new_irb, scope, source_node);
1201 inst->operand = operand;1201 inst->operand = operand;
12021202
1203 if (operand != nullptr) ir_ref_inst_gen(operand);1203 if (operand != nullptr) ir_ref_inst_gen(operand);
...@@ -1205,10 +1205,10 @@ static IrInstGen *ir_build_return_gen(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -1205,10 +1205,10 @@ static IrInstGen *ir_build_return_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
1205 return &inst->base;1205 return &inst->base;
1206}1206}
12071207
1208static IrInstGen *ir_build_bin_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *res_type,1208static Stage1AirInst *ir_build_bin_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *res_type,
1209 IrBinOp op_id, IrInstGen *op1, IrInstGen *op2, bool safety_check_on)1209 IrBinOp op_id, Stage1AirInst *op1, Stage1AirInst *op2, bool safety_check_on)
1210{1210{
1211 IrInstGenBinOp *inst = ir_build_inst_gen<IrInstGenBinOp>(&ira->new_irb,1211 Stage1AirInstBinOp *inst = ir_build_inst_gen<Stage1AirInstBinOp>(&ira->new_irb,
1212 scope, source_node);1212 scope, source_node);
1213 inst->base.value->type = res_type;1213 inst->base.value->type = res_type;
1214 inst->op_id = op_id;1214 inst->op_id = op_id;
...@@ -1223,8 +1223,8 @@ static IrInstGen *ir_build_bin_op_gen(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -1223,8 +1223,8 @@ static IrInstGen *ir_build_bin_op_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
1223}1223}
12241224
12251225
1226static IrInstGen *ir_build_var_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) {1226static Stage1AirInst *ir_build_var_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) {
1227 IrInstGenVarPtr *instruction = ir_build_inst_gen<IrInstGenVarPtr>(&ira->new_irb, scope, source_node);1227 Stage1AirInstVarPtr *instruction = ir_build_inst_gen<Stage1AirInstVarPtr>(&ira->new_irb, scope, source_node);
1228 instruction->var = var;1228 instruction->var = var;
12291229
1230 var->ref_count += 1;1230 var->ref_count += 1;
...@@ -1232,16 +1232,16 @@ static IrInstGen *ir_build_var_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -1232,16 +1232,16 @@ static IrInstGen *ir_build_var_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *so
1232 return &instruction->base;1232 return &instruction->base;
1233}1233}
12341234
1235static IrInstGen *ir_build_return_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {1235static Stage1AirInst *ir_build_return_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
1236 IrInstGenReturnPtr *instruction = ir_build_inst_gen<IrInstGenReturnPtr>(&ira->new_irb, scope, source_node);1236 Stage1AirInstReturnPtr *instruction = ir_build_inst_gen<Stage1AirInstReturnPtr>(&ira->new_irb, scope, source_node);
1237 instruction->base.value->type = ty;1237 instruction->base.value->type = ty;
1238 return &instruction->base;1238 return &instruction->base;
1239}1239}
12401240
1241static IrInstGen *ir_build_elem_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1241static Stage1AirInst *ir_build_elem_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1242 IrInstGen *array_ptr, IrInstGen *elem_index, bool safety_check_on, ZigType *return_type)1242 Stage1AirInst *array_ptr, Stage1AirInst *elem_index, bool safety_check_on, ZigType *return_type)
1243{1243{
1244 IrInstGenElemPtr *instruction = ir_build_inst_gen<IrInstGenElemPtr>(&ira->new_irb, scope, source_node);1244 Stage1AirInstElemPtr *instruction = ir_build_inst_gen<Stage1AirInstElemPtr>(&ira->new_irb, scope, source_node);
1245 instruction->base.value->type = return_type;1245 instruction->base.value->type = return_type;
1246 instruction->array_ptr = array_ptr;1246 instruction->array_ptr = array_ptr;
1247 instruction->elem_index = elem_index;1247 instruction->elem_index = elem_index;
...@@ -1253,10 +1253,10 @@ static IrInstGen *ir_build_elem_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -1253,10 +1253,10 @@ static IrInstGen *ir_build_elem_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *s
1253 return &instruction->base;1253 return &instruction->base;
1254}1254}
12551255
1256static IrInstGen *ir_build_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,1256static Stage1AirInst *ir_build_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1257 IrInstGen *struct_ptr, TypeStructField *field, ZigType *ptr_type)1257 Stage1AirInst *struct_ptr, TypeStructField *field, ZigType *ptr_type)
1258{1258{
1259 IrInstGenStructFieldPtr *inst = ir_build_inst_gen<IrInstGenStructFieldPtr>(&ira->new_irb, scope, source_node);1259 Stage1AirInstStructFieldPtr *inst = ir_build_inst_gen<Stage1AirInstStructFieldPtr>(&ira->new_irb, scope, source_node);
1260 inst->base.value->type = ptr_type;1260 inst->base.value->type = ptr_type;
1261 inst->struct_ptr = struct_ptr;1261 inst->struct_ptr = struct_ptr;
1262 inst->field = field;1262 inst->field = field;
...@@ -1266,10 +1266,10 @@ static IrInstGen *ir_build_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNod...@@ -1266,10 +1266,10 @@ static IrInstGen *ir_build_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNod
1266 return &inst->base;1266 return &inst->base;
1267}1267}
12681268
1269static IrInstGen *ir_build_union_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,1269static Stage1AirInst *ir_build_union_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1270 IrInstGen *union_ptr, TypeUnionField *field, bool safety_check_on, bool initializing, ZigType *ptr_type)1270 Stage1AirInst *union_ptr, TypeUnionField *field, bool safety_check_on, bool initializing, ZigType *ptr_type)
1271{1271{
1272 IrInstGenUnionFieldPtr *inst = ir_build_inst_gen<IrInstGenUnionFieldPtr>(&ira->new_irb,1272 Stage1AirInstUnionFieldPtr *inst = ir_build_inst_gen<Stage1AirInstUnionFieldPtr>(&ira->new_irb,
1273 scope, source_node);1273 scope, source_node);
1274 inst->base.value->type = ptr_type;1274 inst->base.value->type = ptr_type;
1275 inst->initializing = initializing;1275 inst->initializing = initializing;
...@@ -1282,12 +1282,12 @@ static IrInstGen *ir_build_union_field_ptr(IrAnalyze *ira, Scope *scope, AstNode...@@ -1282,12 +1282,12 @@ static IrInstGen *ir_build_union_field_ptr(IrAnalyze *ira, Scope *scope, AstNode
1282 return &inst->base;1282 return &inst->base;
1283}1283}
12841284
1285static IrInstGenCall *ir_build_call_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1285static Stage1AirInstCall *ir_build_call_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1286 ZigFn *fn_entry, IrInstGen *fn_ref, size_t arg_count, IrInstGen **args,1286 ZigFn *fn_entry, Stage1AirInst *fn_ref, size_t arg_count, Stage1AirInst **args,
1287 CallModifier modifier, IrInstGen *new_stack, bool is_async_call_builtin,1287 CallModifier modifier, Stage1AirInst *new_stack, bool is_async_call_builtin,
1288 IrInstGen *result_loc, ZigType *return_type)1288 Stage1AirInst *result_loc, ZigType *return_type)
1289{1289{
1290 IrInstGenCall *call_instruction = ir_build_inst_gen<IrInstGenCall>(&ira->new_irb,1290 Stage1AirInstCall *call_instruction = ir_build_inst_gen<Stage1AirInstCall>(&ira->new_irb,
1291 scope, source_node);1291 scope, source_node);
1292 call_instruction->base.value->type = return_type;1292 call_instruction->base.value->type = return_type;
1293 call_instruction->fn_entry = fn_entry;1293 call_instruction->fn_entry = fn_entry;
...@@ -1308,13 +1308,13 @@ static IrInstGenCall *ir_build_call_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -1308,13 +1308,13 @@ static IrInstGenCall *ir_build_call_gen(IrAnalyze *ira, Scope *scope, AstNode *s
1308 return call_instruction;1308 return call_instruction;
1309}1309}
13101310
1311static IrInstGen *ir_build_phi_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, size_t incoming_count,1311static Stage1AirInst *ir_build_phi_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, size_t incoming_count,
1312 IrBasicBlockGen **incoming_blocks, IrInstGen **incoming_values, ZigType *result_type)1312 Stage1AirBasicBlock **incoming_blocks, Stage1AirInst **incoming_values, ZigType *result_type)
1313{1313{
1314 assert(incoming_count != 0);1314 assert(incoming_count != 0);
1315 assert(incoming_count != SIZE_MAX);1315 assert(incoming_count != SIZE_MAX);
13161316
1317 IrInstGenPhi *phi_instruction = ir_build_inst_gen<IrInstGenPhi>(&ira->new_irb,1317 Stage1AirInstPhi *phi_instruction = ir_build_inst_gen<Stage1AirInstPhi>(&ira->new_irb,
1318 scope, source_node);1318 scope, source_node);
1319 phi_instruction->base.value->type = result_type;1319 phi_instruction->base.value->type = result_type;
1320 phi_instruction->incoming_count = incoming_count;1320 phi_instruction->incoming_count = incoming_count;
...@@ -1328,15 +1328,15 @@ static IrInstGen *ir_build_phi_gen(IrAnalyze *ira, Scope *scope, AstNode *source...@@ -1328,15 +1328,15 @@ static IrInstGen *ir_build_phi_gen(IrAnalyze *ira, Scope *scope, AstNode *source
1328 return &phi_instruction->base;1328 return &phi_instruction->base;
1329}1329}
13301330
1331static IrInstGen *ir_build_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrBasicBlockGen *dest_block) {1331static Stage1AirInst *ir_build_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirBasicBlock *dest_block) {
1332 IrInstGenBr *inst = ir_build_inst_noreturn<IrInstGenBr>(&ira->new_irb, scope, source_node);1332 Stage1AirInstBr *inst = ir_build_inst_noreturn<Stage1AirInstBr>(&ira->new_irb, scope, source_node);
1333 inst->dest_block = dest_block;1333 inst->dest_block = dest_block;
13341334
1335 return &inst->base;1335 return &inst->base;
1336}1336}
13371337
1338static IrInstGen *ir_build_negation(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand, ZigType *expr_type, bool wrapping) {1338static Stage1AirInst *ir_build_negation(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand, ZigType *expr_type, bool wrapping) {
1339 IrInstGenNegation *instruction = ir_build_inst_gen<IrInstGenNegation>(&ira->new_irb,1339 Stage1AirInstNegation *instruction = ir_build_inst_gen<Stage1AirInstNegation>(&ira->new_irb,
1340 scope, source_node);1340 scope, source_node);
1341 instruction->base.value->type = expr_type;1341 instruction->base.value->type = expr_type;
1342 instruction->operand = operand;1342 instruction->operand = operand;
...@@ -1347,10 +1347,10 @@ static IrInstGen *ir_build_negation(IrAnalyze *ira, Scope *scope, AstNode *sourc...@@ -1347,10 +1347,10 @@ static IrInstGen *ir_build_negation(IrAnalyze *ira, Scope *scope, AstNode *sourc
1347 return &instruction->base;1347 return &instruction->base;
1348}1348}
13491349
1350static IrInstGen *ir_build_binary_not(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand,1350static Stage1AirInst *ir_build_binary_not(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand,
1351 ZigType *expr_type)1351 ZigType *expr_type)
1352{1352{
1353 IrInstGenBinaryNot *instruction = ir_build_inst_gen<IrInstGenBinaryNot>(&ira->new_irb,1353 Stage1AirInstBinaryNot *instruction = ir_build_inst_gen<Stage1AirInstBinaryNot>(&ira->new_irb,
1354 scope, source_node);1354 scope, source_node);
1355 instruction->base.value->type = expr_type;1355 instruction->base.value->type = expr_type;
1356 instruction->operand = operand;1356 instruction->operand = operand;
...@@ -1360,13 +1360,13 @@ static IrInstGen *ir_build_binary_not(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -1360,13 +1360,13 @@ static IrInstGen *ir_build_binary_not(IrAnalyze *ira, Scope *scope, AstNode *sou
1360 return &instruction->base;1360 return &instruction->base;
1361}1361}
13621362
1363static IrInstGen *ir_build_unreachable_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {1363static Stage1AirInst *ir_build_unreachable_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1364 IrInstGenUnreachable *inst = ir_build_inst_noreturn<IrInstGenUnreachable>(&ira->new_irb, scope, source_node);1364 Stage1AirInstUnreachable *inst = ir_build_inst_noreturn<Stage1AirInstUnreachable>(&ira->new_irb, scope, source_node);
1365 return &inst->base;1365 return &inst->base;
1366}1366}
13671367
1368static IrInstGen *ir_build_store_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *ptr, IrInstGen *value) {1368static Stage1AirInst *ir_build_store_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *ptr, Stage1AirInst *value) {
1369 IrInstGenStorePtr *instruction = ir_build_inst_void<IrInstGenStorePtr>(&ira->new_irb,1369 Stage1AirInstStorePtr *instruction = ir_build_inst_void<Stage1AirInstStorePtr>(&ira->new_irb,
1370 scope, source_node);1370 scope, source_node);
1371 instruction->ptr = ptr;1371 instruction->ptr = ptr;
1372 instruction->value = value;1372 instruction->value = value;
...@@ -1377,10 +1377,10 @@ static IrInstGen *ir_build_store_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *...@@ -1377,10 +1377,10 @@ static IrInstGen *ir_build_store_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *
1377 return &instruction->base;1377 return &instruction->base;
1378}1378}
13791379
1380static IrInstGen *ir_build_vector_store_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node,1380static Stage1AirInst *ir_build_vector_store_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1381 IrInstGen *vector_ptr, IrInstGen *index, IrInstGen *value)1381 Stage1AirInst *vector_ptr, Stage1AirInst *index, Stage1AirInst *value)
1382{1382{
1383 IrInstGenVectorStoreElem *inst = ir_build_inst_void<IrInstGenVectorStoreElem>(1383 Stage1AirInstVectorStoreElem *inst = ir_build_inst_void<Stage1AirInstVectorStoreElem>(
1384 &ira->new_irb, scope, source_node);1384 &ira->new_irb, scope, source_node);
1385 inst->vector_ptr = vector_ptr;1385 inst->vector_ptr = vector_ptr;
1386 inst->index = index;1386 inst->index = index;
...@@ -1393,10 +1393,10 @@ static IrInstGen *ir_build_vector_store_elem(IrAnalyze *ira, Scope *scope, AstNo...@@ -1393,10 +1393,10 @@ static IrInstGen *ir_build_vector_store_elem(IrAnalyze *ira, Scope *scope, AstNo
1393 return &inst->base;1393 return &inst->base;
1394}1394}
13951395
1396static IrInstGen *ir_build_var_decl_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1396static Stage1AirInst *ir_build_var_decl_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1397 ZigVar *var, IrInstGen *var_ptr)1397 ZigVar *var, Stage1AirInst *var_ptr)
1398{1398{
1399 IrInstGenDeclVar *inst = ir_build_inst_gen<IrInstGenDeclVar>(&ira->new_irb,1399 Stage1AirInstDeclVar *inst = ir_build_inst_gen<Stage1AirInstDeclVar>(&ira->new_irb,
1400 scope, source_node);1400 scope, source_node);
1401 inst->base.value->special = ConstValSpecialStatic;1401 inst->base.value->special = ConstValSpecialStatic;
1402 inst->base.value->type = ira->codegen->builtin_types.entry_void;1402 inst->base.value->type = ira->codegen->builtin_types.entry_void;
...@@ -1408,10 +1408,10 @@ static IrInstGen *ir_build_var_decl_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -1408,10 +1408,10 @@ static IrInstGen *ir_build_var_decl_gen(IrAnalyze *ira, Scope *scope, AstNode *s
1408 return &inst->base;1408 return &inst->base;
1409}1409}
14101410
1411static IrInstGen *ir_build_extern_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Buf *name,1411static Stage1AirInst *ir_build_extern_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Buf *name,
1412 GlobalLinkageId linkage, bool is_thread_local, ZigType *expr_type)1412 GlobalLinkageId linkage, bool is_thread_local, ZigType *expr_type)
1413{1413{
1414 IrInstGenExtern *instruction = ir_build_inst_gen<IrInstGenExtern>(&ira->new_irb,1414 Stage1AirInstExtern *instruction = ir_build_inst_gen<Stage1AirInstExtern>(&ira->new_irb,
1415 scope, source_node);1415 scope, source_node);
1416 instruction->base.value->type = expr_type;1416 instruction->base.value->type = expr_type;
1417 instruction->name = name;1417 instruction->name = name;
...@@ -1421,10 +1421,10 @@ static IrInstGen *ir_build_extern_gen(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -1421,10 +1421,10 @@ static IrInstGen *ir_build_extern_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
1421 return &instruction->base;1421 return &instruction->base;
1422}1422}
14231423
1424static IrInstGen *ir_build_load_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1424static Stage1AirInst *ir_build_load_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1425 IrInstGen *ptr, ZigType *ty, IrInstGen *result_loc)1425 Stage1AirInst *ptr, ZigType *ty, Stage1AirInst *result_loc)
1426{1426{
1427 IrInstGenLoadPtr *instruction = ir_build_inst_gen<IrInstGenLoadPtr>(1427 Stage1AirInstLoadPtr *instruction = ir_build_inst_gen<Stage1AirInstLoadPtr>(
1428 &ira->new_irb, scope, source_node);1428 &ira->new_irb, scope, source_node);
1429 instruction->base.value->type = ty;1429 instruction->base.value->type = ty;
1430 instruction->ptr = ptr;1430 instruction->ptr = ptr;
...@@ -1436,12 +1436,12 @@ static IrInstGen *ir_build_load_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -1436,12 +1436,12 @@ static IrInstGen *ir_build_load_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *s
1436 return &instruction->base;1436 return &instruction->base;
1437}1437}
14381438
1439static IrInstGen *ir_build_asm_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1439static Stage1AirInst *ir_build_asm_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1440 Buf *asm_template, AsmToken *token_list, size_t token_list_len,1440 Buf *asm_template, AsmToken *token_list, size_t token_list_len,
1441 IrInstGen **input_list, IrInstGen **output_types, ZigVar **output_vars, size_t return_count,1441 Stage1AirInst **input_list, Stage1AirInst **output_types, ZigVar **output_vars, size_t return_count,
1442 bool has_side_effects, ZigType *return_type)1442 bool has_side_effects, ZigType *return_type)
1443{1443{
1444 IrInstGenAsm *instruction = ir_build_inst_gen<IrInstGenAsm>(&ira->new_irb, scope, source_node);1444 Stage1AirInstAsm *instruction = ir_build_inst_gen<Stage1AirInstAsm>(&ira->new_irb, scope, source_node);
1445 instruction->base.value->type = return_type;1445 instruction->base.value->type = return_type;
1446 instruction->asm_template = asm_template;1446 instruction->asm_template = asm_template;
1447 instruction->token_list = token_list;1447 instruction->token_list = token_list;
...@@ -1454,20 +1454,20 @@ static IrInstGen *ir_build_asm_gen(IrAnalyze *ira, Scope *scope, AstNode *source...@@ -1454,20 +1454,20 @@ static IrInstGen *ir_build_asm_gen(IrAnalyze *ira, Scope *scope, AstNode *source
14541454
1455 assert(source_node->type == NodeTypeAsmExpr);1455 assert(source_node->type == NodeTypeAsmExpr);
1456 for (size_t i = 0; i < source_node->data.asm_expr.output_list.length; i += 1) {1456 for (size_t i = 0; i < source_node->data.asm_expr.output_list.length; i += 1) {
1457 IrInstGen *output_type = output_types[i];1457 Stage1AirInst *output_type = output_types[i];
1458 if (output_type) ir_ref_inst_gen(output_type);1458 if (output_type) ir_ref_inst_gen(output_type);
1459 }1459 }
14601460
1461 for (size_t i = 0; i < source_node->data.asm_expr.input_list.length; i += 1) {1461 for (size_t i = 0; i < source_node->data.asm_expr.input_list.length; i += 1) {
1462 IrInstGen *input_value = input_list[i];1462 Stage1AirInst *input_value = input_list[i];
1463 ir_ref_inst_gen(input_value);1463 ir_ref_inst_gen(input_value);
1464 }1464 }
14651465
1466 return &instruction->base;1466 return &instruction->base;
1467}1467}
14681468
1469static IrInstGen *ir_build_test_non_null_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) {1469static Stage1AirInst *ir_build_test_non_null_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) {
1470 IrInstGenTestNonNull *inst = ir_build_inst_gen<IrInstGenTestNonNull>(&ira->new_irb,1470 Stage1AirInstTestNonNull *inst = ir_build_inst_gen<Stage1AirInstTestNonNull>(&ira->new_irb,
1471 scope, source_node);1471 scope, source_node);
1472 inst->base.value->type = ira->codegen->builtin_types.entry_bool;1472 inst->base.value->type = ira->codegen->builtin_types.entry_bool;
1473 inst->value = value;1473 inst->value = value;
...@@ -1477,10 +1477,10 @@ static IrInstGen *ir_build_test_non_null_gen(IrAnalyze *ira, Scope *scope, AstNo...@@ -1477,10 +1477,10 @@ static IrInstGen *ir_build_test_non_null_gen(IrAnalyze *ira, Scope *scope, AstNo
1477 return &inst->base;1477 return &inst->base;
1478}1478}
14791479
1480static IrInstGen *ir_build_optional_unwrap_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1480static Stage1AirInst *ir_build_optional_unwrap_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1481 IrInstGen *base_ptr, bool safety_check_on, bool initializing, ZigType *result_type)1481 Stage1AirInst *base_ptr, bool safety_check_on, bool initializing, ZigType *result_type)
1482{1482{
1483 IrInstGenOptionalUnwrapPtr *inst = ir_build_inst_gen<IrInstGenOptionalUnwrapPtr>(&ira->new_irb,1483 Stage1AirInstOptionalUnwrapPtr *inst = ir_build_inst_gen<Stage1AirInstOptionalUnwrapPtr>(&ira->new_irb,
1484 scope, source_node);1484 scope, source_node);
1485 inst->base.value->type = result_type;1485 inst->base.value->type = result_type;
1486 inst->base_ptr = base_ptr;1486 inst->base_ptr = base_ptr;
...@@ -1492,10 +1492,10 @@ static IrInstGen *ir_build_optional_unwrap_ptr_gen(IrAnalyze *ira, Scope *scope,...@@ -1492,10 +1492,10 @@ static IrInstGen *ir_build_optional_unwrap_ptr_gen(IrAnalyze *ira, Scope *scope,
1492 return &inst->base;1492 return &inst->base;
1493}1493}
14941494
1495static IrInstGen *ir_build_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_ty,1495static Stage1AirInst *ir_build_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_ty,
1496 IrInstGen *operand, IrInstGen *result_loc)1496 Stage1AirInst *operand, Stage1AirInst *result_loc)
1497{1497{
1498 IrInstGenOptionalWrap *instruction = ir_build_inst_gen<IrInstGenOptionalWrap>(1498 Stage1AirInstOptionalWrap *instruction = ir_build_inst_gen<Stage1AirInstOptionalWrap>(
1499 &ira->new_irb, scope, source_node);1499 &ira->new_irb, scope, source_node);
1500 instruction->base.value->type = result_ty;1500 instruction->base.value->type = result_ty;
1501 instruction->operand = operand;1501 instruction->operand = operand;
...@@ -1507,10 +1507,10 @@ static IrInstGen *ir_build_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *...@@ -1507,10 +1507,10 @@ static IrInstGen *ir_build_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *
1507 return &instruction->base;1507 return &instruction->base;
1508}1508}
15091509
1510static IrInstGen *ir_build_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,1510static Stage1AirInst *ir_build_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1511 ZigType *result_type, IrInstGen *operand, IrInstGen *result_loc)1511 ZigType *result_type, Stage1AirInst *operand, Stage1AirInst *result_loc)
1512{1512{
1513 IrInstGenErrWrapPayload *instruction = ir_build_inst_gen<IrInstGenErrWrapPayload>(1513 Stage1AirInstErrWrapPayload *instruction = ir_build_inst_gen<Stage1AirInstErrWrapPayload>(
1514 &ira->new_irb, scope, source_node);1514 &ira->new_irb, scope, source_node);
1515 instruction->base.value->type = result_type;1515 instruction->base.value->type = result_type;
1516 instruction->operand = operand;1516 instruction->operand = operand;
...@@ -1522,10 +1522,10 @@ static IrInstGen *ir_build_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNod...@@ -1522,10 +1522,10 @@ static IrInstGen *ir_build_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNod
1522 return &instruction->base;1522 return &instruction->base;
1523}1523}
15241524
1525static IrInstGen *ir_build_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,1525static Stage1AirInst *ir_build_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1526 ZigType *result_type, IrInstGen *operand, IrInstGen *result_loc)1526 ZigType *result_type, Stage1AirInst *operand, Stage1AirInst *result_loc)
1527{1527{
1528 IrInstGenErrWrapCode *instruction = ir_build_inst_gen<IrInstGenErrWrapCode>(1528 Stage1AirInstErrWrapCode *instruction = ir_build_inst_gen<Stage1AirInstErrWrapCode>(
1529 &ira->new_irb, scope, source_node);1529 &ira->new_irb, scope, source_node);
1530 instruction->base.value->type = result_type;1530 instruction->base.value->type = result_type;
1531 instruction->operand = operand;1531 instruction->operand = operand;
...@@ -1537,8 +1537,8 @@ static IrInstGen *ir_build_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *...@@ -1537,8 +1537,8 @@ static IrInstGen *ir_build_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *
1537 return &instruction->base;1537 return &instruction->base;
1538}1538}
15391539
1540static IrInstGen *ir_build_clz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, IrInstGen *op) {1540static Stage1AirInst *ir_build_clz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, Stage1AirInst *op) {
1541 IrInstGenClz *instruction = ir_build_inst_gen<IrInstGenClz>(&ira->new_irb,1541 Stage1AirInstClz *instruction = ir_build_inst_gen<Stage1AirInstClz>(&ira->new_irb,
1542 scope, source_node);1542 scope, source_node);
1543 instruction->base.value->type = result_type;1543 instruction->base.value->type = result_type;
1544 instruction->op = op;1544 instruction->op = op;
...@@ -1548,8 +1548,8 @@ static IrInstGen *ir_build_clz_gen(IrAnalyze *ira, Scope *scope, AstNode *source...@@ -1548,8 +1548,8 @@ static IrInstGen *ir_build_clz_gen(IrAnalyze *ira, Scope *scope, AstNode *source
1548 return &instruction->base;1548 return &instruction->base;
1549}1549}
15501550
1551static IrInstGen *ir_build_ctz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, IrInstGen *op) {1551static Stage1AirInst *ir_build_ctz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, Stage1AirInst *op) {
1552 IrInstGenCtz *instruction = ir_build_inst_gen<IrInstGenCtz>(&ira->new_irb,1552 Stage1AirInstCtz *instruction = ir_build_inst_gen<Stage1AirInstCtz>(&ira->new_irb,
1553 scope, source_node);1553 scope, source_node);
1554 instruction->base.value->type = result_type;1554 instruction->base.value->type = result_type;
1555 instruction->op = op;1555 instruction->op = op;
...@@ -1559,10 +1559,10 @@ static IrInstGen *ir_build_ctz_gen(IrAnalyze *ira, Scope *scope, AstNode *source...@@ -1559,10 +1559,10 @@ static IrInstGen *ir_build_ctz_gen(IrAnalyze *ira, Scope *scope, AstNode *source
1559 return &instruction->base;1559 return &instruction->base;
1560}1560}
15611561
1562static IrInstGen *ir_build_pop_count_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,1562static Stage1AirInst *ir_build_pop_count_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1563 IrInstGen *op)1563 Stage1AirInst *op)
1564{1564{
1565 IrInstGenPopCount *instruction = ir_build_inst_gen<IrInstGenPopCount>(&ira->new_irb,1565 Stage1AirInstPopCount *instruction = ir_build_inst_gen<Stage1AirInstPopCount>(&ira->new_irb,
1566 scope, source_node);1566 scope, source_node);
1567 instruction->base.value->type = result_type;1567 instruction->base.value->type = result_type;
1568 instruction->op = op;1568 instruction->op = op;
...@@ -1572,10 +1572,10 @@ static IrInstGen *ir_build_pop_count_gen(IrAnalyze *ira, Scope *scope, AstNode *...@@ -1572,10 +1572,10 @@ static IrInstGen *ir_build_pop_count_gen(IrAnalyze *ira, Scope *scope, AstNode *
1572 return &instruction->base;1572 return &instruction->base;
1573}1573}
15741574
1575static IrInstGen *ir_build_bswap_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *op_type,1575static Stage1AirInst *ir_build_bswap_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *op_type,
1576 IrInstGen *op)1576 Stage1AirInst *op)
1577{1577{
1578 IrInstGenBswap *instruction = ir_build_inst_gen<IrInstGenBswap>(&ira->new_irb,1578 Stage1AirInstBswap *instruction = ir_build_inst_gen<Stage1AirInstBswap>(&ira->new_irb,
1579 scope, source_node);1579 scope, source_node);
1580 instruction->base.value->type = op_type;1580 instruction->base.value->type = op_type;
1581 instruction->op = op;1581 instruction->op = op;
...@@ -1585,10 +1585,10 @@ static IrInstGen *ir_build_bswap_gen(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -1585,10 +1585,10 @@ static IrInstGen *ir_build_bswap_gen(IrAnalyze *ira, Scope *scope, AstNode *sour
1585 return &instruction->base;1585 return &instruction->base;
1586}1586}
15871587
1588static IrInstGen *ir_build_bit_reverse_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *int_type,1588static Stage1AirInst *ir_build_bit_reverse_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *int_type,
1589 IrInstGen *op)1589 Stage1AirInst *op)
1590{1590{
1591 IrInstGenBitReverse *instruction = ir_build_inst_gen<IrInstGenBitReverse>(&ira->new_irb,1591 Stage1AirInstBitReverse *instruction = ir_build_inst_gen<Stage1AirInstBitReverse>(&ira->new_irb,
1592 scope, source_node);1592 scope, source_node);
1593 instruction->base.value->type = int_type;1593 instruction->base.value->type = int_type;
1594 instruction->op = op;1594 instruction->op = op;
...@@ -1598,10 +1598,10 @@ static IrInstGen *ir_build_bit_reverse_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -1598,10 +1598,10 @@ static IrInstGen *ir_build_bit_reverse_gen(IrAnalyze *ira, Scope *scope, AstNode
1598 return &instruction->base;1598 return &instruction->base;
1599}1599}
16001600
1601static IrInstGenSwitchBr *ir_build_switch_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1601static Stage1AirInstSwitchBr *ir_build_switch_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1602 IrInstGen *target_value, IrBasicBlockGen *else_block, size_t case_count, IrInstGenSwitchBrCase *cases)1602 Stage1AirInst *target_value, Stage1AirBasicBlock *else_block, size_t case_count, Stage1AirInstSwitchBrCase *cases)
1603{1603{
1604 IrInstGenSwitchBr *instruction = ir_build_inst_noreturn<IrInstGenSwitchBr>(&ira->new_irb,1604 Stage1AirInstSwitchBr *instruction = ir_build_inst_noreturn<Stage1AirInstSwitchBr>(&ira->new_irb,
1605 scope, source_node);1605 scope, source_node);
1606 instruction->target_value = target_value;1606 instruction->target_value = target_value;
1607 instruction->else_block = else_block;1607 instruction->else_block = else_block;
...@@ -1617,10 +1617,10 @@ static IrInstGenSwitchBr *ir_build_switch_br_gen(IrAnalyze *ira, Scope *scope, A...@@ -1617,10 +1617,10 @@ static IrInstGenSwitchBr *ir_build_switch_br_gen(IrAnalyze *ira, Scope *scope, A
1617 return instruction;1617 return instruction;
1618}1618}
16191619
1620static IrInstGen *ir_build_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,1620static Stage1AirInst *ir_build_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
1621 ZigType *tag_type)1621 ZigType *tag_type)
1622{1622{
1623 IrInstGenUnionTag *instruction = ir_build_inst_gen<IrInstGenUnionTag>(&ira->new_irb,1623 Stage1AirInstUnionTag *instruction = ir_build_inst_gen<Stage1AirInstUnionTag>(&ira->new_irb,
1624 scope, source_node);1624 scope, source_node);
1625 instruction->value = value;1625 instruction->value = value;
1626 instruction->base.value->type = tag_type;1626 instruction->base.value->type = tag_type;
...@@ -1630,10 +1630,10 @@ static IrInstGen *ir_build_union_tag(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -1630,10 +1630,10 @@ static IrInstGen *ir_build_union_tag(IrAnalyze *ira, Scope *scope, AstNode *sour
1630 return &instruction->base;1630 return &instruction->base;
1631}1631}
16321632
1633static IrInstGen *ir_build_ref_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,1633static Stage1AirInst *ir_build_ref_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1634 IrInstGen *operand, IrInstGen *result_loc)1634 Stage1AirInst *operand, Stage1AirInst *result_loc)
1635{1635{
1636 IrInstGenRef *instruction = ir_build_inst_gen<IrInstGenRef>(&ira->new_irb,1636 Stage1AirInstRef *instruction = ir_build_inst_gen<Stage1AirInstRef>(&ira->new_irb,
1637 scope, source_node);1637 scope, source_node);
1638 instruction->base.value->type = result_type;1638 instruction->base.value->type = result_type;
1639 instruction->operand = operand;1639 instruction->operand = operand;
...@@ -1645,10 +1645,10 @@ static IrInstGen *ir_build_ref_gen(IrAnalyze *ira, Scope *scope, AstNode *source...@@ -1645,10 +1645,10 @@ static IrInstGen *ir_build_ref_gen(IrAnalyze *ira, Scope *scope, AstNode *source
1645 return &instruction->base;1645 return &instruction->base;
1646}1646}
16471647
1648static IrInstGen *ir_build_err_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,1648static Stage1AirInst *ir_build_err_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
1649 ZigType *str_type)1649 ZigType *str_type)
1650{1650{
1651 IrInstGenErrName *instruction = ir_build_inst_gen<IrInstGenErrName>(&ira->new_irb,1651 Stage1AirInstErrName *instruction = ir_build_inst_gen<Stage1AirInstErrName>(&ira->new_irb,
1652 scope, source_node);1652 scope, source_node);
1653 instruction->base.value->type = str_type;1653 instruction->base.value->type = str_type;
1654 instruction->value = value;1654 instruction->value = value;
...@@ -1658,11 +1658,11 @@ static IrInstGen *ir_build_err_name_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -1658,11 +1658,11 @@ static IrInstGen *ir_build_err_name_gen(IrAnalyze *ira, Scope *scope, AstNode *s
1658 return &instruction->base;1658 return &instruction->base;
1659}1659}
16601660
1661static IrInstGen *ir_build_cmpxchg_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,1661static Stage1AirInst *ir_build_cmpxchg_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1662 IrInstGen *ptr, IrInstGen *cmp_value, IrInstGen *new_value,1662 Stage1AirInst *ptr, Stage1AirInst *cmp_value, Stage1AirInst *new_value,
1663 AtomicOrder success_order, AtomicOrder failure_order, bool is_weak, IrInstGen *result_loc)1663 AtomicOrder success_order, AtomicOrder failure_order, bool is_weak, Stage1AirInst *result_loc)
1664{1664{
1665 IrInstGenCmpxchg *instruction = ir_build_inst_gen<IrInstGenCmpxchg>(&ira->new_irb,1665 Stage1AirInstCmpxchg *instruction = ir_build_inst_gen<Stage1AirInstCmpxchg>(&ira->new_irb,
1666 scope, source_node);1666 scope, source_node);
1667 instruction->base.value->type = result_type;1667 instruction->base.value->type = result_type;
1668 instruction->ptr = ptr;1668 instruction->ptr = ptr;
...@@ -1681,16 +1681,16 @@ static IrInstGen *ir_build_cmpxchg_gen(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -1681,16 +1681,16 @@ static IrInstGen *ir_build_cmpxchg_gen(IrAnalyze *ira, Scope *scope, AstNode *so
1681 return &instruction->base;1681 return &instruction->base;
1682}1682}
16831683
1684static IrInstGen *ir_build_fence_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, AtomicOrder order) {1684static Stage1AirInst *ir_build_fence_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, AtomicOrder order) {
1685 IrInstGenFence *instruction = ir_build_inst_void<IrInstGenFence>(&ira->new_irb,1685 Stage1AirInstFence *instruction = ir_build_inst_void<Stage1AirInstFence>(&ira->new_irb,
1686 scope, source_node);1686 scope, source_node);
1687 instruction->order = order;1687 instruction->order = order;
16881688
1689 return &instruction->base;1689 return &instruction->base;
1690}1690}
16911691
1692static IrInstGen *ir_build_reduce_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ReduceOp op, IrInstGen *value, ZigType *result_type) {1692static Stage1AirInst *ir_build_reduce_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ReduceOp op, Stage1AirInst *value, ZigType *result_type) {
1693 IrInstGenReduce *instruction = ir_build_inst_gen<IrInstGenReduce>(&ira->new_irb,1693 Stage1AirInstReduce *instruction = ir_build_inst_gen<Stage1AirInstReduce>(&ira->new_irb,
1694 scope, source_node);1694 scope, source_node);
1695 instruction->base.value->type = result_type;1695 instruction->base.value->type = result_type;
1696 instruction->op = op;1696 instruction->op = op;
...@@ -1701,38 +1701,38 @@ static IrInstGen *ir_build_reduce_gen(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -1701,38 +1701,38 @@ static IrInstGen *ir_build_reduce_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
1701 return &instruction->base;1701 return &instruction->base;
1702}1702}
17031703
1704static void ir_set_cursor_at_end_gen(IrBuilderGen *irb, IrBasicBlockGen *basic_block) {1704static void ir_set_cursor_at_end_gen(IrBuilderGen *irb, Stage1AirBasicBlock *basic_block) {
1705 assert(basic_block);1705 assert(basic_block);
1706 irb->current_basic_block = basic_block;1706 irb->current_basic_block = basic_block;
1707}1707}
17081708
1709static void ir_append_basic_block_gen(IrBuilderGen *irb, IrBasicBlockGen *bb) {1709static void ir_append_basic_block_gen(IrBuilderGen *irb, Stage1AirBasicBlock *bb) {
1710 assert(!bb->already_appended);1710 assert(!bb->already_appended);
1711 bb->already_appended = true;1711 bb->already_appended = true;
1712 irb->exec->basic_block_list.append(bb);1712 irb->exec->basic_block_list.append(bb);
1713}1713}
17141714
1715static void ir_set_cursor_at_end_and_append_block_gen(IrBuilderGen *irb, IrBasicBlockGen *basic_block) {1715static void ir_set_cursor_at_end_and_append_block_gen(IrBuilderGen *irb, Stage1AirBasicBlock *basic_block) {
1716 ir_append_basic_block_gen(irb, basic_block);1716 ir_append_basic_block_gen(irb, basic_block);
1717 ir_set_cursor_at_end_gen(irb, basic_block);1717 ir_set_cursor_at_end_gen(irb, basic_block);
1718}1718}
17191719
1720static IrInstGen *ir_build_suspend_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {1720static Stage1AirInst *ir_build_suspend_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1721 IrInstGenSuspendBegin *inst = ir_build_inst_void<IrInstGenSuspendBegin>(&ira->new_irb,1721 Stage1AirInstSuspendBegin *inst = ir_build_inst_void<Stage1AirInstSuspendBegin>(&ira->new_irb,
1722 scope, source_node);1722 scope, source_node);
1723 return &inst->base;1723 return &inst->base;
1724}1724}
17251725
1726static IrInstGen *ir_build_save_err_ret_addr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {1726static Stage1AirInst *ir_build_save_err_ret_addr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1727 IrInstGenSaveErrRetAddr *inst = ir_build_inst_void<IrInstGenSaveErrRetAddr>(&ira->new_irb,1727 Stage1AirInstSaveErrRetAddr *inst = ir_build_inst_void<Stage1AirInstSaveErrRetAddr>(&ira->new_irb,
1728 scope, source_node);1728 scope, source_node);
1729 return &inst->base;1729 return &inst->base;
1730}1730}
17311731
1732static IrInstGen *ir_build_truncate_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *dest_type,1732static Stage1AirInst *ir_build_truncate_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *dest_type,
1733 IrInstGen *target)1733 Stage1AirInst *target)
1734{1734{
1735 IrInstGenTruncate *instruction = ir_build_inst_gen<IrInstGenTruncate>(&ira->new_irb,1735 Stage1AirInstTruncate *instruction = ir_build_inst_gen<Stage1AirInstTruncate>(&ira->new_irb,
1736 scope, source_node);1736 scope, source_node);
1737 instruction->base.value->type = dest_type;1737 instruction->base.value->type = dest_type;
1738 instruction->target = target;1738 instruction->target = target;
...@@ -1742,10 +1742,10 @@ static IrInstGen *ir_build_truncate_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -1742,10 +1742,10 @@ static IrInstGen *ir_build_truncate_gen(IrAnalyze *ira, Scope *scope, AstNode *s
1742 return &instruction->base;1742 return &instruction->base;
1743}1743}
17441744
1745static IrInstGen *ir_build_shuffle_vector_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1745static Stage1AirInst *ir_build_shuffle_vector_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1746 ZigType *result_type, IrInstGen *a, IrInstGen *b, IrInstGen *mask)1746 ZigType *result_type, Stage1AirInst *a, Stage1AirInst *b, Stage1AirInst *mask)
1747{1747{
1748 IrInstGenShuffleVector *inst = ir_build_inst_gen<IrInstGenShuffleVector>(&ira->new_irb, scope, source_node);1748 Stage1AirInstShuffleVector *inst = ir_build_inst_gen<Stage1AirInstShuffleVector>(&ira->new_irb, scope, source_node);
1749 inst->base.value->type = result_type;1749 inst->base.value->type = result_type;
1750 inst->a = a;1750 inst->a = a;
1751 inst->b = b;1751 inst->b = b;
...@@ -1758,10 +1758,10 @@ static IrInstGen *ir_build_shuffle_vector_gen(IrAnalyze *ira, Scope *scope, AstN...@@ -1758,10 +1758,10 @@ static IrInstGen *ir_build_shuffle_vector_gen(IrAnalyze *ira, Scope *scope, AstN
1758 return &inst->base;1758 return &inst->base;
1759}1759}
17601760
1761static IrInstGen *ir_build_splat_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,1761static Stage1AirInst *ir_build_splat_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1762 IrInstGen *scalar)1762 Stage1AirInst *scalar)
1763{1763{
1764 IrInstGenSplat *instruction = ir_build_inst_gen<IrInstGenSplat>(1764 Stage1AirInstSplat *instruction = ir_build_inst_gen<Stage1AirInstSplat>(
1765 &ira->new_irb, scope, source_node);1765 &ira->new_irb, scope, source_node);
1766 instruction->base.value->type = result_type;1766 instruction->base.value->type = result_type;
1767 instruction->scalar = scalar;1767 instruction->scalar = scalar;
...@@ -1771,8 +1771,8 @@ static IrInstGen *ir_build_splat_gen(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -1771,8 +1771,8 @@ static IrInstGen *ir_build_splat_gen(IrAnalyze *ira, Scope *scope, AstNode *sour
1771 return &instruction->base;1771 return &instruction->base;
1772}1772}
17731773
1774static IrInstGen *ir_build_bool_not_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) {1774static Stage1AirInst *ir_build_bool_not_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) {
1775 IrInstGenBoolNot *instruction = ir_build_inst_gen<IrInstGenBoolNot>(&ira->new_irb,1775 Stage1AirInstBoolNot *instruction = ir_build_inst_gen<Stage1AirInstBoolNot>(&ira->new_irb,
1776 scope, source_node);1776 scope, source_node);
1777 instruction->base.value->type = ira->codegen->builtin_types.entry_bool;1777 instruction->base.value->type = ira->codegen->builtin_types.entry_bool;
1778 instruction->value = value;1778 instruction->value = value;
...@@ -1782,10 +1782,10 @@ static IrInstGen *ir_build_bool_not_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -1782,10 +1782,10 @@ static IrInstGen *ir_build_bool_not_gen(IrAnalyze *ira, Scope *scope, AstNode *s
1782 return &instruction->base;1782 return &instruction->base;
1783}1783}
17841784
1785static IrInstGen *ir_build_memset_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1785static Stage1AirInst *ir_build_memset_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1786 IrInstGen *dest_ptr, IrInstGen *byte, IrInstGen *count)1786 Stage1AirInst *dest_ptr, Stage1AirInst *byte, Stage1AirInst *count)
1787{1787{
1788 IrInstGenMemset *instruction = ir_build_inst_void<IrInstGenMemset>(&ira->new_irb,1788 Stage1AirInstMemset *instruction = ir_build_inst_void<Stage1AirInstMemset>(&ira->new_irb,
1789 scope, source_node);1789 scope, source_node);
1790 instruction->dest_ptr = dest_ptr;1790 instruction->dest_ptr = dest_ptr;
1791 instruction->byte = byte;1791 instruction->byte = byte;
...@@ -1798,10 +1798,10 @@ static IrInstGen *ir_build_memset_gen(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -1798,10 +1798,10 @@ static IrInstGen *ir_build_memset_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
1798 return &instruction->base;1798 return &instruction->base;
1799}1799}
18001800
1801static IrInstGen *ir_build_memcpy_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1801static Stage1AirInst *ir_build_memcpy_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1802 IrInstGen *dest_ptr, IrInstGen *src_ptr, IrInstGen *count)1802 Stage1AirInst *dest_ptr, Stage1AirInst *src_ptr, Stage1AirInst *count)
1803{1803{
1804 IrInstGenMemcpy *instruction = ir_build_inst_void<IrInstGenMemcpy>(&ira->new_irb,1804 Stage1AirInstMemcpy *instruction = ir_build_inst_void<Stage1AirInstMemcpy>(&ira->new_irb,
1805 scope, source_node);1805 scope, source_node);
1806 instruction->dest_ptr = dest_ptr;1806 instruction->dest_ptr = dest_ptr;
1807 instruction->src_ptr = src_ptr;1807 instruction->src_ptr = src_ptr;
...@@ -1814,11 +1814,11 @@ static IrInstGen *ir_build_memcpy_gen(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -1814,11 +1814,11 @@ static IrInstGen *ir_build_memcpy_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
1814 return &instruction->base;1814 return &instruction->base;
1815}1815}
18161816
1817static IrInstGen *ir_build_slice_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *slice_type,1817static Stage1AirInst *ir_build_slice_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *slice_type,
1818 IrInstGen *ptr, IrInstGen *start, IrInstGen *end, bool safety_check_on, IrInstGen *result_loc,1818 Stage1AirInst *ptr, Stage1AirInst *start, Stage1AirInst *end, bool safety_check_on, Stage1AirInst *result_loc,
1819 ZigValue *sentinel)1819 ZigValue *sentinel)
1820{1820{
1821 IrInstGenSlice *instruction = ir_build_inst_gen<IrInstGenSlice>(1821 Stage1AirInstSlice *instruction = ir_build_inst_gen<Stage1AirInstSlice>(
1822 &ira->new_irb, scope, source_node);1822 &ira->new_irb, scope, source_node);
1823 instruction->base.value->type = slice_type;1823 instruction->base.value->type = slice_type;
1824 instruction->ptr = ptr;1824 instruction->ptr = ptr;
...@@ -1836,33 +1836,33 @@ static IrInstGen *ir_build_slice_gen(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -1836,33 +1836,33 @@ static IrInstGen *ir_build_slice_gen(IrAnalyze *ira, Scope *scope, AstNode *sour
1836 return &instruction->base;1836 return &instruction->base;
1837}1837}
18381838
1839static IrInstGen *ir_build_breakpoint_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {1839static Stage1AirInst *ir_build_breakpoint_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1840 IrInstGenBreakpoint *instruction = ir_build_inst_void<IrInstGenBreakpoint>(&ira->new_irb,1840 Stage1AirInstBreakpoint *instruction = ir_build_inst_void<Stage1AirInstBreakpoint>(&ira->new_irb,
1841 scope, source_node);1841 scope, source_node);
1842 return &instruction->base;1842 return &instruction->base;
1843}1843}
18441844
1845static IrInstGen *ir_build_return_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {1845static Stage1AirInst *ir_build_return_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1846 IrInstGenReturnAddress *inst = ir_build_inst_gen<IrInstGenReturnAddress>(&ira->new_irb, scope, source_node);1846 Stage1AirInstReturnAddress *inst = ir_build_inst_gen<Stage1AirInstReturnAddress>(&ira->new_irb, scope, source_node);
1847 inst->base.value->type = ira->codegen->builtin_types.entry_usize;1847 inst->base.value->type = ira->codegen->builtin_types.entry_usize;
1848 return &inst->base;1848 return &inst->base;
1849}1849}
18501850
1851static IrInstGen *ir_build_frame_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {1851static Stage1AirInst *ir_build_frame_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1852 IrInstGenFrameAddress *inst = ir_build_inst_gen<IrInstGenFrameAddress>(&ira->new_irb, scope, source_node);1852 Stage1AirInstFrameAddress *inst = ir_build_inst_gen<Stage1AirInstFrameAddress>(&ira->new_irb, scope, source_node);
1853 inst->base.value->type = ira->codegen->builtin_types.entry_usize;1853 inst->base.value->type = ira->codegen->builtin_types.entry_usize;
1854 return &inst->base;1854 return &inst->base;
1855}1855}
18561856
1857static IrInstGen *ir_build_handle_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {1857static Stage1AirInst *ir_build_handle_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
1858 IrInstGenFrameHandle *inst = ir_build_inst_gen<IrInstGenFrameHandle>(&ira->new_irb, scope, source_node);1858 Stage1AirInstFrameHandle *inst = ir_build_inst_gen<Stage1AirInstFrameHandle>(&ira->new_irb, scope, source_node);
1859 inst->base.value->type = ty;1859 inst->base.value->type = ty;
1860 return &inst->base;1860 return &inst->base;
1861}1861}
18621862
1863static IrInstGen *ir_build_frame_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *fn)1863static Stage1AirInst *ir_build_frame_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *fn)
1864{1864{
1865 IrInstGenFrameSize *inst = ir_build_inst_gen<IrInstGenFrameSize>(&ira->new_irb, scope, source_node);1865 Stage1AirInstFrameSize *inst = ir_build_inst_gen<Stage1AirInstFrameSize>(&ira->new_irb, scope, source_node);
1866 inst->base.value->type = ira->codegen->builtin_types.entry_usize;1866 inst->base.value->type = ira->codegen->builtin_types.entry_usize;
1867 inst->fn = fn;1867 inst->fn = fn;
18681868
...@@ -1871,11 +1871,11 @@ static IrInstGen *ir_build_frame_size_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -1871,11 +1871,11 @@ static IrInstGen *ir_build_frame_size_gen(IrAnalyze *ira, Scope *scope, AstNode
1871 return &inst->base;1871 return &inst->base;
1872}1872}
18731873
1874static IrInstGen *ir_build_overflow_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1874static Stage1AirInst *ir_build_overflow_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1875 IrOverflowOp op, IrInstGen *op1, IrInstGen *op2, IrInstGen *result_ptr,1875 IrOverflowOp op, Stage1AirInst *op1, Stage1AirInst *op2, Stage1AirInst *result_ptr,
1876 ZigType *result_ptr_type)1876 ZigType *result_ptr_type)
1877{1877{
1878 IrInstGenOverflowOp *instruction = ir_build_inst_gen<IrInstGenOverflowOp>(&ira->new_irb,1878 Stage1AirInstOverflowOp *instruction = ir_build_inst_gen<Stage1AirInstOverflowOp>(&ira->new_irb,
1879 scope, source_node);1879 scope, source_node);
1880 instruction->base.value->type = ira->codegen->builtin_types.entry_bool;1880 instruction->base.value->type = ira->codegen->builtin_types.entry_bool;
1881 instruction->op = op;1881 instruction->op = op;
...@@ -1891,10 +1891,10 @@ static IrInstGen *ir_build_overflow_op_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -1891,10 +1891,10 @@ static IrInstGen *ir_build_overflow_op_gen(IrAnalyze *ira, Scope *scope, AstNode
1891 return &instruction->base;1891 return &instruction->base;
1892}1892}
18931893
1894static IrInstGen *ir_build_float_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand,1894static Stage1AirInst *ir_build_float_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand,
1895 BuiltinFnId fn_id, ZigType *operand_type)1895 BuiltinFnId fn_id, ZigType *operand_type)
1896{1896{
1897 IrInstGenFloatOp *instruction = ir_build_inst_gen<IrInstGenFloatOp>(&ira->new_irb,1897 Stage1AirInstFloatOp *instruction = ir_build_inst_gen<Stage1AirInstFloatOp>(&ira->new_irb,
1898 scope, source_node);1898 scope, source_node);
1899 instruction->base.value->type = operand_type;1899 instruction->base.value->type = operand_type;
1900 instruction->operand = operand;1900 instruction->operand = operand;
...@@ -1905,10 +1905,10 @@ static IrInstGen *ir_build_float_op_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -1905,10 +1905,10 @@ static IrInstGen *ir_build_float_op_gen(IrAnalyze *ira, Scope *scope, AstNode *s
1905 return &instruction->base;1905 return &instruction->base;
1906}1906}
19071907
1908static IrInstGen *ir_build_mul_add_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *op1, IrInstGen *op2,1908static Stage1AirInst *ir_build_mul_add_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *op1, Stage1AirInst *op2,
1909 IrInstGen *op3, ZigType *expr_type)1909 Stage1AirInst *op3, ZigType *expr_type)
1910{1910{
1911 IrInstGenMulAdd *instruction = ir_build_inst_gen<IrInstGenMulAdd>(&ira->new_irb,1911 Stage1AirInstMulAdd *instruction = ir_build_inst_gen<Stage1AirInstMulAdd>(&ira->new_irb,
1912 scope, source_node);1912 scope, source_node);
1913 instruction->base.value->type = expr_type;1913 instruction->base.value->type = expr_type;
1914 instruction->op1 = op1;1914 instruction->op1 = op1;
...@@ -1922,8 +1922,8 @@ static IrInstGen *ir_build_mul_add_gen(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -1922,8 +1922,8 @@ static IrInstGen *ir_build_mul_add_gen(IrAnalyze *ira, Scope *scope, AstNode *so
1922 return &instruction->base;1922 return &instruction->base;
1923}1923}
19241924
1925static IrInstGen *ir_build_test_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *err_union) {1925static Stage1AirInst *ir_build_test_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *err_union) {
1926 IrInstGenTestErr *instruction = ir_build_inst_gen<IrInstGenTestErr>(1926 Stage1AirInstTestErr *instruction = ir_build_inst_gen<Stage1AirInstTestErr>(
1927 &ira->new_irb, scope, source_node);1927 &ira->new_irb, scope, source_node);
1928 instruction->base.value->type = ira->codegen->builtin_types.entry_bool;1928 instruction->base.value->type = ira->codegen->builtin_types.entry_bool;
1929 instruction->err_union = err_union;1929 instruction->err_union = err_union;
...@@ -1933,10 +1933,10 @@ static IrInstGen *ir_build_test_err_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -1933,10 +1933,10 @@ static IrInstGen *ir_build_test_err_gen(IrAnalyze *ira, Scope *scope, AstNode *s
1933 return &instruction->base;1933 return &instruction->base;
1934}1934}
19351935
1936static IrInstGen *ir_build_unwrap_err_code_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1936static Stage1AirInst *ir_build_unwrap_err_code_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1937 IrInstGen *err_union_ptr, ZigType *result_type)1937 Stage1AirInst *err_union_ptr, ZigType *result_type)
1938{1938{
1939 IrInstGenUnwrapErrCode *inst = ir_build_inst_gen<IrInstGenUnwrapErrCode>(&ira->new_irb, scope, source_node);1939 Stage1AirInstUnwrapErrCode *inst = ir_build_inst_gen<Stage1AirInstUnwrapErrCode>(&ira->new_irb, scope, source_node);
1940 inst->base.value->type = result_type;1940 inst->base.value->type = result_type;
1941 inst->err_union_ptr = err_union_ptr;1941 inst->err_union_ptr = err_union_ptr;
19421942
...@@ -1945,10 +1945,10 @@ static IrInstGen *ir_build_unwrap_err_code_gen(IrAnalyze *ira, Scope *scope, Ast...@@ -1945,10 +1945,10 @@ static IrInstGen *ir_build_unwrap_err_code_gen(IrAnalyze *ira, Scope *scope, Ast
1945 return &inst->base;1945 return &inst->base;
1946}1946}
19471947
1948static IrInstGen *ir_build_unwrap_err_payload_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1948static Stage1AirInst *ir_build_unwrap_err_payload_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1949 IrInstGen *value, bool safety_check_on, bool initializing, ZigType *result_type)1949 Stage1AirInst *value, bool safety_check_on, bool initializing, ZigType *result_type)
1950{1950{
1951 IrInstGenUnwrapErrPayload *inst = ir_build_inst_gen<IrInstGenUnwrapErrPayload>(&ira->new_irb, scope, source_node);1951 Stage1AirInstUnwrapErrPayload *inst = ir_build_inst_gen<Stage1AirInstUnwrapErrPayload>(&ira->new_irb, scope, source_node);
1952 inst->base.value->type = result_type;1952 inst->base.value->type = result_type;
1953 inst->value = value;1953 inst->value = value;
1954 inst->safety_check_on = safety_check_on;1954 inst->safety_check_on = safety_check_on;
...@@ -1959,10 +1959,10 @@ static IrInstGen *ir_build_unwrap_err_payload_gen(IrAnalyze *ira, Scope *scope,...@@ -1959,10 +1959,10 @@ static IrInstGen *ir_build_unwrap_err_payload_gen(IrAnalyze *ira, Scope *scope,
1959 return &inst->base;1959 return &inst->base;
1960}1960}
19611961
1962static IrInstGen *ir_build_ptr_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1962static Stage1AirInst *ir_build_ptr_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1963 ZigType *ptr_type, IrInstGen *ptr, bool safety_check_on)1963 ZigType *ptr_type, Stage1AirInst *ptr, bool safety_check_on)
1964{1964{
1965 IrInstGenPtrCast *instruction = ir_build_inst_gen<IrInstGenPtrCast>(1965 Stage1AirInstPtrCast *instruction = ir_build_inst_gen<Stage1AirInstPtrCast>(
1966 &ira->new_irb, scope, source_node);1966 &ira->new_irb, scope, source_node);
1967 instruction->base.value->type = ptr_type;1967 instruction->base.value->type = ptr_type;
1968 instruction->ptr = ptr;1968 instruction->ptr = ptr;
...@@ -1973,10 +1973,10 @@ static IrInstGen *ir_build_ptr_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -1973,10 +1973,10 @@ static IrInstGen *ir_build_ptr_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *s
1973 return &instruction->base;1973 return &instruction->base;
1974}1974}
19751975
1976static IrInstGen *ir_build_bit_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,1976static Stage1AirInst *ir_build_bit_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1977 IrInstGen *operand, ZigType *ty)1977 Stage1AirInst *operand, ZigType *ty)
1978{1978{
1979 IrInstGenBitCast *instruction = ir_build_inst_gen<IrInstGenBitCast>(1979 Stage1AirInstBitCast *instruction = ir_build_inst_gen<Stage1AirInstBitCast>(
1980 &ira->new_irb, scope, source_node);1980 &ira->new_irb, scope, source_node);
1981 instruction->base.value->type = ty;1981 instruction->base.value->type = ty;
1982 instruction->operand = operand;1982 instruction->operand = operand;
...@@ -1986,10 +1986,10 @@ static IrInstGen *ir_build_bit_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -1986,10 +1986,10 @@ static IrInstGen *ir_build_bit_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *s
1986 return &instruction->base;1986 return &instruction->base;
1987}1987}
19881988
1989static IrInstGen *ir_build_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,1989static Stage1AirInst *ir_build_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
1990 ZigType *result_type)1990 ZigType *result_type)
1991{1991{
1992 IrInstGenWidenOrShorten *inst = ir_build_inst_gen<IrInstGenWidenOrShorten>(&ira->new_irb, scope, source_node);1992 Stage1AirInstWidenOrShorten *inst = ir_build_inst_gen<Stage1AirInstWidenOrShorten>(&ira->new_irb, scope, source_node);
1993 inst->base.value->type = result_type;1993 inst->base.value->type = result_type;
1994 inst->target = target;1994 inst->target = target;
19951995
...@@ -1998,10 +1998,10 @@ static IrInstGen *ir_build_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNod...@@ -1998,10 +1998,10 @@ static IrInstGen *ir_build_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNod
1998 return &inst->base;1998 return &inst->base;
1999}1999}
20002000
2001static IrInstGen *ir_build_int_to_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,2001static Stage1AirInst *ir_build_int_to_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2002 IrInstGen *target, ZigType *ptr_type)2002 Stage1AirInst *target, ZigType *ptr_type)
2003{2003{
2004 IrInstGenIntToPtr *instruction = ir_build_inst_gen<IrInstGenIntToPtr>(&ira->new_irb, scope, source_node);2004 Stage1AirInstIntToPtr *instruction = ir_build_inst_gen<Stage1AirInstIntToPtr>(&ira->new_irb, scope, source_node);
2005 instruction->base.value->type = ptr_type;2005 instruction->base.value->type = ptr_type;
2006 instruction->target = target;2006 instruction->target = target;
20072007
...@@ -2010,8 +2010,8 @@ static IrInstGen *ir_build_int_to_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -2010,8 +2010,8 @@ static IrInstGen *ir_build_int_to_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode
2010 return &instruction->base;2010 return &instruction->base;
2011}2011}
20122012
2013static IrInstGen *ir_build_ptr_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target) {2013static Stage1AirInst *ir_build_ptr_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target) {
2014 IrInstGenPtrToInt *inst = ir_build_inst_gen<IrInstGenPtrToInt>(&ira->new_irb, scope, source_node);2014 Stage1AirInstPtrToInt *inst = ir_build_inst_gen<Stage1AirInstPtrToInt>(&ira->new_irb, scope, source_node);
2015 inst->base.value->type = ira->codegen->builtin_types.entry_usize;2015 inst->base.value->type = ira->codegen->builtin_types.entry_usize;
2016 inst->target = target;2016 inst->target = target;
20172017
...@@ -2020,10 +2020,10 @@ static IrInstGen *ir_build_ptr_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -2020,10 +2020,10 @@ static IrInstGen *ir_build_ptr_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode
2020 return &inst->base;2020 return &inst->base;
2021}2021}
20222022
2023static IrInstGen *ir_build_int_to_enum_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,2023static Stage1AirInst *ir_build_int_to_enum_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2024 ZigType *dest_type, IrInstGen *target)2024 ZigType *dest_type, Stage1AirInst *target)
2025{2025{
2026 IrInstGenIntToEnum *instruction = ir_build_inst_gen<IrInstGenIntToEnum>(&ira->new_irb, scope, source_node);2026 Stage1AirInstIntToEnum *instruction = ir_build_inst_gen<Stage1AirInstIntToEnum>(&ira->new_irb, scope, source_node);
2027 instruction->base.value->type = dest_type;2027 instruction->base.value->type = dest_type;
2028 instruction->target = target;2028 instruction->target = target;
20292029
...@@ -2032,10 +2032,10 @@ static IrInstGen *ir_build_int_to_enum_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -2032,10 +2032,10 @@ static IrInstGen *ir_build_int_to_enum_gen(IrAnalyze *ira, Scope *scope, AstNode
2032 return &instruction->base;2032 return &instruction->base;
2033}2033}
20342034
2035static IrInstGen *ir_build_int_to_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,2035static Stage1AirInst *ir_build_int_to_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
2036 ZigType *wanted_type)2036 ZigType *wanted_type)
2037{2037{
2038 IrInstGenIntToErr *instruction = ir_build_inst_gen<IrInstGenIntToErr>(&ira->new_irb, scope, source_node);2038 Stage1AirInstIntToErr *instruction = ir_build_inst_gen<Stage1AirInstIntToErr>(&ira->new_irb, scope, source_node);
2039 instruction->base.value->type = wanted_type;2039 instruction->base.value->type = wanted_type;
2040 instruction->target = target;2040 instruction->target = target;
20412041
...@@ -2044,10 +2044,10 @@ static IrInstGen *ir_build_int_to_err_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -2044,10 +2044,10 @@ static IrInstGen *ir_build_int_to_err_gen(IrAnalyze *ira, Scope *scope, AstNode
2044 return &instruction->base;2044 return &instruction->base;
2045}2045}
20462046
2047static IrInstGen *ir_build_err_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,2047static Stage1AirInst *ir_build_err_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
2048 ZigType *wanted_type)2048 ZigType *wanted_type)
2049{2049{
2050 IrInstGenErrToInt *instruction = ir_build_inst_gen<IrInstGenErrToInt>(&ira->new_irb, scope, source_node);2050 Stage1AirInstErrToInt *instruction = ir_build_inst_gen<Stage1AirInstErrToInt>(&ira->new_irb, scope, source_node);
2051 instruction->base.value->type = wanted_type;2051 instruction->base.value->type = wanted_type;
2052 instruction->target = target;2052 instruction->target = target;
20532053
...@@ -2056,8 +2056,8 @@ static IrInstGen *ir_build_err_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -2056,8 +2056,8 @@ static IrInstGen *ir_build_err_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode
2056 return &instruction->base;2056 return &instruction->base;
2057}2057}
20582058
2059static IrInstGen *ir_build_panic_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *msg) {2059static Stage1AirInst *ir_build_panic_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *msg) {
2060 IrInstGenPanic *instruction = ir_build_inst_noreturn<IrInstGenPanic>(&ira->new_irb,2060 Stage1AirInstPanic *instruction = ir_build_inst_noreturn<Stage1AirInstPanic>(&ira->new_irb,
2061 scope, source_node);2061 scope, source_node);
2062 instruction->msg = msg;2062 instruction->msg = msg;
20632063
...@@ -2066,10 +2066,10 @@ static IrInstGen *ir_build_panic_gen(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -2066,10 +2066,10 @@ static IrInstGen *ir_build_panic_gen(IrAnalyze *ira, Scope *scope, AstNode *sour
2066 return &instruction->base;2066 return &instruction->base;
2067}2067}
20682068
2069static IrInstGen *ir_build_tag_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,2069static Stage1AirInst *ir_build_tag_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
2070 ZigType *result_type)2070 ZigType *result_type)
2071{2071{
2072 IrInstGenTagName *instruction = ir_build_inst_gen<IrInstGenTagName>(&ira->new_irb,2072 Stage1AirInstTagName *instruction = ir_build_inst_gen<Stage1AirInstTagName>(&ira->new_irb,
2073 scope, source_node);2073 scope, source_node);
2074 instruction->base.value->type = result_type;2074 instruction->base.value->type = result_type;
2075 instruction->target = target;2075 instruction->target = target;
...@@ -2079,10 +2079,10 @@ static IrInstGen *ir_build_tag_name_gen(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -2079,10 +2079,10 @@ static IrInstGen *ir_build_tag_name_gen(IrAnalyze *ira, Scope *scope, AstNode *s
2079 return &instruction->base;2079 return &instruction->base;
2080}2080}
20812081
2082static IrInstGen *ir_build_field_parent_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,2082static Stage1AirInst *ir_build_field_parent_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2083 IrInstGen *field_ptr, TypeStructField *field, ZigType *result_type)2083 Stage1AirInst *field_ptr, TypeStructField *field, ZigType *result_type)
2084{2084{
2085 IrInstGenFieldParentPtr *inst = ir_build_inst_gen<IrInstGenFieldParentPtr>(&ira->new_irb,2085 Stage1AirInstFieldParentPtr *inst = ir_build_inst_gen<Stage1AirInstFieldParentPtr>(&ira->new_irb,
2086 scope, source_node);2086 scope, source_node);
2087 inst->base.value->type = result_type;2087 inst->base.value->type = result_type;
2088 inst->field_ptr = field_ptr;2088 inst->field_ptr = field_ptr;
...@@ -2093,10 +2093,10 @@ static IrInstGen *ir_build_field_parent_ptr_gen(IrAnalyze *ira, Scope *scope, As...@@ -2093,10 +2093,10 @@ static IrInstGen *ir_build_field_parent_ptr_gen(IrAnalyze *ira, Scope *scope, As
2093 return &inst->base;2093 return &inst->base;
2094}2094}
20952095
2096static IrInstGen *ir_build_align_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,2096static Stage1AirInst *ir_build_align_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
2097 ZigType *result_type)2097 ZigType *result_type)
2098{2098{
2099 IrInstGenAlignCast *instruction = ir_build_inst_gen<IrInstGenAlignCast>(&ira->new_irb, scope, source_node);2099 Stage1AirInstAlignCast *instruction = ir_build_inst_gen<Stage1AirInstAlignCast>(&ira->new_irb, scope, source_node);
2100 instruction->base.value->type = result_type;2100 instruction->base.value->type = result_type;
2101 instruction->target = target;2101 instruction->target = target;
21022102
...@@ -2105,20 +2105,20 @@ static IrInstGen *ir_build_align_cast_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -2105,20 +2105,20 @@ static IrInstGen *ir_build_align_cast_gen(IrAnalyze *ira, Scope *scope, AstNode
2105 return &instruction->base;2105 return &instruction->base;
2106}2106}
21072107
2108static IrInstGen *ir_build_error_return_trace_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,2108static Stage1AirInst *ir_build_error_return_trace_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2109 IrInstErrorReturnTraceOptional optional, ZigType *result_type)2109 IrInstErrorReturnTraceOptional optional, ZigType *result_type)
2110{2110{
2111 IrInstGenErrorReturnTrace *inst = ir_build_inst_gen<IrInstGenErrorReturnTrace>(&ira->new_irb, scope, source_node);2111 Stage1AirInstErrorReturnTrace *inst = ir_build_inst_gen<Stage1AirInstErrorReturnTrace>(&ira->new_irb, scope, source_node);
2112 inst->base.value->type = result_type;2112 inst->base.value->type = result_type;
2113 inst->optional = optional;2113 inst->optional = optional;
21142114
2115 return &inst->base;2115 return &inst->base;
2116}2116}
21172117
2118static IrInstGen *ir_build_atomic_rmw_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,2118static Stage1AirInst *ir_build_atomic_rmw_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2119 IrInstGen *ptr, IrInstGen *operand, AtomicRmwOp op, AtomicOrder ordering, ZigType *operand_type)2119 Stage1AirInst *ptr, Stage1AirInst *operand, AtomicRmwOp op, AtomicOrder ordering, ZigType *operand_type)
2120{2120{
2121 IrInstGenAtomicRmw *instruction = ir_build_inst_gen<IrInstGenAtomicRmw>(&ira->new_irb, scope, source_node);2121 Stage1AirInstAtomicRmw *instruction = ir_build_inst_gen<Stage1AirInstAtomicRmw>(&ira->new_irb, scope, source_node);
2122 instruction->base.value->type = operand_type;2122 instruction->base.value->type = operand_type;
2123 instruction->ptr = ptr;2123 instruction->ptr = ptr;
2124 instruction->op = op;2124 instruction->op = op;
...@@ -2131,10 +2131,10 @@ static IrInstGen *ir_build_atomic_rmw_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -2131,10 +2131,10 @@ static IrInstGen *ir_build_atomic_rmw_gen(IrAnalyze *ira, Scope *scope, AstNode
2131 return &instruction->base;2131 return &instruction->base;
2132}2132}
21332133
2134static IrInstGen *ir_build_atomic_load_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,2134static Stage1AirInst *ir_build_atomic_load_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2135 IrInstGen *ptr, AtomicOrder ordering, ZigType *operand_type)2135 Stage1AirInst *ptr, AtomicOrder ordering, ZigType *operand_type)
2136{2136{
2137 IrInstGenAtomicLoad *instruction = ir_build_inst_gen<IrInstGenAtomicLoad>(&ira->new_irb,2137 Stage1AirInstAtomicLoad *instruction = ir_build_inst_gen<Stage1AirInstAtomicLoad>(&ira->new_irb,
2138 scope, source_node);2138 scope, source_node);
2139 instruction->base.value->type = operand_type;2139 instruction->base.value->type = operand_type;
2140 instruction->ptr = ptr;2140 instruction->ptr = ptr;
...@@ -2145,10 +2145,10 @@ static IrInstGen *ir_build_atomic_load_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -2145,10 +2145,10 @@ static IrInstGen *ir_build_atomic_load_gen(IrAnalyze *ira, Scope *scope, AstNode
2145 return &instruction->base;2145 return &instruction->base;
2146}2146}
21472147
2148static IrInstGen *ir_build_atomic_store_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,2148static Stage1AirInst *ir_build_atomic_store_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2149 IrInstGen *ptr, IrInstGen *value, AtomicOrder ordering)2149 Stage1AirInst *ptr, Stage1AirInst *value, AtomicOrder ordering)
2150{2150{
2151 IrInstGenAtomicStore *instruction = ir_build_inst_void<IrInstGenAtomicStore>(&ira->new_irb,2151 Stage1AirInstAtomicStore *instruction = ir_build_inst_void<Stage1AirInstAtomicStore>(&ira->new_irb,
2152 scope, source_node);2152 scope, source_node);
2153 instruction->ptr = ptr;2153 instruction->ptr = ptr;
2154 instruction->value = value;2154 instruction->value = value;
...@@ -2161,10 +2161,10 @@ static IrInstGen *ir_build_atomic_store_gen(IrAnalyze *ira, Scope *scope, AstNod...@@ -2161,10 +2161,10 @@ static IrInstGen *ir_build_atomic_store_gen(IrAnalyze *ira, Scope *scope, AstNod
2161}2161}
21622162
21632163
2164static IrInstGen *ir_build_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,2164static Stage1AirInst *ir_build_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2165 ZigType *result_type, IrInstGen *vector, IrInstGen *result_loc)2165 ZigType *result_type, Stage1AirInst *vector, Stage1AirInst *result_loc)
2166{2166{
2167 IrInstGenVectorToArray *instruction = ir_build_inst_gen<IrInstGenVectorToArray>(&ira->new_irb,2167 Stage1AirInstVectorToArray *instruction = ir_build_inst_gen<Stage1AirInstVectorToArray>(&ira->new_irb,
2168 scope, source_node);2168 scope, source_node);
2169 instruction->base.value->type = result_type;2169 instruction->base.value->type = result_type;
2170 instruction->vector = vector;2170 instruction->vector = vector;
...@@ -2176,10 +2176,10 @@ static IrInstGen *ir_build_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode...@@ -2176,10 +2176,10 @@ static IrInstGen *ir_build_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode
2176 return &instruction->base;2176 return &instruction->base;
2177}2177}
21782178
2179static IrInstGen *ir_build_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node,2179static Stage1AirInst *ir_build_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2180 ZigType *result_type, IrInstGen *operand, IrInstGen *result_loc)2180 ZigType *result_type, Stage1AirInst *operand, Stage1AirInst *result_loc)
2181{2181{
2182 IrInstGenPtrOfArrayToSlice *instruction = ir_build_inst_gen<IrInstGenPtrOfArrayToSlice>(&ira->new_irb,2182 Stage1AirInstPtrOfArrayToSlice *instruction = ir_build_inst_gen<Stage1AirInstPtrOfArrayToSlice>(&ira->new_irb,
2183 scope, source_node);2183 scope, source_node);
2184 instruction->base.value->type = result_type;2184 instruction->base.value->type = result_type;
2185 instruction->operand = operand;2185 instruction->operand = operand;
...@@ -2191,10 +2191,10 @@ static IrInstGen *ir_build_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, A...@@ -2191,10 +2191,10 @@ static IrInstGen *ir_build_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, A
2191 return &instruction->base;2191 return &instruction->base;
2192}2192}
21932193
2194static IrInstGen *ir_build_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,2194static Stage1AirInst *ir_build_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2195 IrInstGen *array, ZigType *result_type)2195 Stage1AirInst *array, ZigType *result_type)
2196{2196{
2197 IrInstGenArrayToVector *instruction = ir_build_inst_gen<IrInstGenArrayToVector>(&ira->new_irb,2197 Stage1AirInstArrayToVector *instruction = ir_build_inst_gen<Stage1AirInstArrayToVector>(&ira->new_irb,
2198 scope, source_node);2198 scope, source_node);
2199 instruction->base.value->type = result_type;2199 instruction->base.value->type = result_type;
2200 instruction->array = array;2200 instruction->array = array;
...@@ -2204,10 +2204,10 @@ static IrInstGen *ir_build_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode...@@ -2204,10 +2204,10 @@ static IrInstGen *ir_build_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode
2204 return &instruction->base;2204 return &instruction->base;
2205}2205}
22062206
2207static IrInstGen *ir_build_assert_zero(IrAnalyze *ira, Scope *scope, AstNode *source_node,2207static Stage1AirInst *ir_build_assert_zero(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2208 IrInstGen *target)2208 Stage1AirInst *target)
2209{2209{
2210 IrInstGenAssertZero *instruction = ir_build_inst_gen<IrInstGenAssertZero>(&ira->new_irb,2210 Stage1AirInstAssertZero *instruction = ir_build_inst_gen<Stage1AirInstAssertZero>(&ira->new_irb,
2211 scope, source_node);2211 scope, source_node);
2212 instruction->base.value->type = ira->codegen->builtin_types.entry_void;2212 instruction->base.value->type = ira->codegen->builtin_types.entry_void;
2213 instruction->target = target;2213 instruction->target = target;
...@@ -2217,10 +2217,10 @@ static IrInstGen *ir_build_assert_zero(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -2217,10 +2217,10 @@ static IrInstGen *ir_build_assert_zero(IrAnalyze *ira, Scope *scope, AstNode *so
2217 return &instruction->base;2217 return &instruction->base;
2218}2218}
22192219
2220static IrInstGen *ir_build_assert_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node,2220static Stage1AirInst *ir_build_assert_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2221 IrInstGen *target)2221 Stage1AirInst *target)
2222{2222{
2223 IrInstGenAssertNonNull *instruction = ir_build_inst_gen<IrInstGenAssertNonNull>(&ira->new_irb,2223 Stage1AirInstAssertNonNull *instruction = ir_build_inst_gen<Stage1AirInstAssertNonNull>(&ira->new_irb,
2224 scope, source_node);2224 scope, source_node);
2225 instruction->base.value->type = ira->codegen->builtin_types.entry_void;2225 instruction->base.value->type = ira->codegen->builtin_types.entry_void;
2226 instruction->target = target;2226 instruction->target = target;
...@@ -2230,10 +2230,10 @@ static IrInstGen *ir_build_assert_non_null(IrAnalyze *ira, Scope *scope, AstNode...@@ -2230,10 +2230,10 @@ static IrInstGen *ir_build_assert_non_null(IrAnalyze *ira, Scope *scope, AstNode
2230 return &instruction->base;2230 return &instruction->base;
2231}2231}
22322232
2233static IrInstGenAlloca *ir_build_alloca_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,2233static Stage1AirInstAlloca *ir_build_alloca_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2234 uint32_t align, const char *name_hint)2234 uint32_t align, const char *name_hint)
2235{2235{
2236 IrInstGenAlloca *instruction = ir_create_inst_gen<IrInstGenAlloca>(&ira->new_irb,2236 Stage1AirInstAlloca *instruction = ir_create_inst_gen<Stage1AirInstAlloca>(&ira->new_irb,
2237 scope, source_node);2237 scope, source_node);
2238 instruction->align = align;2238 instruction->align = align;
2239 instruction->name_hint = name_hint;2239 instruction->name_hint = name_hint;
...@@ -2241,8 +2241,8 @@ static IrInstGenAlloca *ir_build_alloca_gen(IrAnalyze *ira, Scope *scope, AstNod...@@ -2241,8 +2241,8 @@ static IrInstGenAlloca *ir_build_alloca_gen(IrAnalyze *ira, Scope *scope, AstNod
2241 return instruction;2241 return instruction;
2242}2242}
22432243
2244static IrInstGen *ir_build_suspend_finish_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGenSuspendBegin *begin) {2244static Stage1AirInst *ir_build_suspend_finish_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInstSuspendBegin *begin) {
2245 IrInstGenSuspendFinish *inst = ir_build_inst_void<IrInstGenSuspendFinish>(&ira->new_irb,2245 Stage1AirInstSuspendFinish *inst = ir_build_inst_void<Stage1AirInstSuspendFinish>(&ira->new_irb,
2246 scope, source_node);2246 scope, source_node);
2247 inst->begin = begin;2247 inst->begin = begin;
22482248
...@@ -2251,10 +2251,10 @@ static IrInstGen *ir_build_suspend_finish_gen(IrAnalyze *ira, Scope *scope, AstN...@@ -2251,10 +2251,10 @@ static IrInstGen *ir_build_suspend_finish_gen(IrAnalyze *ira, Scope *scope, AstN
2251 return &inst->base;2251 return &inst->base;
2252}2252}
22532253
2254static IrInstGenAwait *ir_build_await_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,2254static Stage1AirInstAwait *ir_build_await_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2255 IrInstGen *frame, ZigType *result_type, IrInstGen *result_loc, bool is_nosuspend)2255 Stage1AirInst *frame, ZigType *result_type, Stage1AirInst *result_loc, bool is_nosuspend)
2256{2256{
2257 IrInstGenAwait *instruction = ir_build_inst_gen<IrInstGenAwait>(&ira->new_irb,2257 Stage1AirInstAwait *instruction = ir_build_inst_gen<Stage1AirInstAwait>(&ira->new_irb,
2258 scope, source_node);2258 scope, source_node);
2259 instruction->base.value->type = result_type;2259 instruction->base.value->type = result_type;
2260 instruction->frame = frame;2260 instruction->frame = frame;
...@@ -2267,8 +2267,8 @@ static IrInstGenAwait *ir_build_await_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -2267,8 +2267,8 @@ static IrInstGenAwait *ir_build_await_gen(IrAnalyze *ira, Scope *scope, AstNode
2267 return instruction;2267 return instruction;
2268}2268}
22692269
2270static IrInstGen *ir_build_resume_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *frame) {2270static Stage1AirInst *ir_build_resume_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *frame) {
2271 IrInstGenResume *instruction = ir_build_inst_void<IrInstGenResume>(&ira->new_irb,2271 Stage1AirInstResume *instruction = ir_build_inst_void<Stage1AirInstResume>(&ira->new_irb,
2272 scope, source_node);2272 scope, source_node);
2273 instruction->frame = frame;2273 instruction->frame = frame;
22742274
...@@ -2277,10 +2277,10 @@ static IrInstGen *ir_build_resume_gen(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -2277,10 +2277,10 @@ static IrInstGen *ir_build_resume_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
2277 return &instruction->base;2277 return &instruction->base;
2278}2278}
22792279
2280static IrInstGen *ir_build_spill_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand,2280static Stage1AirInst *ir_build_spill_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand,
2281 SpillId spill_id)2281 SpillId spill_id)
2282{2282{
2283 IrInstGenSpillBegin *instruction = ir_build_inst_void<IrInstGenSpillBegin>(&ira->new_irb,2283 Stage1AirInstSpillBegin *instruction = ir_build_inst_void<Stage1AirInstSpillBegin>(&ira->new_irb,
2284 scope, source_node);2284 scope, source_node);
2285 instruction->operand = operand;2285 instruction->operand = operand;
2286 instruction->spill_id = spill_id;2286 instruction->spill_id = spill_id;
...@@ -2290,10 +2290,10 @@ static IrInstGen *ir_build_spill_begin_gen(IrAnalyze *ira, Scope *scope, AstNode...@@ -2290,10 +2290,10 @@ static IrInstGen *ir_build_spill_begin_gen(IrAnalyze *ira, Scope *scope, AstNode
2290 return &instruction->base;2290 return &instruction->base;
2291}2291}
22922292
2293static IrInstGen *ir_build_spill_end_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGenSpillBegin *begin,2293static Stage1AirInst *ir_build_spill_end_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInstSpillBegin *begin,
2294 ZigType *result_type)2294 ZigType *result_type)
2295{2295{
2296 IrInstGenSpillEnd *instruction = ir_build_inst_gen<IrInstGenSpillEnd>(&ira->new_irb,2296 Stage1AirInstSpillEnd *instruction = ir_build_inst_gen<Stage1AirInstSpillEnd>(&ira->new_irb,
2297 scope, source_node);2297 scope, source_node);
2298 instruction->base.value->type = result_type;2298 instruction->base.value->type = result_type;
2299 instruction->begin = begin;2299 instruction->begin = begin;
...@@ -2303,10 +2303,10 @@ static IrInstGen *ir_build_spill_end_gen(IrAnalyze *ira, Scope *scope, AstNode *...@@ -2303,10 +2303,10 @@ static IrInstGen *ir_build_spill_end_gen(IrAnalyze *ira, Scope *scope, AstNode *
2303 return &instruction->base;2303 return &instruction->base;
2304}2304}
23052305
2306static IrInstGen *ir_build_vector_extract_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node,2306static Stage1AirInst *ir_build_vector_extract_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2307 IrInstGen *vector, IrInstGen *index)2307 Stage1AirInst *vector, Stage1AirInst *index)
2308{2308{
2309 IrInstGenVectorExtractElem *instruction = ir_build_inst_gen<IrInstGenVectorExtractElem>(2309 Stage1AirInstVectorExtractElem *instruction = ir_build_inst_gen<Stage1AirInstVectorExtractElem>(
2310 &ira->new_irb, scope, source_node);2310 &ira->new_irb, scope, source_node);
2311 instruction->base.value->type = vector->value->type->data.vector.elem_type;2311 instruction->base.value->type = vector->value->type->data.vector.elem_type;
2312 instruction->vector = vector;2312 instruction->vector = vector;
...@@ -2318,8 +2318,8 @@ static IrInstGen *ir_build_vector_extract_elem(IrAnalyze *ira, Scope *scope, Ast...@@ -2318,8 +2318,8 @@ static IrInstGen *ir_build_vector_extract_elem(IrAnalyze *ira, Scope *scope, Ast
2318 return &instruction->base;2318 return &instruction->base;
2319}2319}
23202320
2321static IrInstGen *ir_build_wasm_memory_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *index) {2321static Stage1AirInst *ir_build_wasm_memory_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *index) {
2322 IrInstGenWasmMemorySize *instruction = ir_build_inst_gen<IrInstGenWasmMemorySize>(&ira->new_irb,2322 Stage1AirInstWasmMemorySize *instruction = ir_build_inst_gen<Stage1AirInstWasmMemorySize>(&ira->new_irb,
2323 scope, source_node);2323 scope, source_node);
2324 instruction->base.value->type = ira->codegen->builtin_types.entry_u32;2324 instruction->base.value->type = ira->codegen->builtin_types.entry_u32;
2325 instruction->index = index;2325 instruction->index = index;
...@@ -2329,8 +2329,8 @@ static IrInstGen *ir_build_wasm_memory_size_gen(IrAnalyze *ira, Scope *scope, As...@@ -2329,8 +2329,8 @@ static IrInstGen *ir_build_wasm_memory_size_gen(IrAnalyze *ira, Scope *scope, As
2329 return &instruction->base;2329 return &instruction->base;
2330}2330}
23312331
2332static IrInstGen *ir_build_wasm_memory_grow_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *index, IrInstGen *delta) {2332static Stage1AirInst *ir_build_wasm_memory_grow_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *index, Stage1AirInst *delta) {
2333 IrInstGenWasmMemoryGrow *instruction = ir_build_inst_gen<IrInstGenWasmMemoryGrow>(&ira->new_irb,2333 Stage1AirInstWasmMemoryGrow *instruction = ir_build_inst_gen<Stage1AirInstWasmMemoryGrow>(&ira->new_irb,
2334 scope, source_node);2334 scope, source_node);
2335 instruction->base.value->type = ira->codegen->builtin_types.entry_i32;2335 instruction->base.value->type = ira->codegen->builtin_types.entry_i32;
2336 instruction->index = index;2336 instruction->index = index;
...@@ -2555,7 +2555,7 @@ static ErrorMsg *opt_ir_add_error_node(IrAnalyze *ira, CodeGen *codegen, AstNode...@@ -2555,7 +2555,7 @@ static ErrorMsg *opt_ir_add_error_node(IrAnalyze *ira, CodeGen *codegen, AstNode
2555 return add_node_error(codegen, source_node, msg);2555 return add_node_error(codegen, source_node, msg);
2556}2556}
25572557
2558static ErrorMsg *ir_add_error(IrAnalyze *ira, IrInstGen *source_instruction, Buf *msg) {2558static ErrorMsg *ir_add_error(IrAnalyze *ira, Stage1AirInst *source_instruction, Buf *msg) {
2559 return ir_add_error_node(ira, source_instruction->source_node, msg);2559 return ir_add_error_node(ira, source_instruction->source_node, msg);
2560}2560}
25612561
...@@ -2605,17 +2605,17 @@ ZigValue *const_ptr_pointee(IrAnalyze *ira, CodeGen *codegen, ZigValue *const_va...@@ -2605,17 +2605,17 @@ ZigValue *const_ptr_pointee(IrAnalyze *ira, CodeGen *codegen, ZigValue *const_va
2605}2605}
26062606
2607static Error ir_exec_scan_for_side_effects(CodeGen *codegen, Stage1Air *exec) {2607static Error ir_exec_scan_for_side_effects(CodeGen *codegen, Stage1Air *exec) {
2608 IrBasicBlockGen *bb = exec->basic_block_list.at(0);2608 Stage1AirBasicBlock *bb = exec->basic_block_list.at(0);
2609 for (size_t i = 0; i < bb->instruction_list.length; i += 1) {2609 for (size_t i = 0; i < bb->instruction_list.length; i += 1) {
2610 IrInstGen *instruction = bb->instruction_list.at(i);2610 Stage1AirInst *instruction = bb->instruction_list.at(i);
2611 if (instruction->id == IrInstGenIdReturn) {2611 if (instruction->id == Stage1AirInstIdReturn) {
2612 return ErrorNone;2612 return ErrorNone;
2613 } else if (ir_inst_gen_has_side_effects(instruction)) {2613 } else if (ir_inst_gen_has_side_effects(instruction)) {
2614 if (instr_is_comptime(instruction)) {2614 if (instr_is_comptime(instruction)) {
2615 switch (instruction->id) {2615 switch (instruction->id) {
2616 case IrInstGenIdUnwrapErrPayload:2616 case Stage1AirInstIdUnwrapErrPayload:
2617 case IrInstGenIdOptionalUnwrapPtr:2617 case Stage1AirInstIdOptionalUnwrapPtr:
2618 case IrInstGenIdUnionFieldPtr:2618 case Stage1AirInstIdUnionFieldPtr:
2619 continue;2619 continue;
2620 default:2620 default:
2621 break;2621 break;
...@@ -2633,7 +2633,7 @@ static Error ir_exec_scan_for_side_effects(CodeGen *codegen, Stage1Air *exec) {...@@ -2633,7 +2633,7 @@ static Error ir_exec_scan_for_side_effects(CodeGen *codegen, Stage1Air *exec) {
2633 zig_unreachable();2633 zig_unreachable();
2634}2634}
26352635
2636static bool ir_emit_global_runtime_side_effect(IrAnalyze *ira, IrInstSrc* source_instruction) {2636static bool ir_emit_global_runtime_side_effect(IrAnalyze *ira, Stage1ZirInst* source_instruction) {
2637 if (ir_should_inline(ira->zir, source_instruction->scope)) {2637 if (ir_should_inline(ira->zir, source_instruction->scope)) {
2638 ir_add_error_node(ira, source_instruction->source_node, buf_sprintf("unable to evaluate constant expression"));2638 ir_add_error_node(ira, source_instruction->source_node, buf_sprintf("unable to evaluate constant expression"));
2639 return false;2639 return false;
...@@ -3423,7 +3423,7 @@ static void value_to_bigfloat(BigFloat *out, ZigValue *val) {...@@ -3423,7 +3423,7 @@ static void value_to_bigfloat(BigFloat *out, ZigValue *val) {
3423 }3423 }
3424}3424}
34253425
3426static bool ir_num_lit_fits_in_other_type(IrAnalyze *ira, IrInstGen *instruction, ZigType *other_type,3426static bool ir_num_lit_fits_in_other_type(IrAnalyze *ira, Stage1AirInst *instruction, ZigType *other_type,
3427 bool explicit_cast)3427 bool explicit_cast)
3428{3428{
3429 if (type_is_invalid(other_type)) {3429 if (type_is_invalid(other_type)) {
...@@ -4185,11 +4185,11 @@ static void update_errors_helper(CodeGen *g, ErrorTableEntry ***errors, size_t *...@@ -4185,11 +4185,11 @@ static void update_errors_helper(CodeGen *g, ErrorTableEntry ***errors, size_t *
4185}4185}
41864186
4187static ZigType *ir_resolve_peer_types(IrAnalyze *ira, AstNode *source_node, ZigType *expected_type,4187static ZigType *ir_resolve_peer_types(IrAnalyze *ira, AstNode *source_node, ZigType *expected_type,
4188 IrInstGen **instructions, size_t instruction_count)4188 Stage1AirInst **instructions, size_t instruction_count)
4189{4189{
4190 Error err;4190 Error err;
4191 assert(instruction_count >= 1);4191 assert(instruction_count >= 1);
4192 IrInstGen *prev_inst;4192 Stage1AirInst *prev_inst;
4193 size_t i = 0;4193 size_t i = 0;
4194 for (;;) {4194 for (;;) {
4195 prev_inst = instructions[i];4195 prev_inst = instructions[i];
...@@ -4231,7 +4231,7 @@ static ZigType *ir_resolve_peer_types(IrAnalyze *ira, AstNode *source_node, ZigT...@@ -4231,7 +4231,7 @@ static ZigType *ir_resolve_peer_types(IrAnalyze *ira, AstNode *source_node, ZigT
4231 bool make_the_slice_const = false;4231 bool make_the_slice_const = false;
4232 bool make_the_pointer_const = false;4232 bool make_the_pointer_const = false;
4233 for (; i < instruction_count; i += 1) {4233 for (; i < instruction_count; i += 1) {
4234 IrInstGen *cur_inst = instructions[i];4234 Stage1AirInst *cur_inst = instructions[i];
4235 ZigType *cur_type = cur_inst->value->type;4235 ZigType *cur_type = cur_inst->value->type;
4236 ZigType *prev_type = prev_inst->value->type;4236 ZigType *prev_type = prev_inst->value->type;
42374237
...@@ -5085,36 +5085,36 @@ static bool eval_const_expr_implicit_cast(IrAnalyze *ira, Scope *scope, AstNode...@@ -5085,36 +5085,36 @@ static bool eval_const_expr_implicit_cast(IrAnalyze *ira, Scope *scope, AstNode
5085 return true;5085 return true;
5086}5086}
50875087
5088static IrInstGen *ir_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {5088static Stage1AirInst *ir_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
5089 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,5089 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
5090 scope, source_node);5090 scope, source_node);
5091 IrInstGen *new_instruction = &const_instruction->base;5091 Stage1AirInst *new_instruction = &const_instruction->base;
5092 new_instruction->value->type = ty;5092 new_instruction->value->type = ty;
5093 new_instruction->value->special = ConstValSpecialStatic;5093 new_instruction->value->special = ConstValSpecialStatic;
5094 ira->new_irb.constants.append(&heap::c_allocator, const_instruction);5094 ira->new_irb.constants.append(&heap::c_allocator, const_instruction);
5095 return new_instruction;5095 return new_instruction;
5096}5096}
50975097
5098static IrInstGen *ir_const_noval(IrAnalyze *ira, Scope *scope, AstNode *source_node) {5098static Stage1AirInst *ir_const_noval(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
5099 IrInstGenConst *const_instruction = ir_create_inst_noval<IrInstGenConst>(&ira->new_irb,5099 Stage1AirInstConst *const_instruction = ir_create_inst_noval<Stage1AirInstConst>(&ira->new_irb,
5100 scope, source_node);5100 scope, source_node);
5101 ira->new_irb.constants.append(&heap::c_allocator, const_instruction);5101 ira->new_irb.constants.append(&heap::c_allocator, const_instruction);
5102 return &const_instruction->base;5102 return &const_instruction->base;
5103}5103}
51045104
5105// This function initializes the new IrInstGen with the provided ZigValue,5105// This function initializes the new Stage1AirInst with the provided ZigValue,
5106// rather than creating a new one.5106// rather than creating a new one.
5107static IrInstGen *ir_const_move(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigValue *val) {5107static Stage1AirInst *ir_const_move(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigValue *val) {
5108 IrInstGen *result = ir_const_noval(ira, scope, source_node);5108 Stage1AirInst *result = ir_const_noval(ira, scope, source_node);
5109 result->value = val;5109 result->value = val;
5110 return result;5110 return result;
5111}5111}
51125112
5113static IrInstGen *ir_resolve_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,5113static Stage1AirInst *ir_resolve_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
5114 ZigType *wanted_type, CastOp cast_op)5114 ZigType *wanted_type, CastOp cast_op)
5115{5115{
5116 if (instr_is_comptime(value) || !type_has_bits(ira->codegen, wanted_type)) {5116 if (instr_is_comptime(value) || !type_has_bits(ira->codegen, wanted_type)) {
5117 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);5117 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
5118 ZigValue *val = ir_resolve_const(ira, value, UndefBad);5118 ZigValue *val = ir_resolve_const(ira, value, UndefBad);
5119 if (val == nullptr)5119 if (val == nullptr)
5120 return ira->codegen->invalid_inst_gen;5120 return ira->codegen->invalid_inst_gen;
...@@ -5131,8 +5131,8 @@ static IrInstGen *ir_resolve_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -5131,8 +5131,8 @@ static IrInstGen *ir_resolve_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
5131 }5131 }
5132}5132}
51335133
5134static IrInstGen *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira,5134static Stage1AirInst *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira,
5135 Scope *scope, AstNode *source_node, IrInstGen *value, ZigType *wanted_type)5135 Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *wanted_type)
5136{5136{
5137 src_assert(value->value->type->id == ZigTypeIdPointer, source_node);5137 src_assert(value->value->type->id == ZigTypeIdPointer, source_node);
51385138
...@@ -5157,7 +5157,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira,...@@ -5157,7 +5157,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira,
5157 if (pointee == nullptr)5157 if (pointee == nullptr)
5158 return ira->codegen->invalid_inst_gen;5158 return ira->codegen->invalid_inst_gen;
5159 if (pointee->special != ConstValSpecialRuntime) {5159 if (pointee->special != ConstValSpecialRuntime) {
5160 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);5160 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
5161 result->value->data.x_ptr.special = ConstPtrSpecialBaseArray;5161 result->value->data.x_ptr.special = ConstPtrSpecialBaseArray;
5162 result->value->data.x_ptr.mut = val->data.x_ptr.mut;5162 result->value->data.x_ptr.mut = val->data.x_ptr.mut;
5163 result->value->data.x_ptr.data.base_array.array_val = pointee;5163 result->value->data.x_ptr.data.base_array.array_val = pointee;
...@@ -5170,8 +5170,8 @@ static IrInstGen *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira,...@@ -5170,8 +5170,8 @@ static IrInstGen *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira,
5170 wanted_type, value, CastOpBitCast);5170 wanted_type, value, CastOpBitCast);
5171}5171}
51725172
5173static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node,5173static Stage1AirInst *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5174 IrInstGen *array_ptr, ZigType *wanted_type, ResultLoc *result_loc)5174 Stage1AirInst *array_ptr, ZigType *wanted_type, ResultLoc *result_loc)
5175{5175{
5176 Error err;5176 Error err;
51775177
...@@ -5190,7 +5190,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,...@@ -5190,7 +5190,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
5190 // undef_array->special = ConstValSpecialUndef;5190 // undef_array->special = ConstValSpecialUndef;
5191 // undef_array->type = array_type;5191 // undef_array->type = array_type;
51925192
5193 // IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);5193 // Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
5194 // init_const_slice(ira->codegen, result->value, undef_array, 0, 0, false, nullptr);5194 // init_const_slice(ira->codegen, result->value, undef_array, 0, 0, false, nullptr);
5195 // result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = ConstPtrMutComptimeConst;5195 // result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = ConstPtrMutComptimeConst;
5196 // result->value->type = wanted_type;5196 // result->value->type = wanted_type;
...@@ -5217,7 +5217,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,...@@ -5217,7 +5217,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
5217 undef_array->special = ConstValSpecialUndef;5217 undef_array->special = ConstValSpecialUndef;
5218 undef_array->type = array_type;5218 undef_array->type = array_type;
52195219
5220 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);5220 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
5221 init_const_slice(ira->codegen, result->value, undef_array, 0, 0, false, nullptr);5221 init_const_slice(ira->codegen, result->value, undef_array, 0, 0, false, nullptr);
5222 result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = ConstPtrMutComptimeConst;5222 result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = ConstPtrMutComptimeConst;
5223 result->value->type = wanted_type;5223 result->value->type = wanted_type;
...@@ -5228,7 +5228,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,...@@ -5228,7 +5228,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
5228 if (array_ptr_val->data.x_ptr.special == ConstPtrSpecialSubArray) {5228 if (array_ptr_val->data.x_ptr.special == ConstPtrSpecialSubArray) {
5229 ZigValue *array_val = array_ptr_val->data.x_ptr.data.base_array.array_val;5229 ZigValue *array_val = array_ptr_val->data.x_ptr.data.base_array.array_val;
5230 if (array_val->special != ConstValSpecialRuntime) {5230 if (array_val->special != ConstValSpecialRuntime) {
5231 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);5231 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
5232 init_const_slice(ira->codegen, result->value, array_val,5232 init_const_slice(ira->codegen, result->value, array_val,
5233 array_ptr_val->data.x_ptr.data.base_array.elem_index,5233 array_ptr_val->data.x_ptr.data.base_array.elem_index,
5234 array_type->data.array.len, wanted_const, nullptr);5234 array_type->data.array.len, wanted_const, nullptr);
...@@ -5243,7 +5243,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,...@@ -5243,7 +5243,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
5243 if (pointee->special != ConstValSpecialRuntime) {5243 if (pointee->special != ConstValSpecialRuntime) {
5244 assert(array_ptr_val->type->id == ZigTypeIdPointer);5244 assert(array_ptr_val->type->id == ZigTypeIdPointer);
52455245
5246 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);5246 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
5247 init_const_slice(ira->codegen, result->value, pointee, 0, array_type->data.array.len, wanted_const, nullptr);5247 init_const_slice(ira->codegen, result->value, pointee, 0, array_type->data.array.len, wanted_const, nullptr);
5248 result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = array_ptr_val->data.x_ptr.mut;5248 result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = array_ptr_val->data.x_ptr.mut;
5249 result->value->type = wanted_type;5249 result->value->type = wanted_type;
...@@ -5253,7 +5253,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,...@@ -5253,7 +5253,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
5253 }5253 }
52545254
5255 if (result_loc == nullptr) result_loc = no_result_loc();5255 if (result_loc == nullptr) result_loc = no_result_loc();
5256 IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr,5256 Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr,
5257 result_loc, wanted_type, nullptr, true, true);5257 result_loc, wanted_type, nullptr, true, true);
5258 if (type_is_invalid(result_loc_inst->value->type) ||5258 if (type_is_invalid(result_loc_inst->value->type) ||
5259 result_loc_inst->value->type->id == ZigTypeIdUnreachable)5259 result_loc_inst->value->type->id == ZigTypeIdUnreachable)
...@@ -5263,7 +5263,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,...@@ -5263,7 +5263,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
5263 return ir_build_ptr_of_array_to_slice(ira, scope, source_node, wanted_type, array_ptr, result_loc_inst);5263 return ir_build_ptr_of_array_to_slice(ira, scope, source_node, wanted_type, array_ptr, result_loc_inst);
5264}5264}
52655265
5266static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, IrInstSrc *ref_old_instruction) {5266static Stage1AirBasicBlock *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirInst *ref_old_instruction) {
5267 assert(old_bb);5267 assert(old_bb);
52685268
5269 if (old_bb->child) {5269 if (old_bb->child) {
...@@ -5272,15 +5272,15 @@ static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_b...@@ -5272,15 +5272,15 @@ static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_b
5272 }5272 }
5273 }5273 }
52745274
5275 IrBasicBlockGen *new_bb = ir_build_bb_from(ira, old_bb);5275 Stage1AirBasicBlock *new_bb = ir_build_bb_from(ira, old_bb);
5276 new_bb->ref_instruction = ref_old_instruction;5276 new_bb->ref_instruction = ref_old_instruction;
52775277
5278 return new_bb;5278 return new_bb;
5279}5279}
52805280
5281static IrBasicBlockGen *ir_get_new_bb_runtime(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, IrInstSrc *ref_old_instruction) {5281static Stage1AirBasicBlock *ir_get_new_bb_runtime(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirInst *ref_old_instruction) {
5282 assert(ref_old_instruction != nullptr);5282 assert(ref_old_instruction != nullptr);
5283 IrBasicBlockGen *new_bb = ir_get_new_bb(ira, old_bb, ref_old_instruction);5283 Stage1AirBasicBlock *new_bb = ir_get_new_bb(ira, old_bb, ref_old_instruction);
5284 if (new_bb->must_be_comptime_source_node != nullptr) {5284 if (new_bb->must_be_comptime_source_node != nullptr) {
5285 ErrorMsg *msg = ir_add_error_node(ira, ref_old_instruction->source_node,5285 ErrorMsg *msg = ir_add_error_node(ira, ref_old_instruction->source_node,
5286 buf_sprintf("control flow attempts to use compile-time variable at runtime"));5286 buf_sprintf("control flow attempts to use compile-time variable at runtime"));
...@@ -5301,7 +5301,7 @@ static void ir_start_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirBa...@@ -5301,7 +5301,7 @@ static void ir_start_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirBa
5301 ira->old_bb_index = old_bb->index;5301 ira->old_bb_index = old_bb->index;
5302}5302}
53035303
5304static IrInstGen *ira_suspend(IrAnalyze *ira, IrInstSrc *old_instruction, Stage1ZirBasicBlock *next_bb,5304static Stage1AirInst *ira_suspend(IrAnalyze *ira, Stage1ZirInst *old_instruction, Stage1ZirBasicBlock *next_bb,
5305 IrSuspendPosition *suspend_pos)5305 IrSuspendPosition *suspend_pos)
5306{5306{
5307 if (ira->codegen->verbose_ir) {5307 if (ira->codegen->verbose_ir) {
...@@ -5331,7 +5331,7 @@ static IrInstGen *ira_suspend(IrAnalyze *ira, IrInstSrc *old_instruction, Stage1...@@ -5331,7 +5331,7 @@ static IrInstGen *ira_suspend(IrAnalyze *ira, IrInstSrc *old_instruction, Stage1
5331 return ira->codegen->unreach_instruction;5331 return ira->codegen->unreach_instruction;
5332}5332}
53335333
5334static IrInstGen *ira_resume(IrAnalyze *ira) {5334static Stage1AirInst *ira_resume(IrAnalyze *ira) {
5335 IrSuspendPosition pos = ira->resume_stack.pop();5335 IrSuspendPosition pos = ira->resume_stack.pop();
5336 if (ira->codegen->verbose_ir) {5336 if (ira->codegen->verbose_ir) {
5337 fprintf(stderr, "resume (%zu,%zu) ", pos.basic_block_index, pos.instruction_index);5337 fprintf(stderr, "resume (%zu,%zu) ", pos.basic_block_index, pos.instruction_index);
...@@ -5414,7 +5414,7 @@ static void ir_finish_bb(IrAnalyze *ira) {...@@ -5414,7 +5414,7 @@ static void ir_finish_bb(IrAnalyze *ira) {
5414 ir_start_next_bb(ira);5414 ir_start_next_bb(ira);
5415}5415}
54165416
5417static IrInstGen *ir_unreach_error(IrAnalyze *ira) {5417static Stage1AirInst *ir_unreach_error(IrAnalyze *ira) {
5418 ira->old_bb_index = SIZE_MAX;5418 ira->old_bb_index = SIZE_MAX;
5419 if (ira->new_irb.exec->first_err_trace_msg == nullptr) {5419 if (ira->new_irb.exec->first_err_trace_msg == nullptr) {
5420 ira->new_irb.exec->first_err_trace_msg = ira->codegen->trace_err;5420 ira->new_irb.exec->first_err_trace_msg = ira->codegen->trace_err;
...@@ -5441,7 +5441,7 @@ static bool ir_emit_backward_branch(IrAnalyze *ira, AstNode* source_node) {...@@ -5441,7 +5441,7 @@ static bool ir_emit_backward_branch(IrAnalyze *ira, AstNode* source_node) {
5441 return true;5441 return true;
5442}5442}
54435443
5444static IrInstGen *ir_inline_bb(IrAnalyze *ira, AstNode* source_node, Stage1ZirBasicBlock *old_bb) {5444static Stage1AirInst *ir_inline_bb(IrAnalyze *ira, AstNode* source_node, Stage1ZirBasicBlock *old_bb) {
5445 if (old_bb->debug_id <= ira->zir_current_basic_block->debug_id) {5445 if (old_bb->debug_id <= ira->zir_current_basic_block->debug_id) {
5446 if (!ir_emit_backward_branch(ira, source_node))5446 if (!ir_emit_backward_branch(ira, source_node))
5447 return ir_unreach_error(ira);5447 return ir_unreach_error(ira);
...@@ -5452,14 +5452,14 @@ static IrInstGen *ir_inline_bb(IrAnalyze *ira, AstNode* source_node, Stage1ZirBa...@@ -5452,14 +5452,14 @@ static IrInstGen *ir_inline_bb(IrAnalyze *ira, AstNode* source_node, Stage1ZirBa
5452 return ira->codegen->unreach_instruction;5452 return ira->codegen->unreach_instruction;
5453}5453}
54545454
5455static IrInstGen *ir_finish_anal(IrAnalyze *ira, IrInstGen *instruction) {5455static Stage1AirInst *ir_finish_anal(IrAnalyze *ira, Stage1AirInst *instruction) {
5456 if (instruction->value->type->id == ZigTypeIdUnreachable)5456 if (instruction->value->type->id == ZigTypeIdUnreachable)
5457 ir_finish_bb(ira);5457 ir_finish_bb(ira);
5458 return instruction;5458 return instruction;
5459}5459}
54605460
5461static IrInstGen *ir_const_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry) {5461static Stage1AirInst *ir_const_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry) {
5462 IrInstGen *result = ir_const(ira, scope, source_node, fn_entry->type_entry);5462 Stage1AirInst *result = ir_const(ira, scope, source_node, fn_entry->type_entry);
5463 result->value->special = ConstValSpecialStatic;5463 result->value->special = ConstValSpecialStatic;
5464 result->value->data.x_ptr.data.fn.fn_entry = fn_entry;5464 result->value->data.x_ptr.data.fn.fn_entry = fn_entry;
5465 result->value->data.x_ptr.mut = ConstPtrMutComptimeConst;5465 result->value->data.x_ptr.mut = ConstPtrMutComptimeConst;
...@@ -5467,62 +5467,62 @@ static IrInstGen *ir_const_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node...@@ -5467,62 +5467,62 @@ static IrInstGen *ir_const_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node
5467 return result;5467 return result;
5468}5468}
54695469
5470static IrInstGen *ir_const_bound_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node,5470static Stage1AirInst *ir_const_bound_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5471 ZigFn *fn_entry, IrInstGen *first_arg, AstNode *first_arg_src)5471 ZigFn *fn_entry, Stage1AirInst *first_arg, AstNode *first_arg_src)
5472{5472{
5473 // This is unfortunately required to avoid improperly freeing first_arg_src5473 // This is unfortunately required to avoid improperly freeing first_arg_src
5474 ira_ref(ira);5474 ira_ref(ira);
54755475
5476 IrInstGen *result = ir_const(ira, scope, source_node, get_bound_fn_type(ira->codegen, fn_entry));5476 Stage1AirInst *result = ir_const(ira, scope, source_node, get_bound_fn_type(ira->codegen, fn_entry));
5477 result->value->data.x_bound_fn.fn = fn_entry;5477 result->value->data.x_bound_fn.fn = fn_entry;
5478 result->value->data.x_bound_fn.first_arg = first_arg;5478 result->value->data.x_bound_fn.first_arg = first_arg;
5479 result->value->data.x_bound_fn.first_arg_src = first_arg_src;5479 result->value->data.x_bound_fn.first_arg_src = first_arg_src;
5480 return result;5480 return result;
5481}5481}
54825482
5483static IrInstGen *ir_const_type(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {5483static Stage1AirInst *ir_const_type(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
5484 IrInstGen *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_type);5484 Stage1AirInst *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_type);
5485 result->value->data.x_type = ty;5485 result->value->data.x_type = ty;
5486 return result;5486 return result;
5487}5487}
54885488
5489static IrInstGen *ir_const_bool(IrAnalyze *ira, Scope *scope, AstNode *source_node, bool value) {5489static Stage1AirInst *ir_const_bool(IrAnalyze *ira, Scope *scope, AstNode *source_node, bool value) {
5490 IrInstGen *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_bool);5490 Stage1AirInst *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_bool);
5491 result->value->data.x_bool = value;5491 result->value->data.x_bool = value;
5492 return result;5492 return result;
5493}5493}
54945494
5495static IrInstGen *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {5495static Stage1AirInst *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
5496 IrInstGen *result = ir_const(ira, scope, source_node, ty);5496 Stage1AirInst *result = ir_const(ira, scope, source_node, ty);
5497 result->value->special = ConstValSpecialUndef;5497 result->value->special = ConstValSpecialUndef;
5498 return result;5498 return result;
5499}5499}
55005500
5501static IrInstGen *ir_const_unreachable(IrAnalyze *ira, Scope *scope, AstNode *source_node) {5501static Stage1AirInst *ir_const_unreachable(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
5502 IrInstGen *result = ir_const_noval(ira, scope, source_node);5502 Stage1AirInst *result = ir_const_noval(ira, scope, source_node);
5503 result->value = ira->codegen->intern.for_unreachable();5503 result->value = ira->codegen->intern.for_unreachable();
5504 return result;5504 return result;
5505}5505}
55065506
5507static IrInstGen *ir_const_void(IrAnalyze *ira, Scope *scope, AstNode *source_node) {5507static Stage1AirInst *ir_const_void(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
5508 IrInstGen *result = ir_const_noval(ira, scope, source_node);5508 Stage1AirInst *result = ir_const_noval(ira, scope, source_node);
5509 result->value = ira->codegen->intern.for_void();5509 result->value = ira->codegen->intern.for_void();
5510 return result;5510 return result;
5511}5511}
55125512
5513static IrInstGen *ir_const_unsigned(IrAnalyze *ira, Scope *scope, AstNode *source_node, uint64_t value) {5513static Stage1AirInst *ir_const_unsigned(IrAnalyze *ira, Scope *scope, AstNode *source_node, uint64_t value) {
5514 IrInstGen *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_num_lit_int);5514 Stage1AirInst *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_num_lit_int);
5515 bigint_init_unsigned(&result->value->data.x_bigint, value);5515 bigint_init_unsigned(&result->value->data.x_bigint, value);
5516 return result;5516 return result;
5517}5517}
55185518
5519static IrInstGen *ir_get_const_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,5519static Stage1AirInst *ir_get_const_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5520 ZigValue *pointee, ZigType *pointee_type,5520 ZigValue *pointee, ZigType *pointee_type,
5521 ConstPtrMut ptr_mut, bool ptr_is_const, bool ptr_is_volatile, uint32_t ptr_align)5521 ConstPtrMut ptr_mut, bool ptr_is_const, bool ptr_is_volatile, uint32_t ptr_align)
5522{5522{
5523 ZigType *ptr_type = get_pointer_to_type_extra(ira->codegen, pointee_type,5523 ZigType *ptr_type = get_pointer_to_type_extra(ira->codegen, pointee_type,
5524 ptr_is_const, ptr_is_volatile, PtrLenSingle, ptr_align, 0, 0, false);5524 ptr_is_const, ptr_is_volatile, PtrLenSingle, ptr_align, 0, 0, false);
5525 IrInstGen *const_instr = ir_const(ira, scope, source_node, ptr_type);5525 Stage1AirInst *const_instr = ir_const(ira, scope, source_node, ptr_type);
5526 ZigValue *const_val = const_instr->value;5526 ZigValue *const_val = const_instr->value;
5527 const_val->data.x_ptr.special = ConstPtrSpecialRef;5527 const_val->data.x_ptr.special = ConstPtrSpecialRef;
5528 const_val->data.x_ptr.mut = ptr_mut;5528 const_val->data.x_ptr.mut = ptr_mut;
...@@ -5564,7 +5564,7 @@ static Error ir_resolve_const_val(CodeGen *codegen, Stage1Air *exec, AstNode *so...@@ -5564,7 +5564,7 @@ static Error ir_resolve_const_val(CodeGen *codegen, Stage1Air *exec, AstNode *so
5564 }5564 }
5565}5565}
55665566
5567static ZigValue *ir_resolve_const(IrAnalyze *ira, IrInstGen *value, UndefAllowed undef_allowed) {5567static ZigValue *ir_resolve_const(IrAnalyze *ira, Stage1AirInst *value, UndefAllowed undef_allowed) {
5568 Error err;5568 Error err;
5569 if ((err = ir_resolve_const_val(ira->codegen, ira->new_irb.exec, value->source_node,5569 if ((err = ir_resolve_const_val(ira->codegen, ira->new_irb.exec, value->source_node,
5570 value->value, undef_allowed)))5570 value->value, undef_allowed)))
...@@ -5640,7 +5640,7 @@ Error ir_eval_const_value(CodeGen *codegen, Scope *scope, AstNode *node,...@@ -5640,7 +5640,7 @@ Error ir_eval_const_value(CodeGen *codegen, Scope *scope, AstNode *node,
5640 return ErrorNone;5640 return ErrorNone;
5641}5641}
56425642
5643static ErrorTableEntry *ir_resolve_error(IrAnalyze *ira, IrInstGen *err_value) {5643static ErrorTableEntry *ir_resolve_error(IrAnalyze *ira, Stage1AirInst *err_value) {
5644 if (type_is_invalid(err_value->value->type))5644 if (type_is_invalid(err_value->value->type))
5645 return nullptr;5645 return nullptr;
56465646
...@@ -5669,7 +5669,7 @@ static ZigType *ir_resolve_const_type(CodeGen *codegen, Stage1Air *exec, AstNode...@@ -5669,7 +5669,7 @@ static ZigType *ir_resolve_const_type(CodeGen *codegen, Stage1Air *exec, AstNode
5669 return val->data.x_type;5669 return val->data.x_type;
5670}5670}
56715671
5672static ZigValue *ir_resolve_type_lazy(IrAnalyze *ira, IrInstGen *type_value) {5672static ZigValue *ir_resolve_type_lazy(IrAnalyze *ira, Stage1AirInst *type_value) {
5673 if (type_is_invalid(type_value->value->type))5673 if (type_is_invalid(type_value->value->type))
5674 return nullptr;5674 return nullptr;
56755675
...@@ -5689,7 +5689,7 @@ static ZigValue *ir_resolve_type_lazy(IrAnalyze *ira, IrInstGen *type_value) {...@@ -5689,7 +5689,7 @@ static ZigValue *ir_resolve_type_lazy(IrAnalyze *ira, IrInstGen *type_value) {
5689 return type_value->value;5689 return type_value->value;
5690}5690}
56915691
5692static ZigType *ir_resolve_type(IrAnalyze *ira, IrInstGen *type_value) {5692static ZigType *ir_resolve_type(IrAnalyze *ira, Stage1AirInst *type_value) {
5693 ZigValue *val = ir_resolve_type_lazy(ira, type_value);5693 ZigValue *val = ir_resolve_type_lazy(ira, type_value);
5694 if (val == nullptr)5694 if (val == nullptr)
5695 return ira->codegen->builtin_types.entry_invalid;5695 return ira->codegen->builtin_types.entry_invalid;
...@@ -5711,7 +5711,7 @@ static Error ir_validate_vector_elem_type(IrAnalyze *ira, AstNode *source_node,...@@ -5711,7 +5711,7 @@ static Error ir_validate_vector_elem_type(IrAnalyze *ira, AstNode *source_node,
5711 return ErrorNone;5711 return ErrorNone;
5712}5712}
57135713
5714static ZigType *ir_resolve_vector_elem_type(IrAnalyze *ira, IrInstGen *elem_type_value) {5714static ZigType *ir_resolve_vector_elem_type(IrAnalyze *ira, Stage1AirInst *elem_type_value) {
5715 Error err;5715 Error err;
5716 ZigType *elem_type = ir_resolve_type(ira, elem_type_value);5716 ZigType *elem_type = ir_resolve_type(ira, elem_type_value);
5717 if (type_is_invalid(elem_type))5717 if (type_is_invalid(elem_type))
...@@ -5721,7 +5721,7 @@ static ZigType *ir_resolve_vector_elem_type(IrAnalyze *ira, IrInstGen *elem_type...@@ -5721,7 +5721,7 @@ static ZigType *ir_resolve_vector_elem_type(IrAnalyze *ira, IrInstGen *elem_type
5721 return elem_type;5721 return elem_type;
5722}5722}
57235723
5724static ZigType *ir_resolve_int_type(IrAnalyze *ira, IrInstGen *type_value) {5724static ZigType *ir_resolve_int_type(IrAnalyze *ira, Stage1AirInst *type_value) {
5725 ZigType *ty = ir_resolve_type(ira, type_value);5725 ZigType *ty = ir_resolve_type(ira, type_value);
5726 if (type_is_invalid(ty))5726 if (type_is_invalid(ty))
5727 return ira->codegen->builtin_types.entry_invalid;5727 return ira->codegen->builtin_types.entry_invalid;
...@@ -5742,7 +5742,7 @@ static ZigType *ir_resolve_int_type(IrAnalyze *ira, IrInstGen *type_value) {...@@ -5742,7 +5742,7 @@ static ZigType *ir_resolve_int_type(IrAnalyze *ira, IrInstGen *type_value) {
5742 return ty;5742 return ty;
5743}5743}
57445744
5745static ZigType *ir_resolve_error_set_type(IrAnalyze *ira, AstNode *op_source, IrInstGen *type_value) {5745static ZigType *ir_resolve_error_set_type(IrAnalyze *ira, AstNode *op_source, Stage1AirInst *type_value) {
5746 if (type_is_invalid(type_value->value->type))5746 if (type_is_invalid(type_value->value->type))
5747 return ira->codegen->builtin_types.entry_invalid;5747 return ira->codegen->builtin_types.entry_invalid;
57485748
...@@ -5770,7 +5770,7 @@ static ZigType *ir_resolve_error_set_type(IrAnalyze *ira, AstNode *op_source, Ir...@@ -5770,7 +5770,7 @@ static ZigType *ir_resolve_error_set_type(IrAnalyze *ira, AstNode *op_source, Ir
5770 return result_type;5770 return result_type;
5771}5771}
57725772
5773static ZigFn *ir_resolve_fn(IrAnalyze *ira, IrInstGen *fn_value) {5773static ZigFn *ir_resolve_fn(IrAnalyze *ira, Stage1AirInst *fn_value) {
5774 if (type_is_invalid(fn_value->value->type))5774 if (type_is_invalid(fn_value->value->type))
5775 return nullptr;5775 return nullptr;
57765776
...@@ -5791,14 +5791,14 @@ static ZigFn *ir_resolve_fn(IrAnalyze *ira, IrInstGen *fn_value) {...@@ -5791,14 +5791,14 @@ static ZigFn *ir_resolve_fn(IrAnalyze *ira, IrInstGen *fn_value) {
5791 return const_val->data.x_ptr.data.fn.fn_entry;5791 return const_val->data.x_ptr.data.fn.fn_entry;
5792}5792}
57935793
5794static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node,5794static Stage1AirInst *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5795 IrInstGen *value, ZigType *wanted_type, ResultLoc *result_loc)5795 Stage1AirInst *value, ZigType *wanted_type, ResultLoc *result_loc)
5796{5796{
5797 assert(wanted_type->id == ZigTypeIdOptional);5797 assert(wanted_type->id == ZigTypeIdOptional);
57985798
5799 if (instr_is_comptime(value)) {5799 if (instr_is_comptime(value)) {
5800 ZigType *payload_type = wanted_type->data.maybe.child_type;5800 ZigType *payload_type = wanted_type->data.maybe.child_type;
5801 IrInstGen *casted_payload = ir_implicit_cast(ira, value, payload_type);5801 Stage1AirInst *casted_payload = ir_implicit_cast(ira, value, payload_type);
5802 if (type_is_invalid(casted_payload->value->type))5802 if (type_is_invalid(casted_payload->value->type))
5803 return ira->codegen->invalid_inst_gen;5803 return ira->codegen->invalid_inst_gen;
58045804
...@@ -5806,7 +5806,7 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode...@@ -5806,7 +5806,7 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode
5806 if (!val)5806 if (!val)
5807 return ira->codegen->invalid_inst_gen;5807 return ira->codegen->invalid_inst_gen;
58085808
5809 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,5809 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
5810 scope, source_node);5810 scope, source_node);
5811 const_instruction->base.value->special = ConstValSpecialStatic;5811 const_instruction->base.value->special = ConstValSpecialStatic;
5812 if (types_have_same_zig_comptime_repr(ira->codegen, wanted_type, payload_type)) {5812 if (types_have_same_zig_comptime_repr(ira->codegen, wanted_type, payload_type)) {
...@@ -5821,7 +5821,7 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode...@@ -5821,7 +5821,7 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode
5821 if (result_loc == nullptr && handle_is_ptr(ira->codegen, wanted_type)) {5821 if (result_loc == nullptr && handle_is_ptr(ira->codegen, wanted_type)) {
5822 result_loc = no_result_loc();5822 result_loc = no_result_loc();
5823 }5823 }
5824 IrInstGen *result_loc_inst = nullptr;5824 Stage1AirInst *result_loc_inst = nullptr;
5825 if (result_loc != nullptr) {5825 if (result_loc != nullptr) {
5826 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true);5826 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true);
5827 if (type_is_invalid(result_loc_inst->value->type) ||5827 if (type_is_invalid(result_loc_inst->value->type) ||
...@@ -5830,20 +5830,20 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode...@@ -5830,20 +5830,20 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode
5830 return result_loc_inst;5830 return result_loc_inst;
5831 }5831 }
5832 }5832 }
5833 IrInstGen *result = ir_build_optional_wrap(ira, scope, source_node, wanted_type, value, result_loc_inst);5833 Stage1AirInst *result = ir_build_optional_wrap(ira, scope, source_node, wanted_type, value, result_loc_inst);
5834 result->value->data.rh_maybe = RuntimeHintOptionalNonNull;5834 result->value->data.rh_maybe = RuntimeHintOptionalNonNull;
5835 return result;5835 return result;
5836}5836}
58375837
5838static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,5838static Stage1AirInst *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5839 IrInstGen *value, ZigType *wanted_type, ResultLoc *result_loc)5839 Stage1AirInst *value, ZigType *wanted_type, ResultLoc *result_loc)
5840{5840{
5841 assert(wanted_type->id == ZigTypeIdErrorUnion);5841 assert(wanted_type->id == ZigTypeIdErrorUnion);
58425842
5843 ZigType *payload_type = wanted_type->data.error_union.payload_type;5843 ZigType *payload_type = wanted_type->data.error_union.payload_type;
5844 ZigType *err_set_type = wanted_type->data.error_union.err_set_type;5844 ZigType *err_set_type = wanted_type->data.error_union.err_set_type;
5845 if (instr_is_comptime(value)) {5845 if (instr_is_comptime(value)) {
5846 IrInstGen *casted_payload = ir_implicit_cast(ira, value, payload_type);5846 Stage1AirInst *casted_payload = ir_implicit_cast(ira, value, payload_type);
5847 if (type_is_invalid(casted_payload->value->type))5847 if (type_is_invalid(casted_payload->value->type))
5848 return ira->codegen->invalid_inst_gen;5848 return ira->codegen->invalid_inst_gen;
58495849
...@@ -5856,7 +5856,7 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN...@@ -5856,7 +5856,7 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN
5856 err_set_val->special = ConstValSpecialStatic;5856 err_set_val->special = ConstValSpecialStatic;
5857 err_set_val->data.x_err_set = nullptr;5857 err_set_val->data.x_err_set = nullptr;
58585858
5859 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,5859 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
5860 scope, source_node);5860 scope, source_node);
5861 const_instruction->base.value->type = wanted_type;5861 const_instruction->base.value->type = wanted_type;
5862 const_instruction->base.value->special = ConstValSpecialStatic;5862 const_instruction->base.value->special = ConstValSpecialStatic;
...@@ -5865,7 +5865,7 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN...@@ -5865,7 +5865,7 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN
5865 return &const_instruction->base;5865 return &const_instruction->base;
5866 }5866 }
58675867
5868 IrInstGen *result_loc_inst;5868 Stage1AirInst *result_loc_inst;
5869 if (handle_is_ptr(ira->codegen, wanted_type)) {5869 if (handle_is_ptr(ira->codegen, wanted_type)) {
5870 if (result_loc == nullptr) result_loc = no_result_loc();5870 if (result_loc == nullptr) result_loc = no_result_loc();
5871 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true);5871 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true);
...@@ -5877,12 +5877,12 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN...@@ -5877,12 +5877,12 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN
5877 result_loc_inst = nullptr;5877 result_loc_inst = nullptr;
5878 }5878 }
58795879
5880 IrInstGen *result = ir_build_err_wrap_payload(ira, scope, source_node, wanted_type, value, result_loc_inst);5880 Stage1AirInst *result = ir_build_err_wrap_payload(ira, scope, source_node, wanted_type, value, result_loc_inst);
5881 result->value->data.rh_error_union = RuntimeHintErrorUnionNonError;5881 result->value->data.rh_error_union = RuntimeHintErrorUnionNonError;
5882 return result;5882 return result;
5883}5883}
58845884
5885static IrInstGen *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,5885static Stage1AirInst *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
5886 ZigType *wanted_type)5886 ZigType *wanted_type)
5887{5887{
5888 assert(value->value->type->id == ZigTypeIdErrorSet);5888 assert(value->value->type->id == ZigTypeIdErrorSet);
...@@ -5912,7 +5912,7 @@ static IrInstGen *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode...@@ -5912,7 +5912,7 @@ static IrInstGen *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode
5912 }5912 }
5913 }5913 }
59145914
5915 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,5915 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
5916 scope, source_node);5916 scope, source_node);
5917 const_instruction->base.value->type = wanted_type;5917 const_instruction->base.value->type = wanted_type;
5918 const_instruction->base.value->special = ConstValSpecialStatic;5918 const_instruction->base.value->special = ConstValSpecialStatic;
...@@ -5923,8 +5923,8 @@ static IrInstGen *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode...@@ -5923,8 +5923,8 @@ static IrInstGen *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode
5923 return ir_build_cast(ira, scope, source_node, wanted_type, value, CastOpErrSet);5923 return ir_build_cast(ira, scope, source_node, wanted_type, value, CastOpErrSet);
5924}5924}
59255925
5926static IrInstGen *ir_analyze_frame_ptr_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node,5926static Stage1AirInst *ir_analyze_frame_ptr_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5927 IrInstGen *frame_ptr, ZigType *wanted_type)5927 Stage1AirInst *frame_ptr, ZigType *wanted_type)
5928{5928{
5929 if (instr_is_comptime(frame_ptr)) {5929 if (instr_is_comptime(frame_ptr)) {
5930 ZigValue *ptr_val = ir_resolve_const(ira, frame_ptr, UndefBad);5930 ZigValue *ptr_val = ir_resolve_const(ira, frame_ptr, UndefBad);
...@@ -5940,8 +5940,8 @@ static IrInstGen *ir_analyze_frame_ptr_to_anyframe(IrAnalyze *ira, Scope *scope,...@@ -5940,8 +5940,8 @@ static IrInstGen *ir_analyze_frame_ptr_to_anyframe(IrAnalyze *ira, Scope *scope,
5940 return ir_build_cast(ira, scope, source_node, wanted_type, frame_ptr, CastOpBitCast);5940 return ir_build_cast(ira, scope, source_node, wanted_type, frame_ptr, CastOpBitCast);
5941}5941}
59425942
5943static IrInstGen *ir_analyze_anyframe_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node,5943static Stage1AirInst *ir_analyze_anyframe_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5944 IrInstGen *value, ZigType *wanted_type)5944 Stage1AirInst *value, ZigType *wanted_type)
5945{5945{
5946 if (instr_is_comptime(value)) {5946 if (instr_is_comptime(value)) {
5947 zig_panic("TODO comptime anyframe->T to anyframe");5947 zig_panic("TODO comptime anyframe->T to anyframe");
...@@ -5951,12 +5951,12 @@ static IrInstGen *ir_analyze_anyframe_to_anyframe(IrAnalyze *ira, Scope *scope,...@@ -5951,12 +5951,12 @@ static IrInstGen *ir_analyze_anyframe_to_anyframe(IrAnalyze *ira, Scope *scope,
5951}5951}
59525952
59535953
5954static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,5954static Stage1AirInst *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
5955 ZigType *wanted_type, ResultLoc *result_loc)5955 ZigType *wanted_type, ResultLoc *result_loc)
5956{5956{
5957 assert(wanted_type->id == ZigTypeIdErrorUnion);5957 assert(wanted_type->id == ZigTypeIdErrorUnion);
59585958
5959 IrInstGen *casted_value = ir_implicit_cast(ira, value, wanted_type->data.error_union.err_set_type);5959 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, wanted_type->data.error_union.err_set_type);
59605960
5961 if (instr_is_comptime(casted_value)) {5961 if (instr_is_comptime(casted_value)) {
5962 ZigValue *val = ir_resolve_const(ira, casted_value, UndefBad);5962 ZigValue *val = ir_resolve_const(ira, casted_value, UndefBad);
...@@ -5968,7 +5968,7 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode...@@ -5968,7 +5968,7 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode
5968 err_set_val->type = wanted_type->data.error_union.err_set_type;5968 err_set_val->type = wanted_type->data.error_union.err_set_type;
5969 err_set_val->data.x_err_set = val->data.x_err_set;5969 err_set_val->data.x_err_set = val->data.x_err_set;
59705970
5971 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,5971 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
5972 scope, source_node);5972 scope, source_node);
5973 const_instruction->base.value->type = wanted_type;5973 const_instruction->base.value->type = wanted_type;
5974 const_instruction->base.value->special = ConstValSpecialStatic;5974 const_instruction->base.value->special = ConstValSpecialStatic;
...@@ -5977,7 +5977,7 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode...@@ -5977,7 +5977,7 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode
5977 return &const_instruction->base;5977 return &const_instruction->base;
5978 }5978 }
59795979
5980 IrInstGen *result_loc_inst;5980 Stage1AirInst *result_loc_inst;
5981 if (handle_is_ptr(ira->codegen, wanted_type)) {5981 if (handle_is_ptr(ira->codegen, wanted_type)) {
5982 if (result_loc == nullptr) result_loc = no_result_loc();5982 if (result_loc == nullptr) result_loc = no_result_loc();
5983 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true);5983 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true);
...@@ -5991,19 +5991,19 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode...@@ -5991,19 +5991,19 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode
5991 }5991 }
59925992
59935993
5994 IrInstGen *result = ir_build_err_wrap_code(ira, scope, source_node, wanted_type, value, result_loc_inst);5994 Stage1AirInst *result = ir_build_err_wrap_code(ira, scope, source_node, wanted_type, value, result_loc_inst);
5995 result->value->data.rh_error_union = RuntimeHintErrorUnionError;5995 result->value->data.rh_error_union = RuntimeHintErrorUnionError;
5996 return result;5996 return result;
5997}5997}
59985998
5999static IrInstGen *ir_analyze_null_to_maybe(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, ZigType *wanted_type) {5999static Stage1AirInst *ir_analyze_null_to_maybe(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *wanted_type) {
6000 assert(wanted_type->id == ZigTypeIdOptional);6000 assert(wanted_type->id == ZigTypeIdOptional);
6001 assert(instr_is_comptime(value));6001 assert(instr_is_comptime(value));
60026002
6003 ZigValue *val = ir_resolve_const(ira, value, UndefBad);6003 ZigValue *val = ir_resolve_const(ira, value, UndefBad);
6004 assert(val != nullptr);6004 assert(val != nullptr);
60056005
6006 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6006 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
6007 result->value->special = ConstValSpecialStatic;6007 result->value->special = ConstValSpecialStatic;
60086008
6009 if (get_src_ptr_type(wanted_type) != nullptr) {6009 if (get_src_ptr_type(wanted_type) != nullptr) {
...@@ -6016,8 +6016,8 @@ static IrInstGen *ir_analyze_null_to_maybe(IrAnalyze *ira, Scope *scope, AstNode...@@ -6016,8 +6016,8 @@ static IrInstGen *ir_analyze_null_to_maybe(IrAnalyze *ira, Scope *scope, AstNode
6016 return result;6016 return result;
6017}6017}
60186018
6019static IrInstGen *ir_analyze_null_to_c_pointer(IrAnalyze *ira, Scope *scope, AstNode *source_node,6019static Stage1AirInst *ir_analyze_null_to_c_pointer(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6020 IrInstGen *value, ZigType *wanted_type)6020 Stage1AirInst *value, ZigType *wanted_type)
6021{6021{
6022 assert(wanted_type->id == ZigTypeIdPointer);6022 assert(wanted_type->id == ZigTypeIdPointer);
6023 assert(wanted_type->data.pointer.ptr_len == PtrLenC);6023 assert(wanted_type->data.pointer.ptr_len == PtrLenC);
...@@ -6026,13 +6026,13 @@ static IrInstGen *ir_analyze_null_to_c_pointer(IrAnalyze *ira, Scope *scope, Ast...@@ -6026,13 +6026,13 @@ static IrInstGen *ir_analyze_null_to_c_pointer(IrAnalyze *ira, Scope *scope, Ast
6026 ZigValue *val = ir_resolve_const(ira, value, UndefBad);6026 ZigValue *val = ir_resolve_const(ira, value, UndefBad);
6027 assert(val != nullptr);6027 assert(val != nullptr);
60286028
6029 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6029 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
6030 result->value->data.x_ptr.special = ConstPtrSpecialNull;6030 result->value->data.x_ptr.special = ConstPtrSpecialNull;
6031 result->value->data.x_ptr.mut = ConstPtrMutComptimeConst;6031 result->value->data.x_ptr.mut = ConstPtrMutComptimeConst;
6032 return result;6032 return result;
6033}6033}
60346034
6035static IrInstGen *ir_get_ref2(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,6035static Stage1AirInst *ir_get_ref2(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
6036 ZigType *elem_type, bool is_const, bool is_volatile)6036 ZigType *elem_type, bool is_const, bool is_volatile)
6037{6037{
6038 Error err;6038 Error err;
...@@ -6054,19 +6054,19 @@ static IrInstGen *ir_get_ref2(IrAnalyze *ira, Scope *scope, AstNode *source_node...@@ -6054,19 +6054,19 @@ static IrInstGen *ir_get_ref2(IrAnalyze *ira, Scope *scope, AstNode *source_node
6054 if ((err = type_resolve(ira->codegen, ptr_type, ResolveStatusZeroBitsKnown)))6054 if ((err = type_resolve(ira->codegen, ptr_type, ResolveStatusZeroBitsKnown)))
6055 return ira->codegen->invalid_inst_gen;6055 return ira->codegen->invalid_inst_gen;
60566056
6057 IrInstGen *result_loc;6057 Stage1AirInst *result_loc;
6058 if (type_has_bits(ira->codegen, ptr_type) && !handle_is_ptr(ira->codegen, elem_type)) {6058 if (type_has_bits(ira->codegen, ptr_type) && !handle_is_ptr(ira->codegen, elem_type)) {
6059 result_loc = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), elem_type, nullptr, true, true);6059 result_loc = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), elem_type, nullptr, true, true);
6060 } else {6060 } else {
6061 result_loc = nullptr;6061 result_loc = nullptr;
6062 }6062 }
60636063
6064 IrInstGen *new_instruction = ir_build_ref_gen(ira, scope, source_node, ptr_type, value, result_loc);6064 Stage1AirInst *new_instruction = ir_build_ref_gen(ira, scope, source_node, ptr_type, value, result_loc);
6065 new_instruction->value->data.rh_ptr = RuntimeHintPtrStack;6065 new_instruction->value->data.rh_ptr = RuntimeHintPtrStack;
6066 return new_instruction;6066 return new_instruction;
6067}6067}
60686068
6069static IrInstGen *ir_get_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,6069static Stage1AirInst *ir_get_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
6070 bool is_const, bool is_volatile)6070 bool is_const, bool is_volatile)
6071{6071{
6072 return ir_get_ref2(ira, scope, source_node, value, value->value->type, is_const, is_volatile);6072 return ir_get_ref2(ira, scope, source_node, value, value->value->type, is_const, is_volatile);
...@@ -6103,10 +6103,10 @@ static bool can_fold_enum_type(ZigType *ty) {...@@ -6103,10 +6103,10 @@ static bool can_fold_enum_type(ZigType *ty) {
6103 (tag_int_type->id == ZigTypeIdInt && tag_int_type->data.integral.bit_count == 0);6103 (tag_int_type->id == ZigTypeIdInt && tag_int_type->data.integral.bit_count == 0);
6104}6104}
61056105
6106static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target) {6106static Stage1AirInst *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target) {
6107 Error err;6107 Error err;
61086108
6109 IrInstGen *enum_target;6109 Stage1AirInst *enum_target;
6110 ZigType *enum_type;6110 ZigType *enum_type;
6111 if (target->value->type->id == ZigTypeIdUnion) {6111 if (target->value->type->id == ZigTypeIdUnion) {
6112 enum_type = ir_resolve_union_tag_type(ira, target->source_node, target->value->type);6112 enum_type = ir_resolve_union_tag_type(ira, target->source_node, target->value->type);
...@@ -6132,7 +6132,7 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *...@@ -6132,7 +6132,7 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *
61326132
6133 // If there is only one possible tag, then we know at comptime what it is.6133 // If there is only one possible tag, then we know at comptime what it is.
6134 if (can_fold_enum_type(enum_type)) {6134 if (can_fold_enum_type(enum_type)) {
6135 IrInstGen *result = ir_const(ira, scope, source_node, tag_type);6135 Stage1AirInst *result = ir_const(ira, scope, source_node, tag_type);
6136 init_const_bigint(result->value, tag_type,6136 init_const_bigint(result->value, tag_type,
6137 &enum_type->data.enumeration.fields[0].value);6137 &enum_type->data.enumeration.fields[0].value);
6138 return result;6138 return result;
...@@ -6142,7 +6142,7 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *...@@ -6142,7 +6142,7 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *
6142 ZigValue *val = ir_resolve_const(ira, enum_target, UndefBad);6142 ZigValue *val = ir_resolve_const(ira, enum_target, UndefBad);
6143 if (!val)6143 if (!val)
6144 return ira->codegen->invalid_inst_gen;6144 return ira->codegen->invalid_inst_gen;
6145 IrInstGen *result = ir_const(ira, scope, source_node, tag_type);6145 Stage1AirInst *result = ir_const(ira, scope, source_node, tag_type);
6146 init_const_bigint(result->value, tag_type, &val->data.x_enum_tag);6146 init_const_bigint(result->value, tag_type, &val->data.x_enum_tag);
6147 return result;6147 return result;
6148 }6148 }
...@@ -6150,8 +6150,8 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *...@@ -6150,8 +6150,8 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *
6150 return ir_build_widen_or_shorten(ira, scope, source_node, enum_target, tag_type);6150 return ir_build_widen_or_shorten(ira, scope, source_node, enum_target, tag_type);
6151}6151}
61526152
6153static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node,6153static Stage1AirInst *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6154 IrInstGen *target, ZigType *wanted_type)6154 Stage1AirInst *target, ZigType *wanted_type)
6155{6155{
6156 assert(target->value->type->id == ZigTypeIdUnion);6156 assert(target->value->type->id == ZigTypeIdUnion);
6157 assert(wanted_type->id == ZigTypeIdEnum);6157 assert(wanted_type->id == ZigTypeIdEnum);
...@@ -6161,7 +6161,7 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode...@@ -6161,7 +6161,7 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode
6161 ZigValue *val = ir_resolve_const(ira, target, UndefBad);6161 ZigValue *val = ir_resolve_const(ira, target, UndefBad);
6162 if (!val)6162 if (!val)
6163 return ira->codegen->invalid_inst_gen;6163 return ira->codegen->invalid_inst_gen;
6164 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6164 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
6165 result->value->special = ConstValSpecialStatic;6165 result->value->special = ConstValSpecialStatic;
6166 result->value->type = wanted_type;6166 result->value->type = wanted_type;
6167 bigint_init_bigint(&result->value->data.x_enum_tag, &val->data.x_union.tag);6167 bigint_init_bigint(&result->value->data.x_enum_tag, &val->data.x_union.tag);
...@@ -6170,7 +6170,7 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode...@@ -6170,7 +6170,7 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode
61706170
6171 // If there is only 1 possible tag, then we know at comptime what it is.6171 // If there is only 1 possible tag, then we know at comptime what it is.
6172 if (can_fold_enum_type(wanted_type)) {6172 if (can_fold_enum_type(wanted_type)) {
6173 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6173 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
6174 result->value->special = ConstValSpecialStatic;6174 result->value->special = ConstValSpecialStatic;
6175 result->value->type = wanted_type;6175 result->value->type = wanted_type;
6176 TypeEnumField *enum_field = target->value->type->data.unionation.fields[0].enum_field;6176 TypeEnumField *enum_field = target->value->type->data.unionation.fields[0].enum_field;
...@@ -6181,16 +6181,16 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode...@@ -6181,16 +6181,16 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode
6181 return ir_build_union_tag(ira, scope, source_node, target, wanted_type);6181 return ir_build_union_tag(ira, scope, source_node, target, wanted_type);
6182}6182}
61836183
6184static IrInstGen *ir_analyze_undefined_to_anything(IrAnalyze *ira, Scope *scope, AstNode *source_node,6184static Stage1AirInst *ir_analyze_undefined_to_anything(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6185 IrInstGen *target, ZigType *wanted_type)6185 Stage1AirInst *target, ZigType *wanted_type)
6186{6186{
6187 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6187 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
6188 result->value->special = ConstValSpecialUndef;6188 result->value->special = ConstValSpecialUndef;
6189 return result;6189 return result;
6190}6190}
61916191
6192static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node,6192static Stage1AirInst *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6193 IrInstGen *uncasted_target, ZigType *wanted_type)6193 Stage1AirInst *uncasted_target, ZigType *wanted_type)
6194{6194{
6195 Error err;6195 Error err;
6196 assert(wanted_type->id == ZigTypeIdUnion);6196 assert(wanted_type->id == ZigTypeIdUnion);
...@@ -6198,7 +6198,7 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode...@@ -6198,7 +6198,7 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode
6198 if ((err = type_resolve(ira->codegen, wanted_type, ResolveStatusZeroBitsKnown)))6198 if ((err = type_resolve(ira->codegen, wanted_type, ResolveStatusZeroBitsKnown)))
6199 return ira->codegen->invalid_inst_gen;6199 return ira->codegen->invalid_inst_gen;
62006200
6201 IrInstGen *target = ir_implicit_cast(ira, uncasted_target, wanted_type->data.unionation.tag_type);6201 Stage1AirInst *target = ir_implicit_cast(ira, uncasted_target, wanted_type->data.unionation.tag_type);
6202 if (type_is_invalid(target->value->type))6202 if (type_is_invalid(target->value->type))
6203 return ira->codegen->invalid_inst_gen;6203 return ira->codegen->invalid_inst_gen;
62046204
...@@ -6240,7 +6240,7 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode...@@ -6240,7 +6240,7 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode
6240 break;6240 break;
6241 }6241 }
62426242
6243 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6243 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
6244 result->value->special = ConstValSpecialStatic;6244 result->value->special = ConstValSpecialStatic;
6245 result->value->type = wanted_type;6245 result->value->type = wanted_type;
6246 bigint_init_bigint(&result->value->data.x_union.tag, &val->data.x_enum_tag);6246 bigint_init_bigint(&result->value->data.x_union.tag, &val->data.x_enum_tag);
...@@ -6287,8 +6287,8 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode...@@ -6287,8 +6287,8 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode
62876287
6288static bool value_numeric_fits_in_type(ZigValue *value, ZigType *type_entry);6288static bool value_numeric_fits_in_type(ZigValue *value, ZigType *type_entry);
62896289
6290static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node,6290static Stage1AirInst *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6291 IrInstGen *target, ZigType *wanted_type)6291 Stage1AirInst *target, ZigType *wanted_type)
6292{6292{
6293 ZigType *wanted_scalar_type = (target->value->type->id == ZigTypeIdVector) ?6293 ZigType *wanted_scalar_type = (target->value->type->id == ZigTypeIdVector) ?
6294 wanted_type->data.vector.elem_type : wanted_type;6294 wanted_type->data.vector.elem_type : wanted_type;
...@@ -6314,7 +6314,7 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN...@@ -6314,7 +6314,7 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN
6314 }6314 }
6315 }6315 }
63166316
6317 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6317 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
6318 result->value->type = wanted_type;6318 result->value->type = wanted_type;
63196319
6320 if (wanted_type->id == ZigTypeIdVector) {6320 if (wanted_type->id == ZigTypeIdVector) {
...@@ -6351,7 +6351,7 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN...@@ -6351,7 +6351,7 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN
6351 assert(wanted_type->id == ZigTypeIdInt);6351 assert(wanted_type->id == ZigTypeIdInt);
6352 assert(type_has_bits(ira->codegen, target->value->type));6352 assert(type_has_bits(ira->codegen, target->value->type));
6353 ir_build_assert_zero(ira, scope, source_node, target);6353 ir_build_assert_zero(ira, scope, source_node, target);
6354 IrInstGen *result = ir_const_unsigned(ira, scope, source_node, 0);6354 Stage1AirInst *result = ir_const_unsigned(ira, scope, source_node, 0);
6355 result->value->type = wanted_type;6355 result->value->type = wanted_type;
6356 return result;6356 return result;
6357 }6357 }
...@@ -6359,8 +6359,8 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN...@@ -6359,8 +6359,8 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN
6359 return ir_build_widen_or_shorten(ira, scope, source_node, target, wanted_type);6359 return ir_build_widen_or_shorten(ira, scope, source_node, target, wanted_type);
6360}6360}
63616361
6362static IrInstGen *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *source_node,6362static Stage1AirInst *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6363 IrInstGen *target, ZigType *wanted_type)6363 Stage1AirInst *target, ZigType *wanted_type)
6364{6364{
6365 Error err;6365 Error err;
6366 assert(wanted_type->id == ZigTypeIdEnum);6366 assert(wanted_type->id == ZigTypeIdEnum);
...@@ -6397,7 +6397,7 @@ static IrInstGen *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *...@@ -6397,7 +6397,7 @@ static IrInstGen *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *
6397 return ira->codegen->invalid_inst_gen;6397 return ira->codegen->invalid_inst_gen;
6398 }6398 }
63996399
6400 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6400 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
6401 bigint_init_bigint(&result->value->data.x_enum_tag, &val->data.x_bigint);6401 bigint_init_bigint(&result->value->data.x_enum_tag, &val->data.x_bigint);
6402 return result;6402 return result;
6403 }6403 }
...@@ -6405,14 +6405,14 @@ static IrInstGen *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *...@@ -6405,14 +6405,14 @@ static IrInstGen *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *
6405 return ir_build_int_to_enum_gen(ira, scope, source_node, wanted_type, target);6405 return ir_build_int_to_enum_gen(ira, scope, source_node, wanted_type, target);
6406}6406}
64076407
6408static IrInstGen *ir_analyze_number_to_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node,6408static Stage1AirInst *ir_analyze_number_to_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6409 IrInstGen *target, ZigType *wanted_type)6409 Stage1AirInst *target, ZigType *wanted_type)
6410{6410{
6411 ZigValue *val = ir_resolve_const(ira, target, UndefBad);6411 ZigValue *val = ir_resolve_const(ira, target, UndefBad);
6412 if (!val)6412 if (!val)
6413 return ira->codegen->invalid_inst_gen;6413 return ira->codegen->invalid_inst_gen;
64146414
6415 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6415 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
6416 if (wanted_type->id == ZigTypeIdComptimeFloat) {6416 if (wanted_type->id == ZigTypeIdComptimeFloat) {
6417 float_init_float(result->value, val);6417 float_init_float(result->value, val);
6418 } else if (wanted_type->id == ZigTypeIdComptimeInt) {6418 } else if (wanted_type->id == ZigTypeIdComptimeInt) {
...@@ -6423,7 +6423,7 @@ static IrInstGen *ir_analyze_number_to_literal(IrAnalyze *ira, Scope *scope, Ast...@@ -6423,7 +6423,7 @@ static IrInstGen *ir_analyze_number_to_literal(IrAnalyze *ira, Scope *scope, Ast
6423 return result;6423 return result;
6424}6424}
64256425
6426static IrInstGen *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,6426static Stage1AirInst *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
6427 ZigType *wanted_type)6427 ZigType *wanted_type)
6428{6428{
6429 assert(target->value->type->id == ZigTypeIdInt);6429 assert(target->value->type->id == ZigTypeIdInt);
...@@ -6435,7 +6435,7 @@ static IrInstGen *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -6435,7 +6435,7 @@ static IrInstGen *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *s
6435 if (!val)6435 if (!val)
6436 return ira->codegen->invalid_inst_gen;6436 return ira->codegen->invalid_inst_gen;
64376437
6438 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6438 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
64396439
6440 if (!resolve_inferred_error_set(ira->codegen, wanted_type, source_node)) {6440 if (!resolve_inferred_error_set(ira->codegen, wanted_type, source_node)) {
6441 return ira->codegen->invalid_inst_gen;6441 return ira->codegen->invalid_inst_gen;
...@@ -6485,7 +6485,7 @@ static IrInstGen *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -6485,7 +6485,7 @@ static IrInstGen *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *s
6485 return ir_build_int_to_err_gen(ira, scope, source_node, target, wanted_type);6485 return ir_build_int_to_err_gen(ira, scope, source_node, target, wanted_type);
6486}6486}
64876487
6488static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,6488static Stage1AirInst *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
6489 ZigType *wanted_type)6489 ZigType *wanted_type)
6490{6490{
6491 assert(wanted_type->id == ZigTypeIdInt);6491 assert(wanted_type->id == ZigTypeIdInt);
...@@ -6497,7 +6497,7 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -6497,7 +6497,7 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s
6497 if (!val)6497 if (!val)
6498 return ira->codegen->invalid_inst_gen;6498 return ira->codegen->invalid_inst_gen;
64996499
6500 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6500 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
65016501
6502 ErrorTableEntry *err;6502 ErrorTableEntry *err;
6503 if (err_type->id == ZigTypeIdErrorUnion) {6503 if (err_type->id == ZigTypeIdErrorUnion) {
...@@ -6536,11 +6536,11 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -6536,11 +6536,11 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s
6536 return ira->codegen->invalid_inst_gen;6536 return ira->codegen->invalid_inst_gen;
6537 }6537 }
6538 if (err_set_type->data.error_set.err_count == 0) {6538 if (err_set_type->data.error_set.err_count == 0) {
6539 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6539 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
6540 bigint_init_unsigned(&result->value->data.x_bigint, 0);6540 bigint_init_unsigned(&result->value->data.x_bigint, 0);
6541 return result;6541 return result;
6542 } else if (err_set_type->data.error_set.err_count == 1) {6542 } else if (err_set_type->data.error_set.err_count == 1) {
6543 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);6543 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
6544 ErrorTableEntry *err = err_set_type->data.error_set.errors[0];6544 ErrorTableEntry *err = err_set_type->data.error_set.errors[0];
6545 bigint_init_unsigned(&result->value->data.x_bigint, err->value);6545 bigint_init_unsigned(&result->value->data.x_bigint, err->value);
6546 return result;6546 return result;
...@@ -6558,7 +6558,7 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -6558,7 +6558,7 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s
6558 return ir_build_err_to_int_gen(ira, scope, source_node, target, wanted_type);6558 return ir_build_err_to_int_gen(ira, scope, source_node, target, wanted_type);
6559}6559}
65606560
6561static IrInstGen *ir_analyze_ptr_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,6561static Stage1AirInst *ir_analyze_ptr_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
6562 ZigType *wanted_type)6562 ZigType *wanted_type)
6563{6563{
6564 assert(wanted_type->id == ZigTypeIdPointer);6564 assert(wanted_type->id == ZigTypeIdPointer);
...@@ -6589,7 +6589,7 @@ static IrInstGen *ir_analyze_ptr_to_array(IrAnalyze *ira, Scope *scope, AstNode...@@ -6589,7 +6589,7 @@ static IrInstGen *ir_analyze_ptr_to_array(IrAnalyze *ira, Scope *scope, AstNode
6589 array_val->parent.id = ConstParentIdScalar;6589 array_val->parent.id = ConstParentIdScalar;
6590 array_val->parent.data.p_scalar.scalar_val = pointee;6590 array_val->parent.data.p_scalar.scalar_val = pointee;
65916591
6592 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,6592 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
6593 scope, source_node);6593 scope, source_node);
6594 const_instruction->base.value->type = wanted_type;6594 const_instruction->base.value->type = wanted_type;
6595 const_instruction->base.value->special = ConstValSpecialStatic;6595 const_instruction->base.value->special = ConstValSpecialStatic;
...@@ -6798,12 +6798,12 @@ static void report_recursive_error(IrAnalyze *ira, AstNode *source_node, ConstCa...@@ -6798,12 +6798,12 @@ static void report_recursive_error(IrAnalyze *ira, AstNode *source_node, ConstCa
6798 }6798 }
6799}6799}
68006800
6801static IrInstGen *ir_analyze_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,6801static Stage1AirInst *ir_analyze_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6802 IrInstGen *array, ZigType *vector_type)6802 Stage1AirInst *array, ZigType *vector_type)
6803{6803{
6804 if (instr_is_comptime(array)) {6804 if (instr_is_comptime(array)) {
6805 // arrays and vectors have the same ZigValue representation6805 // arrays and vectors have the same ZigValue representation
6806 IrInstGen *result = ir_const(ira, scope, source_node, vector_type);6806 Stage1AirInst *result = ir_const(ira, scope, source_node, vector_type);
6807 copy_const_val(ira->codegen, result->value, array->value);6807 copy_const_val(ira->codegen, result->value, array->value);
6808 result->value->type = vector_type;6808 result->value->type = vector_type;
6809 return result;6809 return result;
...@@ -6811,12 +6811,12 @@ static IrInstGen *ir_analyze_array_to_vector(IrAnalyze *ira, Scope *scope, AstNo...@@ -6811,12 +6811,12 @@ static IrInstGen *ir_analyze_array_to_vector(IrAnalyze *ira, Scope *scope, AstNo
6811 return ir_build_array_to_vector(ira, scope, source_node, array, vector_type);6811 return ir_build_array_to_vector(ira, scope, source_node, array, vector_type);
6812}6812}
68136813
6814static IrInstGen *ir_analyze_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,6814static Stage1AirInst *ir_analyze_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6815 IrInstGen *vector, ZigType *array_type, ResultLoc *result_loc)6815 Stage1AirInst *vector, ZigType *array_type, ResultLoc *result_loc)
6816{6816{
6817 if (instr_is_comptime(vector)) {6817 if (instr_is_comptime(vector)) {
6818 // arrays and vectors have the same ZigValue representation6818 // arrays and vectors have the same ZigValue representation
6819 IrInstGen *result = ir_const(ira, scope, source_node, array_type);6819 Stage1AirInst *result = ir_const(ira, scope, source_node, array_type);
6820 copy_const_val(ira->codegen, result->value, vector->value);6820 copy_const_val(ira->codegen, result->value, vector->value);
6821 result->value->type = array_type;6821 result->value->type = array_type;
6822 return result;6822 return result;
...@@ -6824,17 +6824,17 @@ static IrInstGen *ir_analyze_vector_to_array(IrAnalyze *ira, Scope *scope, AstNo...@@ -6824,17 +6824,17 @@ static IrInstGen *ir_analyze_vector_to_array(IrAnalyze *ira, Scope *scope, AstNo
6824 if (result_loc == nullptr) {6824 if (result_loc == nullptr) {
6825 result_loc = no_result_loc();6825 result_loc = no_result_loc();
6826 }6826 }
6827 IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, array_type, nullptr, true, true);6827 Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, array_type, nullptr, true, true);
6828 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {6828 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {
6829 return result_loc_inst;6829 return result_loc_inst;
6830 }6830 }
6831 return ir_build_vector_to_array(ira, scope, source_node, array_type, vector, result_loc_inst);6831 return ir_build_vector_to_array(ira, scope, source_node, array_type, vector, result_loc_inst);
6832}6832}
68336833
6834static IrInstGen *ir_analyze_int_to_c_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,6834static Stage1AirInst *ir_analyze_int_to_c_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6835 IrInstGen *integer, ZigType *dest_type)6835 Stage1AirInst *integer, ZigType *dest_type)
6836{6836{
6837 IrInstGen *unsigned_integer;6837 Stage1AirInst *unsigned_integer;
6838 if (instr_is_comptime(integer)) {6838 if (instr_is_comptime(integer)) {
6839 unsigned_integer = integer;6839 unsigned_integer = integer;
6840 } else {6840 } else {
...@@ -6875,7 +6875,7 @@ static bool is_pointery_and_elem_is_not_pointery(ZigType *ty) {...@@ -6875,7 +6875,7 @@ static bool is_pointery_and_elem_is_not_pointery(ZigType *ty) {
6875 return false;6875 return false;
6876}6876}
68776877
6878static IrInstGen *ir_analyze_enum_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,6878static Stage1AirInst *ir_analyze_enum_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
6879 ZigType *enum_type)6879 ZigType *enum_type)
6880{6880{
6881 assert(enum_type->id == ZigTypeIdEnum);6881 assert(enum_type->id == ZigTypeIdEnum);
...@@ -6892,14 +6892,14 @@ static IrInstGen *ir_analyze_enum_literal(IrAnalyze *ira, Scope *scope, AstNode...@@ -6892,14 +6892,14 @@ static IrInstGen *ir_analyze_enum_literal(IrAnalyze *ira, Scope *scope, AstNode
6892 buf_sprintf("'%s' declared here", buf_ptr(&enum_type->name)));6892 buf_sprintf("'%s' declared here", buf_ptr(&enum_type->name)));
6893 return ira->codegen->invalid_inst_gen;6893 return ira->codegen->invalid_inst_gen;
6894 }6894 }
6895 IrInstGen *result = ir_const(ira, scope, source_node, enum_type);6895 Stage1AirInst *result = ir_const(ira, scope, source_node, enum_type);
6896 bigint_init_bigint(&result->value->data.x_enum_tag, &field->value);6896 bigint_init_bigint(&result->value->data.x_enum_tag, &field->value);
68976897
6898 return result;6898 return result;
6899}6899}
69006900
6901static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,6901static Stage1AirInst *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6902 IrInstGen *struct_ptr, ZigType *actual_type, ZigType *wanted_type)6902 Stage1AirInst *struct_ptr, ZigType *actual_type, ZigType *wanted_type)
6903{6903{
6904 Error err;6904 Error err;
69056905
...@@ -6918,20 +6918,20 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop...@@ -6918,20 +6918,20 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop
69186918
6919 // Determine if the struct_operand will be comptime.6919 // Determine if the struct_operand will be comptime.
6920 ZigValue *elem_values = heap::c_allocator.allocate<ZigValue>(array_len);6920 ZigValue *elem_values = heap::c_allocator.allocate<ZigValue>(array_len);
6921 IrInstGen **casted_fields = heap::c_allocator.allocate<IrInstGen *>(array_len);6921 Stage1AirInst **casted_fields = heap::c_allocator.allocate<Stage1AirInst *>(array_len);
6922 IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type);6922 Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type);
69236923
6924 for (size_t i = 0; i < array_len; i += 1) {6924 for (size_t i = 0; i < array_len; i += 1) {
6925 TypeStructField *src_field = actual_type->data.structure.fields[i];6925 TypeStructField *src_field = actual_type->data.structure.fields[i];
69266926
6927 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr,6927 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr,
6928 actual_type, false);6928 actual_type, false);
6929 if (type_is_invalid(field_ptr->value->type))6929 if (type_is_invalid(field_ptr->value->type))
6930 return ira->codegen->invalid_inst_gen;6930 return ira->codegen->invalid_inst_gen;
6931 IrInstGen *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);6931 Stage1AirInst *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);
6932 if (type_is_invalid(field_value->value->type))6932 if (type_is_invalid(field_value->value->type))
6933 return ira->codegen->invalid_inst_gen;6933 return ira->codegen->invalid_inst_gen;
6934 IrInstGen *casted_value = ir_implicit_cast(ira, field_value, elem_type);6934 Stage1AirInst *casted_value = ir_implicit_cast(ira, field_value, elem_type);
6935 if (type_is_invalid(casted_value->value->type))6935 if (type_is_invalid(casted_value->value->type))
6936 return ira->codegen->invalid_inst_gen;6936 return ira->codegen->invalid_inst_gen;
69376937
...@@ -6954,13 +6954,13 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop...@@ -6954,13 +6954,13 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop
6954 }6954 }
69556955
6956 if (is_comptime) {6956 if (is_comptime) {
6957 IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type);6957 Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type);
6958 const_result->value->data.x_array.special = ConstArraySpecialNone;6958 const_result->value->data.x_array.special = ConstArraySpecialNone;
6959 const_result->value->data.x_array.data.s_none.elements = elem_values;6959 const_result->value->data.x_array.data.s_none.elements = elem_values;
6960 return const_result;6960 return const_result;
6961 }6961 }
69626962
6963 IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),6963 Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
6964 wanted_type, nullptr, true, true);6964 wanted_type, nullptr, true, true);
6965 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {6965 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {
6966 return ira->codegen->invalid_inst_gen;6966 return ira->codegen->invalid_inst_gen;
...@@ -6968,12 +6968,12 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop...@@ -6968,12 +6968,12 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop
69686968
6969 ZigType *elem_type_ptr = get_pointer_to_type(ira->codegen, elem_type, false);6969 ZigType *elem_type_ptr = get_pointer_to_type(ira->codegen, elem_type, false);
6970 for (size_t i = 0; i < array_len; i += 1) {6970 for (size_t i = 0; i < array_len; i += 1) {
6971 IrInstGen *index_val = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_usize);6971 Stage1AirInst *index_val = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_usize);
6972 bigint_init_unsigned(&index_val->value->data.x_bigint, i);6972 bigint_init_unsigned(&index_val->value->data.x_bigint, i);
69736973
6974 IrInstGen *elem_ptr = ir_build_elem_ptr_gen(ira, scope, source_node,6974 Stage1AirInst *elem_ptr = ir_build_elem_ptr_gen(ira, scope, source_node,
6975 result_loc_inst, index_val, false, elem_type_ptr);6975 result_loc_inst, index_val, false, elem_type_ptr);
6976 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, elem_ptr, casted_fields[i], true);6976 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, elem_ptr, casted_fields[i], true);
6977 if (type_is_invalid(store_ptr_inst->value->type))6977 if (type_is_invalid(store_ptr_inst->value->type))
6978 return ira->codegen->invalid_inst_gen;6978 return ira->codegen->invalid_inst_gen;
6979 }6979 }
...@@ -6984,8 +6984,8 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop...@@ -6984,8 +6984,8 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop
6984 return result_loc_inst;6984 return result_loc_inst;
6985}6985}
69866986
6987static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *scope, AstNode *source_node,6987static Stage1AirInst *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6988 IrInstGen *struct_ptr, ZigType *actual_type, ZigType *wanted_type)6988 Stage1AirInst *struct_ptr, ZigType *actual_type, ZigType *wanted_type)
6989{6989{
6990 Error err;6990 Error err;
69916991
...@@ -7008,8 +7008,8 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco...@@ -7008,8 +7008,8 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco
7008 // Also emit compile errors for missing fields and duplicate fields.7008 // Also emit compile errors for missing fields and duplicate fields.
7009 AstNode **field_assign_nodes = heap::c_allocator.allocate<AstNode *>(actual_field_count);7009 AstNode **field_assign_nodes = heap::c_allocator.allocate<AstNode *>(actual_field_count);
7010 ZigValue **field_values = heap::c_allocator.allocate<ZigValue *>(actual_field_count);7010 ZigValue **field_values = heap::c_allocator.allocate<ZigValue *>(actual_field_count);
7011 IrInstGen **casted_fields = heap::c_allocator.allocate<IrInstGen *>(actual_field_count);7011 Stage1AirInst **casted_fields = heap::c_allocator.allocate<Stage1AirInst *>(actual_field_count);
7012 IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type);7012 Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type);
70137013
7014 for (size_t i = 0; i < instr_field_count; i += 1) {7014 for (size_t i = 0; i < instr_field_count; i += 1) {
7015 TypeStructField *src_field = actual_type->data.structure.fields[i];7015 TypeStructField *src_field = actual_type->data.structure.fields[i];
...@@ -7046,14 +7046,14 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco...@@ -7046,14 +7046,14 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco
7046 }7046 }
7047 field_assign_nodes[dst_field->src_index] = src_field->decl_node;7047 field_assign_nodes[dst_field->src_index] = src_field->decl_node;
70487048
7049 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr,7049 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr,
7050 actual_type, false);7050 actual_type, false);
7051 if (type_is_invalid(field_ptr->value->type))7051 if (type_is_invalid(field_ptr->value->type))
7052 return ira->codegen->invalid_inst_gen;7052 return ira->codegen->invalid_inst_gen;
7053 IrInstGen *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);7053 Stage1AirInst *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);
7054 if (type_is_invalid(field_value->value->type))7054 if (type_is_invalid(field_value->value->type))
7055 return ira->codegen->invalid_inst_gen;7055 return ira->codegen->invalid_inst_gen;
7056 IrInstGen *casted_value = ir_implicit_cast(ira, field_value, dst_field->type_entry);7056 Stage1AirInst *casted_value = ir_implicit_cast(ira, field_value, dst_field->type_entry);
7057 if (type_is_invalid(casted_value->value->type))7057 if (type_is_invalid(casted_value->value->type))
7058 return ira->codegen->invalid_inst_gen;7058 return ira->codegen->invalid_inst_gen;
70597059
...@@ -7103,12 +7103,12 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco...@@ -7103,12 +7103,12 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco
71037103
7104 if (is_comptime) {7104 if (is_comptime) {
7105 heap::c_allocator.deallocate(field_assign_nodes, actual_field_count);7105 heap::c_allocator.deallocate(field_assign_nodes, actual_field_count);
7106 IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type);7106 Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type);
7107 const_result->value->data.x_struct.fields = field_values;7107 const_result->value->data.x_struct.fields = field_values;
7108 return const_result;7108 return const_result;
7109 }7109 }
71107110
7111 IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),7111 Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
7112 wanted_type, nullptr, true, true);7112 wanted_type, nullptr, true, true);
7113 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {7113 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {
7114 return ira->codegen->invalid_inst_gen;7114 return ira->codegen->invalid_inst_gen;
...@@ -7119,10 +7119,10 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco...@@ -7119,10 +7119,10 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco
7119 if (field->is_comptime)7119 if (field->is_comptime)
7120 continue;7120 continue;
71217121
7122 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc_inst, wanted_type, true);7122 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc_inst, wanted_type, true);
7123 if (type_is_invalid(field_ptr->value->type))7123 if (type_is_invalid(field_ptr->value->type))
7124 return ira->codegen->invalid_inst_gen;7124 return ira->codegen->invalid_inst_gen;
7125 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, field_ptr, casted_fields[i], true);7125 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, field_ptr, casted_fields[i], true);
7126 if (type_is_invalid(store_ptr_inst->value->type))7126 if (type_is_invalid(store_ptr_inst->value->type))
7127 return ira->codegen->invalid_inst_gen;7127 return ira->codegen->invalid_inst_gen;
7128 }7128 }
...@@ -7134,8 +7134,8 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco...@@ -7134,8 +7134,8 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco
7134 return result_loc_inst;7134 return result_loc_inst;
7135}7135}
71367136
7137static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node,7137static Stage1AirInst *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7138 IrInstGen *struct_ptr, ZigType *struct_type, ZigType *union_type)7138 Stage1AirInst *struct_ptr, ZigType *struct_type, ZigType *union_type)
7139{7139{
7140 Error err;7140 Error err;
71417141
...@@ -7160,15 +7160,15 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop...@@ -7160,15 +7160,15 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop
7160 if (payload_type == nullptr)7160 if (payload_type == nullptr)
7161 return ira->codegen->invalid_inst_gen;7161 return ira->codegen->invalid_inst_gen;
71627162
7163 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, only_field, struct_ptr,7163 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, only_field, struct_ptr,
7164 struct_type, false);7164 struct_type, false);
7165 if (type_is_invalid(field_ptr->value->type))7165 if (type_is_invalid(field_ptr->value->type))
7166 return ira->codegen->invalid_inst_gen;7166 return ira->codegen->invalid_inst_gen;
7167 IrInstGen *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);7167 Stage1AirInst *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);
7168 if (type_is_invalid(field_value->value->type))7168 if (type_is_invalid(field_value->value->type))
7169 return ira->codegen->invalid_inst_gen;7169 return ira->codegen->invalid_inst_gen;
71707170
7171 IrInstGen *casted_value = ir_implicit_cast(ira, field_value, payload_type);7171 Stage1AirInst *casted_value = ir_implicit_cast(ira, field_value, payload_type);
7172 if (type_is_invalid(casted_value->value->type))7172 if (type_is_invalid(casted_value->value->type))
7173 return ira->codegen->invalid_inst_gen;7173 return ira->codegen->invalid_inst_gen;
71747174
...@@ -7177,7 +7177,7 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop...@@ -7177,7 +7177,7 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop
7177 if (val == nullptr)7177 if (val == nullptr)
7178 return ira->codegen->invalid_inst_gen;7178 return ira->codegen->invalid_inst_gen;
71797179
7180 IrInstGen *result = ir_const(ira, scope, source_node, union_type);7180 Stage1AirInst *result = ir_const(ira, scope, source_node, union_type);
7181 bigint_init_bigint(&result->value->data.x_union.tag, &union_field->enum_field->value);7181 bigint_init_bigint(&result->value->data.x_union.tag, &union_field->enum_field->value);
7182 result->value->data.x_union.payload = val;7182 result->value->data.x_union.payload = val;
71837183
...@@ -7187,18 +7187,18 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop...@@ -7187,18 +7187,18 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop
7187 return result;7187 return result;
7188 }7188 }
71897189
7190 IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),7190 Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
7191 union_type, nullptr, true, true);7191 union_type, nullptr, true, true);
7192 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {7192 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {
7193 return ira->codegen->invalid_inst_gen;7193 return ira->codegen->invalid_inst_gen;
7194 }7194 }
71957195
7196 IrInstGen *payload_ptr = ir_analyze_container_field_ptr(ira, only_field->name,7196 Stage1AirInst *payload_ptr = ir_analyze_container_field_ptr(ira, only_field->name,
7197 scope, source_node, result_loc_inst, source_node, union_type, true);7197 scope, source_node, result_loc_inst, source_node, union_type, true);
7198 if (type_is_invalid(payload_ptr->value->type))7198 if (type_is_invalid(payload_ptr->value->type))
7199 return ira->codegen->invalid_inst_gen;7199 return ira->codegen->invalid_inst_gen;
72007200
7201 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, payload_ptr, casted_value, false);7201 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, payload_ptr, casted_value, false);
7202 if (type_is_invalid(store_ptr_inst->value->type))7202 if (type_is_invalid(store_ptr_inst->value->type))
7203 return ira->codegen->invalid_inst_gen;7203 return ira->codegen->invalid_inst_gen;
72047204
...@@ -7243,30 +7243,30 @@ static Error ir_cast_ptr_align(IrAnalyze *ira, Scope *scope, AstNode *source_nod...@@ -7243,30 +7243,30 @@ static Error ir_cast_ptr_align(IrAnalyze *ira, Scope *scope, AstNode *source_nod
7243 return ErrorNone;7243 return ErrorNone;
7244}7244}
72457245
7246static IrInstGen *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,7246static Stage1AirInst *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7247 IrInstGen *struct_operand, TypeStructField *field)7247 Stage1AirInst *struct_operand, TypeStructField *field)
7248{7248{
7249 IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, struct_operand, true, false);7249 Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, struct_operand, true, false);
7250 if (type_is_invalid(struct_ptr->value->type))7250 if (type_is_invalid(struct_ptr->value->type))
7251 return ira->codegen->invalid_inst_gen;7251 return ira->codegen->invalid_inst_gen;
7252 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, struct_ptr,7252 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, struct_ptr,
7253 struct_operand->value->type, false);7253 struct_operand->value->type, false);
7254 if (type_is_invalid(field_ptr->value->type))7254 if (type_is_invalid(field_ptr->value->type))
7255 return ira->codegen->invalid_inst_gen;7255 return ira->codegen->invalid_inst_gen;
7256 return ir_get_deref(ira, scope, source_node, field_ptr, nullptr);7256 return ir_get_deref(ira, scope, source_node, field_ptr, nullptr);
7257}7257}
72587258
7259static IrInstGen *ir_analyze_optional_value_payload_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,7259static Stage1AirInst *ir_analyze_optional_value_payload_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7260 IrInstGen *optional_operand, bool safety_check_on)7260 Stage1AirInst *optional_operand, bool safety_check_on)
7261{7261{
7262 IrInstGen *opt_ptr = ir_get_ref(ira, scope, source_node, optional_operand, true, false);7262 Stage1AirInst *opt_ptr = ir_get_ref(ira, scope, source_node, optional_operand, true, false);
7263 IrInstGen *payload_ptr = ir_analyze_unwrap_optional_payload(ira, scope, source_node, opt_ptr,7263 Stage1AirInst *payload_ptr = ir_analyze_unwrap_optional_payload(ira, scope, source_node, opt_ptr,
7264 safety_check_on, false);7264 safety_check_on, false);
7265 return ir_get_deref(ira, scope, source_node, payload_ptr, nullptr);7265 return ir_get_deref(ira, scope, source_node, payload_ptr, nullptr);
7266}7266}
72677267
7268static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,7268static Stage1AirInst *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7269 ZigType *wanted_type, IrInstGen *value)7269 ZigType *wanted_type, Stage1AirInst *value)
7270{7270{
7271 Error err;7271 Error err;
7272 ZigType *actual_type = value->value->type;7272 ZigType *actual_type = value->value->type;
...@@ -7336,7 +7336,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7336,7 +7336,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7336 actual_type->data.pointer.child_type->data.array.child_type, source_node,7336 actual_type->data.pointer.child_type->data.array.child_type, source_node,
7337 !wanted_child_type->data.pointer.is_const).id == ConstCastResultIdOk)7337 !wanted_child_type->data.pointer.is_const).id == ConstCastResultIdOk)
7338 {7338 {
7339 IrInstGen *cast1 = ir_resolve_ptr_of_array_to_unknown_len_ptr(ira, scope, source_node, value,7339 Stage1AirInst *cast1 = ir_resolve_ptr_of_array_to_unknown_len_ptr(ira, scope, source_node, value,
7340 wanted_child_type);7340 wanted_child_type);
7341 if (type_is_invalid(cast1->value->type))7341 if (type_is_invalid(cast1->value->type))
7342 return ira->codegen->invalid_inst_gen;7342 return ira->codegen->invalid_inst_gen;
...@@ -7373,11 +7373,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7373,11 +7373,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7373 actual_type->id == ZigTypeIdComptimeInt ||7373 actual_type->id == ZigTypeIdComptimeInt ||
7374 actual_type->id == ZigTypeIdComptimeFloat)7374 actual_type->id == ZigTypeIdComptimeFloat)
7375 {7375 {
7376 IrInstGen *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.error_union.payload_type, value);7376 Stage1AirInst *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.error_union.payload_type, value);
7377 if (type_is_invalid(cast1->value->type))7377 if (type_is_invalid(cast1->value->type))
7378 return ira->codegen->invalid_inst_gen;7378 return ira->codegen->invalid_inst_gen;
73797379
7380 IrInstGen *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);7380 Stage1AirInst *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);
7381 if (type_is_invalid(cast2->value->type))7381 if (type_is_invalid(cast2->value->type))
7382 return ira->codegen->invalid_inst_gen;7382 return ira->codegen->invalid_inst_gen;
73837383
...@@ -7394,13 +7394,13 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7394,13 +7394,13 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7394 wanted_type->id == ZigTypeIdFloat || wanted_type->id == ZigTypeIdComptimeFloat))7394 wanted_type->id == ZigTypeIdFloat || wanted_type->id == ZigTypeIdComptimeFloat))
7395 {7395 {
7396 if (value->value->special == ConstValSpecialUndef) {7396 if (value->value->special == ConstValSpecialUndef) {
7397 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);7397 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
7398 result->value->special = ConstValSpecialUndef;7398 result->value->special = ConstValSpecialUndef;
7399 return result;7399 return result;
7400 }7400 }
7401 if (ir_num_lit_fits_in_other_type(ira, value, wanted_type, true)) {7401 if (ir_num_lit_fits_in_other_type(ira, value, wanted_type, true)) {
7402 if (wanted_type->id == ZigTypeIdComptimeInt || wanted_type->id == ZigTypeIdInt) {7402 if (wanted_type->id == ZigTypeIdComptimeInt || wanted_type->id == ZigTypeIdInt) {
7403 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);7403 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
7404 if (actual_type->id == ZigTypeIdComptimeInt || actual_type->id == ZigTypeIdInt) {7404 if (actual_type->id == ZigTypeIdComptimeInt || actual_type->id == ZigTypeIdInt) {
7405 copy_const_val(ira->codegen, result->value, value->value);7405 copy_const_val(ira->codegen, result->value, value->value);
7406 result->value->type = wanted_type;7406 result->value->type = wanted_type;
...@@ -7409,7 +7409,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7409,7 +7409,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7409 }7409 }
7410 return result;7410 return result;
7411 } else if (wanted_type->id == ZigTypeIdComptimeFloat || wanted_type->id == ZigTypeIdFloat) {7411 } else if (wanted_type->id == ZigTypeIdComptimeFloat || wanted_type->id == ZigTypeIdFloat) {
7412 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);7412 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
7413 if (actual_type->id == ZigTypeIdComptimeInt || actual_type->id == ZigTypeIdInt) {7413 if (actual_type->id == ZigTypeIdComptimeInt || actual_type->id == ZigTypeIdInt) {
7414 BigFloat bf;7414 BigFloat bf;
7415 bigfloat_init_bigint(&bf, &value->value->data.x_bigint);7415 bigfloat_init_bigint(&bf, &value->value->data.x_bigint);
...@@ -7457,11 +7457,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7457,11 +7457,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7457 actual_type->data.pointer.ptr_len == PtrLenSingle &&7457 actual_type->data.pointer.ptr_len == PtrLenSingle &&
7458 actual_type->data.pointer.child_type->id == ZigTypeIdArray)7458 actual_type->data.pointer.child_type->id == ZigTypeIdArray)
7459 {7459 {
7460 IrInstGen *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.maybe.child_type, value);7460 Stage1AirInst *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.maybe.child_type, value);
7461 if (type_is_invalid(cast1->value->type))7461 if (type_is_invalid(cast1->value->type))
7462 return ira->codegen->invalid_inst_gen;7462 return ira->codegen->invalid_inst_gen;
74637463
7464 IrInstGen *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);7464 Stage1AirInst *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);
7465 if (type_is_invalid(cast2->value->type))7465 if (type_is_invalid(cast2->value->type))
7466 return ira->codegen->invalid_inst_gen;7466 return ira->codegen->invalid_inst_gen;
74677467
...@@ -7543,11 +7543,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7543,11 +7543,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7543 }7543 }
7544 if (ok_align) {7544 if (ok_align) {
7545 if (wanted_type->id == ZigTypeIdErrorUnion) {7545 if (wanted_type->id == ZigTypeIdErrorUnion) {
7546 IrInstGen *cast1 = ir_analyze_cast(ira, scope, source_node, slice_type, value);7546 Stage1AirInst *cast1 = ir_analyze_cast(ira, scope, source_node, slice_type, value);
7547 if (type_is_invalid(cast1->value->type))7547 if (type_is_invalid(cast1->value->type))
7548 return ira->codegen->invalid_inst_gen;7548 return ira->codegen->invalid_inst_gen;
75497549
7550 IrInstGen *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);7550 Stage1AirInst *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);
7551 if (type_is_invalid(cast2->value->type))7551 if (type_is_invalid(cast2->value->type))
7552 return ira->codegen->invalid_inst_gen;7552 return ira->codegen->invalid_inst_gen;
75537553
...@@ -7623,7 +7623,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7623,7 +7623,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7623 }7623 }
7624 }7624 }
7625 if (ok) {7625 if (ok) {
7626 IrInstGen *cast1 = ir_analyze_frame_ptr_to_anyframe(ira, scope, source_node, value, anyframe_type);7626 Stage1AirInst *cast1 = ir_analyze_frame_ptr_to_anyframe(ira, scope, source_node, value, anyframe_type);
7627 if (anyframe_type == wanted_type)7627 if (anyframe_type == wanted_type)
7628 return cast1;7628 return cast1;
7629 return ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);7629 return ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);
...@@ -7678,7 +7678,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7678,7 +7678,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7678 if (actual_type->id == ZigTypeIdEnumLiteral &&7678 if (actual_type->id == ZigTypeIdEnumLiteral &&
7679 (wanted_type->id == ZigTypeIdOptional && wanted_type->data.maybe.child_type->id == ZigTypeIdEnum))7679 (wanted_type->id == ZigTypeIdOptional && wanted_type->data.maybe.child_type->id == ZigTypeIdEnum))
7680 {7680 {
7681 IrInstGen *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.maybe.child_type);7681 Stage1AirInst *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.maybe.child_type);
7682 if (type_is_invalid(result->value->type))7682 if (type_is_invalid(result->value->type))
7683 return result;7683 return result;
76847684
...@@ -7689,7 +7689,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7689,7 +7689,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7689 if (actual_type->id == ZigTypeIdEnumLiteral &&7689 if (actual_type->id == ZigTypeIdEnumLiteral &&
7690 (wanted_type->id == ZigTypeIdErrorUnion && wanted_type->data.error_union.payload_type->id == ZigTypeIdEnum))7690 (wanted_type->id == ZigTypeIdErrorUnion && wanted_type->data.error_union.payload_type->id == ZigTypeIdEnum))
7691 {7691 {
7692 IrInstGen *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.error_union.payload_type);7692 Stage1AirInst *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.error_union.payload_type);
7693 if (type_is_invalid(result->value->type))7693 if (type_is_invalid(result->value->type))
7694 return result;7694 return result;
76957695
...@@ -7751,7 +7751,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7751,7 +7751,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7751 slice_ptr_type->data.pointer.sentinel))))7751 slice_ptr_type->data.pointer.sentinel))))
7752 {7752 {
7753 TypeStructField *ptr_field = actual_type->data.structure.fields[slice_ptr_index];7753 TypeStructField *ptr_field = actual_type->data.structure.fields[slice_ptr_index];
7754 IrInstGen *slice_ptr = ir_analyze_struct_value_field_value(ira, scope, source_node, value, ptr_field);7754 Stage1AirInst *slice_ptr = ir_analyze_struct_value_field_value(ira, scope, source_node, value, ptr_field);
7755 return ir_implicit_cast2(ira, scope, source_node, slice_ptr, wanted_type);7755 return ir_implicit_cast2(ira, scope, source_node, slice_ptr, wanted_type);
7756 }7756 }
7757 }7757 }
...@@ -7835,31 +7835,31 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7835,31 +7835,31 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7835 if (wanted_type->id == ZigTypeIdArray && (is_array_init || field_count == 0) &&7835 if (wanted_type->id == ZigTypeIdArray && (is_array_init || field_count == 0) &&
7836 wanted_type->data.array.len == field_count)7836 wanted_type->data.array.len == field_count)
7837 {7837 {
7838 IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);7838 Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);
7839 if (type_is_invalid(struct_ptr->value->type))7839 if (type_is_invalid(struct_ptr->value->type))
7840 return ira->codegen->invalid_inst_gen;7840 return ira->codegen->invalid_inst_gen;
78417841
7842 IrInstGen *ptr = ir_analyze_struct_literal_to_array(ira, scope, source_node, struct_ptr, actual_type, wanted_type);7842 Stage1AirInst *ptr = ir_analyze_struct_literal_to_array(ira, scope, source_node, struct_ptr, actual_type, wanted_type);
7843 if (ptr->value->type->id != ZigTypeIdPointer)7843 if (ptr->value->type->id != ZigTypeIdPointer)
7844 return ptr;7844 return ptr;
7845 return ir_get_deref(ira, scope, source_node, ptr, nullptr);7845 return ir_get_deref(ira, scope, source_node, ptr, nullptr);
7846 } else if (wanted_type->id == ZigTypeIdStruct && !is_slice(wanted_type) &&7846 } else if (wanted_type->id == ZigTypeIdStruct && !is_slice(wanted_type) &&
7847 (!is_array_init || field_count == 0))7847 (!is_array_init || field_count == 0))
7848 {7848 {
7849 IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);7849 Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);
7850 if (type_is_invalid(struct_ptr->value->type))7850 if (type_is_invalid(struct_ptr->value->type))
7851 return ira->codegen->invalid_inst_gen;7851 return ira->codegen->invalid_inst_gen;
78527852
7853 IrInstGen *ptr = ir_analyze_struct_literal_to_struct(ira, scope, source_node, struct_ptr, actual_type, wanted_type);7853 Stage1AirInst *ptr = ir_analyze_struct_literal_to_struct(ira, scope, source_node, struct_ptr, actual_type, wanted_type);
7854 if (ptr->value->type->id != ZigTypeIdPointer)7854 if (ptr->value->type->id != ZigTypeIdPointer)
7855 return ptr;7855 return ptr;
7856 return ir_get_deref(ira, scope, source_node, ptr, nullptr);7856 return ir_get_deref(ira, scope, source_node, ptr, nullptr);
7857 } else if (wanted_type->id == ZigTypeIdUnion && !is_array_init && field_count == 1) {7857 } else if (wanted_type->id == ZigTypeIdUnion && !is_array_init && field_count == 1) {
7858 IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);7858 Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);
7859 if (type_is_invalid(struct_ptr->value->type))7859 if (type_is_invalid(struct_ptr->value->type))
7860 return ira->codegen->invalid_inst_gen;7860 return ira->codegen->invalid_inst_gen;
78617861
7862 IrInstGen *ptr = ir_analyze_struct_literal_to_union(ira, scope, source_node, struct_ptr, actual_type, wanted_type);7862 Stage1AirInst *ptr = ir_analyze_struct_literal_to_union(ira, scope, source_node, struct_ptr, actual_type, wanted_type);
7863 if (ptr->value->type->id != ZigTypeIdPointer)7863 if (ptr->value->type->id != ZigTypeIdPointer)
7864 return ptr;7864 return ptr;
7865 return ir_get_deref(ira, scope, source_node, ptr, nullptr);7865 return ir_get_deref(ira, scope, source_node, ptr, nullptr);
...@@ -7881,19 +7881,19 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7881,19 +7881,19 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7881 if (wanted_child->id == ZigTypeIdArray && (is_array_init || field_count == 0) &&7881 if (wanted_child->id == ZigTypeIdArray && (is_array_init || field_count == 0) &&
7882 wanted_child->data.array.len == field_count && (const_ok || field_count == 0))7882 wanted_child->data.array.len == field_count && (const_ok || field_count == 0))
7883 {7883 {
7884 IrInstGen *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, wanted_child);7884 Stage1AirInst *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, wanted_child);
7885 if (res->value->type->id == ZigTypeIdPointer)7885 if (res->value->type->id == ZigTypeIdPointer)
7886 return res;7886 return res;
7887 return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile);7887 return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile);
7888 } else if (wanted_child->id == ZigTypeIdStruct && !is_slice(wanted_type) &&7888 } else if (wanted_child->id == ZigTypeIdStruct && !is_slice(wanted_type) &&
7889 (!is_array_init || field_count == 0) && const_ok)7889 (!is_array_init || field_count == 0) && const_ok)
7890 {7890 {
7891 IrInstGen *res = ir_analyze_struct_literal_to_struct(ira, scope, source_node, value, anon_type, wanted_child);7891 Stage1AirInst *res = ir_analyze_struct_literal_to_struct(ira, scope, source_node, value, anon_type, wanted_child);
7892 if (res->value->type->id == ZigTypeIdPointer)7892 if (res->value->type->id == ZigTypeIdPointer)
7893 return res;7893 return res;
7894 return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile);7894 return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile);
7895 } else if (wanted_child->id == ZigTypeIdUnion && !is_array_init && field_count == 1 && const_ok) {7895 } else if (wanted_child->id == ZigTypeIdUnion && !is_array_init && field_count == 1 && const_ok) {
7896 IrInstGen *res = ir_analyze_struct_literal_to_union(ira, scope, source_node, value, anon_type, wanted_child);7896 Stage1AirInst *res = ir_analyze_struct_literal_to_union(ira, scope, source_node, value, anon_type, wanted_child);
7897 if (res->value->type->id == ZigTypeIdPointer)7897 if (res->value->type->id == ZigTypeIdPointer)
7898 return res;7898 return res;
7899 return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile);7899 return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile);
...@@ -7905,7 +7905,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7905,7 +7905,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7905 {7905 {
7906 ZigType *slice_child_type = slice_type->data.pointer.child_type;7906 ZigType *slice_child_type = slice_type->data.pointer.child_type;
7907 ZigType *slice_array_type = get_array_type(ira->codegen, slice_child_type, field_count, nullptr);7907 ZigType *slice_array_type = get_array_type(ira->codegen, slice_child_type, field_count, nullptr);
7908 IrInstGen *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, slice_array_type);7908 Stage1AirInst *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, slice_array_type);
7909 if (type_is_invalid(res->value->type))7909 if (type_is_invalid(res->value->type))
7910 return ira->codegen->invalid_inst_gen;7910 return ira->codegen->invalid_inst_gen;
7911 if (res->value->type->id != ZigTypeIdPointer)7911 if (res->value->type->id != ZigTypeIdPointer)
...@@ -7923,7 +7923,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7923,7 +7923,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
79237923
7924 // T to ?U, where T implicitly casts to U7924 // T to ?U, where T implicitly casts to U
7925 if (wanted_type->id == ZigTypeIdOptional && actual_type->id != ZigTypeIdOptional) {7925 if (wanted_type->id == ZigTypeIdOptional && actual_type->id != ZigTypeIdOptional) {
7926 IrInstGen *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.maybe.child_type);7926 Stage1AirInst *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.maybe.child_type);
7927 if (type_is_invalid(cast1->value->type))7927 if (type_is_invalid(cast1->value->type))
7928 return ira->codegen->invalid_inst_gen;7928 return ira->codegen->invalid_inst_gen;
7929 return ir_implicit_cast2(ira, scope, source_node, cast1, wanted_type);7929 return ir_implicit_cast2(ira, scope, source_node, cast1, wanted_type);
...@@ -7933,7 +7933,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7933,7 +7933,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7933 if (wanted_type->id == ZigTypeIdErrorUnion && actual_type->id != ZigTypeIdErrorUnion &&7933 if (wanted_type->id == ZigTypeIdErrorUnion && actual_type->id != ZigTypeIdErrorUnion &&
7934 actual_type->id != ZigTypeIdErrorSet)7934 actual_type->id != ZigTypeIdErrorSet)
7935 {7935 {
7936 IrInstGen *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.error_union.payload_type);7936 Stage1AirInst *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.error_union.payload_type);
7937 if (type_is_invalid(cast1->value->type))7937 if (type_is_invalid(cast1->value->type))
7938 return ira->codegen->invalid_inst_gen;7938 return ira->codegen->invalid_inst_gen;
7939 return ir_implicit_cast2(ira, scope, source_node, cast1, wanted_type);7939 return ir_implicit_cast2(ira, scope, source_node, cast1, wanted_type);
...@@ -7947,8 +7947,8 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -7947,8 +7947,8 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
7947 return ira->codegen->invalid_inst_gen;7947 return ira->codegen->invalid_inst_gen;
7948}7948}
79497949
7950static IrInstGen *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node,7950static Stage1AirInst *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7951 IrInstGen *value, ZigType *expected_type)7951 Stage1AirInst *value, ZigType *expected_type)
7952{7952{
7953 assert(value);7953 assert(value);
7954 assert(!expected_type || !type_is_invalid(expected_type));7954 assert(!expected_type || !type_is_invalid(expected_type));
...@@ -7964,11 +7964,11 @@ static IrInstGen *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *sourc...@@ -7964,11 +7964,11 @@ static IrInstGen *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *sourc
7964 return ir_analyze_cast(ira, scope, source_node, expected_type, value);7964 return ir_analyze_cast(ira, scope, source_node, expected_type, value);
7965}7965}
79667966
7967static IrInstGen *ir_implicit_cast(IrAnalyze *ira, IrInstGen *value, ZigType *expected_type) {7967static Stage1AirInst *ir_implicit_cast(IrAnalyze *ira, Stage1AirInst *value, ZigType *expected_type) {
7968 return ir_implicit_cast2(ira, value->scope, value->source_node, value, expected_type);7968 return ir_implicit_cast2(ira, value->scope, value->source_node, value, expected_type);
7969}7969}
79707970
7971static ZigType *get_ptr_elem_type(CodeGen *g, IrInstGen *ptr) {7971static ZigType *get_ptr_elem_type(CodeGen *g, Stage1AirInst *ptr) {
7972 ir_assert(ptr->value->type->id == ZigTypeIdPointer, ptr);7972 ir_assert(ptr->value->type->id == ZigTypeIdPointer, ptr);
7973 ZigType *elem_type = ptr->value->type->data.pointer.child_type;7973 ZigType *elem_type = ptr->value->type->data.pointer.child_type;
7974 if (elem_type != g->builtin_types.entry_anytype)7974 if (elem_type != g->builtin_types.entry_anytype)
...@@ -7982,7 +7982,7 @@ static ZigType *get_ptr_elem_type(CodeGen *g, IrInstGen *ptr) {...@@ -7982,7 +7982,7 @@ static ZigType *get_ptr_elem_type(CodeGen *g, IrInstGen *ptr) {
7982 return pointee->type;7982 return pointee->type;
7983}7983}
79847984
7985static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *ptr,7985static Stage1AirInst *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *ptr,
7986 ResultLoc *result_loc)7986 ResultLoc *result_loc)
7987{7987{
7988 Error err;7988 Error err;
...@@ -8027,7 +8027,7 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod...@@ -8027,7 +8027,7 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod
8027 child_type = pointee->type;8027 child_type = pointee->type;
8028 }8028 }
8029 if (pointee->special != ConstValSpecialRuntime) {8029 if (pointee->special != ConstValSpecialRuntime) {
8030 IrInstGen *result = ir_const(ira, scope, source_node, child_type);8030 Stage1AirInst *result = ir_const(ira, scope, source_node, child_type);
80318031
8032 if ((err = ir_read_const_ptr(ira, ira->codegen, source_node, result->value,8032 if ((err = ir_read_const_ptr(ira, ira->codegen, source_node, result->value,
8033 ptr->value)))8033 ptr->value)))
...@@ -8041,25 +8041,25 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod...@@ -8041,25 +8041,25 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod
8041 }8041 }
80428042
8043 // if the instruction is a const ref instruction we can skip it8043 // if the instruction is a const ref instruction we can skip it
8044 if (ptr->id == IrInstGenIdRef) {8044 if (ptr->id == Stage1AirInstIdRef) {
8045 IrInstGenRef *ref_inst = reinterpret_cast<IrInstGenRef *>(ptr);8045 Stage1AirInstRef *ref_inst = reinterpret_cast<Stage1AirInstRef *>(ptr);
8046 return ref_inst->operand;8046 return ref_inst->operand;
8047 }8047 }
80488048
8049 // If the instruction is a element pointer instruction to a vector, we emit8049 // If the instruction is a element pointer instruction to a vector, we emit
8050 // vector element extract instruction rather than load pointer. If the8050 // vector element extract instruction rather than load pointer. If the
8051 // pointer type has non-VECTOR_INDEX_RUNTIME value, it would have been8051 // pointer type has non-VECTOR_INDEX_RUNTIME value, it would have been
8052 // possible to implement this in the codegen for IrInstGenLoadPtr.8052 // possible to implement this in the codegen for Stage1AirInstLoadPtr.
8053 // However if it has VECTOR_INDEX_RUNTIME then we must emit a compile error8053 // However if it has VECTOR_INDEX_RUNTIME then we must emit a compile error
8054 // if the vector index cannot be determined right here, right now, because8054 // if the vector index cannot be determined right here, right now, because
8055 // the type information does not contain enough information to actually8055 // the type information does not contain enough information to actually
8056 // perform a dereference.8056 // perform a dereference.
8057 if (ptr_type->data.pointer.vector_index == VECTOR_INDEX_RUNTIME) {8057 if (ptr_type->data.pointer.vector_index == VECTOR_INDEX_RUNTIME) {
8058 if (ptr->id == IrInstGenIdElemPtr) {8058 if (ptr->id == Stage1AirInstIdElemPtr) {
8059 IrInstGenElemPtr *elem_ptr = (IrInstGenElemPtr *)ptr;8059 Stage1AirInstElemPtr *elem_ptr = (Stage1AirInstElemPtr *)ptr;
8060 IrInstGen *vector_loaded = ir_get_deref(ira, elem_ptr->array_ptr->scope,8060 Stage1AirInst *vector_loaded = ir_get_deref(ira, elem_ptr->array_ptr->scope,
8061 elem_ptr->array_ptr->source_node, elem_ptr->array_ptr, nullptr);8061 elem_ptr->array_ptr->source_node, elem_ptr->array_ptr, nullptr);
8062 IrInstGen *elem_index = elem_ptr->elem_index;8062 Stage1AirInst *elem_index = elem_ptr->elem_index;
8063 return ir_build_vector_extract_elem(ira, scope, source_node, vector_loaded, elem_index);8063 return ir_build_vector_extract_elem(ira, scope, source_node, vector_loaded, elem_index);
8064 }8064 }
8065 ir_add_error(ira, ptr,8065 ir_add_error(ira, ptr,
...@@ -8067,7 +8067,7 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod...@@ -8067,7 +8067,7 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod
8067 return ira->codegen->invalid_inst_gen;8067 return ira->codegen->invalid_inst_gen;
8068 }8068 }
80698069
8070 IrInstGen *result_loc_inst;8070 Stage1AirInst *result_loc_inst;
8071 if (ptr_type->data.pointer.host_int_bytes != 0 && handle_is_ptr(ira->codegen, child_type)) {8071 if (ptr_type->data.pointer.host_int_bytes != 0 && handle_is_ptr(ira->codegen, child_type)) {
8072 if (result_loc == nullptr) result_loc = no_result_loc();8072 if (result_loc == nullptr) result_loc = no_result_loc();
8073 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, child_type, nullptr, true, true);8073 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, child_type, nullptr, true, true);
...@@ -8104,7 +8104,7 @@ static bool ir_resolve_const_align(CodeGen *codegen, Stage1Air *exec, AstNode *s...@@ -8104,7 +8104,7 @@ static bool ir_resolve_const_align(CodeGen *codegen, Stage1Air *exec, AstNode *s
8104 return true;8104 return true;
8105}8105}
81068106
8107static bool ir_resolve_align(IrAnalyze *ira, IrInstGen *value, ZigType *elem_type, uint32_t *out) {8107static bool ir_resolve_align(IrAnalyze *ira, Stage1AirInst *value, ZigType *elem_type, uint32_t *out) {
8108 if (type_is_invalid(value->value->type))8108 if (type_is_invalid(value->value->type))
8109 return false;8109 return false;
81108110
...@@ -8125,7 +8125,7 @@ static bool ir_resolve_align(IrAnalyze *ira, IrInstGen *value, ZigType *elem_typ...@@ -8125,7 +8125,7 @@ static bool ir_resolve_align(IrAnalyze *ira, IrInstGen *value, ZigType *elem_typ
8125 }8125 }
8126 }8126 }
81278127
8128 IrInstGen *casted_value = ir_implicit_cast(ira, value, get_align_amt_type(ira->codegen));8128 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, get_align_amt_type(ira->codegen));
8129 if (type_is_invalid(casted_value->value->type))8129 if (type_is_invalid(casted_value->value->type))
8130 return false;8130 return false;
81318131
...@@ -8133,11 +8133,11 @@ static bool ir_resolve_align(IrAnalyze *ira, IrInstGen *value, ZigType *elem_typ...@@ -8133,11 +8133,11 @@ static bool ir_resolve_align(IrAnalyze *ira, IrInstGen *value, ZigType *elem_typ
8133 casted_value->value, out);8133 casted_value->value, out);
8134}8134}
81358135
8136static bool ir_resolve_unsigned(IrAnalyze *ira, IrInstGen *value, ZigType *int_type, uint64_t *out) {8136static bool ir_resolve_unsigned(IrAnalyze *ira, Stage1AirInst *value, ZigType *int_type, uint64_t *out) {
8137 if (type_is_invalid(value->value->type))8137 if (type_is_invalid(value->value->type))
8138 return false;8138 return false;
81398139
8140 IrInstGen *casted_value = ir_implicit_cast(ira, value, int_type);8140 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, int_type);
8141 if (type_is_invalid(casted_value->value->type))8141 if (type_is_invalid(casted_value->value->type))
8142 return false;8142 return false;
81438143
...@@ -8149,15 +8149,15 @@ static bool ir_resolve_unsigned(IrAnalyze *ira, IrInstGen *value, ZigType *int_t...@@ -8149,15 +8149,15 @@ static bool ir_resolve_unsigned(IrAnalyze *ira, IrInstGen *value, ZigType *int_t
8149 return true;8149 return true;
8150}8150}
81518151
8152static bool ir_resolve_usize(IrAnalyze *ira, IrInstGen *value, uint64_t *out) {8152static bool ir_resolve_usize(IrAnalyze *ira, Stage1AirInst *value, uint64_t *out) {
8153 return ir_resolve_unsigned(ira, value, ira->codegen->builtin_types.entry_usize, out);8153 return ir_resolve_unsigned(ira, value, ira->codegen->builtin_types.entry_usize, out);
8154}8154}
81558155
8156static bool ir_resolve_bool(IrAnalyze *ira, IrInstGen *value, bool *out) {8156static bool ir_resolve_bool(IrAnalyze *ira, Stage1AirInst *value, bool *out) {
8157 if (type_is_invalid(value->value->type))8157 if (type_is_invalid(value->value->type))
8158 return false;8158 return false;
81598159
8160 IrInstGen *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_bool);8160 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_bool);
8161 if (type_is_invalid(casted_value->value->type))8161 if (type_is_invalid(casted_value->value->type))
8162 return false;8162 return false;
81638163
...@@ -8169,7 +8169,7 @@ static bool ir_resolve_bool(IrAnalyze *ira, IrInstGen *value, bool *out) {...@@ -8169,7 +8169,7 @@ static bool ir_resolve_bool(IrAnalyze *ira, IrInstGen *value, bool *out) {
8169 return true;8169 return true;
8170}8170}
81718171
8172static bool ir_resolve_comptime(IrAnalyze *ira, IrInstGen *value, bool *out) {8172static bool ir_resolve_comptime(IrAnalyze *ira, Stage1AirInst *value, bool *out) {
8173 if (!value) {8173 if (!value) {
8174 *out = false;8174 *out = false;
8175 return true;8175 return true;
...@@ -8177,13 +8177,13 @@ static bool ir_resolve_comptime(IrAnalyze *ira, IrInstGen *value, bool *out) {...@@ -8177,13 +8177,13 @@ static bool ir_resolve_comptime(IrAnalyze *ira, IrInstGen *value, bool *out) {
8177 return ir_resolve_bool(ira, value, out);8177 return ir_resolve_bool(ira, value, out);
8178}8178}
81798179
8180static bool ir_resolve_reduce_op(IrAnalyze *ira, IrInstGen *value, ReduceOp *out) {8180static bool ir_resolve_reduce_op(IrAnalyze *ira, Stage1AirInst *value, ReduceOp *out) {
8181 if (type_is_invalid(value->value->type))8181 if (type_is_invalid(value->value->type))
8182 return false;8182 return false;
81838183
8184 ZigType *reduce_op_type = get_builtin_type(ira->codegen, "ReduceOp");8184 ZigType *reduce_op_type = get_builtin_type(ira->codegen, "ReduceOp");
81858185
8186 IrInstGen *casted_value = ir_implicit_cast(ira, value, reduce_op_type);8186 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, reduce_op_type);
8187 if (type_is_invalid(casted_value->value->type))8187 if (type_is_invalid(casted_value->value->type))
8188 return false;8188 return false;
81898189
...@@ -8195,13 +8195,13 @@ static bool ir_resolve_reduce_op(IrAnalyze *ira, IrInstGen *value, ReduceOp *out...@@ -8195,13 +8195,13 @@ static bool ir_resolve_reduce_op(IrAnalyze *ira, IrInstGen *value, ReduceOp *out
8195 return true;8195 return true;
8196}8196}
81978197
8198static bool ir_resolve_atomic_order(IrAnalyze *ira, IrInstGen *value, AtomicOrder *out) {8198static bool ir_resolve_atomic_order(IrAnalyze *ira, Stage1AirInst *value, AtomicOrder *out) {
8199 if (type_is_invalid(value->value->type))8199 if (type_is_invalid(value->value->type))
8200 return false;8200 return false;
82018201
8202 ZigType *atomic_order_type = get_builtin_type(ira->codegen, "AtomicOrder");8202 ZigType *atomic_order_type = get_builtin_type(ira->codegen, "AtomicOrder");
82038203
8204 IrInstGen *casted_value = ir_implicit_cast(ira, value, atomic_order_type);8204 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, atomic_order_type);
8205 if (type_is_invalid(casted_value->value->type))8205 if (type_is_invalid(casted_value->value->type))
8206 return false;8206 return false;
82078207
...@@ -8213,13 +8213,13 @@ static bool ir_resolve_atomic_order(IrAnalyze *ira, IrInstGen *value, AtomicOrde...@@ -8213,13 +8213,13 @@ static bool ir_resolve_atomic_order(IrAnalyze *ira, IrInstGen *value, AtomicOrde
8213 return true;8213 return true;
8214}8214}
82158215
8216static bool ir_resolve_atomic_rmw_op(IrAnalyze *ira, IrInstGen *value, AtomicRmwOp *out) {8216static bool ir_resolve_atomic_rmw_op(IrAnalyze *ira, Stage1AirInst *value, AtomicRmwOp *out) {
8217 if (type_is_invalid(value->value->type))8217 if (type_is_invalid(value->value->type))
8218 return false;8218 return false;
82198219
8220 ZigType *atomic_rmw_op_type = get_builtin_type(ira->codegen, "AtomicRmwOp");8220 ZigType *atomic_rmw_op_type = get_builtin_type(ira->codegen, "AtomicRmwOp");
82218221
8222 IrInstGen *casted_value = ir_implicit_cast(ira, value, atomic_rmw_op_type);8222 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, atomic_rmw_op_type);
8223 if (type_is_invalid(casted_value->value->type))8223 if (type_is_invalid(casted_value->value->type))
8224 return false;8224 return false;
82258225
...@@ -8231,13 +8231,13 @@ static bool ir_resolve_atomic_rmw_op(IrAnalyze *ira, IrInstGen *value, AtomicRmw...@@ -8231,13 +8231,13 @@ static bool ir_resolve_atomic_rmw_op(IrAnalyze *ira, IrInstGen *value, AtomicRmw
8231 return true;8231 return true;
8232}8232}
82338233
8234static bool ir_resolve_global_linkage(IrAnalyze *ira, IrInstGen *value, GlobalLinkageId *out) {8234static bool ir_resolve_global_linkage(IrAnalyze *ira, Stage1AirInst *value, GlobalLinkageId *out) {
8235 if (type_is_invalid(value->value->type))8235 if (type_is_invalid(value->value->type))
8236 return false;8236 return false;
82378237
8238 ZigType *global_linkage_type = get_builtin_type(ira->codegen, "GlobalLinkage");8238 ZigType *global_linkage_type = get_builtin_type(ira->codegen, "GlobalLinkage");
82398239
8240 IrInstGen *casted_value = ir_implicit_cast(ira, value, global_linkage_type);8240 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, global_linkage_type);
8241 if (type_is_invalid(casted_value->value->type))8241 if (type_is_invalid(casted_value->value->type))
8242 return false;8242 return false;
82438243
...@@ -8249,13 +8249,13 @@ static bool ir_resolve_global_linkage(IrAnalyze *ira, IrInstGen *value, GlobalLi...@@ -8249,13 +8249,13 @@ static bool ir_resolve_global_linkage(IrAnalyze *ira, IrInstGen *value, GlobalLi
8249 return true;8249 return true;
8250}8250}
82518251
8252static bool ir_resolve_float_mode(IrAnalyze *ira, IrInstGen *value, FloatMode *out) {8252static bool ir_resolve_float_mode(IrAnalyze *ira, Stage1AirInst *value, FloatMode *out) {
8253 if (type_is_invalid(value->value->type))8253 if (type_is_invalid(value->value->type))
8254 return false;8254 return false;
82558255
8256 ZigType *float_mode_type = get_builtin_type(ira->codegen, "FloatMode");8256 ZigType *float_mode_type = get_builtin_type(ira->codegen, "FloatMode");
82578257
8258 IrInstGen *casted_value = ir_implicit_cast(ira, value, float_mode_type);8258 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, float_mode_type);
8259 if (type_is_invalid(casted_value->value->type))8259 if (type_is_invalid(casted_value->value->type))
8260 return false;8260 return false;
82618261
...@@ -8267,14 +8267,14 @@ static bool ir_resolve_float_mode(IrAnalyze *ira, IrInstGen *value, FloatMode *o...@@ -8267,14 +8267,14 @@ static bool ir_resolve_float_mode(IrAnalyze *ira, IrInstGen *value, FloatMode *o
8267 return true;8267 return true;
8268}8268}
82698269
8270static Buf *ir_resolve_str(IrAnalyze *ira, IrInstGen *value) {8270static Buf *ir_resolve_str(IrAnalyze *ira, Stage1AirInst *value) {
8271 if (type_is_invalid(value->value->type))8271 if (type_is_invalid(value->value->type))
8272 return nullptr;8272 return nullptr;
82738273
8274 ZigType *ptr_type = get_pointer_to_type_extra(ira->codegen, ira->codegen->builtin_types.entry_u8,8274 ZigType *ptr_type = get_pointer_to_type_extra(ira->codegen, ira->codegen->builtin_types.entry_u8,
8275 true, false, PtrLenUnknown, 0, 0, 0, false);8275 true, false, PtrLenUnknown, 0, 0, 0, false);
8276 ZigType *str_type = get_slice_type(ira->codegen, ptr_type);8276 ZigType *str_type = get_slice_type(ira->codegen, ptr_type);
8277 IrInstGen *casted_value = ir_implicit_cast(ira, value, str_type);8277 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, str_type);
8278 if (type_is_invalid(casted_value->value->type))8278 if (type_is_invalid(casted_value->value->type))
8279 return nullptr;8279 return nullptr;
82808280
...@@ -8309,10 +8309,10 @@ static Buf *ir_resolve_str(IrAnalyze *ira, IrInstGen *value) {...@@ -8309,10 +8309,10 @@ static Buf *ir_resolve_str(IrAnalyze *ira, IrInstGen *value) {
8309 return result;8309 return result;
8310}8310}
83118311
8312static IrInstGen *ir_analyze_instruction_add_implicit_return_type(IrAnalyze *ira,8312static Stage1AirInst *ir_analyze_instruction_add_implicit_return_type(IrAnalyze *ira,
8313 IrInstSrcAddImplicitReturnType *instruction)8313 Stage1ZirInstAddImplicitReturnType *instruction)
8314{8314{
8315 IrInstGen *value = instruction->value->child;8315 Stage1AirInst *value = instruction->value->child;
8316 if (type_is_invalid(value->value->type))8316 if (type_is_invalid(value->value->type))
8317 return ir_unreach_error(ira);8317 return ir_unreach_error(ira);
83188318
...@@ -8323,18 +8323,18 @@ static IrInstGen *ir_analyze_instruction_add_implicit_return_type(IrAnalyze *ira...@@ -8323,18 +8323,18 @@ static IrInstGen *ir_analyze_instruction_add_implicit_return_type(IrAnalyze *ira
8323 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);8323 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
8324}8324}
83258325
8326static IrInstGen *ir_analyze_instruction_return(IrAnalyze *ira, IrInstSrcReturn *instruction) {8326static Stage1AirInst *ir_analyze_instruction_return(IrAnalyze *ira, Stage1ZirInstReturn *instruction) {
8327 if (instruction->operand == nullptr) {8327 if (instruction->operand == nullptr) {
8328 // result location mechanism took care of it.8328 // result location mechanism took care of it.
8329 IrInstGen *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr);8329 Stage1AirInst *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr);
8330 return ir_finish_anal(ira, result);8330 return ir_finish_anal(ira, result);
8331 }8331 }
83328332
8333 IrInstGen *operand = instruction->operand->child;8333 Stage1AirInst *operand = instruction->operand->child;
8334 if (type_is_invalid(operand->value->type))8334 if (type_is_invalid(operand->value->type))
8335 return ir_unreach_error(ira);8335 return ir_unreach_error(ira);
83368336
8337 IrInstGen *casted_operand = ir_implicit_cast(ira, operand, ira->explicit_return_type);8337 Stage1AirInst *casted_operand = ir_implicit_cast(ira, operand, ira->explicit_return_type);
8338 if (type_is_invalid(casted_operand->value->type)) {8338 if (type_is_invalid(casted_operand->value->type)) {
8339 AstNode *source_node = ira->explicit_return_type_source_node;8339 AstNode *source_node = ira->explicit_return_type_source_node;
8340 if (source_node != nullptr) {8340 if (source_node != nullptr) {
...@@ -8349,7 +8349,7 @@ static IrInstGen *ir_analyze_instruction_return(IrAnalyze *ira, IrInstSrcReturn...@@ -8349,7 +8349,7 @@ static IrInstGen *ir_analyze_instruction_return(IrAnalyze *ira, IrInstSrcReturn
8349 handle_is_ptr(ira->codegen, ira->explicit_return_type))8349 handle_is_ptr(ira->codegen, ira->explicit_return_type))
8350 {8350 {
8351 // result location mechanism took care of it.8351 // result location mechanism took care of it.
8352 IrInstGen *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr);8352 Stage1AirInst *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr);
8353 return ir_finish_anal(ira, result);8353 return ir_finish_anal(ira, result);
8354 }8354 }
83558355
...@@ -8362,30 +8362,30 @@ static IrInstGen *ir_analyze_instruction_return(IrAnalyze *ira, IrInstSrcReturn...@@ -8362,30 +8362,30 @@ static IrInstGen *ir_analyze_instruction_return(IrAnalyze *ira, IrInstSrcReturn
8362 return ir_unreach_error(ira);8362 return ir_unreach_error(ira);
8363 }8363 }
83648364
8365 IrInstGen *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, casted_operand);8365 Stage1AirInst *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, casted_operand);
8366 return ir_finish_anal(ira, result);8366 return ir_finish_anal(ira, result);
8367}8367}
83688368
8369static IrInstGen *ir_analyze_instruction_const(IrAnalyze *ira, IrInstSrcConst *instruction) {8369static Stage1AirInst *ir_analyze_instruction_const(IrAnalyze *ira, Stage1ZirInstConst *instruction) {
8370 return ir_const_move(ira, instruction->base.scope, instruction->base.source_node, instruction->value);8370 return ir_const_move(ira, instruction->base.scope, instruction->base.source_node, instruction->value);
8371}8371}
83728372
8373static IrInstGen *ir_analyze_bin_op_bool(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) {8373static Stage1AirInst *ir_analyze_bin_op_bool(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) {
8374 IrInstGen *op1 = bin_op_instruction->op1->child;8374 Stage1AirInst *op1 = bin_op_instruction->op1->child;
8375 if (type_is_invalid(op1->value->type))8375 if (type_is_invalid(op1->value->type))
8376 return ira->codegen->invalid_inst_gen;8376 return ira->codegen->invalid_inst_gen;
83778377
8378 IrInstGen *op2 = bin_op_instruction->op2->child;8378 Stage1AirInst *op2 = bin_op_instruction->op2->child;
8379 if (type_is_invalid(op2->value->type))8379 if (type_is_invalid(op2->value->type))
8380 return ira->codegen->invalid_inst_gen;8380 return ira->codegen->invalid_inst_gen;
83818381
8382 ZigType *bool_type = ira->codegen->builtin_types.entry_bool;8382 ZigType *bool_type = ira->codegen->builtin_types.entry_bool;
83838383
8384 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, bool_type);8384 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, bool_type);
8385 if (type_is_invalid(casted_op1->value->type))8385 if (type_is_invalid(casted_op1->value->type))
8386 return ira->codegen->invalid_inst_gen;8386 return ira->codegen->invalid_inst_gen;
83878387
8388 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, bool_type);8388 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, bool_type);
8389 if (type_is_invalid(casted_op2->value->type))8389 if (type_is_invalid(casted_op2->value->type))
8390 return ira->codegen->invalid_inst_gen;8390 return ira->codegen->invalid_inst_gen;
83918391
...@@ -8465,7 +8465,7 @@ static void set_optional_payload(ZigValue *opt_val, ZigValue *payload) {...@@ -8465,7 +8465,7 @@ static void set_optional_payload(ZigValue *opt_val, ZigValue *payload) {
8465 }8465 }
8466}8466}
84678467
8468static IrInstGen *ir_evaluate_bin_op_cmp(IrAnalyze *ira, ZigType *resolved_type,8468static Stage1AirInst *ir_evaluate_bin_op_cmp(IrAnalyze *ira, ZigType *resolved_type,
8469 ZigValue *op1_val, ZigValue *op2_val, Scope *scope, AstNode *source_node, IrBinOp op_id,8469 ZigValue *op1_val, ZigValue *op2_val, Scope *scope, AstNode *source_node, IrBinOp op_id,
8470 bool one_possible_value)8470 bool one_possible_value)
8471{8471{
...@@ -8508,7 +8508,7 @@ static IrInstGen *ir_evaluate_bin_op_cmp(IrAnalyze *ira, ZigType *resolved_type,...@@ -8508,7 +8508,7 @@ static IrInstGen *ir_evaluate_bin_op_cmp(IrAnalyze *ira, ZigType *resolved_type,
8508 zig_unreachable();8508 zig_unreachable();
8509}8509}
85108510
8511static IrInstGen *ir_try_evaluate_bin_op_cmp_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *op1, IrInstGen *op2,8511static Stage1AirInst *ir_try_evaluate_bin_op_cmp_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *op1, Stage1AirInst *op2,
8512 ZigType *resolved_type, IrBinOp op_id)8512 ZigType *resolved_type, IrBinOp op_id)
8513{8513{
8514 assert(op1->value->type == resolved_type && op2->value->type == resolved_type);8514 assert(op1->value->type == resolved_type && op2->value->type == resolved_type);
...@@ -8533,14 +8533,14 @@ static IrInstGen *ir_try_evaluate_bin_op_cmp_const(IrAnalyze *ira, Scope *scope,...@@ -8533,14 +8533,14 @@ static IrInstGen *ir_try_evaluate_bin_op_cmp_const(IrAnalyze *ira, Scope *scope,
8533 return ira->codegen->invalid_inst_gen;8533 return ira->codegen->invalid_inst_gen;
8534 if (resolved_type->id != ZigTypeIdVector)8534 if (resolved_type->id != ZigTypeIdVector)
8535 return ir_evaluate_bin_op_cmp(ira, resolved_type, op1_val, op2_val, scope, source_node, op_id, one_possible_value);8535 return ir_evaluate_bin_op_cmp(ira, resolved_type, op1_val, op2_val, scope, source_node, op_id, one_possible_value);
8536 IrInstGen *result = ir_const(ira, scope, source_node,8536 Stage1AirInst *result = ir_const(ira, scope, source_node,
8537 get_vector_type(ira->codegen, resolved_type->data.vector.len, ira->codegen->builtin_types.entry_bool));8537 get_vector_type(ira->codegen, resolved_type->data.vector.len, ira->codegen->builtin_types.entry_bool));
8538 result->value->data.x_array.data.s_none.elements =8538 result->value->data.x_array.data.s_none.elements =
8539 ira->codegen->pass1_arena->allocate<ZigValue>(resolved_type->data.vector.len);8539 ira->codegen->pass1_arena->allocate<ZigValue>(resolved_type->data.vector.len);
85408540
8541 expand_undef_array(ira->codegen, result->value);8541 expand_undef_array(ira->codegen, result->value);
8542 for (size_t i = 0;i < resolved_type->data.vector.len;i++) {8542 for (size_t i = 0;i < resolved_type->data.vector.len;i++) {
8543 IrInstGen *cur_res = ir_evaluate_bin_op_cmp(ira, resolved_type->data.vector.elem_type,8543 Stage1AirInst *cur_res = ir_evaluate_bin_op_cmp(ira, resolved_type->data.vector.elem_type,
8544 &op1_val->data.x_array.data.s_none.elements[i],8544 &op1_val->data.x_array.data.s_none.elements[i],
8545 &op2_val->data.x_array.data.s_none.elements[i],8545 &op2_val->data.x_array.data.s_none.elements[i],
8546 scope, source_node, op_id, one_possible_value);8546 scope, source_node, op_id, one_possible_value);
...@@ -8708,14 +8708,14 @@ never_mind_just_calculate_it_normally:...@@ -8708,14 +8708,14 @@ never_mind_just_calculate_it_normally:
8708 return nullptr;8708 return nullptr;
8709 }8709 }
8710 if (op1_val->type->id == ZigTypeIdComptimeFloat) {8710 if (op1_val->type->id == ZigTypeIdComptimeFloat) {
8711 IrInstGen *tmp = ir_const_noval(ira, scope, source_node);8711 Stage1AirInst *tmp = ir_const_noval(ira, scope, source_node);
8712 tmp->value = op1_val;8712 tmp->value = op1_val;
8713 IrInstGen *casted = ir_implicit_cast(ira, tmp, op2_val->type);8713 Stage1AirInst *casted = ir_implicit_cast(ira, tmp, op2_val->type);
8714 op1_val = casted->value;8714 op1_val = casted->value;
8715 } else if (op2_val->type->id == ZigTypeIdComptimeFloat) {8715 } else if (op2_val->type->id == ZigTypeIdComptimeFloat) {
8716 IrInstGen *tmp = ir_const_noval(ira, scope, source_node);8716 Stage1AirInst *tmp = ir_const_noval(ira, scope, source_node);
8717 tmp->value = op2_val;8717 tmp->value = op2_val;
8718 IrInstGen *casted = ir_implicit_cast(ira, tmp, op1_val->type);8718 Stage1AirInst *casted = ir_implicit_cast(ira, tmp, op1_val->type);
8719 op2_val = casted->value;8719 op2_val = casted->value;
8720 }8720 }
8721 Cmp cmp_result = float_cmp(op1_val, op2_val);8721 Cmp cmp_result = float_cmp(op1_val, op2_val);
...@@ -8768,8 +8768,8 @@ never_mind_just_calculate_it_normally:...@@ -8768,8 +8768,8 @@ never_mind_just_calculate_it_normally:
8768 return nullptr;8768 return nullptr;
8769}8769}
87708770
8771static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, AstNode *source_node,8771static Stage1AirInst *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, AstNode *source_node,
8772 IrInstGen *op1, IrInstGen *op2, IrBinOp op_id)8772 Stage1AirInst *op1, Stage1AirInst *op2, IrBinOp op_id)
8773{8773{
8774 Error err;8774 Error err;
87758775
...@@ -8833,7 +8833,7 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As...@@ -8833,7 +8833,7 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As
8833 if (((opv_op1 || instr_is_comptime(op1)) && (opv_op2 || instr_is_comptime(op2))) ||8833 if (((opv_op1 || instr_is_comptime(op1)) && (opv_op2 || instr_is_comptime(op2))) ||
8834 (have_op1_cmp_zero && have_op2_cmp_zero))8834 (have_op1_cmp_zero && have_op2_cmp_zero))
8835 {8835 {
8836 IrInstGen *result_instruction = ir_const(ira, scope, source_node, result_type);8836 Stage1AirInst *result_instruction = ir_const(ira, scope, source_node, result_type);
8837 ZigValue *out_val = result_instruction->value;8837 ZigValue *out_val = result_instruction->value;
8838 if (result_type->id == ZigTypeIdVector) {8838 if (result_type->id == ZigTypeIdVector) {
8839 size_t len = result_type->data.vector.len;8839 size_t len = result_type->data.vector.len;
...@@ -8954,8 +8954,8 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As...@@ -8954,8 +8954,8 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As
8954 }8954 }
8955 ZigType *dest_type = (result_type->id == ZigTypeIdVector) ?8955 ZigType *dest_type = (result_type->id == ZigTypeIdVector) ?
8956 get_vector_type(ira->codegen, result_type->data.vector.len, dest_scalar_type) : dest_scalar_type;8956 get_vector_type(ira->codegen, result_type->data.vector.len, dest_scalar_type) : dest_scalar_type;
8957 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, dest_type);8957 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, dest_type);
8958 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, dest_type);8958 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, dest_type);
8959 if (type_is_invalid(casted_op1->value->type) || type_is_invalid(casted_op2->value->type))8959 if (type_is_invalid(casted_op1->value->type) || type_is_invalid(casted_op2->value->type))
8960 return ira->codegen->invalid_inst_gen;8960 return ira->codegen->invalid_inst_gen;
8961 return ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id, casted_op1, casted_op2, true);8961 return ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id, casted_op1, casted_op2, true);
...@@ -9071,10 +9071,10 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As...@@ -9071,10 +9071,10 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As
9071 ZigType *dest_type = (result_type->id == ZigTypeIdVector) ?9071 ZigType *dest_type = (result_type->id == ZigTypeIdVector) ?
9072 get_vector_type(ira->codegen, result_type->data.vector.len, dest_scalar_type) : dest_scalar_type;9072 get_vector_type(ira->codegen, result_type->data.vector.len, dest_scalar_type) : dest_scalar_type;
90739073
9074 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, dest_type);9074 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, dest_type);
9075 if (type_is_invalid(casted_op1->value->type))9075 if (type_is_invalid(casted_op1->value->type))
9076 return ira->codegen->invalid_inst_gen;9076 return ira->codegen->invalid_inst_gen;
9077 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, dest_type);9077 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, dest_type);
9078 if (type_is_invalid(casted_op2->value->type))9078 if (type_is_invalid(casted_op2->value->type))
9079 return ira->codegen->invalid_inst_gen;9079 return ira->codegen->invalid_inst_gen;
9080 return ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id, casted_op1, casted_op2, true);9080 return ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id, casted_op1, casted_op2, true);
...@@ -9128,8 +9128,8 @@ static bool type_is_self_comparable(ZigType *ty, bool is_equality_cmp) {...@@ -9128,8 +9128,8 @@ static bool type_is_self_comparable(ZigType *ty, bool is_equality_cmp) {
9128 zig_unreachable();9128 zig_unreachable();
9129}9129}
91309130
9131static IrInstGen *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type,9131static Stage1AirInst *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type,
9132 IrInstGen *optional, IrInstGen *non_optional, IrBinOp op_id)9132 Stage1AirInst *optional, Stage1AirInst *non_optional, IrBinOp op_id)
9133{9133{
9134 assert(optional->value->type->id == ZigTypeIdOptional);9134 assert(optional->value->type->id == ZigTypeIdOptional);
9135 assert(optional->value->type->data.maybe.child_type == non_optional->value->type);9135 assert(optional->value->type->data.maybe.child_type == non_optional->value->type);
...@@ -9148,12 +9148,12 @@ static IrInstGen *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira...@@ -9148,12 +9148,12 @@ static IrInstGen *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira
9148 }9148 }
91499149
9150 if (!optional_value_is_null(optional_val)) {9150 if (!optional_value_is_null(optional_val)) {
9151 IrInstGen *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false);9151 Stage1AirInst *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false);
9152 if (type_is_invalid(optional_unwrapped->value->type)) {9152 if (type_is_invalid(optional_unwrapped->value->type)) {
9153 return ira->codegen->invalid_inst_gen;9153 return ira->codegen->invalid_inst_gen;
9154 }9154 }
91559155
9156 IrInstGen *ret = ir_try_evaluate_bin_op_cmp_const(ira, scope, source_node, optional_unwrapped, non_optional, child_type, op_id);9156 Stage1AirInst *ret = ir_try_evaluate_bin_op_cmp_const(ira, scope, source_node, optional_unwrapped, non_optional, child_type, op_id);
9157 assert(ret != nullptr);9157 assert(ret != nullptr);
9158 return ret;9158 return ret;
9159 }9159 }
...@@ -9163,8 +9163,8 @@ static IrInstGen *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira...@@ -9163,8 +9163,8 @@ static IrInstGen *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira
9163 }9163 }
9164}9164}
91659165
9166static IrInstGen *ir_evaluate_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type,9166static Stage1AirInst *ir_evaluate_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type,
9167 IrInstGen *optional, IrInstGen *non_optional, IrBinOp op_id)9167 Stage1AirInst *optional, Stage1AirInst *non_optional, IrBinOp op_id)
9168{9168{
9169 assert(optional->value->type->id == ZigTypeIdOptional);9169 assert(optional->value->type->id == ZigTypeIdOptional);
9170 assert(optional->value->type->data.maybe.child_type == non_optional->value->type);9170 assert(optional->value->type->data.maybe.child_type == non_optional->value->type);
...@@ -9174,47 +9174,47 @@ static IrInstGen *ir_evaluate_cmp_optional_non_optional(IrAnalyze *ira, Scope *s...@@ -9174,47 +9174,47 @@ static IrInstGen *ir_evaluate_cmp_optional_non_optional(IrAnalyze *ira, Scope *s
9174 ZigType *result_type = ira->codegen->builtin_types.entry_bool;9174 ZigType *result_type = ira->codegen->builtin_types.entry_bool;
9175 ir_append_basic_block_gen(&ira->new_irb, ira->new_irb.current_basic_block);9175 ir_append_basic_block_gen(&ira->new_irb, ira->new_irb.current_basic_block);
91769176
9177 IrBasicBlockGen *null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNull");9177 Stage1AirBasicBlock *null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNull");
9178 IrBasicBlockGen *non_null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNotNull");9178 Stage1AirBasicBlock *non_null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNotNull");
9179 IrBasicBlockGen *end_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalEnd");9179 Stage1AirBasicBlock *end_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalEnd");
91809180
9181 IrInstGen *is_non_null = ir_build_test_non_null_gen(ira, scope, source_node, optional);9181 Stage1AirInst *is_non_null = ir_build_test_non_null_gen(ira, scope, source_node, optional);
9182 ir_build_cond_br_gen(ira, scope, source_node, is_non_null, non_null_block, null_block);9182 ir_build_cond_br_gen(ira, scope, source_node, is_non_null, non_null_block, null_block);
91839183
9184 ir_set_cursor_at_end_and_append_block_gen(&ira->new_irb, non_null_block);9184 ir_set_cursor_at_end_and_append_block_gen(&ira->new_irb, non_null_block);
9185 IrInstGen *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false);9185 Stage1AirInst *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false);
9186 if (type_is_invalid(optional_unwrapped->value->type)) {9186 if (type_is_invalid(optional_unwrapped->value->type)) {
9187 return ira->codegen->invalid_inst_gen;9187 return ira->codegen->invalid_inst_gen;
9188 }9188 }
9189 IrInstGen *non_null_cmp_result = ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id,9189 Stage1AirInst *non_null_cmp_result = ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id,
9190 optional_unwrapped, non_optional, false); // safety check unnecessary for comparison operators9190 optional_unwrapped, non_optional, false); // safety check unnecessary for comparison operators
9191 ir_build_br_gen(ira, scope, source_node, end_block);9191 ir_build_br_gen(ira, scope, source_node, end_block);
91929192
91939193
9194 ir_set_cursor_at_end_and_append_block_gen(&ira->new_irb, null_block);9194 ir_set_cursor_at_end_and_append_block_gen(&ira->new_irb, null_block);
9195 IrInstGen *null_result = ir_const_bool(ira, scope, source_node, (op_id != IrBinOpCmpEq));9195 Stage1AirInst *null_result = ir_const_bool(ira, scope, source_node, (op_id != IrBinOpCmpEq));
9196 ir_build_br_gen(ira, scope, source_node, end_block);9196 ir_build_br_gen(ira, scope, source_node, end_block);
91979197
9198 ir_set_cursor_at_end_gen(&ira->new_irb, end_block);9198 ir_set_cursor_at_end_gen(&ira->new_irb, end_block);
9199 int incoming_count = 2;9199 int incoming_count = 2;
9200 IrBasicBlockGen **incoming_blocks = heap::c_allocator.allocate_nonzero<IrBasicBlockGen *>(incoming_count);9200 Stage1AirBasicBlock **incoming_blocks = heap::c_allocator.allocate_nonzero<Stage1AirBasicBlock *>(incoming_count);
9201 incoming_blocks[0] = null_block;9201 incoming_blocks[0] = null_block;
9202 incoming_blocks[1] = non_null_block;9202 incoming_blocks[1] = non_null_block;
9203 IrInstGen **incoming_values = heap::c_allocator.allocate_nonzero<IrInstGen *>(incoming_count);9203 Stage1AirInst **incoming_values = heap::c_allocator.allocate_nonzero<Stage1AirInst *>(incoming_count);
9204 incoming_values[0] = null_result;9204 incoming_values[0] = null_result;
9205 incoming_values[1] = non_null_cmp_result;9205 incoming_values[1] = non_null_cmp_result;
92069206
9207 return ir_build_phi_gen(ira, scope, source_node, incoming_count, incoming_blocks, incoming_values, result_type);9207 return ir_build_phi_gen(ira, scope, source_node, incoming_count, incoming_blocks, incoming_values, result_type);
9208}9208}
92099209
9210static IrInstGen *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node,9210static Stage1AirInst *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node,
9211 IrInstGen *op1, IrInstGen *op2, IrInstGen *optional, IrBinOp op_id)9211 Stage1AirInst *op1, Stage1AirInst *op2, Stage1AirInst *optional, IrBinOp op_id)
9212{9212{
9213 assert(op_id == IrBinOpCmpEq || op_id == IrBinOpCmpNotEq);9213 assert(op_id == IrBinOpCmpEq || op_id == IrBinOpCmpNotEq);
9214 assert(optional->value->type->id == ZigTypeIdOptional);9214 assert(optional->value->type->id == ZigTypeIdOptional);
9215 assert(get_src_ptr_type(optional->value->type) == nullptr);9215 assert(get_src_ptr_type(optional->value->type) == nullptr);
92169216
9217 IrInstGen *non_optional;9217 Stage1AirInst *non_optional;
9218 if (op1 == optional) {9218 if (op1 == optional) {
9219 non_optional = op2;9219 non_optional = op2;
9220 } else if (op2 == optional) {9220 } else if (op2 == optional) {
...@@ -9253,7 +9253,7 @@ static IrInstGen *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *sc...@@ -9253,7 +9253,7 @@ static IrInstGen *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *sc
9253 return ira->codegen->invalid_inst_gen;9253 return ira->codegen->invalid_inst_gen;
9254 }9254 }
92559255
9256 if (IrInstGen *const_result = ir_try_evaluate_cmp_optional_non_optional_const(ira, scope, source_node, child_type,9256 if (Stage1AirInst *const_result = ir_try_evaluate_cmp_optional_non_optional_const(ira, scope, source_node, child_type,
9257 optional, non_optional, op_id))9257 optional, non_optional, op_id))
9258 {9258 {
9259 return const_result;9259 return const_result;
...@@ -9262,12 +9262,12 @@ static IrInstGen *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *sc...@@ -9262,12 +9262,12 @@ static IrInstGen *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *sc
9262 return ir_evaluate_cmp_optional_non_optional(ira, scope, source_node, child_type, optional, non_optional, op_id);9262 return ir_evaluate_cmp_optional_non_optional(ira, scope, source_node, child_type, optional, non_optional, op_id);
9263}9263}
92649264
9265static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) {9265static Stage1AirInst *ir_analyze_bin_op_cmp(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) {
9266 IrInstGen *op1 = bin_op_instruction->op1->child;9266 Stage1AirInst *op1 = bin_op_instruction->op1->child;
9267 if (type_is_invalid(op1->value->type))9267 if (type_is_invalid(op1->value->type))
9268 return ira->codegen->invalid_inst_gen;9268 return ira->codegen->invalid_inst_gen;
92699269
9270 IrInstGen *op2 = bin_op_instruction->op2->child;9270 Stage1AirInst *op2 = bin_op_instruction->op2->child;
9271 if (type_is_invalid(op2->value->type))9271 if (type_is_invalid(op2->value->type))
9272 return ira->codegen->invalid_inst_gen;9272 return ira->codegen->invalid_inst_gen;
92739273
...@@ -9282,7 +9282,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i...@@ -9282,7 +9282,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
9282 ((op1->value->type->id == ZigTypeIdNull && op2->value->type->id == ZigTypeIdOptional) ||9282 ((op1->value->type->id == ZigTypeIdNull && op2->value->type->id == ZigTypeIdOptional) ||
9283 (op2->value->type->id == ZigTypeIdNull && op1->value->type->id == ZigTypeIdOptional)))9283 (op2->value->type->id == ZigTypeIdNull && op1->value->type->id == ZigTypeIdOptional)))
9284 {9284 {
9285 IrInstGen *maybe_op;9285 Stage1AirInst *maybe_op;
9286 if (op1->value->type->id == ZigTypeIdNull) {9286 if (op1->value->type->id == ZigTypeIdNull) {
9287 maybe_op = op2;9287 maybe_op = op2;
9288 } else if (op2->value->type->id == ZigTypeIdNull) {9288 } else if (op2->value->type->id == ZigTypeIdNull) {
...@@ -9300,7 +9300,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i...@@ -9300,7 +9300,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
9300 bin_op_instruction->base.source_node, bool_result);9300 bin_op_instruction->base.source_node, bool_result);
9301 }9301 }
93029302
9303 IrInstGen *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope,9303 Stage1AirInst *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope,
9304 bin_op_instruction->base.source_node, maybe_op);9304 bin_op_instruction->base.source_node, maybe_op);
93059305
9306 if (op_id == IrBinOpCmpEq) {9306 if (op_id == IrBinOpCmpEq) {
...@@ -9315,7 +9315,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i...@@ -9315,7 +9315,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
9315 (op2->value->type->id == ZigTypeIdNull && op1->value->type->id == ZigTypeIdPointer &&9315 (op2->value->type->id == ZigTypeIdNull && op1->value->type->id == ZigTypeIdPointer &&
9316 op1->value->type->data.pointer.ptr_len == PtrLenC)))9316 op1->value->type->data.pointer.ptr_len == PtrLenC)))
9317 {9317 {
9318 IrInstGen *c_ptr_op;9318 Stage1AirInst *c_ptr_op;
9319 if (op1->value->type->id == ZigTypeIdNull) {9319 if (op1->value->type->id == ZigTypeIdNull) {
9320 c_ptr_op = op2;9320 c_ptr_op = op2;
9321 } else if (op2->value->type->id == ZigTypeIdNull) {9321 } else if (op2->value->type->id == ZigTypeIdNull) {
...@@ -9335,7 +9335,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i...@@ -9335,7 +9335,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
9335 bool bool_result = (op_id == IrBinOpCmpEq) ? is_null : !is_null;9335 bool bool_result = (op_id == IrBinOpCmpEq) ? is_null : !is_null;
9336 return ir_const_bool(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, bool_result);9336 return ir_const_bool(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, bool_result);
9337 }9337 }
9338 IrInstGen *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, c_ptr_op);9338 Stage1AirInst *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, c_ptr_op);
93399339
9340 if (op_id == IrBinOpCmpEq) {9340 if (op_id == IrBinOpCmpEq) {
9341 return ir_build_bool_not_gen(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, is_non_null);9341 return ir_build_bool_not_gen(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, is_non_null);
...@@ -9360,8 +9360,8 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i...@@ -9360,8 +9360,8 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
9360 (op2->value->type->id == ZigTypeIdEnumLiteral && op1->value->type->id == ZigTypeIdUnion)))9360 (op2->value->type->id == ZigTypeIdEnumLiteral && op1->value->type->id == ZigTypeIdUnion)))
9361 {9361 {
9362 // Support equality comparison between a union's tag value and a enum literal9362 // Support equality comparison between a union's tag value and a enum literal
9363 IrInstGen *union_val = op1->value->type->id == ZigTypeIdUnion ? op1 : op2;9363 Stage1AirInst *union_val = op1->value->type->id == ZigTypeIdUnion ? op1 : op2;
9364 IrInstGen *enum_val = op1->value->type->id == ZigTypeIdUnion ? op2 : op1;9364 Stage1AirInst *enum_val = op1->value->type->id == ZigTypeIdUnion ? op2 : op1;
93659365
9366 if (!is_tagged_union(union_val->value->type)) {9366 if (!is_tagged_union(union_val->value->type)) {
9367 ErrorMsg *msg = ir_add_error_node(ira, source_node,9367 ErrorMsg *msg = ir_add_error_node(ira, source_node,
...@@ -9375,11 +9375,11 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i...@@ -9375,11 +9375,11 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
9375 ZigType *tag_type = union_val->value->type->data.unionation.tag_type;9375 ZigType *tag_type = union_val->value->type->data.unionation.tag_type;
9376 assert(tag_type != nullptr);9376 assert(tag_type != nullptr);
93779377
9378 IrInstGen *casted_union = ir_implicit_cast(ira, union_val, tag_type);9378 Stage1AirInst *casted_union = ir_implicit_cast(ira, union_val, tag_type);
9379 if (type_is_invalid(casted_union->value->type))9379 if (type_is_invalid(casted_union->value->type))
9380 return ira->codegen->invalid_inst_gen;9380 return ira->codegen->invalid_inst_gen;
93819381
9382 IrInstGen *casted_val = ir_implicit_cast(ira, enum_val, tag_type);9382 Stage1AirInst *casted_val = ir_implicit_cast(ira, enum_val, tag_type);
9383 if (type_is_invalid(casted_val->value->type))9383 if (type_is_invalid(casted_val->value->type))
9384 return ira->codegen->invalid_inst_gen;9384 return ira->codegen->invalid_inst_gen;
93859385
...@@ -9486,7 +9486,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i...@@ -9486,7 +9486,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
9486 return ir_analyze_bin_op_cmp_numeric(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, op1, op2, op_id);9486 return ir_analyze_bin_op_cmp_numeric(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, op1, op2, op_id);
9487 }9487 }
94889488
9489 IrInstGen *instructions[] = {op1, op2};9489 Stage1AirInst *instructions[] = {op1, op2};
9490 ZigType *resolved_type = ir_resolve_peer_types(ira, source_node, nullptr, instructions, 2);9490 ZigType *resolved_type = ir_resolve_peer_types(ira, source_node, nullptr, instructions, 2);
9491 if (type_is_invalid(resolved_type))9491 if (type_is_invalid(resolved_type))
9492 return ira->codegen->invalid_inst_gen;9492 return ira->codegen->invalid_inst_gen;
...@@ -9499,15 +9499,15 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i...@@ -9499,15 +9499,15 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
9499 return ira->codegen->invalid_inst_gen;9499 return ira->codegen->invalid_inst_gen;
9500 }9500 }
95019501
9502 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, resolved_type);9502 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, resolved_type);
9503 if (type_is_invalid(casted_op1->value->type))9503 if (type_is_invalid(casted_op1->value->type))
9504 return ira->codegen->invalid_inst_gen;9504 return ira->codegen->invalid_inst_gen;
95059505
9506 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, resolved_type);9506 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, resolved_type);
9507 if (type_is_invalid(casted_op2->value->type))9507 if (type_is_invalid(casted_op2->value->type))
9508 return ira->codegen->invalid_inst_gen;9508 return ira->codegen->invalid_inst_gen;
95099509
9510 IrInstGen *resolve_const_result = ir_try_evaluate_bin_op_cmp_const(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, casted_op1,9510 Stage1AirInst *resolve_const_result = ir_try_evaluate_bin_op_cmp_const(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, casted_op1,
9511 casted_op2, resolved_type, op_id);9511 casted_op2, resolved_type, op_id);
9512 if (resolve_const_result != nullptr) {9512 if (resolve_const_result != nullptr) {
9513 return resolve_const_result;9513 return resolve_const_result;
...@@ -9700,10 +9700,10 @@ static ErrorMsg *ir_eval_math_op_scalar(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -9700,10 +9700,10 @@ static ErrorMsg *ir_eval_math_op_scalar(IrAnalyze *ira, Scope *scope, AstNode *s
9700}9700}
97019701
9702// This works on operands that have already been checked to be comptime known.9702// This works on operands that have already been checked to be comptime known.
9703static IrInstGen *ir_analyze_math_op(IrAnalyze *ira, Scope *scope, AstNode *source_node,9703static Stage1AirInst *ir_analyze_math_op(IrAnalyze *ira, Scope *scope, AstNode *source_node,
9704 ZigType *type_entry, ZigValue *op1_val, IrBinOp op_id, ZigValue *op2_val)9704 ZigType *type_entry, ZigValue *op1_val, IrBinOp op_id, ZigValue *op2_val)
9705{9705{
9706 IrInstGen *result_instruction = ir_const(ira, scope, source_node, type_entry);9706 Stage1AirInst *result_instruction = ir_const(ira, scope, source_node, type_entry);
9707 ZigValue *out_val = result_instruction->value;9707 ZigValue *out_val = result_instruction->value;
9708 if (type_entry->id == ZigTypeIdVector) {9708 if (type_entry->id == ZigTypeIdVector) {
9709 expand_undef_array(ira->codegen, op1_val);9709 expand_undef_array(ira->codegen, op1_val);
...@@ -9736,12 +9736,12 @@ static IrInstGen *ir_analyze_math_op(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -9736,12 +9736,12 @@ static IrInstGen *ir_analyze_math_op(IrAnalyze *ira, Scope *scope, AstNode *sour
9736 return ir_implicit_cast(ira, result_instruction, type_entry);9736 return ir_implicit_cast(ira, result_instruction, type_entry);
9737}9737}
97389738
9739static IrInstGen *ir_analyze_bit_shift(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) {9739static Stage1AirInst *ir_analyze_bit_shift(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) {
9740 IrInstGen *op1 = bin_op_instruction->op1->child;9740 Stage1AirInst *op1 = bin_op_instruction->op1->child;
9741 if (type_is_invalid(op1->value->type))9741 if (type_is_invalid(op1->value->type))
9742 return ira->codegen->invalid_inst_gen;9742 return ira->codegen->invalid_inst_gen;
97439743
9744 IrInstGen *op2 = bin_op_instruction->op2->child;9744 Stage1AirInst *op2 = bin_op_instruction->op2->child;
9745 if (type_is_invalid(op2->value->type))9745 if (type_is_invalid(op2->value->type))
9746 return ira->codegen->invalid_inst_gen;9746 return ira->codegen->invalid_inst_gen;
97479747
...@@ -9781,7 +9781,7 @@ static IrInstGen *ir_analyze_bit_shift(IrAnalyze *ira, IrInstSrcBinOp *bin_op_in...@@ -9781,7 +9781,7 @@ static IrInstGen *ir_analyze_bit_shift(IrAnalyze *ira, IrInstSrcBinOp *bin_op_in
9781 return ira->codegen->invalid_inst_gen;9781 return ira->codegen->invalid_inst_gen;
9782 }9782 }
97839783
9784 IrInstGen *casted_op2;9784 Stage1AirInst *casted_op2;
9785 IrBinOp op_id = bin_op_instruction->op_id;9785 IrBinOp op_id = bin_op_instruction->op_id;
9786 if (op1_scalar_type->id == ZigTypeIdComptimeInt) {9786 if (op1_scalar_type->id == ZigTypeIdComptimeInt) {
9787 // comptime_int has no finite bit width9787 // comptime_int has no finite bit width
...@@ -10005,14 +10005,14 @@ static bool value_cmp_numeric_val_all(ZigValue *left, Cmp predicate, ZigValue *r...@@ -10005,14 +10005,14 @@ static bool value_cmp_numeric_val_all(ZigValue *left, Cmp predicate, ZigValue *r
10005 return value_cmp_numeric_val(left, predicate, right, false);10005 return value_cmp_numeric_val(left, predicate, right, false);
10006}10006}
1000710007
10008static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruction) {10008static Stage1AirInst *ir_analyze_bin_op_math(IrAnalyze *ira, Stage1ZirInstBinOp *instruction) {
10009 Error err;10009 Error err;
1001010010
10011 IrInstGen *op1 = instruction->op1->child;10011 Stage1AirInst *op1 = instruction->op1->child;
10012 if (type_is_invalid(op1->value->type))10012 if (type_is_invalid(op1->value->type))
10013 return ira->codegen->invalid_inst_gen;10013 return ira->codegen->invalid_inst_gen;
1001410014
10015 IrInstGen *op2 = instruction->op2->child;10015 Stage1AirInst *op2 = instruction->op2->child;
10016 if (type_is_invalid(op2->value->type))10016 if (type_is_invalid(op2->value->type))
10017 return ira->codegen->invalid_inst_gen;10017 return ira->codegen->invalid_inst_gen;
1001810018
...@@ -10020,7 +10020,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc...@@ -10020,7 +10020,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
1002010020
10021 // look for pointer math10021 // look for pointer math
10022 if (is_pointer_arithmetic_allowed(op1->value->type, op_id)) {10022 if (is_pointer_arithmetic_allowed(op1->value->type, op_id)) {
10023 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, ira->codegen->builtin_types.entry_usize);10023 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, ira->codegen->builtin_types.entry_usize);
10024 if (type_is_invalid(casted_op2->value->type))10024 if (type_is_invalid(casted_op2->value->type))
10025 return ira->codegen->invalid_inst_gen;10025 return ira->codegen->invalid_inst_gen;
1002610026
...@@ -10095,7 +10095,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc...@@ -10095,7 +10095,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
10095 } else {10095 } else {
10096 zig_unreachable();10096 zig_unreachable();
10097 }10097 }
10098 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);10098 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
10099 result->value->data.x_ptr.special = ConstPtrSpecialHardCodedAddr;10099 result->value->data.x_ptr.special = ConstPtrSpecialHardCodedAddr;
10100 result->value->data.x_ptr.mut = ConstPtrMutRuntimeVar;10100 result->value->data.x_ptr.mut = ConstPtrMutRuntimeVar;
10101 result->value->data.x_ptr.data.hard_coded_addr.addr = new_addr;10101 result->value->data.x_ptr.data.hard_coded_addr.addr = new_addr;
...@@ -10105,7 +10105,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc...@@ -10105,7 +10105,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
10105 return ir_build_bin_op_gen(ira, instruction->base.scope, instruction->base.source_node, result_type, op_id, op1, casted_op2, true);10105 return ir_build_bin_op_gen(ira, instruction->base.scope, instruction->base.source_node, result_type, op_id, op1, casted_op2, true);
10106 }10106 }
1010710107
10108 IrInstGen *instructions[] = {op1, op2};10108 Stage1AirInst *instructions[] = {op1, op2};
10109 ZigType *resolved_type = ir_resolve_peer_types(ira, instruction->base.source_node, nullptr, instructions, 2);10109 ZigType *resolved_type = ir_resolve_peer_types(ira, instruction->base.source_node, nullptr, instructions, 2);
10110 if (type_is_invalid(resolved_type))10110 if (type_is_invalid(resolved_type))
10111 return ira->codegen->invalid_inst_gen;10111 return ira->codegen->invalid_inst_gen;
...@@ -10125,11 +10125,11 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc...@@ -10125,11 +10125,11 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
10125 return ira->codegen->invalid_inst_gen;10125 return ira->codegen->invalid_inst_gen;
10126 }10126 }
1012710127
10128 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, resolved_type);10128 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, resolved_type);
10129 if (type_is_invalid(casted_op1->value->type))10129 if (type_is_invalid(casted_op1->value->type))
10130 return ira->codegen->invalid_inst_gen;10130 return ira->codegen->invalid_inst_gen;
1013110131
10132 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, resolved_type);10132 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, resolved_type);
10133 if (type_is_invalid(casted_op2->value->type))10133 if (type_is_invalid(casted_op2->value->type))
10134 return ira->codegen->invalid_inst_gen;10134 return ira->codegen->invalid_inst_gen;
1013510135
...@@ -10170,17 +10170,17 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc...@@ -10170,17 +10170,17 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
10170 // division function ambiguity problem.10170 // division function ambiguity problem.
10171 ok = true;10171 ok = true;
10172 } else {10172 } else {
10173 IrInstGen *trunc_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,10173 Stage1AirInst *trunc_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
10174 op1_val, IrBinOpDivTrunc, op2_val);10174 op1_val, IrBinOpDivTrunc, op2_val);
10175 if (type_is_invalid(trunc_val->value->type))10175 if (type_is_invalid(trunc_val->value->type))
10176 return ira->codegen->invalid_inst_gen;10176 return ira->codegen->invalid_inst_gen;
1017710177
10178 IrInstGen *floor_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,10178 Stage1AirInst *floor_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
10179 op1_val, IrBinOpDivFloor, op2_val);10179 op1_val, IrBinOpDivFloor, op2_val);
10180 if (type_is_invalid(floor_val->value->type))10180 if (type_is_invalid(floor_val->value->type))
10181 return ira->codegen->invalid_inst_gen;10181 return ira->codegen->invalid_inst_gen;
1018210182
10183 IrInstGen *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node,10183 Stage1AirInst *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node,
10184 trunc_val, floor_val, IrBinOpCmpEq);10184 trunc_val, floor_val, IrBinOpCmpEq);
10185 if (type_is_invalid(cmp_val->value->type))10185 if (type_is_invalid(cmp_val->value->type))
10186 return ira->codegen->invalid_inst_gen;10186 return ira->codegen->invalid_inst_gen;
...@@ -10209,17 +10209,17 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc...@@ -10209,17 +10209,17 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
10209 // division function ambiguity problem.10209 // division function ambiguity problem.
10210 ok = true;10210 ok = true;
10211 } else {10211 } else {
10212 IrInstGen *rem_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,10212 Stage1AirInst *rem_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
10213 op1_val, IrBinOpRemRem, op2_val);10213 op1_val, IrBinOpRemRem, op2_val);
10214 if (type_is_invalid(rem_val->value->type))10214 if (type_is_invalid(rem_val->value->type))
10215 return ira->codegen->invalid_inst_gen;10215 return ira->codegen->invalid_inst_gen;
1021610216
10217 IrInstGen *mod_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,10217 Stage1AirInst *mod_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
10218 op1_val, IrBinOpRemMod, op2_val);10218 op1_val, IrBinOpRemMod, op2_val);
10219 if (type_is_invalid(mod_val->value->type))10219 if (type_is_invalid(mod_val->value->type))
10220 return ira->codegen->invalid_inst_gen;10220 return ira->codegen->invalid_inst_gen;
1022110221
10222 IrInstGen *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node,10222 Stage1AirInst *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node,
10223 rem_val, mod_val, IrBinOpCmpEq);10223 rem_val, mod_val, IrBinOpCmpEq);
10224 if (type_is_invalid(cmp_val->value->type))10224 if (type_is_invalid(cmp_val->value->type))
10225 return ira->codegen->invalid_inst_gen;10225 return ira->codegen->invalid_inst_gen;
...@@ -10273,8 +10273,8 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc...@@ -10273,8 +10273,8 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
10273 op_id, casted_op1, casted_op2, instruction->safety_check_on);10273 op_id, casted_op1, casted_op2, instruction->safety_check_on);
10274}10274}
1027510275
10276static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *source_node,10276static Stage1AirInst *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *source_node,
10277 IrInstGen *op1, IrInstGen *op2)10277 Stage1AirInst *op1, Stage1AirInst *op2)
10278{10278{
10279 Error err;10279 Error err;
10280 ZigType *op1_type = op1->value->type;10280 ZigType *op1_type = op1->value->type;
...@@ -10296,7 +10296,7 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -10296,7 +10296,7 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so
10296 new_type->data.structure.fields = realloc_type_struct_fields(new_type->data.structure.fields,10296 new_type->data.structure.fields = realloc_type_struct_fields(new_type->data.structure.fields,
10297 0, new_field_count);10297 0, new_field_count);
1029810298
10299 IrInstGen *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),10299 Stage1AirInst *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
10300 new_type, nullptr, false, true);10300 new_type, nullptr, false, true);
1030110301
10302 for (uint32_t i = 0; i < new_field_count; i += 1) {10302 for (uint32_t i = 0; i < new_field_count; i += 1) {
...@@ -10318,10 +10318,10 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -10318,10 +10318,10 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so
10318 if ((err = type_resolve(ira->codegen, new_type, ResolveStatusZeroBitsKnown)))10318 if ((err = type_resolve(ira->codegen, new_type, ResolveStatusZeroBitsKnown)))
10319 return ira->codegen->invalid_inst_gen;10319 return ira->codegen->invalid_inst_gen;
1032010320
10321 ZigList<IrInstGen *> const_ptrs = {};10321 ZigList<Stage1AirInst *> const_ptrs = {};
10322 for (uint32_t i = 0; i < new_field_count; i += 1) {10322 for (uint32_t i = 0; i < new_field_count; i += 1) {
10323 TypeStructField *dst_field = new_type->data.structure.fields[i];10323 TypeStructField *dst_field = new_type->data.structure.fields[i];
10324 IrInstGen *src_struct_op;10324 Stage1AirInst *src_struct_op;
10325 TypeStructField *src_field;10325 TypeStructField *src_field;
10326 if (i < op1_field_count) {10326 if (i < op1_field_count) {
10327 src_field = op1_type->data.structure.fields[i];10327 src_field = op1_type->data.structure.fields[i];
...@@ -10330,18 +10330,18 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -10330,18 +10330,18 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so
10330 src_field = op2_type->data.structure.fields[i - op1_field_count];10330 src_field = op2_type->data.structure.fields[i - op1_field_count];
10331 src_struct_op = op2;10331 src_struct_op = op2;
10332 }10332 }
10333 IrInstGen *field_value = ir_analyze_struct_value_field_value(ira, scope, source_node,10333 Stage1AirInst *field_value = ir_analyze_struct_value_field_value(ira, scope, source_node,
10334 src_struct_op, src_field);10334 src_struct_op, src_field);
10335 if (type_is_invalid(field_value->value->type))10335 if (type_is_invalid(field_value->value->type))
10336 return ira->codegen->invalid_inst_gen;10336 return ira->codegen->invalid_inst_gen;
10337 IrInstGen *dest_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, dst_field,10337 Stage1AirInst *dest_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, dst_field,
10338 new_struct_ptr, new_type, true);10338 new_struct_ptr, new_type, true);
10339 if (type_is_invalid(dest_ptr->value->type))10339 if (type_is_invalid(dest_ptr->value->type))
10340 return ira->codegen->invalid_inst_gen;10340 return ira->codegen->invalid_inst_gen;
10341 if (instr_is_comptime(field_value)) {10341 if (instr_is_comptime(field_value)) {
10342 const_ptrs.append(dest_ptr);10342 const_ptrs.append(dest_ptr);
10343 }10343 }
10344 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, dest_ptr, field_value,10344 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, dest_ptr, field_value,
10345 true);10345 true);
10346 if (type_is_invalid(store_ptr_inst->value->type))10346 if (type_is_invalid(store_ptr_inst->value->type))
10347 return ira->codegen->invalid_inst_gen;10347 return ira->codegen->invalid_inst_gen;
...@@ -10349,13 +10349,13 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -10349,13 +10349,13 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so
10349 if (const_ptrs.length != new_field_count) {10349 if (const_ptrs.length != new_field_count) {
10350 new_struct_ptr->value->special = ConstValSpecialRuntime;10350 new_struct_ptr->value->special = ConstValSpecialRuntime;
10351 for (size_t i = 0; i < const_ptrs.length; i += 1) {10351 for (size_t i = 0; i < const_ptrs.length; i += 1) {
10352 IrInstGen *elem_result_loc = const_ptrs.at(i);10352 Stage1AirInst *elem_result_loc = const_ptrs.at(i);
10353 assert(elem_result_loc->value->special == ConstValSpecialStatic);10353 assert(elem_result_loc->value->special == ConstValSpecialStatic);
10354 if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) {10354 if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) {
10355 // This field will be generated comptime; no need to do this.10355 // This field will be generated comptime; no need to do this.
10356 continue;10356 continue;
10357 }10357 }
10358 IrInstGen *deref = ir_get_deref(ira, elem_result_loc->scope,10358 Stage1AirInst *deref = ir_get_deref(ira, elem_result_loc->scope,
10359 elem_result_loc->source_node, elem_result_loc, nullptr);10359 elem_result_loc->source_node, elem_result_loc, nullptr);
10360 if (!type_requires_comptime(ira->codegen, elem_result_loc->value->type->data.pointer.child_type)) {10360 if (!type_requires_comptime(ira->codegen, elem_result_loc->value->type->data.pointer.child_type)) {
10361 elem_result_loc->value->special = ConstValSpecialRuntime;10361 elem_result_loc->value->special = ConstValSpecialRuntime;
...@@ -10369,13 +10369,13 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -10369,13 +10369,13 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so
10369 return ir_get_deref(ira, scope, source_node, new_struct_ptr, nullptr);10369 return ir_get_deref(ira, scope, source_node, new_struct_ptr, nullptr);
10370}10370}
1037110371
10372static IrInstGen *ir_analyze_array_cat(IrAnalyze *ira, IrInstSrcBinOp *instruction) {10372static Stage1AirInst *ir_analyze_array_cat(IrAnalyze *ira, Stage1ZirInstBinOp *instruction) {
10373 IrInstGen *op1 = instruction->op1->child;10373 Stage1AirInst *op1 = instruction->op1->child;
10374 ZigType *op1_type = op1->value->type;10374 ZigType *op1_type = op1->value->type;
10375 if (type_is_invalid(op1_type))10375 if (type_is_invalid(op1_type))
10376 return ira->codegen->invalid_inst_gen;10376 return ira->codegen->invalid_inst_gen;
1037710377
10378 IrInstGen *op2 = instruction->op2->child;10378 Stage1AirInst *op2 = instruction->op2->child;
10379 ZigType *op2_type = op2->value->type;10379 ZigType *op2_type = op2->value->type;
10380 if (type_is_invalid(op2_type))10380 if (type_is_invalid(op2_type))
10381 return ira->codegen->invalid_inst_gen;10381 return ira->codegen->invalid_inst_gen;
...@@ -10510,7 +10510,7 @@ static IrInstGen *ir_analyze_array_cat(IrAnalyze *ira, IrInstSrcBinOp *instructi...@@ -10510,7 +10510,7 @@ static IrInstGen *ir_analyze_array_cat(IrAnalyze *ira, IrInstSrcBinOp *instructi
10510 }10510 }
1051110511
10512 // The type of result is populated in the following if blocks10512 // The type of result is populated in the following if blocks
10513 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);10513 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
10514 ZigValue *out_val = result->value;10514 ZigValue *out_val = result->value;
1051510515
10516 ZigValue *out_array_val;10516 ZigValue *out_array_val;
...@@ -10598,8 +10598,8 @@ static IrInstGen *ir_analyze_array_cat(IrAnalyze *ira, IrInstSrcBinOp *instructi...@@ -10598,8 +10598,8 @@ static IrInstGen *ir_analyze_array_cat(IrAnalyze *ira, IrInstSrcBinOp *instructi
10598 return result;10598 return result;
10599}10599}
1060010600
10601static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *source_node,10601static Stage1AirInst *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *source_node,
10602 IrInstGen *op1, IrInstGen *op2)10602 Stage1AirInst *op1, Stage1AirInst *op2)
10603{10603{
10604 Error err;10604 Error err;
10605 ZigType *op1_type = op1->value->type;10605 ZigType *op1_type = op1->value->type;
...@@ -10626,7 +10626,7 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -10626,7 +10626,7 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s
10626 new_type->data.structure.fields = realloc_type_struct_fields(10626 new_type->data.structure.fields = realloc_type_struct_fields(
10627 new_type->data.structure.fields, 0, new_field_count);10627 new_type->data.structure.fields, 0, new_field_count);
1062810628
10629 IrInstGen *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),10629 Stage1AirInst *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
10630 new_type, nullptr, false, true);10630 new_type, nullptr, false, true);
1063110631
10632 for (uint64_t i = 0; i < new_field_count; i += 1) {10632 for (uint64_t i = 0; i < new_field_count; i += 1) {
...@@ -10645,17 +10645,17 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -10645,17 +10645,17 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s
10645 if ((err = type_resolve(ira->codegen, new_type, ResolveStatusZeroBitsKnown)))10645 if ((err = type_resolve(ira->codegen, new_type, ResolveStatusZeroBitsKnown)))
10646 return ira->codegen->invalid_inst_gen;10646 return ira->codegen->invalid_inst_gen;
1064710647
10648 ZigList<IrInstGen *> const_ptrs = {};10648 ZigList<Stage1AirInst *> const_ptrs = {};
10649 for (uint64_t i = 0; i < new_field_count; i += 1) {10649 for (uint64_t i = 0; i < new_field_count; i += 1) {
10650 TypeStructField *src_field = op1_type->data.structure.fields[i % op1_field_count];10650 TypeStructField *src_field = op1_type->data.structure.fields[i % op1_field_count];
10651 TypeStructField *dst_field = new_type->data.structure.fields[i];10651 TypeStructField *dst_field = new_type->data.structure.fields[i];
1065210652
10653 IrInstGen *field_value = ir_analyze_struct_value_field_value(10653 Stage1AirInst *field_value = ir_analyze_struct_value_field_value(
10654 ira, scope, source_node, op1, src_field);10654 ira, scope, source_node, op1, src_field);
10655 if (type_is_invalid(field_value->value->type))10655 if (type_is_invalid(field_value->value->type))
10656 return ira->codegen->invalid_inst_gen;10656 return ira->codegen->invalid_inst_gen;
1065710657
10658 IrInstGen *dest_ptr = ir_analyze_struct_field_ptr(10658 Stage1AirInst *dest_ptr = ir_analyze_struct_field_ptr(
10659 ira, scope, source_node, dst_field, new_struct_ptr, new_type, true);10659 ira, scope, source_node, dst_field, new_struct_ptr, new_type, true);
10660 if (type_is_invalid(dest_ptr->value->type))10660 if (type_is_invalid(dest_ptr->value->type))
10661 return ira->codegen->invalid_inst_gen;10661 return ira->codegen->invalid_inst_gen;
...@@ -10664,7 +10664,7 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -10664,7 +10664,7 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s
10664 const_ptrs.append(dest_ptr);10664 const_ptrs.append(dest_ptr);
10665 }10665 }
1066610666
10667 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(10667 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(
10668 ira, scope, source_node, dest_ptr, field_value, true);10668 ira, scope, source_node, dest_ptr, field_value, true);
10669 if (type_is_invalid(store_ptr_inst->value->type))10669 if (type_is_invalid(store_ptr_inst->value->type))
10670 return ira->codegen->invalid_inst_gen;10670 return ira->codegen->invalid_inst_gen;
...@@ -10673,18 +10673,18 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -10673,18 +10673,18 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s
10673 if (const_ptrs.length != new_field_count) {10673 if (const_ptrs.length != new_field_count) {
10674 new_struct_ptr->value->special = ConstValSpecialRuntime;10674 new_struct_ptr->value->special = ConstValSpecialRuntime;
10675 for (size_t i = 0; i < const_ptrs.length; i += 1) {10675 for (size_t i = 0; i < const_ptrs.length; i += 1) {
10676 IrInstGen *elem_result_loc = const_ptrs.at(i);10676 Stage1AirInst *elem_result_loc = const_ptrs.at(i);
10677 assert(elem_result_loc->value->special == ConstValSpecialStatic);10677 assert(elem_result_loc->value->special == ConstValSpecialStatic);
10678 if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) {10678 if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) {
10679 // This field will be generated comptime; no need to do this.10679 // This field will be generated comptime; no need to do this.
10680 continue;10680 continue;
10681 }10681 }
10682 IrInstGen *deref = ir_get_deref(ira, elem_result_loc->scope,10682 Stage1AirInst *deref = ir_get_deref(ira, elem_result_loc->scope,
10683 elem_result_loc->source_node, elem_result_loc, nullptr);10683 elem_result_loc->source_node, elem_result_loc, nullptr);
10684 if (!type_requires_comptime(ira->codegen, elem_result_loc->value->type->data.pointer.child_type)) {10684 if (!type_requires_comptime(ira->codegen, elem_result_loc->value->type->data.pointer.child_type)) {
10685 elem_result_loc->value->special = ConstValSpecialRuntime;10685 elem_result_loc->value->special = ConstValSpecialRuntime;
10686 }10686 }
10687 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, elem_result_loc->scope,10687 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, elem_result_loc->scope,
10688 elem_result_loc->source_node, elem_result_loc, deref, true);10688 elem_result_loc->source_node, elem_result_loc, deref, true);
10689 if (type_is_invalid(store_ptr_inst->value->type))10689 if (type_is_invalid(store_ptr_inst->value->type))
10690 return ira->codegen->invalid_inst_gen;10690 return ira->codegen->invalid_inst_gen;
...@@ -10696,12 +10696,12 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -10696,12 +10696,12 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s
10696 return ir_get_deref(ira, scope, source_node, new_struct_ptr, nullptr);10696 return ir_get_deref(ira, scope, source_node, new_struct_ptr, nullptr);
10697}10697}
1069810698
10699static IrInstGen *ir_analyze_array_mult(IrAnalyze *ira, IrInstSrcBinOp *instruction) {10699static Stage1AirInst *ir_analyze_array_mult(IrAnalyze *ira, Stage1ZirInstBinOp *instruction) {
10700 IrInstGen *op1 = instruction->op1->child;10700 Stage1AirInst *op1 = instruction->op1->child;
10701 if (type_is_invalid(op1->value->type))10701 if (type_is_invalid(op1->value->type))
10702 return ira->codegen->invalid_inst_gen;10702 return ira->codegen->invalid_inst_gen;
1070310703
10704 IrInstGen *op2 = instruction->op2->child;10704 Stage1AirInst *op2 = instruction->op2->child;
10705 if (type_is_invalid(op2->value->type))10705 if (type_is_invalid(op2->value->type))
10706 return ira->codegen->invalid_inst_gen;10706 return ira->codegen->invalid_inst_gen;
1070710707
...@@ -10718,7 +10718,7 @@ static IrInstGen *ir_analyze_array_mult(IrAnalyze *ira, IrInstSrcBinOp *instruct...@@ -10718,7 +10718,7 @@ static IrInstGen *ir_analyze_array_mult(IrAnalyze *ira, IrInstSrcBinOp *instruct
10718 op1->value->type->data.pointer.child_type->id == ZigTypeIdArray)10718 op1->value->type->data.pointer.child_type->id == ZigTypeIdArray)
10719 {10719 {
10720 array_type = op1->value->type->data.pointer.child_type;10720 array_type = op1->value->type->data.pointer.child_type;
10721 IrInstGen *array_inst = ir_get_deref(ira, op1->scope, op1->source_node, op1, nullptr);10721 Stage1AirInst *array_inst = ir_get_deref(ira, op1->scope, op1->source_node, op1, nullptr);
10722 if (type_is_invalid(array_inst->value->type))10722 if (type_is_invalid(array_inst->value->type))
10723 return ira->codegen->invalid_inst_gen;10723 return ira->codegen->invalid_inst_gen;
10724 array_val = ir_resolve_const(ira, array_inst, UndefOk);10724 array_val = ir_resolve_const(ira, array_inst, UndefOk);
...@@ -10748,7 +10748,7 @@ static IrInstGen *ir_analyze_array_mult(IrAnalyze *ira, IrInstSrcBinOp *instruct...@@ -10748,7 +10748,7 @@ static IrInstGen *ir_analyze_array_mult(IrAnalyze *ira, IrInstSrcBinOp *instruct
10748 ZigType *result_array_type = get_array_type(ira->codegen, child_type, new_array_len,10748 ZigType *result_array_type = get_array_type(ira->codegen, child_type, new_array_len,
10749 array_type->data.array.sentinel);10749 array_type->data.array.sentinel);
1075010750
10751 IrInstGen *array_result;10751 Stage1AirInst *array_result;
10752 if (array_val->special == ConstValSpecialUndef || array_val->data.x_array.special == ConstArraySpecialUndef) {10752 if (array_val->special == ConstValSpecialUndef || array_val->data.x_array.special == ConstArraySpecialUndef) {
10753 array_result = ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, result_array_type);10753 array_result = ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, result_array_type);
10754 } else {10754 } else {
...@@ -10799,8 +10799,8 @@ skip_computation:...@@ -10799,8 +10799,8 @@ skip_computation:
10799 }10799 }
10800}10800}
1080110801
10802static IrInstGen *ir_analyze_instruction_merge_err_sets(IrAnalyze *ira,10802static Stage1AirInst *ir_analyze_instruction_merge_err_sets(IrAnalyze *ira,
10803 IrInstSrcMergeErrSets *instruction)10803 Stage1ZirInstMergeErrSets *instruction)
10804{10804{
10805 ZigType *op1_type = ir_resolve_error_set_type(ira, instruction->base.source_node, instruction->op1->child);10805 ZigType *op1_type = ir_resolve_error_set_type(ira, instruction->base.source_node, instruction->op1->child);
10806 if (type_is_invalid(op1_type))10806 if (type_is_invalid(op1_type))
...@@ -10838,7 +10838,7 @@ static IrInstGen *ir_analyze_instruction_merge_err_sets(IrAnalyze *ira,...@@ -10838,7 +10838,7 @@ static IrInstGen *ir_analyze_instruction_merge_err_sets(IrAnalyze *ira,
10838}10838}
1083910839
1084010840
10841static IrInstGen *ir_analyze_instruction_bin_op(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) {10841static Stage1AirInst *ir_analyze_instruction_bin_op(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) {
10842 IrBinOp op_id = bin_op_instruction->op_id;10842 IrBinOp op_id = bin_op_instruction->op_id;
10843 switch (op_id) {10843 switch (op_id) {
10844 case IrBinOpInvalid:10844 case IrBinOpInvalid:
...@@ -10883,12 +10883,12 @@ static IrInstGen *ir_analyze_instruction_bin_op(IrAnalyze *ira, IrInstSrcBinOp *...@@ -10883,12 +10883,12 @@ static IrInstGen *ir_analyze_instruction_bin_op(IrAnalyze *ira, IrInstSrcBinOp *
10883 zig_unreachable();10883 zig_unreachable();
10884}10884}
1088510885
10886static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclVar *decl_var_instruction) {10886static Stage1AirInst *ir_analyze_instruction_decl_var(IrAnalyze *ira, Stage1ZirInstDeclVar *decl_var_instruction) {
10887 Error err;10887 Error err;
10888 ZigVar *var = decl_var_instruction->var;10888 ZigVar *var = decl_var_instruction->var;
1088910889
10890 ZigType *explicit_type = nullptr;10890 ZigType *explicit_type = nullptr;
10891 IrInstGen *var_type = nullptr;10891 Stage1AirInst *var_type = nullptr;
10892 if (decl_var_instruction->var_type != nullptr) {10892 if (decl_var_instruction->var_type != nullptr) {
10893 var_type = decl_var_instruction->var_type->child;10893 var_type = decl_var_instruction->var_type->child;
10894 ZigType *proposed_type = ir_resolve_type(ira, var_type);10894 ZigType *proposed_type = ir_resolve_type(ira, var_type);
...@@ -10905,7 +10905,7 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV...@@ -10905,7 +10905,7 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV
1090510905
10906 bool var_class_requires_const = false;10906 bool var_class_requires_const = false;
1090710907
10908 IrInstGen *var_ptr = decl_var_instruction->ptr->child;10908 Stage1AirInst *var_ptr = decl_var_instruction->ptr->child;
10909 // if this is null, a compiler error happened and did not initialize the variable.10909 // if this is null, a compiler error happened and did not initialize the variable.
10910 // if there are no compile errors there may be a missing ir_expr_wrap in pass1 IR generation.10910 // if there are no compile errors there may be a missing ir_expr_wrap in pass1 IR generation.
10911 if (var_ptr == nullptr || type_is_invalid(var_ptr->value->type)) {10911 if (var_ptr == nullptr || type_is_invalid(var_ptr->value->type)) {
...@@ -11022,7 +11022,7 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV...@@ -11022,7 +11022,7 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV
11022 // we need a runtime ptr but we have a comptime val.11022 // we need a runtime ptr but we have a comptime val.
11023 // since it's a comptime val there are no instructions for it.11023 // since it's a comptime val there are no instructions for it.
11024 // we memcpy the init value here11024 // we memcpy the init value here
11025 IrInstGen *deref = ir_get_deref(ira, var_ptr->scope, var_ptr->source_node, var_ptr, nullptr);11025 Stage1AirInst *deref = ir_get_deref(ira, var_ptr->scope, var_ptr->source_node, var_ptr, nullptr);
11026 if (type_is_invalid(deref->value->type)) {11026 if (type_is_invalid(deref->value->type)) {
11027 var->var_type = ira->codegen->builtin_types.entry_invalid;11027 var->var_type = ira->codegen->builtin_types.entry_invalid;
11028 return ira->codegen->invalid_inst_gen;11028 return ira->codegen->invalid_inst_gen;
...@@ -11051,12 +11051,12 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV...@@ -11051,12 +11051,12 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV
11051 return ir_build_var_decl_gen(ira, decl_var_instruction->base.scope, decl_var_instruction->base.source_node, var, var_ptr);11051 return ir_build_var_decl_gen(ira, decl_var_instruction->base.scope, decl_var_instruction->base.source_node, var, var_ptr);
11052}11052}
1105311053
11054static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport *instruction) {11054static Stage1AirInst *ir_analyze_instruction_export(IrAnalyze *ira, Stage1ZirInstExport *instruction) {
11055 IrInstGen *target = instruction->target->child;11055 Stage1AirInst *target = instruction->target->child;
11056 if (type_is_invalid(target->value->type))11056 if (type_is_invalid(target->value->type))
11057 return ira->codegen->invalid_inst_gen;11057 return ira->codegen->invalid_inst_gen;
1105811058
11059 IrInstGen *options = instruction->options->child;11059 Stage1AirInst *options = instruction->options->child;
11060 if (type_is_invalid(options->value->type))11060 if (type_is_invalid(options->value->type))
11061 return ira->codegen->invalid_inst_gen;11061 return ira->codegen->invalid_inst_gen;
1106211062
...@@ -11065,29 +11065,29 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport...@@ -11065,29 +11065,29 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport
1106511065
11066 TypeStructField *name_field = find_struct_type_field(options_type, buf_create_from_str("name"));11066 TypeStructField *name_field = find_struct_type_field(options_type, buf_create_from_str("name"));
11067 src_assert(name_field != nullptr, instruction->base.source_node);11067 src_assert(name_field != nullptr, instruction->base.source_node);
11068 IrInstGen *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field);11068 Stage1AirInst *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field);
11069 if (type_is_invalid(name_inst->value->type))11069 if (type_is_invalid(name_inst->value->type))
11070 return ira->codegen->invalid_inst_gen;11070 return ira->codegen->invalid_inst_gen;
1107111071
11072 TypeStructField *linkage_field = find_struct_type_field(options_type, buf_create_from_str("linkage"));11072 TypeStructField *linkage_field = find_struct_type_field(options_type, buf_create_from_str("linkage"));
11073 src_assert(linkage_field != nullptr, instruction->base.source_node);11073 src_assert(linkage_field != nullptr, instruction->base.source_node);
11074 IrInstGen *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field);11074 Stage1AirInst *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field);
11075 if (type_is_invalid(linkage_inst->value->type))11075 if (type_is_invalid(linkage_inst->value->type))
11076 return ira->codegen->invalid_inst_gen;11076 return ira->codegen->invalid_inst_gen;
1107711077
11078 TypeStructField *section_field = find_struct_type_field(options_type, buf_create_from_str("section"));11078 TypeStructField *section_field = find_struct_type_field(options_type, buf_create_from_str("section"));
11079 src_assert(section_field != nullptr, instruction->base.source_node);11079 src_assert(section_field != nullptr, instruction->base.source_node);
11080 IrInstGen *section_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, section_field);11080 Stage1AirInst *section_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, section_field);
11081 if (type_is_invalid(section_inst->value->type))11081 if (type_is_invalid(section_inst->value->type))
11082 return ira->codegen->invalid_inst_gen;11082 return ira->codegen->invalid_inst_gen;
1108311083
11084 // The `section` field is optional, we have to unwrap it first11084 // The `section` field is optional, we have to unwrap it first
11085 IrInstGen *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, section_inst);11085 Stage1AirInst *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, section_inst);
11086 bool is_non_null;11086 bool is_non_null;
11087 if (!ir_resolve_bool(ira, non_null_check, &is_non_null))11087 if (!ir_resolve_bool(ira, non_null_check, &is_non_null))
11088 return ira->codegen->invalid_inst_gen;11088 return ira->codegen->invalid_inst_gen;
1108911089
11090 IrInstGen *section_str_inst = nullptr;11090 Stage1AirInst *section_str_inst = nullptr;
11091 if (is_non_null) {11091 if (is_non_null) {
11092 section_str_inst = ir_analyze_optional_value_payload_value(ira, instruction->base.scope, instruction->base.source_node, section_inst, false);11092 section_str_inst = ir_analyze_optional_value_payload_value(ira, instruction->base.scope, instruction->base.source_node, section_inst, false);
11093 if (type_is_invalid(section_str_inst->value->type))11093 if (type_is_invalid(section_str_inst->value->type))
...@@ -11307,10 +11307,10 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport...@@ -11307,10 +11307,10 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport
11307 }11307 }
1130811308
11309 // TODO audit the various ways to use @export11309 // TODO audit the various ways to use @export
11310 if (want_var_export && target->id == IrInstGenIdLoadPtr) {11310 if (want_var_export && target->id == Stage1AirInstIdLoadPtr) {
11311 IrInstGenLoadPtr *load_ptr = reinterpret_cast<IrInstGenLoadPtr *>(target);11311 Stage1AirInstLoadPtr *load_ptr = reinterpret_cast<Stage1AirInstLoadPtr *>(target);
11312 if (load_ptr->ptr->id == IrInstGenIdVarPtr) {11312 if (load_ptr->ptr->id == Stage1AirInstIdVarPtr) {
11313 IrInstGenVarPtr *var_ptr = reinterpret_cast<IrInstGenVarPtr *>(load_ptr->ptr);11313 Stage1AirInstVarPtr *var_ptr = reinterpret_cast<Stage1AirInstVarPtr *>(load_ptr->ptr);
11314 ZigVar *var = var_ptr->var;11314 ZigVar *var = var_ptr->var;
11315 add_var_export(ira->codegen, var, buf_ptr(symbol_name), global_linkage_id);11315 add_var_export(ira->codegen, var, buf_ptr(symbol_name), global_linkage_id);
11316 var->section_name = section_name;11316 var->section_name = section_name;
...@@ -11322,12 +11322,12 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport...@@ -11322,12 +11322,12 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport
1132211322
11323static void add_link_lib_symbol(IrAnalyze *ira, Buf *lib_name, Buf *symbol_name, AstNode *source_node);11323static void add_link_lib_symbol(IrAnalyze *ira, Buf *lib_name, Buf *symbol_name, AstNode *source_node);
1132411324
11325static IrInstGen *ir_analyze_instruction_extern(IrAnalyze *ira, IrInstSrcExtern *instruction) {11325static Stage1AirInst *ir_analyze_instruction_extern(IrAnalyze *ira, Stage1ZirInstExtern *instruction) {
11326 IrInstGen *type_inst = instruction->type->child;11326 Stage1AirInst *type_inst = instruction->type->child;
11327 if (type_is_invalid(type_inst->value->type))11327 if (type_is_invalid(type_inst->value->type))
11328 return ira->codegen->invalid_inst_gen;11328 return ira->codegen->invalid_inst_gen;
1132911329
11330 IrInstGen *options = instruction->options->child;11330 Stage1AirInst *options = instruction->options->child;
11331 if (type_is_invalid(options->value->type))11331 if (type_is_invalid(options->value->type))
11332 return ira->codegen->invalid_inst_gen;11332 return ira->codegen->invalid_inst_gen;
1133311333
...@@ -11336,35 +11336,35 @@ static IrInstGen *ir_analyze_instruction_extern(IrAnalyze *ira, IrInstSrcExtern...@@ -11336,35 +11336,35 @@ static IrInstGen *ir_analyze_instruction_extern(IrAnalyze *ira, IrInstSrcExtern
1133611336
11337 TypeStructField *name_field = find_struct_type_field(options_type, buf_create_from_str("name"));11337 TypeStructField *name_field = find_struct_type_field(options_type, buf_create_from_str("name"));
11338 src_assert(name_field != nullptr, instruction->base.source_node);11338 src_assert(name_field != nullptr, instruction->base.source_node);
11339 IrInstGen *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field);11339 Stage1AirInst *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field);
11340 if (type_is_invalid(name_inst->value->type))11340 if (type_is_invalid(name_inst->value->type))
11341 return ira->codegen->invalid_inst_gen;11341 return ira->codegen->invalid_inst_gen;
1134211342
11343 TypeStructField *linkage_field = find_struct_type_field(options_type, buf_create_from_str("linkage"));11343 TypeStructField *linkage_field = find_struct_type_field(options_type, buf_create_from_str("linkage"));
11344 src_assert(linkage_field != nullptr, instruction->base.source_node);11344 src_assert(linkage_field != nullptr, instruction->base.source_node);
11345 IrInstGen *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field);11345 Stage1AirInst *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field);
11346 if (type_is_invalid(linkage_inst->value->type))11346 if (type_is_invalid(linkage_inst->value->type))
11347 return ira->codegen->invalid_inst_gen;11347 return ira->codegen->invalid_inst_gen;
1134811348
11349 TypeStructField *is_thread_local_field = find_struct_type_field(options_type, buf_create_from_str("is_thread_local"));11349 TypeStructField *is_thread_local_field = find_struct_type_field(options_type, buf_create_from_str("is_thread_local"));
11350 src_assert(is_thread_local_field != nullptr, instruction->base.source_node);11350 src_assert(is_thread_local_field != nullptr, instruction->base.source_node);
11351 IrInstGen *is_thread_local_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, is_thread_local_field);11351 Stage1AirInst *is_thread_local_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, is_thread_local_field);
11352 if (type_is_invalid(is_thread_local_inst->value->type))11352 if (type_is_invalid(is_thread_local_inst->value->type))
11353 return ira->codegen->invalid_inst_gen;11353 return ira->codegen->invalid_inst_gen;
1135411354
11355 TypeStructField *library_name_field = find_struct_type_field(options_type, buf_create_from_str("library_name"));11355 TypeStructField *library_name_field = find_struct_type_field(options_type, buf_create_from_str("library_name"));
11356 src_assert(library_name_field != nullptr, instruction->base.source_node);11356 src_assert(library_name_field != nullptr, instruction->base.source_node);
11357 IrInstGen *library_name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, library_name_field);11357 Stage1AirInst *library_name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, library_name_field);
11358 if (type_is_invalid(library_name_inst->value->type))11358 if (type_is_invalid(library_name_inst->value->type))
11359 return ira->codegen->invalid_inst_gen;11359 return ira->codegen->invalid_inst_gen;
1136011360
11361 // The `library_name` field is optional, we have to unwrap it first11361 // The `library_name` field is optional, we have to unwrap it first
11362 IrInstGen *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, library_name_inst);11362 Stage1AirInst *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, library_name_inst);
11363 bool is_non_null;11363 bool is_non_null;
11364 if (!ir_resolve_bool(ira, non_null_check, &is_non_null))11364 if (!ir_resolve_bool(ira, non_null_check, &is_non_null))
11365 return ira->codegen->invalid_inst_gen;11365 return ira->codegen->invalid_inst_gen;
1136611366
11367 IrInstGen *library_name_val_inst = nullptr;11367 Stage1AirInst *library_name_val_inst = nullptr;
11368 if (is_non_null) {11368 if (is_non_null) {
11369 library_name_val_inst = ir_analyze_optional_value_payload_value(ira, instruction->base.scope, instruction->base.source_node, library_name_inst, false);11369 library_name_val_inst = ir_analyze_optional_value_payload_value(ira, instruction->base.scope, instruction->base.source_node, library_name_inst, false);
11370 if (type_is_invalid(library_name_val_inst->value->type))11370 if (type_is_invalid(library_name_val_inst->value->type))
...@@ -11445,14 +11445,14 @@ static bool ira_has_err_ret_trace(IrAnalyze *ira) {...@@ -11445,14 +11445,14 @@ static bool ira_has_err_ret_trace(IrAnalyze *ira) {
11445 return fn != nullptr && fn->calls_or_awaits_errorable_fn && ira->codegen->have_err_ret_tracing;11445 return fn != nullptr && fn->calls_or_awaits_errorable_fn && ira->codegen->have_err_ret_tracing;
11446}11446}
1144711447
11448static IrInstGen *ir_analyze_instruction_error_return_trace(IrAnalyze *ira,11448static Stage1AirInst *ir_analyze_instruction_error_return_trace(IrAnalyze *ira,
11449 IrInstSrcErrorReturnTrace *instruction)11449 Stage1ZirInstErrorReturnTrace *instruction)
11450{11450{
11451 ZigType *ptr_to_stack_trace_type = get_pointer_to_type(ira->codegen, get_stack_trace_type(ira->codegen), false);11451 ZigType *ptr_to_stack_trace_type = get_pointer_to_type(ira->codegen, get_stack_trace_type(ira->codegen), false);
11452 if (instruction->optional == IrInstErrorReturnTraceNull) {11452 if (instruction->optional == IrInstErrorReturnTraceNull) {
11453 ZigType *optional_type = get_optional_type(ira->codegen, ptr_to_stack_trace_type);11453 ZigType *optional_type = get_optional_type(ira->codegen, ptr_to_stack_trace_type);
11454 if (!ira_has_err_ret_trace(ira)) {11454 if (!ira_has_err_ret_trace(ira)) {
11455 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, optional_type);11455 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, optional_type);
11456 ZigValue *out_val = result->value;11456 ZigValue *out_val = result->value;
11457 assert(get_src_ptr_type(optional_type) != nullptr);11457 assert(get_src_ptr_type(optional_type) != nullptr);
11458 out_val->data.x_ptr.special = ConstPtrSpecialHardCodedAddr;11458 out_val->data.x_ptr.special = ConstPtrSpecialHardCodedAddr;
...@@ -11468,8 +11468,8 @@ static IrInstGen *ir_analyze_instruction_error_return_trace(IrAnalyze *ira,...@@ -11468,8 +11468,8 @@ static IrInstGen *ir_analyze_instruction_error_return_trace(IrAnalyze *ira,
11468 }11468 }
11469}11469}
1147011470
11471static IrInstGen *ir_analyze_instruction_error_union(IrAnalyze *ira, IrInstSrcErrorUnion *instruction) {11471static Stage1AirInst *ir_analyze_instruction_error_union(IrAnalyze *ira, Stage1ZirInstErrorUnion *instruction) {
11472 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);11472 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
11473 result->value->special = ConstValSpecialLazy;11473 result->value->special = ConstValSpecialLazy;
1147411474
11475 LazyValueErrUnionType *lazy_err_union_type = heap::c_allocator.create<LazyValueErrUnionType>();11475 LazyValueErrUnionType *lazy_err_union_type = heap::c_allocator.create<LazyValueErrUnionType>();
...@@ -11488,7 +11488,7 @@ static IrInstGen *ir_analyze_instruction_error_union(IrAnalyze *ira, IrInstSrcEr...@@ -11488,7 +11488,7 @@ static IrInstGen *ir_analyze_instruction_error_union(IrAnalyze *ira, IrInstSrcEr
11488 return result;11488 return result;
11489}11489}
1149011490
11491static IrInstGen *ir_analyze_alloca(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *var_type,11491static Stage1AirInst *ir_analyze_alloca(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *var_type,
11492 uint32_t align, const char *name_hint, bool force_comptime)11492 uint32_t align, const char *name_hint, bool force_comptime)
11493{11493{
11494 Error err;11494 Error err;
...@@ -11497,7 +11497,7 @@ static IrInstGen *ir_analyze_alloca(IrAnalyze *ira, Scope *scope, AstNode *sourc...@@ -11497,7 +11497,7 @@ static IrInstGen *ir_analyze_alloca(IrAnalyze *ira, Scope *scope, AstNode *sourc
11497 pointee->special = ConstValSpecialUndef;11497 pointee->special = ConstValSpecialUndef;
11498 pointee->llvm_align = align;11498 pointee->llvm_align = align;
1149911499
11500 IrInstGenAlloca *result = ir_build_alloca_gen(ira, scope, source_node, align, name_hint);11500 Stage1AirInstAlloca *result = ir_build_alloca_gen(ira, scope, source_node, align, name_hint);
11501 result->base.value->special = ConstValSpecialStatic;11501 result->base.value->special = ConstValSpecialStatic;
11502 result->base.value->data.x_ptr.special = ConstPtrSpecialRef;11502 result->base.value->data.x_ptr.special = ConstPtrSpecialRef;
11503 result->base.value->data.x_ptr.mut = force_comptime ? ConstPtrMutComptimeVar : ConstPtrMutInfer;11503 result->base.value->data.x_ptr.mut = force_comptime ? ConstPtrMutComptimeVar : ConstPtrMutInfer;
...@@ -11572,7 +11572,7 @@ static bool type_can_bit_cast(ZigType *t) {...@@ -11572,7 +11572,7 @@ static bool type_can_bit_cast(ZigType *t) {
11572 }11572 }
11573}11573}
1157411574
11575static void set_up_result_loc_for_inferred_comptime(IrAnalyze *ira, IrInstGen *ptr) {11575static void set_up_result_loc_for_inferred_comptime(IrAnalyze *ira, Stage1AirInst *ptr) {
11576 ZigValue *undef_child = ira->codegen->pass1_arena->create<ZigValue>();11576 ZigValue *undef_child = ira->codegen->pass1_arena->create<ZigValue>();
11577 undef_child->type = ptr->value->type->data.pointer.child_type;11577 undef_child->type = ptr->value->type->data.pointer.child_type;
11578 undef_child->special = ConstValSpecialUndef;11578 undef_child->special = ConstValSpecialUndef;
...@@ -11611,12 +11611,12 @@ static Error ir_result_has_type(IrAnalyze *ira, ResultLoc *result_loc, bool *out...@@ -11611,12 +11611,12 @@ static Error ir_result_has_type(IrAnalyze *ira, ResultLoc *result_loc, bool *out
11611 zig_unreachable();11611 zig_unreachable();
11612}11612}
1161311613
11614static IrInstGen *ir_resolve_no_result_loc(IrAnalyze *ira, IrInstSrc *suspend_source_instr,11614static Stage1AirInst *ir_resolve_no_result_loc(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr,
11615 ResultLoc *result_loc, ZigType *value_type)11615 ResultLoc *result_loc, ZigType *value_type)
11616{11616{
11617 if (type_is_invalid(value_type))11617 if (type_is_invalid(value_type))
11618 return ira->codegen->invalid_inst_gen;11618 return ira->codegen->invalid_inst_gen;
11619 IrInstGenAlloca *alloca_gen = ir_build_alloca_gen(ira, suspend_source_instr->scope,11619 Stage1AirInstAlloca *alloca_gen = ir_build_alloca_gen(ira, suspend_source_instr->scope,
11620 suspend_source_instr->source_node, 0, "");11620 suspend_source_instr->source_node, 0, "");
11621 alloca_gen->base.value->type = get_pointer_to_type_extra(ira->codegen, value_type, false, false,11621 alloca_gen->base.value->type = get_pointer_to_type_extra(ira->codegen, value_type, false, false,
11622 PtrLenSingle, 0, 0, 0, false);11622 PtrLenSingle, 0, 0, 0, false);
...@@ -11632,9 +11632,9 @@ static IrInstGen *ir_resolve_no_result_loc(IrAnalyze *ira, IrInstSrc *suspend_so...@@ -11632,9 +11632,9 @@ static IrInstGen *ir_resolve_no_result_loc(IrAnalyze *ira, IrInstSrc *suspend_so
1163211632
11633static bool result_loc_is_discard(ResultLoc *result_loc_pass1) {11633static bool result_loc_is_discard(ResultLoc *result_loc_pass1) {
11634 if (result_loc_pass1->id == ResultLocIdInstruction &&11634 if (result_loc_pass1->id == ResultLocIdInstruction &&
11635 result_loc_pass1->source_instruction->id == IrInstSrcIdConst)11635 result_loc_pass1->source_instruction->id == Stage1ZirInstIdConst)
11636 {11636 {
11637 IrInstSrcConst *const_inst = reinterpret_cast<IrInstSrcConst *>(result_loc_pass1->source_instruction);11637 Stage1ZirInstConst *const_inst = reinterpret_cast<Stage1ZirInstConst *>(result_loc_pass1->source_instruction);
11638 if (value_is_comptime(const_inst->value) &&11638 if (value_is_comptime(const_inst->value) &&
11639 const_inst->value->type->id == ZigTypeIdPointer &&11639 const_inst->value->type->id == ZigTypeIdPointer &&
11640 const_inst->value->data.x_ptr.special == ConstPtrSpecialDiscard)11640 const_inst->value->data.x_ptr.special == ConstPtrSpecialDiscard)
...@@ -11646,8 +11646,8 @@ static bool result_loc_is_discard(ResultLoc *result_loc_pass1) {...@@ -11646,8 +11646,8 @@ static bool result_loc_is_discard(ResultLoc *result_loc_pass1) {
11646}11646}
1164711647
11648// when calling this function, at the callsite must check for result type noreturn and propagate it up11648// when calling this function, at the callsite must check for result type noreturn and propagate it up
11649static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_source_instr,11649static Stage1AirInst *ir_resolve_result_raw(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr,
11650 ResultLoc *result_loc, ZigType *value_type, IrInstGen *value, bool force_runtime,11650 ResultLoc *result_loc, ZigType *value_type, Stage1AirInst *value, bool force_runtime,
11651 bool allow_discard)11651 bool allow_discard)
11652{11652{
11653 Error err;11653 Error err;
...@@ -11672,8 +11672,8 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc...@@ -11672,8 +11672,8 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
11672 }11672 }
11673 case ResultLocIdVar: {11673 case ResultLocIdVar: {
11674 ResultLocVar *result_loc_var = reinterpret_cast<ResultLocVar *>(result_loc);11674 ResultLocVar *result_loc_var = reinterpret_cast<ResultLocVar *>(result_loc);
11675 assert(result_loc->source_instruction->id == IrInstSrcIdAlloca);11675 assert(result_loc->source_instruction->id == Stage1ZirInstIdAlloca);
11676 IrInstSrcAlloca *alloca_src = reinterpret_cast<IrInstSrcAlloca *>(result_loc->source_instruction);11676 Stage1ZirInstAlloca *alloca_src = reinterpret_cast<Stage1ZirInstAlloca *>(result_loc->source_instruction);
1167711677
11678 ZigVar *var = result_loc_var->var;11678 ZigVar *var = result_loc_var->var;
11679 if (var->var_type != nullptr && !ir_get_var_is_comptime(var)) {11679 if (var->var_type != nullptr && !ir_get_var_is_comptime(var)) {
...@@ -11702,7 +11702,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc...@@ -11702,7 +11702,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
11702 if (alloca_src->align != nullptr && !ir_resolve_align(ira, alloca_src->align->child, nullptr, &align)) {11702 if (alloca_src->align != nullptr && !ir_resolve_align(ira, alloca_src->align->child, nullptr, &align)) {
11703 return ira->codegen->invalid_inst_gen;11703 return ira->codegen->invalid_inst_gen;
11704 }11704 }
11705 IrInstGen *alloca_gen = ir_analyze_alloca(ira,11705 Stage1AirInst *alloca_gen = ir_analyze_alloca(ira,
11706 result_loc->source_instruction->scope,11706 result_loc->source_instruction->scope,
11707 result_loc->source_instruction->source_node, value_type,11707 result_loc->source_instruction->source_node, value_type,
11708 align, alloca_src->name_hint, force_comptime);11708 align, alloca_src->name_hint, force_comptime);
...@@ -11739,7 +11739,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc...@@ -11739,7 +11739,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
11739 ResultLocPeerParent *peer_parent = result_peer->parent;11739 ResultLocPeerParent *peer_parent = result_peer->parent;
1174011740
11741 if (peer_parent->peers.length == 1) {11741 if (peer_parent->peers.length == 1) {
11742 IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,11742 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,
11743 value_type, value, force_runtime, true);11743 value_type, value, force_runtime, true);
11744 result_peer->suspend_pos.basic_block_index = SIZE_MAX;11744 result_peer->suspend_pos.basic_block_index = SIZE_MAX;
11745 result_peer->suspend_pos.instruction_index = SIZE_MAX;11745 result_peer->suspend_pos.instruction_index = SIZE_MAX;
...@@ -11766,7 +11766,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc...@@ -11766,7 +11766,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
11766 return ira->codegen->invalid_inst_gen;11766 return ira->codegen->invalid_inst_gen;
11767 if (peer_parent_has_type) {11767 if (peer_parent_has_type) {
11768 peer_parent->skipped = true;11768 peer_parent->skipped = true;
11769 IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,11769 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,
11770 value_type, value, force_runtime || !is_condition_comptime, true);11770 value_type, value, force_runtime || !is_condition_comptime, true);
11771 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||11771 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||
11772 parent_result_loc->value->type->id == ZigTypeIdUnreachable)11772 parent_result_loc->value->type->id == ZigTypeIdUnreachable)
...@@ -11783,7 +11783,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc...@@ -11783,7 +11783,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
11783 if (peer_parent->end_bb->suspend_instruction_ref == nullptr) {11783 if (peer_parent->end_bb->suspend_instruction_ref == nullptr) {
11784 peer_parent->end_bb->suspend_instruction_ref = suspend_source_instr;11784 peer_parent->end_bb->suspend_instruction_ref = suspend_source_instr;
11785 }11785 }
11786 IrInstGen *unreach_inst = ira_suspend(ira, suspend_source_instr, result_peer->next_bb,11786 Stage1AirInst *unreach_inst = ira_suspend(ira, suspend_source_instr, result_peer->next_bb,
11787 &result_peer->suspend_pos);11787 &result_peer->suspend_pos);
11788 if (result_peer->next_bb == nullptr) {11788 if (result_peer->next_bb == nullptr) {
11789 ir_start_next_bb(ira);11789 ir_start_next_bb(ira);
...@@ -11791,7 +11791,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc...@@ -11791,7 +11791,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
11791 return unreach_inst;11791 return unreach_inst;
11792 }11792 }
1179311793
11794 IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,11794 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,
11795 peer_parent->resolved_type, nullptr, force_runtime, true);11795 peer_parent->resolved_type, nullptr, force_runtime, true);
11796 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||11796 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||
11797 parent_result_loc->value->type->id == ZigTypeIdUnreachable)11797 parent_result_loc->value->type->id == ZigTypeIdUnreachable)
...@@ -11814,7 +11814,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc...@@ -11814,7 +11814,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
11814 return ir_resolve_no_result_loc(ira, suspend_source_instr, result_loc, value_type);11814 return ir_resolve_no_result_loc(ira, suspend_source_instr, result_loc, value_type);
11815 }11815 }
1181611816
11817 IrInstGen *casted_value;11817 Stage1AirInst *casted_value;
11818 if (value != nullptr) {11818 if (value != nullptr) {
11819 casted_value = ir_implicit_cast2(ira, suspend_source_instr->scope,11819 casted_value = ir_implicit_cast2(ira, suspend_source_instr->scope,
11820 suspend_source_instr->source_node, value, dest_type);11820 suspend_source_instr->source_node, value, dest_type);
...@@ -11825,7 +11825,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc...@@ -11825,7 +11825,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
11825 casted_value = nullptr;11825 casted_value = nullptr;
11826 }11826 }
1182711827
11828 IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_cast->parent,11828 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_cast->parent,
11829 dest_type, casted_value, force_runtime, true);11829 dest_type, casted_value, force_runtime, true);
11830 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||11830 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||
11831 parent_result_loc->value->type->id == ZigTypeIdUnreachable)11831 parent_result_loc->value->type->id == ZigTypeIdUnreachable)
...@@ -11922,7 +11922,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc...@@ -11922,7 +11922,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
11922 return ira->codegen->invalid_inst_gen;11922 return ira->codegen->invalid_inst_gen;
11923 }11923 }
1192411924
11925 IrInstGen *bitcasted_value;11925 Stage1AirInst *bitcasted_value;
11926 if (value != nullptr) {11926 if (value != nullptr) {
11927 bitcasted_value = ir_analyze_bit_cast(ira, result_loc->source_instruction->scope,11927 bitcasted_value = ir_analyze_bit_cast(ira, result_loc->source_instruction->scope,
11928 result_loc->source_instruction->source_node, value, dest_type);11928 result_loc->source_instruction->source_node, value, dest_type);
...@@ -11936,7 +11936,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc...@@ -11936,7 +11936,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
11936 }11936 }
1193711937
11938 bool parent_was_written = result_bit_cast->parent->written;11938 bool parent_was_written = result_bit_cast->parent->written;
11939 IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_bit_cast->parent,11939 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_bit_cast->parent,
11940 dest_type, bitcasted_value, force_runtime, true);11940 dest_type, bitcasted_value, force_runtime, true);
11941 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||11941 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||
11942 parent_result_loc->value->type->id == ZigTypeIdUnreachable)11942 parent_result_loc->value->type->id == ZigTypeIdUnreachable)
...@@ -11987,15 +11987,15 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc...@@ -11987,15 +11987,15 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
11987 zig_unreachable();11987 zig_unreachable();
11988}11988}
1198911989
11990static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_instr,11990static Stage1AirInst *ir_resolve_result(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr,
11991 ResultLoc *result_loc_pass1, ZigType *value_type, IrInstGen *value, bool force_runtime,11991 ResultLoc *result_loc_pass1, ZigType *value_type, Stage1AirInst *value, bool force_runtime,
11992 bool allow_discard)11992 bool allow_discard)
11993{11993{
11994 if (!allow_discard && result_loc_is_discard(result_loc_pass1)) {11994 if (!allow_discard && result_loc_is_discard(result_loc_pass1)) {
11995 result_loc_pass1 = no_result_loc();11995 result_loc_pass1 = no_result_loc();
11996 }11996 }
11997 bool was_written = result_loc_pass1->written;11997 bool was_written = result_loc_pass1->written;
11998 IrInstGen *result_loc = ir_resolve_result_raw(ira, suspend_source_instr, result_loc_pass1, value_type,11998 Stage1AirInst *result_loc = ir_resolve_result_raw(ira, suspend_source_instr, result_loc_pass1, value_type,
11999 value, force_runtime, allow_discard);11999 value, force_runtime, allow_discard);
12000 if (result_loc == nullptr || result_loc->value->type->id == ZigTypeIdUnreachable ||12000 if (result_loc == nullptr || result_loc->value->type->id == ZigTypeIdUnreachable ||
12001 type_is_invalid(result_loc->value->type))12001 type_is_invalid(result_loc->value->type))
...@@ -12012,7 +12012,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in...@@ -12012,7 +12012,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in
12012 InferredStructField *isf = result_loc->value->type->data.pointer.inferred_struct_field;12012 InferredStructField *isf = result_loc->value->type->data.pointer.inferred_struct_field;
12013 if (isf != nullptr) {12013 if (isf != nullptr) {
12014 TypeStructField *field;12014 TypeStructField *field;
12015 IrInstGen *casted_ptr;12015 Stage1AirInst *casted_ptr;
12016 if (isf->already_resolved) {12016 if (isf->already_resolved) {
12017 field = find_struct_type_field(isf->inferred_struct_type, isf->field_name);12017 field = find_struct_type_field(isf->inferred_struct_type, isf->field_name);
12018 casted_ptr = result_loc;12018 casted_ptr = result_loc;
...@@ -12102,7 +12102,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in...@@ -12102,7 +12102,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in
12102 return ir_analyze_unwrap_err_code(ira, suspend_source_instr->scope,12102 return ir_analyze_unwrap_err_code(ira, suspend_source_instr->scope,
12103 suspend_source_instr->source_node, result_loc, true);12103 suspend_source_instr->source_node, result_loc, true);
12104 } else {12104 } else {
12105 IrInstGen *unwrapped_err_ptr = ir_analyze_unwrap_error_payload(ira,12105 Stage1AirInst *unwrapped_err_ptr = ir_analyze_unwrap_error_payload(ira,
12106 suspend_source_instr->scope, suspend_source_instr->source_node,12106 suspend_source_instr->scope, suspend_source_instr->source_node,
12107 result_loc, false, true);12107 result_loc, false, true);
12108 ZigType *actual_payload_type = actual_elem_type->data.error_union.payload_type;12108 ZigType *actual_payload_type = actual_elem_type->data.error_union.payload_type;
...@@ -12119,7 +12119,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in...@@ -12119,7 +12119,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in
12119 return result_loc;12119 return result_loc;
12120}12120}
1212112121
12122static IrInstGen *ir_analyze_instruction_resolve_result(IrAnalyze *ira, IrInstSrcResolveResult *instruction) {12122static Stage1AirInst *ir_analyze_instruction_resolve_result(IrAnalyze *ira, Stage1ZirInstResolveResult *instruction) {
12123 ZigType *implicit_elem_type;12123 ZigType *implicit_elem_type;
12124 if (instruction->ty == nullptr) {12124 if (instruction->ty == nullptr) {
12125 if (instruction->result_loc->id == ResultLocIdCast) {12125 if (instruction->result_loc->id == ResultLocIdCast) {
...@@ -12158,7 +12158,7 @@ static IrInstGen *ir_analyze_instruction_resolve_result(IrAnalyze *ira, IrInstSr...@@ -12158,7 +12158,7 @@ static IrInstGen *ir_analyze_instruction_resolve_result(IrAnalyze *ira, IrInstSr
12158 if (type_is_invalid(implicit_elem_type))12158 if (type_is_invalid(implicit_elem_type))
12159 return ira->codegen->invalid_inst_gen;12159 return ira->codegen->invalid_inst_gen;
12160 }12160 }
12161 IrInstGen *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,12161 Stage1AirInst *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
12162 implicit_elem_type, nullptr, false, true);12162 implicit_elem_type, nullptr, false, true);
12163 if (result_loc != nullptr)12163 if (result_loc != nullptr)
12164 return result_loc;12164 return result_loc;
...@@ -12178,9 +12178,9 @@ static IrInstGen *ir_analyze_instruction_resolve_result(IrAnalyze *ira, IrInstSr...@@ -12178,9 +12178,9 @@ static IrInstGen *ir_analyze_instruction_resolve_result(IrAnalyze *ira, IrInstSr
12178 return result_loc;12178 return result_loc;
12179 }12179 }
1218012180
12181 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, implicit_elem_type);12181 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, implicit_elem_type);
12182 result->value->special = ConstValSpecialUndef;12182 result->value->special = ConstValSpecialUndef;
12183 IrInstGen *ptr = ir_get_ref(ira, instruction->base.scope, instruction->base.source_node, result, false, false);12183 Stage1AirInst *ptr = ir_get_ref(ira, instruction->base.scope, instruction->base.source_node, result, false, false);
12184 ptr->value->data.x_ptr.mut = ConstPtrMutComptimeVar;12184 ptr->value->data.x_ptr.mut = ConstPtrMutComptimeVar;
12185 return ptr;12185 return ptr;
12186}12186}
...@@ -12204,7 +12204,7 @@ static void ir_reset_result(ResultLoc *result_loc) {...@@ -12204,7 +12204,7 @@ static void ir_reset_result(ResultLoc *result_loc) {
12204 break;12204 break;
12205 }12205 }
12206 case ResultLocIdVar: {12206 case ResultLocIdVar: {
12207 IrInstSrcAlloca *alloca_src = reinterpret_cast<IrInstSrcAlloca *>(result_loc->source_instruction);12207 Stage1ZirInstAlloca *alloca_src = reinterpret_cast<Stage1ZirInstAlloca *>(result_loc->source_instruction);
12208 alloca_src->base.child = nullptr;12208 alloca_src->base.child = nullptr;
12209 break;12209 break;
12210 }12210 }
...@@ -12220,14 +12220,14 @@ static void ir_reset_result(ResultLoc *result_loc) {...@@ -12220,14 +12220,14 @@ static void ir_reset_result(ResultLoc *result_loc) {
12220 }12220 }
12221}12221}
1222212222
12223static IrInstGen *ir_analyze_instruction_reset_result(IrAnalyze *ira, IrInstSrcResetResult *instruction) {12223static Stage1AirInst *ir_analyze_instruction_reset_result(IrAnalyze *ira, Stage1ZirInstResetResult *instruction) {
12224 ir_reset_result(instruction->result_loc);12224 ir_reset_result(instruction->result_loc);
12225 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);12225 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
12226}12226}
1222712227
12228static IrInstGen *get_async_call_result_loc(IrAnalyze *ira, Scope *scope, AstNode *source_node,12228static Stage1AirInst *get_async_call_result_loc(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12229 ZigType *fn_ret_type, bool is_async_call_builtin, IrInstGen **args_ptr, size_t args_len,12229 ZigType *fn_ret_type, bool is_async_call_builtin, Stage1AirInst **args_ptr, size_t args_len,
12230 IrInstGen *ret_ptr_uncasted)12230 Stage1AirInst *ret_ptr_uncasted)
12231{12231{
12232 src_assert(is_async_call_builtin, source_node);12232 src_assert(is_async_call_builtin, source_node);
12233 if (type_is_invalid(ret_ptr_uncasted->value->type))12233 if (type_is_invalid(ret_ptr_uncasted->value->type))
...@@ -12239,9 +12239,9 @@ static IrInstGen *get_async_call_result_loc(IrAnalyze *ira, Scope *scope, AstNod...@@ -12239,9 +12239,9 @@ static IrInstGen *get_async_call_result_loc(IrAnalyze *ira, Scope *scope, AstNod
12239 return ir_implicit_cast(ira, ret_ptr_uncasted, get_pointer_to_type(ira->codegen, fn_ret_type, false));12239 return ir_implicit_cast(ira, ret_ptr_uncasted, get_pointer_to_type(ira->codegen, fn_ret_type, false));
12240}12240}
1224112241
12242static IrInstGen *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry,12242static Stage1AirInst *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry,
12243 ZigType *fn_type, IrInstGen *fn_ref, IrInstGen **casted_args, size_t arg_count,12243 ZigType *fn_type, Stage1AirInst *fn_ref, Stage1AirInst **casted_args, size_t arg_count,
12244 IrInstGen *casted_new_stack, bool is_async_call_builtin, IrInstGen *ret_ptr_uncasted,12244 Stage1AirInst *casted_new_stack, bool is_async_call_builtin, Stage1AirInst *ret_ptr_uncasted,
12245 ResultLoc *call_result_loc)12245 ResultLoc *call_result_loc)
12246{12246{
12247 if (fn_entry == nullptr) {12247 if (fn_entry == nullptr) {
...@@ -12257,20 +12257,20 @@ static IrInstGen *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -12257,20 +12257,20 @@ static IrInstGen *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *s
12257 }12257 }
12258 if (casted_new_stack != nullptr) {12258 if (casted_new_stack != nullptr) {
12259 ZigType *fn_ret_type = fn_type->data.fn.fn_type_id.return_type;12259 ZigType *fn_ret_type = fn_type->data.fn.fn_type_id.return_type;
12260 IrInstGen *ret_ptr = get_async_call_result_loc(ira, scope, source_node, fn_ret_type, is_async_call_builtin,12260 Stage1AirInst *ret_ptr = get_async_call_result_loc(ira, scope, source_node, fn_ret_type, is_async_call_builtin,
12261 casted_args, arg_count, ret_ptr_uncasted);12261 casted_args, arg_count, ret_ptr_uncasted);
12262 if (ret_ptr != nullptr && type_is_invalid(ret_ptr->value->type))12262 if (ret_ptr != nullptr && type_is_invalid(ret_ptr->value->type))
12263 return ira->codegen->invalid_inst_gen;12263 return ira->codegen->invalid_inst_gen;
1226412264
12265 ZigType *anyframe_type = get_any_frame_type(ira->codegen, fn_ret_type);12265 ZigType *anyframe_type = get_any_frame_type(ira->codegen, fn_ret_type);
1226612266
12267 IrInstGenCall *call_gen = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref,12267 Stage1AirInstCall *call_gen = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref,
12268 arg_count, casted_args, CallModifierAsync, casted_new_stack,12268 arg_count, casted_args, CallModifierAsync, casted_new_stack,
12269 is_async_call_builtin, ret_ptr, anyframe_type);12269 is_async_call_builtin, ret_ptr, anyframe_type);
12270 return &call_gen->base;12270 return &call_gen->base;
12271 } else {12271 } else {
12272 ZigType *frame_type = get_fn_frame_type(ira->codegen, fn_entry);12272 ZigType *frame_type = get_fn_frame_type(ira->codegen, fn_entry);
12273 IrInstGen *result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc,12273 Stage1AirInst *result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc,
12274 frame_type, nullptr, true, false);12274 frame_type, nullptr, true, false);
12275 if (type_is_invalid(result_loc->value->type) || result_loc->value->type->id == ZigTypeIdUnreachable) {12275 if (type_is_invalid(result_loc->value->type) || result_loc->value->type->id == ZigTypeIdUnreachable) {
12276 return result_loc;12276 return result_loc;
...@@ -12285,12 +12285,12 @@ static IrInstGen *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -12285,12 +12285,12 @@ static IrInstGen *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *s
12285 }12285 }
12286}12286}
12287static bool ir_analyze_fn_call_inline_arg(IrAnalyze *ira, AstNode *fn_proto_node,12287static bool ir_analyze_fn_call_inline_arg(IrAnalyze *ira, AstNode *fn_proto_node,
12288 IrInstGen *arg, Scope **exec_scope, size_t *next_proto_i)12288 Stage1AirInst *arg, Scope **exec_scope, size_t *next_proto_i)
12289{12289{
12290 AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(*next_proto_i);12290 AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(*next_proto_i);
12291 assert(param_decl_node->type == NodeTypeParamDecl);12291 assert(param_decl_node->type == NodeTypeParamDecl);
1229212292
12293 IrInstGen *casted_arg;12293 Stage1AirInst *casted_arg;
12294 if (param_decl_node->data.param_decl.anytype_token == 0) {12294 if (param_decl_node->data.param_decl.anytype_token == 0) {
12295 AstNode *param_type_node = param_decl_node->data.param_decl.type;12295 AstNode *param_type_node = param_decl_node->data.param_decl.type;
12296 ZigType *param_type = ir_analyze_type_expr(ira, *exec_scope, param_type_node);12296 ZigType *param_type = ir_analyze_type_expr(ira, *exec_scope, param_type_node);
...@@ -12318,15 +12318,15 @@ static bool ir_analyze_fn_call_inline_arg(IrAnalyze *ira, AstNode *fn_proto_node...@@ -12318,15 +12318,15 @@ static bool ir_analyze_fn_call_inline_arg(IrAnalyze *ira, AstNode *fn_proto_node
12318}12318}
1231912319
12320static bool ir_analyze_fn_call_generic_arg(IrAnalyze *ira, AstNode *fn_proto_node,12320static bool ir_analyze_fn_call_generic_arg(IrAnalyze *ira, AstNode *fn_proto_node,
12321 IrInstGen *arg, AstNode *arg_src, Scope **child_scope, size_t *next_proto_i,12321 Stage1AirInst *arg, AstNode *arg_src, Scope **child_scope, size_t *next_proto_i,
12322 GenericFnTypeId *generic_id, FnTypeId *fn_type_id, IrInstGen **casted_args,12322 GenericFnTypeId *generic_id, FnTypeId *fn_type_id, Stage1AirInst **casted_args,
12323 ZigFn *impl_fn)12323 ZigFn *impl_fn)
12324{12324{
12325 AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(*next_proto_i);12325 AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(*next_proto_i);
12326 assert(param_decl_node->type == NodeTypeParamDecl);12326 assert(param_decl_node->type == NodeTypeParamDecl);
12327 bool is_var_args = param_decl_node->data.param_decl.is_var_args;12327 bool is_var_args = param_decl_node->data.param_decl.is_var_args;
12328 bool arg_part_of_generic_id = false;12328 bool arg_part_of_generic_id = false;
12329 IrInstGen *casted_arg;12329 Stage1AirInst *casted_arg;
1233012330
12331 ZigType *param_info_type = nullptr;12331 ZigType *param_info_type = nullptr;
12332 if (is_var_args) {12332 if (is_var_args) {
...@@ -12414,7 +12414,7 @@ static bool ir_analyze_fn_call_generic_arg(IrAnalyze *ira, AstNode *fn_proto_nod...@@ -12414,7 +12414,7 @@ static bool ir_analyze_fn_call_generic_arg(IrAnalyze *ira, AstNode *fn_proto_nod
12414 return true;12414 return true;
12415}12415}
1241612416
12417static IrInstGen *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) {12417static Stage1AirInst *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) {
12418 while (var->next_var != nullptr) {12418 while (var->next_var != nullptr) {
12419 var = var->next_var;12419 var = var->next_var;
12420 }12420 }
...@@ -12433,7 +12433,7 @@ static IrInstGen *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_n...@@ -12433,7 +12433,7 @@ static IrInstGen *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_n
12433 bool comptime_var_mem = ir_get_var_is_comptime(var);12433 bool comptime_var_mem = ir_get_var_is_comptime(var);
12434 bool linkage_makes_it_runtime = var->decl_node->data.variable_declaration.is_extern;12434 bool linkage_makes_it_runtime = var->decl_node->data.variable_declaration.is_extern;
1243512435
12436 IrInstGen *result = ir_build_var_ptr_gen(ira, scope, source_node, var);12436 Stage1AirInst *result = ir_build_var_ptr_gen(ira, scope, source_node, var);
12437 result->value->type = var_ptr_type;12437 result->value->type = var_ptr_type;
1243812438
12439 if (!linkage_makes_it_runtime && !var->is_thread_local && value_is_comptime(var->const_value)) {12439 if (!linkage_makes_it_runtime && !var->is_thread_local && value_is_comptime(var->const_value)) {
...@@ -12482,8 +12482,8 @@ static void mark_comptime_value_escape(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -12482,8 +12482,8 @@ static void mark_comptime_value_escape(IrAnalyze *ira, Scope *scope, AstNode *so
12482 }12482 }
12483}12483}
1248412484
12485static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,12485static Stage1AirInst *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12486 IrInstGen *ptr, IrInstGen *uncasted_value, bool allow_write_through_const)12486 Stage1AirInst *ptr, Stage1AirInst *uncasted_value, bool allow_write_through_const)
12487{12487{
12488 assert(ptr->value->type->id == ZigTypeIdPointer);12488 assert(ptr->value->type->id == ZigTypeIdPointer);
1248912489
...@@ -12503,7 +12503,7 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -12503,7 +12503,7 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so
12503 }12503 }
1250412504
12505 ZigType *child_type = ptr->value->type->data.pointer.child_type;12505 ZigType *child_type = ptr->value->type->data.pointer.child_type;
12506 IrInstGen *value = ir_implicit_cast(ira, uncasted_value, child_type);12506 Stage1AirInst *value = ir_implicit_cast(ira, uncasted_value, child_type);
12507 if (type_is_invalid(value->value->type))12507 if (type_is_invalid(value->value->type))
12508 return ira->codegen->invalid_inst_gen;12508 return ira->codegen->invalid_inst_gen;
1250912509
...@@ -12583,14 +12583,14 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -12583,14 +12583,14 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so
12583 }12583 }
1258412584
12585 // If this is a store to a pointer with a runtime-known vector index,12585 // If this is a store to a pointer with a runtime-known vector index,
12586 // we have to figure out the IrInstGen which represents the index and12586 // we have to figure out the Stage1AirInst which represents the index and
12587 // emit a IrInstGenVectorStoreElem, or emit a compile error12587 // emit a Stage1AirInstVectorStoreElem, or emit a compile error
12588 // explaining why it is impossible for this store to work. Which is that12588 // explaining why it is impossible for this store to work. Which is that
12589 // the pointer address is of the vector; without the element index being known12589 // the pointer address is of the vector; without the element index being known
12590 // we cannot properly perform the insertion.12590 // we cannot properly perform the insertion.
12591 if (ptr->value->type->data.pointer.vector_index == VECTOR_INDEX_RUNTIME) {12591 if (ptr->value->type->data.pointer.vector_index == VECTOR_INDEX_RUNTIME) {
12592 if (ptr->id == IrInstGenIdElemPtr) {12592 if (ptr->id == Stage1AirInstIdElemPtr) {
12593 IrInstGenElemPtr *elem_ptr = (IrInstGenElemPtr *)ptr;12593 Stage1AirInstElemPtr *elem_ptr = (Stage1AirInstElemPtr *)ptr;
12594 return ir_build_vector_store_elem(ira, scope, source_node, elem_ptr->array_ptr,12594 return ir_build_vector_store_elem(ira, scope, source_node, elem_ptr->array_ptr,
12595 elem_ptr->elem_index, value);12595 elem_ptr->elem_index, value);
12596 }12596 }
...@@ -12603,8 +12603,8 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -12603,8 +12603,8 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so
12603 return ir_build_store_ptr_gen(ira, scope, source_node, ptr, value);12603 return ir_build_store_ptr_gen(ira, scope, source_node, ptr, value);
12604}12604}
1260512605
12606static IrInstGen *analyze_casted_new_stack(IrAnalyze *ira, Scope *scope, AstNode *source_node,12606static Stage1AirInst *analyze_casted_new_stack(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12607 IrInstGen *new_stack, AstNode *new_stack_src, bool is_async_call_builtin, ZigFn *fn_entry)12607 Stage1AirInst *new_stack, AstNode *new_stack_src, bool is_async_call_builtin, ZigFn *fn_entry)
12608{12608{
12609 if (new_stack == nullptr)12609 if (new_stack == nullptr)
12610 return nullptr;12610 return nullptr;
...@@ -12637,11 +12637,11 @@ static IrInstGen *analyze_casted_new_stack(IrAnalyze *ira, Scope *scope, AstNode...@@ -12637,11 +12637,11 @@ static IrInstGen *analyze_casted_new_stack(IrAnalyze *ira, Scope *scope, AstNode
12637 }12637 }
12638}12638}
1263912639
12640static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *source_node,12640static Stage1AirInst *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12641 ZigFn *fn_entry, ZigType *fn_type, IrInstGen *fn_ref,12641 ZigFn *fn_entry, ZigType *fn_type, Stage1AirInst *fn_ref,
12642 IrInstGen *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier,12642 Stage1AirInst *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier,
12643 IrInstGen *new_stack, AstNode *new_stack_src, bool is_async_call_builtin,12643 Stage1AirInst *new_stack, AstNode *new_stack_src, bool is_async_call_builtin,
12644 IrInstGen **args_ptr, size_t args_len, IrInstGen *ret_ptr, ResultLoc *call_result_loc)12644 Stage1AirInst **args_ptr, size_t args_len, Stage1AirInst *ret_ptr, ResultLoc *call_result_loc)
12645{12645{
12646 Error err;12646 Error err;
12647 FnTypeId *fn_type_id = &fn_type->data.fn.fn_type_id;12647 FnTypeId *fn_type_id = &fn_type->data.fn.fn_type_id;
...@@ -12729,7 +12729,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -12729,7 +12729,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
12729 first_arg_known_bare = param_type->id != ZigTypeIdPointer;12729 first_arg_known_bare = param_type->id != ZigTypeIdPointer;
12730 }12730 }
1273112731
12732 IrInstGen *first_arg;12732 Stage1AirInst *first_arg;
12733 if (!first_arg_known_bare) {12733 if (!first_arg_known_bare) {
12734 first_arg = first_arg_ptr;12734 first_arg = first_arg_ptr;
12735 } else {12735 } else {
...@@ -12743,7 +12743,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -12743,7 +12743,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
12743 }12743 }
1274412744
12745 for (size_t call_i = 0; call_i < args_len; call_i += 1) {12745 for (size_t call_i = 0; call_i < args_len; call_i += 1) {
12746 IrInstGen *old_arg = args_ptr[call_i];12746 Stage1AirInst *old_arg = args_ptr[call_i];
1274712747
12748 if (!ir_analyze_fn_call_inline_arg(ira, fn_proto_node, old_arg, &exec_scope, &next_proto_i))12748 if (!ir_analyze_fn_call_inline_arg(ira, fn_proto_node, old_arg, &exec_scope, &next_proto_i))
12749 return ira->codegen->invalid_inst_gen;12749 return ira->codegen->invalid_inst_gen;
...@@ -12841,7 +12841,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -12841,7 +12841,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
12841 }12841 }
12842 }12842 }
1284312843
12844 IrInstGen *new_instruction = ir_const_move(ira, scope, source_node, result);12844 Stage1AirInst *new_instruction = ir_const_move(ira, scope, source_node, result);
12845 return ir_finish_anal(ira, new_instruction);12845 return ir_finish_anal(ira, new_instruction);
12846 }12846 }
1284712847
...@@ -12854,7 +12854,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -12854,7 +12854,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1285412854
12855 size_t new_fn_arg_count = first_arg_1_or_0 + args_len;12855 size_t new_fn_arg_count = first_arg_1_or_0 + args_len;
1285612856
12857 IrInstGen **casted_args = heap::c_allocator.allocate<IrInstGen *>(new_fn_arg_count);12857 Stage1AirInst **casted_args = heap::c_allocator.allocate<Stage1AirInst *>(new_fn_arg_count);
1285812858
12859 // Fork a scope of the function with known values for the parameters.12859 // Fork a scope of the function with known values for the parameters.
12860 Scope *parent_scope = fn_entry->fndef_scope->base.parent;12860 Scope *parent_scope = fn_entry->fndef_scope->base.parent;
...@@ -12887,7 +12887,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -12887,7 +12887,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
12887 first_arg_known_bare = param_type->id != ZigTypeIdPointer;12887 first_arg_known_bare = param_type->id != ZigTypeIdPointer;
12888 }12888 }
1288912889
12890 IrInstGen *first_arg;12890 Stage1AirInst *first_arg;
12891 if (!first_arg_known_bare) {12891 if (!first_arg_known_bare) {
12892 first_arg = first_arg_ptr;12892 first_arg = first_arg_ptr;
12893 } else {12893 } else {
...@@ -12907,7 +12907,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -12907,7 +12907,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
12907 ZigFn *parent_fn_entry = ira->fn;12907 ZigFn *parent_fn_entry = ira->fn;
12908 assert(parent_fn_entry);12908 assert(parent_fn_entry);
12909 for (size_t call_i = 0; call_i < args_len; call_i += 1) {12909 for (size_t call_i = 0; call_i < args_len; call_i += 1) {
12910 IrInstGen *arg = args_ptr[call_i];12910 Stage1AirInst *arg = args_ptr[call_i];
1291112911
12912 AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(next_proto_i);12912 AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(next_proto_i);
12913 assert(param_decl_node->type == NodeTypeParamDecl);12913 assert(param_decl_node->type == NodeTypeParamDecl);
...@@ -12932,7 +12932,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -12932,7 +12932,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
12932 {12932 {
12933 return ira->codegen->invalid_inst_gen;12933 return ira->codegen->invalid_inst_gen;
12934 }12934 }
12935 IrInstGenConst *const_instruction = ir_create_inst_noval<IrInstGenConst>(&ira->new_irb,12935 Stage1AirInstConst *const_instruction = ir_create_inst_noval<Stage1AirInstConst>(&ira->new_irb,
12936 impl_fn->child_scope, fn_proto_node->data.fn_proto.align_expr);12936 impl_fn->child_scope, fn_proto_node->data.fn_proto.align_expr);
12937 const_instruction->base.value = align_result;12937 const_instruction->base.value = align_result;
1293812938
...@@ -13015,20 +13015,20 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13015,20 +13015,20 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
13015 parent_fn_entry->calls_or_awaits_errorable_fn = true;13015 parent_fn_entry->calls_or_awaits_errorable_fn = true;
13016 }13016 }
1301713017
13018 IrInstGen *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack,13018 Stage1AirInst *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack,
13019 new_stack_src, is_async_call_builtin, impl_fn);13019 new_stack_src, is_async_call_builtin, impl_fn);
13020 if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type))13020 if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type))
13021 return ira->codegen->invalid_inst_gen;13021 return ira->codegen->invalid_inst_gen;
1302213022
13023 size_t impl_param_count = impl_fn_type_id->param_count;13023 size_t impl_param_count = impl_fn_type_id->param_count;
13024 if (modifier == CallModifierAsync) {13024 if (modifier == CallModifierAsync) {
13025 IrInstGen *result = ir_analyze_async_call(ira, scope, source_node, impl_fn, impl_fn->type_entry,13025 Stage1AirInst *result = ir_analyze_async_call(ira, scope, source_node, impl_fn, impl_fn->type_entry,
13026 nullptr, casted_args, impl_param_count, casted_new_stack, is_async_call_builtin, ret_ptr,13026 nullptr, casted_args, impl_param_count, casted_new_stack, is_async_call_builtin, ret_ptr,
13027 call_result_loc);13027 call_result_loc);
13028 return ir_finish_anal(ira, result);13028 return ir_finish_anal(ira, result);
13029 }13029 }
1303013030
13031 IrInstGen *result_loc;13031 Stage1AirInst *result_loc;
13032 if (handle_is_ptr(ira->codegen, impl_fn_type_id->return_type)) {13032 if (handle_is_ptr(ira->codegen, impl_fn_type_id->return_type)) {
13033 result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc,13033 result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc,
13034 impl_fn_type_id->return_type, nullptr, true, false);13034 impl_fn_type_id->return_type, nullptr, true, false);
...@@ -13041,9 +13041,9 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13041,9 +13041,9 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
13041 return ira->codegen->invalid_inst_gen;13041 return ira->codegen->invalid_inst_gen;
13042 }13042 }
1304313043
13044 IrInstGen *dummy_value = ir_const(ira, scope, source_node, impl_fn_type_id->return_type);13044 Stage1AirInst *dummy_value = ir_const(ira, scope, source_node, impl_fn_type_id->return_type);
13045 dummy_value->value->special = ConstValSpecialRuntime;13045 dummy_value->value->special = ConstValSpecialRuntime;
13046 IrInstGen *dummy_result = ir_implicit_cast2(ira, scope, source_node,13046 Stage1AirInst *dummy_result = ir_implicit_cast2(ira, scope, source_node,
13047 dummy_value, result_loc->value->type->data.pointer.child_type);13047 dummy_value, result_loc->value->type->data.pointer.child_type);
13048 if (type_is_invalid(dummy_result->value->type))13048 if (type_is_invalid(dummy_result->value->type))
13049 return ira->codegen->invalid_inst_gen;13049 return ira->codegen->invalid_inst_gen;
...@@ -13073,7 +13073,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13073,7 +13073,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
13073 parent_fn_entry->inferred_async_fn = impl_fn;13073 parent_fn_entry->inferred_async_fn = impl_fn;
13074 }13074 }
1307513075
13076 IrInstGenCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node,13076 Stage1AirInstCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node,
13077 impl_fn, nullptr, impl_param_count, casted_args, modifier, casted_new_stack,13077 impl_fn, nullptr, impl_param_count, casted_args, modifier, casted_new_stack,
13078 is_async_call_builtin, result_loc, impl_fn_type_id->return_type);13078 is_async_call_builtin, result_loc, impl_fn_type_id->return_type);
1307913079
...@@ -13092,7 +13092,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13092,7 +13092,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
13092 }13092 }
1309313093
1309413094
13095 IrInstGen **casted_args = heap::c_allocator.allocate<IrInstGen *>(call_param_count);13095 Stage1AirInst **casted_args = heap::c_allocator.allocate<Stage1AirInst *>(call_param_count);
13096 size_t next_arg_index = 0;13096 size_t next_arg_index = 0;
13097 if (first_arg_ptr) {13097 if (first_arg_ptr) {
13098 assert(first_arg_ptr->value->type->id == ZigTypeIdPointer);13098 assert(first_arg_ptr->value->type->id == ZigTypeIdPointer);
...@@ -13101,7 +13101,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13101,7 +13101,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
13101 if (type_is_invalid(param_type))13101 if (type_is_invalid(param_type))
13102 return ira->codegen->invalid_inst_gen;13102 return ira->codegen->invalid_inst_gen;
1310313103
13104 IrInstGen *first_arg;13104 Stage1AirInst *first_arg;
13105 if (param_type->id == ZigTypeIdPointer) {13105 if (param_type->id == ZigTypeIdPointer) {
13106 first_arg = first_arg_ptr;13106 first_arg = first_arg_ptr;
13107 } else {13107 } else {
...@@ -13111,7 +13111,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13111,7 +13111,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
13111 return ira->codegen->invalid_inst_gen;13111 return ira->codegen->invalid_inst_gen;
13112 }13112 }
1311313113
13114 IrInstGen *casted_arg = ir_implicit_cast2(ira, first_arg->scope, first_arg_ptr_src, first_arg, param_type);13114 Stage1AirInst *casted_arg = ir_implicit_cast2(ira, first_arg->scope, first_arg_ptr_src, first_arg, param_type);
13115 if (type_is_invalid(casted_arg->value->type))13115 if (type_is_invalid(casted_arg->value->type))
13116 return ira->codegen->invalid_inst_gen;13116 return ira->codegen->invalid_inst_gen;
1311713117
...@@ -13119,11 +13119,11 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13119,11 +13119,11 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
13119 next_arg_index += 1;13119 next_arg_index += 1;
13120 }13120 }
13121 for (size_t call_i = 0; call_i < args_len; call_i += 1) {13121 for (size_t call_i = 0; call_i < args_len; call_i += 1) {
13122 IrInstGen *old_arg = args_ptr[call_i];13122 Stage1AirInst *old_arg = args_ptr[call_i];
13123 if (type_is_invalid(old_arg->value->type))13123 if (type_is_invalid(old_arg->value->type))
13124 return ira->codegen->invalid_inst_gen;13124 return ira->codegen->invalid_inst_gen;
1312513125
13126 IrInstGen *casted_arg;13126 Stage1AirInst *casted_arg;
13127 if (next_arg_index < src_param_count) {13127 if (next_arg_index < src_param_count) {
13128 ZigType *param_type = fn_type_id->param_info[next_arg_index].type;13128 ZigType *param_type = fn_type_id->param_info[next_arg_index].type;
13129 if (type_is_invalid(param_type))13129 if (type_is_invalid(param_type))
...@@ -13151,13 +13151,13 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13151,13 +13151,13 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
13151 return ira->codegen->invalid_inst_gen;13151 return ira->codegen->invalid_inst_gen;
13152 }13152 }
1315313153
13154 IrInstGen *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack, new_stack_src,13154 Stage1AirInst *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack, new_stack_src,
13155 is_async_call_builtin, fn_entry);13155 is_async_call_builtin, fn_entry);
13156 if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type))13156 if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type))
13157 return ira->codegen->invalid_inst_gen;13157 return ira->codegen->invalid_inst_gen;
1315813158
13159 if (modifier == CallModifierAsync) {13159 if (modifier == CallModifierAsync) {
13160 IrInstGen *result = ir_analyze_async_call(ira, scope, source_node, fn_entry, fn_type, fn_ref,13160 Stage1AirInst *result = ir_analyze_async_call(ira, scope, source_node, fn_entry, fn_type, fn_ref,
13161 casted_args, call_param_count, casted_new_stack, is_async_call_builtin, ret_ptr, call_result_loc);13161 casted_args, call_param_count, casted_new_stack, is_async_call_builtin, ret_ptr, call_result_loc);
13162 return ir_finish_anal(ira, result);13162 return ir_finish_anal(ira, result);
13163 }13163 }
...@@ -13170,7 +13170,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13170,7 +13170,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
13170 parent_fn_entry->inferred_async_fn = fn_entry;13170 parent_fn_entry->inferred_async_fn = fn_entry;
13171 }13171 }
1317213172
13173 IrInstGen *result_loc;13173 Stage1AirInst *result_loc;
13174 if (handle_is_ptr(ira->codegen, return_type)) {13174 if (handle_is_ptr(ira->codegen, return_type)) {
13175 result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc,13175 result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc,
13176 return_type, nullptr, true, false);13176 return_type, nullptr, true, false);
...@@ -13185,9 +13185,9 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13185,9 +13185,9 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1318513185
13186 ZigType *expected_return_type = result_loc->value->type->data.pointer.child_type;13186 ZigType *expected_return_type = result_loc->value->type->data.pointer.child_type;
1318713187
13188 IrInstGen *dummy_value = ir_const(ira, scope, source_node, return_type);13188 Stage1AirInst *dummy_value = ir_const(ira, scope, source_node, return_type);
13189 dummy_value->value->special = ConstValSpecialRuntime;13189 dummy_value->value->special = ConstValSpecialRuntime;
13190 IrInstGen *dummy_result = ir_implicit_cast2(ira, scope, source_node,13190 Stage1AirInst *dummy_result = ir_implicit_cast2(ira, scope, source_node,
13191 dummy_value, expected_return_type);13191 dummy_value, expected_return_type);
13192 if (type_is_invalid(dummy_result->value->type)) {13192 if (type_is_invalid(dummy_result->value->type)) {
13193 if ((return_type->id == ZigTypeIdErrorUnion || return_type->id == ZigTypeIdErrorSet) &&13193 if ((return_type->id == ZigTypeIdErrorUnion || return_type->id == ZigTypeIdErrorSet) &&
...@@ -13220,7 +13220,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13220,7 +13220,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
13220 result_loc = nullptr;13220 result_loc = nullptr;
13221 }13221 }
1322213222
13223 IrInstGenCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref,13223 Stage1AirInstCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref,
13224 call_param_count, casted_args, modifier, casted_new_stack,13224 call_param_count, casted_args, modifier, casted_new_stack,
13225 is_async_call_builtin, result_loc, return_type);13225 is_async_call_builtin, result_loc, return_type);
13226 if (get_scope_typeof(scope) == nullptr) {13226 if (get_scope_typeof(scope) == nullptr) {
...@@ -13229,11 +13229,11 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -13229,11 +13229,11 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
13229 return ir_finish_anal(ira, &new_call_instruction->base);13229 return ir_finish_anal(ira, &new_call_instruction->base);
13230}13230}
1323113231
13232static IrInstGen *ir_analyze_fn_call_src(IrAnalyze *ira, IrInstSrcCall *call_instruction,13232static Stage1AirInst *ir_analyze_fn_call_src(IrAnalyze *ira, Stage1ZirInstCall *call_instruction,
13233 ZigFn *fn_entry, ZigType *fn_type, IrInstGen *fn_ref,13233 ZigFn *fn_entry, ZigType *fn_type, Stage1AirInst *fn_ref,
13234 IrInstGen *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier)13234 Stage1AirInst *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier)
13235{13235{
13236 IrInstGen *new_stack = nullptr;13236 Stage1AirInst *new_stack = nullptr;
13237 AstNode *new_stack_src = nullptr;13237 AstNode *new_stack_src = nullptr;
13238 if (call_instruction->new_stack) {13238 if (call_instruction->new_stack) {
13239 new_stack = call_instruction->new_stack->child;13239 new_stack = call_instruction->new_stack->child;
...@@ -13241,19 +13241,19 @@ static IrInstGen *ir_analyze_fn_call_src(IrAnalyze *ira, IrInstSrcCall *call_ins...@@ -13241,19 +13241,19 @@ static IrInstGen *ir_analyze_fn_call_src(IrAnalyze *ira, IrInstSrcCall *call_ins
13241 return ira->codegen->invalid_inst_gen;13241 return ira->codegen->invalid_inst_gen;
13242 new_stack_src = call_instruction->new_stack->source_node;13242 new_stack_src = call_instruction->new_stack->source_node;
13243 }13243 }
13244 IrInstGen **args_ptr = heap::c_allocator.allocate<IrInstGen *>(call_instruction->arg_count);13244 Stage1AirInst **args_ptr = heap::c_allocator.allocate<Stage1AirInst *>(call_instruction->arg_count);
13245 for (size_t i = 0; i < call_instruction->arg_count; i += 1) {13245 for (size_t i = 0; i < call_instruction->arg_count; i += 1) {
13246 args_ptr[i] = call_instruction->args[i]->child;13246 args_ptr[i] = call_instruction->args[i]->child;
13247 if (type_is_invalid(args_ptr[i]->value->type))13247 if (type_is_invalid(args_ptr[i]->value->type))
13248 return ira->codegen->invalid_inst_gen;13248 return ira->codegen->invalid_inst_gen;
13249 }13249 }
13250 IrInstGen *ret_ptr = nullptr;13250 Stage1AirInst *ret_ptr = nullptr;
13251 if (call_instruction->ret_ptr != nullptr) {13251 if (call_instruction->ret_ptr != nullptr) {
13252 ret_ptr = call_instruction->ret_ptr->child;13252 ret_ptr = call_instruction->ret_ptr->child;
13253 if (type_is_invalid(ret_ptr->value->type))13253 if (type_is_invalid(ret_ptr->value->type))
13254 return ira->codegen->invalid_inst_gen;13254 return ira->codegen->invalid_inst_gen;
13255 }13255 }
13256 IrInstGen *result = ir_analyze_fn_call(ira, call_instruction->base.scope,13256 Stage1AirInst *result = ir_analyze_fn_call(ira, call_instruction->base.scope,
13257 call_instruction->base.source_node, fn_entry, fn_type, fn_ref,13257 call_instruction->base.source_node, fn_entry, fn_type, fn_ref,
13258 first_arg_ptr, first_arg_ptr_src, modifier, new_stack, new_stack_src,13258 first_arg_ptr, first_arg_ptr_src, modifier, new_stack, new_stack_src,
13259 call_instruction->is_async_call_builtin, args_ptr, call_instruction->arg_count, ret_ptr,13259 call_instruction->is_async_call_builtin, args_ptr, call_instruction->arg_count, ret_ptr,
...@@ -13262,21 +13262,21 @@ static IrInstGen *ir_analyze_fn_call_src(IrAnalyze *ira, IrInstSrcCall *call_ins...@@ -13262,21 +13262,21 @@ static IrInstGen *ir_analyze_fn_call_src(IrAnalyze *ira, IrInstSrcCall *call_ins
13262 return result;13262 return result;
13263}13263}
1326413264
13265static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node,13265static Stage1AirInst *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node,
13266 IrInstSrc *pass1_options, IrInstSrc *pass1_fn_ref, IrInstGen **args_ptr, size_t args_len,13266 Stage1ZirInst *pass1_options, Stage1ZirInst *pass1_fn_ref, Stage1AirInst **args_ptr, size_t args_len,
13267 ResultLoc *result_loc)13267 ResultLoc *result_loc)
13268{13268{
13269 IrInstGen *options = pass1_options->child;13269 Stage1AirInst *options = pass1_options->child;
13270 if (type_is_invalid(options->value->type))13270 if (type_is_invalid(options->value->type))
13271 return ira->codegen->invalid_inst_gen;13271 return ira->codegen->invalid_inst_gen;
1327213272
13273 IrInstGen *fn_ref = pass1_fn_ref->child;13273 Stage1AirInst *fn_ref = pass1_fn_ref->child;
13274 if (type_is_invalid(fn_ref->value->type))13274 if (type_is_invalid(fn_ref->value->type))
13275 return ira->codegen->invalid_inst_gen;13275 return ira->codegen->invalid_inst_gen;
1327613276
13277 TypeStructField *modifier_field = find_struct_type_field(options->value->type, buf_create_from_str("modifier"));13277 TypeStructField *modifier_field = find_struct_type_field(options->value->type, buf_create_from_str("modifier"));
13278 src_assert(modifier_field != nullptr, source_node);13278 src_assert(modifier_field != nullptr, source_node);
13279 IrInstGen *modifier_inst = ir_analyze_struct_value_field_value(ira, scope, source_node, options, modifier_field);13279 Stage1AirInst *modifier_inst = ir_analyze_struct_value_field_value(ira, scope, source_node, options, modifier_field);
13280 ZigValue *modifier_val = ir_resolve_const(ira, modifier_inst, UndefBad);13280 ZigValue *modifier_val = ir_resolve_const(ira, modifier_inst, UndefBad);
13281 if (modifier_val == nullptr)13281 if (modifier_val == nullptr)
13282 return ira->codegen->invalid_inst_gen;13282 return ira->codegen->invalid_inst_gen;
...@@ -13307,7 +13307,7 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -13307,7 +13307,7 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s
13307 }13307 }
13308 }13308 }
1330913309
13310 IrInstGen *first_arg_ptr = nullptr;13310 Stage1AirInst *first_arg_ptr = nullptr;
13311 AstNode *first_arg_ptr_src = nullptr;13311 AstNode *first_arg_ptr_src = nullptr;
13312 ZigFn *fn = nullptr;13312 ZigFn *fn = nullptr;
13313 if (instr_is_comptime(fn_ref)) {13313 if (instr_is_comptime(fn_ref)) {
...@@ -13342,16 +13342,16 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -13342,16 +13342,16 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s
1334213342
13343 TypeStructField *stack_field = find_struct_type_field(options->value->type, buf_create_from_str("stack"));13343 TypeStructField *stack_field = find_struct_type_field(options->value->type, buf_create_from_str("stack"));
13344 src_assert(stack_field != nullptr, source_node);13344 src_assert(stack_field != nullptr, source_node);
13345 IrInstGen *opt_stack = ir_analyze_struct_value_field_value(ira, scope, source_node, options, stack_field);13345 Stage1AirInst *opt_stack = ir_analyze_struct_value_field_value(ira, scope, source_node, options, stack_field);
13346 if (type_is_invalid(opt_stack->value->type))13346 if (type_is_invalid(opt_stack->value->type))
13347 return ira->codegen->invalid_inst_gen;13347 return ira->codegen->invalid_inst_gen;
1334813348
13349 IrInstGen *stack_is_non_null_inst = ir_analyze_test_non_null(ira, scope, source_node, opt_stack);13349 Stage1AirInst *stack_is_non_null_inst = ir_analyze_test_non_null(ira, scope, source_node, opt_stack);
13350 bool stack_is_non_null;13350 bool stack_is_non_null;
13351 if (!ir_resolve_bool(ira, stack_is_non_null_inst, &stack_is_non_null))13351 if (!ir_resolve_bool(ira, stack_is_non_null_inst, &stack_is_non_null))
13352 return ira->codegen->invalid_inst_gen;13352 return ira->codegen->invalid_inst_gen;
1335313353
13354 IrInstGen *stack = nullptr;13354 Stage1AirInst *stack = nullptr;
13355 AstNode *stack_src = nullptr;13355 AstNode *stack_src = nullptr;
13356 if (stack_is_non_null) {13356 if (stack_is_non_null) {
13357 stack = ir_analyze_optional_value_payload_value(ira, scope, source_node, opt_stack, false);13357 stack = ir_analyze_optional_value_payload_value(ira, scope, source_node, opt_stack, false);
...@@ -13364,10 +13364,10 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -13364,10 +13364,10 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s
13364 modifier, stack, stack_src, false, args_ptr, args_len, nullptr, result_loc);13364 modifier, stack, stack_src, false, args_ptr, args_len, nullptr, result_loc);
13365}13365}
1336613366
13367static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node, CallModifier modifier,13367static Stage1AirInst *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node, CallModifier modifier,
13368 IrInstSrc *pass1_fn_ref, IrInstSrc *ret_ptr, IrInstSrc *new_stack, IrInstGen **args_ptr, size_t args_len, ResultLoc *result_loc)13368 Stage1ZirInst *pass1_fn_ref, Stage1ZirInst *ret_ptr, Stage1ZirInst *new_stack, Stage1AirInst **args_ptr, size_t args_len, ResultLoc *result_loc)
13369{13369{
13370 IrInstGen *fn_ref = pass1_fn_ref->child;13370 Stage1AirInst *fn_ref = pass1_fn_ref->child;
13371 if (type_is_invalid(fn_ref->value->type))13371 if (type_is_invalid(fn_ref->value->type))
13372 return ira->codegen->invalid_inst_gen;13372 return ira->codegen->invalid_inst_gen;
1337313373
...@@ -13376,7 +13376,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN...@@ -13376,7 +13376,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN
13376 return ira->codegen->invalid_inst_gen;13376 return ira->codegen->invalid_inst_gen;
13377 }13377 }
1337813378
13379 IrInstGen *first_arg_ptr = nullptr;13379 Stage1AirInst *first_arg_ptr = nullptr;
13380 AstNode *first_arg_ptr_src = nullptr;13380 AstNode *first_arg_ptr_src = nullptr;
13381 ZigFn *fn = nullptr;13381 ZigFn *fn = nullptr;
13382 if (instr_is_comptime(fn_ref)) {13382 if (instr_is_comptime(fn_ref)) {
...@@ -13392,7 +13392,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN...@@ -13392,7 +13392,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN
13392 }13392 }
13393 }13393 }
1339413394
13395 IrInstGen *ret_ptr_uncasted = nullptr;13395 Stage1AirInst *ret_ptr_uncasted = nullptr;
13396 if (ret_ptr != nullptr) {13396 if (ret_ptr != nullptr) {
13397 ret_ptr_uncasted = ret_ptr->child;13397 ret_ptr_uncasted = ret_ptr->child;
13398 if (type_is_invalid(ret_ptr_uncasted->value->type))13398 if (type_is_invalid(ret_ptr_uncasted->value->type))
...@@ -13400,7 +13400,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN...@@ -13400,7 +13400,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN
13400 }13400 }
1340113401
13402 ZigType *fn_type = (fn != nullptr) ? fn->type_entry : fn_ref->value->type;13402 ZigType *fn_type = (fn != nullptr) ? fn->type_entry : fn_ref->value->type;
13403 IrInstGen *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node,13403 Stage1AirInst *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node,
13404 new_stack->child, new_stack->source_node, true, fn);13404 new_stack->child, new_stack->source_node, true, fn);
13405 if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type))13405 if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type))
13406 return ira->codegen->invalid_inst_gen;13406 return ira->codegen->invalid_inst_gen;
...@@ -13410,7 +13410,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN...@@ -13410,7 +13410,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN
13410 args_len, ret_ptr_uncasted, result_loc);13410 args_len, ret_ptr_uncasted, result_loc);
13411}13411}
1341213412
13413static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *args, IrInstGen ***args_ptr, size_t *args_len) {13413static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *args, Stage1AirInst ***args_ptr, size_t *args_len) {
13414 ZigType *args_type = args->value->type;13414 ZigType *args_type = args->value->type;
13415 if (type_is_invalid(args_type))13415 if (type_is_invalid(args_type))
13416 return false;13416 return false;
...@@ -13423,7 +13423,7 @@ static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -13423,7 +13423,7 @@ static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *so
1342313423
13424 if (is_tuple(args_type)) {13424 if (is_tuple(args_type)) {
13425 *args_len = args_type->data.structure.src_field_count;13425 *args_len = args_type->data.structure.src_field_count;
13426 *args_ptr = heap::c_allocator.allocate<IrInstGen *>(*args_len);13426 *args_ptr = heap::c_allocator.allocate<Stage1AirInst *>(*args_len);
13427 for (size_t i = 0; i < *args_len; i += 1) {13427 for (size_t i = 0; i < *args_len; i += 1) {
13428 TypeStructField *arg_field = args_type->data.structure.fields[i];13428 TypeStructField *arg_field = args_type->data.structure.fields[i];
13429 (*args_ptr)[i] = ir_analyze_struct_value_field_value(ira, scope, source_node, args, arg_field);13429 (*args_ptr)[i] = ir_analyze_struct_value_field_value(ira, scope, source_node, args, arg_field);
...@@ -13437,50 +13437,50 @@ static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -13437,50 +13437,50 @@ static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *so
13437 return true;13437 return true;
13438}13438}
1343913439
13440static IrInstGen *ir_analyze_instruction_call_extra(IrAnalyze *ira, IrInstSrcCallExtra *instruction) {13440static Stage1AirInst *ir_analyze_instruction_call_extra(IrAnalyze *ira, Stage1ZirInstCallExtra *instruction) {
13441 IrInstGen *args = instruction->args->child;13441 Stage1AirInst *args = instruction->args->child;
13442 IrInstGen **args_ptr = nullptr;13442 Stage1AirInst **args_ptr = nullptr;
13443 size_t args_len = 0;13443 size_t args_len = 0;
13444 if (!ir_extract_tuple_call_args(ira, instruction->base.scope, instruction->base.source_node, args, &args_ptr, &args_len)) {13444 if (!ir_extract_tuple_call_args(ira, instruction->base.scope, instruction->base.source_node, args, &args_ptr, &args_len)) {
13445 return ira->codegen->invalid_inst_gen;13445 return ira->codegen->invalid_inst_gen;
13446 }13446 }
1344713447
13448 IrInstGen *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options,13448 Stage1AirInst *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options,
13449 instruction->fn_ref, args_ptr, args_len, instruction->result_loc);13449 instruction->fn_ref, args_ptr, args_len, instruction->result_loc);
13450 heap::c_allocator.deallocate(args_ptr, args_len);13450 heap::c_allocator.deallocate(args_ptr, args_len);
13451 return result;13451 return result;
13452}13452}
1345313453
13454static IrInstGen *ir_analyze_instruction_async_call_extra(IrAnalyze *ira, IrInstSrcAsyncCallExtra *instruction) {13454static Stage1AirInst *ir_analyze_instruction_async_call_extra(IrAnalyze *ira, Stage1ZirInstAsyncCallExtra *instruction) {
13455 IrInstGen *args = instruction->args->child;13455 Stage1AirInst *args = instruction->args->child;
13456 IrInstGen **args_ptr = nullptr;13456 Stage1AirInst **args_ptr = nullptr;
13457 size_t args_len = 0;13457 size_t args_len = 0;
13458 if (!ir_extract_tuple_call_args(ira, instruction->base.scope, instruction->base.source_node, args, &args_ptr, &args_len)) {13458 if (!ir_extract_tuple_call_args(ira, instruction->base.scope, instruction->base.source_node, args, &args_ptr, &args_len)) {
13459 return ira->codegen->invalid_inst_gen;13459 return ira->codegen->invalid_inst_gen;
13460 }13460 }
1346113461
13462 IrInstGen *result = ir_analyze_async_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->modifier,13462 Stage1AirInst *result = ir_analyze_async_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->modifier,
13463 instruction->fn_ref, instruction->ret_ptr, instruction->new_stack, args_ptr, args_len, instruction->result_loc);13463 instruction->fn_ref, instruction->ret_ptr, instruction->new_stack, args_ptr, args_len, instruction->result_loc);
13464 heap::c_allocator.deallocate(args_ptr, args_len);13464 heap::c_allocator.deallocate(args_ptr, args_len);
13465 return result;13465 return result;
13466}13466}
1346713467
13468static IrInstGen *ir_analyze_instruction_call_args(IrAnalyze *ira, IrInstSrcCallArgs *instruction) {13468static Stage1AirInst *ir_analyze_instruction_call_args(IrAnalyze *ira, Stage1ZirInstCallArgs *instruction) {
13469 IrInstGen **args_ptr = heap::c_allocator.allocate<IrInstGen *>(instruction->args_len);13469 Stage1AirInst **args_ptr = heap::c_allocator.allocate<Stage1AirInst *>(instruction->args_len);
13470 for (size_t i = 0; i < instruction->args_len; i += 1) {13470 for (size_t i = 0; i < instruction->args_len; i += 1) {
13471 args_ptr[i] = instruction->args_ptr[i]->child;13471 args_ptr[i] = instruction->args_ptr[i]->child;
13472 if (type_is_invalid(args_ptr[i]->value->type))13472 if (type_is_invalid(args_ptr[i]->value->type))
13473 return ira->codegen->invalid_inst_gen;13473 return ira->codegen->invalid_inst_gen;
13474 }13474 }
1347513475
13476 IrInstGen *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options,13476 Stage1AirInst *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options,
13477 instruction->fn_ref, args_ptr, instruction->args_len, instruction->result_loc);13477 instruction->fn_ref, args_ptr, instruction->args_len, instruction->result_loc);
13478 heap::c_allocator.deallocate(args_ptr, instruction->args_len);13478 heap::c_allocator.deallocate(args_ptr, instruction->args_len);
13479 return result;13479 return result;
13480}13480}
1348113481
13482static IrInstGen *ir_analyze_instruction_call(IrAnalyze *ira, IrInstSrcCall *call_instruction) {13482static Stage1AirInst *ir_analyze_instruction_call(IrAnalyze *ira, Stage1ZirInstCall *call_instruction) {
13483 IrInstGen *fn_ref = call_instruction->fn_ref->child;13483 Stage1AirInst *fn_ref = call_instruction->fn_ref->child;
13484 if (type_is_invalid(fn_ref->value->type))13484 if (type_is_invalid(fn_ref->value->type))
13485 return ira->codegen->invalid_inst_gen;13485 return ira->codegen->invalid_inst_gen;
1348613486
...@@ -13507,7 +13507,7 @@ static IrInstGen *ir_analyze_instruction_call(IrAnalyze *ira, IrInstSrcCall *cal...@@ -13507,7 +13507,7 @@ static IrInstGen *ir_analyze_instruction_call(IrAnalyze *ira, IrInstSrcCall *cal
13507 } else if (fn_ref->value->type->id == ZigTypeIdBoundFn) {13507 } else if (fn_ref->value->type->id == ZigTypeIdBoundFn) {
13508 assert(fn_ref->value->special == ConstValSpecialStatic);13508 assert(fn_ref->value->special == ConstValSpecialStatic);
13509 ZigFn *fn_table_entry = fn_ref->value->data.x_bound_fn.fn;13509 ZigFn *fn_table_entry = fn_ref->value->data.x_bound_fn.fn;
13510 IrInstGen *first_arg_ptr = fn_ref->value->data.x_bound_fn.first_arg;13510 Stage1AirInst *first_arg_ptr = fn_ref->value->data.x_bound_fn.first_arg;
13511 AstNode *first_arg_ptr_src = fn_ref->value->data.x_bound_fn.first_arg_src;13511 AstNode *first_arg_ptr_src = fn_ref->value->data.x_bound_fn.first_arg_src;
13512 CallModifier modifier = is_comptime ? CallModifierCompileTime : call_instruction->modifier;13512 CallModifier modifier = is_comptime ? CallModifierCompileTime : call_instruction->modifier;
13513 return ir_analyze_fn_call_src(ira, call_instruction, fn_table_entry, fn_table_entry->type_entry,13513 return ir_analyze_fn_call_src(ira, call_instruction, fn_table_entry, fn_table_entry->type_entry,
...@@ -13641,8 +13641,8 @@ static Error ir_read_const_ptr(IrAnalyze *ira, CodeGen *codegen, AstNode *source...@@ -13641,8 +13641,8 @@ static Error ir_read_const_ptr(IrAnalyze *ira, CodeGen *codegen, AstNode *source
13641 zig_unreachable();13641 zig_unreachable();
13642}13642}
1364313643
13644static IrInstGen *ir_analyze_optional_type(IrAnalyze *ira, IrInstSrcUnOp *instruction) {13644static Stage1AirInst *ir_analyze_optional_type(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) {
13645 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);13645 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
13646 result->value->special = ConstValSpecialLazy;13646 result->value->special = ConstValSpecialLazy;
1364713647
13648 LazyValueOptType *lazy_opt_type = heap::c_allocator.create<LazyValueOptType>();13648 LazyValueOptType *lazy_opt_type = heap::c_allocator.create<LazyValueOptType>();
...@@ -13692,8 +13692,8 @@ static ErrorMsg *ir_eval_negation_scalar(IrAnalyze *ira, Scope *scope, AstNode *...@@ -13692,8 +13692,8 @@ static ErrorMsg *ir_eval_negation_scalar(IrAnalyze *ira, Scope *scope, AstNode *
13692 return nullptr;13692 return nullptr;
13693}13693}
1369413694
13695static IrInstGen *ir_analyze_negation(IrAnalyze *ira, IrInstSrcUnOp *instruction) {13695static Stage1AirInst *ir_analyze_negation(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) {
13696 IrInstGen *value = instruction->value->child;13696 Stage1AirInst *value = instruction->value->child;
13697 ZigType *expr_type = value->value->type;13697 ZigType *expr_type = value->value->type;
13698 if (type_is_invalid(expr_type))13698 if (type_is_invalid(expr_type))
13699 return ira->codegen->invalid_inst_gen;13699 return ira->codegen->invalid_inst_gen;
...@@ -13723,7 +13723,7 @@ static IrInstGen *ir_analyze_negation(IrAnalyze *ira, IrInstSrcUnOp *instruction...@@ -13723,7 +13723,7 @@ static IrInstGen *ir_analyze_negation(IrAnalyze *ira, IrInstSrcUnOp *instruction
13723 if (!operand_val)13723 if (!operand_val)
13724 return ira->codegen->invalid_inst_gen;13724 return ira->codegen->invalid_inst_gen;
1372513725
13726 IrInstGen *result_instruction = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);13726 Stage1AirInst *result_instruction = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);
13727 ZigValue *out_val = result_instruction->value;13727 ZigValue *out_val = result_instruction->value;
13728 if (expr_type->id == ZigTypeIdVector) {13728 if (expr_type->id == ZigTypeIdVector) {
13729 expand_undef_array(ira->codegen, operand_val);13729 expand_undef_array(ira->codegen, operand_val);
...@@ -13758,8 +13758,8 @@ static IrInstGen *ir_analyze_negation(IrAnalyze *ira, IrInstSrcUnOp *instruction...@@ -13758,8 +13758,8 @@ static IrInstGen *ir_analyze_negation(IrAnalyze *ira, IrInstSrcUnOp *instruction
13758 return ir_build_negation(ira, instruction->base.scope, instruction->base.source_node, value, expr_type, is_wrap_op);13758 return ir_build_negation(ira, instruction->base.scope, instruction->base.source_node, value, expr_type, is_wrap_op);
13759}13759}
1376013760
13761static IrInstGen *ir_analyze_bin_not(IrAnalyze *ira, IrInstSrcUnOp *instruction) {13761static Stage1AirInst *ir_analyze_bin_not(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) {
13762 IrInstGen *value = instruction->value->child;13762 Stage1AirInst *value = instruction->value->child;
13763 ZigType *expr_type = value->value->type;13763 ZigType *expr_type = value->value->type;
13764 if (type_is_invalid(expr_type))13764 if (type_is_invalid(expr_type))
13765 return ira->codegen->invalid_inst_gen;13765 return ira->codegen->invalid_inst_gen;
...@@ -13778,7 +13778,7 @@ static IrInstGen *ir_analyze_bin_not(IrAnalyze *ira, IrInstSrcUnOp *instruction)...@@ -13778,7 +13778,7 @@ static IrInstGen *ir_analyze_bin_not(IrAnalyze *ira, IrInstSrcUnOp *instruction)
13778 if (expr_val == nullptr)13778 if (expr_val == nullptr)
13779 return ira->codegen->invalid_inst_gen;13779 return ira->codegen->invalid_inst_gen;
1378013780
13781 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);13781 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);
1378213782
13783 if (expr_type->id == ZigTypeIdVector) {13783 if (expr_type->id == ZigTypeIdVector) {
13784 expand_undef_array(ira->codegen, expr_val);13784 expand_undef_array(ira->codegen, expr_val);
...@@ -13805,7 +13805,7 @@ static IrInstGen *ir_analyze_bin_not(IrAnalyze *ira, IrInstSrcUnOp *instruction)...@@ -13805,7 +13805,7 @@ static IrInstGen *ir_analyze_bin_not(IrAnalyze *ira, IrInstSrcUnOp *instruction)
13805 return ir_build_binary_not(ira, instruction->base.scope, instruction->base.source_node, value, expr_type);13805 return ir_build_binary_not(ira, instruction->base.scope, instruction->base.source_node, value, expr_type);
13806}13806}
1380713807
13808static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *instruction) {13808static Stage1AirInst *ir_analyze_instruction_un_op(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) {
13809 IrUnOp op_id = instruction->op_id;13809 IrUnOp op_id = instruction->op_id;
13810 switch (op_id) {13810 switch (op_id) {
13811 case IrUnOpInvalid:13811 case IrUnOpInvalid:
...@@ -13816,7 +13816,7 @@ static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *in...@@ -13816,7 +13816,7 @@ static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *in
13816 case IrUnOpNegationWrap:13816 case IrUnOpNegationWrap:
13817 return ir_analyze_negation(ira, instruction);13817 return ir_analyze_negation(ira, instruction);
13818 case IrUnOpDereference: {13818 case IrUnOpDereference: {
13819 IrInstGen *ptr = instruction->value->child;13819 Stage1AirInst *ptr = instruction->value->child;
13820 if (type_is_invalid(ptr->value->type))13820 if (type_is_invalid(ptr->value->type))
13821 return ira->codegen->invalid_inst_gen;13821 return ira->codegen->invalid_inst_gen;
13822 ZigType *ptr_type = ptr->value->type;13822 ZigType *ptr_type = ptr->value->type;
...@@ -13827,7 +13827,7 @@ static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *in...@@ -13827,7 +13827,7 @@ static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *in
13827 return ira->codegen->invalid_inst_gen;13827 return ira->codegen->invalid_inst_gen;
13828 }13828 }
1382913829
13830 IrInstGen *result = ir_get_deref(ira, instruction->base.scope,13830 Stage1AirInst *result = ir_get_deref(ira, instruction->base.scope,
13831 instruction->base.source_node, ptr, instruction->result_loc);13831 instruction->base.source_node, ptr, instruction->result_loc);
13832 if (type_is_invalid(result->value->type))13832 if (type_is_invalid(result->value->type))
13833 return ira->codegen->invalid_inst_gen;13833 return ira->codegen->invalid_inst_gen;
...@@ -13860,7 +13860,7 @@ static void ir_push_resume_block(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb) {...@@ -13860,7 +13860,7 @@ static void ir_push_resume_block(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb) {
13860 }13860 }
13861}13861}
1386213862
13863static IrInstGen *ir_analyze_instruction_br(IrAnalyze *ira, IrInstSrcBr *br_instruction) {13863static Stage1AirInst *ir_analyze_instruction_br(IrAnalyze *ira, Stage1ZirInstBr *br_instruction) {
13864 Stage1ZirBasicBlock *old_dest_block = br_instruction->dest_block;13864 Stage1ZirBasicBlock *old_dest_block = br_instruction->dest_block;
1386513865
13866 bool is_comptime;13866 bool is_comptime;
...@@ -13870,18 +13870,18 @@ static IrInstGen *ir_analyze_instruction_br(IrAnalyze *ira, IrInstSrcBr *br_inst...@@ -13870,18 +13870,18 @@ static IrInstGen *ir_analyze_instruction_br(IrAnalyze *ira, IrInstSrcBr *br_inst
13870 if (is_comptime || (old_dest_block->ref_count == 1 && old_dest_block->suspend_instruction_ref == nullptr))13870 if (is_comptime || (old_dest_block->ref_count == 1 && old_dest_block->suspend_instruction_ref == nullptr))
13871 return ir_inline_bb(ira, br_instruction->base.source_node, old_dest_block);13871 return ir_inline_bb(ira, br_instruction->base.source_node, old_dest_block);
1387213872
13873 IrBasicBlockGen *new_bb = ir_get_new_bb_runtime(ira, old_dest_block, &br_instruction->base);13873 Stage1AirBasicBlock *new_bb = ir_get_new_bb_runtime(ira, old_dest_block, &br_instruction->base);
13874 if (new_bb == nullptr)13874 if (new_bb == nullptr)
13875 return ir_unreach_error(ira);13875 return ir_unreach_error(ira);
1387613876
13877 ir_push_resume_block(ira, old_dest_block);13877 ir_push_resume_block(ira, old_dest_block);
1387813878
13879 IrInstGen *result = ir_build_br_gen(ira, br_instruction->base.scope, br_instruction->base.source_node, new_bb);13879 Stage1AirInst *result = ir_build_br_gen(ira, br_instruction->base.scope, br_instruction->base.source_node, new_bb);
13880 return ir_finish_anal(ira, result);13880 return ir_finish_anal(ira, result);
13881}13881}
1388213882
13883static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr *cond_br_instruction) {13883static Stage1AirInst *ir_analyze_instruction_cond_br(IrAnalyze *ira, Stage1ZirInstCondBr *cond_br_instruction) {
13884 IrInstGen *condition = cond_br_instruction->condition->child;13884 Stage1AirInst *condition = cond_br_instruction->condition->child;
13885 if (type_is_invalid(condition->value->type))13885 if (type_is_invalid(condition->value->type))
13886 return ir_unreach_error(ira);13886 return ir_unreach_error(ira);
1388713887
...@@ -13890,7 +13890,7 @@ static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr...@@ -13890,7 +13890,7 @@ static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr
13890 return ir_unreach_error(ira);13890 return ir_unreach_error(ira);
1389113891
13892 ZigType *bool_type = ira->codegen->builtin_types.entry_bool;13892 ZigType *bool_type = ira->codegen->builtin_types.entry_bool;
13893 IrInstGen *casted_condition = ir_implicit_cast(ira, condition, bool_type);13893 Stage1AirInst *casted_condition = ir_implicit_cast(ira, condition, bool_type);
13894 if (type_is_invalid(casted_condition->value->type))13894 if (type_is_invalid(casted_condition->value->type))
13895 return ir_unreach_error(ira);13895 return ir_unreach_error(ira);
1389613896
...@@ -13905,37 +13905,37 @@ static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr...@@ -13905,37 +13905,37 @@ static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr
13905 if (is_comptime || (old_dest_block->ref_count == 1 && old_dest_block->suspend_instruction_ref == nullptr))13905 if (is_comptime || (old_dest_block->ref_count == 1 && old_dest_block->suspend_instruction_ref == nullptr))
13906 return ir_inline_bb(ira, cond_br_instruction->base.source_node, old_dest_block);13906 return ir_inline_bb(ira, cond_br_instruction->base.source_node, old_dest_block);
1390713907
13908 IrBasicBlockGen *new_dest_block = ir_get_new_bb_runtime(ira, old_dest_block, &cond_br_instruction->base);13908 Stage1AirBasicBlock *new_dest_block = ir_get_new_bb_runtime(ira, old_dest_block, &cond_br_instruction->base);
13909 if (new_dest_block == nullptr)13909 if (new_dest_block == nullptr)
13910 return ir_unreach_error(ira);13910 return ir_unreach_error(ira);
1391113911
13912 ir_push_resume_block(ira, old_dest_block);13912 ir_push_resume_block(ira, old_dest_block);
1391313913
13914 IrInstGen *result = ir_build_br_gen(ira, cond_br_instruction->base.scope,13914 Stage1AirInst *result = ir_build_br_gen(ira, cond_br_instruction->base.scope,
13915 cond_br_instruction->base.source_node, new_dest_block);13915 cond_br_instruction->base.source_node, new_dest_block);
13916 return ir_finish_anal(ira, result);13916 return ir_finish_anal(ira, result);
13917 }13917 }
1391813918
13919 assert(cond_br_instruction->then_block != cond_br_instruction->else_block);13919 assert(cond_br_instruction->then_block != cond_br_instruction->else_block);
13920 IrBasicBlockGen *new_then_block = ir_get_new_bb_runtime(ira, cond_br_instruction->then_block, &cond_br_instruction->base);13920 Stage1AirBasicBlock *new_then_block = ir_get_new_bb_runtime(ira, cond_br_instruction->then_block, &cond_br_instruction->base);
13921 if (new_then_block == nullptr)13921 if (new_then_block == nullptr)
13922 return ir_unreach_error(ira);13922 return ir_unreach_error(ira);
1392313923
13924 IrBasicBlockGen *new_else_block = ir_get_new_bb_runtime(ira, cond_br_instruction->else_block, &cond_br_instruction->base);13924 Stage1AirBasicBlock *new_else_block = ir_get_new_bb_runtime(ira, cond_br_instruction->else_block, &cond_br_instruction->base);
13925 if (new_else_block == nullptr)13925 if (new_else_block == nullptr)
13926 return ir_unreach_error(ira);13926 return ir_unreach_error(ira);
1392713927
13928 ir_push_resume_block(ira, cond_br_instruction->else_block);13928 ir_push_resume_block(ira, cond_br_instruction->else_block);
13929 ir_push_resume_block(ira, cond_br_instruction->then_block);13929 ir_push_resume_block(ira, cond_br_instruction->then_block);
1393013930
13931 IrInstGen *result = ir_build_cond_br_gen(ira, cond_br_instruction->base.scope,13931 Stage1AirInst *result = ir_build_cond_br_gen(ira, cond_br_instruction->base.scope,
13932 cond_br_instruction->base.source_node, casted_condition, new_then_block,13932 cond_br_instruction->base.source_node, casted_condition, new_then_block,
13933 new_else_block);13933 new_else_block);
13934 return ir_finish_anal(ira, result);13934 return ir_finish_anal(ira, result);
13935}13935}
1393613936
13937static IrInstGen *ir_analyze_instruction_unreachable(IrAnalyze *ira,13937static Stage1AirInst *ir_analyze_instruction_unreachable(IrAnalyze *ira,
13938 IrInstSrcUnreachable *unreachable_instruction)13938 Stage1ZirInstUnreachable *unreachable_instruction)
13939{13939{
13940 if (ir_should_inline(ira->zir, unreachable_instruction->base.scope)) {13940 if (ir_should_inline(ira->zir, unreachable_instruction->base.scope)) {
13941 ir_add_error_node(ira, unreachable_instruction->base.source_node,13941 ir_add_error_node(ira, unreachable_instruction->base.source_node,
...@@ -13943,12 +13943,12 @@ static IrInstGen *ir_analyze_instruction_unreachable(IrAnalyze *ira,...@@ -13943,12 +13943,12 @@ static IrInstGen *ir_analyze_instruction_unreachable(IrAnalyze *ira,
13943 return ir_unreach_error(ira);13943 return ir_unreach_error(ira);
13944 }13944 }
1394513945
13946 IrInstGen *result = ir_build_unreachable_gen(ira, unreachable_instruction->base.scope,13946 Stage1AirInst *result = ir_build_unreachable_gen(ira, unreachable_instruction->base.scope,
13947 unreachable_instruction->base.source_node);13947 unreachable_instruction->base.source_node);
13948 return ir_finish_anal(ira, result);13948 return ir_finish_anal(ira, result);
13949}13949}
1395013950
13951static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_instruction) {13951static Stage1AirInst *ir_analyze_instruction_phi(IrAnalyze *ira, Stage1ZirInstPhi *phi_instruction) {
13952 Error err;13952 Error err;
1395313953
13954 if (ira->const_predecessor_bb) {13954 if (ira->const_predecessor_bb) {
...@@ -13956,13 +13956,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -13956,13 +13956,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
13956 Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i];13956 Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i];
13957 if (predecessor != ira->const_predecessor_bb)13957 if (predecessor != ira->const_predecessor_bb)
13958 continue;13958 continue;
13959 IrInstGen *value = phi_instruction->incoming_values[i]->child;13959 Stage1AirInst *value = phi_instruction->incoming_values[i]->child;
13960 assert(value->value->type);13960 assert(value->value->type);
13961 if (type_is_invalid(value->value->type))13961 if (type_is_invalid(value->value->type))
13962 return ira->codegen->invalid_inst_gen;13962 return ira->codegen->invalid_inst_gen;
1396313963
13964 if (value->value->special != ConstValSpecialRuntime) {13964 if (value->value->special != ConstValSpecialRuntime) {
13965 IrInstGen *result = ir_const(ira, phi_instruction->base.scope,13965 Stage1AirInst *result = ir_const(ira, phi_instruction->base.scope,
13966 phi_instruction->base.source_node, nullptr);13966 phi_instruction->base.source_node, nullptr);
13967 copy_const_val(ira->codegen, result->value, value->value);13967 copy_const_val(ira->codegen, result->value, value->value);
13968 return result;13968 return result;
...@@ -13978,11 +13978,11 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -13978,11 +13978,11 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
13978 peer_parent->peers.length >= 2)13978 peer_parent->peers.length >= 2)
13979 {13979 {
13980 if (peer_parent->resolved_type == nullptr) {13980 if (peer_parent->resolved_type == nullptr) {
13981 IrInstGen **instructions = heap::c_allocator.allocate<IrInstGen *>(peer_parent->peers.length);13981 Stage1AirInst **instructions = heap::c_allocator.allocate<Stage1AirInst *>(peer_parent->peers.length);
13982 for (size_t i = 0; i < peer_parent->peers.length; i += 1) {13982 for (size_t i = 0; i < peer_parent->peers.length; i += 1) {
13983 ResultLocPeer *this_peer = peer_parent->peers.at(i);13983 ResultLocPeer *this_peer = peer_parent->peers.at(i);
1398413984
13985 IrInstGen *gen_instruction = this_peer->base.gen_instruction;13985 Stage1AirInst *gen_instruction = this_peer->base.gen_instruction;
13986 if (gen_instruction == nullptr) {13986 if (gen_instruction == nullptr) {
13987 // unreachable instructions will cause implicit_elem_type to be null13987 // unreachable instructions will cause implicit_elem_type to be null
13988 if (this_peer->base.implicit_elem_type == nullptr) {13988 if (this_peer->base.implicit_elem_type == nullptr) {
...@@ -14010,7 +14010,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -14010,7 +14010,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
14010 phi_instruction->base.source_node);14010 phi_instruction->base.source_node);
1401114011
14012 // In case resolving the parent activates a suspend, do it now14012 // In case resolving the parent activates a suspend, do it now
14013 IrInstGen *parent_result_loc = ir_resolve_result(ira, &phi_instruction->base, peer_parent->parent,14013 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, &phi_instruction->base, peer_parent->parent,
14014 peer_parent->resolved_type, nullptr, false, true);14014 peer_parent->resolved_type, nullptr, false, true);
14015 if (parent_result_loc != nullptr &&14015 if (parent_result_loc != nullptr &&
14016 (type_is_invalid(parent_result_loc->value->type) || parent_result_loc->value->type->id == ZigTypeIdUnreachable))14016 (type_is_invalid(parent_result_loc->value->type) || parent_result_loc->value->type->id == ZigTypeIdUnreachable))
...@@ -14019,13 +14019,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -14019,13 +14019,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
14019 }14019 }
14020 // If the above code generated any instructions in the current basic block, we need14020 // If the above code generated any instructions in the current basic block, we need
14021 // to move them to the peer parent predecessor.14021 // to move them to the peer parent predecessor.
14022 ZigList<IrInstGen *> instrs_to_move = {};14022 ZigList<Stage1AirInst *> instrs_to_move = {};
14023 while (ira->new_irb.current_basic_block->instruction_list.length != 0) {14023 while (ira->new_irb.current_basic_block->instruction_list.length != 0) {
14024 instrs_to_move.append(ira->new_irb.current_basic_block->instruction_list.pop());14024 instrs_to_move.append(ira->new_irb.current_basic_block->instruction_list.pop());
14025 }14025 }
14026 if (instrs_to_move.length != 0) {14026 if (instrs_to_move.length != 0) {
14027 IrBasicBlockGen *predecessor = peer_parent->base.source_instruction->child->owner_bb;14027 Stage1AirBasicBlock *predecessor = peer_parent->base.source_instruction->child->owner_bb;
14028 IrInstGen *branch_instruction = predecessor->instruction_list.pop();14028 Stage1AirInst *branch_instruction = predecessor->instruction_list.pop();
14029 src_assert(branch_instruction->value->type->id == ZigTypeIdUnreachable,14029 src_assert(branch_instruction->value->type->id == ZigTypeIdUnreachable,
14030 phi_instruction->base.source_node);14030 phi_instruction->base.source_node);
14031 while (instrs_to_move.length != 0) {14031 while (instrs_to_move.length != 0) {
...@@ -14053,8 +14053,8 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -14053,8 +14053,8 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
14053 return ira_resume(ira);14053 return ira_resume(ira);
14054 }14054 }
1405514055
14056 ZigList<IrBasicBlockGen*> new_incoming_blocks = {0};14056 ZigList<Stage1AirBasicBlock*> new_incoming_blocks = {0};
14057 ZigList<IrInstGen*> new_incoming_values = {0};14057 ZigList<Stage1AirInst*> new_incoming_values = {0};
1405814058
14059 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {14059 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
14060 Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i];14060 Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i];
...@@ -14062,9 +14062,9 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -14062,9 +14062,9 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
14062 continue;14062 continue;
1406314063
1406414064
14065 IrInstSrc *old_value = phi_instruction->incoming_values[i];14065 Stage1ZirInst *old_value = phi_instruction->incoming_values[i];
14066 assert(old_value);14066 assert(old_value);
14067 IrInstGen *new_value = old_value->child;14067 Stage1AirInst *new_value = old_value->child;
14068 if (!new_value || new_value->value->type->id == ZigTypeIdUnreachable || predecessor->child == nullptr)14068 if (!new_value || new_value->value->type->id == ZigTypeIdUnreachable || predecessor->child == nullptr)
14069 continue;14069 continue;
1407014070
...@@ -14078,13 +14078,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -14078,13 +14078,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
14078 }14078 }
1407914079
14080 if (new_incoming_blocks.length == 0) {14080 if (new_incoming_blocks.length == 0) {
14081 IrInstGen *result = ir_build_unreachable_gen(ira, phi_instruction->base.scope,14081 Stage1AirInst *result = ir_build_unreachable_gen(ira, phi_instruction->base.scope,
14082 phi_instruction->base.source_node);14082 phi_instruction->base.source_node);
14083 return ir_finish_anal(ira, result);14083 return ir_finish_anal(ira, result);
14084 }14084 }
1408514085
14086 if (new_incoming_blocks.length == 1) {14086 if (new_incoming_blocks.length == 1) {
14087 IrInstGen *incoming_value = new_incoming_values.at(0);14087 Stage1AirInst *incoming_value = new_incoming_values.at(0);
14088 new_incoming_blocks.deinit();14088 new_incoming_blocks.deinit();
14089 new_incoming_values.deinit();14089 new_incoming_values.deinit();
14090 return incoming_value;14090 return incoming_value;
...@@ -14145,14 +14145,14 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -14145,14 +14145,14 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
14145 // cast all values to the resolved type. however we can't put cast instructions in front of the phi instruction.14145 // cast all values to the resolved type. however we can't put cast instructions in front of the phi instruction.
14146 // so we go back and insert the casts as the last instruction in the corresponding predecessor blocks, and14146 // so we go back and insert the casts as the last instruction in the corresponding predecessor blocks, and
14147 // then make sure the branch instruction is preserved.14147 // then make sure the branch instruction is preserved.
14148 IrBasicBlockGen *cur_bb = ira->new_irb.current_basic_block;14148 Stage1AirBasicBlock *cur_bb = ira->new_irb.current_basic_block;
14149 for (size_t i = 0; i < new_incoming_values.length; i += 1) {14149 for (size_t i = 0; i < new_incoming_values.length; i += 1) {
14150 IrInstGen *new_value = new_incoming_values.at(i);14150 Stage1AirInst *new_value = new_incoming_values.at(i);
14151 IrBasicBlockGen *predecessor = new_incoming_blocks.at(i);14151 Stage1AirBasicBlock *predecessor = new_incoming_blocks.at(i);
14152 src_assert(predecessor->instruction_list.length != 0, phi_instruction->base.source_node);14152 src_assert(predecessor->instruction_list.length != 0, phi_instruction->base.source_node);
14153 IrInstGen *branch_instruction = predecessor->instruction_list.pop();14153 Stage1AirInst *branch_instruction = predecessor->instruction_list.pop();
14154 ir_set_cursor_at_end_gen(&ira->new_irb, predecessor);14154 ir_set_cursor_at_end_gen(&ira->new_irb, predecessor);
14155 IrInstGen *casted_value = ir_implicit_cast(ira, new_value, resolved_type);14155 Stage1AirInst *casted_value = ir_implicit_cast(ira, new_value, resolved_type);
14156 if (type_is_invalid(casted_value->value->type)) {14156 if (type_is_invalid(casted_value->value->type)) {
14157 return ira->codegen->invalid_inst_gen;14157 return ira->codegen->invalid_inst_gen;
14158 }14158 }
...@@ -14167,7 +14167,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -14167,7 +14167,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
14167 }14167 }
14168 ir_set_cursor_at_end_gen(&ira->new_irb, cur_bb);14168 ir_set_cursor_at_end_gen(&ira->new_irb, cur_bb);
1416914169
14170 IrInstGen *result = ir_build_phi_gen(ira, phi_instruction->base.scope,14170 Stage1AirInst *result = ir_build_phi_gen(ira, phi_instruction->base.scope,
14171 phi_instruction->base.source_node, new_incoming_blocks.length,14171 phi_instruction->base.source_node, new_incoming_blocks.length,
14172 new_incoming_blocks.items, new_incoming_values.items, resolved_type);14172 new_incoming_blocks.items, new_incoming_values.items, resolved_type);
1417314173
...@@ -14179,9 +14179,9 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -14179,9 +14179,9 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
14179 return result;14179 return result;
14180}14180}
1418114181
14182static IrInstGen *ir_analyze_instruction_var_ptr(IrAnalyze *ira, IrInstSrcVarPtr *instruction) {14182static Stage1AirInst *ir_analyze_instruction_var_ptr(IrAnalyze *ira, Stage1ZirInstVarPtr *instruction) {
14183 ZigVar *var = instruction->var;14183 ZigVar *var = instruction->var;
14184 IrInstGen *result = ir_get_var_ptr(ira, instruction->base.scope, instruction->base.source_node, var);14184 Stage1AirInst *result = ir_get_var_ptr(ira, instruction->base.scope, instruction->base.source_node, var);
14185 if (instruction->crossed_fndef_scope != nullptr && !instr_is_comptime(result)) {14185 if (instruction->crossed_fndef_scope != nullptr && !instr_is_comptime(result)) {
14186 ErrorMsg *msg = ir_add_error_node(ira, instruction->base.source_node,14186 ErrorMsg *msg = ir_add_error_node(ira, instruction->base.source_node,
14187 buf_sprintf("'%s' not accessible from inner function", var->name));14187 buf_sprintf("'%s' not accessible from inner function", var->name));
...@@ -14309,13 +14309,13 @@ static Error compute_elem_align(IrAnalyze *ira, ZigType *elem_type, uint32_t bas...@@ -14309,13 +14309,13 @@ static Error compute_elem_align(IrAnalyze *ira, ZigType *elem_type, uint32_t bas
14309 return ErrorNone;14309 return ErrorNone;
14310}14310}
1431114311
14312static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemPtr *elem_ptr_instruction) {14312static Stage1AirInst *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, Stage1ZirInstElemPtr *elem_ptr_instruction) {
14313 Error err;14313 Error err;
14314 IrInstGen *array_ptr = elem_ptr_instruction->array_ptr->child;14314 Stage1AirInst *array_ptr = elem_ptr_instruction->array_ptr->child;
14315 if (type_is_invalid(array_ptr->value->type))14315 if (type_is_invalid(array_ptr->value->type))
14316 return ira->codegen->invalid_inst_gen;14316 return ira->codegen->invalid_inst_gen;
1431714317
14318 IrInstGen *elem_index = elem_ptr_instruction->elem_index->child;14318 Stage1AirInst *elem_index = elem_ptr_instruction->elem_index->child;
14319 if (type_is_invalid(elem_index->value->type))14319 if (type_is_invalid(elem_index->value->type))
14320 return ira->codegen->invalid_inst_gen;14320 return ira->codegen->invalid_inst_gen;
1432114321
...@@ -14337,7 +14337,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP...@@ -14337,7 +14337,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
14337 array_type->data.pointer.ptr_len == PtrLenSingle &&14337 array_type->data.pointer.ptr_len == PtrLenSingle &&
14338 array_type->data.pointer.child_type->id == ZigTypeIdArray)14338 array_type->data.pointer.child_type->id == ZigTypeIdArray)
14339 {14339 {
14340 IrInstGen *ptr_value = ir_get_deref(ira, elem_ptr_instruction->base.scope,14340 Stage1AirInst *ptr_value = ir_get_deref(ira, elem_ptr_instruction->base.scope,
14341 elem_ptr_instruction->base.source_node, array_ptr, nullptr);14341 elem_ptr_instruction->base.source_node, array_ptr, nullptr);
14342 if (type_is_invalid(ptr_value->value->type))14342 if (type_is_invalid(ptr_value->value->type))
14343 return ira->codegen->invalid_inst_gen;14343 return ira->codegen->invalid_inst_gen;
...@@ -14392,7 +14392,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP...@@ -14392,7 +14392,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
14392 array_type->data.structure.resolve_status == ResolveStatusBeingInferred)14392 array_type->data.structure.resolve_status == ResolveStatusBeingInferred)
14393 {14393 {
14394 ZigType *usize = ira->codegen->builtin_types.entry_usize;14394 ZigType *usize = ira->codegen->builtin_types.entry_usize;
14395 IrInstGen *casted_elem_index = ir_implicit_cast(ira, elem_index, usize);14395 Stage1AirInst *casted_elem_index = ir_implicit_cast(ira, elem_index, usize);
14396 if (type_is_invalid(casted_elem_index->value->type))14396 if (type_is_invalid(casted_elem_index->value->type))
14397 return ira->codegen->invalid_inst_gen;14397 return ira->codegen->invalid_inst_gen;
14398 src_assert(instr_is_comptime(casted_elem_index), elem_ptr_instruction->base.source_node);14398 src_assert(instr_is_comptime(casted_elem_index), elem_ptr_instruction->base.source_node);
...@@ -14421,7 +14421,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP...@@ -14421,7 +14421,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
14421 }14421 }
1442214422
14423 ZigType *usize = ira->codegen->builtin_types.entry_usize;14423 ZigType *usize = ira->codegen->builtin_types.entry_usize;
14424 IrInstGen *casted_elem_index = ir_implicit_cast(ira, elem_index, usize);14424 Stage1AirInst *casted_elem_index = ir_implicit_cast(ira, elem_index, usize);
14425 if (type_is_invalid(casted_elem_index->value->type))14425 if (type_is_invalid(casted_elem_index->value->type))
14426 return ira->codegen->invalid_inst_gen;14426 return ira->codegen->invalid_inst_gen;
1442714427
...@@ -14553,7 +14553,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP...@@ -14553,7 +14553,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
14553 return ira->codegen->invalid_inst_gen;14553 return ira->codegen->invalid_inst_gen;
14554 }14554 }
14555 if (array_type->id == ZigTypeIdPointer) {14555 if (array_type->id == ZigTypeIdPointer) {
14556 IrInstGen *result = ir_const(ira, elem_ptr_instruction->base.scope, elem_ptr_instruction->base.source_node, return_type);14556 Stage1AirInst *result = ir_const(ira, elem_ptr_instruction->base.scope, elem_ptr_instruction->base.source_node, return_type);
14557 ZigValue *out_val = result->value;14557 ZigValue *out_val = result->value;
14558 out_val->data.x_ptr.mut = array_ptr_val->data.x_ptr.mut;14558 out_val->data.x_ptr.mut = array_ptr_val->data.x_ptr.mut;
14559 size_t new_index;14559 size_t new_index;
...@@ -14639,7 +14639,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP...@@ -14639,7 +14639,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
14639 return_type);14639 return_type);
14640 }14640 }
14641 ZigValue *len_field = array_ptr_val->data.x_struct.fields[slice_len_index];14641 ZigValue *len_field = array_ptr_val->data.x_struct.fields[slice_len_index];
14642 IrInstGen *result = ir_const(ira, elem_ptr_instruction->base.scope,14642 Stage1AirInst *result = ir_const(ira, elem_ptr_instruction->base.scope,
14643 elem_ptr_instruction->base.source_node, return_type);14643 elem_ptr_instruction->base.source_node, return_type);
14644 ZigValue *out_val = result->value;14644 ZigValue *out_val = result->value;
14645 ZigType *slice_ptr_type = array_type->data.structure.fields[slice_ptr_index]->type_entry;14645 ZigType *slice_ptr_type = array_type->data.structure.fields[slice_ptr_index]->type_entry;
...@@ -14699,7 +14699,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP...@@ -14699,7 +14699,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
14699 } else if (array_type->id == ZigTypeIdArray || array_type->id == ZigTypeIdVector) {14699 } else if (array_type->id == ZigTypeIdArray || array_type->id == ZigTypeIdVector) {
14700 expand_undef_array(ira->codegen, array_ptr_val);14700 expand_undef_array(ira->codegen, array_ptr_val);
1470114701
14702 IrInstGen *result;14702 Stage1AirInst *result;
14703 if (orig_array_ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {14703 if (orig_array_ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
14704 result = ir_build_elem_ptr_gen(ira, elem_ptr_instruction->base.scope,14704 result = ir_build_elem_ptr_gen(ira, elem_ptr_instruction->base.scope,
14705 elem_ptr_instruction->base.source_node, array_ptr, casted_elem_index,14705 elem_ptr_instruction->base.source_node, array_ptr, casted_elem_index,
...@@ -14766,9 +14766,9 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP...@@ -14766,9 +14766,9 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
14766 elem_ptr_instruction->base.source_node, array_ptr, casted_elem_index, safety_check_on, return_type);14766 elem_ptr_instruction->base.source_node, array_ptr, casted_elem_index, safety_check_on, return_type);
14767}14767}
1476814768
14769static IrInstGen *ir_analyze_container_member_access_inner(IrAnalyze *ira,14769static Stage1AirInst *ir_analyze_container_member_access_inner(IrAnalyze *ira,
14770 ZigType *bare_struct_type, Buf *field_name, Scope *scope, AstNode *source_node,14770 ZigType *bare_struct_type, Buf *field_name, Scope *scope, AstNode *source_node,
14771 IrInstGen *container_ptr, AstNode *container_ptr_src, ZigType *container_type)14771 Stage1AirInst *container_ptr, AstNode *container_ptr_src, ZigType *container_type)
14772{14772{
14773 if (!is_slice(bare_struct_type)) {14773 if (!is_slice(bare_struct_type)) {
14774 ScopeDecls *container_scope = get_container_scope(bare_struct_type);14774 ScopeDecls *container_scope = get_container_scope(bare_struct_type);
...@@ -14798,7 +14798,7 @@ static IrInstGen *ir_analyze_container_member_access_inner(IrAnalyze *ira,...@@ -14798,7 +14798,7 @@ static IrInstGen *ir_analyze_container_member_access_inner(IrAnalyze *ira,
14798 if (type_is_invalid(fn_entry->type_entry))14798 if (type_is_invalid(fn_entry->type_entry))
14799 return ira->codegen->invalid_inst_gen;14799 return ira->codegen->invalid_inst_gen;
1480014800
14801 IrInstGen *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn_entry, container_ptr,14801 Stage1AirInst *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn_entry, container_ptr,
14802 container_ptr_src);14802 container_ptr_src);
14803 return ir_get_ref(ira, scope, source_node, bound_fn_value, true, false);14803 return ir_get_ref(ira, scope, source_node, bound_fn_value, true, false);
14804 } else if (tld->id == TldIdVar) {14804 } else if (tld->id == TldIdVar) {
...@@ -14818,7 +14818,7 @@ static IrInstGen *ir_analyze_container_member_access_inner(IrAnalyze *ira,...@@ -14818,7 +14818,7 @@ static IrInstGen *ir_analyze_container_member_access_inner(IrAnalyze *ira,
14818 if (var->const_value->type->id == ZigTypeIdFn) {14818 if (var->const_value->type->id == ZigTypeIdFn) {
14819 src_assert(var->const_value->data.x_ptr.special == ConstPtrSpecialFunction, source_node);14819 src_assert(var->const_value->data.x_ptr.special == ConstPtrSpecialFunction, source_node);
14820 ZigFn *fn = var->const_value->data.x_ptr.data.fn.fn_entry;14820 ZigFn *fn = var->const_value->data.x_ptr.data.fn.fn_entry;
14821 IrInstGen *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn, container_ptr,14821 Stage1AirInst *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn, container_ptr,
14822 container_ptr_src);14822 container_ptr_src);
14823 return ir_get_ref(ira, scope, source_node, bound_fn_value, true, false);14823 return ir_get_ref(ira, scope, source_node, bound_fn_value, true, false);
14824 }14824 }
...@@ -14857,15 +14857,15 @@ static void memoize_field_init_val(CodeGen *codegen, ZigType *container_type, Ty...@@ -14857,15 +14857,15 @@ static void memoize_field_init_val(CodeGen *codegen, ZigType *container_type, Ty
14857 field->type_entry, nullptr, UndefOk);14857 field->type_entry, nullptr, UndefOk);
14858}14858}
1485914859
14860static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,14860static Stage1AirInst *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
14861 TypeStructField *field, IrInstGen *struct_ptr, ZigType *struct_type, bool initializing)14861 TypeStructField *field, Stage1AirInst *struct_ptr, ZigType *struct_type, bool initializing)
14862{14862{
14863 Error err;14863 Error err;
14864 ZigType *field_type = resolve_struct_field_type(ira->codegen, field);14864 ZigType *field_type = resolve_struct_field_type(ira->codegen, field);
14865 if (field_type == nullptr)14865 if (field_type == nullptr)
14866 return ira->codegen->invalid_inst_gen;14866 return ira->codegen->invalid_inst_gen;
14867 if (field->is_comptime) {14867 if (field->is_comptime) {
14868 IrInstGen *elem = ir_const(ira, scope, source_node, field_type);14868 Stage1AirInst *elem = ir_const(ira, scope, source_node, field_type);
14869 memoize_field_init_val(ira->codegen, struct_type, field);14869 memoize_field_init_val(ira->codegen, struct_type, field);
14870 if(field->init_val != nullptr && type_is_invalid(field->init_val->type)){14870 if(field->init_val != nullptr && type_is_invalid(field->init_val->type)){
14871 return ira->codegen->invalid_inst_gen;14871 return ira->codegen->invalid_inst_gen;
...@@ -14877,7 +14877,7 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN...@@ -14877,7 +14877,7 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN
14877 case OnePossibleValueInvalid:14877 case OnePossibleValueInvalid:
14878 return ira->codegen->invalid_inst_gen;14878 return ira->codegen->invalid_inst_gen;
14879 case OnePossibleValueYes: {14879 case OnePossibleValueYes: {
14880 IrInstGen *elem = ir_const_move(ira, scope, source_node,14880 Stage1AirInst *elem = ir_const_move(ira, scope, source_node,
14881 get_the_one_possible_value(ira->codegen, field_type));14881 get_the_one_possible_value(ira->codegen, field_type));
14882 return ir_get_ref(ira, scope, source_node, elem,14882 return ir_get_ref(ira, scope, source_node, elem,
14883 struct_ptr->value->type->data.pointer.is_const,14883 struct_ptr->value->type->data.pointer.is_const,
...@@ -14941,7 +14941,7 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN...@@ -14941,7 +14941,7 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN
14941 field_val->parent.data.p_struct.field_index = i;14941 field_val->parent.data.p_struct.field_index = i;
14942 }14942 }
14943 }14943 }
14944 IrInstGen *result;14944 Stage1AirInst *result;
14945 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {14945 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
14946 result = ir_build_struct_field_ptr(ira, scope, source_node, struct_ptr, field, ptr_type);14946 result = ir_build_struct_field_ptr(ira, scope, source_node, struct_ptr, field, ptr_type);
14947 result->value->special = ConstValSpecialStatic;14947 result->value->special = ConstValSpecialStatic;
...@@ -14959,8 +14959,8 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN...@@ -14959,8 +14959,8 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN
14959 return ir_build_struct_field_ptr(ira, scope, source_node, struct_ptr, field, ptr_type);14959 return ir_build_struct_field_ptr(ira, scope, source_node, struct_ptr, field, ptr_type);
14960}14960}
1496114961
14962static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,14962static Stage1AirInst *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,
14963 Scope *scope, AstNode *source_node, IrInstGen *container_ptr, ZigType *container_type)14963 Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, ZigType *container_type)
14964{14964{
14965 // The type of the field is not available until a store using this pointer happens.14965 // The type of the field is not available until a store using this pointer happens.
14966 // So, here we create a special pointer type which has the inferred struct type and14966 // So, here we create a special pointer type which has the inferred struct type and
...@@ -14985,7 +14985,7 @@ static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,...@@ -14985,7 +14985,7 @@ static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,
14985 if (ptr_val == nullptr)14985 if (ptr_val == nullptr)
14986 return ira->codegen->invalid_inst_gen;14986 return ira->codegen->invalid_inst_gen;
1498714987
14988 IrInstGen *result;14988 Stage1AirInst *result;
14989 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {14989 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
14990 result = ir_build_cast(ira, scope, source_node, container_ptr_type, container_ptr, CastOpNoop);14990 result = ir_build_cast(ira, scope, source_node, container_ptr_type, container_ptr, CastOpNoop);
14991 } else {14991 } else {
...@@ -14999,8 +14999,8 @@ static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,...@@ -14999,8 +14999,8 @@ static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,
14999 return ir_build_cast(ira, scope, source_node, field_ptr_type, container_ptr, CastOpNoop);14999 return ir_build_cast(ira, scope, source_node, field_ptr_type, container_ptr, CastOpNoop);
15000}15000}
1500115001
15002static IrInstGen *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name,15002static Stage1AirInst *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name,
15003 Scope *scope, AstNode *source_node, IrInstGen *container_ptr, AstNode *container_ptr_src,15003 Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, AstNode *container_ptr_src,
15004 ZigType *container_type, bool initializing)15004 ZigType *container_type, bool initializing)
15005{15005{
15006 Error err;15006 Error err;
...@@ -15108,7 +15108,7 @@ static IrInstGen *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name...@@ -15108,7 +15108,7 @@ static IrInstGen *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name
15108 ZigValue *payload_val = union_val->data.x_union.payload;15108 ZigValue *payload_val = union_val->data.x_union.payload;
15109 assert(payload_val);15109 assert(payload_val);
1511015110
15111 IrInstGen *result;15111 Stage1AirInst *result;
15112 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {15112 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
15113 result = ir_build_union_field_ptr(ira, scope, source_node, container_ptr, field, true,15113 result = ir_build_union_field_ptr(ira, scope, source_node, container_ptr, field, true,
15114 initializing, ptr_type);15114 initializing, ptr_type);
...@@ -15139,12 +15139,12 @@ static void add_link_lib_symbol(IrAnalyze *ira, Buf *lib_name, Buf *symbol_name,...@@ -15139,12 +15139,12 @@ static void add_link_lib_symbol(IrAnalyze *ira, Buf *lib_name, Buf *symbol_name,
15139 }15139 }
15140}15140}
1514115141
15142static IrInstGen *ir_error_dependency_loop(IrAnalyze *ira, AstNode* source_node) {15142static Stage1AirInst *ir_error_dependency_loop(IrAnalyze *ira, AstNode* source_node) {
15143 ir_add_error_node(ira, source_node, buf_sprintf("dependency loop detected"));15143 ir_add_error_node(ira, source_node, buf_sprintf("dependency loop detected"));
15144 return ira->codegen->invalid_inst_gen;15144 return ira->codegen->invalid_inst_gen;
15145}15145}
1514615146
15147static IrInstGen *ir_analyze_decl_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Tld *tld) {15147static Stage1AirInst *ir_analyze_decl_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Tld *tld) {
15148 resolve_top_level_decl(ira->codegen, tld, source_node, true);15148 resolve_top_level_decl(ira->codegen, tld, source_node, true);
15149 if (tld->resolution == TldResolutionInvalid) {15149 if (tld->resolution == TldResolutionInvalid) {
15150 return ira->codegen->invalid_inst_gen;15150 return ira->codegen->invalid_inst_gen;
...@@ -15181,7 +15181,7 @@ static IrInstGen *ir_analyze_decl_ref(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -15181,7 +15181,7 @@ static IrInstGen *ir_analyze_decl_ref(IrAnalyze *ira, Scope *scope, AstNode *sou
15181 add_link_lib_symbol(ira, tld_fn->extern_lib_name, &fn_entry->symbol_name, source_node);15181 add_link_lib_symbol(ira, tld_fn->extern_lib_name, &fn_entry->symbol_name, source_node);
15182 }15182 }
1518315183
15184 IrInstGen *fn_inst = ir_const_fn(ira, scope, source_node, fn_entry);15184 Stage1AirInst *fn_inst = ir_const_fn(ira, scope, source_node, fn_entry);
15185 return ir_get_ref(ira, scope, source_node, fn_inst, true, false);15185 return ir_get_ref(ira, scope, source_node, fn_inst, true, false);
15186 }15186 }
15187 }15187 }
...@@ -15199,9 +15199,9 @@ static ErrorTableEntry *find_err_table_entry(ZigType *err_set_type, Buf *field_n...@@ -15199,9 +15199,9 @@ static ErrorTableEntry *find_err_table_entry(ZigType *err_set_type, Buf *field_n
15199 return nullptr;15199 return nullptr;
15200}15200}
1520115201
15202static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFieldPtr *field_ptr_instruction) {15202static Stage1AirInst *ir_analyze_instruction_field_ptr(IrAnalyze *ira, Stage1ZirInstFieldPtr *field_ptr_instruction) {
15203 Error err;15203 Error err;
15204 IrInstGen *container_ptr = field_ptr_instruction->container_ptr->child;15204 Stage1AirInst *container_ptr = field_ptr_instruction->container_ptr->child;
15205 if (type_is_invalid(container_ptr->value->type))15205 if (type_is_invalid(container_ptr->value->type))
15206 return ira->codegen->invalid_inst_gen;15206 return ira->codegen->invalid_inst_gen;
1520715207
...@@ -15209,7 +15209,7 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel...@@ -15209,7 +15209,7 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel
1520915209
15210 Buf *field_name = field_ptr_instruction->field_name_buffer;15210 Buf *field_name = field_ptr_instruction->field_name_buffer;
15211 if (!field_name) {15211 if (!field_name) {
15212 IrInstGen *field_name_expr = field_ptr_instruction->field_name_expr->child;15212 Stage1AirInst *field_name_expr = field_ptr_instruction->field_name_expr->child;
15213 field_name = ir_resolve_str(ira, field_name_expr);15213 field_name = ir_resolve_str(ira, field_name_expr);
15214 if (!field_name)15214 if (!field_name)
15215 return ira->codegen->invalid_inst_gen;15215 return ira->codegen->invalid_inst_gen;
...@@ -15221,22 +15221,22 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel...@@ -15221,22 +15221,22 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel
15221 if (type_is_invalid(container_type)) {15221 if (type_is_invalid(container_type)) {
15222 return ira->codegen->invalid_inst_gen;15222 return ira->codegen->invalid_inst_gen;
15223 } else if (is_tuple(container_type) && !field_ptr_instruction->initializing && buf_eql_str(field_name, "len")) {15223 } else if (is_tuple(container_type) && !field_ptr_instruction->initializing && buf_eql_str(field_name, "len")) {
15224 IrInstGen *len_inst = ir_const_unsigned(ira, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node,15224 Stage1AirInst *len_inst = ir_const_unsigned(ira, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node,
15225 container_type->data.structure.src_field_count);15225 container_type->data.structure.src_field_count);
15226 return ir_get_ref(ira, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node, len_inst, true, false);15226 return ir_get_ref(ira, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node, len_inst, true, false);
15227 } else if (is_slice(container_type) || is_container_ref(container_type)) {15227 } else if (is_slice(container_type) || is_container_ref(container_type)) {
15228 assert(container_ptr->value->type->id == ZigTypeIdPointer);15228 assert(container_ptr->value->type->id == ZigTypeIdPointer);
15229 if (container_type->id == ZigTypeIdPointer) {15229 if (container_type->id == ZigTypeIdPointer) {
15230 ZigType *bare_type = container_ref_type(container_type);15230 ZigType *bare_type = container_ref_type(container_type);
15231 IrInstGen *container_child = ir_get_deref(ira, field_ptr_instruction->base.scope,15231 Stage1AirInst *container_child = ir_get_deref(ira, field_ptr_instruction->base.scope,
15232 field_ptr_instruction->base.source_node, container_ptr, nullptr);15232 field_ptr_instruction->base.source_node, container_ptr, nullptr);
15233 IrInstGen *result = ir_analyze_container_field_ptr(ira, field_name,15233 Stage1AirInst *result = ir_analyze_container_field_ptr(ira, field_name,
15234 field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node,15234 field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node,
15235 container_child, field_ptr_instruction->container_ptr->source_node, bare_type,15235 container_child, field_ptr_instruction->container_ptr->source_node, bare_type,
15236 field_ptr_instruction->initializing);15236 field_ptr_instruction->initializing);
15237 return result;15237 return result;
15238 } else {15238 } else {
15239 IrInstGen *result = ir_analyze_container_field_ptr(ira, field_name,15239 Stage1AirInst *result = ir_analyze_container_field_ptr(ira, field_name,
15240 field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node,15240 field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node,
15241 container_ptr, field_ptr_instruction->container_ptr->source_node,15241 container_ptr, field_ptr_instruction->container_ptr->source_node,
15242 container_type, field_ptr_instruction->initializing);15242 container_type, field_ptr_instruction->initializing);
...@@ -15390,26 +15390,26 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel...@@ -15390,26 +15390,26 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel
15390 }15390 }
15391}15391}
1539215392
15393static IrInstGen *ir_analyze_instruction_store_ptr(IrAnalyze *ira, IrInstSrcStorePtr *instruction) {15393static Stage1AirInst *ir_analyze_instruction_store_ptr(IrAnalyze *ira, Stage1ZirInstStorePtr *instruction) {
15394 IrInstGen *ptr = instruction->ptr->child;15394 Stage1AirInst *ptr = instruction->ptr->child;
15395 if (type_is_invalid(ptr->value->type))15395 if (type_is_invalid(ptr->value->type))
15396 return ira->codegen->invalid_inst_gen;15396 return ira->codegen->invalid_inst_gen;
1539715397
15398 IrInstGen *value = instruction->value->child;15398 Stage1AirInst *value = instruction->value->child;
15399 if (type_is_invalid(value->value->type))15399 if (type_is_invalid(value->value->type))
15400 return ira->codegen->invalid_inst_gen;15400 return ira->codegen->invalid_inst_gen;
1540115401
15402 return ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, ptr, value, instruction->allow_write_through_const);15402 return ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, ptr, value, instruction->allow_write_through_const);
15403}15403}
1540415404
15405static IrInstGen *ir_analyze_instruction_load_ptr(IrAnalyze *ira, IrInstSrcLoadPtr *instruction) {15405static Stage1AirInst *ir_analyze_instruction_load_ptr(IrAnalyze *ira, Stage1ZirInstLoadPtr *instruction) {
15406 IrInstGen *ptr = instruction->ptr->child;15406 Stage1AirInst *ptr = instruction->ptr->child;
15407 if (type_is_invalid(ptr->value->type))15407 if (type_is_invalid(ptr->value->type))
15408 return ira->codegen->invalid_inst_gen;15408 return ira->codegen->invalid_inst_gen;
15409 return ir_get_deref(ira, instruction->base.scope, instruction->base.source_node, ptr, nullptr);15409 return ir_get_deref(ira, instruction->base.scope, instruction->base.source_node, ptr, nullptr);
15410}15410}
1541115411
15412static IrInstGen *ir_analyze_instruction_typeof(IrAnalyze *ira, IrInstSrcTypeOf *typeof_instruction) {15412static Stage1AirInst *ir_analyze_instruction_typeof(IrAnalyze *ira, Stage1ZirInstTypeOf *typeof_instruction) {
15413 ZigType *type_entry;15413 ZigType *type_entry;
1541415414
15415 const size_t value_count = typeof_instruction->value_count;15415 const size_t value_count = typeof_instruction->value_count;
...@@ -15418,9 +15418,9 @@ static IrInstGen *ir_analyze_instruction_typeof(IrAnalyze *ira, IrInstSrcTypeOf...@@ -15418,9 +15418,9 @@ static IrInstGen *ir_analyze_instruction_typeof(IrAnalyze *ira, IrInstSrcTypeOf
15418 if (value_count < 2) {15418 if (value_count < 2) {
15419 type_entry = typeof_instruction->value.scalar->child->value->type;15419 type_entry = typeof_instruction->value.scalar->child->value->type;
15420 } else {15420 } else {
15421 IrInstGen **args = heap::c_allocator.allocate<IrInstGen*>(value_count);15421 Stage1AirInst **args = heap::c_allocator.allocate<Stage1AirInst*>(value_count);
15422 for (size_t i = 0; i < value_count; i += 1) {15422 for (size_t i = 0; i < value_count; i += 1) {
15423 IrInstGen *value = typeof_instruction->value.list[i]->child;15423 Stage1AirInst *value = typeof_instruction->value.list[i]->child;
15424 if (type_is_invalid(value->value->type))15424 if (type_is_invalid(value->value->type))
15425 return ira->codegen->invalid_inst_gen;15425 return ira->codegen->invalid_inst_gen;
15426 args[i] = value;15426 args[i] = value;
...@@ -15438,13 +15438,13 @@ static IrInstGen *ir_analyze_instruction_typeof(IrAnalyze *ira, IrInstSrcTypeOf...@@ -15438,13 +15438,13 @@ static IrInstGen *ir_analyze_instruction_typeof(IrAnalyze *ira, IrInstSrcTypeOf
15438 return ir_const_type(ira, typeof_instruction->base.scope, typeof_instruction->base.source_node, type_entry);15438 return ir_const_type(ira, typeof_instruction->base.scope, typeof_instruction->base.source_node, type_entry);
15439}15439}
1544015440
15441static IrInstGen *ir_analyze_instruction_set_cold(IrAnalyze *ira, IrInstSrcSetCold *instruction) {15441static Stage1AirInst *ir_analyze_instruction_set_cold(IrAnalyze *ira, Stage1ZirInstSetCold *instruction) {
15442 if (ira->new_irb.exec->is_inline) {15442 if (ira->new_irb.exec->is_inline) {
15443 // ignore setCold when running functions at compile time15443 // ignore setCold when running functions at compile time
15444 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);15444 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
15445 }15445 }
1544615446
15447 IrInstGen *is_cold_value = instruction->is_cold->child;15447 Stage1AirInst *is_cold_value = instruction->is_cold->child;
15448 bool want_cold;15448 bool want_cold;
15449 if (!ir_resolve_bool(ira, is_cold_value, &want_cold))15449 if (!ir_resolve_bool(ira, is_cold_value, &want_cold))
15450 return ira->codegen->invalid_inst_gen;15450 return ira->codegen->invalid_inst_gen;
...@@ -15467,8 +15467,8 @@ static IrInstGen *ir_analyze_instruction_set_cold(IrAnalyze *ira, IrInstSrcSetCo...@@ -15467,8 +15467,8 @@ static IrInstGen *ir_analyze_instruction_set_cold(IrAnalyze *ira, IrInstSrcSetCo
15467 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);15467 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
15468}15468}
1546915469
15470static IrInstGen *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira,15470static Stage1AirInst *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira,
15471 IrInstSrcSetRuntimeSafety *set_runtime_safety_instruction)15471 Stage1ZirInstSetRuntimeSafety *set_runtime_safety_instruction)
15472{15472{
15473 if (ira->new_irb.exec->is_inline) {15473 if (ira->new_irb.exec->is_inline) {
15474 // ignore setRuntimeSafety when running functions at compile time15474 // ignore setRuntimeSafety when running functions at compile time
...@@ -15505,7 +15505,7 @@ static IrInstGen *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira,...@@ -15505,7 +15505,7 @@ static IrInstGen *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira,
15505 }15505 }
15506 assert(scope != nullptr);15506 assert(scope != nullptr);
1550715507
15508 IrInstGen *safety_on_value = set_runtime_safety_instruction->safety_on->child;15508 Stage1AirInst *safety_on_value = set_runtime_safety_instruction->safety_on->child;
15509 bool want_runtime_safety;15509 bool want_runtime_safety;
15510 if (!ir_resolve_bool(ira, safety_on_value, &want_runtime_safety))15510 if (!ir_resolve_bool(ira, safety_on_value, &want_runtime_safety))
15511 return ira->codegen->invalid_inst_gen;15511 return ira->codegen->invalid_inst_gen;
...@@ -15524,8 +15524,8 @@ static IrInstGen *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira,...@@ -15524,8 +15524,8 @@ static IrInstGen *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira,
15524 set_runtime_safety_instruction->base.source_node);15524 set_runtime_safety_instruction->base.source_node);
15525}15525}
1552615526
15527static IrInstGen *ir_analyze_instruction_set_float_mode(IrAnalyze *ira,15527static Stage1AirInst *ir_analyze_instruction_set_float_mode(IrAnalyze *ira,
15528 IrInstSrcSetFloatMode *instruction)15528 Stage1ZirInstSetFloatMode *instruction)
15529{15529{
15530 if (ira->new_irb.exec->is_inline) {15530 if (ira->new_irb.exec->is_inline) {
15531 // ignore setFloatMode when running functions at compile time15531 // ignore setFloatMode when running functions at compile time
...@@ -15561,7 +15561,7 @@ static IrInstGen *ir_analyze_instruction_set_float_mode(IrAnalyze *ira,...@@ -15561,7 +15561,7 @@ static IrInstGen *ir_analyze_instruction_set_float_mode(IrAnalyze *ira,
15561 }15561 }
15562 assert(scope != nullptr);15562 assert(scope != nullptr);
1556315563
15564 IrInstGen *float_mode_value = instruction->mode_value->child;15564 Stage1AirInst *float_mode_value = instruction->mode_value->child;
15565 FloatMode float_mode_scalar;15565 FloatMode float_mode_scalar;
15566 if (!ir_resolve_float_mode(ira, float_mode_value, &float_mode_scalar))15566 if (!ir_resolve_float_mode(ira, float_mode_value, &float_mode_scalar))
15567 return ira->codegen->invalid_inst_gen;15567 return ira->codegen->invalid_inst_gen;
...@@ -15579,7 +15579,7 @@ static IrInstGen *ir_analyze_instruction_set_float_mode(IrAnalyze *ira,...@@ -15579,7 +15579,7 @@ static IrInstGen *ir_analyze_instruction_set_float_mode(IrAnalyze *ira,
15579 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);15579 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
15580}15580}
1558115581
15582static IrInstGen *ir_analyze_instruction_any_frame_type(IrAnalyze *ira, IrInstSrcAnyFrameType *instruction) {15582static Stage1AirInst *ir_analyze_instruction_any_frame_type(IrAnalyze *ira, Stage1ZirInstAnyFrameType *instruction) {
15583 ZigType *payload_type = nullptr;15583 ZigType *payload_type = nullptr;
15584 if (instruction->payload_type != nullptr) {15584 if (instruction->payload_type != nullptr) {
15585 payload_type = ir_resolve_type(ira, instruction->payload_type->child);15585 payload_type = ir_resolve_type(ira, instruction->payload_type->child);
...@@ -15591,8 +15591,8 @@ static IrInstGen *ir_analyze_instruction_any_frame_type(IrAnalyze *ira, IrInstSr...@@ -15591,8 +15591,8 @@ static IrInstGen *ir_analyze_instruction_any_frame_type(IrAnalyze *ira, IrInstSr
15591 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, any_frame_type);15591 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, any_frame_type);
15592}15592}
1559315593
15594static IrInstGen *ir_analyze_instruction_slice_type(IrAnalyze *ira, IrInstSrcSliceType *slice_type_instruction) {15594static Stage1AirInst *ir_analyze_instruction_slice_type(IrAnalyze *ira, Stage1ZirInstSliceType *slice_type_instruction) {
15595 IrInstGen *result = ir_const(ira, slice_type_instruction->base.scope,15595 Stage1AirInst *result = ir_const(ira, slice_type_instruction->base.scope,
15596 slice_type_instruction->base.source_node, ira->codegen->builtin_types.entry_type);15596 slice_type_instruction->base.source_node, ira->codegen->builtin_types.entry_type);
15597 result->value->special = ConstValSpecialLazy;15597 result->value->special = ConstValSpecialLazy;
1559815598
...@@ -15643,7 +15643,7 @@ static size_t find_asm_index(CodeGen *g, AstNode *node, AsmToken *tok, Buf *src_...@@ -15643,7 +15643,7 @@ static size_t find_asm_index(CodeGen *g, AstNode *node, AsmToken *tok, Buf *src_
15643 return SIZE_MAX;15643 return SIZE_MAX;
15644}15644}
1564515645
15646static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_instruction) {15646static Stage1AirInst *ir_analyze_instruction_asm(IrAnalyze *ira, Stage1ZirInstAsm *asm_instruction) {
15647 Error err;15647 Error err;
1564815648
15649 assert(asm_instruction->base.source_node->type == NodeTypeAsmExpr);15649 assert(asm_instruction->base.source_node->type == NodeTypeAsmExpr);
...@@ -15688,8 +15688,8 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i...@@ -15688,8 +15688,8 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i
1568815688
15689 // TODO validate the output types and variable types15689 // TODO validate the output types and variable types
1569015690
15691 IrInstGen **input_list = heap::c_allocator.allocate<IrInstGen *>(asm_expr->input_list.length);15691 Stage1AirInst **input_list = heap::c_allocator.allocate<Stage1AirInst *>(asm_expr->input_list.length);
15692 IrInstGen **output_types = heap::c_allocator.allocate<IrInstGen *>(asm_expr->output_list.length);15692 Stage1AirInst **output_types = heap::c_allocator.allocate<Stage1AirInst *>(asm_expr->output_list.length);
1569315693
15694 ZigType *return_type = ira->codegen->builtin_types.entry_void;15694 ZigType *return_type = ira->codegen->builtin_types.entry_void;
15695 for (size_t i = 0; i < asm_expr->output_list.length; i += 1) {15695 for (size_t i = 0; i < asm_expr->output_list.length; i += 1) {
...@@ -15703,7 +15703,7 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i...@@ -15703,7 +15703,7 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i
15703 }15703 }
1570415704
15705 for (size_t i = 0; i < asm_expr->input_list.length; i += 1) {15705 for (size_t i = 0; i < asm_expr->input_list.length; i += 1) {
15706 IrInstGen *const input_value = asm_instruction->input_list[i]->child;15706 Stage1AirInst *const input_value = asm_instruction->input_list[i]->child;
15707 if (type_is_invalid(input_value->value->type))15707 if (type_is_invalid(input_value->value->type))
15708 return ira->codegen->invalid_inst_gen;15708 return ira->codegen->invalid_inst_gen;
1570915709
...@@ -15724,8 +15724,8 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i...@@ -15724,8 +15724,8 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i
15724 asm_instruction->has_side_effects, return_type);15724 asm_instruction->has_side_effects, return_type);
15725}15725}
1572615726
15727static IrInstGen *ir_analyze_instruction_array_type(IrAnalyze *ira, IrInstSrcArrayType *array_type_instruction) {15727static Stage1AirInst *ir_analyze_instruction_array_type(IrAnalyze *ira, Stage1ZirInstArrayType *array_type_instruction) {
15728 IrInstGen *result = ir_const(ira, array_type_instruction->base.scope,15728 Stage1AirInst *result = ir_const(ira, array_type_instruction->base.scope,
15729 array_type_instruction->base.source_node, ira->codegen->builtin_types.entry_type);15729 array_type_instruction->base.source_node, ira->codegen->builtin_types.entry_type);
15730 result->value->special = ConstValSpecialLazy;15730 result->value->special = ConstValSpecialLazy;
1573115731
...@@ -15750,8 +15750,8 @@ static IrInstGen *ir_analyze_instruction_array_type(IrAnalyze *ira, IrInstSrcArr...@@ -15750,8 +15750,8 @@ static IrInstGen *ir_analyze_instruction_array_type(IrAnalyze *ira, IrInstSrcArr
15750 return result;15750 return result;
15751}15751}
1575215752
15753static IrInstGen *ir_analyze_instruction_size_of(IrAnalyze *ira, IrInstSrcSizeOf *instruction) {15753static Stage1AirInst *ir_analyze_instruction_size_of(IrAnalyze *ira, Stage1ZirInstSizeOf *instruction) {
15754 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int);15754 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int);
15755 result->value->special = ConstValSpecialLazy;15755 result->value->special = ConstValSpecialLazy;
1575615756
15757 LazyValueSizeOf *lazy_size_of = heap::c_allocator.create<LazyValueSizeOf>();15757 LazyValueSizeOf *lazy_size_of = heap::c_allocator.create<LazyValueSizeOf>();
...@@ -15767,7 +15767,7 @@ static IrInstGen *ir_analyze_instruction_size_of(IrAnalyze *ira, IrInstSrcSizeOf...@@ -15767,7 +15767,7 @@ static IrInstGen *ir_analyze_instruction_size_of(IrAnalyze *ira, IrInstSrcSizeOf
15767 return result;15767 return result;
15768}15768}
1576915769
15770static IrInstGen *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) {15770static Stage1AirInst *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) {
15771 ZigType *type_entry = value->value->type;15771 ZigType *type_entry = value->value->type;
1577215772
15773 if (type_entry->id == ZigTypeIdPointer && type_entry->data.pointer.allow_zero) {15773 if (type_entry->id == ZigTypeIdPointer && type_entry->data.pointer.allow_zero) {
...@@ -15803,16 +15803,16 @@ static IrInstGen *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode...@@ -15803,16 +15803,16 @@ static IrInstGen *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode
15803 }15803 }
15804}15804}
1580515805
15806static IrInstGen *ir_analyze_instruction_test_non_null(IrAnalyze *ira, IrInstSrcTestNonNull *instruction) {15806static Stage1AirInst *ir_analyze_instruction_test_non_null(IrAnalyze *ira, Stage1ZirInstTestNonNull *instruction) {
15807 IrInstGen *value = instruction->value->child;15807 Stage1AirInst *value = instruction->value->child;
15808 if (type_is_invalid(value->value->type))15808 if (type_is_invalid(value->value->type))
15809 return ira->codegen->invalid_inst_gen;15809 return ira->codegen->invalid_inst_gen;
1581015810
15811 return ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, value);15811 return ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, value);
15812}15812}
1581315813
15814static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,15814static Stage1AirInst *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
15815 IrInstGen *base_ptr, bool safety_check_on, bool initializing)15815 Stage1AirInst *base_ptr, bool safety_check_on, bool initializing)
15816{15816{
15817 Error err;15817 Error err;
1581815818
...@@ -15841,7 +15841,7 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop...@@ -15841,7 +15841,7 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop
15841 }15841 }
15842 if (!safety_check_on)15842 if (!safety_check_on)
15843 return base_ptr;15843 return base_ptr;
15844 IrInstGen *c_ptr_val = ir_get_deref(ira, scope, source_node, base_ptr, nullptr);15844 Stage1AirInst *c_ptr_val = ir_get_deref(ira, scope, source_node, base_ptr, nullptr);
15845 ir_build_assert_non_null(ira, scope, source_node, c_ptr_val);15845 ir_build_assert_non_null(ira, scope, source_node, c_ptr_val);
15846 return base_ptr;15846 return base_ptr;
15847 }15847 }
...@@ -15900,7 +15900,7 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop...@@ -15900,7 +15900,7 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop
15900 }15900 }
15901 }15901 }
1590215902
15903 IrInstGen *result;15903 Stage1AirInst *result;
15904 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {15904 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
15905 result = ir_build_optional_unwrap_ptr_gen(ira, scope, source_node, base_ptr, false,15905 result = ir_build_optional_unwrap_ptr_gen(ira, scope, source_node, base_ptr, false,
15906 initializing, result_type);15906 initializing, result_type);
...@@ -15935,10 +15935,10 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop...@@ -15935,10 +15935,10 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop
15935 initializing, result_type);15935 initializing, result_type);
15936}15936}
1593715937
15938static IrInstGen *ir_analyze_instruction_optional_unwrap_ptr(IrAnalyze *ira,15938static Stage1AirInst *ir_analyze_instruction_optional_unwrap_ptr(IrAnalyze *ira,
15939 IrInstSrcOptionalUnwrapPtr *instruction)15939 Stage1ZirInstOptionalUnwrapPtr *instruction)
15940{15940{
15941 IrInstGen *base_ptr = instruction->base_ptr->child;15941 Stage1AirInst *base_ptr = instruction->base_ptr->child;
15942 if (type_is_invalid(base_ptr->value->type))15942 if (type_is_invalid(base_ptr->value->type))
15943 return ira->codegen->invalid_inst_gen;15943 return ira->codegen->invalid_inst_gen;
1594415944
...@@ -15946,12 +15946,12 @@ static IrInstGen *ir_analyze_instruction_optional_unwrap_ptr(IrAnalyze *ira,...@@ -15946,12 +15946,12 @@ static IrInstGen *ir_analyze_instruction_optional_unwrap_ptr(IrAnalyze *ira,
15946 instruction->safety_check_on, false);15946 instruction->safety_check_on, false);
15947}15947}
1594815948
15949static IrInstGen *ir_analyze_instruction_ctz(IrAnalyze *ira, IrInstSrcCtz *instruction) {15949static Stage1AirInst *ir_analyze_instruction_ctz(IrAnalyze *ira, Stage1ZirInstCtz *instruction) {
15950 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);15950 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
15951 if (type_is_invalid(int_type))15951 if (type_is_invalid(int_type))
15952 return ira->codegen->invalid_inst_gen;15952 return ira->codegen->invalid_inst_gen;
1595315953
15954 IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type);15954 Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type);
15955 if (type_is_invalid(op->value->type))15955 if (type_is_invalid(op->value->type))
15956 return ira->codegen->invalid_inst_gen;15956 return ira->codegen->invalid_inst_gen;
1595715957
...@@ -15972,12 +15972,12 @@ static IrInstGen *ir_analyze_instruction_ctz(IrAnalyze *ira, IrInstSrcCtz *instr...@@ -15972,12 +15972,12 @@ static IrInstGen *ir_analyze_instruction_ctz(IrAnalyze *ira, IrInstSrcCtz *instr
15972 return ir_build_ctz_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op);15972 return ir_build_ctz_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op);
15973}15973}
1597415974
15975static IrInstGen *ir_analyze_instruction_clz(IrAnalyze *ira, IrInstSrcClz *instruction) {15975static Stage1AirInst *ir_analyze_instruction_clz(IrAnalyze *ira, Stage1ZirInstClz *instruction) {
15976 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);15976 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
15977 if (type_is_invalid(int_type))15977 if (type_is_invalid(int_type))
15978 return ira->codegen->invalid_inst_gen;15978 return ira->codegen->invalid_inst_gen;
1597915979
15980 IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type);15980 Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type);
15981 if (type_is_invalid(op->value->type))15981 if (type_is_invalid(op->value->type))
15982 return ira->codegen->invalid_inst_gen;15982 return ira->codegen->invalid_inst_gen;
1598315983
...@@ -15998,12 +15998,12 @@ static IrInstGen *ir_analyze_instruction_clz(IrAnalyze *ira, IrInstSrcClz *instr...@@ -15998,12 +15998,12 @@ static IrInstGen *ir_analyze_instruction_clz(IrAnalyze *ira, IrInstSrcClz *instr
15998 return ir_build_clz_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op);15998 return ir_build_clz_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op);
15999}15999}
1600016000
16001static IrInstGen *ir_analyze_instruction_pop_count(IrAnalyze *ira, IrInstSrcPopCount *instruction) {16001static Stage1AirInst *ir_analyze_instruction_pop_count(IrAnalyze *ira, Stage1ZirInstPopCount *instruction) {
16002 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);16002 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
16003 if (type_is_invalid(int_type))16003 if (type_is_invalid(int_type))
16004 return ira->codegen->invalid_inst_gen;16004 return ira->codegen->invalid_inst_gen;
1600516005
16006 IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type);16006 Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type);
16007 if (type_is_invalid(op->value->type))16007 if (type_is_invalid(op->value->type))
16008 return ira->codegen->invalid_inst_gen;16008 return ira->codegen->invalid_inst_gen;
1600916009
...@@ -16029,7 +16029,7 @@ static IrInstGen *ir_analyze_instruction_pop_count(IrAnalyze *ira, IrInstSrcPopC...@@ -16029,7 +16029,7 @@ static IrInstGen *ir_analyze_instruction_pop_count(IrAnalyze *ira, IrInstSrcPopC
16029 return ir_build_pop_count_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op);16029 return ir_build_pop_count_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op);
16030}16030}
1603116031
16032static IrInstGen *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) {16032static Stage1AirInst *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) {
16033 if (type_is_invalid(value->value->type))16033 if (type_is_invalid(value->value->type))
16034 return ira->codegen->invalid_inst_gen;16034 return ira->codegen->invalid_inst_gen;
1603516035
...@@ -16055,7 +16055,7 @@ static IrInstGen *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -16055,7 +16055,7 @@ static IrInstGen *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *so
16055 if (!val)16055 if (!val)
16056 return ira->codegen->invalid_inst_gen;16056 return ira->codegen->invalid_inst_gen;
1605716057
16058 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,16058 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
16059 scope, source_node);16059 scope, source_node);
16060 const_instruction->base.value->type = tag_type;16060 const_instruction->base.value->type = tag_type;
16061 const_instruction->base.value->special = ConstValSpecialStatic;16061 const_instruction->base.value->special = ConstValSpecialStatic;
...@@ -16066,10 +16066,10 @@ static IrInstGen *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *so...@@ -16066,10 +16066,10 @@ static IrInstGen *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *so
16066 return ir_build_union_tag(ira, scope, source_node, value, tag_type);16066 return ir_build_union_tag(ira, scope, source_node, value, tag_type);
16067}16067}
1606816068
16069static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,16069static Stage1AirInst *ir_analyze_instruction_switch_br(IrAnalyze *ira,
16070 IrInstSrcSwitchBr *switch_br_instruction)16070 Stage1ZirInstSwitchBr *switch_br_instruction)
16071{16071{
16072 IrInstGen *target_value = switch_br_instruction->target_value->child;16072 Stage1AirInst *target_value = switch_br_instruction->target_value->child;
16073 if (type_is_invalid(target_value->value->type))16073 if (type_is_invalid(target_value->value->type))
16074 return ir_unreach_error(ira);16074 return ir_unreach_error(ira);
1607516075
...@@ -16093,12 +16093,12 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,...@@ -16093,12 +16093,12 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,
1609316093
16094 Stage1ZirBasicBlock *old_dest_block = switch_br_instruction->else_block;16094 Stage1ZirBasicBlock *old_dest_block = switch_br_instruction->else_block;
16095 for (size_t i = 0; i < case_count; i += 1) {16095 for (size_t i = 0; i < case_count; i += 1) {
16096 IrInstSrcSwitchBrCase *old_case = &switch_br_instruction->cases[i];16096 Stage1ZirInstSwitchBrCase *old_case = &switch_br_instruction->cases[i];
16097 IrInstGen *case_value = old_case->value->child;16097 Stage1AirInst *case_value = old_case->value->child;
16098 if (type_is_invalid(case_value->value->type))16098 if (type_is_invalid(case_value->value->type))
16099 return ir_unreach_error(ira);16099 return ir_unreach_error(ira);
1610016100
16101 IrInstGen *casted_case_value = ir_implicit_cast(ira, case_value, target_value->value->type);16101 Stage1AirInst *casted_case_value = ir_implicit_cast(ira, case_value, target_value->value->type);
16102 if (type_is_invalid(casted_case_value->value->type))16102 if (type_is_invalid(casted_case_value->value->type))
16103 return ir_unreach_error(ira);16103 return ir_unreach_error(ira);
1610416104
...@@ -16115,17 +16115,17 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,...@@ -16115,17 +16115,17 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,
16115 if (is_comptime || old_dest_block->ref_count == 1) {16115 if (is_comptime || old_dest_block->ref_count == 1) {
16116 return ir_inline_bb(ira, switch_br_instruction->base.source_node, old_dest_block);16116 return ir_inline_bb(ira, switch_br_instruction->base.source_node, old_dest_block);
16117 } else {16117 } else {
16118 IrBasicBlockGen *new_dest_block = ir_get_new_bb(ira, old_dest_block, &switch_br_instruction->base);16118 Stage1AirBasicBlock *new_dest_block = ir_get_new_bb(ira, old_dest_block, &switch_br_instruction->base);
16119 IrInstGen *result = ir_build_br_gen(ira, switch_br_instruction->base.scope,16119 Stage1AirInst *result = ir_build_br_gen(ira, switch_br_instruction->base.scope,
16120 switch_br_instruction->base.source_node, new_dest_block);16120 switch_br_instruction->base.source_node, new_dest_block);
16121 return ir_finish_anal(ira, result);16121 return ir_finish_anal(ira, result);
16122 }16122 }
16123 }16123 }
1612416124
16125 IrInstGenSwitchBrCase *cases = heap::c_allocator.allocate<IrInstGenSwitchBrCase>(case_count);16125 Stage1AirInstSwitchBrCase *cases = heap::c_allocator.allocate<Stage1AirInstSwitchBrCase>(case_count);
16126 for (size_t i = 0; i < case_count; i += 1) {16126 for (size_t i = 0; i < case_count; i += 1) {
16127 IrInstSrcSwitchBrCase *old_case = &switch_br_instruction->cases[i];16127 Stage1ZirInstSwitchBrCase *old_case = &switch_br_instruction->cases[i];
16128 IrInstGenSwitchBrCase *new_case = &cases[i];16128 Stage1AirInstSwitchBrCase *new_case = &cases[i];
16129 new_case->block = ir_get_new_bb(ira, old_case->block, &switch_br_instruction->base);16129 new_case->block = ir_get_new_bb(ira, old_case->block, &switch_br_instruction->base);
16130 new_case->value = ira->codegen->invalid_inst_gen;16130 new_case->value = ira->codegen->invalid_inst_gen;
1613116131
...@@ -16135,12 +16135,12 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,...@@ -16135,12 +16135,12 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,
16135 // it back after the loop.16135 // it back after the loop.
16136 new_case->block->ref_instruction = nullptr;16136 new_case->block->ref_instruction = nullptr;
1613716137
16138 IrInstSrc *old_value = old_case->value;16138 Stage1ZirInst *old_value = old_case->value;
16139 IrInstGen *new_value = old_value->child;16139 Stage1AirInst *new_value = old_value->child;
16140 if (type_is_invalid(new_value->value->type))16140 if (type_is_invalid(new_value->value->type))
16141 continue;16141 continue;
1614216142
16143 IrInstGen *casted_new_value = ir_implicit_cast(ira, new_value, target_value->value->type);16143 Stage1AirInst *casted_new_value = ir_implicit_cast(ira, new_value, target_value->value->type);
16144 if (type_is_invalid(casted_new_value->value->type))16144 if (type_is_invalid(casted_new_value->value->type))
16145 continue;16145 continue;
1614616146
...@@ -16151,23 +16151,23 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,...@@ -16151,23 +16151,23 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,
16151 }16151 }
1615216152
16153 for (size_t i = 0; i < case_count; i += 1) {16153 for (size_t i = 0; i < case_count; i += 1) {
16154 IrInstGenSwitchBrCase *new_case = &cases[i];16154 Stage1AirInstSwitchBrCase *new_case = &cases[i];
16155 if (type_is_invalid(new_case->value->value->type))16155 if (type_is_invalid(new_case->value->value->type))
16156 return ir_unreach_error(ira);16156 return ir_unreach_error(ira);
16157 new_case->block->ref_instruction = &switch_br_instruction->base;16157 new_case->block->ref_instruction = &switch_br_instruction->base;
16158 }16158 }
1615916159
16160 IrBasicBlockGen *new_else_block = ir_get_new_bb(ira, switch_br_instruction->else_block, &switch_br_instruction->base);16160 Stage1AirBasicBlock *new_else_block = ir_get_new_bb(ira, switch_br_instruction->else_block, &switch_br_instruction->base);
16161 IrInstGenSwitchBr *switch_br = ir_build_switch_br_gen(ira, switch_br_instruction->base.scope,16161 Stage1AirInstSwitchBr *switch_br = ir_build_switch_br_gen(ira, switch_br_instruction->base.scope,
16162 switch_br_instruction->base.source_node, target_value, new_else_block, case_count, cases);16162 switch_br_instruction->base.source_node, target_value, new_else_block, case_count, cases);
16163 return ir_finish_anal(ira, &switch_br->base);16163 return ir_finish_anal(ira, &switch_br->base);
16164}16164}
1616516165
16166static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,16166static Stage1AirInst *ir_analyze_instruction_switch_target(IrAnalyze *ira,
16167 IrInstSrcSwitchTarget *switch_target_instruction)16167 Stage1ZirInstSwitchTarget *switch_target_instruction)
16168{16168{
16169 Error err;16169 Error err;
16170 IrInstGen *target_value_ptr = switch_target_instruction->target_value_ptr->child;16170 Stage1AirInst *target_value_ptr = switch_target_instruction->target_value_ptr->child;
16171 if (type_is_invalid(target_value_ptr->value->type))16171 if (type_is_invalid(target_value_ptr->value->type))
16172 return ira->codegen->invalid_inst_gen;16172 return ira->codegen->invalid_inst_gen;
1617316173
...@@ -16207,14 +16207,14 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,...@@ -16207,14 +16207,14 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,
16207 case ZigTypeIdFn:16207 case ZigTypeIdFn:
16208 case ZigTypeIdErrorSet: {16208 case ZigTypeIdErrorSet: {
16209 if (pointee_val) {16209 if (pointee_val) {
16210 IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope,16210 Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope,
16211 switch_target_instruction->base.source_node, nullptr);16211 switch_target_instruction->base.source_node, nullptr);
16212 copy_const_val(ira->codegen, result->value, pointee_val);16212 copy_const_val(ira->codegen, result->value, pointee_val);
16213 result->value->type = target_type;16213 result->value->type = target_type;
16214 return result;16214 return result;
16215 }16215 }
1621616216
16217 IrInstGen *result = ir_get_deref(ira, switch_target_instruction->base.scope,16217 Stage1AirInst *result = ir_get_deref(ira, switch_target_instruction->base.scope,
16218 switch_target_instruction->base.source_node, target_value_ptr, nullptr);16218 switch_target_instruction->base.source_node, target_value_ptr, nullptr);
16219 result->value->type = target_type;16219 result->value->type = target_type;
16220 return result;16220 return result;
...@@ -16234,19 +16234,19 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,...@@ -16234,19 +16234,19 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,
16234 assert(tag_type != nullptr);16234 assert(tag_type != nullptr);
16235 assert(tag_type->id == ZigTypeIdEnum);16235 assert(tag_type->id == ZigTypeIdEnum);
16236 if (pointee_val) {16236 if (pointee_val) {
16237 IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type);16237 Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type);
16238 bigint_init_bigint(&result->value->data.x_enum_tag, &pointee_val->data.x_union.tag);16238 bigint_init_bigint(&result->value->data.x_enum_tag, &pointee_val->data.x_union.tag);
16239 return result;16239 return result;
16240 }16240 }
1624116241
16242 if (can_fold_enum_type(tag_type)) {16242 if (can_fold_enum_type(tag_type)) {
16243 IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type);16243 Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type);
16244 TypeEnumField *only_field = &tag_type->data.enumeration.fields[0];16244 TypeEnumField *only_field = &tag_type->data.enumeration.fields[0];
16245 bigint_init_bigint(&result->value->data.x_enum_tag, &only_field->value);16245 bigint_init_bigint(&result->value->data.x_enum_tag, &only_field->value);
16246 return result;16246 return result;
16247 }16247 }
1624816248
16249 IrInstGen *union_value = ir_get_deref(ira, switch_target_instruction->base.scope,16249 Stage1AirInst *union_value = ir_get_deref(ira, switch_target_instruction->base.scope,
16250 switch_target_instruction->base.source_node, target_value_ptr, nullptr);16250 switch_target_instruction->base.source_node, target_value_ptr, nullptr);
16251 union_value->value->type = target_type;16251 union_value->value->type = target_type;
1625216252
...@@ -16258,18 +16258,18 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,...@@ -16258,18 +16258,18 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,
1625816258
16259 if (can_fold_enum_type(target_type)) {16259 if (can_fold_enum_type(target_type)) {
16260 TypeEnumField *only_field = &target_type->data.enumeration.fields[0];16260 TypeEnumField *only_field = &target_type->data.enumeration.fields[0];
16261 IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type);16261 Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type);
16262 bigint_init_bigint(&result->value->data.x_enum_tag, &only_field->value);16262 bigint_init_bigint(&result->value->data.x_enum_tag, &only_field->value);
16263 return result;16263 return result;
16264 }16264 }
1626516265
16266 if (pointee_val) {16266 if (pointee_val) {
16267 IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type);16267 Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type);
16268 bigint_init_bigint(&result->value->data.x_enum_tag, &pointee_val->data.x_enum_tag);16268 bigint_init_bigint(&result->value->data.x_enum_tag, &pointee_val->data.x_enum_tag);
16269 return result;16269 return result;
16270 }16270 }
1627116271
16272 IrInstGen *enum_value = ir_get_deref(ira, switch_target_instruction->base.scope,16272 Stage1AirInst *enum_value = ir_get_deref(ira, switch_target_instruction->base.scope,
16273 switch_target_instruction->base.source_node, target_value_ptr, nullptr);16273 switch_target_instruction->base.source_node, target_value_ptr, nullptr);
16274 enum_value->value->type = target_type;16274 enum_value->value->type = target_type;
16275 return enum_value;16275 return enum_value;
...@@ -16293,8 +16293,8 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,...@@ -16293,8 +16293,8 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,
16293 zig_unreachable();16293 zig_unreachable();
16294}16294}
1629516295
16296static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwitchVar *instruction) {16296static Stage1AirInst *ir_analyze_instruction_switch_var(IrAnalyze *ira, Stage1ZirInstSwitchVar *instruction) {
16297 IrInstGen *target_value_ptr = instruction->target_value_ptr->child;16297 Stage1AirInst *target_value_ptr = instruction->target_value_ptr->child;
16298 if (type_is_invalid(target_value_ptr->value->type))16298 if (type_is_invalid(target_value_ptr->value->type))
16299 return ira->codegen->invalid_inst_gen;16299 return ira->codegen->invalid_inst_gen;
1630016300
...@@ -16307,11 +16307,11 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi...@@ -16307,11 +16307,11 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi
16307 assert(enum_type->id == ZigTypeIdEnum);16307 assert(enum_type->id == ZigTypeIdEnum);
16308 assert(instruction->prongs_len > 0);16308 assert(instruction->prongs_len > 0);
1630916309
16310 IrInstGen *first_prong_value = instruction->prongs_ptr[0]->child;16310 Stage1AirInst *first_prong_value = instruction->prongs_ptr[0]->child;
16311 if (type_is_invalid(first_prong_value->value->type))16311 if (type_is_invalid(first_prong_value->value->type))
16312 return ira->codegen->invalid_inst_gen;16312 return ira->codegen->invalid_inst_gen;
1631316313
16314 IrInstGen *first_casted_prong_value = ir_implicit_cast(ira, first_prong_value, enum_type);16314 Stage1AirInst *first_casted_prong_value = ir_implicit_cast(ira, first_prong_value, enum_type);
16315 if (type_is_invalid(first_casted_prong_value->value->type))16315 if (type_is_invalid(first_casted_prong_value->value->type))
16316 return ira->codegen->invalid_inst_gen;16316 return ira->codegen->invalid_inst_gen;
1631716317
...@@ -16323,11 +16323,11 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi...@@ -16323,11 +16323,11 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi
1632316323
16324 ErrorMsg *invalid_payload_msg = nullptr;16324 ErrorMsg *invalid_payload_msg = nullptr;
16325 for (size_t prong_i = 1; prong_i < instruction->prongs_len; prong_i += 1) {16325 for (size_t prong_i = 1; prong_i < instruction->prongs_len; prong_i += 1) {
16326 IrInstGen *this_prong_inst = instruction->prongs_ptr[prong_i]->child;16326 Stage1AirInst *this_prong_inst = instruction->prongs_ptr[prong_i]->child;
16327 if (type_is_invalid(this_prong_inst->value->type))16327 if (type_is_invalid(this_prong_inst->value->type))
16328 return ira->codegen->invalid_inst_gen;16328 return ira->codegen->invalid_inst_gen;
1632916329
16330 IrInstGen *this_casted_prong_value = ir_implicit_cast(ira, this_prong_inst, enum_type);16330 Stage1AirInst *this_casted_prong_value = ir_implicit_cast(ira, this_prong_inst, enum_type);
16331 if (type_is_invalid(this_casted_prong_value->value->type))16331 if (type_is_invalid(this_casted_prong_value->value->type))
16332 return ira->codegen->invalid_inst_gen;16332 return ira->codegen->invalid_inst_gen;
1633316333
...@@ -16362,7 +16362,7 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi...@@ -16362,7 +16362,7 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi
16362 if (pointee_val == nullptr)16362 if (pointee_val == nullptr)
16363 return ira->codegen->invalid_inst_gen;16363 return ira->codegen->invalid_inst_gen;
1636416364
16365 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node,16365 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node,
16366 get_pointer_to_type(ira->codegen, first_field->type_entry,16366 get_pointer_to_type(ira->codegen, first_field->type_entry,
16367 target_val_ptr->type->data.pointer.is_const));16367 target_val_ptr->type->data.pointer.is_const));
16368 ZigValue *out_val = result->value;16368 ZigValue *out_val = result->value;
...@@ -16416,10 +16416,10 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi...@@ -16416,10 +16416,10 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi
16416 }16416 }
16417}16417}
1641816418
16419static IrInstGen *ir_analyze_instruction_switch_else_var(IrAnalyze *ira,16419static Stage1AirInst *ir_analyze_instruction_switch_else_var(IrAnalyze *ira,
16420 IrInstSrcSwitchElseVar *instruction)16420 Stage1ZirInstSwitchElseVar *instruction)
16421{16421{
16422 IrInstGen *target_value_ptr = instruction->target_value_ptr->child;16422 Stage1AirInst *target_value_ptr = instruction->target_value_ptr->child;
16423 if (type_is_invalid(target_value_ptr->value->type))16423 if (type_is_invalid(target_value_ptr->value->type))
16424 return ira->codegen->invalid_inst_gen;16424 return ira->codegen->invalid_inst_gen;
1642516425
...@@ -16441,8 +16441,8 @@ static IrInstGen *ir_analyze_instruction_switch_else_var(IrAnalyze *ira,...@@ -16441,8 +16441,8 @@ static IrInstGen *ir_analyze_instruction_switch_else_var(IrAnalyze *ira,
16441 // We may not have any case in the switch if this is a lone else16441 // We may not have any case in the switch if this is a lone else
16442 const size_t switch_cases = instruction->switch_br ? instruction->switch_br->case_count : 0;16442 const size_t switch_cases = instruction->switch_br ? instruction->switch_br->case_count : 0;
16443 for (size_t case_i = 0; case_i < switch_cases; case_i += 1) {16443 for (size_t case_i = 0; case_i < switch_cases; case_i += 1) {
16444 IrInstSrcSwitchBrCase *br_case = &instruction->switch_br->cases[case_i];16444 Stage1ZirInstSwitchBrCase *br_case = &instruction->switch_br->cases[case_i];
16445 IrInstGen *case_expr = br_case->value->child;16445 Stage1AirInst *case_expr = br_case->value->child;
16446 if (case_expr->value->type->id == ZigTypeIdErrorSet) {16446 if (case_expr->value->type->id == ZigTypeIdErrorSet) {
16447 ErrorTableEntry *err = ir_resolve_error(ira, case_expr);16447 ErrorTableEntry *err = ir_resolve_error(ira, case_expr);
16448 if (err == nullptr)16448 if (err == nullptr)
...@@ -16498,10 +16498,10 @@ static IrInstGen *ir_analyze_instruction_switch_else_var(IrAnalyze *ira,...@@ -16498,10 +16498,10 @@ static IrInstGen *ir_analyze_instruction_switch_else_var(IrAnalyze *ira,
16498 return target_value_ptr;16498 return target_value_ptr;
16499}16499}
1650016500
16501static IrInstGen *ir_analyze_instruction_import(IrAnalyze *ira, IrInstSrcImport *import_instruction) {16501static Stage1AirInst *ir_analyze_instruction_import(IrAnalyze *ira, Stage1ZirInstImport *import_instruction) {
16502 Error err;16502 Error err;
1650316503
16504 IrInstGen *name_value = import_instruction->name->child;16504 Stage1AirInst *name_value = import_instruction->name->child;
16505 Buf *import_target_str = ir_resolve_str(ira, name_value);16505 Buf *import_target_str = ir_resolve_str(ira, name_value);
16506 if (!import_target_str)16506 if (!import_target_str)
16507 return ira->codegen->invalid_inst_gen;16507 return ira->codegen->invalid_inst_gen;
...@@ -16534,8 +16534,8 @@ static IrInstGen *ir_analyze_instruction_import(IrAnalyze *ira, IrInstSrcImport...@@ -16534,8 +16534,8 @@ static IrInstGen *ir_analyze_instruction_import(IrAnalyze *ira, IrInstSrcImport
16534 return ir_const_type(ira, import_instruction->base.scope, import_instruction->base.source_node, target_import);16534 return ir_const_type(ira, import_instruction->base.scope, import_instruction->base.source_node, target_import);
16535}16535}
1653616536
16537static IrInstGen *ir_analyze_instruction_ref(IrAnalyze *ira, IrInstSrcRef *ref_instruction) {16537static Stage1AirInst *ir_analyze_instruction_ref(IrAnalyze *ira, Stage1ZirInstRef *ref_instruction) {
16538 IrInstGen *value = ref_instruction->value->child;16538 Stage1AirInst *value = ref_instruction->value->child;
16539 if (type_is_invalid(value->value->type))16539 if (type_is_invalid(value->value->type))
16540 return ira->codegen->invalid_inst_gen;16540 return ira->codegen->invalid_inst_gen;
1654116541
...@@ -16550,9 +16550,9 @@ static IrInstGen *ir_analyze_instruction_ref(IrAnalyze *ira, IrInstSrcRef *ref_i...@@ -16550,9 +16550,9 @@ static IrInstGen *ir_analyze_instruction_ref(IrAnalyze *ira, IrInstSrcRef *ref_i
16550 return ir_get_ref(ira, ref_instruction->base.scope, ref_instruction->base.source_node, value, is_const, is_volatile);16550 return ir_get_ref(ira, ref_instruction->base.scope, ref_instruction->base.source_node, value, is_const, is_volatile);
16551}16551}
1655216552
16553static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node,16553static Stage1AirInst *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node,
16554 AstNode *field_source_node, ZigType *union_type, Buf *field_name, IrInstGen *field_result_loc,16554 AstNode *field_source_node, ZigType *union_type, Buf *field_name, Stage1AirInst *field_result_loc,
16555 IrInstGen *result_loc)16555 Stage1AirInst *result_loc)
16556{16556{
16557 Error err;16557 Error err;
16558 assert(union_type->id == ZigTypeIdUnion);16558 assert(union_type->id == ZigTypeIdUnion);
...@@ -16584,7 +16584,7 @@ static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -16584,7 +16584,7 @@ static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *s
16584 bool is_comptime = ir_should_inline(ira->zir, scope)16584 bool is_comptime = ir_should_inline(ira->zir, scope)
16585 || type_requires_comptime(ira->codegen, union_type) == ReqCompTimeYes;16585 || type_requires_comptime(ira->codegen, union_type) == ReqCompTimeYes;
1658616586
16587 IrInstGen *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr);16587 Stage1AirInst *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr);
16588 if (is_comptime && !instr_is_comptime(result)) {16588 if (is_comptime && !instr_is_comptime(result)) {
16589 ir_add_error(ira, field_result_loc,16589 ir_add_error(ira, field_result_loc,
16590 buf_sprintf("unable to evaluate constant expression"));16590 buf_sprintf("unable to evaluate constant expression"));
...@@ -16593,9 +16593,9 @@ static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -16593,9 +16593,9 @@ static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *s
16593 return result;16593 return result;
16594}16594}
1659516595
16596static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, AstNode *source_node,16596static Stage1AirInst *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, AstNode *source_node,
16597 ZigType *container_type, size_t instr_field_count, IrInstSrcContainerInitFieldsField *fields,16597 ZigType *container_type, size_t instr_field_count, Stage1ZirInstContainerInitFieldsField *fields,
16598 IrInstGen *result_loc)16598 Stage1AirInst *result_loc)
16599{16599{
16600 Error err;16600 Error err;
16601 if (container_type->id == ZigTypeIdUnion) {16601 if (container_type->id == ZigTypeIdUnion) {
...@@ -16604,8 +16604,8 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,...@@ -16604,8 +16604,8 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
16604 buf_sprintf("union initialization expects exactly one field"));16604 buf_sprintf("union initialization expects exactly one field"));
16605 return ira->codegen->invalid_inst_gen;16605 return ira->codegen->invalid_inst_gen;
16606 }16606 }
16607 IrInstSrcContainerInitFieldsField *field = &fields[0];16607 Stage1ZirInstContainerInitFieldsField *field = &fields[0];
16608 IrInstGen *field_result_loc = field->result_loc->child;16608 Stage1AirInst *field_result_loc = field->result_loc->child;
16609 if (type_is_invalid(field_result_loc->value->type))16609 if (type_is_invalid(field_result_loc->value->type))
16610 return ira->codegen->invalid_inst_gen;16610 return ira->codegen->invalid_inst_gen;
1661116611
...@@ -16629,10 +16629,10 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,...@@ -16629,10 +16629,10 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
1662916629
16630 size_t actual_field_count = container_type->data.structure.src_field_count;16630 size_t actual_field_count = container_type->data.structure.src_field_count;
1663116631
16632 IrInstGen *first_non_const_instruction = nullptr;16632 Stage1AirInst *first_non_const_instruction = nullptr;
1663316633
16634 AstNode **field_assign_nodes = heap::c_allocator.allocate<AstNode *>(actual_field_count);16634 AstNode **field_assign_nodes = heap::c_allocator.allocate<AstNode *>(actual_field_count);
16635 ZigList<IrInstGen *> const_ptrs = {};16635 ZigList<Stage1AirInst *> const_ptrs = {};
1663616636
16637 bool is_comptime = ir_should_inline(ira->zir, scope)16637 bool is_comptime = ir_should_inline(ira->zir, scope)
16638 || type_requires_comptime(ira->codegen, container_type) == ReqCompTimeYes;16638 || type_requires_comptime(ira->codegen, container_type) == ReqCompTimeYes;
...@@ -16650,9 +16650,9 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,...@@ -16650,9 +16650,9 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
16650 // comptime-known values.16650 // comptime-known values.
1665116651
16652 for (size_t i = 0; i < instr_field_count; i += 1) {16652 for (size_t i = 0; i < instr_field_count; i += 1) {
16653 IrInstSrcContainerInitFieldsField *field = &fields[i];16653 Stage1ZirInstContainerInitFieldsField *field = &fields[i];
1665416654
16655 IrInstGen *field_result_loc = field->result_loc->child;16655 Stage1AirInst *field_result_loc = field->result_loc->child;
16656 if (type_is_invalid(field_result_loc->value->type))16656 if (type_is_invalid(field_result_loc->value->type))
16657 return ira->codegen->invalid_inst_gen;16657 return ira->codegen->invalid_inst_gen;
1665816658
...@@ -16701,10 +16701,10 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,...@@ -16701,10 +16701,10 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
16701 if (type_is_invalid(field->init_val->type))16701 if (type_is_invalid(field->init_val->type))
16702 return ira->codegen->invalid_inst_gen;16702 return ira->codegen->invalid_inst_gen;
1670316703
16704 IrInstGen *runtime_inst = ir_const(ira, scope, source_node, field->init_val->type);16704 Stage1AirInst *runtime_inst = ir_const(ira, scope, source_node, field->init_val->type);
16705 copy_const_val(ira->codegen, runtime_inst->value, field->init_val);16705 copy_const_val(ira->codegen, runtime_inst->value, field->init_val);
1670616706
16707 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc,16707 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc,
16708 container_type, true);16708 container_type, true);
16709 ir_analyze_store_ptr(ira, scope, source_node, field_ptr, runtime_inst, false);16709 ir_analyze_store_ptr(ira, scope, source_node, field_ptr, runtime_inst, false);
16710 if (instr_is_comptime(field_ptr) && field_ptr->value->data.x_ptr.mut != ConstPtrMutRuntimeVar) {16710 if (instr_is_comptime(field_ptr) && field_ptr->value->data.x_ptr.mut != ConstPtrMutRuntimeVar) {
...@@ -16721,8 +16721,8 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,...@@ -16721,8 +16721,8 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
16721 if (const_ptrs.length != actual_field_count) {16721 if (const_ptrs.length != actual_field_count) {
16722 result_loc->value->special = ConstValSpecialRuntime;16722 result_loc->value->special = ConstValSpecialRuntime;
16723 for (size_t i = 0; i < const_ptrs.length; i += 1) {16723 for (size_t i = 0; i < const_ptrs.length; i += 1) {
16724 IrInstGen *field_result_loc = const_ptrs.at(i);16724 Stage1AirInst *field_result_loc = const_ptrs.at(i);
16725 IrInstGen *deref = ir_get_deref(ira, field_result_loc->scope,16725 Stage1AirInst *deref = ir_get_deref(ira, field_result_loc->scope,
16726 field_result_loc->source_node, field_result_loc, nullptr);16726 field_result_loc->source_node, field_result_loc, nullptr);
16727 field_result_loc->value->special = ConstValSpecialRuntime;16727 field_result_loc->value->special = ConstValSpecialRuntime;
16728 ir_analyze_store_ptr(ira, field_result_loc->scope, field_result_loc->source_node,16728 ir_analyze_store_ptr(ira, field_result_loc->scope, field_result_loc->source_node,
...@@ -16732,7 +16732,7 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,...@@ -16732,7 +16732,7 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
16732 }16732 }
1673316733
16734 const_ptrs.deinit();16734 const_ptrs.deinit();
16735 IrInstGen *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr);16735 Stage1AirInst *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr);
1673616736
16737 if (is_comptime && !instr_is_comptime(result)) {16737 if (is_comptime && !instr_is_comptime(result)) {
16738 ir_add_error_node(ira, first_non_const_instruction->source_node,16738 ir_add_error_node(ira, first_non_const_instruction->source_node,
...@@ -16743,11 +16743,11 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,...@@ -16743,11 +16743,11 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
16743 return result;16743 return result;
16744}16744}
1674516745
16746static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,16746static Stage1AirInst *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
16747 IrInstSrcContainerInitList *instruction)16747 Stage1ZirInstContainerInitList *instruction)
16748{16748{
16749 src_assert(instruction->result_loc != nullptr, instruction->base.source_node);16749 src_assert(instruction->result_loc != nullptr, instruction->base.source_node);
16750 IrInstGen *result_loc = instruction->result_loc->child;16750 Stage1AirInst *result_loc = instruction->result_loc->child;
16751 if (type_is_invalid(result_loc->value->type))16751 if (type_is_invalid(result_loc->value->type))
16752 return result_loc;16752 return result_loc;
1675316753
...@@ -16778,7 +16778,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,...@@ -16778,7 +16778,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
1677816778
16779 if (container_type->id == ZigTypeIdStruct && elem_count == 0) {16779 if (container_type->id == ZigTypeIdStruct && elem_count == 0) {
16780 src_assert(instruction->result_loc != nullptr, instruction->base.source_node);16780 src_assert(instruction->result_loc != nullptr, instruction->base.source_node);
16781 IrInstGen *result_loc = instruction->result_loc->child;16781 Stage1AirInst *result_loc = instruction->result_loc->child;
16782 if (type_is_invalid(result_loc->value->type))16782 if (type_is_invalid(result_loc->value->type))
16783 return result_loc;16783 return result_loc;
16784 return ir_analyze_container_init_fields(ira, instruction->base.scope, instruction->base.source_node, container_type, 0, nullptr, result_loc);16784 return ir_analyze_container_init_fields(ira, instruction->base.scope, instruction->base.source_node, container_type, 0, nullptr, result_loc);
...@@ -16830,7 +16830,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,...@@ -16830,7 +16830,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
16830 break;16830 break;
16831 }16831 }
1683216832
16833 IrInstGen *first_non_const_instruction = nullptr;16833 Stage1AirInst *first_non_const_instruction = nullptr;
1683416834
16835 // The Result Location Mechanism has already emitted runtime instructions to16835 // The Result Location Mechanism has already emitted runtime instructions to
16836 // initialize runtime elements and has omitted instructions for the comptime16836 // initialize runtime elements and has omitted instructions for the comptime
...@@ -16839,10 +16839,10 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,...@@ -16839,10 +16839,10 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
16839 // array initialization can be a comptime value, overwrite ConstPtrMutInfer with16839 // array initialization can be a comptime value, overwrite ConstPtrMutInfer with
16840 // ConstPtrMutComptimeConst. Otherwise, emit instructions to runtime-initialize the16840 // ConstPtrMutComptimeConst. Otherwise, emit instructions to runtime-initialize the
16841 // elements that have comptime-known values.16841 // elements that have comptime-known values.
16842 ZigList<IrInstGen *> const_ptrs = {};16842 ZigList<Stage1AirInst *> const_ptrs = {};
1684316843
16844 for (size_t i = 0; i < elem_count; i += 1) {16844 for (size_t i = 0; i < elem_count; i += 1) {
16845 IrInstGen *elem_result_loc = instruction->elem_result_loc_list[i]->child;16845 Stage1AirInst *elem_result_loc = instruction->elem_result_loc_list[i]->child;
16846 if (type_is_invalid(elem_result_loc->value->type))16846 if (type_is_invalid(elem_result_loc->value->type))
16847 return ira->codegen->invalid_inst_gen;16847 return ira->codegen->invalid_inst_gen;
1684816848
...@@ -16861,13 +16861,13 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,...@@ -16861,13 +16861,13 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
16861 if (const_ptrs.length != elem_count) {16861 if (const_ptrs.length != elem_count) {
16862 result_loc->value->special = ConstValSpecialRuntime;16862 result_loc->value->special = ConstValSpecialRuntime;
16863 for (size_t i = 0; i < const_ptrs.length; i += 1) {16863 for (size_t i = 0; i < const_ptrs.length; i += 1) {
16864 IrInstGen *elem_result_loc = const_ptrs.at(i);16864 Stage1AirInst *elem_result_loc = const_ptrs.at(i);
16865 assert(elem_result_loc->value->special == ConstValSpecialStatic);16865 assert(elem_result_loc->value->special == ConstValSpecialStatic);
16866 if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) {16866 if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) {
16867 // This field will be generated comptime; no need to do this.16867 // This field will be generated comptime; no need to do this.
16868 continue;16868 continue;
16869 }16869 }
16870 IrInstGen *deref = ir_get_deref(ira, elem_result_loc->scope,16870 Stage1AirInst *deref = ir_get_deref(ira, elem_result_loc->scope,
16871 elem_result_loc->source_node, elem_result_loc, nullptr);16871 elem_result_loc->source_node, elem_result_loc, nullptr);
16872 elem_result_loc->value->special = ConstValSpecialRuntime;16872 elem_result_loc->value->special = ConstValSpecialRuntime;
16873 ir_analyze_store_ptr(ira, elem_result_loc->scope, elem_result_loc->source_node,16873 ir_analyze_store_ptr(ira, elem_result_loc->scope, elem_result_loc->source_node,
...@@ -16878,7 +16878,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,...@@ -16878,7 +16878,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
1687816878
16879 const_ptrs.deinit();16879 const_ptrs.deinit();
1688016880
16881 IrInstGen *result = ir_get_deref(ira, instruction->base.scope, instruction->base.source_node,16881 Stage1AirInst *result = ir_get_deref(ira, instruction->base.scope, instruction->base.source_node,
16882 result_loc, nullptr);16882 result_loc, nullptr);
16883 // If the result is a tuple, we are allowed to return a struct that uses ConstValSpecialRuntime fields at comptime.16883 // If the result is a tuple, we are allowed to return a struct that uses ConstValSpecialRuntime fields at comptime.
16884 if (instr_is_comptime(result) || is_tuple(container_type))16884 if (instr_is_comptime(result) || is_tuple(container_type))
...@@ -16902,11 +16902,11 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,...@@ -16902,11 +16902,11 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
16902 return result;16902 return result;
16903}16903}
1690416904
16905static IrInstGen *ir_analyze_instruction_container_init_fields(IrAnalyze *ira,16905static Stage1AirInst *ir_analyze_instruction_container_init_fields(IrAnalyze *ira,
16906 IrInstSrcContainerInitFields *instruction)16906 Stage1ZirInstContainerInitFields *instruction)
16907{16907{
16908 src_assert(instruction->result_loc != nullptr, instruction->base.source_node);16908 src_assert(instruction->result_loc != nullptr, instruction->base.source_node);
16909 IrInstGen *result_loc = instruction->result_loc->child;16909 Stage1AirInst *result_loc = instruction->result_loc->child;
16910 if (type_is_invalid(result_loc->value->type))16910 if (type_is_invalid(result_loc->value->type))
16911 return result_loc;16911 return result_loc;
1691216912
...@@ -16922,8 +16922,8 @@ static IrInstGen *ir_analyze_instruction_container_init_fields(IrAnalyze *ira,...@@ -16922,8 +16922,8 @@ static IrInstGen *ir_analyze_instruction_container_init_fields(IrAnalyze *ira,
16922 instruction->field_count, instruction->fields, result_loc);16922 instruction->field_count, instruction->fields, result_loc);
16923}16923}
1692416924
16925static IrInstGen *ir_analyze_instruction_compile_err(IrAnalyze *ira, IrInstSrcCompileErr *instruction) {16925static Stage1AirInst *ir_analyze_instruction_compile_err(IrAnalyze *ira, Stage1ZirInstCompileErr *instruction) {
16926 IrInstGen *msg_value = instruction->msg->child;16926 Stage1AirInst *msg_value = instruction->msg->child;
16927 Buf *msg_buf = ir_resolve_str(ira, msg_value);16927 Buf *msg_buf = ir_resolve_str(ira, msg_value);
16928 if (!msg_buf)16928 if (!msg_buf)
16929 return ira->codegen->invalid_inst_gen;16929 return ira->codegen->invalid_inst_gen;
...@@ -16933,11 +16933,11 @@ static IrInstGen *ir_analyze_instruction_compile_err(IrAnalyze *ira, IrInstSrcCo...@@ -16933,11 +16933,11 @@ static IrInstGen *ir_analyze_instruction_compile_err(IrAnalyze *ira, IrInstSrcCo
16933 return ira->codegen->invalid_inst_gen;16933 return ira->codegen->invalid_inst_gen;
16934}16934}
1693516935
16936static IrInstGen *ir_analyze_instruction_compile_log(IrAnalyze *ira, IrInstSrcCompileLog *instruction) {16936static Stage1AirInst *ir_analyze_instruction_compile_log(IrAnalyze *ira, Stage1ZirInstCompileLog *instruction) {
16937 Buf buf = BUF_INIT;16937 Buf buf = BUF_INIT;
16938 fprintf(stderr, "| ");16938 fprintf(stderr, "| ");
16939 for (size_t i = 0; i < instruction->msg_count; i += 1) {16939 for (size_t i = 0; i < instruction->msg_count; i += 1) {
16940 IrInstGen *msg = instruction->msg_list[i]->child;16940 Stage1AirInst *msg = instruction->msg_list[i]->child;
16941 if (type_is_invalid(msg->value->type))16941 if (type_is_invalid(msg->value->type))
16942 return ira->codegen->invalid_inst_gen;16942 return ira->codegen->invalid_inst_gen;
16943 buf_resize(&buf, 0);16943 buf_resize(&buf, 0);
...@@ -16963,12 +16963,12 @@ static IrInstGen *ir_analyze_instruction_compile_log(IrAnalyze *ira, IrInstSrcCo...@@ -16963,12 +16963,12 @@ static IrInstGen *ir_analyze_instruction_compile_log(IrAnalyze *ira, IrInstSrcCo
16963 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);16963 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
16964}16964}
1696516965
16966static IrInstGen *ir_analyze_instruction_err_name(IrAnalyze *ira, IrInstSrcErrName *instruction) {16966static Stage1AirInst *ir_analyze_instruction_err_name(IrAnalyze *ira, Stage1ZirInstErrName *instruction) {
16967 IrInstGen *value = instruction->value->child;16967 Stage1AirInst *value = instruction->value->child;
16968 if (type_is_invalid(value->value->type))16968 if (type_is_invalid(value->value->type))
16969 return ira->codegen->invalid_inst_gen;16969 return ira->codegen->invalid_inst_gen;
1697016970
16971 IrInstGen *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_global_error_set);16971 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_global_error_set);
16972 if (type_is_invalid(casted_value->value->type))16972 if (type_is_invalid(casted_value->value->type))
16973 return ira->codegen->invalid_inst_gen;16973 return ira->codegen->invalid_inst_gen;
1697416974
...@@ -16982,7 +16982,7 @@ static IrInstGen *ir_analyze_instruction_err_name(IrAnalyze *ira, IrInstSrcErrNa...@@ -16982,7 +16982,7 @@ static IrInstGen *ir_analyze_instruction_err_name(IrAnalyze *ira, IrInstSrcErrNa
16982 ira->codegen, &err->name,16982 ira->codegen, &err->name,
16983 ira->codegen->intern.for_zero_byte());16983 ira->codegen->intern.for_zero_byte());
16984 }16984 }
16985 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);16985 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
16986 result->value = err->cached_error_name_val;16986 result->value = err->cached_error_name_val;
16987 return result;16987 return result;
16988 }16988 }
...@@ -16996,16 +16996,16 @@ static IrInstGen *ir_analyze_instruction_err_name(IrAnalyze *ira, IrInstSrcErrNa...@@ -16996,16 +16996,16 @@ static IrInstGen *ir_analyze_instruction_err_name(IrAnalyze *ira, IrInstSrcErrNa
16996 return ir_build_err_name_gen(ira, instruction->base.scope, instruction->base.source_node, value, str_type);16996 return ir_build_err_name_gen(ira, instruction->base.scope, instruction->base.source_node, value, str_type);
16997}16997}
1699816998
16999static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrcTagName *instruction) {16999static Stage1AirInst *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, Stage1ZirInstTagName *instruction) {
17000 Error err;17000 Error err;
17001 IrInstGen *target = instruction->target->child;17001 Stage1AirInst *target = instruction->target->child;
17002 if (type_is_invalid(target->value->type))17002 if (type_is_invalid(target->value->type))
17003 return ira->codegen->invalid_inst_gen;17003 return ira->codegen->invalid_inst_gen;
1700417004
17005 ZigType *target_type = target->value->type;17005 ZigType *target_type = target->value->type;
1700617006
17007 if (target_type->id == ZigTypeIdEnumLiteral) {17007 if (target_type->id == ZigTypeIdEnumLiteral) {
17008 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);17008 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
17009 Buf *field_name = target->value->data.x_enum_literal;17009 Buf *field_name = target->value->data.x_enum_literal;
17010 result->value = create_sentineled_str_lit(17010 result->value = create_sentineled_str_lit(
17011 ira->codegen, field_name,17011 ira->codegen, field_name,
...@@ -17028,7 +17028,7 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc...@@ -17028,7 +17028,7 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc
1702817028
17029 if (can_fold_enum_type(target_type)) {17029 if (can_fold_enum_type(target_type)) {
17030 TypeEnumField *only_field = &target_type->data.enumeration.fields[0];17030 TypeEnumField *only_field = &target_type->data.enumeration.fields[0];
17031 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);17031 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
17032 result->value = create_sentineled_str_lit(17032 result->value = create_sentineled_str_lit(
17033 ira->codegen, only_field->name,17033 ira->codegen, only_field->name,
17034 ira->codegen->intern.for_zero_byte());17034 ira->codegen->intern.for_zero_byte());
...@@ -17047,7 +17047,7 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc...@@ -17047,7 +17047,7 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc
17047 buf_sprintf("no tag by value %s", buf_ptr(int_buf)));17047 buf_sprintf("no tag by value %s", buf_ptr(int_buf)));
17048 return ira->codegen->invalid_inst_gen;17048 return ira->codegen->invalid_inst_gen;
17049 }17049 }
17050 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);17050 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
17051 result->value = create_sentineled_str_lit(17051 result->value = create_sentineled_str_lit(
17052 ira->codegen, field->name,17052 ira->codegen, field->name,
17053 ira->codegen->intern.for_zero_byte());17053 ira->codegen->intern.for_zero_byte());
...@@ -17062,21 +17062,21 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc...@@ -17062,21 +17062,21 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc
17062 return ir_build_tag_name_gen(ira, instruction->base.scope, instruction->base.source_node, target, result_type);17062 return ir_build_tag_name_gen(ira, instruction->base.scope, instruction->base.source_node, target, result_type);
17063}17063}
1706417064
17065static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,17065static Stage1AirInst *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,
17066 IrInstSrcFieldParentPtr *instruction)17066 Stage1ZirInstFieldParentPtr *instruction)
17067{17067{
17068 Error err;17068 Error err;
17069 IrInstGen *type_value = instruction->type_value->child;17069 Stage1AirInst *type_value = instruction->type_value->child;
17070 ZigType *container_type = ir_resolve_type(ira, type_value);17070 ZigType *container_type = ir_resolve_type(ira, type_value);
17071 if (type_is_invalid(container_type))17071 if (type_is_invalid(container_type))
17072 return ira->codegen->invalid_inst_gen;17072 return ira->codegen->invalid_inst_gen;
1707317073
17074 IrInstGen *field_name_value = instruction->field_name->child;17074 Stage1AirInst *field_name_value = instruction->field_name->child;
17075 Buf *field_name = ir_resolve_str(ira, field_name_value);17075 Buf *field_name = ir_resolve_str(ira, field_name_value);
17076 if (!field_name)17076 if (!field_name)
17077 return ira->codegen->invalid_inst_gen;17077 return ira->codegen->invalid_inst_gen;
1707817078
17079 IrInstGen *field_ptr = instruction->field_ptr->child;17079 Stage1AirInst *field_ptr = instruction->field_ptr->child;
17080 if (type_is_invalid(field_ptr->value->type))17080 if (type_is_invalid(field_ptr->value->type))
17081 return ira->codegen->invalid_inst_gen;17081 return ira->codegen->invalid_inst_gen;
1708217082
...@@ -17112,7 +17112,7 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,...@@ -17112,7 +17112,7 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,
17112 field_ptr->value->type->data.pointer.is_volatile,17112 field_ptr->value->type->data.pointer.is_volatile,
17113 PtrLenSingle,17113 PtrLenSingle,
17114 field_ptr_align, 0, 0, false);17114 field_ptr_align, 0, 0, false);
17115 IrInstGen *casted_field_ptr = ir_implicit_cast(ira, field_ptr, field_ptr_type);17115 Stage1AirInst *casted_field_ptr = ir_implicit_cast(ira, field_ptr, field_ptr_type);
17116 if (type_is_invalid(casted_field_ptr->value->type))17116 if (type_is_invalid(casted_field_ptr->value->type))
17117 return ira->codegen->invalid_inst_gen;17117 return ira->codegen->invalid_inst_gen;
1711817118
...@@ -17141,7 +17141,7 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,...@@ -17141,7 +17141,7 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,
17141 return ira->codegen->invalid_inst_gen;17141 return ira->codegen->invalid_inst_gen;
17142 }17142 }
1714317143
17144 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);17144 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
17145 ZigValue *out_val = result->value;17145 ZigValue *out_val = result->value;
17146 out_val->data.x_ptr.special = ConstPtrSpecialRef;17146 out_val->data.x_ptr.special = ConstPtrSpecialRef;
17147 out_val->data.x_ptr.data.ref.pointee = field_ptr_val->data.x_ptr.data.base_struct.struct_val;17147 out_val->data.x_ptr.data.ref.pointee = field_ptr_val->data.x_ptr.data.base_struct.struct_val;
...@@ -17153,8 +17153,8 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,...@@ -17153,8 +17153,8 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,
17153}17153}
1715417154
17155static TypeStructField *validate_host_int_byte_offset(IrAnalyze *ira,17155static TypeStructField *validate_host_int_byte_offset(IrAnalyze *ira,
17156 IrInstGen *type_value,17156 Stage1AirInst *type_value,
17157 IrInstGen *field_name_value,17157 Stage1AirInst *field_name_value,
17158 size_t *byte_offset)17158 size_t *byte_offset)
17159{17159{
17160 ZigType *container_type = ir_resolve_type(ira, type_value);17160 ZigType *container_type = ir_resolve_type(ira, type_value);
...@@ -17194,12 +17194,12 @@ static TypeStructField *validate_host_int_byte_offset(IrAnalyze *ira,...@@ -17194,12 +17194,12 @@ static TypeStructField *validate_host_int_byte_offset(IrAnalyze *ira,
17194 return field;17194 return field;
17195}17195}
1719617196
17197static IrInstGen *ir_analyze_instruction_offset_of(IrAnalyze *ira, IrInstSrcOffsetOf *instruction) {17197static Stage1AirInst *ir_analyze_instruction_offset_of(IrAnalyze *ira, Stage1ZirInstOffsetOf *instruction) {
17198 IrInstGen *type_value = instruction->type_value->child;17198 Stage1AirInst *type_value = instruction->type_value->child;
17199 if (type_is_invalid(type_value->value->type))17199 if (type_is_invalid(type_value->value->type))
17200 return ira->codegen->invalid_inst_gen;17200 return ira->codegen->invalid_inst_gen;
1720117201
17202 IrInstGen *field_name_value = instruction->field_name->child;17202 Stage1AirInst *field_name_value = instruction->field_name->child;
17203 size_t host_int_byte_offset = 0;17203 size_t host_int_byte_offset = 0;
17204 TypeStructField *field = nullptr;17204 TypeStructField *field = nullptr;
17205 if (!(field = validate_host_int_byte_offset(ira, type_value, field_name_value, &host_int_byte_offset)))17205 if (!(field = validate_host_int_byte_offset(ira, type_value, field_name_value, &host_int_byte_offset)))
...@@ -17209,11 +17209,11 @@ static IrInstGen *ir_analyze_instruction_offset_of(IrAnalyze *ira, IrInstSrcOffs...@@ -17209,11 +17209,11 @@ static IrInstGen *ir_analyze_instruction_offset_of(IrAnalyze *ira, IrInstSrcOffs
17209 return ir_const_unsigned(ira, instruction->base.scope, instruction->base.source_node, byte_offset);17209 return ir_const_unsigned(ira, instruction->base.scope, instruction->base.source_node, byte_offset);
17210}17210}
1721117211
17212static IrInstGen *ir_analyze_instruction_bit_offset_of(IrAnalyze *ira, IrInstSrcBitOffsetOf *instruction) {17212static Stage1AirInst *ir_analyze_instruction_bit_offset_of(IrAnalyze *ira, Stage1ZirInstBitOffsetOf *instruction) {
17213 IrInstGen *type_value = instruction->type_value->child;17213 Stage1AirInst *type_value = instruction->type_value->child;
17214 if (type_is_invalid(type_value->value->type))17214 if (type_is_invalid(type_value->value->type))
17215 return ira->codegen->invalid_inst_gen;17215 return ira->codegen->invalid_inst_gen;
17216 IrInstGen *field_name_value = instruction->field_name->child;17216 Stage1AirInst *field_name_value = instruction->field_name->child;
17217 size_t host_int_byte_offset = 0;17217 size_t host_int_byte_offset = 0;
17218 TypeStructField *field = nullptr;17218 TypeStructField *field = nullptr;
17219 if (!(field = validate_host_int_byte_offset(ira, type_value, field_name_value, &host_int_byte_offset)))17219 if (!(field = validate_host_int_byte_offset(ira, type_value, field_name_value, &host_int_byte_offset)))
...@@ -18275,9 +18275,9 @@ static Error ir_make_type_info_value(IrAnalyze *ira, Scope *scope, AstNode *sour...@@ -18275,9 +18275,9 @@ static Error ir_make_type_info_value(IrAnalyze *ira, Scope *scope, AstNode *sour
18275 return ErrorNone;18275 return ErrorNone;
18276}18276}
1827718277
18278static IrInstGen *ir_analyze_instruction_type_info(IrAnalyze *ira, IrInstSrcTypeInfo *instruction) {18278static Stage1AirInst *ir_analyze_instruction_type_info(IrAnalyze *ira, Stage1ZirInstTypeInfo *instruction) {
18279 Error err;18279 Error err;
18280 IrInstGen *type_value = instruction->type_value->child;18280 Stage1AirInst *type_value = instruction->type_value->child;
18281 ZigType *type_entry = ir_resolve_type(ira, type_value);18281 ZigType *type_entry = ir_resolve_type(ira, type_value);
18282 if (type_is_invalid(type_entry))18282 if (type_is_invalid(type_entry))
18283 return ira->codegen->invalid_inst_gen;18283 return ira->codegen->invalid_inst_gen;
...@@ -18288,7 +18288,7 @@ static IrInstGen *ir_analyze_instruction_type_info(IrAnalyze *ira, IrInstSrcType...@@ -18288,7 +18288,7 @@ static IrInstGen *ir_analyze_instruction_type_info(IrAnalyze *ira, IrInstSrcType
18288 if ((err = ir_make_type_info_value(ira, instruction->base.scope, instruction->base.source_node, type_entry, &payload)))18288 if ((err = ir_make_type_info_value(ira, instruction->base.scope, instruction->base.source_node, type_entry, &payload)))
18289 return ira->codegen->invalid_inst_gen;18289 return ira->codegen->invalid_inst_gen;
1829018290
18291 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);18291 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
18292 ZigValue *out_val = result->value;18292 ZigValue *out_val = result->value;
18293 bigint_init_unsigned(&out_val->data.x_union.tag, type_id_index(type_entry));18293 bigint_init_unsigned(&out_val->data.x_union.tag, type_id_index(type_entry));
18294 out_val->data.x_union.payload = payload;18294 out_val->data.x_union.payload = payload;
...@@ -18321,8 +18321,8 @@ static Error get_const_field_sentinel(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -18321,8 +18321,8 @@ static Error get_const_field_sentinel(IrAnalyze *ira, Scope *scope, AstNode *sou
18321 if (field_val == nullptr)18321 if (field_val == nullptr)
18322 return ErrorSemanticAnalyzeFail;18322 return ErrorSemanticAnalyzeFail;
1832318323
18324 IrInstGen *field_inst = ir_const_move(ira, scope, source_node, field_val);18324 Stage1AirInst *field_inst = ir_const_move(ira, scope, source_node, field_val);
18325 IrInstGen *casted_field_inst = ir_implicit_cast(ira, field_inst,18325 Stage1AirInst *casted_field_inst = ir_implicit_cast(ira, field_inst,
18326 get_optional_type(ira->codegen, elem_type));18326 get_optional_type(ira->codegen, elem_type));
18327 if (type_is_invalid(casted_field_inst->value->type))18327 if (type_is_invalid(casted_field_inst->value->type))
18328 return ErrorSemanticAnalyzeFail;18328 return ErrorSemanticAnalyzeFail;
...@@ -19065,12 +19065,12 @@ static ZigType *type_info_to_type(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -19065,12 +19065,12 @@ static ZigType *type_info_to_type(IrAnalyze *ira, Scope *scope, AstNode *source_
19065 zig_unreachable();19065 zig_unreachable();
19066}19066}
1906719067
19068static IrInstGen *ir_analyze_instruction_type(IrAnalyze *ira, IrInstSrcType *instruction) {19068static Stage1AirInst *ir_analyze_instruction_type(IrAnalyze *ira, Stage1ZirInstType *instruction) {
19069 IrInstGen *uncasted_type_info = instruction->type_info->child;19069 Stage1AirInst *uncasted_type_info = instruction->type_info->child;
19070 if (type_is_invalid(uncasted_type_info->value->type))19070 if (type_is_invalid(uncasted_type_info->value->type))
19071 return ira->codegen->invalid_inst_gen;19071 return ira->codegen->invalid_inst_gen;
1907219072
19073 IrInstGen *type_info = ir_implicit_cast(ira, uncasted_type_info, ir_type_info_get_type(ira, nullptr, nullptr));19073 Stage1AirInst *type_info = ir_implicit_cast(ira, uncasted_type_info, ir_type_info_get_type(ira, nullptr, nullptr));
19074 if (type_is_invalid(type_info->value->type))19074 if (type_is_invalid(type_info->value->type))
19075 return ira->codegen->invalid_inst_gen;19075 return ira->codegen->invalid_inst_gen;
1907619076
...@@ -19085,8 +19085,8 @@ static IrInstGen *ir_analyze_instruction_type(IrAnalyze *ira, IrInstSrcType *ins...@@ -19085,8 +19085,8 @@ static IrInstGen *ir_analyze_instruction_type(IrAnalyze *ira, IrInstSrcType *ins
19085 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, type);19085 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, type);
19086}19086}
1908719087
19088static IrInstGen *ir_analyze_instruction_set_eval_branch_quota(IrAnalyze *ira,19088static Stage1AirInst *ir_analyze_instruction_set_eval_branch_quota(IrAnalyze *ira,
19089 IrInstSrcSetEvalBranchQuota *instruction)19089 Stage1ZirInstSetEvalBranchQuota *instruction)
19090{19090{
19091 uint64_t new_quota;19091 uint64_t new_quota;
19092 if (!ir_resolve_unsigned(ira, instruction->new_quota->child, ira->codegen->builtin_types.entry_u32, &new_quota))19092 if (!ir_resolve_unsigned(ira, instruction->new_quota->child, ira->codegen->builtin_types.entry_u32, &new_quota))
...@@ -19099,8 +19099,8 @@ static IrInstGen *ir_analyze_instruction_set_eval_branch_quota(IrAnalyze *ira,...@@ -19099,8 +19099,8 @@ static IrInstGen *ir_analyze_instruction_set_eval_branch_quota(IrAnalyze *ira,
19099 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);19099 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
19100}19100}
1910119101
19102static IrInstGen *ir_analyze_instruction_type_name(IrAnalyze *ira, IrInstSrcTypeName *instruction) {19102static Stage1AirInst *ir_analyze_instruction_type_name(IrAnalyze *ira, Stage1ZirInstTypeName *instruction) {
19103 IrInstGen *type_value = instruction->type_value->child;19103 Stage1AirInst *type_value = instruction->type_value->child;
19104 ZigType *type_entry = ir_resolve_type(ira, type_value);19104 ZigType *type_entry = ir_resolve_type(ira, type_value);
19105 if (type_is_invalid(type_entry))19105 if (type_is_invalid(type_entry))
19106 return ira->codegen->invalid_inst_gen;19106 return ira->codegen->invalid_inst_gen;
...@@ -19108,12 +19108,12 @@ static IrInstGen *ir_analyze_instruction_type_name(IrAnalyze *ira, IrInstSrcType...@@ -19108,12 +19108,12 @@ static IrInstGen *ir_analyze_instruction_type_name(IrAnalyze *ira, IrInstSrcType
19108 if (!type_entry->cached_const_name_val) {19108 if (!type_entry->cached_const_name_val) {
19109 type_entry->cached_const_name_val = create_const_str_lit(ira->codegen, type_bare_name(type_entry));19109 type_entry->cached_const_name_val = create_const_str_lit(ira->codegen, type_bare_name(type_entry));
19110 }19110 }
19111 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);19111 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
19112 copy_const_val(ira->codegen, result->value, type_entry->cached_const_name_val);19112 copy_const_val(ira->codegen, result->value, type_entry->cached_const_name_val);
19113 return result;19113 return result;
19114}19114}
1911519115
19116static IrInstGen *ir_analyze_instruction_c_import(IrAnalyze *ira, IrInstSrcCImport *instruction) {19116static Stage1AirInst *ir_analyze_instruction_c_import(IrAnalyze *ira, Stage1ZirInstCImport *instruction) {
19117 Error err;19117 Error err;
19118 AstNode *node = instruction->base.source_node;19118 AstNode *node = instruction->base.source_node;
19119 assert(node->type == NodeTypeFnCallExpr);19119 assert(node->type == NodeTypeFnCallExpr);
...@@ -19195,8 +19195,8 @@ static IrInstGen *ir_analyze_instruction_c_import(IrAnalyze *ira, IrInstSrcCImpo...@@ -19195,8 +19195,8 @@ static IrInstGen *ir_analyze_instruction_c_import(IrAnalyze *ira, IrInstSrcCImpo
19195 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, child_import);19195 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, child_import);
19196}19196}
1919719197
19198static IrInstGen *ir_analyze_instruction_c_include(IrAnalyze *ira, IrInstSrcCInclude *instruction) {19198static Stage1AirInst *ir_analyze_instruction_c_include(IrAnalyze *ira, Stage1ZirInstCInclude *instruction) {
19199 IrInstGen *name_value = instruction->name->child;19199 Stage1AirInst *name_value = instruction->name->child;
19200 if (type_is_invalid(name_value->value->type))19200 if (type_is_invalid(name_value->value->type))
19201 return ira->codegen->invalid_inst_gen;19201 return ira->codegen->invalid_inst_gen;
1920219202
...@@ -19213,8 +19213,8 @@ static IrInstGen *ir_analyze_instruction_c_include(IrAnalyze *ira, IrInstSrcCInc...@@ -19213,8 +19213,8 @@ static IrInstGen *ir_analyze_instruction_c_include(IrAnalyze *ira, IrInstSrcCInc
19213 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);19213 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
19214}19214}
1921519215
19216static IrInstGen *ir_analyze_instruction_c_define(IrAnalyze *ira, IrInstSrcCDefine *instruction) {19216static Stage1AirInst *ir_analyze_instruction_c_define(IrAnalyze *ira, Stage1ZirInstCDefine *instruction) {
19217 IrInstGen *name = instruction->name->child;19217 Stage1AirInst *name = instruction->name->child;
19218 if (type_is_invalid(name->value->type))19218 if (type_is_invalid(name->value->type))
19219 return ira->codegen->invalid_inst_gen;19219 return ira->codegen->invalid_inst_gen;
1922019220
...@@ -19222,7 +19222,7 @@ static IrInstGen *ir_analyze_instruction_c_define(IrAnalyze *ira, IrInstSrcCDefi...@@ -19222,7 +19222,7 @@ static IrInstGen *ir_analyze_instruction_c_define(IrAnalyze *ira, IrInstSrcCDefi
19222 if (!define_name)19222 if (!define_name)
19223 return ira->codegen->invalid_inst_gen;19223 return ira->codegen->invalid_inst_gen;
1922419224
19225 IrInstGen *value = instruction->value->child;19225 Stage1AirInst *value = instruction->value->child;
19226 if (type_is_invalid(value->value->type))19226 if (type_is_invalid(value->value->type))
19227 return ira->codegen->invalid_inst_gen;19227 return ira->codegen->invalid_inst_gen;
1922819228
...@@ -19244,8 +19244,8 @@ static IrInstGen *ir_analyze_instruction_c_define(IrAnalyze *ira, IrInstSrcCDefi...@@ -19244,8 +19244,8 @@ static IrInstGen *ir_analyze_instruction_c_define(IrAnalyze *ira, IrInstSrcCDefi
19244 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);19244 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
19245}19245}
1924619246
19247static IrInstGen *ir_analyze_instruction_c_undef(IrAnalyze *ira, IrInstSrcCUndef *instruction) {19247static Stage1AirInst *ir_analyze_instruction_c_undef(IrAnalyze *ira, Stage1ZirInstCUndef *instruction) {
19248 IrInstGen *name = instruction->name->child;19248 Stage1AirInst *name = instruction->name->child;
19249 if (type_is_invalid(name->value->type))19249 if (type_is_invalid(name->value->type))
19250 return ira->codegen->invalid_inst_gen;19250 return ira->codegen->invalid_inst_gen;
1925119251
...@@ -19262,8 +19262,8 @@ static IrInstGen *ir_analyze_instruction_c_undef(IrAnalyze *ira, IrInstSrcCUndef...@@ -19262,8 +19262,8 @@ static IrInstGen *ir_analyze_instruction_c_undef(IrAnalyze *ira, IrInstSrcCUndef
19262 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);19262 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
19263}19263}
1926419264
19265static IrInstGen *ir_analyze_instruction_embed_file(IrAnalyze *ira, IrInstSrcEmbedFile *instruction) {19265static Stage1AirInst *ir_analyze_instruction_embed_file(IrAnalyze *ira, Stage1ZirInstEmbedFile *instruction) {
19266 IrInstGen *name = instruction->name->child;19266 Stage1AirInst *name = instruction->name->child;
19267 if (type_is_invalid(name->value->type))19267 if (type_is_invalid(name->value->type))
19268 return ira->codegen->invalid_inst_gen;19268 return ira->codegen->invalid_inst_gen;
1926919269
...@@ -19298,12 +19298,12 @@ static IrInstGen *ir_analyze_instruction_embed_file(IrAnalyze *ira, IrInstSrcEmb...@@ -19298,12 +19298,12 @@ static IrInstGen *ir_analyze_instruction_embed_file(IrAnalyze *ira, IrInstSrcEmb
19298 }19298 }
19299 }19299 }
1930019300
19301 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);19301 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
19302 init_const_str_lit(ira->codegen, result->value, file_contents, true);19302 init_const_str_lit(ira->codegen, result->value, file_contents, true);
19303 return result;19303 return result;
19304}19304}
1930519305
19306static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxchg *instruction) {19306static Stage1AirInst *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, Stage1ZirInstCmpxchg *instruction) {
19307 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->type_value->child);19307 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->type_value->child);
19308 if (type_is_invalid(operand_type))19308 if (type_is_invalid(operand_type))
19309 return ira->codegen->invalid_inst_gen;19309 return ira->codegen->invalid_inst_gen;
...@@ -19314,26 +19314,26 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch...@@ -19314,26 +19314,26 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
19314 return ira->codegen->invalid_inst_gen;19314 return ira->codegen->invalid_inst_gen;
19315 }19315 }
1931619316
19317 IrInstGen *ptr = instruction->ptr->child;19317 Stage1AirInst *ptr = instruction->ptr->child;
19318 if (type_is_invalid(ptr->value->type))19318 if (type_is_invalid(ptr->value->type))
19319 return ira->codegen->invalid_inst_gen;19319 return ira->codegen->invalid_inst_gen;
1932019320
19321 // TODO let this be volatile19321 // TODO let this be volatile
19322 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false);19322 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false);
19323 IrInstGen *casted_ptr = ir_implicit_cast2(ira, instruction->ptr->scope,19323 Stage1AirInst *casted_ptr = ir_implicit_cast2(ira, instruction->ptr->scope,
19324 instruction->ptr->source_node, ptr, ptr_type);19324 instruction->ptr->source_node, ptr, ptr_type);
19325 if (type_is_invalid(casted_ptr->value->type))19325 if (type_is_invalid(casted_ptr->value->type))
19326 return ira->codegen->invalid_inst_gen;19326 return ira->codegen->invalid_inst_gen;
1932719327
19328 IrInstGen *cmp_value = instruction->cmp_value->child;19328 Stage1AirInst *cmp_value = instruction->cmp_value->child;
19329 if (type_is_invalid(cmp_value->value->type))19329 if (type_is_invalid(cmp_value->value->type))
19330 return ira->codegen->invalid_inst_gen;19330 return ira->codegen->invalid_inst_gen;
1933119331
19332 IrInstGen *new_value = instruction->new_value->child;19332 Stage1AirInst *new_value = instruction->new_value->child;
19333 if (type_is_invalid(new_value->value->type))19333 if (type_is_invalid(new_value->value->type))
19334 return ira->codegen->invalid_inst_gen;19334 return ira->codegen->invalid_inst_gen;
1933519335
19336 IrInstGen *success_order_value = instruction->success_order_value->child;19336 Stage1AirInst *success_order_value = instruction->success_order_value->child;
19337 if (type_is_invalid(success_order_value->value->type))19337 if (type_is_invalid(success_order_value->value->type))
19338 return ira->codegen->invalid_inst_gen;19338 return ira->codegen->invalid_inst_gen;
1933919339
...@@ -19341,7 +19341,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch...@@ -19341,7 +19341,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
19341 if (!ir_resolve_atomic_order(ira, success_order_value, &success_order))19341 if (!ir_resolve_atomic_order(ira, success_order_value, &success_order))
19342 return ira->codegen->invalid_inst_gen;19342 return ira->codegen->invalid_inst_gen;
1934319343
19344 IrInstGen *failure_order_value = instruction->failure_order_value->child;19344 Stage1AirInst *failure_order_value = instruction->failure_order_value->child;
19345 if (type_is_invalid(failure_order_value->value->type))19345 if (type_is_invalid(failure_order_value->value->type))
19346 return ira->codegen->invalid_inst_gen;19346 return ira->codegen->invalid_inst_gen;
1934719347
...@@ -19349,12 +19349,12 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch...@@ -19349,12 +19349,12 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
19349 if (!ir_resolve_atomic_order(ira, failure_order_value, &failure_order))19349 if (!ir_resolve_atomic_order(ira, failure_order_value, &failure_order))
19350 return ira->codegen->invalid_inst_gen;19350 return ira->codegen->invalid_inst_gen;
1935119351
19352 IrInstGen *casted_cmp_value = ir_implicit_cast2(ira, instruction->cmp_value->scope,19352 Stage1AirInst *casted_cmp_value = ir_implicit_cast2(ira, instruction->cmp_value->scope,
19353 instruction->cmp_value->source_node, cmp_value, operand_type);19353 instruction->cmp_value->source_node, cmp_value, operand_type);
19354 if (type_is_invalid(casted_cmp_value->value->type))19354 if (type_is_invalid(casted_cmp_value->value->type))
19355 return ira->codegen->invalid_inst_gen;19355 return ira->codegen->invalid_inst_gen;
1935619356
19357 IrInstGen *casted_new_value = ir_implicit_cast2(ira, instruction->new_value->scope,19357 Stage1AirInst *casted_new_value = ir_implicit_cast2(ira, instruction->new_value->scope,
19358 instruction->new_value->source_node, new_value, operand_type);19358 instruction->new_value->source_node, new_value, operand_type);
19359 if (type_is_invalid(casted_new_value->value->type))19359 if (type_is_invalid(casted_new_value->value->type))
19360 return ira->codegen->invalid_inst_gen;19360 return ira->codegen->invalid_inst_gen;
...@@ -19387,7 +19387,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch...@@ -19387,7 +19387,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
19387 case OnePossibleValueInvalid:19387 case OnePossibleValueInvalid:
19388 return ira->codegen->invalid_inst_gen;19388 return ira->codegen->invalid_inst_gen;
19389 case OnePossibleValueYes: {19389 case OnePossibleValueYes: {
19390 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);19390 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
19391 set_optional_value_to_null(result->value);19391 set_optional_value_to_null(result->value);
19392 return result;19392 return result;
19393 }19393 }
...@@ -19414,7 +19414,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch...@@ -19414,7 +19414,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
19414 return ira->codegen->invalid_inst_gen;19414 return ira->codegen->invalid_inst_gen;
1941519415
19416 bool eql = const_values_equal(ira->codegen, stored_val, expected_val);19416 bool eql = const_values_equal(ira->codegen, stored_val, expected_val);
19417 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);19417 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
19418 if (eql) {19418 if (eql) {
19419 copy_const_val(ira->codegen, stored_val, new_val);19419 copy_const_val(ira->codegen, stored_val, new_val);
19420 set_optional_value_to_null(result->value);19420 set_optional_value_to_null(result->value);
...@@ -19424,7 +19424,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch...@@ -19424,7 +19424,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
19424 return result;19424 return result;
19425 }19425 }
1942619426
19427 IrInstGen *result_loc;19427 Stage1AirInst *result_loc;
19428 if (handle_is_ptr(ira->codegen, result_type)) {19428 if (handle_is_ptr(ira->codegen, result_type)) {
19429 result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,19429 result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
19430 result_type, nullptr, true, true);19430 result_type, nullptr, true, true);
...@@ -19568,12 +19568,12 @@ static ErrorMsg *ir_eval_reduce(IrAnalyze *ira, Scope *scope, AstNode *source_no...@@ -19568,12 +19568,12 @@ static ErrorMsg *ir_eval_reduce(IrAnalyze *ira, Scope *scope, AstNode *source_no
19568 return nullptr;19568 return nullptr;
19569}19569}
1957019570
19571static IrInstGen *ir_analyze_instruction_reduce(IrAnalyze *ira, IrInstSrcReduce *instruction) {19571static Stage1AirInst *ir_analyze_instruction_reduce(IrAnalyze *ira, Stage1ZirInstReduce *instruction) {
19572 IrInstGen *op_inst = instruction->op->child;19572 Stage1AirInst *op_inst = instruction->op->child;
19573 if (type_is_invalid(op_inst->value->type))19573 if (type_is_invalid(op_inst->value->type))
19574 return ira->codegen->invalid_inst_gen;19574 return ira->codegen->invalid_inst_gen;
1957519575
19576 IrInstGen *value_inst = instruction->value->child;19576 Stage1AirInst *value_inst = instruction->value->child;
19577 if (type_is_invalid(value_inst->value->type))19577 if (type_is_invalid(value_inst->value->type))
19578 return ira->codegen->invalid_inst_gen;19578 return ira->codegen->invalid_inst_gen;
1957919579
...@@ -19624,7 +19624,7 @@ static IrInstGen *ir_analyze_instruction_reduce(IrAnalyze *ira, IrInstSrcReduce...@@ -19624,7 +19624,7 @@ static IrInstGen *ir_analyze_instruction_reduce(IrAnalyze *ira, IrInstSrcReduce
19624 }19624 }
1962519625
19626 if (instr_is_comptime(value_inst)) {19626 if (instr_is_comptime(value_inst)) {
19627 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, elem_type);19627 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, elem_type);
19628 if (ir_eval_reduce(ira, instruction->base.scope, instruction->base.source_node, op, value_inst->value, result->value))19628 if (ir_eval_reduce(ira, instruction->base.scope, instruction->base.source_node, op, value_inst->value, result->value))
19629 return ira->codegen->invalid_inst_gen;19629 return ira->codegen->invalid_inst_gen;
19630 return result;19630 return result;
...@@ -19633,8 +19633,8 @@ static IrInstGen *ir_analyze_instruction_reduce(IrAnalyze *ira, IrInstSrcReduce...@@ -19633,8 +19633,8 @@ static IrInstGen *ir_analyze_instruction_reduce(IrAnalyze *ira, IrInstSrcReduce
19633 return ir_build_reduce_gen(ira, instruction->base.scope, instruction->base.source_node, op, value_inst, elem_type);19633 return ir_build_reduce_gen(ira, instruction->base.scope, instruction->base.source_node, op, value_inst, elem_type);
19634}19634}
1963519635
19636static IrInstGen *ir_analyze_instruction_fence(IrAnalyze *ira, IrInstSrcFence *instruction) {19636static Stage1AirInst *ir_analyze_instruction_fence(IrAnalyze *ira, Stage1ZirInstFence *instruction) {
19637 IrInstGen *order_inst = instruction->order->child;19637 Stage1AirInst *order_inst = instruction->order->child;
19638 if (type_is_invalid(order_inst->value->type))19638 if (type_is_invalid(order_inst->value->type))
19639 return ira->codegen->invalid_inst_gen;19639 return ira->codegen->invalid_inst_gen;
1964019640
...@@ -19651,8 +19651,8 @@ static IrInstGen *ir_analyze_instruction_fence(IrAnalyze *ira, IrInstSrcFence *i...@@ -19651,8 +19651,8 @@ static IrInstGen *ir_analyze_instruction_fence(IrAnalyze *ira, IrInstSrcFence *i
19651 return ir_build_fence_gen(ira, instruction->base.scope, instruction->base.source_node, order);19651 return ir_build_fence_gen(ira, instruction->base.scope, instruction->base.source_node, order);
19652}19652}
1965319653
19654static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTruncate *instruction) {19654static Stage1AirInst *ir_analyze_instruction_truncate(IrAnalyze *ira, Stage1ZirInstTruncate *instruction) {
19655 IrInstGen *dest_type_value = instruction->dest_type->child;19655 Stage1AirInst *dest_type_value = instruction->dest_type->child;
19656 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);19656 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);
19657 if (type_is_invalid(dest_type))19657 if (type_is_invalid(dest_type))
19658 return ira->codegen->invalid_inst_gen;19658 return ira->codegen->invalid_inst_gen;
...@@ -19664,7 +19664,7 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc...@@ -19664,7 +19664,7 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc
19664 return ira->codegen->invalid_inst_gen;19664 return ira->codegen->invalid_inst_gen;
19665 }19665 }
1966619666
19667 IrInstGen *target = instruction->target->child;19667 Stage1AirInst *target = instruction->target->child;
19668 ZigType *src_type = target->value->type;19668 ZigType *src_type = target->value->type;
19669 if (type_is_invalid(src_type))19669 if (type_is_invalid(src_type))
19670 return ira->codegen->invalid_inst_gen;19670 return ira->codegen->invalid_inst_gen;
...@@ -19697,14 +19697,14 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc...@@ -19697,14 +19697,14 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc
19697 if (val == nullptr)19697 if (val == nullptr)
19698 return ira->codegen->invalid_inst_gen;19698 return ira->codegen->invalid_inst_gen;
1969919699
19700 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type);19700 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type);
19701 bigint_truncate(&result->value->data.x_bigint, &val->data.x_bigint,19701 bigint_truncate(&result->value->data.x_bigint, &val->data.x_bigint,
19702 dest_type->data.integral.bit_count, dest_type->data.integral.is_signed);19702 dest_type->data.integral.bit_count, dest_type->data.integral.is_signed);
19703 return result;19703 return result;
19704 }19704 }
1970519705
19706 if (src_type->data.integral.bit_count == 0 || dest_type->data.integral.bit_count == 0) {19706 if (src_type->data.integral.bit_count == 0 || dest_type->data.integral.bit_count == 0) {
19707 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type);19707 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type);
19708 bigint_init_unsigned(&result->value->data.x_bigint, 0);19708 bigint_init_unsigned(&result->value->data.x_bigint, 0);
19709 return result;19709 return result;
19710 }19710 }
...@@ -19712,7 +19712,7 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc...@@ -19712,7 +19712,7 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc
19712 return ir_build_truncate_gen(ira, instruction->base.scope, instruction->base.source_node, dest_type, target);19712 return ir_build_truncate_gen(ira, instruction->base.scope, instruction->base.source_node, dest_type, target);
19713}19713}
1971419714
19715static IrInstGen *ir_analyze_instruction_int_cast(IrAnalyze *ira, IrInstSrcIntCast *instruction) {19715static Stage1AirInst *ir_analyze_instruction_int_cast(IrAnalyze *ira, Stage1ZirInstIntCast *instruction) {
19716 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);19716 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);
19717 if (type_is_invalid(dest_type))19717 if (type_is_invalid(dest_type))
19718 return ira->codegen->invalid_inst_gen;19718 return ira->codegen->invalid_inst_gen;
...@@ -19726,7 +19726,7 @@ static IrInstGen *ir_analyze_instruction_int_cast(IrAnalyze *ira, IrInstSrcIntCa...@@ -19726,7 +19726,7 @@ static IrInstGen *ir_analyze_instruction_int_cast(IrAnalyze *ira, IrInstSrcIntCa
19726 return ira->codegen->invalid_inst_gen;19726 return ira->codegen->invalid_inst_gen;
19727 }19727 }
1972819728
19729 IrInstGen *target = instruction->target->child;19729 Stage1AirInst *target = instruction->target->child;
19730 if (type_is_invalid(target->value->type))19730 if (type_is_invalid(target->value->type))
19731 return ira->codegen->invalid_inst_gen;19731 return ira->codegen->invalid_inst_gen;
1973219732
...@@ -19750,7 +19750,7 @@ static IrInstGen *ir_analyze_instruction_int_cast(IrAnalyze *ira, IrInstSrcIntCa...@@ -19750,7 +19750,7 @@ static IrInstGen *ir_analyze_instruction_int_cast(IrAnalyze *ira, IrInstSrcIntCa
19750 return ir_analyze_widen_or_shorten(ira, instruction->base.scope, instruction->base.source_node, target, dest_type);19750 return ir_analyze_widen_or_shorten(ira, instruction->base.scope, instruction->base.source_node, target, dest_type);
19751}19751}
1975219752
19753static IrInstGen *ir_analyze_instruction_float_cast(IrAnalyze *ira, IrInstSrcFloatCast *instruction) {19753static Stage1AirInst *ir_analyze_instruction_float_cast(IrAnalyze *ira, Stage1ZirInstFloatCast *instruction) {
19754 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);19754 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);
19755 if (type_is_invalid(dest_type))19755 if (type_is_invalid(dest_type))
19756 return ira->codegen->invalid_inst_gen;19756 return ira->codegen->invalid_inst_gen;
...@@ -19761,7 +19761,7 @@ static IrInstGen *ir_analyze_instruction_float_cast(IrAnalyze *ira, IrInstSrcFlo...@@ -19761,7 +19761,7 @@ static IrInstGen *ir_analyze_instruction_float_cast(IrAnalyze *ira, IrInstSrcFlo
19761 return ira->codegen->invalid_inst_gen;19761 return ira->codegen->invalid_inst_gen;
19762 }19762 }
1976319763
19764 IrInstGen *target = instruction->target->child;19764 Stage1AirInst *target = instruction->target->child;
19765 if (type_is_invalid(target->value->type))19765 if (type_is_invalid(target->value->type))
19766 return ira->codegen->invalid_inst_gen;19766 return ira->codegen->invalid_inst_gen;
1976719767
...@@ -19800,7 +19800,7 @@ static IrInstGen *ir_analyze_instruction_float_cast(IrAnalyze *ira, IrInstSrcFlo...@@ -19800,7 +19800,7 @@ static IrInstGen *ir_analyze_instruction_float_cast(IrAnalyze *ira, IrInstSrcFlo
19800 return ir_analyze_widen_or_shorten(ira, instruction->base.scope, instruction->base.source_node, target, dest_type);19800 return ir_analyze_widen_or_shorten(ira, instruction->base.scope, instruction->base.source_node, target, dest_type);
19801}19801}
1980219802
19803static IrInstGen *ir_analyze_instruction_err_set_cast(IrAnalyze *ira, IrInstSrcErrSetCast *instruction) {19803static Stage1AirInst *ir_analyze_instruction_err_set_cast(IrAnalyze *ira, Stage1ZirInstErrSetCast *instruction) {
19804 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);19804 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);
19805 if (type_is_invalid(dest_type))19805 if (type_is_invalid(dest_type))
19806 return ira->codegen->invalid_inst_gen;19806 return ira->codegen->invalid_inst_gen;
...@@ -19811,7 +19811,7 @@ static IrInstGen *ir_analyze_instruction_err_set_cast(IrAnalyze *ira, IrInstSrcE...@@ -19811,7 +19811,7 @@ static IrInstGen *ir_analyze_instruction_err_set_cast(IrAnalyze *ira, IrInstSrcE
19811 return ira->codegen->invalid_inst_gen;19811 return ira->codegen->invalid_inst_gen;
19812 }19812 }
1981319813
19814 IrInstGen *target = instruction->target->child;19814 Stage1AirInst *target = instruction->target->child;
19815 if (type_is_invalid(target->value->type))19815 if (type_is_invalid(target->value->type))
19816 return ira->codegen->invalid_inst_gen;19816 return ira->codegen->invalid_inst_gen;
1981719817
...@@ -19849,7 +19849,7 @@ static Error resolve_ptr_align(IrAnalyze *ira, ZigType *ty, uint32_t *result_ali...@@ -19849,7 +19849,7 @@ static Error resolve_ptr_align(IrAnalyze *ira, ZigType *ty, uint32_t *result_ali
19849 return ErrorNone;19849 return ErrorNone;
19850}19850}
1985119851
19852static IrInstGen *ir_analyze_instruction_int_to_float(IrAnalyze *ira, IrInstSrcIntToFloat *instruction) {19852static Stage1AirInst *ir_analyze_instruction_int_to_float(IrAnalyze *ira, Stage1ZirInstIntToFloat *instruction) {
19853 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);19853 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);
19854 if (type_is_invalid(dest_type))19854 if (type_is_invalid(dest_type))
19855 return ira->codegen->invalid_inst_gen;19855 return ira->codegen->invalid_inst_gen;
...@@ -19860,7 +19860,7 @@ static IrInstGen *ir_analyze_instruction_int_to_float(IrAnalyze *ira, IrInstSrcI...@@ -19860,7 +19860,7 @@ static IrInstGen *ir_analyze_instruction_int_to_float(IrAnalyze *ira, IrInstSrcI
19860 return ira->codegen->invalid_inst_gen;19860 return ira->codegen->invalid_inst_gen;
19861 }19861 }
1986219862
19863 IrInstGen *target = instruction->target->child;19863 Stage1AirInst *target = instruction->target->child;
19864 if (type_is_invalid(target->value->type))19864 if (type_is_invalid(target->value->type))
19865 return ira->codegen->invalid_inst_gen;19865 return ira->codegen->invalid_inst_gen;
1986619866
...@@ -19873,7 +19873,7 @@ static IrInstGen *ir_analyze_instruction_int_to_float(IrAnalyze *ira, IrInstSrcI...@@ -19873,7 +19873,7 @@ static IrInstGen *ir_analyze_instruction_int_to_float(IrAnalyze *ira, IrInstSrcI
19873 return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, dest_type, CastOpIntToFloat);19873 return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, dest_type, CastOpIntToFloat);
19874}19874}
1987519875
19876static IrInstGen *ir_analyze_instruction_float_to_int(IrAnalyze *ira, IrInstSrcFloatToInt *instruction) {19876static Stage1AirInst *ir_analyze_instruction_float_to_int(IrAnalyze *ira, Stage1ZirInstFloatToInt *instruction) {
19877 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);19877 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);
19878 if (type_is_invalid(dest_type))19878 if (type_is_invalid(dest_type))
19879 return ira->codegen->invalid_inst_gen;19879 return ira->codegen->invalid_inst_gen;
...@@ -19884,7 +19884,7 @@ static IrInstGen *ir_analyze_instruction_float_to_int(IrAnalyze *ira, IrInstSrcF...@@ -19884,7 +19884,7 @@ static IrInstGen *ir_analyze_instruction_float_to_int(IrAnalyze *ira, IrInstSrcF
19884 return ira->codegen->invalid_inst_gen;19884 return ira->codegen->invalid_inst_gen;
19885 }19885 }
1988619886
19887 IrInstGen *target = instruction->target->child;19887 Stage1AirInst *target = instruction->target->child;
19888 if (type_is_invalid(target->value->type))19888 if (type_is_invalid(target->value->type))
19889 return ira->codegen->invalid_inst_gen;19889 return ira->codegen->invalid_inst_gen;
1989019890
...@@ -19901,12 +19901,12 @@ static IrInstGen *ir_analyze_instruction_float_to_int(IrAnalyze *ira, IrInstSrcF...@@ -19901,12 +19901,12 @@ static IrInstGen *ir_analyze_instruction_float_to_int(IrAnalyze *ira, IrInstSrcF
19901 return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, dest_type, CastOpFloatToInt);19901 return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, dest_type, CastOpFloatToInt);
19902}19902}
1990319903
19904static IrInstGen *ir_analyze_instruction_err_to_int(IrAnalyze *ira, IrInstSrcErrToInt *instruction) {19904static Stage1AirInst *ir_analyze_instruction_err_to_int(IrAnalyze *ira, Stage1ZirInstErrToInt *instruction) {
19905 IrInstGen *target = instruction->target->child;19905 Stage1AirInst *target = instruction->target->child;
19906 if (type_is_invalid(target->value->type))19906 if (type_is_invalid(target->value->type))
19907 return ira->codegen->invalid_inst_gen;19907 return ira->codegen->invalid_inst_gen;
1990819908
19909 IrInstGen *casted_target;19909 Stage1AirInst *casted_target;
19910 if (target->value->type->id == ZigTypeIdErrorSet) {19910 if (target->value->type->id == ZigTypeIdErrorSet) {
19911 casted_target = target;19911 casted_target = target;
19912 } else {19912 } else {
...@@ -19918,20 +19918,20 @@ static IrInstGen *ir_analyze_instruction_err_to_int(IrAnalyze *ira, IrInstSrcErr...@@ -19918,20 +19918,20 @@ static IrInstGen *ir_analyze_instruction_err_to_int(IrAnalyze *ira, IrInstSrcErr
19918 return ir_analyze_err_to_int(ira, instruction->base.scope, instruction->base.source_node, casted_target, ira->codegen->err_tag_type);19918 return ir_analyze_err_to_int(ira, instruction->base.scope, instruction->base.source_node, casted_target, ira->codegen->err_tag_type);
19919}19919}
1992019920
19921static IrInstGen *ir_analyze_instruction_int_to_err(IrAnalyze *ira, IrInstSrcIntToErr *instruction) {19921static Stage1AirInst *ir_analyze_instruction_int_to_err(IrAnalyze *ira, Stage1ZirInstIntToErr *instruction) {
19922 IrInstGen *target = instruction->target->child;19922 Stage1AirInst *target = instruction->target->child;
19923 if (type_is_invalid(target->value->type))19923 if (type_is_invalid(target->value->type))
19924 return ira->codegen->invalid_inst_gen;19924 return ira->codegen->invalid_inst_gen;
1992519925
19926 IrInstGen *casted_target = ir_implicit_cast(ira, target, ira->codegen->err_tag_type);19926 Stage1AirInst *casted_target = ir_implicit_cast(ira, target, ira->codegen->err_tag_type);
19927 if (type_is_invalid(casted_target->value->type))19927 if (type_is_invalid(casted_target->value->type))
19928 return ira->codegen->invalid_inst_gen;19928 return ira->codegen->invalid_inst_gen;
1992919929
19930 return ir_analyze_int_to_err(ira, instruction->base.scope, instruction->base.source_node, casted_target, ira->codegen->builtin_types.entry_global_error_set);19930 return ir_analyze_int_to_err(ira, instruction->base.scope, instruction->base.source_node, casted_target, ira->codegen->builtin_types.entry_global_error_set);
19931}19931}
1993219932
19933static IrInstGen *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, IrInstSrcBoolToInt *instruction) {19933static Stage1AirInst *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, Stage1ZirInstBoolToInt *instruction) {
19934 IrInstGen *target = instruction->target->child;19934 Stage1AirInst *target = instruction->target->child;
19935 if (type_is_invalid(target->value->type))19935 if (type_is_invalid(target->value->type))
19936 return ira->codegen->invalid_inst_gen;19936 return ira->codegen->invalid_inst_gen;
1993719937
...@@ -19953,7 +19953,7 @@ static IrInstGen *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, IrInstSrcBo...@@ -19953,7 +19953,7 @@ static IrInstGen *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, IrInstSrcBo
19953 return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, u1_type, CastOpBoolToInt);19953 return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, u1_type, CastOpBoolToInt);
19954}19954}
1995519955
19956static IrInstGen *ir_analyze_instruction_vector_type(IrAnalyze *ira, IrInstSrcVectorType *instruction) {19956static Stage1AirInst *ir_analyze_instruction_vector_type(IrAnalyze *ira, Stage1ZirInstVectorType *instruction) {
19957 uint64_t len;19957 uint64_t len;
19958 if (!ir_resolve_unsigned(ira, instruction->len->child, ira->codegen->builtin_types.entry_u32, &len))19958 if (!ir_resolve_unsigned(ira, instruction->len->child, ira->codegen->builtin_types.entry_u32, &len))
19959 return ira->codegen->invalid_inst_gen;19959 return ira->codegen->invalid_inst_gen;
...@@ -19967,8 +19967,8 @@ static IrInstGen *ir_analyze_instruction_vector_type(IrAnalyze *ira, IrInstSrcVe...@@ -19967,8 +19967,8 @@ static IrInstGen *ir_analyze_instruction_vector_type(IrAnalyze *ira, IrInstSrcVe
19967 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, vector_type);19967 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, vector_type);
19968}19968}
1996919969
19970static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,19970static Stage1AirInst *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,
19971 ZigType *scalar_type, IrInstGen *a, IrInstGen *b, IrInstGen *mask)19971 ZigType *scalar_type, Stage1AirInst *a, Stage1AirInst *b, Stage1AirInst *mask)
19972{19972{
19973 Error err;19973 Error err;
19974 src_assert(source_node && scalar_type && a && b && mask, source_node);19974 src_assert(source_node && scalar_type && a && b && mask, source_node);
...@@ -20056,7 +20056,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod...@@ -20056,7 +20056,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod
20056 continue;20056 continue;
20057 int32_t v_i32 = bigint_as_signed(&mask_elem_val->data.x_bigint);20057 int32_t v_i32 = bigint_as_signed(&mask_elem_val->data.x_bigint);
20058 uint32_t v;20058 uint32_t v;
20059 IrInstGen *chosen_operand;20059 Stage1AirInst *chosen_operand;
20060 if (v_i32 >= 0) {20060 if (v_i32 >= 0) {
20061 v = (uint32_t)v_i32;20061 v = (uint32_t)v_i32;
20062 chosen_operand = a;20062 chosen_operand = a;
...@@ -20091,7 +20091,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod...@@ -20091,7 +20091,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod
20091 expand_undef_array(ira->codegen, a_val);20091 expand_undef_array(ira->codegen, a_val);
20092 expand_undef_array(ira->codegen, b_val);20092 expand_undef_array(ira->codegen, b_val);
2009320093
20094 IrInstGen *result = ir_const(ira, scope, source_node, result_type);20094 Stage1AirInst *result = ir_const(ira, scope, source_node, result_type);
20095 result->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate<ZigValue>(len_mask);20095 result->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate<ZigValue>(len_mask);
20096 for (uint32_t i = 0; i < mask_val->type->data.vector.len; i += 1) {20096 for (uint32_t i = 0; i < mask_val->type->data.vector.len; i += 1) {
20097 ZigValue *mask_elem_val = &mask_val->data.x_array.data.s_none.elements[i];20097 ZigValue *mask_elem_val = &mask_val->data.x_array.data.s_none.elements[i];
...@@ -20123,7 +20123,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod...@@ -20123,7 +20123,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod
20123 uint32_t len_min = min(len_a, len_b);20123 uint32_t len_min = min(len_a, len_b);
20124 uint32_t len_max = max(len_a, len_b);20124 uint32_t len_max = max(len_a, len_b);
2012520125
20126 IrInstGen *expand_mask = ir_const(ira, mask->scope, mask->source_node,20126 Stage1AirInst *expand_mask = ir_const(ira, mask->scope, mask->source_node,
20127 get_vector_type(ira->codegen, len_max, ira->codegen->builtin_types.entry_i32));20127 get_vector_type(ira->codegen, len_max, ira->codegen->builtin_types.entry_i32));
20128 expand_mask->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate<ZigValue>(len_max);20128 expand_mask->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate<ZigValue>(len_max);
20129 uint32_t i = 0;20129 uint32_t i = 0;
...@@ -20132,7 +20132,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod...@@ -20132,7 +20132,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod
20132 for (; i < len_max; i += 1)20132 for (; i < len_max; i += 1)
20133 bigint_init_signed(&expand_mask->value->data.x_array.data.s_none.elements[i].data.x_bigint, -1);20133 bigint_init_signed(&expand_mask->value->data.x_array.data.s_none.elements[i].data.x_bigint, -1);
2013420134
20135 IrInstGen *undef = ir_const_undef(ira, scope, source_node,20135 Stage1AirInst *undef = ir_const_undef(ira, scope, source_node,
20136 get_vector_type(ira->codegen, len_min, scalar_type));20136 get_vector_type(ira->codegen, len_min, scalar_type));
2013720137
20138 if (len_b < len_a) {20138 if (len_b < len_a) {
...@@ -20146,34 +20146,34 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod...@@ -20146,34 +20146,34 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod
20146 result_type, a, b, mask);20146 result_type, a, b, mask);
20147}20147}
2014820148
20149static IrInstGen *ir_analyze_instruction_shuffle_vector(IrAnalyze *ira, IrInstSrcShuffleVector *instruction) {20149static Stage1AirInst *ir_analyze_instruction_shuffle_vector(IrAnalyze *ira, Stage1ZirInstShuffleVector *instruction) {
20150 ZigType *scalar_type = ir_resolve_vector_elem_type(ira, instruction->scalar_type->child);20150 ZigType *scalar_type = ir_resolve_vector_elem_type(ira, instruction->scalar_type->child);
20151 if (type_is_invalid(scalar_type))20151 if (type_is_invalid(scalar_type))
20152 return ira->codegen->invalid_inst_gen;20152 return ira->codegen->invalid_inst_gen;
2015320153
20154 IrInstGen *a = instruction->a->child;20154 Stage1AirInst *a = instruction->a->child;
20155 if (type_is_invalid(a->value->type))20155 if (type_is_invalid(a->value->type))
20156 return ira->codegen->invalid_inst_gen;20156 return ira->codegen->invalid_inst_gen;
2015720157
20158 IrInstGen *b = instruction->b->child;20158 Stage1AirInst *b = instruction->b->child;
20159 if (type_is_invalid(b->value->type))20159 if (type_is_invalid(b->value->type))
20160 return ira->codegen->invalid_inst_gen;20160 return ira->codegen->invalid_inst_gen;
2016120161
20162 IrInstGen *mask = instruction->mask->child;20162 Stage1AirInst *mask = instruction->mask->child;
20163 if (type_is_invalid(mask->value->type))20163 if (type_is_invalid(mask->value->type))
20164 return ira->codegen->invalid_inst_gen;20164 return ira->codegen->invalid_inst_gen;
2016520165
20166 return ir_analyze_shuffle_vector(ira, instruction->base.scope, instruction->base.source_node, scalar_type, a, b, mask);20166 return ir_analyze_shuffle_vector(ira, instruction->base.scope, instruction->base.source_node, scalar_type, a, b, mask);
20167}20167}
2016820168
20169static IrInstGen *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstSrcSplat *instruction) {20169static Stage1AirInst *ir_analyze_instruction_splat(IrAnalyze *ira, Stage1ZirInstSplat *instruction) {
20170 Error err;20170 Error err;
2017120171
20172 IrInstGen *len = instruction->len->child;20172 Stage1AirInst *len = instruction->len->child;
20173 if (type_is_invalid(len->value->type))20173 if (type_is_invalid(len->value->type))
20174 return ira->codegen->invalid_inst_gen;20174 return ira->codegen->invalid_inst_gen;
2017520175
20176 IrInstGen *scalar = instruction->scalar->child;20176 Stage1AirInst *scalar = instruction->scalar->child;
20177 if (type_is_invalid(scalar->value->type))20177 if (type_is_invalid(scalar->value->type))
20178 return ira->codegen->invalid_inst_gen;20178 return ira->codegen->invalid_inst_gen;
2017920179
...@@ -20194,7 +20194,7 @@ static IrInstGen *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstSrcSplat *i...@@ -20194,7 +20194,7 @@ static IrInstGen *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstSrcSplat *i
20194 if (scalar_val->special == ConstValSpecialUndef)20194 if (scalar_val->special == ConstValSpecialUndef)
20195 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, return_type);20195 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, return_type);
2019620196
20197 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);20197 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);
20198 result->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate<ZigValue>(len_int);20198 result->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate<ZigValue>(len_int);
20199 for (uint32_t i = 0; i < len_int; i += 1) {20199 for (uint32_t i = 0; i < len_int; i += 1) {
20200 copy_const_val(ira->codegen, &result->value->data.x_array.data.s_none.elements[i], scalar_val);20200 copy_const_val(ira->codegen, &result->value->data.x_array.data.s_none.elements[i], scalar_val);
...@@ -20205,14 +20205,14 @@ static IrInstGen *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstSrcSplat *i...@@ -20205,14 +20205,14 @@ static IrInstGen *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstSrcSplat *i
20205 return ir_build_splat_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, scalar);20205 return ir_build_splat_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, scalar);
20206}20206}
2020720207
20208static IrInstGen *ir_analyze_instruction_bool_not(IrAnalyze *ira, IrInstSrcBoolNot *instruction) {20208static Stage1AirInst *ir_analyze_instruction_bool_not(IrAnalyze *ira, Stage1ZirInstBoolNot *instruction) {
20209 IrInstGen *value = instruction->value->child;20209 Stage1AirInst *value = instruction->value->child;
20210 if (type_is_invalid(value->value->type))20210 if (type_is_invalid(value->value->type))
20211 return ira->codegen->invalid_inst_gen;20211 return ira->codegen->invalid_inst_gen;
2021220212
20213 ZigType *bool_type = ira->codegen->builtin_types.entry_bool;20213 ZigType *bool_type = ira->codegen->builtin_types.entry_bool;
2021420214
20215 IrInstGen *casted_value = ir_implicit_cast(ira, value, bool_type);20215 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, bool_type);
20216 if (type_is_invalid(casted_value->value->type))20216 if (type_is_invalid(casted_value->value->type))
20217 return ira->codegen->invalid_inst_gen;20217 return ira->codegen->invalid_inst_gen;
2021820218
...@@ -20227,18 +20227,18 @@ static IrInstGen *ir_analyze_instruction_bool_not(IrAnalyze *ira, IrInstSrcBoolN...@@ -20227,18 +20227,18 @@ static IrInstGen *ir_analyze_instruction_bool_not(IrAnalyze *ira, IrInstSrcBoolN
20227 return ir_build_bool_not_gen(ira, instruction->base.scope, instruction->base.source_node, casted_value);20227 return ir_build_bool_not_gen(ira, instruction->base.scope, instruction->base.source_node, casted_value);
20228}20228}
2022920229
20230static IrInstGen *ir_analyze_instruction_memset(IrAnalyze *ira, IrInstSrcMemset *instruction) {20230static Stage1AirInst *ir_analyze_instruction_memset(IrAnalyze *ira, Stage1ZirInstMemset *instruction) {
20231 Error err;20231 Error err;
2023220232
20233 IrInstGen *dest_ptr = instruction->dest_ptr->child;20233 Stage1AirInst *dest_ptr = instruction->dest_ptr->child;
20234 if (type_is_invalid(dest_ptr->value->type))20234 if (type_is_invalid(dest_ptr->value->type))
20235 return ira->codegen->invalid_inst_gen;20235 return ira->codegen->invalid_inst_gen;
2023620236
20237 IrInstGen *byte_value = instruction->byte->child;20237 Stage1AirInst *byte_value = instruction->byte->child;
20238 if (type_is_invalid(byte_value->value->type))20238 if (type_is_invalid(byte_value->value->type))
20239 return ira->codegen->invalid_inst_gen;20239 return ira->codegen->invalid_inst_gen;
2024020240
20241 IrInstGen *count_value = instruction->count->child;20241 Stage1AirInst *count_value = instruction->count->child;
20242 if (type_is_invalid(count_value->value->type))20242 if (type_is_invalid(count_value->value->type))
20243 return ira->codegen->invalid_inst_gen;20243 return ira->codegen->invalid_inst_gen;
2024420244
...@@ -20258,15 +20258,15 @@ static IrInstGen *ir_analyze_instruction_memset(IrAnalyze *ira, IrInstSrcMemset...@@ -20258,15 +20258,15 @@ static IrInstGen *ir_analyze_instruction_memset(IrAnalyze *ira, IrInstSrcMemset
20258 ZigType *u8_ptr = get_pointer_to_type_extra(ira->codegen, u8, false, dest_is_volatile,20258 ZigType *u8_ptr = get_pointer_to_type_extra(ira->codegen, u8, false, dest_is_volatile,
20259 PtrLenUnknown, dest_align, 0, 0, false);20259 PtrLenUnknown, dest_align, 0, 0, false);
2026020260
20261 IrInstGen *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr);20261 Stage1AirInst *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr);
20262 if (type_is_invalid(casted_dest_ptr->value->type))20262 if (type_is_invalid(casted_dest_ptr->value->type))
20263 return ira->codegen->invalid_inst_gen;20263 return ira->codegen->invalid_inst_gen;
2026420264
20265 IrInstGen *casted_byte = ir_implicit_cast(ira, byte_value, u8);20265 Stage1AirInst *casted_byte = ir_implicit_cast(ira, byte_value, u8);
20266 if (type_is_invalid(casted_byte->value->type))20266 if (type_is_invalid(casted_byte->value->type))
20267 return ira->codegen->invalid_inst_gen;20267 return ira->codegen->invalid_inst_gen;
2026820268
20269 IrInstGen *casted_count = ir_implicit_cast(ira, count_value, usize);20269 Stage1AirInst *casted_count = ir_implicit_cast(ira, count_value, usize);
20270 if (type_is_invalid(casted_count->value->type))20270 if (type_is_invalid(casted_count->value->type))
20271 return ira->codegen->invalid_inst_gen;20271 return ira->codegen->invalid_inst_gen;
2027220272
...@@ -20346,18 +20346,18 @@ static IrInstGen *ir_analyze_instruction_memset(IrAnalyze *ira, IrInstSrcMemset...@@ -20346,18 +20346,18 @@ static IrInstGen *ir_analyze_instruction_memset(IrAnalyze *ira, IrInstSrcMemset
20346 return ir_build_memset_gen(ira, instruction->base.scope, instruction->base.source_node, casted_dest_ptr, casted_byte, casted_count);20346 return ir_build_memset_gen(ira, instruction->base.scope, instruction->base.source_node, casted_dest_ptr, casted_byte, casted_count);
20347}20347}
2034820348
20349static IrInstGen *ir_analyze_instruction_memcpy(IrAnalyze *ira, IrInstSrcMemcpy *instruction) {20349static Stage1AirInst *ir_analyze_instruction_memcpy(IrAnalyze *ira, Stage1ZirInstMemcpy *instruction) {
20350 Error err;20350 Error err;
2035120351
20352 IrInstGen *dest_ptr = instruction->dest_ptr->child;20352 Stage1AirInst *dest_ptr = instruction->dest_ptr->child;
20353 if (type_is_invalid(dest_ptr->value->type))20353 if (type_is_invalid(dest_ptr->value->type))
20354 return ira->codegen->invalid_inst_gen;20354 return ira->codegen->invalid_inst_gen;
2035520355
20356 IrInstGen *src_ptr = instruction->src_ptr->child;20356 Stage1AirInst *src_ptr = instruction->src_ptr->child;
20357 if (type_is_invalid(src_ptr->value->type))20357 if (type_is_invalid(src_ptr->value->type))
20358 return ira->codegen->invalid_inst_gen;20358 return ira->codegen->invalid_inst_gen;
2035920359
20360 IrInstGen *count_value = instruction->count->child;20360 Stage1AirInst *count_value = instruction->count->child;
20361 if (type_is_invalid(count_value->value->type))20361 if (type_is_invalid(count_value->value->type))
20362 return ira->codegen->invalid_inst_gen;20362 return ira->codegen->invalid_inst_gen;
2036320363
...@@ -20391,15 +20391,15 @@ static IrInstGen *ir_analyze_instruction_memcpy(IrAnalyze *ira, IrInstSrcMemcpy...@@ -20391,15 +20391,15 @@ static IrInstGen *ir_analyze_instruction_memcpy(IrAnalyze *ira, IrInstSrcMemcpy
20391 ZigType *u8_ptr_const = get_pointer_to_type_extra(ira->codegen, u8, true, src_is_volatile,20391 ZigType *u8_ptr_const = get_pointer_to_type_extra(ira->codegen, u8, true, src_is_volatile,
20392 PtrLenUnknown, src_align, 0, 0, false);20392 PtrLenUnknown, src_align, 0, 0, false);
2039320393
20394 IrInstGen *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr_mut);20394 Stage1AirInst *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr_mut);
20395 if (type_is_invalid(casted_dest_ptr->value->type))20395 if (type_is_invalid(casted_dest_ptr->value->type))
20396 return ira->codegen->invalid_inst_gen;20396 return ira->codegen->invalid_inst_gen;
2039720397
20398 IrInstGen *casted_src_ptr = ir_implicit_cast(ira, src_ptr, u8_ptr_const);20398 Stage1AirInst *casted_src_ptr = ir_implicit_cast(ira, src_ptr, u8_ptr_const);
20399 if (type_is_invalid(casted_src_ptr->value->type))20399 if (type_is_invalid(casted_src_ptr->value->type))
20400 return ira->codegen->invalid_inst_gen;20400 return ira->codegen->invalid_inst_gen;
2040120401
20402 IrInstGen *casted_count = ir_implicit_cast(ira, count_value, usize);20402 Stage1AirInst *casted_count = ir_implicit_cast(ira, count_value, usize);
20403 if (type_is_invalid(casted_count->value->type))20403 if (type_is_invalid(casted_count->value->type))
20404 return ira->codegen->invalid_inst_gen;20404 return ira->codegen->invalid_inst_gen;
2040520405
...@@ -20534,10 +20534,10 @@ static ZigType *get_result_loc_type(IrAnalyze *ira, ResultLoc *result_loc) {...@@ -20534,10 +20534,10 @@ static ZigType *get_result_loc_type(IrAnalyze *ira, ResultLoc *result_loc) {
20534 return nullptr;20534 return nullptr;
20535}20535}
2053620536
20537static IrInstGen *ir_analyze_instruction_slice(IrAnalyze *ira, IrInstSrcSlice *instruction) {20537static Stage1AirInst *ir_analyze_instruction_slice(IrAnalyze *ira, Stage1ZirInstSlice *instruction) {
20538 Error err;20538 Error err;
2053920539
20540 IrInstGen *ptr_ptr = instruction->ptr->child;20540 Stage1AirInst *ptr_ptr = instruction->ptr->child;
20541 if (type_is_invalid(ptr_ptr->value->type))20541 if (type_is_invalid(ptr_ptr->value->type))
20542 return ira->codegen->invalid_inst_gen;20542 return ira->codegen->invalid_inst_gen;
2054320543
...@@ -20545,16 +20545,16 @@ static IrInstGen *ir_analyze_instruction_slice(IrAnalyze *ira, IrInstSrcSlice *i...@@ -20545,16 +20545,16 @@ static IrInstGen *ir_analyze_instruction_slice(IrAnalyze *ira, IrInstSrcSlice *i
20545 assert(ptr_ptr_type->id == ZigTypeIdPointer);20545 assert(ptr_ptr_type->id == ZigTypeIdPointer);
20546 ZigType *array_type = ptr_ptr_type->data.pointer.child_type;20546 ZigType *array_type = ptr_ptr_type->data.pointer.child_type;
2054720547
20548 IrInstGen *start = instruction->start->child;20548 Stage1AirInst *start = instruction->start->child;
20549 if (type_is_invalid(start->value->type))20549 if (type_is_invalid(start->value->type))
20550 return ira->codegen->invalid_inst_gen;20550 return ira->codegen->invalid_inst_gen;
2055120551
20552 ZigType *usize = ira->codegen->builtin_types.entry_usize;20552 ZigType *usize = ira->codegen->builtin_types.entry_usize;
20553 IrInstGen *casted_start = ir_implicit_cast(ira, start, usize);20553 Stage1AirInst *casted_start = ir_implicit_cast(ira, start, usize);
20554 if (type_is_invalid(casted_start->value->type))20554 if (type_is_invalid(casted_start->value->type))
20555 return ira->codegen->invalid_inst_gen;20555 return ira->codegen->invalid_inst_gen;
2055620556
20557 IrInstGen *end;20557 Stage1AirInst *end;
20558 if (instruction->end) {20558 if (instruction->end) {
20559 end = instruction->end->child;20559 end = instruction->end->child;
20560 if (type_is_invalid(end->value->type))20560 if (type_is_invalid(end->value->type))
...@@ -20626,10 +20626,10 @@ static IrInstGen *ir_analyze_instruction_slice(IrAnalyze *ira, IrInstSrcSlice *i...@@ -20626,10 +20626,10 @@ static IrInstGen *ir_analyze_instruction_slice(IrAnalyze *ira, IrInstSrcSlice *i
2062620626
20627 ZigValue *sentinel_val = nullptr;20627 ZigValue *sentinel_val = nullptr;
20628 if (instruction->sentinel) {20628 if (instruction->sentinel) {
20629 IrInstGen *uncasted_sentinel = instruction->sentinel->child;20629 Stage1AirInst *uncasted_sentinel = instruction->sentinel->child;
20630 if (type_is_invalid(uncasted_sentinel->value->type))20630 if (type_is_invalid(uncasted_sentinel->value->type))
20631 return ira->codegen->invalid_inst_gen;20631 return ira->codegen->invalid_inst_gen;
20632 IrInstGen *sentinel = ir_implicit_cast(ira, uncasted_sentinel, elem_type);20632 Stage1AirInst *sentinel = ir_implicit_cast(ira, uncasted_sentinel, elem_type);
20633 if (type_is_invalid(sentinel->value->type))20633 if (type_is_invalid(sentinel->value->type))
20634 return ira->codegen->invalid_inst_gen;20634 return ira->codegen->invalid_inst_gen;
20635 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);20635 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);
...@@ -20990,7 +20990,7 @@ done_with_return_type:...@@ -20990,7 +20990,7 @@ done_with_return_type:
20990 }20990 }
20991 exit_check_sentinel:20991 exit_check_sentinel:
2099220992
20993 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);20993 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);
2099420994
20995 ZigValue *ptr_val;20995 ZigValue *ptr_val;
20996 if (return_type->id == ZigTypeIdPointer) {20996 if (return_type->id == ZigTypeIdPointer) {
...@@ -21061,7 +21061,7 @@ done_with_return_type:...@@ -21061,7 +21061,7 @@ done_with_return_type:
21061 }21061 }
2106221062
21063 if (generate_non_null_assert) {21063 if (generate_non_null_assert) {
21064 IrInstGen *ptr_val = ir_get_deref(ira, instruction->base.scope,21064 Stage1AirInst *ptr_val = ir_get_deref(ira, instruction->base.scope,
21065 instruction->base.source_node, ptr_ptr, nullptr);21065 instruction->base.source_node, ptr_ptr, nullptr);
2106621066
21067 if (type_is_invalid(ptr_val->value->type))21067 if (type_is_invalid(ptr_val->value->type))
...@@ -21070,7 +21070,7 @@ done_with_return_type:...@@ -21070,7 +21070,7 @@ done_with_return_type:
21070 ir_build_assert_non_null(ira, instruction->base.scope, instruction->base.source_node, ptr_val);21070 ir_build_assert_non_null(ira, instruction->base.scope, instruction->base.source_node, ptr_val);
21071 }21071 }
2107221072
21073 IrInstGen *result_loc = nullptr;21073 Stage1AirInst *result_loc = nullptr;
2107421074
21075 if (return_type->id != ZigTypeIdPointer) {21075 if (return_type->id != ZigTypeIdPointer) {
21076 result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,21076 result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
...@@ -21086,9 +21086,9 @@ done_with_return_type:...@@ -21086,9 +21086,9 @@ done_with_return_type:
21086 return ira->codegen->invalid_inst_gen;21086 return ira->codegen->invalid_inst_gen;
21087 }21087 }
2108821088
21089 IrInstGen *dummy_value = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);21089 Stage1AirInst *dummy_value = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);
21090 dummy_value->value->special = ConstValSpecialRuntime;21090 dummy_value->value->special = ConstValSpecialRuntime;
21091 IrInstGen *dummy_result = ir_implicit_cast2(ira,21091 Stage1AirInst *dummy_result = ir_implicit_cast2(ira,
21092 instruction->base.scope, instruction->base.source_node,21092 instruction->base.scope, instruction->base.source_node,
21093 dummy_value, result_loc->value->type->data.pointer.child_type);21093 dummy_value, result_loc->value->type->data.pointer.child_type);
21094 if (type_is_invalid(dummy_result->value->type))21094 if (type_is_invalid(dummy_result->value->type))
...@@ -21100,7 +21100,7 @@ done_with_return_type:...@@ -21100,7 +21100,7 @@ done_with_return_type:
21100 casted_start, end, instruction->safety_check_on, result_loc, sentinel_val);21100 casted_start, end, instruction->safety_check_on, result_loc, sentinel_val);
21101}21101}
2110221102
21103static IrInstGen *ir_analyze_instruction_has_field(IrAnalyze *ira, IrInstSrcHasField *instruction) {21103static Stage1AirInst *ir_analyze_instruction_has_field(IrAnalyze *ira, Stage1ZirInstHasField *instruction) {
21104 Error err;21104 Error err;
21105 ZigType *container_type = ir_resolve_type(ira, instruction->container_type->child);21105 ZigType *container_type = ir_resolve_type(ira, instruction->container_type->child);
21106 if (type_is_invalid(container_type))21106 if (type_is_invalid(container_type))
...@@ -21128,7 +21128,7 @@ static IrInstGen *ir_analyze_instruction_has_field(IrAnalyze *ira, IrInstSrcHasF...@@ -21128,7 +21128,7 @@ static IrInstGen *ir_analyze_instruction_has_field(IrAnalyze *ira, IrInstSrcHasF
21128 return ir_const_bool(ira, instruction->base.scope, instruction->base.source_node, result);21128 return ir_const_bool(ira, instruction->base.scope, instruction->base.source_node, result);
21129}21129}
2113021130
21131static IrInstGen *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, IrInstSrcWasmMemorySize *instruction) {21131static Stage1AirInst *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, Stage1ZirInstWasmMemorySize *instruction) {
21132 // TODO generate compile error for target_arch different than 32bit21132 // TODO generate compile error for target_arch different than 32bit
21133 if (!target_is_wasm(ira->codegen->zig_target)) {21133 if (!target_is_wasm(ira->codegen->zig_target)) {
21134 ir_add_error_node(ira, instruction->base.source_node,21134 ir_add_error_node(ira, instruction->base.source_node,
...@@ -21136,20 +21136,20 @@ static IrInstGen *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, IrInst...@@ -21136,20 +21136,20 @@ static IrInstGen *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, IrInst
21136 return ira->codegen->invalid_inst_gen;21136 return ira->codegen->invalid_inst_gen;
21137 }21137 }
2113821138
21139 IrInstGen *index = instruction->index->child;21139 Stage1AirInst *index = instruction->index->child;
21140 if (type_is_invalid(index->value->type))21140 if (type_is_invalid(index->value->type))
21141 return ira->codegen->invalid_inst_gen;21141 return ira->codegen->invalid_inst_gen;
2114221142
21143 ZigType *u32 = ira->codegen->builtin_types.entry_u32;21143 ZigType *u32 = ira->codegen->builtin_types.entry_u32;
2114421144
21145 IrInstGen *casted_index = ir_implicit_cast(ira, index, u32);21145 Stage1AirInst *casted_index = ir_implicit_cast(ira, index, u32);
21146 if (type_is_invalid(casted_index->value->type))21146 if (type_is_invalid(casted_index->value->type))
21147 return ira->codegen->invalid_inst_gen;21147 return ira->codegen->invalid_inst_gen;
2114821148
21149 return ir_build_wasm_memory_size_gen(ira, instruction->base.scope, instruction->base.source_node, casted_index);21149 return ir_build_wasm_memory_size_gen(ira, instruction->base.scope, instruction->base.source_node, casted_index);
21150}21150}
2115121151
21152static IrInstGen *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, IrInstSrcWasmMemoryGrow *instruction) {21152static Stage1AirInst *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, Stage1ZirInstWasmMemoryGrow *instruction) {
21153 // TODO generate compile error for target_arch different than 32bit21153 // TODO generate compile error for target_arch different than 32bit
21154 if (!target_is_wasm(ira->codegen->zig_target)) {21154 if (!target_is_wasm(ira->codegen->zig_target)) {
21155 ir_add_error_node(ira, instruction->base.source_node,21155 ir_add_error_node(ira, instruction->base.source_node,
...@@ -21157,40 +21157,40 @@ static IrInstGen *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, IrInst...@@ -21157,40 +21157,40 @@ static IrInstGen *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, IrInst
21157 return ira->codegen->invalid_inst_gen;21157 return ira->codegen->invalid_inst_gen;
21158 }21158 }
2115921159
21160 IrInstGen *index = instruction->index->child;21160 Stage1AirInst *index = instruction->index->child;
21161 if (type_is_invalid(index->value->type))21161 if (type_is_invalid(index->value->type))
21162 return ira->codegen->invalid_inst_gen;21162 return ira->codegen->invalid_inst_gen;
2116321163
21164 ZigType *u32 = ira->codegen->builtin_types.entry_u32;21164 ZigType *u32 = ira->codegen->builtin_types.entry_u32;
2116521165
21166 IrInstGen *casted_index = ir_implicit_cast(ira, index, u32);21166 Stage1AirInst *casted_index = ir_implicit_cast(ira, index, u32);
21167 if (type_is_invalid(casted_index->value->type))21167 if (type_is_invalid(casted_index->value->type))
21168 return ira->codegen->invalid_inst_gen;21168 return ira->codegen->invalid_inst_gen;
2116921169
21170 IrInstGen *delta = instruction->delta->child;21170 Stage1AirInst *delta = instruction->delta->child;
21171 if (type_is_invalid(delta->value->type))21171 if (type_is_invalid(delta->value->type))
21172 return ira->codegen->invalid_inst_gen;21172 return ira->codegen->invalid_inst_gen;
2117321173
21174 IrInstGen *casted_delta = ir_implicit_cast(ira, delta, u32);21174 Stage1AirInst *casted_delta = ir_implicit_cast(ira, delta, u32);
21175 if (type_is_invalid(casted_delta->value->type))21175 if (type_is_invalid(casted_delta->value->type))
21176 return ira->codegen->invalid_inst_gen;21176 return ira->codegen->invalid_inst_gen;
2117721177
21178 return ir_build_wasm_memory_grow_gen(ira, instruction->base.scope, instruction->base.source_node, casted_index, casted_delta);21178 return ir_build_wasm_memory_grow_gen(ira, instruction->base.scope, instruction->base.source_node, casted_index, casted_delta);
21179}21179}
2118021180
21181static IrInstGen *ir_analyze_instruction_breakpoint(IrAnalyze *ira, IrInstSrcBreakpoint *instruction) {21181static Stage1AirInst *ir_analyze_instruction_breakpoint(IrAnalyze *ira, Stage1ZirInstBreakpoint *instruction) {
21182 return ir_build_breakpoint_gen(ira, instruction->base.scope, instruction->base.source_node);21182 return ir_build_breakpoint_gen(ira, instruction->base.scope, instruction->base.source_node);
21183}21183}
2118421184
21185static IrInstGen *ir_analyze_instruction_return_address(IrAnalyze *ira, IrInstSrcReturnAddress *instruction) {21185static Stage1AirInst *ir_analyze_instruction_return_address(IrAnalyze *ira, Stage1ZirInstReturnAddress *instruction) {
21186 return ir_build_return_address_gen(ira, instruction->base.scope, instruction->base.source_node);21186 return ir_build_return_address_gen(ira, instruction->base.scope, instruction->base.source_node);
21187}21187}
2118821188
21189static IrInstGen *ir_analyze_instruction_frame_address(IrAnalyze *ira, IrInstSrcFrameAddress *instruction) {21189static Stage1AirInst *ir_analyze_instruction_frame_address(IrAnalyze *ira, Stage1ZirInstFrameAddress *instruction) {
21190 return ir_build_frame_address_gen(ira, instruction->base.scope, instruction->base.source_node);21190 return ir_build_frame_address_gen(ira, instruction->base.scope, instruction->base.source_node);
21191}21191}
2119221192
21193static IrInstGen *ir_analyze_instruction_frame_handle(IrAnalyze *ira, IrInstSrcFrameHandle *instruction) {21193static Stage1AirInst *ir_analyze_instruction_frame_handle(IrAnalyze *ira, Stage1ZirInstFrameHandle *instruction) {
21194 ZigFn *fn = ira->fn;21194 ZigFn *fn = ira->fn;
21195 src_assert(fn != nullptr, instruction->base.source_node);21195 src_assert(fn != nullptr, instruction->base.source_node);
2119621196
...@@ -21204,7 +21204,7 @@ static IrInstGen *ir_analyze_instruction_frame_handle(IrAnalyze *ira, IrInstSrcF...@@ -21204,7 +21204,7 @@ static IrInstGen *ir_analyze_instruction_frame_handle(IrAnalyze *ira, IrInstSrcF
21204 return ir_build_handle_gen(ira, instruction->base.scope, instruction->base.source_node, ptr_frame_type);21204 return ir_build_handle_gen(ira, instruction->base.scope, instruction->base.source_node, ptr_frame_type);
21205}21205}
2120621206
21207static IrInstGen *ir_analyze_instruction_frame_type(IrAnalyze *ira, IrInstSrcFrameType *instruction) {21207static Stage1AirInst *ir_analyze_instruction_frame_type(IrAnalyze *ira, Stage1ZirInstFrameType *instruction) {
21208 ZigFn *fn = ir_resolve_fn(ira, instruction->fn->child);21208 ZigFn *fn = ir_resolve_fn(ira, instruction->fn->child);
21209 if (fn == nullptr)21209 if (fn == nullptr)
21210 return ira->codegen->invalid_inst_gen;21210 return ira->codegen->invalid_inst_gen;
...@@ -21219,8 +21219,8 @@ static IrInstGen *ir_analyze_instruction_frame_type(IrAnalyze *ira, IrInstSrcFra...@@ -21219,8 +21219,8 @@ static IrInstGen *ir_analyze_instruction_frame_type(IrAnalyze *ira, IrInstSrcFra
21219 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, ty);21219 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, ty);
21220}21220}
2122121221
21222static IrInstGen *ir_analyze_instruction_frame_size(IrAnalyze *ira, IrInstSrcFrameSize *instruction) {21222static Stage1AirInst *ir_analyze_instruction_frame_size(IrAnalyze *ira, Stage1ZirInstFrameSize *instruction) {
21223 IrInstGen *fn = instruction->fn->child;21223 Stage1AirInst *fn = instruction->fn->child;
21224 if (type_is_invalid(fn->value->type))21224 if (type_is_invalid(fn->value->type))
21225 return ira->codegen->invalid_inst_gen;21225 return ira->codegen->invalid_inst_gen;
2122621226
...@@ -21235,13 +21235,13 @@ static IrInstGen *ir_analyze_instruction_frame_size(IrAnalyze *ira, IrInstSrcFra...@@ -21235,13 +21235,13 @@ static IrInstGen *ir_analyze_instruction_frame_size(IrAnalyze *ira, IrInstSrcFra
21235 return ir_build_frame_size_gen(ira, instruction->base.scope, instruction->base.source_node, fn);21235 return ir_build_frame_size_gen(ira, instruction->base.scope, instruction->base.source_node, fn);
21236}21236}
2123721237
21238static IrInstGen *ir_analyze_instruction_align_of(IrAnalyze *ira, IrInstSrcAlignOf *instruction) {21238static Stage1AirInst *ir_analyze_instruction_align_of(IrAnalyze *ira, Stage1ZirInstAlignOf *instruction) {
21239 // Here we create a lazy value in order to avoid resolving the alignment of the type21239 // Here we create a lazy value in order to avoid resolving the alignment of the type
21240 // immediately. This avoids false positive dependency loops such as:21240 // immediately. This avoids false positive dependency loops such as:
21241 // const Node = struct {21241 // const Node = struct {
21242 // field: []align(@alignOf(Node)) Node,21242 // field: []align(@alignOf(Node)) Node,
21243 // };21243 // };
21244 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int);21244 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int);
21245 result->value->special = ConstValSpecialLazy;21245 result->value->special = ConstValSpecialLazy;
2124621246
21247 LazyValueAlignOf *lazy_align_of = heap::c_allocator.create<LazyValueAlignOf>();21247 LazyValueAlignOf *lazy_align_of = heap::c_allocator.create<LazyValueAlignOf>();
...@@ -21256,10 +21256,10 @@ static IrInstGen *ir_analyze_instruction_align_of(IrAnalyze *ira, IrInstSrcAlign...@@ -21256,10 +21256,10 @@ static IrInstGen *ir_analyze_instruction_align_of(IrAnalyze *ira, IrInstSrcAlign
21256 return result;21256 return result;
21257}21257}
2125821258
21259static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOverflowOp *instruction) {21259static Stage1AirInst *ir_analyze_instruction_overflow_op(IrAnalyze *ira, Stage1ZirInstOverflowOp *instruction) {
21260 Error err;21260 Error err;
2126121261
21262 IrInstGen *type_value = instruction->type_value->child;21262 Stage1AirInst *type_value = instruction->type_value->child;
21263 if (type_is_invalid(type_value->value->type))21263 if (type_is_invalid(type_value->value->type))
21264 return ira->codegen->invalid_inst_gen;21264 return ira->codegen->invalid_inst_gen;
2126521265
...@@ -21273,19 +21273,19 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv...@@ -21273,19 +21273,19 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv
21273 return ira->codegen->invalid_inst_gen;21273 return ira->codegen->invalid_inst_gen;
21274 }21274 }
2127521275
21276 IrInstGen *op1 = instruction->op1->child;21276 Stage1AirInst *op1 = instruction->op1->child;
21277 if (type_is_invalid(op1->value->type))21277 if (type_is_invalid(op1->value->type))
21278 return ira->codegen->invalid_inst_gen;21278 return ira->codegen->invalid_inst_gen;
2127921279
21280 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, dest_type);21280 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, dest_type);
21281 if (type_is_invalid(casted_op1->value->type))21281 if (type_is_invalid(casted_op1->value->type))
21282 return ira->codegen->invalid_inst_gen;21282 return ira->codegen->invalid_inst_gen;
2128321283
21284 IrInstGen *op2 = instruction->op2->child;21284 Stage1AirInst *op2 = instruction->op2->child;
21285 if (type_is_invalid(op2->value->type))21285 if (type_is_invalid(op2->value->type))
21286 return ira->codegen->invalid_inst_gen;21286 return ira->codegen->invalid_inst_gen;
2128721287
21288 IrInstGen *casted_op2;21288 Stage1AirInst *casted_op2;
21289 if (instruction->op == IrOverflowOpShl) {21289 if (instruction->op == IrOverflowOpShl) {
21290 ZigType *shift_amt_type = get_smallest_unsigned_int_type(ira->codegen,21290 ZigType *shift_amt_type = get_smallest_unsigned_int_type(ira->codegen,
21291 dest_type->data.integral.bit_count - 1);21291 dest_type->data.integral.bit_count - 1);
...@@ -21296,7 +21296,7 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv...@@ -21296,7 +21296,7 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv
21296 if (type_is_invalid(casted_op2->value->type))21296 if (type_is_invalid(casted_op2->value->type))
21297 return ira->codegen->invalid_inst_gen;21297 return ira->codegen->invalid_inst_gen;
2129821298
21299 IrInstGen *result_ptr = instruction->result_ptr->child;21299 Stage1AirInst *result_ptr = instruction->result_ptr->child;
21300 if (type_is_invalid(result_ptr->value->type))21300 if (type_is_invalid(result_ptr->value->type))
21301 return ira->codegen->invalid_inst_gen;21301 return ira->codegen->invalid_inst_gen;
2130221302
...@@ -21313,7 +21313,7 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv...@@ -21313,7 +21313,7 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv
21313 expected_ptr_type = get_pointer_to_type(ira->codegen, dest_type, false);21313 expected_ptr_type = get_pointer_to_type(ira->codegen, dest_type, false);
21314 }21314 }
2131521315
21316 IrInstGen *casted_result_ptr = ir_implicit_cast(ira, result_ptr, expected_ptr_type);21316 Stage1AirInst *casted_result_ptr = ir_implicit_cast(ira, result_ptr, expected_ptr_type);
21317 if (type_is_invalid(casted_result_ptr->value->type))21317 if (type_is_invalid(casted_result_ptr->value->type))
21318 return ira->codegen->invalid_inst_gen;21318 return ira->codegen->invalid_inst_gen;
2131921319
...@@ -21403,8 +21403,8 @@ static void ir_eval_mul_add(IrAnalyze *ira, ZigType *float_type,...@@ -21403,8 +21403,8 @@ static void ir_eval_mul_add(IrAnalyze *ira, ZigType *float_type,
21403 }21403 }
21404}21404}
2140521405
21406static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd *instruction) {21406static Stage1AirInst *ir_analyze_instruction_mul_add(IrAnalyze *ira, Stage1ZirInstMulAdd *instruction) {
21407 IrInstGen *type_value = instruction->type_value->child;21407 Stage1AirInst *type_value = instruction->type_value->child;
21408 if (type_is_invalid(type_value->value->type))21408 if (type_is_invalid(type_value->value->type))
21409 return ira->codegen->invalid_inst_gen;21409 return ira->codegen->invalid_inst_gen;
2141021410
...@@ -21420,27 +21420,27 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd...@@ -21420,27 +21420,27 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd
21420 return ira->codegen->invalid_inst_gen;21420 return ira->codegen->invalid_inst_gen;
21421 }21421 }
2142221422
21423 IrInstGen *op1 = instruction->op1->child;21423 Stage1AirInst *op1 = instruction->op1->child;
21424 if (type_is_invalid(op1->value->type))21424 if (type_is_invalid(op1->value->type))
21425 return ira->codegen->invalid_inst_gen;21425 return ira->codegen->invalid_inst_gen;
2142621426
21427 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, expr_type);21427 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, expr_type);
21428 if (type_is_invalid(casted_op1->value->type))21428 if (type_is_invalid(casted_op1->value->type))
21429 return ira->codegen->invalid_inst_gen;21429 return ira->codegen->invalid_inst_gen;
2143021430
21431 IrInstGen *op2 = instruction->op2->child;21431 Stage1AirInst *op2 = instruction->op2->child;
21432 if (type_is_invalid(op2->value->type))21432 if (type_is_invalid(op2->value->type))
21433 return ira->codegen->invalid_inst_gen;21433 return ira->codegen->invalid_inst_gen;
2143421434
21435 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, expr_type);21435 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, expr_type);
21436 if (type_is_invalid(casted_op2->value->type))21436 if (type_is_invalid(casted_op2->value->type))
21437 return ira->codegen->invalid_inst_gen;21437 return ira->codegen->invalid_inst_gen;
2143821438
21439 IrInstGen *op3 = instruction->op3->child;21439 Stage1AirInst *op3 = instruction->op3->child;
21440 if (type_is_invalid(op3->value->type))21440 if (type_is_invalid(op3->value->type))
21441 return ira->codegen->invalid_inst_gen;21441 return ira->codegen->invalid_inst_gen;
2144221442
21443 IrInstGen *casted_op3 = ir_implicit_cast(ira, op3, expr_type);21443 Stage1AirInst *casted_op3 = ir_implicit_cast(ira, op3, expr_type);
21444 if (type_is_invalid(casted_op3->value->type))21444 if (type_is_invalid(casted_op3->value->type))
21445 return ira->codegen->invalid_inst_gen;21445 return ira->codegen->invalid_inst_gen;
2144621446
...@@ -21457,7 +21457,7 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd...@@ -21457,7 +21457,7 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd
21457 if (!op3_const)21457 if (!op3_const)
21458 return ira->codegen->invalid_inst_gen;21458 return ira->codegen->invalid_inst_gen;
2145921459
21460 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);21460 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);
21461 ZigValue *out_val = result->value;21461 ZigValue *out_val = result->value;
2146221462
21463 if (expr_type->id == ZigTypeIdVector) {21463 if (expr_type->id == ZigTypeIdVector) {
...@@ -21491,12 +21491,12 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd...@@ -21491,12 +21491,12 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd
21491 return ir_build_mul_add_gen(ira, instruction->base.scope, instruction->base.source_node, casted_op1, casted_op2, casted_op3, expr_type);21491 return ir_build_mul_add_gen(ira, instruction->base.scope, instruction->base.source_node, casted_op1, casted_op2, casted_op3, expr_type);
21492}21492}
2149321493
21494static IrInstGen *ir_analyze_instruction_test_err(IrAnalyze *ira, IrInstSrcTestErr *instruction) {21494static Stage1AirInst *ir_analyze_instruction_test_err(IrAnalyze *ira, Stage1ZirInstTestErr *instruction) {
21495 IrInstGen *base_ptr = instruction->base_ptr->child;21495 Stage1AirInst *base_ptr = instruction->base_ptr->child;
21496 if (type_is_invalid(base_ptr->value->type))21496 if (type_is_invalid(base_ptr->value->type))
21497 return ira->codegen->invalid_inst_gen;21497 return ira->codegen->invalid_inst_gen;
2149821498
21499 IrInstGen *value;21499 Stage1AirInst *value;
21500 if (instruction->base_ptr_is_payload) {21500 if (instruction->base_ptr_is_payload) {
21501 value = base_ptr;21501 value = base_ptr;
21502 } else {21502 } else {
...@@ -21540,8 +21540,8 @@ static IrInstGen *ir_analyze_instruction_test_err(IrAnalyze *ira, IrInstSrcTestE...@@ -21540,8 +21540,8 @@ static IrInstGen *ir_analyze_instruction_test_err(IrAnalyze *ira, IrInstSrcTestE
21540 }21540 }
21541}21541}
2154221542
21543static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,21543static Stage1AirInst *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,
21544 IrInstGen *base_ptr, bool initializing)21544 Stage1AirInst *base_ptr, bool initializing)
21545{21545{
21546 ZigType *ptr_type = base_ptr->value->type;21546 ZigType *ptr_type = base_ptr->value->type;
2154721547
...@@ -21595,7 +21595,7 @@ static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNo...@@ -21595,7 +21595,7 @@ static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNo
21595 }21595 }
21596 src_assert(err_union_val->special != ConstValSpecialRuntime, source_node);21596 src_assert(err_union_val->special != ConstValSpecialRuntime, source_node);
2159721597
21598 IrInstGen *result;21598 Stage1AirInst *result;
21599 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {21599 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
21600 result = ir_build_unwrap_err_code_gen(ira, scope,21600 result = ir_build_unwrap_err_code_gen(ira, scope,
21601 source_node, base_ptr, result_type);21601 source_node, base_ptr, result_type);
...@@ -21614,15 +21614,15 @@ static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNo...@@ -21614,15 +21614,15 @@ static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNo
21614 return ir_build_unwrap_err_code_gen(ira, scope, source_node, base_ptr, result_type);21614 return ir_build_unwrap_err_code_gen(ira, scope, source_node, base_ptr, result_type);
21615}21615}
2161621616
21617static IrInstGen *ir_analyze_instruction_unwrap_err_code(IrAnalyze *ira, IrInstSrcUnwrapErrCode *instruction) {21617static Stage1AirInst *ir_analyze_instruction_unwrap_err_code(IrAnalyze *ira, Stage1ZirInstUnwrapErrCode *instruction) {
21618 IrInstGen *base_ptr = instruction->err_union_ptr->child;21618 Stage1AirInst *base_ptr = instruction->err_union_ptr->child;
21619 if (type_is_invalid(base_ptr->value->type))21619 if (type_is_invalid(base_ptr->value->type))
21620 return ira->codegen->invalid_inst_gen;21620 return ira->codegen->invalid_inst_gen;
21621 return ir_analyze_unwrap_err_code(ira, instruction->base.scope, instruction->base.source_node, base_ptr, false);21621 return ir_analyze_unwrap_err_code(ira, instruction->base.scope, instruction->base.source_node, base_ptr, false);
21622}21622}
2162321623
21624static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,21624static Stage1AirInst *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
21625 IrInstGen *base_ptr, bool safety_check_on, bool initializing)21625 Stage1AirInst *base_ptr, bool safety_check_on, bool initializing)
21626{21626{
21627 ZigType *ptr_type = base_ptr->value->type;21627 ZigType *ptr_type = base_ptr->value->type;
2162821628
...@@ -21680,7 +21680,7 @@ static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope,...@@ -21680,7 +21680,7 @@ static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope,
21680 return ira->codegen->invalid_inst_gen;21680 return ira->codegen->invalid_inst_gen;
21681 }21681 }
2168221682
21683 IrInstGen *result;21683 Stage1AirInst *result;
21684 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {21684 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
21685 result = ir_build_unwrap_err_payload_gen(ira, scope,21685 result = ir_build_unwrap_err_payload_gen(ira, scope,
21686 source_node, base_ptr, safety_check_on, initializing, result_type);21686 source_node, base_ptr, safety_check_on, initializing, result_type);
...@@ -21700,22 +21700,22 @@ static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope,...@@ -21700,22 +21700,22 @@ static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope,
21700 base_ptr, safety_check_on, initializing, result_type);21700 base_ptr, safety_check_on, initializing, result_type);
21701}21701}
2170221702
21703static IrInstGen *ir_analyze_instruction_unwrap_err_payload(IrAnalyze *ira,21703static Stage1AirInst *ir_analyze_instruction_unwrap_err_payload(IrAnalyze *ira,
21704 IrInstSrcUnwrapErrPayload *instruction)21704 Stage1ZirInstUnwrapErrPayload *instruction)
21705{21705{
21706 assert(instruction->value->child);21706 assert(instruction->value->child);
21707 IrInstGen *value = instruction->value->child;21707 Stage1AirInst *value = instruction->value->child;
21708 if (type_is_invalid(value->value->type))21708 if (type_is_invalid(value->value->type))
21709 return ira->codegen->invalid_inst_gen;21709 return ira->codegen->invalid_inst_gen;
2171021710
21711 return ir_analyze_unwrap_error_payload(ira, instruction->base.scope, instruction->base.source_node, value, instruction->safety_check_on, false);21711 return ir_analyze_unwrap_error_payload(ira, instruction->base.scope, instruction->base.source_node, value, instruction->safety_check_on, false);
21712}21712}
2171321713
21714static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnProto *instruction) {21714static Stage1AirInst *ir_analyze_instruction_fn_proto(IrAnalyze *ira, Stage1ZirInstFnProto *instruction) {
21715 AstNode *proto_node = instruction->base.source_node;21715 AstNode *proto_node = instruction->base.source_node;
21716 assert(proto_node->type == NodeTypeFnProto);21716 assert(proto_node->type == NodeTypeFnProto);
2171721717
21718 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);21718 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
21719 result->value->special = ConstValSpecialLazy;21719 result->value->special = ConstValSpecialLazy;
2172021720
21721 LazyValueFnType *lazy_fn_type = heap::c_allocator.create<LazyValueFnType>();21721 LazyValueFnType *lazy_fn_type = heap::c_allocator.create<LazyValueFnType>();
...@@ -21733,7 +21733,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro...@@ -21733,7 +21733,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro
21733 if (instruction->callconv_value != nullptr) {21733 if (instruction->callconv_value != nullptr) {
21734 ZigType *cc_enum_type = get_builtin_type(ira->codegen, "CallingConvention");21734 ZigType *cc_enum_type = get_builtin_type(ira->codegen, "CallingConvention");
2173521735
21736 IrInstGen *casted_value = ir_implicit_cast(ira, instruction->callconv_value->child, cc_enum_type);21736 Stage1AirInst *casted_value = ir_implicit_cast(ira, instruction->callconv_value->child, cc_enum_type);
21737 if (type_is_invalid(casted_value->value->type))21737 if (type_is_invalid(casted_value->value->type))
21738 return ira->codegen->invalid_inst_gen;21738 return ira->codegen->invalid_inst_gen;
2173921739
...@@ -21746,7 +21746,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro...@@ -21746,7 +21746,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro
2174621746
21747 size_t param_count = proto_node->data.fn_proto.params.length;21747 size_t param_count = proto_node->data.fn_proto.params.length;
21748 lazy_fn_type->proto_node = proto_node;21748 lazy_fn_type->proto_node = proto_node;
21749 lazy_fn_type->param_types = heap::c_allocator.allocate<IrInstGen *>(param_count);21749 lazy_fn_type->param_types = heap::c_allocator.allocate<Stage1AirInst *>(param_count);
2175021750
21751 for (size_t param_index = 0; param_index < param_count; param_index += 1) {21751 for (size_t param_index = 0; param_index < param_count; param_index += 1) {
21752 AstNode *param_node = proto_node->data.fn_proto.params.at(param_index);21752 AstNode *param_node = proto_node->data.fn_proto.params.at(param_index);
...@@ -21770,7 +21770,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro...@@ -21770,7 +21770,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro
21770 return result;21770 return result;
21771 }21771 }
2177221772
21773 IrInstGen *param_type_value = instruction->param_types[param_index]->child;21773 Stage1AirInst *param_type_value = instruction->param_types[param_index]->child;
21774 if (type_is_invalid(param_type_value->value->type))21774 if (type_is_invalid(param_type_value->value->type))
21775 return ira->codegen->invalid_inst_gen;21775 return ira->codegen->invalid_inst_gen;
21776 if (ir_resolve_const(ira, param_type_value, LazyOk) == nullptr)21776 if (ir_resolve_const(ira, param_type_value, LazyOk) == nullptr)
...@@ -21791,23 +21791,23 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro...@@ -21791,23 +21791,23 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro
21791 return result;21791 return result;
21792}21792}
2179321793
21794static IrInstGen *ir_analyze_instruction_test_comptime(IrAnalyze *ira, IrInstSrcTestComptime *instruction) {21794static Stage1AirInst *ir_analyze_instruction_test_comptime(IrAnalyze *ira, Stage1ZirInstTestComptime *instruction) {
21795 IrInstGen *value = instruction->value->child;21795 Stage1AirInst *value = instruction->value->child;
21796 if (type_is_invalid(value->value->type))21796 if (type_is_invalid(value->value->type))
21797 return ira->codegen->invalid_inst_gen;21797 return ira->codegen->invalid_inst_gen;
2179821798
21799 return ir_const_bool(ira, instruction->base.scope, instruction->base.source_node, instr_is_comptime(value));21799 return ir_const_bool(ira, instruction->base.scope, instruction->base.source_node, instr_is_comptime(value));
21800}21800}
2180121801
21802static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,21802static Stage1AirInst *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
21803 IrInstSrcCheckSwitchProngs *instruction, bool have_underscore_prong)21803 Stage1ZirInstCheckSwitchProngs *instruction, bool have_underscore_prong)
21804{21804{
21805 IrInstGen *target_value = instruction->target_value->child;21805 Stage1AirInst *target_value = instruction->target_value->child;
21806 ZigType *switch_type = target_value->value->type;21806 ZigType *switch_type = target_value->value->type;
21807 if (type_is_invalid(switch_type))21807 if (type_is_invalid(switch_type))
21808 return ira->codegen->invalid_inst_gen;21808 return ira->codegen->invalid_inst_gen;
2180921809
21810 ZigValue *original_value = ((IrInstSrcSwitchTarget *)(instruction->target_value))->target_value_ptr->child->value;21810 ZigValue *original_value = ((Stage1ZirInstSwitchTarget *)(instruction->target_value))->target_value_ptr->child->value;
21811 bool target_is_originally_union = original_value->type->id == ZigTypeIdPointer &&21811 bool target_is_originally_union = original_value->type->id == ZigTypeIdPointer &&
21812 original_value->type->data.pointer.child_type->id == ZigTypeIdUnion;21812 original_value->type->data.pointer.child_type->id == ZigTypeIdUnion;
2181321813
...@@ -21816,19 +21816,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,...@@ -21816,19 +21816,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
21816 field_prev_uses.init(switch_type->data.enumeration.src_field_count);21816 field_prev_uses.init(switch_type->data.enumeration.src_field_count);
2181721817
21818 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {21818 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {
21819 IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i];21819 Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i];
2182021820
21821 IrInstGen *start_value_uncasted = range->start->child;21821 Stage1AirInst *start_value_uncasted = range->start->child;
21822 if (type_is_invalid(start_value_uncasted->value->type))21822 if (type_is_invalid(start_value_uncasted->value->type))
21823 return ira->codegen->invalid_inst_gen;21823 return ira->codegen->invalid_inst_gen;
21824 IrInstGen *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type);21824 Stage1AirInst *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type);
21825 if (type_is_invalid(start_value->value->type))21825 if (type_is_invalid(start_value->value->type))
21826 return ira->codegen->invalid_inst_gen;21826 return ira->codegen->invalid_inst_gen;
2182721827
21828 IrInstGen *end_value_uncasted = range->end->child;21828 Stage1AirInst *end_value_uncasted = range->end->child;
21829 if (type_is_invalid(end_value_uncasted->value->type))21829 if (type_is_invalid(end_value_uncasted->value->type))
21830 return ira->codegen->invalid_inst_gen;21830 return ira->codegen->invalid_inst_gen;
21831 IrInstGen *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type);21831 Stage1AirInst *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type);
21832 if (type_is_invalid(end_value->value->type))21832 if (type_is_invalid(end_value->value->type))
21833 return ira->codegen->invalid_inst_gen;21833 return ira->codegen->invalid_inst_gen;
2183421834
...@@ -21914,19 +21914,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,...@@ -21914,19 +21914,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
21914 AstNode **field_prev_uses = heap::c_allocator.allocate<AstNode *>(field_prev_uses_count);21914 AstNode **field_prev_uses = heap::c_allocator.allocate<AstNode *>(field_prev_uses_count);
2191521915
21916 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {21916 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {
21917 IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i];21917 Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i];
2191821918
21919 IrInstGen *start_value_uncasted = range->start->child;21919 Stage1AirInst *start_value_uncasted = range->start->child;
21920 if (type_is_invalid(start_value_uncasted->value->type))21920 if (type_is_invalid(start_value_uncasted->value->type))
21921 return ira->codegen->invalid_inst_gen;21921 return ira->codegen->invalid_inst_gen;
21922 IrInstGen *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type);21922 Stage1AirInst *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type);
21923 if (type_is_invalid(start_value->value->type))21923 if (type_is_invalid(start_value->value->type))
21924 return ira->codegen->invalid_inst_gen;21924 return ira->codegen->invalid_inst_gen;
2192521925
21926 IrInstGen *end_value_uncasted = range->end->child;21926 Stage1AirInst *end_value_uncasted = range->end->child;
21927 if (type_is_invalid(end_value_uncasted->value->type))21927 if (type_is_invalid(end_value_uncasted->value->type))
21928 return ira->codegen->invalid_inst_gen;21928 return ira->codegen->invalid_inst_gen;
21929 IrInstGen *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type);21929 Stage1AirInst *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type);
21930 if (type_is_invalid(end_value->value->type))21930 if (type_is_invalid(end_value->value->type))
21931 return ira->codegen->invalid_inst_gen;21931 return ira->codegen->invalid_inst_gen;
2193221932
...@@ -21972,19 +21972,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,...@@ -21972,19 +21972,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
21972 } else if (switch_type->id == ZigTypeIdInt) {21972 } else if (switch_type->id == ZigTypeIdInt) {
21973 RangeSet rs = {0};21973 RangeSet rs = {0};
21974 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {21974 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {
21975 IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i];21975 Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i];
2197621976
21977 IrInstGen *start_value = range->start->child;21977 Stage1AirInst *start_value = range->start->child;
21978 if (type_is_invalid(start_value->value->type))21978 if (type_is_invalid(start_value->value->type))
21979 return ira->codegen->invalid_inst_gen;21979 return ira->codegen->invalid_inst_gen;
21980 IrInstGen *casted_start_value = ir_implicit_cast(ira, start_value, switch_type);21980 Stage1AirInst *casted_start_value = ir_implicit_cast(ira, start_value, switch_type);
21981 if (type_is_invalid(casted_start_value->value->type))21981 if (type_is_invalid(casted_start_value->value->type))
21982 return ira->codegen->invalid_inst_gen;21982 return ira->codegen->invalid_inst_gen;
2198321983
21984 IrInstGen *end_value = range->end->child;21984 Stage1AirInst *end_value = range->end->child;
21985 if (type_is_invalid(end_value->value->type))21985 if (type_is_invalid(end_value->value->type))
21986 return ira->codegen->invalid_inst_gen;21986 return ira->codegen->invalid_inst_gen;
21987 IrInstGen *casted_end_value = ir_implicit_cast(ira, end_value, switch_type);21987 Stage1AirInst *casted_end_value = ir_implicit_cast(ira, end_value, switch_type);
21988 if (type_is_invalid(casted_end_value->value->type))21988 if (type_is_invalid(casted_end_value->value->type))
21989 return ira->codegen->invalid_inst_gen;21989 return ira->codegen->invalid_inst_gen;
2199021990
...@@ -22030,11 +22030,11 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,...@@ -22030,11 +22030,11 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
22030 int seenTrue = 0;22030 int seenTrue = 0;
22031 int seenFalse = 0;22031 int seenFalse = 0;
22032 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {22032 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {
22033 IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i];22033 Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i];
2203422034
22035 IrInstGen *value = range->start->child;22035 Stage1AirInst *value = range->start->child;
2203622036
22037 IrInstGen *casted_value = ir_implicit_cast(ira, value, switch_type);22037 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, switch_type);
22038 if (type_is_invalid(casted_value->value->type))22038 if (type_is_invalid(casted_value->value->type))
22039 return ira->codegen->invalid_inst_gen;22039 return ira->codegen->invalid_inst_gen;
2204022040
...@@ -22070,15 +22070,15 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,...@@ -22070,15 +22070,15 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
22070 buf_sprintf("else prong required when switching on type '%s'", buf_ptr(&switch_type->name)));22070 buf_sprintf("else prong required when switching on type '%s'", buf_ptr(&switch_type->name)));
22071 return ira->codegen->invalid_inst_gen;22071 return ira->codegen->invalid_inst_gen;
22072 } else if(switch_type->id == ZigTypeIdMetaType) {22072 } else if(switch_type->id == ZigTypeIdMetaType) {
22073 HashMap<const ZigType*, IrInstGen*, type_ptr_hash, type_ptr_eql> prevs;22073 HashMap<const ZigType*, Stage1AirInst*, type_ptr_hash, type_ptr_eql> prevs;
22074 // HashMap doubles capacity when reaching 60% capacity,22074 // HashMap doubles capacity when reaching 60% capacity,
22075 // because we know the size at init we can avoid reallocation by doubling it here22075 // because we know the size at init we can avoid reallocation by doubling it here
22076 prevs.init(instruction->range_count * 2);22076 prevs.init(instruction->range_count * 2);
22077 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {22077 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {
22078 IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i];22078 Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i];
2207922079
22080 IrInstGen *value = range->start->child;22080 Stage1AirInst *value = range->start->child;
22081 IrInstGen *casted_value = ir_implicit_cast(ira, value, switch_type);22081 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, switch_type);
22082 if (type_is_invalid(casted_value->value->type)) {22082 if (type_is_invalid(casted_value->value->type)) {
22083 prevs.deinit();22083 prevs.deinit();
22084 return ira->codegen->invalid_inst_gen;22084 return ira->codegen->invalid_inst_gen;
...@@ -22103,10 +22103,10 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,...@@ -22103,10 +22103,10 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
22103 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);22103 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
22104}22104}
2210522105
22106static IrInstGen *ir_analyze_instruction_check_statement_is_void(IrAnalyze *ira,22106static Stage1AirInst *ir_analyze_instruction_check_statement_is_void(IrAnalyze *ira,
22107 IrInstSrcCheckStatementIsVoid *instruction)22107 Stage1ZirInstCheckStatementIsVoid *instruction)
22108{22108{
22109 IrInstGen *statement_value = instruction->statement_value->child;22109 Stage1AirInst *statement_value = instruction->statement_value->child;
22110 ZigType *statement_type = statement_value->value->type;22110 ZigType *statement_type = statement_value->value->type;
22111 if (type_is_invalid(statement_type))22111 if (type_is_invalid(statement_type))
22112 return ira->codegen->invalid_inst_gen;22112 return ira->codegen->invalid_inst_gen;
...@@ -22122,8 +22122,8 @@ static IrInstGen *ir_analyze_instruction_check_statement_is_void(IrAnalyze *ira,...@@ -22122,8 +22122,8 @@ static IrInstGen *ir_analyze_instruction_check_statement_is_void(IrAnalyze *ira,
22122 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);22122 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
22123}22123}
2212422124
22125static IrInstGen *ir_analyze_instruction_panic(IrAnalyze *ira, IrInstSrcPanic *instruction) {22125static Stage1AirInst *ir_analyze_instruction_panic(IrAnalyze *ira, Stage1ZirInstPanic *instruction) {
22126 IrInstGen *msg = instruction->msg->child;22126 Stage1AirInst *msg = instruction->msg->child;
22127 if (type_is_invalid(msg->value->type))22127 if (type_is_invalid(msg->value->type))
22128 return ir_unreach_error(ira);22128 return ir_unreach_error(ira);
2212922129
...@@ -22135,15 +22135,15 @@ static IrInstGen *ir_analyze_instruction_panic(IrAnalyze *ira, IrInstSrcPanic *i...@@ -22135,15 +22135,15 @@ static IrInstGen *ir_analyze_instruction_panic(IrAnalyze *ira, IrInstSrcPanic *i
22135 ZigType *u8_ptr_type = get_pointer_to_type_extra(ira->codegen, ira->codegen->builtin_types.entry_u8,22135 ZigType *u8_ptr_type = get_pointer_to_type_extra(ira->codegen, ira->codegen->builtin_types.entry_u8,
22136 true, false, PtrLenUnknown, 0, 0, 0, false);22136 true, false, PtrLenUnknown, 0, 0, 0, false);
22137 ZigType *str_type = get_slice_type(ira->codegen, u8_ptr_type);22137 ZigType *str_type = get_slice_type(ira->codegen, u8_ptr_type);
22138 IrInstGen *casted_msg = ir_implicit_cast(ira, msg, str_type);22138 Stage1AirInst *casted_msg = ir_implicit_cast(ira, msg, str_type);
22139 if (type_is_invalid(casted_msg->value->type))22139 if (type_is_invalid(casted_msg->value->type))
22140 return ir_unreach_error(ira);22140 return ir_unreach_error(ira);
2214122141
22142 IrInstGen *new_instruction = ir_build_panic_gen(ira, instruction->base.scope, instruction->base.source_node, casted_msg);22142 Stage1AirInst *new_instruction = ir_build_panic_gen(ira, instruction->base.scope, instruction->base.source_node, casted_msg);
22143 return ir_finish_anal(ira, new_instruction);22143 return ir_finish_anal(ira, new_instruction);
22144}22144}
2214522145
22146static IrInstGen *ir_align_cast(IrAnalyze *ira, IrInstGen *target, uint32_t align_bytes, bool safety_check_on) {22146static Stage1AirInst *ir_align_cast(IrAnalyze *ira, Stage1AirInst *target, uint32_t align_bytes, bool safety_check_on) {
22147 Error err;22147 Error err;
2214822148
22149 ZigType *target_type = target->value->type;22149 ZigType *target_type = target->value->type;
...@@ -22224,7 +22224,7 @@ static IrInstGen *ir_align_cast(IrAnalyze *ira, IrInstGen *target, uint32_t alig...@@ -22224,7 +22224,7 @@ static IrInstGen *ir_align_cast(IrAnalyze *ira, IrInstGen *target, uint32_t alig
22224 return ira->codegen->invalid_inst_gen;22224 return ira->codegen->invalid_inst_gen;
22225 }22225 }
2222622226
22227 IrInstGen *result = ir_const(ira, target->scope, target->source_node, result_type);22227 Stage1AirInst *result = ir_const(ira, target->scope, target->source_node, result_type);
22228 copy_const_val(ira->codegen, result->value, val);22228 copy_const_val(ira->codegen, result->value, val);
22229 result->value->type = result_type;22229 result->value->type = result_type;
22230 return result;22230 return result;
...@@ -22237,8 +22237,8 @@ static IrInstGen *ir_align_cast(IrAnalyze *ira, IrInstGen *target, uint32_t alig...@@ -22237,8 +22237,8 @@ static IrInstGen *ir_align_cast(IrAnalyze *ira, IrInstGen *target, uint32_t alig
22237 }22237 }
22238}22238}
2223922239
22240static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,22240static Stage1AirInst *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
22241 IrInstGen *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src,22241 Stage1AirInst *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src,
22242 bool safety_check_on, bool keep_bigger_alignment)22242 bool safety_check_on, bool keep_bigger_alignment)
22243{22243{
22244 Error err;22244 Error err;
...@@ -22312,8 +22312,8 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -22312,8 +22312,8 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
22312 // For slices, follow the `ptr` field.22312 // For slices, follow the `ptr` field.
22313 if (is_slice(src_type)) {22313 if (is_slice(src_type)) {
22314 TypeStructField *ptr_field = src_type->data.structure.fields[slice_ptr_index];22314 TypeStructField *ptr_field = src_type->data.structure.fields[slice_ptr_index];
22315 IrInstGen *ptr_ref = ir_get_ref(ira, scope, source_node, ptr, true, false);22315 Stage1AirInst *ptr_ref = ir_get_ref(ira, scope, source_node, ptr, true, false);
22316 IrInstGen *ptr_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, ptr_field, ptr_ref, src_type, false);22316 Stage1AirInst *ptr_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, ptr_field, ptr_ref, src_type, false);
22317 ptr = ir_get_deref(ira, scope, source_node, ptr_ptr, nullptr);22317 ptr = ir_get_deref(ira, scope, source_node, ptr_ptr, nullptr);
22318 }22318 }
2231922319
...@@ -22335,7 +22335,7 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -22335,7 +22335,7 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
22335 }22335 }
22336 }22336 }
2233722337
22338 IrInstGen *result;22338 Stage1AirInst *result;
22339 if (val->data.x_ptr.mut == ConstPtrMutInfer) {22339 if (val->data.x_ptr.mut == ConstPtrMutInfer) {
22340 result = ir_build_ptr_cast_gen(ira, scope, source_node, dest_type, ptr, safety_check_on);22340 result = ir_build_ptr_cast_gen(ira, scope, source_node, dest_type, ptr, safety_check_on);
22341 } else {22341 } else {
...@@ -22380,10 +22380,10 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -22380,10 +22380,10 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
22380 return ira->codegen->invalid_inst_gen;22380 return ira->codegen->invalid_inst_gen;
22381 }22381 }
2238222382
22383 IrInstGen *casted_ptr = ir_build_ptr_cast_gen(ira, scope, source_node, dest_type, ptr, safety_check_on);22383 Stage1AirInst *casted_ptr = ir_build_ptr_cast_gen(ira, scope, source_node, dest_type, ptr, safety_check_on);
2238422384
22385 // Keep the bigger alignment, it can only help- unless the target is zero bits.22385 // Keep the bigger alignment, it can only help- unless the target is zero bits.
22386 IrInstGen *result;22386 Stage1AirInst *result;
22387 if (keep_bigger_alignment && src_align_bytes > dest_align_bytes && type_has_bits(ira->codegen, dest_type)) {22387 if (keep_bigger_alignment && src_align_bytes > dest_align_bytes && type_has_bits(ira->codegen, dest_type)) {
22388 result = ir_align_cast(ira, casted_ptr, src_align_bytes, false);22388 result = ir_align_cast(ira, casted_ptr, src_align_bytes, false);
22389 if (type_is_invalid(result->value->type))22389 if (type_is_invalid(result->value->type))
...@@ -22394,13 +22394,13 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -22394,13 +22394,13 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
22394 return result;22394 return result;
22395}22395}
2239622396
22397static IrInstGen *ir_analyze_instruction_ptr_cast(IrAnalyze *ira, IrInstSrcPtrCast *instruction) {22397static Stage1AirInst *ir_analyze_instruction_ptr_cast(IrAnalyze *ira, Stage1ZirInstPtrCast *instruction) {
22398 IrInstGen *dest_type_value = instruction->dest_type->child;22398 Stage1AirInst *dest_type_value = instruction->dest_type->child;
22399 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);22399 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);
22400 if (type_is_invalid(dest_type))22400 if (type_is_invalid(dest_type))
22401 return ira->codegen->invalid_inst_gen;22401 return ira->codegen->invalid_inst_gen;
2240222402
22403 IrInstGen *ptr = instruction->ptr->child;22403 Stage1AirInst *ptr = instruction->ptr->child;
22404 ZigType *src_type = ptr->value->type;22404 ZigType *src_type = ptr->value->type;
22405 if (type_is_invalid(src_type))22405 if (type_is_invalid(src_type))
22406 return ira->codegen->invalid_inst_gen;22406 return ira->codegen->invalid_inst_gen;
...@@ -22762,7 +22762,7 @@ static Error buf_read_value_bytes(IrAnalyze *ira, CodeGen *codegen, AstNode *sou...@@ -22762,7 +22762,7 @@ static Error buf_read_value_bytes(IrAnalyze *ira, CodeGen *codegen, AstNode *sou
22762 zig_unreachable();22762 zig_unreachable();
22763}22763}
2276422764
22765static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,22765static Stage1AirInst *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
22766 ZigType *dest_type)22766 ZigType *dest_type)
22767{22767{
22768 Error err;22768 Error err;
...@@ -22813,7 +22813,7 @@ static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -22813,7 +22813,7 @@ static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
22813 if (!val)22813 if (!val)
22814 return ira->codegen->invalid_inst_gen;22814 return ira->codegen->invalid_inst_gen;
2281522815
22816 IrInstGen *result = ir_const(ira, scope, source_node, dest_type);22816 Stage1AirInst *result = ir_const(ira, scope, source_node, dest_type);
22817 uint8_t *buf = heap::c_allocator.allocate_nonzero<uint8_t>(src_size_bytes);22817 uint8_t *buf = heap::c_allocator.allocate_nonzero<uint8_t>(src_size_bytes);
22818 buf_write_value_bytes(ira->codegen, buf, val);22818 buf_write_value_bytes(ira->codegen, buf, val);
22819 if ((err = buf_read_value_bytes(ira, ira->codegen, source_node, buf, result->value)))22819 if ((err = buf_read_value_bytes(ira, ira->codegen, source_node, buf, result->value)))
...@@ -22830,7 +22830,7 @@ static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *sou...@@ -22830,7 +22830,7 @@ static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
22830 return ir_build_bit_cast_gen(ira, scope, source_node, value, dest_type);22830 return ir_build_bit_cast_gen(ira, scope, source_node, value, dest_type);
22831}22831}
2283222832
22833static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,22833static Stage1AirInst *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
22834 ZigType *ptr_type)22834 ZigType *ptr_type)
22835{22835{
22836 Error err;22836 Error err;
...@@ -22838,7 +22838,7 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -22838,7 +22838,7 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s
22838 src_assert(get_src_ptr_type(ptr_type) != nullptr, source_node);22838 src_assert(get_src_ptr_type(ptr_type) != nullptr, source_node);
22839 src_assert(type_has_bits(ira->codegen, ptr_type), source_node);22839 src_assert(type_has_bits(ira->codegen, ptr_type), source_node);
2284022840
22841 IrInstGen *casted_int = ir_implicit_cast(ira, target, ira->codegen->builtin_types.entry_usize);22841 Stage1AirInst *casted_int = ir_implicit_cast(ira, target, ira->codegen->builtin_types.entry_usize);
22842 if (type_is_invalid(casted_int->value->type))22842 if (type_is_invalid(casted_int->value->type))
22843 return ira->codegen->invalid_inst_gen;22843 return ira->codegen->invalid_inst_gen;
2284422844
...@@ -22865,7 +22865,7 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -22865,7 +22865,7 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s
22865 return ira->codegen->invalid_inst_gen;22865 return ira->codegen->invalid_inst_gen;
22866 }22866 }
2286722867
22868 IrInstGen *result = ir_const(ira, scope, source_node, ptr_type);22868 Stage1AirInst *result = ir_const(ira, scope, source_node, ptr_type);
22869 if (ptr_type->id == ZigTypeIdOptional && addr == 0) {22869 if (ptr_type->id == ZigTypeIdOptional && addr == 0) {
22870 result->value->data.x_ptr.special = ConstPtrSpecialNull;22870 result->value->data.x_ptr.special = ConstPtrSpecialNull;
22871 result->value->data.x_ptr.mut = ConstPtrMutComptimeConst;22871 result->value->data.x_ptr.mut = ConstPtrMutComptimeConst;
...@@ -22881,9 +22881,9 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s...@@ -22881,9 +22881,9 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s
22881 return ir_build_int_to_ptr_gen(ira, scope, source_node, casted_int, ptr_type);22881 return ir_build_int_to_ptr_gen(ira, scope, source_node, casted_int, ptr_type);
22882}22882}
2288322883
22884static IrInstGen *ir_analyze_instruction_int_to_ptr(IrAnalyze *ira, IrInstSrcIntToPtr *instruction) {22884static Stage1AirInst *ir_analyze_instruction_int_to_ptr(IrAnalyze *ira, Stage1ZirInstIntToPtr *instruction) {
22885 Error err;22885 Error err;
22886 IrInstGen *dest_type_value = instruction->dest_type->child;22886 Stage1AirInst *dest_type_value = instruction->dest_type->child;
22887 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);22887 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);
22888 if (type_is_invalid(dest_type))22888 if (type_is_invalid(dest_type))
22889 return ira->codegen->invalid_inst_gen;22889 return ira->codegen->invalid_inst_gen;
...@@ -22904,15 +22904,15 @@ static IrInstGen *ir_analyze_instruction_int_to_ptr(IrAnalyze *ira, IrInstSrcInt...@@ -22904,15 +22904,15 @@ static IrInstGen *ir_analyze_instruction_int_to_ptr(IrAnalyze *ira, IrInstSrcInt
22904 return ira->codegen->invalid_inst_gen;22904 return ira->codegen->invalid_inst_gen;
22905 }22905 }
2290622906
22907 IrInstGen *target = instruction->target->child;22907 Stage1AirInst *target = instruction->target->child;
22908 if (type_is_invalid(target->value->type))22908 if (type_is_invalid(target->value->type))
22909 return ira->codegen->invalid_inst_gen;22909 return ira->codegen->invalid_inst_gen;
2291022910
22911 return ir_analyze_int_to_ptr(ira, instruction->base.scope, instruction->base.source_node, target, dest_type);22911 return ir_analyze_int_to_ptr(ira, instruction->base.scope, instruction->base.source_node, target, dest_type);
22912}22912}
2291322913
22914static IrInstGen *ir_analyze_instruction_decl_ref(IrAnalyze *ira, IrInstSrcDeclRef *instruction) {22914static Stage1AirInst *ir_analyze_instruction_decl_ref(IrAnalyze *ira, Stage1ZirInstDeclRef *instruction) {
22915 IrInstGen *ref_instruction = ir_analyze_decl_ref(ira, instruction->base.scope, instruction->base.source_node, instruction->tld);22915 Stage1AirInst *ref_instruction = ir_analyze_decl_ref(ira, instruction->base.scope, instruction->base.source_node, instruction->tld);
22916 if (type_is_invalid(ref_instruction->value->type)) {22916 if (type_is_invalid(ref_instruction->value->type)) {
22917 return ira->codegen->invalid_inst_gen;22917 return ira->codegen->invalid_inst_gen;
22918 }22918 }
...@@ -22924,9 +22924,9 @@ static IrInstGen *ir_analyze_instruction_decl_ref(IrAnalyze *ira, IrInstSrcDeclR...@@ -22924,9 +22924,9 @@ static IrInstGen *ir_analyze_instruction_decl_ref(IrAnalyze *ira, IrInstSrcDeclR
22924 }22924 }
22925}22925}
2292622926
22927static IrInstGen *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, IrInstSrcPtrToInt *instruction) {22927static Stage1AirInst *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, Stage1ZirInstPtrToInt *instruction) {
22928 Error err;22928 Error err;
22929 IrInstGen *target = instruction->target->child;22929 Stage1AirInst *target = instruction->target->child;
22930 if (type_is_invalid(target->value->type))22930 if (type_is_invalid(target->value->type))
22931 return ira->codegen->invalid_inst_gen;22931 return ira->codegen->invalid_inst_gen;
2293222932
...@@ -22957,12 +22957,12 @@ static IrInstGen *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, IrInstSrcPtr...@@ -22957,12 +22957,12 @@ static IrInstGen *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, IrInstSrcPtr
22957 // Since we've already run this type trough get_src_ptr_type it is22957 // Since we've already run this type trough get_src_ptr_type it is
22958 // safe to access the x_ptr fields22958 // safe to access the x_ptr fields
22959 if (val->data.x_ptr.special == ConstPtrSpecialHardCodedAddr) {22959 if (val->data.x_ptr.special == ConstPtrSpecialHardCodedAddr) {
22960 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize);22960 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize);
22961 bigint_init_unsigned(&result->value->data.x_bigint, val->data.x_ptr.data.hard_coded_addr.addr);22961 bigint_init_unsigned(&result->value->data.x_bigint, val->data.x_ptr.data.hard_coded_addr.addr);
22962 result->value->type = usize;22962 result->value->type = usize;
22963 return result;22963 return result;
22964 } else if (val->data.x_ptr.special == ConstPtrSpecialNull) {22964 } else if (val->data.x_ptr.special == ConstPtrSpecialNull) {
22965 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize);22965 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize);
22966 bigint_init_unsigned(&result->value->data.x_bigint, 0);22966 bigint_init_unsigned(&result->value->data.x_bigint, 0);
22967 result->value->type = usize;22967 result->value->type = usize;
22968 return result;22968 return result;
...@@ -22972,10 +22972,10 @@ static IrInstGen *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, IrInstSrcPtr...@@ -22972,10 +22972,10 @@ static IrInstGen *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, IrInstSrcPtr
22972 return ir_build_ptr_to_int_gen(ira, instruction->base.scope, instruction->base.source_node, target);22972 return ir_build_ptr_to_int_gen(ira, instruction->base.scope, instruction->base.source_node, target);
22973}22973}
2297422974
22975static IrInstGen *ir_analyze_instruction_ptr_type_simple(IrAnalyze *ira,22975static Stage1AirInst *ir_analyze_instruction_ptr_type_simple(IrAnalyze *ira,
22976 IrInstSrcPtrTypeSimple *instruction, bool is_const)22976 Stage1ZirInstPtrTypeSimple *instruction, bool is_const)
22977{22977{
22978 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);22978 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
22979 result->value->special = ConstValSpecialLazy;22979 result->value->special = ConstValSpecialLazy;
2298022980
22981 LazyValuePtrTypeSimple *lazy_ptr_type = heap::c_allocator.create<LazyValuePtrTypeSimple>();22981 LazyValuePtrTypeSimple *lazy_ptr_type = heap::c_allocator.create<LazyValuePtrTypeSimple>();
...@@ -22990,8 +22990,8 @@ static IrInstGen *ir_analyze_instruction_ptr_type_simple(IrAnalyze *ira,...@@ -22990,8 +22990,8 @@ static IrInstGen *ir_analyze_instruction_ptr_type_simple(IrAnalyze *ira,
22990 return result;22990 return result;
22991}22991}
2299222992
22993static IrInstGen *ir_analyze_instruction_ptr_type(IrAnalyze *ira, IrInstSrcPtrType *instruction) {22993static Stage1AirInst *ir_analyze_instruction_ptr_type(IrAnalyze *ira, Stage1ZirInstPtrType *instruction) {
22994 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);22994 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
22995 result->value->special = ConstValSpecialLazy;22995 result->value->special = ConstValSpecialLazy;
2299622996
22997 LazyValuePtrType *lazy_ptr_type = heap::c_allocator.create<LazyValuePtrType>();22997 LazyValuePtrType *lazy_ptr_type = heap::c_allocator.create<LazyValuePtrType>();
...@@ -23031,8 +23031,8 @@ static IrInstGen *ir_analyze_instruction_ptr_type(IrAnalyze *ira, IrInstSrcPtrTy...@@ -23031,8 +23031,8 @@ static IrInstGen *ir_analyze_instruction_ptr_type(IrAnalyze *ira, IrInstSrcPtrTy
23031 return result;23031 return result;
23032}23032}
2303323033
23034static IrInstGen *ir_analyze_instruction_align_cast(IrAnalyze *ira, IrInstSrcAlignCast *instruction) {23034static Stage1AirInst *ir_analyze_instruction_align_cast(IrAnalyze *ira, Stage1ZirInstAlignCast *instruction) {
23035 IrInstGen *target = instruction->target->child;23035 Stage1AirInst *target = instruction->target->child;
23036 if (type_is_invalid(target->value->type))23036 if (type_is_invalid(target->value->type))
23037 return ira->codegen->invalid_inst_gen;23037 return ira->codegen->invalid_inst_gen;
2303823038
...@@ -23045,20 +23045,20 @@ static IrInstGen *ir_analyze_instruction_align_cast(IrAnalyze *ira, IrInstSrcAli...@@ -23045,20 +23045,20 @@ static IrInstGen *ir_analyze_instruction_align_cast(IrAnalyze *ira, IrInstSrcAli
23045 }23045 }
2304623046
23047 uint32_t align_bytes;23047 uint32_t align_bytes;
23048 IrInstGen *align_bytes_inst = instruction->align_bytes->child;23048 Stage1AirInst *align_bytes_inst = instruction->align_bytes->child;
23049 if (!ir_resolve_align(ira, align_bytes_inst, elem_type, &align_bytes))23049 if (!ir_resolve_align(ira, align_bytes_inst, elem_type, &align_bytes))
23050 return ira->codegen->invalid_inst_gen;23050 return ira->codegen->invalid_inst_gen;
2305123051
23052 IrInstGen *result = ir_align_cast(ira, target, align_bytes, true);23052 Stage1AirInst *result = ir_align_cast(ira, target, align_bytes, true);
23053 if (type_is_invalid(result->value->type))23053 if (type_is_invalid(result->value->type))
23054 return ira->codegen->invalid_inst_gen;23054 return ira->codegen->invalid_inst_gen;
2305523055
23056 return result;23056 return result;
23057}23057}
2305823058
23059static IrInstGen *ir_analyze_instruction_set_align_stack(IrAnalyze *ira, IrInstSrcSetAlignStack *instruction) {23059static Stage1AirInst *ir_analyze_instruction_set_align_stack(IrAnalyze *ira, Stage1ZirInstSetAlignStack *instruction) {
23060 uint32_t align_bytes;23060 uint32_t align_bytes;
23061 IrInstGen *align_bytes_inst = instruction->align_bytes->child;23061 Stage1AirInst *align_bytes_inst = instruction->align_bytes->child;
23062 if (!ir_resolve_align(ira, align_bytes_inst, nullptr, &align_bytes))23062 if (!ir_resolve_align(ira, align_bytes_inst, nullptr, &align_bytes))
23063 return ira->codegen->invalid_inst_gen;23063 return ira->codegen->invalid_inst_gen;
2306423064
...@@ -23095,15 +23095,15 @@ static IrInstGen *ir_analyze_instruction_set_align_stack(IrAnalyze *ira, IrInstS...@@ -23095,15 +23095,15 @@ static IrInstGen *ir_analyze_instruction_set_align_stack(IrAnalyze *ira, IrInstS
23095 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);23095 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
23096}23096}
2309723097
23098static IrInstGen *ir_analyze_instruction_arg_type(IrAnalyze *ira, IrInstSrcArgType *instruction,23098static Stage1AirInst *ir_analyze_instruction_arg_type(IrAnalyze *ira, Stage1ZirInstArgType *instruction,
23099 bool allow_var)23099 bool allow_var)
23100{23100{
23101 IrInstGen *fn_type_inst = instruction->fn_type->child;23101 Stage1AirInst *fn_type_inst = instruction->fn_type->child;
23102 ZigType *fn_type = ir_resolve_type(ira, fn_type_inst);23102 ZigType *fn_type = ir_resolve_type(ira, fn_type_inst);
23103 if (type_is_invalid(fn_type))23103 if (type_is_invalid(fn_type))
23104 return ira->codegen->invalid_inst_gen;23104 return ira->codegen->invalid_inst_gen;
2310523105
23106 IrInstGen *arg_index_inst = instruction->arg_index->child;23106 Stage1AirInst *arg_index_inst = instruction->arg_index->child;
23107 uint64_t arg_index;23107 uint64_t arg_index;
23108 if (!ir_resolve_usize(ira, arg_index_inst, &arg_index))23108 if (!ir_resolve_usize(ira, arg_index_inst, &arg_index))
23109 return ira->codegen->invalid_inst_gen;23109 return ira->codegen->invalid_inst_gen;
...@@ -23146,7 +23146,7 @@ static IrInstGen *ir_analyze_instruction_arg_type(IrAnalyze *ira, IrInstSrcArgTy...@@ -23146,7 +23146,7 @@ static IrInstGen *ir_analyze_instruction_arg_type(IrAnalyze *ira, IrInstSrcArgTy
23146 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, result_type);23146 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, result_type);
23147}23147}
2314823148
23149static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstGen *op) {23149static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, Stage1AirInst *op) {
23150 ZigType *operand_type = ir_resolve_type(ira, op);23150 ZigType *operand_type = ir_resolve_type(ira, op);
23151 if (type_is_invalid(operand_type))23151 if (type_is_invalid(operand_type))
23152 return ira->codegen->builtin_types.entry_invalid;23152 return ira->codegen->builtin_types.entry_invalid;
...@@ -23193,18 +23193,18 @@ static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstGen *op) {...@@ -23193,18 +23193,18 @@ static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstGen *op) {
23193 return operand_type;23193 return operand_type;
23194}23194}
2319523195
23196static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAtomicRmw *instruction) {23196static Stage1AirInst *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, Stage1ZirInstAtomicRmw *instruction) {
23197 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child);23197 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child);
23198 if (type_is_invalid(operand_type))23198 if (type_is_invalid(operand_type))
23199 return ira->codegen->invalid_inst_gen;23199 return ira->codegen->invalid_inst_gen;
2320023200
23201 IrInstGen *ptr_inst = instruction->ptr->child;23201 Stage1AirInst *ptr_inst = instruction->ptr->child;
23202 if (type_is_invalid(ptr_inst->value->type))23202 if (type_is_invalid(ptr_inst->value->type))
23203 return ira->codegen->invalid_inst_gen;23203 return ira->codegen->invalid_inst_gen;
2320423204
23205 // TODO let this be volatile23205 // TODO let this be volatile
23206 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false);23206 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false);
23207 IrInstGen *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);23207 Stage1AirInst *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);
23208 if (type_is_invalid(casted_ptr->value->type))23208 if (type_is_invalid(casted_ptr->value->type))
23209 return ira->codegen->invalid_inst_gen;23209 return ira->codegen->invalid_inst_gen;
2321023210
...@@ -23227,11 +23227,11 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto...@@ -23227,11 +23227,11 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
23227 return ira->codegen->invalid_inst_gen;23227 return ira->codegen->invalid_inst_gen;
23228 }23228 }
2322923229
23230 IrInstGen *operand = instruction->operand->child;23230 Stage1AirInst *operand = instruction->operand->child;
23231 if (type_is_invalid(operand->value->type))23231 if (type_is_invalid(operand->value->type))
23232 return ira->codegen->invalid_inst_gen;23232 return ira->codegen->invalid_inst_gen;
2323323233
23234 IrInstGen *casted_operand = ir_implicit_cast(ira, operand, operand_type);23234 Stage1AirInst *casted_operand = ir_implicit_cast(ira, operand, operand_type);
23235 if (type_is_invalid(casted_operand->value->type))23235 if (type_is_invalid(casted_operand->value->type))
23236 return ira->codegen->invalid_inst_gen;23236 return ira->codegen->invalid_inst_gen;
2323723237
...@@ -23269,7 +23269,7 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto...@@ -23269,7 +23269,7 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
23269 if (op2_val == nullptr)23269 if (op2_val == nullptr)
23270 return ira->codegen->invalid_inst_gen;23270 return ira->codegen->invalid_inst_gen;
2327123271
23272 IrInstGen *result = ir_const(ira, scope, source_node, operand_type);23272 Stage1AirInst *result = ir_const(ira, scope, source_node, operand_type);
23273 copy_const_val(ira->codegen, result->value, op1_val);23273 copy_const_val(ira->codegen, result->value, op1_val);
23274 if (op == AtomicRmwOp_xchg) {23274 if (op == AtomicRmwOp_xchg) {
23275 copy_const_val(ira->codegen, op1_val, op2_val);23275 copy_const_val(ira->codegen, op1_val, op2_val);
...@@ -23292,7 +23292,7 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto...@@ -23292,7 +23292,7 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
23292 // store op2 if op2 > op123292 // store op2 if op2 > op1
23293 bin_op = IrBinOpCmpLessThan;23293 bin_op = IrBinOpCmpLessThan;
2329423294
23295 IrInstGen *dummy_value = ir_const(ira, scope, source_node, operand_type);23295 Stage1AirInst *dummy_value = ir_const(ira, scope, source_node, operand_type);
23296 msg = ir_eval_bin_op_cmp_scalar(ira, scope, source_node, op1_val, bin_op, op2_val, dummy_value->value);23296 msg = ir_eval_bin_op_cmp_scalar(ira, scope, source_node, op1_val, bin_op, op2_val, dummy_value->value);
23297 if (msg != nullptr) {23297 if (msg != nullptr) {
23298 return ira->codegen->invalid_inst_gen;23298 return ira->codegen->invalid_inst_gen;
...@@ -23345,17 +23345,17 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto...@@ -23345,17 +23345,17 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
23345 ordering, operand_type);23345 ordering, operand_type);
23346}23346}
2334723347
23348static IrInstGen *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstSrcAtomicLoad *instruction) {23348static Stage1AirInst *ir_analyze_instruction_atomic_load(IrAnalyze *ira, Stage1ZirInstAtomicLoad *instruction) {
23349 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child);23349 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child);
23350 if (type_is_invalid(operand_type))23350 if (type_is_invalid(operand_type))
23351 return ira->codegen->invalid_inst_gen;23351 return ira->codegen->invalid_inst_gen;
2335223352
23353 IrInstGen *ptr_inst = instruction->ptr->child;23353 Stage1AirInst *ptr_inst = instruction->ptr->child;
23354 if (type_is_invalid(ptr_inst->value->type))23354 if (type_is_invalid(ptr_inst->value->type))
23355 return ira->codegen->invalid_inst_gen;23355 return ira->codegen->invalid_inst_gen;
2335623356
23357 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, true);23357 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, true);
23358 IrInstGen *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);23358 Stage1AirInst *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);
23359 if (type_is_invalid(casted_ptr->value->type))23359 if (type_is_invalid(casted_ptr->value->type))
23360 return ira->codegen->invalid_inst_gen;23360 return ira->codegen->invalid_inst_gen;
2336123361
...@@ -23371,7 +23371,7 @@ static IrInstGen *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstSrcAt...@@ -23371,7 +23371,7 @@ static IrInstGen *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstSrcAt
23371 }23371 }
2337223372
23373 if (instr_is_comptime(casted_ptr)) {23373 if (instr_is_comptime(casted_ptr)) {
23374 IrInstGen *result = ir_get_deref(ira, instruction->base.scope,23374 Stage1AirInst *result = ir_get_deref(ira, instruction->base.scope,
23375 instruction->base.source_node, casted_ptr, nullptr);23375 instruction->base.source_node, casted_ptr, nullptr);
23376 src_assert(result->value->type != nullptr, instruction->base.source_node);23376 src_assert(result->value->type != nullptr, instruction->base.source_node);
23377 return result;23377 return result;
...@@ -23380,25 +23380,25 @@ static IrInstGen *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstSrcAt...@@ -23380,25 +23380,25 @@ static IrInstGen *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstSrcAt
23380 return ir_build_atomic_load_gen(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, ordering, operand_type);23380 return ir_build_atomic_load_gen(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, ordering, operand_type);
23381}23381}
2338223382
23383static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcAtomicStore *instruction) {23383static Stage1AirInst *ir_analyze_instruction_atomic_store(IrAnalyze *ira, Stage1ZirInstAtomicStore *instruction) {
23384 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child);23384 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child);
23385 if (type_is_invalid(operand_type))23385 if (type_is_invalid(operand_type))
23386 return ira->codegen->invalid_inst_gen;23386 return ira->codegen->invalid_inst_gen;
2338723387
23388 IrInstGen *ptr_inst = instruction->ptr->child;23388 Stage1AirInst *ptr_inst = instruction->ptr->child;
23389 if (type_is_invalid(ptr_inst->value->type))23389 if (type_is_invalid(ptr_inst->value->type))
23390 return ira->codegen->invalid_inst_gen;23390 return ira->codegen->invalid_inst_gen;
2339123391
23392 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false);23392 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false);
23393 IrInstGen *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);23393 Stage1AirInst *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);
23394 if (type_is_invalid(casted_ptr->value->type))23394 if (type_is_invalid(casted_ptr->value->type))
23395 return ira->codegen->invalid_inst_gen;23395 return ira->codegen->invalid_inst_gen;
2339623396
23397 IrInstGen *value = instruction->value->child;23397 Stage1AirInst *value = instruction->value->child;
23398 if (type_is_invalid(value->value->type))23398 if (type_is_invalid(value->value->type))
23399 return ira->codegen->invalid_inst_gen;23399 return ira->codegen->invalid_inst_gen;
2340023400
23401 IrInstGen *casted_value = ir_implicit_cast(ira, value, operand_type);23401 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, operand_type);
23402 if (type_is_invalid(casted_value->value->type))23402 if (type_is_invalid(casted_value->value->type))
23403 return ira->codegen->invalid_inst_gen;23403 return ira->codegen->invalid_inst_gen;
2340423404
...@@ -23425,7 +23425,7 @@ static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcA...@@ -23425,7 +23425,7 @@ static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcA
23425 }23425 }
2342623426
23427 if (instr_is_comptime(casted_value) && instr_is_comptime(casted_ptr)) {23427 if (instr_is_comptime(casted_value) && instr_is_comptime(casted_ptr)) {
23428 IrInstGen *result = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, value, false);23428 Stage1AirInst *result = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, value, false);
23429 result->value->type = ira->codegen->builtin_types.entry_void;23429 result->value->type = ira->codegen->builtin_types.entry_void;
23430 return result;23430 return result;
23431 }23431 }
...@@ -23433,7 +23433,7 @@ static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcA...@@ -23433,7 +23433,7 @@ static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcA
23433 return ir_build_atomic_store_gen(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, casted_value, ordering);23433 return ir_build_atomic_store_gen(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, casted_value, ordering);
23434}23434}
2343523435
23436static IrInstGen *ir_analyze_instruction_save_err_ret_addr(IrAnalyze *ira, IrInstSrcSaveErrRetAddr *instruction) {23436static Stage1AirInst *ir_analyze_instruction_save_err_ret_addr(IrAnalyze *ira, Stage1ZirInstSaveErrRetAddr *instruction) {
23437 return ir_build_save_err_ret_addr_gen(ira, instruction->base.scope, instruction->base.source_node);23437 return ir_build_save_err_ret_addr_gen(ira, instruction->base.scope, instruction->base.source_node);
23438}23438}
2343923439
...@@ -23660,8 +23660,8 @@ static ErrorMsg *ir_eval_float_op(IrAnalyze *ira, Scope *scope, AstNode *source_...@@ -23660,8 +23660,8 @@ static ErrorMsg *ir_eval_float_op(IrAnalyze *ira, Scope *scope, AstNode *source_
23660 return nullptr;23660 return nullptr;
23661}23661}
2366223662
23663static IrInstGen *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstSrcFloatOp *instruction) {23663static Stage1AirInst *ir_analyze_instruction_float_op(IrAnalyze *ira, Stage1ZirInstFloatOp *instruction) {
23664 IrInstGen *operand = instruction->operand->child;23664 Stage1AirInst *operand = instruction->operand->child;
23665 ZigType *operand_type = operand->value->type;23665 ZigType *operand_type = operand->value->type;
23666 if (type_is_invalid(operand_type))23666 if (type_is_invalid(operand_type))
23667 return ira->codegen->invalid_inst_gen;23667 return ira->codegen->invalid_inst_gen;
...@@ -23683,7 +23683,7 @@ static IrInstGen *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstSrcFloat...@@ -23683,7 +23683,7 @@ static IrInstGen *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstSrcFloat
23683 if (operand_val->special == ConstValSpecialUndef)23683 if (operand_val->special == ConstValSpecialUndef)
23684 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, operand_type);23684 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, operand_type);
2368523685
23686 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, operand_type);23686 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, operand_type);
23687 ZigValue *out_val = result->value;23687 ZigValue *out_val = result->value;
2368823688
23689 if (operand_type->id == ZigTypeIdVector) {23689 if (operand_type->id == ZigTypeIdVector) {
...@@ -23722,14 +23722,14 @@ static IrInstGen *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstSrcFloat...@@ -23722,14 +23722,14 @@ static IrInstGen *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstSrcFloat
23722 return ir_build_float_op_gen(ira, instruction->base.scope, instruction->base.source_node, operand, instruction->fn_id, operand_type);23722 return ir_build_float_op_gen(ira, instruction->base.scope, instruction->base.source_node, operand, instruction->fn_id, operand_type);
23723}23723}
2372423724
23725static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *instruction) {23725static Stage1AirInst *ir_analyze_instruction_bswap(IrAnalyze *ira, Stage1ZirInstBswap *instruction) {
23726 Error err;23726 Error err;
2372723727
23728 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);23728 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
23729 if (type_is_invalid(int_type))23729 if (type_is_invalid(int_type))
23730 return ira->codegen->invalid_inst_gen;23730 return ira->codegen->invalid_inst_gen;
2373123731
23732 IrInstGen *uncasted_op = instruction->op->child;23732 Stage1AirInst *uncasted_op = instruction->op->child;
23733 if (type_is_invalid(uncasted_op->value->type))23733 if (type_is_invalid(uncasted_op->value->type))
23734 return ira->codegen->invalid_inst_gen;23734 return ira->codegen->invalid_inst_gen;
2373523735
...@@ -23751,7 +23751,7 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i...@@ -23751,7 +23751,7 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i
23751 bool is_vector = (vector_len != UINT32_MAX);23751 bool is_vector = (vector_len != UINT32_MAX);
23752 ZigType *op_type = is_vector ? get_vector_type(ira->codegen, vector_len, int_type) : int_type;23752 ZigType *op_type = is_vector ? get_vector_type(ira->codegen, vector_len, int_type) : int_type;
2375323753
23754 IrInstGen *op = ir_implicit_cast(ira, uncasted_op, op_type);23754 Stage1AirInst *op = ir_implicit_cast(ira, uncasted_op, op_type);
23755 if (type_is_invalid(op->value->type))23755 if (type_is_invalid(op->value->type))
23756 return ira->codegen->invalid_inst_gen;23756 return ira->codegen->invalid_inst_gen;
2375723757
...@@ -23772,7 +23772,7 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i...@@ -23772,7 +23772,7 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i
23772 if (val->special == ConstValSpecialUndef)23772 if (val->special == ConstValSpecialUndef)
23773 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, op_type);23773 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, op_type);
2377423774
23775 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, op_type);23775 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, op_type);
23776 const size_t buf_size = int_type->data.integral.bit_count / 8;23776 const size_t buf_size = int_type->data.integral.bit_count / 8;
23777 uint8_t *buf = heap::c_allocator.allocate_nonzero<uint8_t>(buf_size);23777 uint8_t *buf = heap::c_allocator.allocate_nonzero<uint8_t>(buf_size);
23778 if (is_vector) {23778 if (is_vector) {
...@@ -23808,17 +23808,17 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i...@@ -23808,17 +23808,17 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i
23808 return ir_build_bswap_gen(ira, instruction->base.scope, instruction->base.source_node, op_type, op);23808 return ir_build_bswap_gen(ira, instruction->base.scope, instruction->base.source_node, op_type, op);
23809}23809}
2381023810
23811static IrInstGen *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, IrInstSrcBitReverse *instruction) {23811static Stage1AirInst *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, Stage1ZirInstBitReverse *instruction) {
23812 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);23812 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
23813 if (type_is_invalid(int_type))23813 if (type_is_invalid(int_type))
23814 return ira->codegen->invalid_inst_gen;23814 return ira->codegen->invalid_inst_gen;
2381523815
23816 IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type);23816 Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type);
23817 if (type_is_invalid(op->value->type))23817 if (type_is_invalid(op->value->type))
23818 return ira->codegen->invalid_inst_gen;23818 return ira->codegen->invalid_inst_gen;
2381923819
23820 if (int_type->data.integral.bit_count == 0) {23820 if (int_type->data.integral.bit_count == 0) {
23821 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type);23821 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type);
23822 bigint_init_unsigned(&result->value->data.x_bigint, 0);23822 bigint_init_unsigned(&result->value->data.x_bigint, 0);
23823 return result;23823 return result;
23824 }23824 }
...@@ -23830,7 +23830,7 @@ static IrInstGen *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, IrInstSrcBi...@@ -23830,7 +23830,7 @@ static IrInstGen *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, IrInstSrcBi
23830 if (val->special == ConstValSpecialUndef)23830 if (val->special == ConstValSpecialUndef)
23831 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, int_type);23831 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, int_type);
2383223832
23833 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type);23833 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type);
23834 size_t num_bits = int_type->data.integral.bit_count;23834 size_t num_bits = int_type->data.integral.bit_count;
23835 size_t buf_size = (num_bits + 7) / 8;23835 size_t buf_size = (num_bits + 7) / 8;
23836 uint8_t *comptime_buf = heap::c_allocator.allocate_nonzero<uint8_t>(buf_size);23836 uint8_t *comptime_buf = heap::c_allocator.allocate_nonzero<uint8_t>(buf_size);
...@@ -23863,17 +23863,17 @@ static IrInstGen *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, IrInstSrcBi...@@ -23863,17 +23863,17 @@ static IrInstGen *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, IrInstSrcBi
23863}23863}
2386423864
2386523865
23866static IrInstGen *ir_analyze_instruction_enum_to_int(IrAnalyze *ira, IrInstSrcEnumToInt *instruction) {23866static Stage1AirInst *ir_analyze_instruction_enum_to_int(IrAnalyze *ira, Stage1ZirInstEnumToInt *instruction) {
23867 IrInstGen *target = instruction->target->child;23867 Stage1AirInst *target = instruction->target->child;
23868 if (type_is_invalid(target->value->type))23868 if (type_is_invalid(target->value->type))
23869 return ira->codegen->invalid_inst_gen;23869 return ira->codegen->invalid_inst_gen;
2387023870
23871 return ir_analyze_enum_to_int(ira, instruction->base.scope, instruction->base.source_node, target);23871 return ir_analyze_enum_to_int(ira, instruction->base.scope, instruction->base.source_node, target);
23872}23872}
2387323873
23874static IrInstGen *ir_analyze_instruction_int_to_enum(IrAnalyze *ira, IrInstSrcIntToEnum *instruction) {23874static Stage1AirInst *ir_analyze_instruction_int_to_enum(IrAnalyze *ira, Stage1ZirInstIntToEnum *instruction) {
23875 Error err;23875 Error err;
23876 IrInstGen *dest_type_value = instruction->dest_type->child;23876 Stage1AirInst *dest_type_value = instruction->dest_type->child;
23877 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);23877 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);
23878 if (type_is_invalid(dest_type))23878 if (type_is_invalid(dest_type))
23879 return ira->codegen->invalid_inst_gen;23879 return ira->codegen->invalid_inst_gen;
...@@ -23889,24 +23889,24 @@ static IrInstGen *ir_analyze_instruction_int_to_enum(IrAnalyze *ira, IrInstSrcIn...@@ -23889,24 +23889,24 @@ static IrInstGen *ir_analyze_instruction_int_to_enum(IrAnalyze *ira, IrInstSrcIn
2388923889
23890 ZigType *tag_type = dest_type->data.enumeration.tag_int_type;23890 ZigType *tag_type = dest_type->data.enumeration.tag_int_type;
2389123891
23892 IrInstGen *target = instruction->target->child;23892 Stage1AirInst *target = instruction->target->child;
23893 if (type_is_invalid(target->value->type))23893 if (type_is_invalid(target->value->type))
23894 return ira->codegen->invalid_inst_gen;23894 return ira->codegen->invalid_inst_gen;
2389523895
23896 IrInstGen *casted_target = ir_implicit_cast(ira, target, tag_type);23896 Stage1AirInst *casted_target = ir_implicit_cast(ira, target, tag_type);
23897 if (type_is_invalid(casted_target->value->type))23897 if (type_is_invalid(casted_target->value->type))
23898 return ira->codegen->invalid_inst_gen;23898 return ira->codegen->invalid_inst_gen;
2389923899
23900 return ir_analyze_int_to_enum(ira, instruction->base.scope, instruction->base.source_node, casted_target, dest_type);23900 return ir_analyze_int_to_enum(ira, instruction->base.scope, instruction->base.source_node, casted_target, dest_type);
23901}23901}
2390223902
23903static IrInstGen *ir_analyze_instruction_check_runtime_scope(IrAnalyze *ira, IrInstSrcCheckRuntimeScope *instruction) {23903static Stage1AirInst *ir_analyze_instruction_check_runtime_scope(IrAnalyze *ira, Stage1ZirInstCheckRuntimeScope *instruction) {
23904 IrInstGen *block_comptime_inst = instruction->scope_is_comptime->child;23904 Stage1AirInst *block_comptime_inst = instruction->scope_is_comptime->child;
23905 bool scope_is_comptime;23905 bool scope_is_comptime;
23906 if (!ir_resolve_bool(ira, block_comptime_inst, &scope_is_comptime))23906 if (!ir_resolve_bool(ira, block_comptime_inst, &scope_is_comptime))
23907 return ira->codegen->invalid_inst_gen;23907 return ira->codegen->invalid_inst_gen;
2390823908
23909 IrInstGen *is_comptime_inst = instruction->is_comptime->child;23909 Stage1AirInst *is_comptime_inst = instruction->is_comptime->child;
23910 bool is_comptime;23910 bool is_comptime;
23911 if (!ir_resolve_bool(ira, is_comptime_inst, &is_comptime))23911 if (!ir_resolve_bool(ira, is_comptime_inst, &is_comptime))
23912 return ira->codegen->invalid_inst_gen;23912 return ira->codegen->invalid_inst_gen;
...@@ -23922,7 +23922,7 @@ static IrInstGen *ir_analyze_instruction_check_runtime_scope(IrAnalyze *ira, IrI...@@ -23922,7 +23922,7 @@ static IrInstGen *ir_analyze_instruction_check_runtime_scope(IrAnalyze *ira, IrI
23922 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);23922 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
23923}23923}
2392423924
23925static IrInstGen *ir_analyze_instruction_has_decl(IrAnalyze *ira, IrInstSrcHasDecl *instruction) {23925static Stage1AirInst *ir_analyze_instruction_has_decl(IrAnalyze *ira, Stage1ZirInstHasDecl *instruction) {
23926 ZigType *container_type = ir_resolve_type(ira, instruction->container->child);23926 ZigType *container_type = ir_resolve_type(ira, instruction->container->child);
23927 if (type_is_invalid(container_type))23927 if (type_is_invalid(container_type))
23928 return ira->codegen->invalid_inst_gen;23928 return ira->codegen->invalid_inst_gen;
...@@ -23965,7 +23965,7 @@ static void populate_invalid_variable_in_scope(CodeGen *g, Scope *scope, AstNode...@@ -23965,7 +23965,7 @@ static void populate_invalid_variable_in_scope(CodeGen *g, Scope *scope, AstNode
23965 scope_decls->decl_table.put(var_name, &tld_var->base);23965 scope_decls->decl_table.put(var_name, &tld_var->base);
23966}23966}
2396723967
23968static IrInstGen *ir_analyze_instruction_undeclared_ident(IrAnalyze *ira, IrInstSrcUndeclaredIdent *instruction) {23968static Stage1AirInst *ir_analyze_instruction_undeclared_ident(IrAnalyze *ira, Stage1ZirInstUndeclaredIdent *instruction) {
23969 // put a variable of same name with invalid type in global scope23969 // put a variable of same name with invalid type in global scope
23970 // so that future references to this same name will find a variable with an invalid type23970 // so that future references to this same name will find a variable with an invalid type
23971 populate_invalid_variable_in_scope(ira->codegen, instruction->base.scope,23971 populate_invalid_variable_in_scope(ira->codegen, instruction->base.scope,
...@@ -23975,13 +23975,13 @@ static IrInstGen *ir_analyze_instruction_undeclared_ident(IrAnalyze *ira, IrInst...@@ -23975,13 +23975,13 @@ static IrInstGen *ir_analyze_instruction_undeclared_ident(IrAnalyze *ira, IrInst
23975 return ira->codegen->invalid_inst_gen;23975 return ira->codegen->invalid_inst_gen;
23976}23976}
2397723977
23978static IrInstGen *ir_analyze_instruction_end_expr(IrAnalyze *ira, IrInstSrcEndExpr *instruction) {23978static Stage1AirInst *ir_analyze_instruction_end_expr(IrAnalyze *ira, Stage1ZirInstEndExpr *instruction) {
23979 IrInstGen *value = instruction->value->child;23979 Stage1AirInst *value = instruction->value->child;
23980 if (type_is_invalid(value->value->type))23980 if (type_is_invalid(value->value->type))
23981 return ira->codegen->invalid_inst_gen;23981 return ira->codegen->invalid_inst_gen;
2398223982
23983 bool was_written = instruction->result_loc->written;23983 bool was_written = instruction->result_loc->written;
23984 IrInstGen *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,23984 Stage1AirInst *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
23985 value->value->type, value, false, true);23985 value->value->type, value, false, true);
23986 if (result_loc != nullptr) {23986 if (result_loc != nullptr) {
23987 if (type_is_invalid(result_loc->value->type))23987 if (type_is_invalid(result_loc->value->type))
...@@ -23990,7 +23990,7 @@ static IrInstGen *ir_analyze_instruction_end_expr(IrAnalyze *ira, IrInstSrcEndEx...@@ -23990,7 +23990,7 @@ static IrInstGen *ir_analyze_instruction_end_expr(IrAnalyze *ira, IrInstSrcEndEx
23990 return result_loc;23990 return result_loc;
2399123991
23992 if (!was_written || instruction->result_loc->id == ResultLocIdPeer) {23992 if (!was_written || instruction->result_loc->id == ResultLocIdPeer) {
23993 IrInstGen *store_ptr = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, result_loc, value,23993 Stage1AirInst *store_ptr = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, result_loc, value,
23994 instruction->result_loc->allow_write_through_const);23994 instruction->result_loc->allow_write_through_const);
23995 if (type_is_invalid(store_ptr->value->type)) {23995 if (type_is_invalid(store_ptr->value->type)) {
23996 if (instruction->result_loc->id == ResultLocIdReturn &&23996 if (instruction->result_loc->id == ResultLocIdReturn &&
...@@ -24018,8 +24018,8 @@ static IrInstGen *ir_analyze_instruction_end_expr(IrAnalyze *ira, IrInstSrcEndEx...@@ -24018,8 +24018,8 @@ static IrInstGen *ir_analyze_instruction_end_expr(IrAnalyze *ira, IrInstSrcEndEx
24018 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);24018 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
24019}24019}
2402024020
24021static IrInstGen *ir_analyze_instruction_implicit_cast(IrAnalyze *ira, IrInstSrcImplicitCast *instruction) {24021static Stage1AirInst *ir_analyze_instruction_implicit_cast(IrAnalyze *ira, Stage1ZirInstImplicitCast *instruction) {
24022 IrInstGen *operand = instruction->operand->child;24022 Stage1AirInst *operand = instruction->operand->child;
24023 if (type_is_invalid(operand->value->type))24023 if (type_is_invalid(operand->value->type))
24024 return operand;24024 return operand;
2402524025
...@@ -24030,12 +24030,12 @@ static IrInstGen *ir_analyze_instruction_implicit_cast(IrAnalyze *ira, IrInstSrc...@@ -24030,12 +24030,12 @@ static IrInstGen *ir_analyze_instruction_implicit_cast(IrAnalyze *ira, IrInstSrc
24030 operand, dest_type);24030 operand, dest_type);
24031}24031}
2403224032
24033static IrInstGen *ir_analyze_instruction_bit_cast_src(IrAnalyze *ira, IrInstSrcBitCast *instruction) {24033static Stage1AirInst *ir_analyze_instruction_bit_cast_src(IrAnalyze *ira, Stage1ZirInstBitCast *instruction) {
24034 IrInstGen *operand = instruction->operand->child;24034 Stage1AirInst *operand = instruction->operand->child;
24035 if (type_is_invalid(operand->value->type))24035 if (type_is_invalid(operand->value->type))
24036 return operand;24036 return operand;
2403724037
24038 IrInstGen *result_loc = ir_resolve_result(ira, &instruction->base,24038 Stage1AirInst *result_loc = ir_resolve_result(ira, &instruction->base,
24039 &instruction->result_loc_bit_cast->base, operand->value->type, operand, false, true);24039 &instruction->result_loc_bit_cast->base, operand->value->type, operand, false, true);
24040 if (result_loc != nullptr &&24040 if (result_loc != nullptr &&
24041 (type_is_invalid(result_loc->value->type) || result_loc->value->type->id == ZigTypeIdUnreachable))24041 (type_is_invalid(result_loc->value->type) || result_loc->value->type->id == ZigTypeIdUnreachable))
...@@ -24050,8 +24050,8 @@ static IrInstGen *ir_analyze_instruction_bit_cast_src(IrAnalyze *ira, IrInstSrcB...@@ -24050,8 +24050,8 @@ static IrInstGen *ir_analyze_instruction_bit_cast_src(IrAnalyze *ira, IrInstSrcB
24050 return ir_analyze_bit_cast(ira, instruction->base.scope, instruction->base.source_node, operand, dest_type);24050 return ir_analyze_bit_cast(ira, instruction->base.scope, instruction->base.source_node, operand, dest_type);
24051}24051}
2405224052
24053static IrInstGen *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira,24053static Stage1AirInst *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira,
24054 IrInstSrcUnionInitNamedField *instruction)24054 Stage1ZirInstUnionInitNamedField *instruction)
24055{24055{
24056 ZigType *union_type = ir_resolve_type(ira, instruction->union_type->child);24056 ZigType *union_type = ir_resolve_type(ira, instruction->union_type->child);
24057 if (type_is_invalid(union_type))24057 if (type_is_invalid(union_type))
...@@ -24067,11 +24067,11 @@ static IrInstGen *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira,...@@ -24067,11 +24067,11 @@ static IrInstGen *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira,
24067 if (field_name == nullptr)24067 if (field_name == nullptr)
24068 return ira->codegen->invalid_inst_gen;24068 return ira->codegen->invalid_inst_gen;
2406924069
24070 IrInstGen *field_result_loc = instruction->field_result_loc->child;24070 Stage1AirInst *field_result_loc = instruction->field_result_loc->child;
24071 if (type_is_invalid(field_result_loc->value->type))24071 if (type_is_invalid(field_result_loc->value->type))
24072 return ira->codegen->invalid_inst_gen;24072 return ira->codegen->invalid_inst_gen;
2407324073
24074 IrInstGen *result_loc = instruction->result_loc->child;24074 Stage1AirInst *result_loc = instruction->result_loc->child;
24075 if (type_is_invalid(result_loc->value->type))24075 if (type_is_invalid(result_loc->value->type))
24076 return ira->codegen->invalid_inst_gen;24076 return ira->codegen->invalid_inst_gen;
2407724077
...@@ -24079,16 +24079,16 @@ static IrInstGen *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira,...@@ -24079,16 +24079,16 @@ static IrInstGen *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira,
24079 union_type, field_name, field_result_loc, result_loc);24079 union_type, field_name, field_result_loc, result_loc);
24080}24080}
2408124081
24082static IrInstGen *ir_analyze_instruction_suspend_begin(IrAnalyze *ira, IrInstSrcSuspendBegin *instruction) {24082static Stage1AirInst *ir_analyze_instruction_suspend_begin(IrAnalyze *ira, Stage1ZirInstSuspendBegin *instruction) {
24083 return ir_build_suspend_begin_gen(ira, instruction->base.scope, instruction->base.source_node);24083 return ir_build_suspend_begin_gen(ira, instruction->base.scope, instruction->base.source_node);
24084}24084}
2408524085
24086static IrInstGen *ir_analyze_instruction_suspend_finish(IrAnalyze *ira, IrInstSrcSuspendFinish *instruction) {24086static Stage1AirInst *ir_analyze_instruction_suspend_finish(IrAnalyze *ira, Stage1ZirInstSuspendFinish *instruction) {
24087 IrInstGen *begin_base = instruction->begin->base.child;24087 Stage1AirInst *begin_base = instruction->begin->base.child;
24088 if (type_is_invalid(begin_base->value->type))24088 if (type_is_invalid(begin_base->value->type))
24089 return ira->codegen->invalid_inst_gen;24089 return ira->codegen->invalid_inst_gen;
24090 src_assert(begin_base->id == IrInstGenIdSuspendBegin, instruction->base.source_node);24090 src_assert(begin_base->id == Stage1AirInstIdSuspendBegin, instruction->base.source_node);
24091 IrInstGenSuspendBegin *begin = reinterpret_cast<IrInstGenSuspendBegin *>(begin_base);24091 Stage1AirInstSuspendBegin *begin = reinterpret_cast<Stage1AirInstSuspendBegin *>(begin_base);
2409224092
24093 ZigFn *fn_entry = ira->fn;24093 ZigFn *fn_entry = ira->fn;
24094 src_assert(fn_entry != nullptr, instruction->base.source_node);24094 src_assert(fn_entry != nullptr, instruction->base.source_node);
...@@ -24100,8 +24100,8 @@ static IrInstGen *ir_analyze_instruction_suspend_finish(IrAnalyze *ira, IrInstSr...@@ -24100,8 +24100,8 @@ static IrInstGen *ir_analyze_instruction_suspend_finish(IrAnalyze *ira, IrInstSr
24100 return ir_build_suspend_finish_gen(ira, instruction->base.scope, instruction->base.source_node, begin);24100 return ir_build_suspend_finish_gen(ira, instruction->base.scope, instruction->base.source_node, begin);
24101}24101}
2410224102
24103static IrInstGen *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope, AstNode *source_node,24103static Stage1AirInst *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope, AstNode *source_node,
24104 IrInstGen *frame_ptr, ZigFn **target_fn)24104 Stage1AirInst *frame_ptr, ZigFn **target_fn)
24105{24105{
24106 if (type_is_invalid(frame_ptr->value->type))24106 if (type_is_invalid(frame_ptr->value->type))
24107 return ira->codegen->invalid_inst_gen;24107 return ira->codegen->invalid_inst_gen;
...@@ -24109,7 +24109,7 @@ static IrInstGen *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope,...@@ -24109,7 +24109,7 @@ static IrInstGen *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope,
24109 *target_fn = nullptr;24109 *target_fn = nullptr;
2411024110
24111 ZigType *result_type;24111 ZigType *result_type;
24112 IrInstGen *frame;24112 Stage1AirInst *frame;
24113 if (frame_ptr->value->type->id == ZigTypeIdPointer &&24113 if (frame_ptr->value->type->id == ZigTypeIdPointer &&
24114 frame_ptr->value->type->data.pointer.ptr_len == PtrLenSingle &&24114 frame_ptr->value->type->data.pointer.ptr_len == PtrLenSingle &&
24115 frame_ptr->value->type->data.pointer.child_type->id == ZigTypeIdFnFrame)24115 frame_ptr->value->type->data.pointer.child_type->id == ZigTypeIdFnFrame)
...@@ -24139,19 +24139,19 @@ static IrInstGen *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope,...@@ -24139,19 +24139,19 @@ static IrInstGen *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope,
24139 }24139 }
2414024140
24141 ZigType *any_frame_type = get_any_frame_type(ira->codegen, result_type);24141 ZigType *any_frame_type = get_any_frame_type(ira->codegen, result_type);
24142 IrInstGen *casted_frame = ir_implicit_cast(ira, frame, any_frame_type);24142 Stage1AirInst *casted_frame = ir_implicit_cast(ira, frame, any_frame_type);
24143 if (type_is_invalid(casted_frame->value->type))24143 if (type_is_invalid(casted_frame->value->type))
24144 return ira->codegen->invalid_inst_gen;24144 return ira->codegen->invalid_inst_gen;
2414524145
24146 return casted_frame;24146 return casted_frame;
24147}24147}
2414824148
24149static IrInstGen *ir_analyze_instruction_await(IrAnalyze *ira, IrInstSrcAwait *instruction) {24149static Stage1AirInst *ir_analyze_instruction_await(IrAnalyze *ira, Stage1ZirInstAwait *instruction) {
24150 IrInstGen *operand = instruction->frame->child;24150 Stage1AirInst *operand = instruction->frame->child;
24151 if (type_is_invalid(operand->value->type))24151 if (type_is_invalid(operand->value->type))
24152 return ira->codegen->invalid_inst_gen;24152 return ira->codegen->invalid_inst_gen;
24153 ZigFn *target_fn;24153 ZigFn *target_fn;
24154 IrInstGen *frame = analyze_frame_ptr_to_anyframe_T(ira, instruction->base.scope, instruction->base.source_node, operand, &target_fn);24154 Stage1AirInst *frame = analyze_frame_ptr_to_anyframe_T(ira, instruction->base.scope, instruction->base.source_node, operand, &target_fn);
24155 if (type_is_invalid(frame->value->type))24155 if (type_is_invalid(frame->value->type))
24156 return ira->codegen->invalid_inst_gen;24156 return ira->codegen->invalid_inst_gen;
2415724157
...@@ -24171,7 +24171,7 @@ static IrInstGen *ir_analyze_instruction_await(IrAnalyze *ira, IrInstSrcAwait *i...@@ -24171,7 +24171,7 @@ static IrInstGen *ir_analyze_instruction_await(IrAnalyze *ira, IrInstSrcAwait *i
24171 fn_entry->calls_or_awaits_errorable_fn = true;24171 fn_entry->calls_or_awaits_errorable_fn = true;
24172 }24172 }
2417324173
24174 IrInstGen *result_loc;24174 Stage1AirInst *result_loc;
24175 if (type_has_bits(ira->codegen, result_type)) {24175 if (type_has_bits(ira->codegen, result_type)) {
24176 result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,24176 result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
24177 result_type, nullptr, true, true);24177 result_type, nullptr, true, true);
...@@ -24184,19 +24184,19 @@ static IrInstGen *ir_analyze_instruction_await(IrAnalyze *ira, IrInstSrcAwait *i...@@ -24184,19 +24184,19 @@ static IrInstGen *ir_analyze_instruction_await(IrAnalyze *ira, IrInstSrcAwait *i
24184 result_loc = nullptr;24184 result_loc = nullptr;
24185 }24185 }
2418624186
24187 IrInstGenAwait *result = ir_build_await_gen(ira, instruction->base.scope, instruction->base.source_node, frame, result_type, result_loc,24187 Stage1AirInstAwait *result = ir_build_await_gen(ira, instruction->base.scope, instruction->base.source_node, frame, result_type, result_loc,
24188 instruction->is_nosuspend);24188 instruction->is_nosuspend);
24189 result->target_fn = target_fn;24189 result->target_fn = target_fn;
24190 fn_entry->await_list.append(result);24190 fn_entry->await_list.append(result);
24191 return ir_finish_anal(ira, &result->base);24191 return ir_finish_anal(ira, &result->base);
24192}24192}
2419324193
24194static IrInstGen *ir_analyze_instruction_resume(IrAnalyze *ira, IrInstSrcResume *instruction) {24194static Stage1AirInst *ir_analyze_instruction_resume(IrAnalyze *ira, Stage1ZirInstResume *instruction) {
24195 IrInstGen *frame_ptr = instruction->frame->child;24195 Stage1AirInst *frame_ptr = instruction->frame->child;
24196 if (type_is_invalid(frame_ptr->value->type))24196 if (type_is_invalid(frame_ptr->value->type))
24197 return ira->codegen->invalid_inst_gen;24197 return ira->codegen->invalid_inst_gen;
2419824198
24199 IrInstGen *frame;24199 Stage1AirInst *frame;
24200 if (frame_ptr->value->type->id == ZigTypeIdPointer &&24200 if (frame_ptr->value->type->id == ZigTypeIdPointer &&
24201 frame_ptr->value->type->data.pointer.ptr_len == PtrLenSingle &&24201 frame_ptr->value->type->data.pointer.ptr_len == PtrLenSingle &&
24202 frame_ptr->value->type->data.pointer.child_type->id == ZigTypeIdFnFrame)24202 frame_ptr->value->type->data.pointer.child_type->id == ZigTypeIdFnFrame)
...@@ -24208,7 +24208,7 @@ static IrInstGen *ir_analyze_instruction_resume(IrAnalyze *ira, IrInstSrcResume...@@ -24208,7 +24208,7 @@ static IrInstGen *ir_analyze_instruction_resume(IrAnalyze *ira, IrInstSrcResume
24208 }24208 }
2420924209
24210 ZigType *any_frame_type = get_any_frame_type(ira->codegen, nullptr);24210 ZigType *any_frame_type = get_any_frame_type(ira->codegen, nullptr);
24211 IrInstGen *casted_frame = ir_implicit_cast2(ira, instruction->frame->scope,24211 Stage1AirInst *casted_frame = ir_implicit_cast2(ira, instruction->frame->scope,
24212 instruction->frame->source_node, frame, any_frame_type);24212 instruction->frame->source_node, frame, any_frame_type);
24213 if (type_is_invalid(casted_frame->value->type))24213 if (type_is_invalid(casted_frame->value->type))
24214 return ira->codegen->invalid_inst_gen;24214 return ira->codegen->invalid_inst_gen;
...@@ -24216,11 +24216,11 @@ static IrInstGen *ir_analyze_instruction_resume(IrAnalyze *ira, IrInstSrcResume...@@ -24216,11 +24216,11 @@ static IrInstGen *ir_analyze_instruction_resume(IrAnalyze *ira, IrInstSrcResume
24216 return ir_build_resume_gen(ira, instruction->base.scope, instruction->base.source_node, casted_frame);24216 return ir_build_resume_gen(ira, instruction->base.scope, instruction->base.source_node, casted_frame);
24217}24217}
2421824218
24219static IrInstGen *ir_analyze_instruction_spill_begin(IrAnalyze *ira, IrInstSrcSpillBegin *instruction) {24219static Stage1AirInst *ir_analyze_instruction_spill_begin(IrAnalyze *ira, Stage1ZirInstSpillBegin *instruction) {
24220 if (ir_should_inline(ira->zir, instruction->base.scope))24220 if (ir_should_inline(ira->zir, instruction->base.scope))
24221 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);24221 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
2422224222
24223 IrInstGen *operand = instruction->operand->child;24223 Stage1AirInst *operand = instruction->operand->child;
24224 if (type_is_invalid(operand->value->type))24224 if (type_is_invalid(operand->value->type))
24225 return ira->codegen->invalid_inst_gen;24225 return ira->codegen->invalid_inst_gen;
2422624226
...@@ -24238,8 +24238,8 @@ static IrInstGen *ir_analyze_instruction_spill_begin(IrAnalyze *ira, IrInstSrcSp...@@ -24238,8 +24238,8 @@ static IrInstGen *ir_analyze_instruction_spill_begin(IrAnalyze *ira, IrInstSrcSp
24238 return ir_build_spill_begin_gen(ira, instruction->base.scope, instruction->base.source_node, operand, instruction->spill_id);24238 return ir_build_spill_begin_gen(ira, instruction->base.scope, instruction->base.source_node, operand, instruction->spill_id);
24239}24239}
2424024240
24241static IrInstGen *ir_analyze_instruction_spill_end(IrAnalyze *ira, IrInstSrcSpillEnd *instruction) {24241static Stage1AirInst *ir_analyze_instruction_spill_end(IrAnalyze *ira, Stage1ZirInstSpillEnd *instruction) {
24242 IrInstGen *operand = instruction->begin->operand->child;24242 Stage1AirInst *operand = instruction->begin->operand->child;
24243 if (type_is_invalid(operand->value->type))24243 if (type_is_invalid(operand->value->type))
24244 return ira->codegen->invalid_inst_gen;24244 return ira->codegen->invalid_inst_gen;
2424524245
...@@ -24250,13 +24250,13 @@ static IrInstGen *ir_analyze_instruction_spill_end(IrAnalyze *ira, IrInstSrcSpil...@@ -24250,13 +24250,13 @@ static IrInstGen *ir_analyze_instruction_spill_end(IrAnalyze *ira, IrInstSrcSpil
24250 return operand;24250 return operand;
24251 }24251 }
2425224252
24253 src_assert(instruction->begin->base.child->id == IrInstGenIdSpillBegin, instruction->base.source_node);24253 src_assert(instruction->begin->base.child->id == Stage1AirInstIdSpillBegin, instruction->base.source_node);
24254 IrInstGenSpillBegin *begin = reinterpret_cast<IrInstGenSpillBegin *>(instruction->begin->base.child);24254 Stage1AirInstSpillBegin *begin = reinterpret_cast<Stage1AirInstSpillBegin *>(instruction->begin->base.child);
2425524255
24256 return ir_build_spill_end_gen(ira, instruction->base.scope, instruction->base.source_node, begin, operand->value->type);24256 return ir_build_spill_end_gen(ira, instruction->base.scope, instruction->base.source_node, begin, operand->value->type);
24257}24257}
2425824258
24259static IrInstGen *ir_analyze_instruction_src(IrAnalyze *ira, IrInstSrcSrc *instruction) {24259static Stage1AirInst *ir_analyze_instruction_src(IrAnalyze *ira, Stage1ZirInstSrc *instruction) {
24260 ZigFn *fn_entry = scope_fn_entry(instruction->base.scope);24260 ZigFn *fn_entry = scope_fn_entry(instruction->base.scope);
24261 if (fn_entry == nullptr) {24261 if (fn_entry == nullptr) {
24262 ir_add_error_node(ira, instruction->base.source_node, buf_sprintf("@src outside function"));24262 ir_add_error_node(ira, instruction->base.source_node, buf_sprintf("@src outside function"));
...@@ -24318,289 +24318,289 @@ static IrInstGen *ir_analyze_instruction_src(IrAnalyze *ira, IrInstSrcSrc *instr...@@ -24318,289 +24318,289 @@ static IrInstGen *ir_analyze_instruction_src(IrAnalyze *ira, IrInstSrcSrc *instr
24318 return ir_const_move(ira, instruction->base.scope, instruction->base.source_node, result);24318 return ir_const_move(ira, instruction->base.scope, instruction->base.source_node, result);
24319}24319}
2432024320
24321static IrInstGen *ir_analyze_instruction_base(IrAnalyze *ira, IrInstSrc *instruction) {24321static Stage1AirInst *ir_analyze_instruction_base(IrAnalyze *ira, Stage1ZirInst *instruction) {
24322 switch (instruction->id) {24322 switch (instruction->id) {
24323 case IrInstSrcIdInvalid:24323 case Stage1ZirInstIdInvalid:
24324 zig_unreachable();24324 zig_unreachable();
2432524325
24326 case IrInstSrcIdReturn:24326 case Stage1ZirInstIdReturn:
24327 return ir_analyze_instruction_return(ira, (IrInstSrcReturn *)instruction);24327 return ir_analyze_instruction_return(ira, (Stage1ZirInstReturn *)instruction);
24328 case IrInstSrcIdConst:24328 case Stage1ZirInstIdConst:
24329 return ir_analyze_instruction_const(ira, (IrInstSrcConst *)instruction);24329 return ir_analyze_instruction_const(ira, (Stage1ZirInstConst *)instruction);
24330 case IrInstSrcIdUnOp:24330 case Stage1ZirInstIdUnOp:
24331 return ir_analyze_instruction_un_op(ira, (IrInstSrcUnOp *)instruction);24331 return ir_analyze_instruction_un_op(ira, (Stage1ZirInstUnOp *)instruction);
24332 case IrInstSrcIdBinOp:24332 case Stage1ZirInstIdBinOp:
24333 return ir_analyze_instruction_bin_op(ira, (IrInstSrcBinOp *)instruction);24333 return ir_analyze_instruction_bin_op(ira, (Stage1ZirInstBinOp *)instruction);
24334 case IrInstSrcIdMergeErrSets:24334 case Stage1ZirInstIdMergeErrSets:
24335 return ir_analyze_instruction_merge_err_sets(ira, (IrInstSrcMergeErrSets *)instruction);24335 return ir_analyze_instruction_merge_err_sets(ira, (Stage1ZirInstMergeErrSets *)instruction);
24336 case IrInstSrcIdDeclVar:24336 case Stage1ZirInstIdDeclVar:
24337 return ir_analyze_instruction_decl_var(ira, (IrInstSrcDeclVar *)instruction);24337 return ir_analyze_instruction_decl_var(ira, (Stage1ZirInstDeclVar *)instruction);
24338 case IrInstSrcIdLoadPtr:24338 case Stage1ZirInstIdLoadPtr:
24339 return ir_analyze_instruction_load_ptr(ira, (IrInstSrcLoadPtr *)instruction);24339 return ir_analyze_instruction_load_ptr(ira, (Stage1ZirInstLoadPtr *)instruction);
24340 case IrInstSrcIdStorePtr:24340 case Stage1ZirInstIdStorePtr:
24341 return ir_analyze_instruction_store_ptr(ira, (IrInstSrcStorePtr *)instruction);24341 return ir_analyze_instruction_store_ptr(ira, (Stage1ZirInstStorePtr *)instruction);
24342 case IrInstSrcIdElemPtr:24342 case Stage1ZirInstIdElemPtr:
24343 return ir_analyze_instruction_elem_ptr(ira, (IrInstSrcElemPtr *)instruction);24343 return ir_analyze_instruction_elem_ptr(ira, (Stage1ZirInstElemPtr *)instruction);
24344 case IrInstSrcIdVarPtr:24344 case Stage1ZirInstIdVarPtr:
24345 return ir_analyze_instruction_var_ptr(ira, (IrInstSrcVarPtr *)instruction);24345 return ir_analyze_instruction_var_ptr(ira, (Stage1ZirInstVarPtr *)instruction);
24346 case IrInstSrcIdFieldPtr:24346 case Stage1ZirInstIdFieldPtr:
24347 return ir_analyze_instruction_field_ptr(ira, (IrInstSrcFieldPtr *)instruction);24347 return ir_analyze_instruction_field_ptr(ira, (Stage1ZirInstFieldPtr *)instruction);
24348 case IrInstSrcIdCall:24348 case Stage1ZirInstIdCall:
24349 return ir_analyze_instruction_call(ira, (IrInstSrcCall *)instruction);24349 return ir_analyze_instruction_call(ira, (Stage1ZirInstCall *)instruction);
24350 case IrInstSrcIdCallArgs:24350 case Stage1ZirInstIdCallArgs:
24351 return ir_analyze_instruction_call_args(ira, (IrInstSrcCallArgs *)instruction);24351 return ir_analyze_instruction_call_args(ira, (Stage1ZirInstCallArgs *)instruction);
24352 case IrInstSrcIdCallExtra:24352 case Stage1ZirInstIdCallExtra:
24353 return ir_analyze_instruction_call_extra(ira, (IrInstSrcCallExtra *)instruction);24353 return ir_analyze_instruction_call_extra(ira, (Stage1ZirInstCallExtra *)instruction);
24354 case IrInstSrcIdAsyncCallExtra:24354 case Stage1ZirInstIdAsyncCallExtra:
24355 return ir_analyze_instruction_async_call_extra(ira, (IrInstSrcAsyncCallExtra *)instruction);24355 return ir_analyze_instruction_async_call_extra(ira, (Stage1ZirInstAsyncCallExtra *)instruction);
24356 case IrInstSrcIdBr:24356 case Stage1ZirInstIdBr:
24357 return ir_analyze_instruction_br(ira, (IrInstSrcBr *)instruction);24357 return ir_analyze_instruction_br(ira, (Stage1ZirInstBr *)instruction);
24358 case IrInstSrcIdCondBr:24358 case Stage1ZirInstIdCondBr:
24359 return ir_analyze_instruction_cond_br(ira, (IrInstSrcCondBr *)instruction);24359 return ir_analyze_instruction_cond_br(ira, (Stage1ZirInstCondBr *)instruction);
24360 case IrInstSrcIdUnreachable:24360 case Stage1ZirInstIdUnreachable:
24361 return ir_analyze_instruction_unreachable(ira, (IrInstSrcUnreachable *)instruction);24361 return ir_analyze_instruction_unreachable(ira, (Stage1ZirInstUnreachable *)instruction);
24362 case IrInstSrcIdPhi:24362 case Stage1ZirInstIdPhi:
24363 return ir_analyze_instruction_phi(ira, (IrInstSrcPhi *)instruction);24363 return ir_analyze_instruction_phi(ira, (Stage1ZirInstPhi *)instruction);
24364 case IrInstSrcIdTypeOf:24364 case Stage1ZirInstIdTypeOf:
24365 return ir_analyze_instruction_typeof(ira, (IrInstSrcTypeOf *)instruction);24365 return ir_analyze_instruction_typeof(ira, (Stage1ZirInstTypeOf *)instruction);
24366 case IrInstSrcIdSetCold:24366 case Stage1ZirInstIdSetCold:
24367 return ir_analyze_instruction_set_cold(ira, (IrInstSrcSetCold *)instruction);24367 return ir_analyze_instruction_set_cold(ira, (Stage1ZirInstSetCold *)instruction);
24368 case IrInstSrcIdSetRuntimeSafety:24368 case Stage1ZirInstIdSetRuntimeSafety:
24369 return ir_analyze_instruction_set_runtime_safety(ira, (IrInstSrcSetRuntimeSafety *)instruction);24369 return ir_analyze_instruction_set_runtime_safety(ira, (Stage1ZirInstSetRuntimeSafety *)instruction);
24370 case IrInstSrcIdSetFloatMode:24370 case Stage1ZirInstIdSetFloatMode:
24371 return ir_analyze_instruction_set_float_mode(ira, (IrInstSrcSetFloatMode *)instruction);24371 return ir_analyze_instruction_set_float_mode(ira, (Stage1ZirInstSetFloatMode *)instruction);
24372 case IrInstSrcIdAnyFrameType:24372 case Stage1ZirInstIdAnyFrameType:
24373 return ir_analyze_instruction_any_frame_type(ira, (IrInstSrcAnyFrameType *)instruction);24373 return ir_analyze_instruction_any_frame_type(ira, (Stage1ZirInstAnyFrameType *)instruction);
24374 case IrInstSrcIdSliceType:24374 case Stage1ZirInstIdSliceType:
24375 return ir_analyze_instruction_slice_type(ira, (IrInstSrcSliceType *)instruction);24375 return ir_analyze_instruction_slice_type(ira, (Stage1ZirInstSliceType *)instruction);
24376 case IrInstSrcIdAsm:24376 case Stage1ZirInstIdAsm:
24377 return ir_analyze_instruction_asm(ira, (IrInstSrcAsm *)instruction);24377 return ir_analyze_instruction_asm(ira, (Stage1ZirInstAsm *)instruction);
24378 case IrInstSrcIdArrayType:24378 case Stage1ZirInstIdArrayType:
24379 return ir_analyze_instruction_array_type(ira, (IrInstSrcArrayType *)instruction);24379 return ir_analyze_instruction_array_type(ira, (Stage1ZirInstArrayType *)instruction);
24380 case IrInstSrcIdSizeOf:24380 case Stage1ZirInstIdSizeOf:
24381 return ir_analyze_instruction_size_of(ira, (IrInstSrcSizeOf *)instruction);24381 return ir_analyze_instruction_size_of(ira, (Stage1ZirInstSizeOf *)instruction);
24382 case IrInstSrcIdTestNonNull:24382 case Stage1ZirInstIdTestNonNull:
24383 return ir_analyze_instruction_test_non_null(ira, (IrInstSrcTestNonNull *)instruction);24383 return ir_analyze_instruction_test_non_null(ira, (Stage1ZirInstTestNonNull *)instruction);
24384 case IrInstSrcIdOptionalUnwrapPtr:24384 case Stage1ZirInstIdOptionalUnwrapPtr:
24385 return ir_analyze_instruction_optional_unwrap_ptr(ira, (IrInstSrcOptionalUnwrapPtr *)instruction);24385 return ir_analyze_instruction_optional_unwrap_ptr(ira, (Stage1ZirInstOptionalUnwrapPtr *)instruction);
24386 case IrInstSrcIdClz:24386 case Stage1ZirInstIdClz:
24387 return ir_analyze_instruction_clz(ira, (IrInstSrcClz *)instruction);24387 return ir_analyze_instruction_clz(ira, (Stage1ZirInstClz *)instruction);
24388 case IrInstSrcIdCtz:24388 case Stage1ZirInstIdCtz:
24389 return ir_analyze_instruction_ctz(ira, (IrInstSrcCtz *)instruction);24389 return ir_analyze_instruction_ctz(ira, (Stage1ZirInstCtz *)instruction);
24390 case IrInstSrcIdPopCount:24390 case Stage1ZirInstIdPopCount:
24391 return ir_analyze_instruction_pop_count(ira, (IrInstSrcPopCount *)instruction);24391 return ir_analyze_instruction_pop_count(ira, (Stage1ZirInstPopCount *)instruction);
24392 case IrInstSrcIdBswap:24392 case Stage1ZirInstIdBswap:
24393 return ir_analyze_instruction_bswap(ira, (IrInstSrcBswap *)instruction);24393 return ir_analyze_instruction_bswap(ira, (Stage1ZirInstBswap *)instruction);
24394 case IrInstSrcIdBitReverse:24394 case Stage1ZirInstIdBitReverse:
24395 return ir_analyze_instruction_bit_reverse(ira, (IrInstSrcBitReverse *)instruction);24395 return ir_analyze_instruction_bit_reverse(ira, (Stage1ZirInstBitReverse *)instruction);
24396 case IrInstSrcIdSwitchBr:24396 case Stage1ZirInstIdSwitchBr:
24397 return ir_analyze_instruction_switch_br(ira, (IrInstSrcSwitchBr *)instruction);24397 return ir_analyze_instruction_switch_br(ira, (Stage1ZirInstSwitchBr *)instruction);
24398 case IrInstSrcIdSwitchTarget:24398 case Stage1ZirInstIdSwitchTarget:
24399 return ir_analyze_instruction_switch_target(ira, (IrInstSrcSwitchTarget *)instruction);24399 return ir_analyze_instruction_switch_target(ira, (Stage1ZirInstSwitchTarget *)instruction);
24400 case IrInstSrcIdSwitchVar:24400 case Stage1ZirInstIdSwitchVar:
24401 return ir_analyze_instruction_switch_var(ira, (IrInstSrcSwitchVar *)instruction);24401 return ir_analyze_instruction_switch_var(ira, (Stage1ZirInstSwitchVar *)instruction);
24402 case IrInstSrcIdSwitchElseVar:24402 case Stage1ZirInstIdSwitchElseVar:
24403 return ir_analyze_instruction_switch_else_var(ira, (IrInstSrcSwitchElseVar *)instruction);24403 return ir_analyze_instruction_switch_else_var(ira, (Stage1ZirInstSwitchElseVar *)instruction);
24404 case IrInstSrcIdImport:24404 case Stage1ZirInstIdImport:
24405 return ir_analyze_instruction_import(ira, (IrInstSrcImport *)instruction);24405 return ir_analyze_instruction_import(ira, (Stage1ZirInstImport *)instruction);
24406 case IrInstSrcIdRef:24406 case Stage1ZirInstIdRef:
24407 return ir_analyze_instruction_ref(ira, (IrInstSrcRef *)instruction);24407 return ir_analyze_instruction_ref(ira, (Stage1ZirInstRef *)instruction);
24408 case IrInstSrcIdContainerInitList:24408 case Stage1ZirInstIdContainerInitList:
24409 return ir_analyze_instruction_container_init_list(ira, (IrInstSrcContainerInitList *)instruction);24409 return ir_analyze_instruction_container_init_list(ira, (Stage1ZirInstContainerInitList *)instruction);
24410 case IrInstSrcIdContainerInitFields:24410 case Stage1ZirInstIdContainerInitFields:
24411 return ir_analyze_instruction_container_init_fields(ira, (IrInstSrcContainerInitFields *)instruction);24411 return ir_analyze_instruction_container_init_fields(ira, (Stage1ZirInstContainerInitFields *)instruction);
24412 case IrInstSrcIdCompileErr:24412 case Stage1ZirInstIdCompileErr:
24413 return ir_analyze_instruction_compile_err(ira, (IrInstSrcCompileErr *)instruction);24413 return ir_analyze_instruction_compile_err(ira, (Stage1ZirInstCompileErr *)instruction);
24414 case IrInstSrcIdCompileLog:24414 case Stage1ZirInstIdCompileLog:
24415 return ir_analyze_instruction_compile_log(ira, (IrInstSrcCompileLog *)instruction);24415 return ir_analyze_instruction_compile_log(ira, (Stage1ZirInstCompileLog *)instruction);
24416 case IrInstSrcIdErrName:24416 case Stage1ZirInstIdErrName:
24417 return ir_analyze_instruction_err_name(ira, (IrInstSrcErrName *)instruction);24417 return ir_analyze_instruction_err_name(ira, (Stage1ZirInstErrName *)instruction);
24418 case IrInstSrcIdTypeName:24418 case Stage1ZirInstIdTypeName:
24419 return ir_analyze_instruction_type_name(ira, (IrInstSrcTypeName *)instruction);24419 return ir_analyze_instruction_type_name(ira, (Stage1ZirInstTypeName *)instruction);
24420 case IrInstSrcIdCImport:24420 case Stage1ZirInstIdCImport:
24421 return ir_analyze_instruction_c_import(ira, (IrInstSrcCImport *)instruction);24421 return ir_analyze_instruction_c_import(ira, (Stage1ZirInstCImport *)instruction);
24422 case IrInstSrcIdCInclude:24422 case Stage1ZirInstIdCInclude:
24423 return ir_analyze_instruction_c_include(ira, (IrInstSrcCInclude *)instruction);24423 return ir_analyze_instruction_c_include(ira, (Stage1ZirInstCInclude *)instruction);
24424 case IrInstSrcIdCDefine:24424 case Stage1ZirInstIdCDefine:
24425 return ir_analyze_instruction_c_define(ira, (IrInstSrcCDefine *)instruction);24425 return ir_analyze_instruction_c_define(ira, (Stage1ZirInstCDefine *)instruction);
24426 case IrInstSrcIdCUndef:24426 case Stage1ZirInstIdCUndef:
24427 return ir_analyze_instruction_c_undef(ira, (IrInstSrcCUndef *)instruction);24427 return ir_analyze_instruction_c_undef(ira, (Stage1ZirInstCUndef *)instruction);
24428 case IrInstSrcIdEmbedFile:24428 case Stage1ZirInstIdEmbedFile:
24429 return ir_analyze_instruction_embed_file(ira, (IrInstSrcEmbedFile *)instruction);24429 return ir_analyze_instruction_embed_file(ira, (Stage1ZirInstEmbedFile *)instruction);
24430 case IrInstSrcIdCmpxchg:24430 case Stage1ZirInstIdCmpxchg:
24431 return ir_analyze_instruction_cmpxchg(ira, (IrInstSrcCmpxchg *)instruction);24431 return ir_analyze_instruction_cmpxchg(ira, (Stage1ZirInstCmpxchg *)instruction);
24432 case IrInstSrcIdFence:24432 case Stage1ZirInstIdFence:
24433 return ir_analyze_instruction_fence(ira, (IrInstSrcFence *)instruction);24433 return ir_analyze_instruction_fence(ira, (Stage1ZirInstFence *)instruction);
24434 case IrInstSrcIdReduce:24434 case Stage1ZirInstIdReduce:
24435 return ir_analyze_instruction_reduce(ira, (IrInstSrcReduce *)instruction);24435 return ir_analyze_instruction_reduce(ira, (Stage1ZirInstReduce *)instruction);
24436 case IrInstSrcIdTruncate:24436 case Stage1ZirInstIdTruncate:
24437 return ir_analyze_instruction_truncate(ira, (IrInstSrcTruncate *)instruction);24437 return ir_analyze_instruction_truncate(ira, (Stage1ZirInstTruncate *)instruction);
24438 case IrInstSrcIdIntCast:24438 case Stage1ZirInstIdIntCast:
24439 return ir_analyze_instruction_int_cast(ira, (IrInstSrcIntCast *)instruction);24439 return ir_analyze_instruction_int_cast(ira, (Stage1ZirInstIntCast *)instruction);
24440 case IrInstSrcIdFloatCast:24440 case Stage1ZirInstIdFloatCast:
24441 return ir_analyze_instruction_float_cast(ira, (IrInstSrcFloatCast *)instruction);24441 return ir_analyze_instruction_float_cast(ira, (Stage1ZirInstFloatCast *)instruction);
24442 case IrInstSrcIdErrSetCast:24442 case Stage1ZirInstIdErrSetCast:
24443 return ir_analyze_instruction_err_set_cast(ira, (IrInstSrcErrSetCast *)instruction);24443 return ir_analyze_instruction_err_set_cast(ira, (Stage1ZirInstErrSetCast *)instruction);
24444 case IrInstSrcIdIntToFloat:24444 case Stage1ZirInstIdIntToFloat:
24445 return ir_analyze_instruction_int_to_float(ira, (IrInstSrcIntToFloat *)instruction);24445 return ir_analyze_instruction_int_to_float(ira, (Stage1ZirInstIntToFloat *)instruction);
24446 case IrInstSrcIdFloatToInt:24446 case Stage1ZirInstIdFloatToInt:
24447 return ir_analyze_instruction_float_to_int(ira, (IrInstSrcFloatToInt *)instruction);24447 return ir_analyze_instruction_float_to_int(ira, (Stage1ZirInstFloatToInt *)instruction);
24448 case IrInstSrcIdBoolToInt:24448 case Stage1ZirInstIdBoolToInt:
24449 return ir_analyze_instruction_bool_to_int(ira, (IrInstSrcBoolToInt *)instruction);24449 return ir_analyze_instruction_bool_to_int(ira, (Stage1ZirInstBoolToInt *)instruction);
24450 case IrInstSrcIdVectorType:24450 case Stage1ZirInstIdVectorType:
24451 return ir_analyze_instruction_vector_type(ira, (IrInstSrcVectorType *)instruction);24451 return ir_analyze_instruction_vector_type(ira, (Stage1ZirInstVectorType *)instruction);
24452 case IrInstSrcIdShuffleVector:24452 case Stage1ZirInstIdShuffleVector:
24453 return ir_analyze_instruction_shuffle_vector(ira, (IrInstSrcShuffleVector *)instruction);24453 return ir_analyze_instruction_shuffle_vector(ira, (Stage1ZirInstShuffleVector *)instruction);
24454 case IrInstSrcIdSplat:24454 case Stage1ZirInstIdSplat:
24455 return ir_analyze_instruction_splat(ira, (IrInstSrcSplat *)instruction);24455 return ir_analyze_instruction_splat(ira, (Stage1ZirInstSplat *)instruction);
24456 case IrInstSrcIdBoolNot:24456 case Stage1ZirInstIdBoolNot:
24457 return ir_analyze_instruction_bool_not(ira, (IrInstSrcBoolNot *)instruction);24457 return ir_analyze_instruction_bool_not(ira, (Stage1ZirInstBoolNot *)instruction);
24458 case IrInstSrcIdMemset:24458 case Stage1ZirInstIdMemset:
24459 return ir_analyze_instruction_memset(ira, (IrInstSrcMemset *)instruction);24459 return ir_analyze_instruction_memset(ira, (Stage1ZirInstMemset *)instruction);
24460 case IrInstSrcIdMemcpy:24460 case Stage1ZirInstIdMemcpy:
24461 return ir_analyze_instruction_memcpy(ira, (IrInstSrcMemcpy *)instruction);24461 return ir_analyze_instruction_memcpy(ira, (Stage1ZirInstMemcpy *)instruction);
24462 case IrInstSrcIdSlice:24462 case Stage1ZirInstIdSlice:
24463 return ir_analyze_instruction_slice(ira, (IrInstSrcSlice *)instruction);24463 return ir_analyze_instruction_slice(ira, (Stage1ZirInstSlice *)instruction);
24464 case IrInstSrcIdBreakpoint:24464 case Stage1ZirInstIdBreakpoint:
24465 return ir_analyze_instruction_breakpoint(ira, (IrInstSrcBreakpoint *)instruction);24465 return ir_analyze_instruction_breakpoint(ira, (Stage1ZirInstBreakpoint *)instruction);
24466 case IrInstSrcIdReturnAddress:24466 case Stage1ZirInstIdReturnAddress:
24467 return ir_analyze_instruction_return_address(ira, (IrInstSrcReturnAddress *)instruction);24467 return ir_analyze_instruction_return_address(ira, (Stage1ZirInstReturnAddress *)instruction);
24468 case IrInstSrcIdFrameAddress:24468 case Stage1ZirInstIdFrameAddress:
24469 return ir_analyze_instruction_frame_address(ira, (IrInstSrcFrameAddress *)instruction);24469 return ir_analyze_instruction_frame_address(ira, (Stage1ZirInstFrameAddress *)instruction);
24470 case IrInstSrcIdFrameHandle:24470 case Stage1ZirInstIdFrameHandle:
24471 return ir_analyze_instruction_frame_handle(ira, (IrInstSrcFrameHandle *)instruction);24471 return ir_analyze_instruction_frame_handle(ira, (Stage1ZirInstFrameHandle *)instruction);
24472 case IrInstSrcIdFrameType:24472 case Stage1ZirInstIdFrameType:
24473 return ir_analyze_instruction_frame_type(ira, (IrInstSrcFrameType *)instruction);24473 return ir_analyze_instruction_frame_type(ira, (Stage1ZirInstFrameType *)instruction);
24474 case IrInstSrcIdFrameSize:24474 case Stage1ZirInstIdFrameSize:
24475 return ir_analyze_instruction_frame_size(ira, (IrInstSrcFrameSize *)instruction);24475 return ir_analyze_instruction_frame_size(ira, (Stage1ZirInstFrameSize *)instruction);
24476 case IrInstSrcIdAlignOf:24476 case Stage1ZirInstIdAlignOf:
24477 return ir_analyze_instruction_align_of(ira, (IrInstSrcAlignOf *)instruction);24477 return ir_analyze_instruction_align_of(ira, (Stage1ZirInstAlignOf *)instruction);
24478 case IrInstSrcIdOverflowOp:24478 case Stage1ZirInstIdOverflowOp:
24479 return ir_analyze_instruction_overflow_op(ira, (IrInstSrcOverflowOp *)instruction);24479 return ir_analyze_instruction_overflow_op(ira, (Stage1ZirInstOverflowOp *)instruction);
24480 case IrInstSrcIdTestErr:24480 case Stage1ZirInstIdTestErr:
24481 return ir_analyze_instruction_test_err(ira, (IrInstSrcTestErr *)instruction);24481 return ir_analyze_instruction_test_err(ira, (Stage1ZirInstTestErr *)instruction);
24482 case IrInstSrcIdUnwrapErrCode:24482 case Stage1ZirInstIdUnwrapErrCode:
24483 return ir_analyze_instruction_unwrap_err_code(ira, (IrInstSrcUnwrapErrCode *)instruction);24483 return ir_analyze_instruction_unwrap_err_code(ira, (Stage1ZirInstUnwrapErrCode *)instruction);
24484 case IrInstSrcIdUnwrapErrPayload:24484 case Stage1ZirInstIdUnwrapErrPayload:
24485 return ir_analyze_instruction_unwrap_err_payload(ira, (IrInstSrcUnwrapErrPayload *)instruction);24485 return ir_analyze_instruction_unwrap_err_payload(ira, (Stage1ZirInstUnwrapErrPayload *)instruction);
24486 case IrInstSrcIdFnProto:24486 case Stage1ZirInstIdFnProto:
24487 return ir_analyze_instruction_fn_proto(ira, (IrInstSrcFnProto *)instruction);24487 return ir_analyze_instruction_fn_proto(ira, (Stage1ZirInstFnProto *)instruction);
24488 case IrInstSrcIdTestComptime:24488 case Stage1ZirInstIdTestComptime:
24489 return ir_analyze_instruction_test_comptime(ira, (IrInstSrcTestComptime *)instruction);24489 return ir_analyze_instruction_test_comptime(ira, (Stage1ZirInstTestComptime *)instruction);
24490 case IrInstSrcIdCheckSwitchProngsUnderNo:24490 case Stage1ZirInstIdCheckSwitchProngsUnderNo:
24491 return ir_analyze_instruction_check_switch_prongs(ira, (IrInstSrcCheckSwitchProngs *)instruction, false);24491 return ir_analyze_instruction_check_switch_prongs(ira, (Stage1ZirInstCheckSwitchProngs *)instruction, false);
24492 case IrInstSrcIdCheckSwitchProngsUnderYes:24492 case Stage1ZirInstIdCheckSwitchProngsUnderYes:
24493 return ir_analyze_instruction_check_switch_prongs(ira, (IrInstSrcCheckSwitchProngs *)instruction, true);24493 return ir_analyze_instruction_check_switch_prongs(ira, (Stage1ZirInstCheckSwitchProngs *)instruction, true);
24494 case IrInstSrcIdCheckStatementIsVoid:24494 case Stage1ZirInstIdCheckStatementIsVoid:
24495 return ir_analyze_instruction_check_statement_is_void(ira, (IrInstSrcCheckStatementIsVoid *)instruction);24495 return ir_analyze_instruction_check_statement_is_void(ira, (Stage1ZirInstCheckStatementIsVoid *)instruction);
24496 case IrInstSrcIdDeclRef:24496 case Stage1ZirInstIdDeclRef:
24497 return ir_analyze_instruction_decl_ref(ira, (IrInstSrcDeclRef *)instruction);24497 return ir_analyze_instruction_decl_ref(ira, (Stage1ZirInstDeclRef *)instruction);
24498 case IrInstSrcIdPanic:24498 case Stage1ZirInstIdPanic:
24499 return ir_analyze_instruction_panic(ira, (IrInstSrcPanic *)instruction);24499 return ir_analyze_instruction_panic(ira, (Stage1ZirInstPanic *)instruction);
24500 case IrInstSrcIdPtrCast:24500 case Stage1ZirInstIdPtrCast:
24501 return ir_analyze_instruction_ptr_cast(ira, (IrInstSrcPtrCast *)instruction);24501 return ir_analyze_instruction_ptr_cast(ira, (Stage1ZirInstPtrCast *)instruction);
24502 case IrInstSrcIdIntToPtr:24502 case Stage1ZirInstIdIntToPtr:
24503 return ir_analyze_instruction_int_to_ptr(ira, (IrInstSrcIntToPtr *)instruction);24503 return ir_analyze_instruction_int_to_ptr(ira, (Stage1ZirInstIntToPtr *)instruction);
24504 case IrInstSrcIdPtrToInt:24504 case Stage1ZirInstIdPtrToInt:
24505 return ir_analyze_instruction_ptr_to_int(ira, (IrInstSrcPtrToInt *)instruction);24505 return ir_analyze_instruction_ptr_to_int(ira, (Stage1ZirInstPtrToInt *)instruction);
24506 case IrInstSrcIdTagName:24506 case Stage1ZirInstIdTagName:
24507 return ir_analyze_instruction_enum_tag_name(ira, (IrInstSrcTagName *)instruction);24507 return ir_analyze_instruction_enum_tag_name(ira, (Stage1ZirInstTagName *)instruction);
24508 case IrInstSrcIdFieldParentPtr:24508 case Stage1ZirInstIdFieldParentPtr:
24509 return ir_analyze_instruction_field_parent_ptr(ira, (IrInstSrcFieldParentPtr *)instruction);24509 return ir_analyze_instruction_field_parent_ptr(ira, (Stage1ZirInstFieldParentPtr *)instruction);
24510 case IrInstSrcIdOffsetOf:24510 case Stage1ZirInstIdOffsetOf:
24511 return ir_analyze_instruction_offset_of(ira, (IrInstSrcOffsetOf *)instruction);24511 return ir_analyze_instruction_offset_of(ira, (Stage1ZirInstOffsetOf *)instruction);
24512 case IrInstSrcIdBitOffsetOf:24512 case Stage1ZirInstIdBitOffsetOf:
24513 return ir_analyze_instruction_bit_offset_of(ira, (IrInstSrcBitOffsetOf *)instruction);24513 return ir_analyze_instruction_bit_offset_of(ira, (Stage1ZirInstBitOffsetOf *)instruction);
24514 case IrInstSrcIdTypeInfo:24514 case Stage1ZirInstIdTypeInfo:
24515 return ir_analyze_instruction_type_info(ira, (IrInstSrcTypeInfo *) instruction);24515 return ir_analyze_instruction_type_info(ira, (Stage1ZirInstTypeInfo *) instruction);
24516 case IrInstSrcIdType:24516 case Stage1ZirInstIdType:
24517 return ir_analyze_instruction_type(ira, (IrInstSrcType *)instruction);24517 return ir_analyze_instruction_type(ira, (Stage1ZirInstType *)instruction);
24518 case IrInstSrcIdHasField:24518 case Stage1ZirInstIdHasField:
24519 return ir_analyze_instruction_has_field(ira, (IrInstSrcHasField *) instruction);24519 return ir_analyze_instruction_has_field(ira, (Stage1ZirInstHasField *) instruction);
24520 case IrInstSrcIdSetEvalBranchQuota:24520 case Stage1ZirInstIdSetEvalBranchQuota:
24521 return ir_analyze_instruction_set_eval_branch_quota(ira, (IrInstSrcSetEvalBranchQuota *)instruction);24521 return ir_analyze_instruction_set_eval_branch_quota(ira, (Stage1ZirInstSetEvalBranchQuota *)instruction);
24522 case IrInstSrcIdPtrType:24522 case Stage1ZirInstIdPtrType:
24523 return ir_analyze_instruction_ptr_type(ira, (IrInstSrcPtrType *)instruction);24523 return ir_analyze_instruction_ptr_type(ira, (Stage1ZirInstPtrType *)instruction);
24524 case IrInstSrcIdPtrTypeSimple:24524 case Stage1ZirInstIdPtrTypeSimple:
24525 return ir_analyze_instruction_ptr_type_simple(ira, (IrInstSrcPtrTypeSimple *)instruction, false);24525 return ir_analyze_instruction_ptr_type_simple(ira, (Stage1ZirInstPtrTypeSimple *)instruction, false);
24526 case IrInstSrcIdPtrTypeSimpleConst:24526 case Stage1ZirInstIdPtrTypeSimpleConst:
24527 return ir_analyze_instruction_ptr_type_simple(ira, (IrInstSrcPtrTypeSimple *)instruction, true);24527 return ir_analyze_instruction_ptr_type_simple(ira, (Stage1ZirInstPtrTypeSimple *)instruction, true);
24528 case IrInstSrcIdAlignCast:24528 case Stage1ZirInstIdAlignCast:
24529 return ir_analyze_instruction_align_cast(ira, (IrInstSrcAlignCast *)instruction);24529 return ir_analyze_instruction_align_cast(ira, (Stage1ZirInstAlignCast *)instruction);
24530 case IrInstSrcIdImplicitCast:24530 case Stage1ZirInstIdImplicitCast:
24531 return ir_analyze_instruction_implicit_cast(ira, (IrInstSrcImplicitCast *)instruction);24531 return ir_analyze_instruction_implicit_cast(ira, (Stage1ZirInstImplicitCast *)instruction);
24532 case IrInstSrcIdResolveResult:24532 case Stage1ZirInstIdResolveResult:
24533 return ir_analyze_instruction_resolve_result(ira, (IrInstSrcResolveResult *)instruction);24533 return ir_analyze_instruction_resolve_result(ira, (Stage1ZirInstResolveResult *)instruction);
24534 case IrInstSrcIdResetResult:24534 case Stage1ZirInstIdResetResult:
24535 return ir_analyze_instruction_reset_result(ira, (IrInstSrcResetResult *)instruction);24535 return ir_analyze_instruction_reset_result(ira, (Stage1ZirInstResetResult *)instruction);
24536 case IrInstSrcIdSetAlignStack:24536 case Stage1ZirInstIdSetAlignStack:
24537 return ir_analyze_instruction_set_align_stack(ira, (IrInstSrcSetAlignStack *)instruction);24537 return ir_analyze_instruction_set_align_stack(ira, (Stage1ZirInstSetAlignStack *)instruction);
24538 case IrInstSrcIdArgTypeAllowVarFalse:24538 case Stage1ZirInstIdArgTypeAllowVarFalse:
24539 return ir_analyze_instruction_arg_type(ira, (IrInstSrcArgType *)instruction, false);24539 return ir_analyze_instruction_arg_type(ira, (Stage1ZirInstArgType *)instruction, false);
24540 case IrInstSrcIdArgTypeAllowVarTrue:24540 case Stage1ZirInstIdArgTypeAllowVarTrue:
24541 return ir_analyze_instruction_arg_type(ira, (IrInstSrcArgType *)instruction, true);24541 return ir_analyze_instruction_arg_type(ira, (Stage1ZirInstArgType *)instruction, true);
24542 case IrInstSrcIdExport:24542 case Stage1ZirInstIdExport:
24543 return ir_analyze_instruction_export(ira, (IrInstSrcExport *)instruction);24543 return ir_analyze_instruction_export(ira, (Stage1ZirInstExport *)instruction);
24544 case IrInstSrcIdExtern:24544 case Stage1ZirInstIdExtern:
24545 return ir_analyze_instruction_extern(ira, (IrInstSrcExtern *)instruction);24545 return ir_analyze_instruction_extern(ira, (Stage1ZirInstExtern *)instruction);
24546 case IrInstSrcIdErrorReturnTrace:24546 case Stage1ZirInstIdErrorReturnTrace:
24547 return ir_analyze_instruction_error_return_trace(ira, (IrInstSrcErrorReturnTrace *)instruction);24547 return ir_analyze_instruction_error_return_trace(ira, (Stage1ZirInstErrorReturnTrace *)instruction);
24548 case IrInstSrcIdErrorUnion:24548 case Stage1ZirInstIdErrorUnion:
24549 return ir_analyze_instruction_error_union(ira, (IrInstSrcErrorUnion *)instruction);24549 return ir_analyze_instruction_error_union(ira, (Stage1ZirInstErrorUnion *)instruction);
24550 case IrInstSrcIdAtomicRmw:24550 case Stage1ZirInstIdAtomicRmw:
24551 return ir_analyze_instruction_atomic_rmw(ira, (IrInstSrcAtomicRmw *)instruction);24551 return ir_analyze_instruction_atomic_rmw(ira, (Stage1ZirInstAtomicRmw *)instruction);
24552 case IrInstSrcIdAtomicLoad:24552 case Stage1ZirInstIdAtomicLoad:
24553 return ir_analyze_instruction_atomic_load(ira, (IrInstSrcAtomicLoad *)instruction);24553 return ir_analyze_instruction_atomic_load(ira, (Stage1ZirInstAtomicLoad *)instruction);
24554 case IrInstSrcIdAtomicStore:24554 case Stage1ZirInstIdAtomicStore:
24555 return ir_analyze_instruction_atomic_store(ira, (IrInstSrcAtomicStore *)instruction);24555 return ir_analyze_instruction_atomic_store(ira, (Stage1ZirInstAtomicStore *)instruction);
24556 case IrInstSrcIdSaveErrRetAddr:24556 case Stage1ZirInstIdSaveErrRetAddr:
24557 return ir_analyze_instruction_save_err_ret_addr(ira, (IrInstSrcSaveErrRetAddr *)instruction);24557 return ir_analyze_instruction_save_err_ret_addr(ira, (Stage1ZirInstSaveErrRetAddr *)instruction);
24558 case IrInstSrcIdAddImplicitReturnType:24558 case Stage1ZirInstIdAddImplicitReturnType:
24559 return ir_analyze_instruction_add_implicit_return_type(ira, (IrInstSrcAddImplicitReturnType *)instruction);24559 return ir_analyze_instruction_add_implicit_return_type(ira, (Stage1ZirInstAddImplicitReturnType *)instruction);
24560 case IrInstSrcIdFloatOp:24560 case Stage1ZirInstIdFloatOp:
24561 return ir_analyze_instruction_float_op(ira, (IrInstSrcFloatOp *)instruction);24561 return ir_analyze_instruction_float_op(ira, (Stage1ZirInstFloatOp *)instruction);
24562 case IrInstSrcIdMulAdd:24562 case Stage1ZirInstIdMulAdd:
24563 return ir_analyze_instruction_mul_add(ira, (IrInstSrcMulAdd *)instruction);24563 return ir_analyze_instruction_mul_add(ira, (Stage1ZirInstMulAdd *)instruction);
24564 case IrInstSrcIdIntToErr:24564 case Stage1ZirInstIdIntToErr:
24565 return ir_analyze_instruction_int_to_err(ira, (IrInstSrcIntToErr *)instruction);24565 return ir_analyze_instruction_int_to_err(ira, (Stage1ZirInstIntToErr *)instruction);
24566 case IrInstSrcIdErrToInt:24566 case Stage1ZirInstIdErrToInt:
24567 return ir_analyze_instruction_err_to_int(ira, (IrInstSrcErrToInt *)instruction);24567 return ir_analyze_instruction_err_to_int(ira, (Stage1ZirInstErrToInt *)instruction);
24568 case IrInstSrcIdIntToEnum:24568 case Stage1ZirInstIdIntToEnum:
24569 return ir_analyze_instruction_int_to_enum(ira, (IrInstSrcIntToEnum *)instruction);24569 return ir_analyze_instruction_int_to_enum(ira, (Stage1ZirInstIntToEnum *)instruction);
24570 case IrInstSrcIdEnumToInt:24570 case Stage1ZirInstIdEnumToInt:
24571 return ir_analyze_instruction_enum_to_int(ira, (IrInstSrcEnumToInt *)instruction);24571 return ir_analyze_instruction_enum_to_int(ira, (Stage1ZirInstEnumToInt *)instruction);
24572 case IrInstSrcIdCheckRuntimeScope:24572 case Stage1ZirInstIdCheckRuntimeScope:
24573 return ir_analyze_instruction_check_runtime_scope(ira, (IrInstSrcCheckRuntimeScope *)instruction);24573 return ir_analyze_instruction_check_runtime_scope(ira, (Stage1ZirInstCheckRuntimeScope *)instruction);
24574 case IrInstSrcIdHasDecl:24574 case Stage1ZirInstIdHasDecl:
24575 return ir_analyze_instruction_has_decl(ira, (IrInstSrcHasDecl *)instruction);24575 return ir_analyze_instruction_has_decl(ira, (Stage1ZirInstHasDecl *)instruction);
24576 case IrInstSrcIdUndeclaredIdent:24576 case Stage1ZirInstIdUndeclaredIdent:
24577 return ir_analyze_instruction_undeclared_ident(ira, (IrInstSrcUndeclaredIdent *)instruction);24577 return ir_analyze_instruction_undeclared_ident(ira, (Stage1ZirInstUndeclaredIdent *)instruction);
24578 case IrInstSrcIdAlloca:24578 case Stage1ZirInstIdAlloca:
24579 return nullptr;24579 return nullptr;
24580 case IrInstSrcIdEndExpr:24580 case Stage1ZirInstIdEndExpr:
24581 return ir_analyze_instruction_end_expr(ira, (IrInstSrcEndExpr *)instruction);24581 return ir_analyze_instruction_end_expr(ira, (Stage1ZirInstEndExpr *)instruction);
24582 case IrInstSrcIdBitCast:24582 case Stage1ZirInstIdBitCast:
24583 return ir_analyze_instruction_bit_cast_src(ira, (IrInstSrcBitCast *)instruction);24583 return ir_analyze_instruction_bit_cast_src(ira, (Stage1ZirInstBitCast *)instruction);
24584 case IrInstSrcIdUnionInitNamedField:24584 case Stage1ZirInstIdUnionInitNamedField:
24585 return ir_analyze_instruction_union_init_named_field(ira, (IrInstSrcUnionInitNamedField *)instruction);24585 return ir_analyze_instruction_union_init_named_field(ira, (Stage1ZirInstUnionInitNamedField *)instruction);
24586 case IrInstSrcIdSuspendBegin:24586 case Stage1ZirInstIdSuspendBegin:
24587 return ir_analyze_instruction_suspend_begin(ira, (IrInstSrcSuspendBegin *)instruction);24587 return ir_analyze_instruction_suspend_begin(ira, (Stage1ZirInstSuspendBegin *)instruction);
24588 case IrInstSrcIdSuspendFinish:24588 case Stage1ZirInstIdSuspendFinish:
24589 return ir_analyze_instruction_suspend_finish(ira, (IrInstSrcSuspendFinish *)instruction);24589 return ir_analyze_instruction_suspend_finish(ira, (Stage1ZirInstSuspendFinish *)instruction);
24590 case IrInstSrcIdResume:24590 case Stage1ZirInstIdResume:
24591 return ir_analyze_instruction_resume(ira, (IrInstSrcResume *)instruction);24591 return ir_analyze_instruction_resume(ira, (Stage1ZirInstResume *)instruction);
24592 case IrInstSrcIdAwait:24592 case Stage1ZirInstIdAwait:
24593 return ir_analyze_instruction_await(ira, (IrInstSrcAwait *)instruction);24593 return ir_analyze_instruction_await(ira, (Stage1ZirInstAwait *)instruction);
24594 case IrInstSrcIdSpillBegin:24594 case Stage1ZirInstIdSpillBegin:
24595 return ir_analyze_instruction_spill_begin(ira, (IrInstSrcSpillBegin *)instruction);24595 return ir_analyze_instruction_spill_begin(ira, (Stage1ZirInstSpillBegin *)instruction);
24596 case IrInstSrcIdSpillEnd:24596 case Stage1ZirInstIdSpillEnd:
24597 return ir_analyze_instruction_spill_end(ira, (IrInstSrcSpillEnd *)instruction);24597 return ir_analyze_instruction_spill_end(ira, (Stage1ZirInstSpillEnd *)instruction);
24598 case IrInstSrcIdWasmMemorySize:24598 case Stage1ZirInstIdWasmMemorySize:
24599 return ir_analyze_instruction_wasm_memory_size(ira, (IrInstSrcWasmMemorySize *)instruction);24599 return ir_analyze_instruction_wasm_memory_size(ira, (Stage1ZirInstWasmMemorySize *)instruction);
24600 case IrInstSrcIdWasmMemoryGrow:24600 case Stage1ZirInstIdWasmMemoryGrow:
24601 return ir_analyze_instruction_wasm_memory_grow(ira, (IrInstSrcWasmMemoryGrow *)instruction);24601 return ir_analyze_instruction_wasm_memory_grow(ira, (Stage1ZirInstWasmMemoryGrow *)instruction);
24602 case IrInstSrcIdSrc:24602 case Stage1ZirInstIdSrc:
24603 return ir_analyze_instruction_src(ira, (IrInstSrcSrc *)instruction);24603 return ir_analyze_instruction_src(ira, (Stage1ZirInstSrc *)instruction);
24604 }24604 }
24605 zig_unreachable();24605 zig_unreachable();
24606}24606}
...@@ -24630,7 +24630,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a...@@ -24630,7 +24630,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
24630 ira->new_irb.exec = stage1_air;24630 ira->new_irb.exec = stage1_air;
2463124631
24632 Stage1ZirBasicBlock *old_entry_bb = ira->zir->basic_block_list.at(0);24632 Stage1ZirBasicBlock *old_entry_bb = ira->zir->basic_block_list.at(0);
24633 IrBasicBlockGen *new_entry_bb = ir_get_new_bb(ira, old_entry_bb, nullptr);24633 Stage1AirBasicBlock *new_entry_bb = ir_get_new_bb(ira, old_entry_bb, nullptr);
24634 ira->new_irb.current_basic_block = new_entry_bb;24634 ira->new_irb.current_basic_block = new_entry_bb;
24635 ira->old_bb_index = 0;24635 ira->old_bb_index = 0;
2463624636
...@@ -24638,7 +24638,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a...@@ -24638,7 +24638,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
2463824638
24639 if (result_ptr != nullptr) {24639 if (result_ptr != nullptr) {
24640 assert(result_ptr->type->id == ZigTypeIdPointer);24640 assert(result_ptr->type->id == ZigTypeIdPointer);
24641 IrInstGenConst *const_inst = ir_create_inst_noval<IrInstGenConst>(24641 Stage1AirInstConst *const_inst = ir_create_inst_noval<Stage1AirInstConst>(
24642 &ira->new_irb, stage1_air->begin_scope, stage1_air->source_node);24642 &ira->new_irb, stage1_air->begin_scope, stage1_air->source_node);
24643 const_inst->base.value = result_ptr;24643 const_inst->base.value = result_ptr;
24644 ira->return_ptr = &const_inst->base;24644 ira->return_ptr = &const_inst->base;
...@@ -24650,7 +24650,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a...@@ -24650,7 +24650,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
24650 }24650 }
2465124651
24652 while (ira->old_bb_index < ira->zir->basic_block_list.length) {24652 while (ira->old_bb_index < ira->zir->basic_block_list.length) {
24653 IrInstSrc *old_instruction = ira->zir_current_basic_block->instruction_list.at(ira->instruction_index);24653 Stage1ZirInst *old_instruction = ira->zir_current_basic_block->instruction_list.at(ira->instruction_index);
2465424654
24655 if (old_instruction->ref_count == 0 && !ir_inst_src_has_side_effects(old_instruction)) {24655 if (old_instruction->ref_count == 0 && !ir_inst_src_has_side_effects(old_instruction)) {
24656 ira->instruction_index += 1;24656 ira->instruction_index += 1;
...@@ -24664,7 +24664,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a...@@ -24664,7 +24664,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
24664 ir_print_inst_src(codegen, stderr, old_instruction, 0);24664 ir_print_inst_src(codegen, stderr, old_instruction, 0);
24665 }24665 }
24666 ira->suspend_source_instr = old_instruction;24666 ira->suspend_source_instr = old_instruction;
24667 IrInstGen *new_instruction = ir_analyze_instruction_base(ira, old_instruction);24667 Stage1AirInst *new_instruction = ir_analyze_instruction_base(ira, old_instruction);
24668 if (new_instruction != nullptr) {24668 if (new_instruction != nullptr) {
24669 src_assert(new_instruction->value->type != nullptr || new_instruction->value->type != nullptr, old_instruction->source_node);24669 src_assert(new_instruction->value->type != nullptr || new_instruction->value->type != nullptr, old_instruction->source_node);
24670 old_instruction->child = new_instruction;24670 old_instruction->child = new_instruction;
...@@ -24732,283 +24732,283 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a...@@ -24732,283 +24732,283 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
24732 return res_type;24732 return res_type;
24733}24733}
2473424734
24735bool ir_inst_gen_has_side_effects(IrInstGen *instruction) {24735bool ir_inst_gen_has_side_effects(Stage1AirInst *instruction) {
24736 switch (instruction->id) {24736 switch (instruction->id) {
24737 case IrInstGenIdInvalid:24737 case Stage1AirInstIdInvalid:
24738 zig_unreachable();24738 zig_unreachable();
24739 case IrInstGenIdBr:24739 case Stage1AirInstIdBr:
24740 case IrInstGenIdCondBr:24740 case Stage1AirInstIdCondBr:
24741 case IrInstGenIdSwitchBr:24741 case Stage1AirInstIdSwitchBr:
24742 case IrInstGenIdDeclVar:24742 case Stage1AirInstIdDeclVar:
24743 case IrInstGenIdStorePtr:24743 case Stage1AirInstIdStorePtr:
24744 case IrInstGenIdVectorStoreElem:24744 case Stage1AirInstIdVectorStoreElem:
24745 case IrInstGenIdCall:24745 case Stage1AirInstIdCall:
24746 case IrInstGenIdReturn:24746 case Stage1AirInstIdReturn:
24747 case IrInstGenIdUnreachable:24747 case Stage1AirInstIdUnreachable:
24748 case IrInstGenIdFence:24748 case Stage1AirInstIdFence:
24749 case IrInstGenIdMemset:24749 case Stage1AirInstIdMemset:
24750 case IrInstGenIdMemcpy:24750 case Stage1AirInstIdMemcpy:
24751 case IrInstGenIdBreakpoint:24751 case Stage1AirInstIdBreakpoint:
24752 case IrInstGenIdOverflowOp: // TODO when we support multiple returns this can be side effect free24752 case Stage1AirInstIdOverflowOp: // TODO when we support multiple returns this can be side effect free
24753 case IrInstGenIdPanic:24753 case Stage1AirInstIdPanic:
24754 case IrInstGenIdSaveErrRetAddr:24754 case Stage1AirInstIdSaveErrRetAddr:
24755 case IrInstGenIdAtomicRmw:24755 case Stage1AirInstIdAtomicRmw:
24756 case IrInstGenIdAtomicStore:24756 case Stage1AirInstIdAtomicStore:
24757 case IrInstGenIdCmpxchg:24757 case Stage1AirInstIdCmpxchg:
24758 case IrInstGenIdAssertZero:24758 case Stage1AirInstIdAssertZero:
24759 case IrInstGenIdAssertNonNull:24759 case Stage1AirInstIdAssertNonNull:
24760 case IrInstGenIdPtrOfArrayToSlice:24760 case Stage1AirInstIdPtrOfArrayToSlice:
24761 case IrInstGenIdSlice:24761 case Stage1AirInstIdSlice:
24762 case IrInstGenIdOptionalWrap:24762 case Stage1AirInstIdOptionalWrap:
24763 case IrInstGenIdVectorToArray:24763 case Stage1AirInstIdVectorToArray:
24764 case IrInstGenIdSuspendBegin:24764 case Stage1AirInstIdSuspendBegin:
24765 case IrInstGenIdSuspendFinish:24765 case Stage1AirInstIdSuspendFinish:
24766 case IrInstGenIdResume:24766 case Stage1AirInstIdResume:
24767 case IrInstGenIdAwait:24767 case Stage1AirInstIdAwait:
24768 case IrInstGenIdSpillBegin:24768 case Stage1AirInstIdSpillBegin:
24769 case IrInstGenIdWasmMemoryGrow:24769 case Stage1AirInstIdWasmMemoryGrow:
24770 case IrInstGenIdExtern:24770 case Stage1AirInstIdExtern:
24771 return true;24771 return true;
2477224772
24773 case IrInstGenIdPhi:24773 case Stage1AirInstIdPhi:
24774 case IrInstGenIdBinOp:24774 case Stage1AirInstIdBinOp:
24775 case IrInstGenIdConst:24775 case Stage1AirInstIdConst:
24776 case IrInstGenIdCast:24776 case Stage1AirInstIdCast:
24777 case IrInstGenIdElemPtr:24777 case Stage1AirInstIdElemPtr:
24778 case IrInstGenIdVarPtr:24778 case Stage1AirInstIdVarPtr:
24779 case IrInstGenIdReturnPtr:24779 case Stage1AirInstIdReturnPtr:
24780 case IrInstGenIdStructFieldPtr:24780 case Stage1AirInstIdStructFieldPtr:
24781 case IrInstGenIdTestNonNull:24781 case Stage1AirInstIdTestNonNull:
24782 case IrInstGenIdClz:24782 case Stage1AirInstIdClz:
24783 case IrInstGenIdCtz:24783 case Stage1AirInstIdCtz:
24784 case IrInstGenIdPopCount:24784 case Stage1AirInstIdPopCount:
24785 case IrInstGenIdBswap:24785 case Stage1AirInstIdBswap:
24786 case IrInstGenIdBitReverse:24786 case Stage1AirInstIdBitReverse:
24787 case IrInstGenIdUnionTag:24787 case Stage1AirInstIdUnionTag:
24788 case IrInstGenIdTruncate:24788 case Stage1AirInstIdTruncate:
24789 case IrInstGenIdShuffleVector:24789 case Stage1AirInstIdShuffleVector:
24790 case IrInstGenIdSplat:24790 case Stage1AirInstIdSplat:
24791 case IrInstGenIdBoolNot:24791 case Stage1AirInstIdBoolNot:
24792 case IrInstGenIdReturnAddress:24792 case Stage1AirInstIdReturnAddress:
24793 case IrInstGenIdFrameAddress:24793 case Stage1AirInstIdFrameAddress:
24794 case IrInstGenIdFrameHandle:24794 case Stage1AirInstIdFrameHandle:
24795 case IrInstGenIdFrameSize:24795 case Stage1AirInstIdFrameSize:
24796 case IrInstGenIdTestErr:24796 case Stage1AirInstIdTestErr:
24797 case IrInstGenIdPtrCast:24797 case Stage1AirInstIdPtrCast:
24798 case IrInstGenIdBitCast:24798 case Stage1AirInstIdBitCast:
24799 case IrInstGenIdWidenOrShorten:24799 case Stage1AirInstIdWidenOrShorten:
24800 case IrInstGenIdPtrToInt:24800 case Stage1AirInstIdPtrToInt:
24801 case IrInstGenIdIntToPtr:24801 case Stage1AirInstIdIntToPtr:
24802 case IrInstGenIdIntToEnum:24802 case Stage1AirInstIdIntToEnum:
24803 case IrInstGenIdIntToErr:24803 case Stage1AirInstIdIntToErr:
24804 case IrInstGenIdErrToInt:24804 case Stage1AirInstIdErrToInt:
24805 case IrInstGenIdErrName:24805 case Stage1AirInstIdErrName:
24806 case IrInstGenIdTagName:24806 case Stage1AirInstIdTagName:
24807 case IrInstGenIdFieldParentPtr:24807 case Stage1AirInstIdFieldParentPtr:
24808 case IrInstGenIdAlignCast:24808 case Stage1AirInstIdAlignCast:
24809 case IrInstGenIdErrorReturnTrace:24809 case Stage1AirInstIdErrorReturnTrace:
24810 case IrInstGenIdFloatOp:24810 case Stage1AirInstIdFloatOp:
24811 case IrInstGenIdMulAdd:24811 case Stage1AirInstIdMulAdd:
24812 case IrInstGenIdAtomicLoad:24812 case Stage1AirInstIdAtomicLoad:
24813 case IrInstGenIdArrayToVector:24813 case Stage1AirInstIdArrayToVector:
24814 case IrInstGenIdAlloca:24814 case Stage1AirInstIdAlloca:
24815 case IrInstGenIdSpillEnd:24815 case Stage1AirInstIdSpillEnd:
24816 case IrInstGenIdVectorExtractElem:24816 case Stage1AirInstIdVectorExtractElem:
24817 case IrInstGenIdBinaryNot:24817 case Stage1AirInstIdBinaryNot:
24818 case IrInstGenIdNegation:24818 case Stage1AirInstIdNegation:
24819 case IrInstGenIdWasmMemorySize:24819 case Stage1AirInstIdWasmMemorySize:
24820 case IrInstGenIdReduce:24820 case Stage1AirInstIdReduce:
24821 return false;24821 return false;
2482224822
24823 case IrInstGenIdAsm:24823 case Stage1AirInstIdAsm:
24824 {24824 {
24825 IrInstGenAsm *asm_instruction = (IrInstGenAsm *)instruction;24825 Stage1AirInstAsm *asm_instruction = (Stage1AirInstAsm *)instruction;
24826 return asm_instruction->has_side_effects;24826 return asm_instruction->has_side_effects;
24827 }24827 }
24828 case IrInstGenIdUnwrapErrPayload:24828 case Stage1AirInstIdUnwrapErrPayload:
24829 {24829 {
24830 IrInstGenUnwrapErrPayload *unwrap_err_payload_instruction =24830 Stage1AirInstUnwrapErrPayload *unwrap_err_payload_instruction =
24831 (IrInstGenUnwrapErrPayload *)instruction;24831 (Stage1AirInstUnwrapErrPayload *)instruction;
24832 return unwrap_err_payload_instruction->safety_check_on ||24832 return unwrap_err_payload_instruction->safety_check_on ||
24833 unwrap_err_payload_instruction->initializing;24833 unwrap_err_payload_instruction->initializing;
24834 }24834 }
24835 case IrInstGenIdUnwrapErrCode:24835 case Stage1AirInstIdUnwrapErrCode:
24836 return reinterpret_cast<IrInstGenUnwrapErrCode *>(instruction)->initializing;24836 return reinterpret_cast<Stage1AirInstUnwrapErrCode *>(instruction)->initializing;
24837 case IrInstGenIdUnionFieldPtr:24837 case Stage1AirInstIdUnionFieldPtr:
24838 return reinterpret_cast<IrInstGenUnionFieldPtr *>(instruction)->initializing;24838 return reinterpret_cast<Stage1AirInstUnionFieldPtr *>(instruction)->initializing;
24839 case IrInstGenIdOptionalUnwrapPtr:24839 case Stage1AirInstIdOptionalUnwrapPtr:
24840 return reinterpret_cast<IrInstGenOptionalUnwrapPtr *>(instruction)->initializing;24840 return reinterpret_cast<Stage1AirInstOptionalUnwrapPtr *>(instruction)->initializing;
24841 case IrInstGenIdErrWrapPayload:24841 case Stage1AirInstIdErrWrapPayload:
24842 return reinterpret_cast<IrInstGenErrWrapPayload *>(instruction)->result_loc != nullptr;24842 return reinterpret_cast<Stage1AirInstErrWrapPayload *>(instruction)->result_loc != nullptr;
24843 case IrInstGenIdErrWrapCode:24843 case Stage1AirInstIdErrWrapCode:
24844 return reinterpret_cast<IrInstGenErrWrapCode *>(instruction)->result_loc != nullptr;24844 return reinterpret_cast<Stage1AirInstErrWrapCode *>(instruction)->result_loc != nullptr;
24845 case IrInstGenIdLoadPtr:24845 case Stage1AirInstIdLoadPtr:
24846 return reinterpret_cast<IrInstGenLoadPtr *>(instruction)->result_loc != nullptr;24846 return reinterpret_cast<Stage1AirInstLoadPtr *>(instruction)->result_loc != nullptr;
24847 case IrInstGenIdRef:24847 case Stage1AirInstIdRef:
24848 return reinterpret_cast<IrInstGenRef *>(instruction)->result_loc != nullptr;24848 return reinterpret_cast<Stage1AirInstRef *>(instruction)->result_loc != nullptr;
24849 }24849 }
24850 zig_unreachable();24850 zig_unreachable();
24851}24851}
2485224852
24853bool ir_inst_src_has_side_effects(IrInstSrc *instruction) {24853bool ir_inst_src_has_side_effects(Stage1ZirInst *instruction) {
24854 switch (instruction->id) {24854 switch (instruction->id) {
24855 case IrInstSrcIdInvalid:24855 case Stage1ZirInstIdInvalid:
24856 zig_unreachable();24856 zig_unreachable();
24857 case IrInstSrcIdBr:24857 case Stage1ZirInstIdBr:
24858 case IrInstSrcIdCondBr:24858 case Stage1ZirInstIdCondBr:
24859 case IrInstSrcIdSwitchBr:24859 case Stage1ZirInstIdSwitchBr:
24860 case IrInstSrcIdDeclVar:24860 case Stage1ZirInstIdDeclVar:
24861 case IrInstSrcIdStorePtr:24861 case Stage1ZirInstIdStorePtr:
24862 case IrInstSrcIdCallExtra:24862 case Stage1ZirInstIdCallExtra:
24863 case IrInstSrcIdAsyncCallExtra:24863 case Stage1ZirInstIdAsyncCallExtra:
24864 case IrInstSrcIdCall:24864 case Stage1ZirInstIdCall:
24865 case IrInstSrcIdCallArgs:24865 case Stage1ZirInstIdCallArgs:
24866 case IrInstSrcIdReturn:24866 case Stage1ZirInstIdReturn:
24867 case IrInstSrcIdUnreachable:24867 case Stage1ZirInstIdUnreachable:
24868 case IrInstSrcIdSetCold:24868 case Stage1ZirInstIdSetCold:
24869 case IrInstSrcIdSetRuntimeSafety:24869 case Stage1ZirInstIdSetRuntimeSafety:
24870 case IrInstSrcIdSetFloatMode:24870 case Stage1ZirInstIdSetFloatMode:
24871 case IrInstSrcIdImport:24871 case Stage1ZirInstIdImport:
24872 case IrInstSrcIdCompileErr:24872 case Stage1ZirInstIdCompileErr:
24873 case IrInstSrcIdCompileLog:24873 case Stage1ZirInstIdCompileLog:
24874 case IrInstSrcIdCImport:24874 case Stage1ZirInstIdCImport:
24875 case IrInstSrcIdCInclude:24875 case Stage1ZirInstIdCInclude:
24876 case IrInstSrcIdCDefine:24876 case Stage1ZirInstIdCDefine:
24877 case IrInstSrcIdCUndef:24877 case Stage1ZirInstIdCUndef:
24878 case IrInstSrcIdFence:24878 case Stage1ZirInstIdFence:
24879 case IrInstSrcIdMemset:24879 case Stage1ZirInstIdMemset:
24880 case IrInstSrcIdMemcpy:24880 case Stage1ZirInstIdMemcpy:
24881 case IrInstSrcIdBreakpoint:24881 case Stage1ZirInstIdBreakpoint:
24882 case IrInstSrcIdOverflowOp: // TODO when we support multiple returns this can be side effect free24882 case Stage1ZirInstIdOverflowOp: // TODO when we support multiple returns this can be side effect free
24883 case IrInstSrcIdCheckSwitchProngsUnderNo:24883 case Stage1ZirInstIdCheckSwitchProngsUnderNo:
24884 case IrInstSrcIdCheckSwitchProngsUnderYes:24884 case Stage1ZirInstIdCheckSwitchProngsUnderYes:
24885 case IrInstSrcIdCheckStatementIsVoid:24885 case Stage1ZirInstIdCheckStatementIsVoid:
24886 case IrInstSrcIdCheckRuntimeScope:24886 case Stage1ZirInstIdCheckRuntimeScope:
24887 case IrInstSrcIdPanic:24887 case Stage1ZirInstIdPanic:
24888 case IrInstSrcIdSetEvalBranchQuota:24888 case Stage1ZirInstIdSetEvalBranchQuota:
24889 case IrInstSrcIdPtrType:24889 case Stage1ZirInstIdPtrType:
24890 case IrInstSrcIdPtrTypeSimple:24890 case Stage1ZirInstIdPtrTypeSimple:
24891 case IrInstSrcIdPtrTypeSimpleConst:24891 case Stage1ZirInstIdPtrTypeSimpleConst:
24892 case IrInstSrcIdSetAlignStack:24892 case Stage1ZirInstIdSetAlignStack:
24893 case IrInstSrcIdExport:24893 case Stage1ZirInstIdExport:
24894 case IrInstSrcIdExtern:24894 case Stage1ZirInstIdExtern:
24895 case IrInstSrcIdSaveErrRetAddr:24895 case Stage1ZirInstIdSaveErrRetAddr:
24896 case IrInstSrcIdAddImplicitReturnType:24896 case Stage1ZirInstIdAddImplicitReturnType:
24897 case IrInstSrcIdAtomicRmw:24897 case Stage1ZirInstIdAtomicRmw:
24898 case IrInstSrcIdAtomicStore:24898 case Stage1ZirInstIdAtomicStore:
24899 case IrInstSrcIdCmpxchg:24899 case Stage1ZirInstIdCmpxchg:
24900 case IrInstSrcIdUndeclaredIdent:24900 case Stage1ZirInstIdUndeclaredIdent:
24901 case IrInstSrcIdEndExpr:24901 case Stage1ZirInstIdEndExpr:
24902 case IrInstSrcIdResetResult:24902 case Stage1ZirInstIdResetResult:
24903 case IrInstSrcIdSuspendBegin:24903 case Stage1ZirInstIdSuspendBegin:
24904 case IrInstSrcIdSuspendFinish:24904 case Stage1ZirInstIdSuspendFinish:
24905 case IrInstSrcIdResume:24905 case Stage1ZirInstIdResume:
24906 case IrInstSrcIdAwait:24906 case Stage1ZirInstIdAwait:
24907 case IrInstSrcIdSpillBegin:24907 case Stage1ZirInstIdSpillBegin:
24908 case IrInstSrcIdWasmMemoryGrow:24908 case Stage1ZirInstIdWasmMemoryGrow:
24909 return true;24909 return true;
2491024910
24911 case IrInstSrcIdPhi:24911 case Stage1ZirInstIdPhi:
24912 case IrInstSrcIdUnOp:24912 case Stage1ZirInstIdUnOp:
24913 case IrInstSrcIdBinOp:24913 case Stage1ZirInstIdBinOp:
24914 case IrInstSrcIdMergeErrSets:24914 case Stage1ZirInstIdMergeErrSets:
24915 case IrInstSrcIdLoadPtr:24915 case Stage1ZirInstIdLoadPtr:
24916 case IrInstSrcIdConst:24916 case Stage1ZirInstIdConst:
24917 case IrInstSrcIdContainerInitList:24917 case Stage1ZirInstIdContainerInitList:
24918 case IrInstSrcIdContainerInitFields:24918 case Stage1ZirInstIdContainerInitFields:
24919 case IrInstSrcIdUnionInitNamedField:24919 case Stage1ZirInstIdUnionInitNamedField:
24920 case IrInstSrcIdFieldPtr:24920 case Stage1ZirInstIdFieldPtr:
24921 case IrInstSrcIdElemPtr:24921 case Stage1ZirInstIdElemPtr:
24922 case IrInstSrcIdVarPtr:24922 case Stage1ZirInstIdVarPtr:
24923 case IrInstSrcIdTypeOf:24923 case Stage1ZirInstIdTypeOf:
24924 case IrInstSrcIdArrayType:24924 case Stage1ZirInstIdArrayType:
24925 case IrInstSrcIdSliceType:24925 case Stage1ZirInstIdSliceType:
24926 case IrInstSrcIdAnyFrameType:24926 case Stage1ZirInstIdAnyFrameType:
24927 case IrInstSrcIdSizeOf:24927 case Stage1ZirInstIdSizeOf:
24928 case IrInstSrcIdTestNonNull:24928 case Stage1ZirInstIdTestNonNull:
24929 case IrInstSrcIdOptionalUnwrapPtr:24929 case Stage1ZirInstIdOptionalUnwrapPtr:
24930 case IrInstSrcIdClz:24930 case Stage1ZirInstIdClz:
24931 case IrInstSrcIdCtz:24931 case Stage1ZirInstIdCtz:
24932 case IrInstSrcIdPopCount:24932 case Stage1ZirInstIdPopCount:
24933 case IrInstSrcIdBswap:24933 case Stage1ZirInstIdBswap:
24934 case IrInstSrcIdBitReverse:24934 case Stage1ZirInstIdBitReverse:
24935 case IrInstSrcIdSwitchVar:24935 case Stage1ZirInstIdSwitchVar:
24936 case IrInstSrcIdSwitchElseVar:24936 case Stage1ZirInstIdSwitchElseVar:
24937 case IrInstSrcIdSwitchTarget:24937 case Stage1ZirInstIdSwitchTarget:
24938 case IrInstSrcIdRef:24938 case Stage1ZirInstIdRef:
24939 case IrInstSrcIdEmbedFile:24939 case Stage1ZirInstIdEmbedFile:
24940 case IrInstSrcIdTruncate:24940 case Stage1ZirInstIdTruncate:
24941 case IrInstSrcIdVectorType:24941 case Stage1ZirInstIdVectorType:
24942 case IrInstSrcIdShuffleVector:24942 case Stage1ZirInstIdShuffleVector:
24943 case IrInstSrcIdSplat:24943 case Stage1ZirInstIdSplat:
24944 case IrInstSrcIdBoolNot:24944 case Stage1ZirInstIdBoolNot:
24945 case IrInstSrcIdSlice:24945 case Stage1ZirInstIdSlice:
24946 case IrInstSrcIdAlignOf:24946 case Stage1ZirInstIdAlignOf:
24947 case IrInstSrcIdReturnAddress:24947 case Stage1ZirInstIdReturnAddress:
24948 case IrInstSrcIdFrameAddress:24948 case Stage1ZirInstIdFrameAddress:
24949 case IrInstSrcIdFrameHandle:24949 case Stage1ZirInstIdFrameHandle:
24950 case IrInstSrcIdFrameType:24950 case Stage1ZirInstIdFrameType:
24951 case IrInstSrcIdFrameSize:24951 case Stage1ZirInstIdFrameSize:
24952 case IrInstSrcIdTestErr:24952 case Stage1ZirInstIdTestErr:
24953 case IrInstSrcIdFnProto:24953 case Stage1ZirInstIdFnProto:
24954 case IrInstSrcIdTestComptime:24954 case Stage1ZirInstIdTestComptime:
24955 case IrInstSrcIdPtrCast:24955 case Stage1ZirInstIdPtrCast:
24956 case IrInstSrcIdBitCast:24956 case Stage1ZirInstIdBitCast:
24957 case IrInstSrcIdPtrToInt:24957 case Stage1ZirInstIdPtrToInt:
24958 case IrInstSrcIdIntToPtr:24958 case Stage1ZirInstIdIntToPtr:
24959 case IrInstSrcIdIntToEnum:24959 case Stage1ZirInstIdIntToEnum:
24960 case IrInstSrcIdIntToErr:24960 case Stage1ZirInstIdIntToErr:
24961 case IrInstSrcIdErrToInt:24961 case Stage1ZirInstIdErrToInt:
24962 case IrInstSrcIdDeclRef:24962 case Stage1ZirInstIdDeclRef:
24963 case IrInstSrcIdErrName:24963 case Stage1ZirInstIdErrName:
24964 case IrInstSrcIdTypeName:24964 case Stage1ZirInstIdTypeName:
24965 case IrInstSrcIdTagName:24965 case Stage1ZirInstIdTagName:
24966 case IrInstSrcIdFieldParentPtr:24966 case Stage1ZirInstIdFieldParentPtr:
24967 case IrInstSrcIdOffsetOf:24967 case Stage1ZirInstIdOffsetOf:
24968 case IrInstSrcIdBitOffsetOf:24968 case Stage1ZirInstIdBitOffsetOf:
24969 case IrInstSrcIdTypeInfo:24969 case Stage1ZirInstIdTypeInfo:
24970 case IrInstSrcIdType:24970 case Stage1ZirInstIdType:
24971 case IrInstSrcIdHasField:24971 case Stage1ZirInstIdHasField:
24972 case IrInstSrcIdAlignCast:24972 case Stage1ZirInstIdAlignCast:
24973 case IrInstSrcIdImplicitCast:24973 case Stage1ZirInstIdImplicitCast:
24974 case IrInstSrcIdResolveResult:24974 case Stage1ZirInstIdResolveResult:
24975 case IrInstSrcIdArgTypeAllowVarFalse:24975 case Stage1ZirInstIdArgTypeAllowVarFalse:
24976 case IrInstSrcIdArgTypeAllowVarTrue:24976 case Stage1ZirInstIdArgTypeAllowVarTrue:
24977 case IrInstSrcIdErrorReturnTrace:24977 case Stage1ZirInstIdErrorReturnTrace:
24978 case IrInstSrcIdErrorUnion:24978 case Stage1ZirInstIdErrorUnion:
24979 case IrInstSrcIdFloatOp:24979 case Stage1ZirInstIdFloatOp:
24980 case IrInstSrcIdMulAdd:24980 case Stage1ZirInstIdMulAdd:
24981 case IrInstSrcIdAtomicLoad:24981 case Stage1ZirInstIdAtomicLoad:
24982 case IrInstSrcIdIntCast:24982 case Stage1ZirInstIdIntCast:
24983 case IrInstSrcIdFloatCast:24983 case Stage1ZirInstIdFloatCast:
24984 case IrInstSrcIdErrSetCast:24984 case Stage1ZirInstIdErrSetCast:
24985 case IrInstSrcIdIntToFloat:24985 case Stage1ZirInstIdIntToFloat:
24986 case IrInstSrcIdFloatToInt:24986 case Stage1ZirInstIdFloatToInt:
24987 case IrInstSrcIdBoolToInt:24987 case Stage1ZirInstIdBoolToInt:
24988 case IrInstSrcIdEnumToInt:24988 case Stage1ZirInstIdEnumToInt:
24989 case IrInstSrcIdHasDecl:24989 case Stage1ZirInstIdHasDecl:
24990 case IrInstSrcIdAlloca:24990 case Stage1ZirInstIdAlloca:
24991 case IrInstSrcIdSpillEnd:24991 case Stage1ZirInstIdSpillEnd:
24992 case IrInstSrcIdWasmMemorySize:24992 case Stage1ZirInstIdWasmMemorySize:
24993 case IrInstSrcIdSrc:24993 case Stage1ZirInstIdSrc:
24994 case IrInstSrcIdReduce:24994 case Stage1ZirInstIdReduce:
24995 return false;24995 return false;
2499624996
24997 case IrInstSrcIdAsm:24997 case Stage1ZirInstIdAsm:
24998 {24998 {
24999 IrInstSrcAsm *asm_instruction = (IrInstSrcAsm *)instruction;24999 Stage1ZirInstAsm *asm_instruction = (Stage1ZirInstAsm *)instruction;
25000 return asm_instruction->has_side_effects;25000 return asm_instruction->has_side_effects;
25001 }25001 }
2500225002
25003 case IrInstSrcIdUnwrapErrPayload:25003 case Stage1ZirInstIdUnwrapErrPayload:
25004 {25004 {
25005 IrInstSrcUnwrapErrPayload *unwrap_err_payload_instruction =25005 Stage1ZirInstUnwrapErrPayload *unwrap_err_payload_instruction =
25006 (IrInstSrcUnwrapErrPayload *)instruction;25006 (Stage1ZirInstUnwrapErrPayload *)instruction;
25007 return unwrap_err_payload_instruction->safety_check_on ||25007 return unwrap_err_payload_instruction->safety_check_on ||
25008 unwrap_err_payload_instruction->initializing;25008 unwrap_err_payload_instruction->initializing;
25009 }25009 }
25010 case IrInstSrcIdUnwrapErrCode:25010 case Stage1ZirInstIdUnwrapErrCode:
25011 return reinterpret_cast<IrInstSrcUnwrapErrCode *>(instruction)->initializing;25011 return reinterpret_cast<Stage1ZirInstUnwrapErrCode *>(instruction)->initializing;
25012 }25012 }
25013 zig_unreachable();25013 zig_unreachable();
25014}25014}
...@@ -25047,7 +25047,7 @@ static ZigType *ir_resolve_lazy_fn_type(IrAnalyze *ira, AstNode *source_node, La...@@ -25047,7 +25047,7 @@ static ZigType *ir_resolve_lazy_fn_type(IrAnalyze *ira, AstNode *source_node, La
25047 param_info->type = nullptr;25047 param_info->type = nullptr;
25048 return get_generic_fn_type(ira->codegen, &fn_type_id);25048 return get_generic_fn_type(ira->codegen, &fn_type_id);
25049 } else {25049 } else {
25050 IrInstGen *param_type_inst = lazy_fn_type->param_types[fn_type_id.next_param_index];25050 Stage1AirInst *param_type_inst = lazy_fn_type->param_types[fn_type_id.next_param_index];
25051 ZigType *param_type = ir_resolve_type(ira, param_type_inst);25051 ZigType *param_type = ir_resolve_type(ira, param_type_inst);
25052 if (type_is_invalid(param_type))25052 if (type_is_invalid(param_type))
25053 return nullptr;25053 return nullptr;
...@@ -25257,7 +25257,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) {...@@ -25257,7 +25257,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) {
25257 if (lazy_slice_type->sentinel != nullptr) {25257 if (lazy_slice_type->sentinel != nullptr) {
25258 if (type_is_invalid(lazy_slice_type->sentinel->value->type))25258 if (type_is_invalid(lazy_slice_type->sentinel->value->type))
25259 return ErrorSemanticAnalyzeFail;25259 return ErrorSemanticAnalyzeFail;
25260 IrInstGen *sentinel = ir_implicit_cast(ira, lazy_slice_type->sentinel, elem_type);25260 Stage1AirInst *sentinel = ir_implicit_cast(ira, lazy_slice_type->sentinel, elem_type);
25261 if (type_is_invalid(sentinel->value->type))25261 if (type_is_invalid(sentinel->value->type))
25262 return ErrorSemanticAnalyzeFail;25262 return ErrorSemanticAnalyzeFail;
25263 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);25263 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);
...@@ -25336,7 +25336,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) {...@@ -25336,7 +25336,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) {
25336 if (lazy_ptr_type->sentinel != nullptr) {25336 if (lazy_ptr_type->sentinel != nullptr) {
25337 if (type_is_invalid(lazy_ptr_type->sentinel->value->type))25337 if (type_is_invalid(lazy_ptr_type->sentinel->value->type))
25338 return ErrorSemanticAnalyzeFail;25338 return ErrorSemanticAnalyzeFail;
25339 IrInstGen *sentinel = ir_implicit_cast(ira, lazy_ptr_type->sentinel, elem_type);25339 Stage1AirInst *sentinel = ir_implicit_cast(ira, lazy_ptr_type->sentinel, elem_type);
25340 if (type_is_invalid(sentinel->value->type))25340 if (type_is_invalid(sentinel->value->type))
25341 return ErrorSemanticAnalyzeFail;25341 return ErrorSemanticAnalyzeFail;
25342 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);25342 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);
...@@ -25500,7 +25500,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) {...@@ -25500,7 +25500,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) {
25500 if (lazy_array_type->sentinel != nullptr) {25500 if (lazy_array_type->sentinel != nullptr) {
25501 if (type_is_invalid(lazy_array_type->sentinel->value->type))25501 if (type_is_invalid(lazy_array_type->sentinel->value->type))
25502 return ErrorSemanticAnalyzeFail;25502 return ErrorSemanticAnalyzeFail;
25503 IrInstGen *sentinel = ir_implicit_cast(ira, lazy_array_type->sentinel, elem_type);25503 Stage1AirInst *sentinel = ir_implicit_cast(ira, lazy_array_type->sentinel, elem_type);
25504 if (type_is_invalid(sentinel->value->type))25504 if (type_is_invalid(sentinel->value->type))
25505 return ErrorSemanticAnalyzeFail;25505 return ErrorSemanticAnalyzeFail;
25506 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);25506 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);
...@@ -25691,8 +25691,8 @@ Error ir_resolve_lazy(CodeGen *codegen, AstNode *source_node, ZigValue *val) {...@@ -25691,8 +25691,8 @@ Error ir_resolve_lazy(CodeGen *codegen, AstNode *source_node, ZigValue *val) {
25691 return ErrorNone;25691 return ErrorNone;
25692}25692}
2569325693
25694void IrInstGen::src() {25694void Stage1AirInst::src() {
25695 IrInstGen *inst = this;25695 Stage1AirInst *inst = this;
25696 if (inst->source_node != nullptr) {25696 if (inst->source_node != nullptr) {
25697 inst->source_node->src();25697 inst->source_node->src();
25698 } else {25698 } else {
...@@ -25700,8 +25700,8 @@ void IrInstGen::src() {...@@ -25700,8 +25700,8 @@ void IrInstGen::src() {
25700 }25700 }
25701}25701}
2570225702
25703void IrInstGen::dump() {25703void Stage1AirInst::dump() {
25704 IrInstGen *inst = this;25704 Stage1AirInst *inst = this;
25705 inst->src();25705 inst->src();
25706 if (inst->scope == nullptr) {25706 if (inst->scope == nullptr) {
25707 fprintf(stderr, "(null scope)\n");25707 fprintf(stderr, "(null scope)\n");
src/stage1/ir.hpp+2-2
...@@ -10,7 +10,7 @@...@@ -10,7 +10,7 @@
1010
11#include "all_types.hpp"11#include "all_types.hpp"
1212
13IrInstGen *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn,13Stage1AirInst *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn,
14 ZigType *var_type, const char *name_hint);14 ZigType *var_type, const char *name_hint);
1515
16Error ir_eval_const_value(CodeGen *codegen, Scope *scope, AstNode *node,16Error ir_eval_const_value(CodeGen *codegen, Scope *scope, AstNode *node,
...@@ -25,7 +25,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a...@@ -25,7 +25,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
25 ZigType *expected_type, AstNode *expected_type_source_node, ZigValue *result_ptr,25 ZigType *expected_type, AstNode *expected_type_source_node, ZigValue *result_ptr,
26 ZigFn *fn);26 ZigFn *fn);
2727
28bool ir_inst_gen_has_side_effects(IrInstGen *inst);28bool ir_inst_gen_has_side_effects(Stage1AirInst *inst);
2929
30struct IrAnalyze;30struct IrAnalyze;
31ZigValue *const_ptr_pointee(IrAnalyze *ira, CodeGen *codegen, ZigValue *const_val,31ZigValue *const_ptr_pointee(IrAnalyze *ira, CodeGen *codegen, ZigValue *const_val,
src/stage1/ir_print.cpp+955-955
...@@ -12,26 +12,26 @@...@@ -12,26 +12,26 @@
12#include "ir_print.hpp"12#include "ir_print.hpp"
13#include "os.hpp"13#include "os.hpp"
1414
15static uint32_t hash_inst_src_ptr(IrInstSrc* instruction) {15static uint32_t hash_inst_src_ptr(Stage1ZirInst* instruction) {
16 return (uint32_t)(uintptr_t)instruction;16 return (uint32_t)(uintptr_t)instruction;
17}17}
1818
19static uint32_t hash_inst_gen_ptr(IrInstGen* instruction) {19static uint32_t hash_inst_gen_ptr(Stage1AirInst* instruction) {
20 return (uint32_t)(uintptr_t)instruction;20 return (uint32_t)(uintptr_t)instruction;
21}21}
2222
23static bool inst_src_ptr_eql(IrInstSrc* a, IrInstSrc* b) {23static bool inst_src_ptr_eql(Stage1ZirInst* a, Stage1ZirInst* b) {
24 return a == b;24 return a == b;
25}25}
2626
27static bool inst_gen_ptr_eql(IrInstGen* a, IrInstGen* b) {27static bool inst_gen_ptr_eql(Stage1AirInst* a, Stage1AirInst* b) {
28 return a == b;28 return a == b;
29}29}
3030
31using InstSetSrc = HashMap<IrInstSrc*, uint8_t, hash_inst_src_ptr, inst_src_ptr_eql>;31using InstSetSrc = HashMap<Stage1ZirInst*, uint8_t, hash_inst_src_ptr, inst_src_ptr_eql>;
32using InstSetGen = HashMap<IrInstGen*, uint8_t, hash_inst_gen_ptr, inst_gen_ptr_eql>;32using InstSetGen = HashMap<Stage1AirInst*, uint8_t, hash_inst_gen_ptr, inst_gen_ptr_eql>;
33using InstListSrc = ZigList<IrInstSrc*>;33using InstListSrc = ZigList<Stage1ZirInst*>;
34using InstListGen = ZigList<IrInstGen*>;34using InstListGen = ZigList<Stage1AirInst*>;
3535
36struct IrPrintSrc {36struct IrPrintSrc {
37 CodeGen *codegen;37 CodeGen *codegen;
...@@ -54,8 +54,8 @@ struct IrPrintGen {...@@ -54,8 +54,8 @@ struct IrPrintGen {
54 InstListGen pending;54 InstListGen pending;
55};55};
5656
57static void ir_print_other_inst_src(IrPrintSrc *irp, IrInstSrc *inst);57static void ir_print_other_inst_src(IrPrintSrc *irp, Stage1ZirInst *inst);
58static void ir_print_other_inst_gen(IrPrintGen *irp, IrInstGen *inst);58static void ir_print_other_inst_gen(IrPrintGen *irp, Stage1AirInst *inst);
5959
60static void ir_print_call_modifier(FILE *f, CallModifier modifier) {60static void ir_print_call_modifier(FILE *f, CallModifier modifier) {
61 switch (modifier) {61 switch (modifier) {
...@@ -87,473 +87,473 @@ static void ir_print_call_modifier(FILE *f, CallModifier modifier) {...@@ -87,473 +87,473 @@ static void ir_print_call_modifier(FILE *f, CallModifier modifier) {
87 }87 }
88}88}
8989
90const char* ir_inst_src_type_str(IrInstSrcId id) {90const char* ir_inst_src_type_str(Stage1ZirInstId id) {
91 switch (id) {91 switch (id) {
92 case IrInstSrcIdInvalid:92 case Stage1ZirInstIdInvalid:
93 return "SrcInvalid";93 return "SrcInvalid";
94 case IrInstSrcIdShuffleVector:94 case Stage1ZirInstIdShuffleVector:
95 return "SrcShuffle";95 return "SrcShuffle";
96 case IrInstSrcIdSplat:96 case Stage1ZirInstIdSplat:
97 return "SrcSplat";97 return "SrcSplat";
98 case IrInstSrcIdDeclVar:98 case Stage1ZirInstIdDeclVar:
99 return "SrcDeclVar";99 return "SrcDeclVar";
100 case IrInstSrcIdBr:100 case Stage1ZirInstIdBr:
101 return "SrcBr";101 return "SrcBr";
102 case IrInstSrcIdCondBr:102 case Stage1ZirInstIdCondBr:
103 return "SrcCondBr";103 return "SrcCondBr";
104 case IrInstSrcIdSwitchBr:104 case Stage1ZirInstIdSwitchBr:
105 return "SrcSwitchBr";105 return "SrcSwitchBr";
106 case IrInstSrcIdSwitchVar:106 case Stage1ZirInstIdSwitchVar:
107 return "SrcSwitchVar";107 return "SrcSwitchVar";
108 case IrInstSrcIdSwitchElseVar:108 case Stage1ZirInstIdSwitchElseVar:
109 return "SrcSwitchElseVar";109 return "SrcSwitchElseVar";
110 case IrInstSrcIdSwitchTarget:110 case Stage1ZirInstIdSwitchTarget:
111 return "SrcSwitchTarget";111 return "SrcSwitchTarget";
112 case IrInstSrcIdPhi:112 case Stage1ZirInstIdPhi:
113 return "SrcPhi";113 return "SrcPhi";
114 case IrInstSrcIdUnOp:114 case Stage1ZirInstIdUnOp:
115 return "SrcUnOp";115 return "SrcUnOp";
116 case IrInstSrcIdBinOp:116 case Stage1ZirInstIdBinOp:
117 return "SrcBinOp";117 return "SrcBinOp";
118 case IrInstSrcIdMergeErrSets:118 case Stage1ZirInstIdMergeErrSets:
119 return "SrcMergeErrSets";119 return "SrcMergeErrSets";
120 case IrInstSrcIdLoadPtr:120 case Stage1ZirInstIdLoadPtr:
121 return "SrcLoadPtr";121 return "SrcLoadPtr";
122 case IrInstSrcIdStorePtr:122 case Stage1ZirInstIdStorePtr:
123 return "SrcStorePtr";123 return "SrcStorePtr";
124 case IrInstSrcIdFieldPtr:124 case Stage1ZirInstIdFieldPtr:
125 return "SrcFieldPtr";125 return "SrcFieldPtr";
126 case IrInstSrcIdElemPtr:126 case Stage1ZirInstIdElemPtr:
127 return "SrcElemPtr";127 return "SrcElemPtr";
128 case IrInstSrcIdVarPtr:128 case Stage1ZirInstIdVarPtr:
129 return "SrcVarPtr";129 return "SrcVarPtr";
130 case IrInstSrcIdCallExtra:130 case Stage1ZirInstIdCallExtra:
131 return "SrcCallExtra";131 return "SrcCallExtra";
132 case IrInstSrcIdAsyncCallExtra:132 case Stage1ZirInstIdAsyncCallExtra:
133 return "SrcAsyncCallExtra";133 return "SrcAsyncCallExtra";
134 case IrInstSrcIdCall:134 case Stage1ZirInstIdCall:
135 return "SrcCall";135 return "SrcCall";
136 case IrInstSrcIdCallArgs:136 case Stage1ZirInstIdCallArgs:
137 return "SrcCallArgs";137 return "SrcCallArgs";
138 case IrInstSrcIdConst:138 case Stage1ZirInstIdConst:
139 return "SrcConst";139 return "SrcConst";
140 case IrInstSrcIdReturn:140 case Stage1ZirInstIdReturn:
141 return "SrcReturn";141 return "SrcReturn";
142 case IrInstSrcIdContainerInitList:142 case Stage1ZirInstIdContainerInitList:
143 return "SrcContainerInitList";143 return "SrcContainerInitList";
144 case IrInstSrcIdContainerInitFields:144 case Stage1ZirInstIdContainerInitFields:
145 return "SrcContainerInitFields";145 return "SrcContainerInitFields";
146 case IrInstSrcIdUnreachable:146 case Stage1ZirInstIdUnreachable:
147 return "SrcUnreachable";147 return "SrcUnreachable";
148 case IrInstSrcIdTypeOf:148 case Stage1ZirInstIdTypeOf:
149 return "SrcTypeOf";149 return "SrcTypeOf";
150 case IrInstSrcIdSetCold:150 case Stage1ZirInstIdSetCold:
151 return "SrcSetCold";151 return "SrcSetCold";
152 case IrInstSrcIdSetRuntimeSafety:152 case Stage1ZirInstIdSetRuntimeSafety:
153 return "SrcSetRuntimeSafety";153 return "SrcSetRuntimeSafety";
154 case IrInstSrcIdSetFloatMode:154 case Stage1ZirInstIdSetFloatMode:
155 return "SrcSetFloatMode";155 return "SrcSetFloatMode";
156 case IrInstSrcIdArrayType:156 case Stage1ZirInstIdArrayType:
157 return "SrcArrayType";157 return "SrcArrayType";
158 case IrInstSrcIdAnyFrameType:158 case Stage1ZirInstIdAnyFrameType:
159 return "SrcAnyFrameType";159 return "SrcAnyFrameType";
160 case IrInstSrcIdSliceType:160 case Stage1ZirInstIdSliceType:
161 return "SrcSliceType";161 return "SrcSliceType";
162 case IrInstSrcIdAsm:162 case Stage1ZirInstIdAsm:
163 return "SrcAsm";163 return "SrcAsm";
164 case IrInstSrcIdSizeOf:164 case Stage1ZirInstIdSizeOf:
165 return "SrcSizeOf";165 return "SrcSizeOf";
166 case IrInstSrcIdTestNonNull:166 case Stage1ZirInstIdTestNonNull:
167 return "SrcTestNonNull";167 return "SrcTestNonNull";
168 case IrInstSrcIdOptionalUnwrapPtr:168 case Stage1ZirInstIdOptionalUnwrapPtr:
169 return "SrcOptionalUnwrapPtr";169 return "SrcOptionalUnwrapPtr";
170 case IrInstSrcIdClz:170 case Stage1ZirInstIdClz:
171 return "SrcClz";171 return "SrcClz";
172 case IrInstSrcIdCtz:172 case Stage1ZirInstIdCtz:
173 return "SrcCtz";173 return "SrcCtz";
174 case IrInstSrcIdPopCount:174 case Stage1ZirInstIdPopCount:
175 return "SrcPopCount";175 return "SrcPopCount";
176 case IrInstSrcIdBswap:176 case Stage1ZirInstIdBswap:
177 return "SrcBswap";177 return "SrcBswap";
178 case IrInstSrcIdBitReverse:178 case Stage1ZirInstIdBitReverse:
179 return "SrcBitReverse";179 return "SrcBitReverse";
180 case IrInstSrcIdImport:180 case Stage1ZirInstIdImport:
181 return "SrcImport";181 return "SrcImport";
182 case IrInstSrcIdCImport:182 case Stage1ZirInstIdCImport:
183 return "SrcCImport";183 return "SrcCImport";
184 case IrInstSrcIdCInclude:184 case Stage1ZirInstIdCInclude:
185 return "SrcCInclude";185 return "SrcCInclude";
186 case IrInstSrcIdCDefine:186 case Stage1ZirInstIdCDefine:
187 return "SrcCDefine";187 return "SrcCDefine";
188 case IrInstSrcIdCUndef:188 case Stage1ZirInstIdCUndef:
189 return "SrcCUndef";189 return "SrcCUndef";
190 case IrInstSrcIdRef:190 case Stage1ZirInstIdRef:
191 return "SrcRef";191 return "SrcRef";
192 case IrInstSrcIdCompileErr:192 case Stage1ZirInstIdCompileErr:
193 return "SrcCompileErr";193 return "SrcCompileErr";
194 case IrInstSrcIdCompileLog:194 case Stage1ZirInstIdCompileLog:
195 return "SrcCompileLog";195 return "SrcCompileLog";
196 case IrInstSrcIdErrName:196 case Stage1ZirInstIdErrName:
197 return "SrcErrName";197 return "SrcErrName";
198 case IrInstSrcIdEmbedFile:198 case Stage1ZirInstIdEmbedFile:
199 return "SrcEmbedFile";199 return "SrcEmbedFile";
200 case IrInstSrcIdCmpxchg:200 case Stage1ZirInstIdCmpxchg:
201 return "SrcCmpxchg";201 return "SrcCmpxchg";
202 case IrInstSrcIdFence:202 case Stage1ZirInstIdFence:
203 return "SrcFence";203 return "SrcFence";
204 case IrInstSrcIdReduce:204 case Stage1ZirInstIdReduce:
205 return "SrcReduce";205 return "SrcReduce";
206 case IrInstSrcIdTruncate:206 case Stage1ZirInstIdTruncate:
207 return "SrcTruncate";207 return "SrcTruncate";
208 case IrInstSrcIdIntCast:208 case Stage1ZirInstIdIntCast:
209 return "SrcIntCast";209 return "SrcIntCast";
210 case IrInstSrcIdFloatCast:210 case Stage1ZirInstIdFloatCast:
211 return "SrcFloatCast";211 return "SrcFloatCast";
212 case IrInstSrcIdIntToFloat:212 case Stage1ZirInstIdIntToFloat:
213 return "SrcIntToFloat";213 return "SrcIntToFloat";
214 case IrInstSrcIdFloatToInt:214 case Stage1ZirInstIdFloatToInt:
215 return "SrcFloatToInt";215 return "SrcFloatToInt";
216 case IrInstSrcIdBoolToInt:216 case Stage1ZirInstIdBoolToInt:
217 return "SrcBoolToInt";217 return "SrcBoolToInt";
218 case IrInstSrcIdVectorType:218 case Stage1ZirInstIdVectorType:
219 return "SrcVectorType";219 return "SrcVectorType";
220 case IrInstSrcIdBoolNot:220 case Stage1ZirInstIdBoolNot:
221 return "SrcBoolNot";221 return "SrcBoolNot";
222 case IrInstSrcIdMemset:222 case Stage1ZirInstIdMemset:
223 return "SrcMemset";223 return "SrcMemset";
224 case IrInstSrcIdMemcpy:224 case Stage1ZirInstIdMemcpy:
225 return "SrcMemcpy";225 return "SrcMemcpy";
226 case IrInstSrcIdSlice:226 case Stage1ZirInstIdSlice:
227 return "SrcSlice";227 return "SrcSlice";
228 case IrInstSrcIdBreakpoint:228 case Stage1ZirInstIdBreakpoint:
229 return "SrcBreakpoint";229 return "SrcBreakpoint";
230 case IrInstSrcIdReturnAddress:230 case Stage1ZirInstIdReturnAddress:
231 return "SrcReturnAddress";231 return "SrcReturnAddress";
232 case IrInstSrcIdFrameAddress:232 case Stage1ZirInstIdFrameAddress:
233 return "SrcFrameAddress";233 return "SrcFrameAddress";
234 case IrInstSrcIdFrameHandle:234 case Stage1ZirInstIdFrameHandle:
235 return "SrcFrameHandle";235 return "SrcFrameHandle";
236 case IrInstSrcIdFrameType:236 case Stage1ZirInstIdFrameType:
237 return "SrcFrameType";237 return "SrcFrameType";
238 case IrInstSrcIdFrameSize:238 case Stage1ZirInstIdFrameSize:
239 return "SrcFrameSize";239 return "SrcFrameSize";
240 case IrInstSrcIdAlignOf:240 case Stage1ZirInstIdAlignOf:
241 return "SrcAlignOf";241 return "SrcAlignOf";
242 case IrInstSrcIdOverflowOp:242 case Stage1ZirInstIdOverflowOp:
243 return "SrcOverflowOp";243 return "SrcOverflowOp";
244 case IrInstSrcIdTestErr:244 case Stage1ZirInstIdTestErr:
245 return "SrcTestErr";245 return "SrcTestErr";
246 case IrInstSrcIdMulAdd:246 case Stage1ZirInstIdMulAdd:
247 return "SrcMulAdd";247 return "SrcMulAdd";
248 case IrInstSrcIdFloatOp:248 case Stage1ZirInstIdFloatOp:
249 return "SrcFloatOp";249 return "SrcFloatOp";
250 case IrInstSrcIdUnwrapErrCode:250 case Stage1ZirInstIdUnwrapErrCode:
251 return "SrcUnwrapErrCode";251 return "SrcUnwrapErrCode";
252 case IrInstSrcIdUnwrapErrPayload:252 case Stage1ZirInstIdUnwrapErrPayload:
253 return "SrcUnwrapErrPayload";253 return "SrcUnwrapErrPayload";
254 case IrInstSrcIdFnProto:254 case Stage1ZirInstIdFnProto:
255 return "SrcFnProto";255 return "SrcFnProto";
256 case IrInstSrcIdTestComptime:256 case Stage1ZirInstIdTestComptime:
257 return "SrcTestComptime";257 return "SrcTestComptime";
258 case IrInstSrcIdPtrCast:258 case Stage1ZirInstIdPtrCast:
259 return "SrcPtrCast";259 return "SrcPtrCast";
260 case IrInstSrcIdBitCast:260 case Stage1ZirInstIdBitCast:
261 return "SrcBitCast";261 return "SrcBitCast";
262 case IrInstSrcIdIntToPtr:262 case Stage1ZirInstIdIntToPtr:
263 return "SrcIntToPtr";263 return "SrcIntToPtr";
264 case IrInstSrcIdPtrToInt:264 case Stage1ZirInstIdPtrToInt:
265 return "SrcPtrToInt";265 return "SrcPtrToInt";
266 case IrInstSrcIdIntToEnum:266 case Stage1ZirInstIdIntToEnum:
267 return "SrcIntToEnum";267 return "SrcIntToEnum";
268 case IrInstSrcIdEnumToInt:268 case Stage1ZirInstIdEnumToInt:
269 return "SrcEnumToInt";269 return "SrcEnumToInt";
270 case IrInstSrcIdIntToErr:270 case Stage1ZirInstIdIntToErr:
271 return "SrcIntToErr";271 return "SrcIntToErr";
272 case IrInstSrcIdErrToInt:272 case Stage1ZirInstIdErrToInt:
273 return "SrcErrToInt";273 return "SrcErrToInt";
274 case IrInstSrcIdCheckSwitchProngsUnderNo:274 case Stage1ZirInstIdCheckSwitchProngsUnderNo:
275 return "SrcCheckSwitchProngsUnderNo";275 return "SrcCheckSwitchProngsUnderNo";
276 case IrInstSrcIdCheckSwitchProngsUnderYes:276 case Stage1ZirInstIdCheckSwitchProngsUnderYes:
277 return "SrcCheckSwitchProngsUnderYes";277 return "SrcCheckSwitchProngsUnderYes";
278 case IrInstSrcIdCheckStatementIsVoid:278 case Stage1ZirInstIdCheckStatementIsVoid:
279 return "SrcCheckStatementIsVoid";279 return "SrcCheckStatementIsVoid";
280 case IrInstSrcIdTypeName:280 case Stage1ZirInstIdTypeName:
281 return "SrcTypeName";281 return "SrcTypeName";
282 case IrInstSrcIdDeclRef:282 case Stage1ZirInstIdDeclRef:
283 return "SrcDeclRef";283 return "SrcDeclRef";
284 case IrInstSrcIdPanic:284 case Stage1ZirInstIdPanic:
285 return "SrcPanic";285 return "SrcPanic";
286 case IrInstSrcIdTagName:286 case Stage1ZirInstIdTagName:
287 return "SrcTagName";287 return "SrcTagName";
288 case IrInstSrcIdFieldParentPtr:288 case Stage1ZirInstIdFieldParentPtr:
289 return "SrcFieldParentPtr";289 return "SrcFieldParentPtr";
290 case IrInstSrcIdOffsetOf:290 case Stage1ZirInstIdOffsetOf:
291 return "SrcOffsetOf";291 return "SrcOffsetOf";
292 case IrInstSrcIdBitOffsetOf:292 case Stage1ZirInstIdBitOffsetOf:
293 return "SrcBitOffsetOf";293 return "SrcBitOffsetOf";
294 case IrInstSrcIdTypeInfo:294 case Stage1ZirInstIdTypeInfo:
295 return "SrcTypeInfo";295 return "SrcTypeInfo";
296 case IrInstSrcIdType:296 case Stage1ZirInstIdType:
297 return "SrcType";297 return "SrcType";
298 case IrInstSrcIdHasField:298 case Stage1ZirInstIdHasField:
299 return "SrcHasField";299 return "SrcHasField";
300 case IrInstSrcIdSetEvalBranchQuota:300 case Stage1ZirInstIdSetEvalBranchQuota:
301 return "SrcSetEvalBranchQuota";301 return "SrcSetEvalBranchQuota";
302 case IrInstSrcIdPtrType:302 case Stage1ZirInstIdPtrType:
303 return "SrcPtrType";303 return "SrcPtrType";
304 case IrInstSrcIdPtrTypeSimple:304 case Stage1ZirInstIdPtrTypeSimple:
305 return "SrcPtrTypeSimple";305 return "SrcPtrTypeSimple";
306 case IrInstSrcIdPtrTypeSimpleConst:306 case Stage1ZirInstIdPtrTypeSimpleConst:
307 return "SrcPtrTypeSimpleConst";307 return "SrcPtrTypeSimpleConst";
308 case IrInstSrcIdAlignCast:308 case Stage1ZirInstIdAlignCast:
309 return "SrcAlignCast";309 return "SrcAlignCast";
310 case IrInstSrcIdImplicitCast:310 case Stage1ZirInstIdImplicitCast:
311 return "SrcImplicitCast";311 return "SrcImplicitCast";
312 case IrInstSrcIdResolveResult:312 case Stage1ZirInstIdResolveResult:
313 return "SrcResolveResult";313 return "SrcResolveResult";
314 case IrInstSrcIdResetResult:314 case Stage1ZirInstIdResetResult:
315 return "SrcResetResult";315 return "SrcResetResult";
316 case IrInstSrcIdSetAlignStack:316 case Stage1ZirInstIdSetAlignStack:
317 return "SrcSetAlignStack";317 return "SrcSetAlignStack";
318 case IrInstSrcIdArgTypeAllowVarFalse:318 case Stage1ZirInstIdArgTypeAllowVarFalse:
319 return "SrcArgTypeAllowVarFalse";319 return "SrcArgTypeAllowVarFalse";
320 case IrInstSrcIdArgTypeAllowVarTrue:320 case Stage1ZirInstIdArgTypeAllowVarTrue:
321 return "SrcArgTypeAllowVarTrue";321 return "SrcArgTypeAllowVarTrue";
322 case IrInstSrcIdExport:322 case Stage1ZirInstIdExport:
323 return "SrcExport";323 return "SrcExport";
324 case IrInstSrcIdExtern:324 case Stage1ZirInstIdExtern:
325 return "SrcExtern";325 return "SrcExtern";
326 case IrInstSrcIdErrorReturnTrace:326 case Stage1ZirInstIdErrorReturnTrace:
327 return "SrcErrorReturnTrace";327 return "SrcErrorReturnTrace";
328 case IrInstSrcIdErrorUnion:328 case Stage1ZirInstIdErrorUnion:
329 return "SrcErrorUnion";329 return "SrcErrorUnion";
330 case IrInstSrcIdAtomicRmw:330 case Stage1ZirInstIdAtomicRmw:
331 return "SrcAtomicRmw";331 return "SrcAtomicRmw";
332 case IrInstSrcIdAtomicLoad:332 case Stage1ZirInstIdAtomicLoad:
333 return "SrcAtomicLoad";333 return "SrcAtomicLoad";
334 case IrInstSrcIdAtomicStore:334 case Stage1ZirInstIdAtomicStore:
335 return "SrcAtomicStore";335 return "SrcAtomicStore";
336 case IrInstSrcIdSaveErrRetAddr:336 case Stage1ZirInstIdSaveErrRetAddr:
337 return "SrcSaveErrRetAddr";337 return "SrcSaveErrRetAddr";
338 case IrInstSrcIdAddImplicitReturnType:338 case Stage1ZirInstIdAddImplicitReturnType:
339 return "SrcAddImplicitReturnType";339 return "SrcAddImplicitReturnType";
340 case IrInstSrcIdErrSetCast:340 case Stage1ZirInstIdErrSetCast:
341 return "SrcErrSetCast";341 return "SrcErrSetCast";
342 case IrInstSrcIdCheckRuntimeScope:342 case Stage1ZirInstIdCheckRuntimeScope:
343 return "SrcCheckRuntimeScope";343 return "SrcCheckRuntimeScope";
344 case IrInstSrcIdHasDecl:344 case Stage1ZirInstIdHasDecl:
345 return "SrcHasDecl";345 return "SrcHasDecl";
346 case IrInstSrcIdUndeclaredIdent:346 case Stage1ZirInstIdUndeclaredIdent:
347 return "SrcUndeclaredIdent";347 return "SrcUndeclaredIdent";
348 case IrInstSrcIdAlloca:348 case Stage1ZirInstIdAlloca:
349 return "SrcAlloca";349 return "SrcAlloca";
350 case IrInstSrcIdEndExpr:350 case Stage1ZirInstIdEndExpr:
351 return "SrcEndExpr";351 return "SrcEndExpr";
352 case IrInstSrcIdUnionInitNamedField:352 case Stage1ZirInstIdUnionInitNamedField:
353 return "SrcUnionInitNamedField";353 return "SrcUnionInitNamedField";
354 case IrInstSrcIdSuspendBegin:354 case Stage1ZirInstIdSuspendBegin:
355 return "SrcSuspendBegin";355 return "SrcSuspendBegin";
356 case IrInstSrcIdSuspendFinish:356 case Stage1ZirInstIdSuspendFinish:
357 return "SrcSuspendFinish";357 return "SrcSuspendFinish";
358 case IrInstSrcIdAwait:358 case Stage1ZirInstIdAwait:
359 return "SrcAwaitSr";359 return "SrcAwaitSr";
360 case IrInstSrcIdResume:360 case Stage1ZirInstIdResume:
361 return "SrcResume";361 return "SrcResume";
362 case IrInstSrcIdSpillBegin:362 case Stage1ZirInstIdSpillBegin:
363 return "SrcSpillBegin";363 return "SrcSpillBegin";
364 case IrInstSrcIdSpillEnd:364 case Stage1ZirInstIdSpillEnd:
365 return "SrcSpillEnd";365 return "SrcSpillEnd";
366 case IrInstSrcIdWasmMemorySize:366 case Stage1ZirInstIdWasmMemorySize:
367 return "SrcWasmMemorySize";367 return "SrcWasmMemorySize";
368 case IrInstSrcIdWasmMemoryGrow:368 case Stage1ZirInstIdWasmMemoryGrow:
369 return "SrcWasmMemoryGrow";369 return "SrcWasmMemoryGrow";
370 case IrInstSrcIdSrc:370 case Stage1ZirInstIdSrc:
371 return "SrcSrc";371 return "SrcSrc";
372 }372 }
373 zig_unreachable();373 zig_unreachable();
374}374}
375375
376const char* ir_inst_gen_type_str(IrInstGenId id) {376const char* ir_inst_gen_type_str(Stage1AirInstId id) {
377 switch (id) {377 switch (id) {
378 case IrInstGenIdInvalid:378 case Stage1AirInstIdInvalid:
379 return "GenInvalid";379 return "GenInvalid";
380 case IrInstGenIdShuffleVector:380 case Stage1AirInstIdShuffleVector:
381 return "GenShuffle";381 return "GenShuffle";
382 case IrInstGenIdSplat:382 case Stage1AirInstIdSplat:
383 return "GenSplat";383 return "GenSplat";
384 case IrInstGenIdDeclVar:384 case Stage1AirInstIdDeclVar:
385 return "GenDeclVar";385 return "GenDeclVar";
386 case IrInstGenIdBr:386 case Stage1AirInstIdBr:
387 return "GenBr";387 return "GenBr";
388 case IrInstGenIdCondBr:388 case Stage1AirInstIdCondBr:
389 return "GenCondBr";389 return "GenCondBr";
390 case IrInstGenIdSwitchBr:390 case Stage1AirInstIdSwitchBr:
391 return "GenSwitchBr";391 return "GenSwitchBr";
392 case IrInstGenIdPhi:392 case Stage1AirInstIdPhi:
393 return "GenPhi";393 return "GenPhi";
394 case IrInstGenIdBinOp:394 case Stage1AirInstIdBinOp:
395 return "GenBinOp";395 return "GenBinOp";
396 case IrInstGenIdLoadPtr:396 case Stage1AirInstIdLoadPtr:
397 return "GenLoadPtr";397 return "GenLoadPtr";
398 case IrInstGenIdStorePtr:398 case Stage1AirInstIdStorePtr:
399 return "GenStorePtr";399 return "GenStorePtr";
400 case IrInstGenIdVectorStoreElem:400 case Stage1AirInstIdVectorStoreElem:
401 return "GenVectorStoreElem";401 return "GenVectorStoreElem";
402 case IrInstGenIdStructFieldPtr:402 case Stage1AirInstIdStructFieldPtr:
403 return "GenStructFieldPtr";403 return "GenStructFieldPtr";
404 case IrInstGenIdUnionFieldPtr:404 case Stage1AirInstIdUnionFieldPtr:
405 return "GenUnionFieldPtr";405 return "GenUnionFieldPtr";
406 case IrInstGenIdElemPtr:406 case Stage1AirInstIdElemPtr:
407 return "GenElemPtr";407 return "GenElemPtr";
408 case IrInstGenIdVarPtr:408 case Stage1AirInstIdVarPtr:
409 return "GenVarPtr";409 return "GenVarPtr";
410 case IrInstGenIdReturnPtr:410 case Stage1AirInstIdReturnPtr:
411 return "GenReturnPtr";411 return "GenReturnPtr";
412 case IrInstGenIdCall:412 case Stage1AirInstIdCall:
413 return "GenCall";413 return "GenCall";
414 case IrInstGenIdConst:414 case Stage1AirInstIdConst:
415 return "GenConst";415 return "GenConst";
416 case IrInstGenIdReturn:416 case Stage1AirInstIdReturn:
417 return "GenReturn";417 return "GenReturn";
418 case IrInstGenIdCast:418 case Stage1AirInstIdCast:
419 return "GenCast";419 return "GenCast";
420 case IrInstGenIdUnreachable:420 case Stage1AirInstIdUnreachable:
421 return "GenUnreachable";421 return "GenUnreachable";
422 case IrInstGenIdAsm:422 case Stage1AirInstIdAsm:
423 return "GenAsm";423 return "GenAsm";
424 case IrInstGenIdTestNonNull:424 case Stage1AirInstIdTestNonNull:
425 return "GenTestNonNull";425 return "GenTestNonNull";
426 case IrInstGenIdOptionalUnwrapPtr:426 case Stage1AirInstIdOptionalUnwrapPtr:
427 return "GenOptionalUnwrapPtr";427 return "GenOptionalUnwrapPtr";
428 case IrInstGenIdOptionalWrap:428 case Stage1AirInstIdOptionalWrap:
429 return "GenOptionalWrap";429 return "GenOptionalWrap";
430 case IrInstGenIdUnionTag:430 case Stage1AirInstIdUnionTag:
431 return "GenUnionTag";431 return "GenUnionTag";
432 case IrInstGenIdClz:432 case Stage1AirInstIdClz:
433 return "GenClz";433 return "GenClz";
434 case IrInstGenIdCtz:434 case Stage1AirInstIdCtz:
435 return "GenCtz";435 return "GenCtz";
436 case IrInstGenIdPopCount:436 case Stage1AirInstIdPopCount:
437 return "GenPopCount";437 return "GenPopCount";
438 case IrInstGenIdBswap:438 case Stage1AirInstIdBswap:
439 return "GenBswap";439 return "GenBswap";
440 case IrInstGenIdBitReverse:440 case Stage1AirInstIdBitReverse:
441 return "GenBitReverse";441 return "GenBitReverse";
442 case IrInstGenIdRef:442 case Stage1AirInstIdRef:
443 return "GenRef";443 return "GenRef";
444 case IrInstGenIdErrName:444 case Stage1AirInstIdErrName:
445 return "GenErrName";445 return "GenErrName";
446 case IrInstGenIdCmpxchg:446 case Stage1AirInstIdCmpxchg:
447 return "GenCmpxchg";447 return "GenCmpxchg";
448 case IrInstGenIdFence:448 case Stage1AirInstIdFence:
449 return "GenFence";449 return "GenFence";
450 case IrInstGenIdReduce:450 case Stage1AirInstIdReduce:
451 return "GenReduce";451 return "GenReduce";
452 case IrInstGenIdTruncate:452 case Stage1AirInstIdTruncate:
453 return "GenTruncate";453 return "GenTruncate";
454 case IrInstGenIdBoolNot:454 case Stage1AirInstIdBoolNot:
455 return "GenBoolNot";455 return "GenBoolNot";
456 case IrInstGenIdMemset:456 case Stage1AirInstIdMemset:
457 return "GenMemset";457 return "GenMemset";
458 case IrInstGenIdMemcpy:458 case Stage1AirInstIdMemcpy:
459 return "GenMemcpy";459 return "GenMemcpy";
460 case IrInstGenIdSlice:460 case Stage1AirInstIdSlice:
461 return "GenSlice";461 return "GenSlice";
462 case IrInstGenIdBreakpoint:462 case Stage1AirInstIdBreakpoint:
463 return "GenBreakpoint";463 return "GenBreakpoint";
464 case IrInstGenIdReturnAddress:464 case Stage1AirInstIdReturnAddress:
465 return "GenReturnAddress";465 return "GenReturnAddress";
466 case IrInstGenIdFrameAddress:466 case Stage1AirInstIdFrameAddress:
467 return "GenFrameAddress";467 return "GenFrameAddress";
468 case IrInstGenIdFrameHandle:468 case Stage1AirInstIdFrameHandle:
469 return "GenFrameHandle";469 return "GenFrameHandle";
470 case IrInstGenIdFrameSize:470 case Stage1AirInstIdFrameSize:
471 return "GenFrameSize";471 return "GenFrameSize";
472 case IrInstGenIdOverflowOp:472 case Stage1AirInstIdOverflowOp:
473 return "GenOverflowOp";473 return "GenOverflowOp";
474 case IrInstGenIdTestErr:474 case Stage1AirInstIdTestErr:
475 return "GenTestErr";475 return "GenTestErr";
476 case IrInstGenIdMulAdd:476 case Stage1AirInstIdMulAdd:
477 return "GenMulAdd";477 return "GenMulAdd";
478 case IrInstGenIdFloatOp:478 case Stage1AirInstIdFloatOp:
479 return "GenFloatOp";479 return "GenFloatOp";
480 case IrInstGenIdUnwrapErrCode:480 case Stage1AirInstIdUnwrapErrCode:
481 return "GenUnwrapErrCode";481 return "GenUnwrapErrCode";
482 case IrInstGenIdUnwrapErrPayload:482 case Stage1AirInstIdUnwrapErrPayload:
483 return "GenUnwrapErrPayload";483 return "GenUnwrapErrPayload";
484 case IrInstGenIdErrWrapCode:484 case Stage1AirInstIdErrWrapCode:
485 return "GenErrWrapCode";485 return "GenErrWrapCode";
486 case IrInstGenIdErrWrapPayload:486 case Stage1AirInstIdErrWrapPayload:
487 return "GenErrWrapPayload";487 return "GenErrWrapPayload";
488 case IrInstGenIdPtrCast:488 case Stage1AirInstIdPtrCast:
489 return "GenPtrCast";489 return "GenPtrCast";
490 case IrInstGenIdBitCast:490 case Stage1AirInstIdBitCast:
491 return "GenBitCast";491 return "GenBitCast";
492 case IrInstGenIdWidenOrShorten:492 case Stage1AirInstIdWidenOrShorten:
493 return "GenWidenOrShorten";493 return "GenWidenOrShorten";
494 case IrInstGenIdIntToPtr:494 case Stage1AirInstIdIntToPtr:
495 return "GenIntToPtr";495 return "GenIntToPtr";
496 case IrInstGenIdPtrToInt:496 case Stage1AirInstIdPtrToInt:
497 return "GenPtrToInt";497 return "GenPtrToInt";
498 case IrInstGenIdIntToEnum:498 case Stage1AirInstIdIntToEnum:
499 return "GenIntToEnum";499 return "GenIntToEnum";
500 case IrInstGenIdIntToErr:500 case Stage1AirInstIdIntToErr:
501 return "GenIntToErr";501 return "GenIntToErr";
502 case IrInstGenIdErrToInt:502 case Stage1AirInstIdErrToInt:
503 return "GenErrToInt";503 return "GenErrToInt";
504 case IrInstGenIdPanic:504 case Stage1AirInstIdPanic:
505 return "GenPanic";505 return "GenPanic";
506 case IrInstGenIdTagName:506 case Stage1AirInstIdTagName:
507 return "GenTagName";507 return "GenTagName";
508 case IrInstGenIdFieldParentPtr:508 case Stage1AirInstIdFieldParentPtr:
509 return "GenFieldParentPtr";509 return "GenFieldParentPtr";
510 case IrInstGenIdAlignCast:510 case Stage1AirInstIdAlignCast:
511 return "GenAlignCast";511 return "GenAlignCast";
512 case IrInstGenIdErrorReturnTrace:512 case Stage1AirInstIdErrorReturnTrace:
513 return "GenErrorReturnTrace";513 return "GenErrorReturnTrace";
514 case IrInstGenIdAtomicRmw:514 case Stage1AirInstIdAtomicRmw:
515 return "GenAtomicRmw";515 return "GenAtomicRmw";
516 case IrInstGenIdAtomicLoad:516 case Stage1AirInstIdAtomicLoad:
517 return "GenAtomicLoad";517 return "GenAtomicLoad";
518 case IrInstGenIdAtomicStore:518 case Stage1AirInstIdAtomicStore:
519 return "GenAtomicStore";519 return "GenAtomicStore";
520 case IrInstGenIdSaveErrRetAddr:520 case Stage1AirInstIdSaveErrRetAddr:
521 return "GenSaveErrRetAddr";521 return "GenSaveErrRetAddr";
522 case IrInstGenIdVectorToArray:522 case Stage1AirInstIdVectorToArray:
523 return "GenVectorToArray";523 return "GenVectorToArray";
524 case IrInstGenIdArrayToVector:524 case Stage1AirInstIdArrayToVector:
525 return "GenArrayToVector";525 return "GenArrayToVector";
526 case IrInstGenIdAssertZero:526 case Stage1AirInstIdAssertZero:
527 return "GenAssertZero";527 return "GenAssertZero";
528 case IrInstGenIdAssertNonNull:528 case Stage1AirInstIdAssertNonNull:
529 return "GenAssertNonNull";529 return "GenAssertNonNull";
530 case IrInstGenIdAlloca:530 case Stage1AirInstIdAlloca:
531 return "GenAlloca";531 return "GenAlloca";
532 case IrInstGenIdPtrOfArrayToSlice:532 case Stage1AirInstIdPtrOfArrayToSlice:
533 return "GenPtrOfArrayToSlice";533 return "GenPtrOfArrayToSlice";
534 case IrInstGenIdSuspendBegin:534 case Stage1AirInstIdSuspendBegin:
535 return "GenSuspendBegin";535 return "GenSuspendBegin";
536 case IrInstGenIdSuspendFinish:536 case Stage1AirInstIdSuspendFinish:
537 return "GenSuspendFinish";537 return "GenSuspendFinish";
538 case IrInstGenIdAwait:538 case Stage1AirInstIdAwait:
539 return "GenAwait";539 return "GenAwait";
540 case IrInstGenIdResume:540 case Stage1AirInstIdResume:
541 return "GenResume";541 return "GenResume";
542 case IrInstGenIdSpillBegin:542 case Stage1AirInstIdSpillBegin:
543 return "GenSpillBegin";543 return "GenSpillBegin";
544 case IrInstGenIdSpillEnd:544 case Stage1AirInstIdSpillEnd:
545 return "GenSpillEnd";545 return "GenSpillEnd";
546 case IrInstGenIdVectorExtractElem:546 case Stage1AirInstIdVectorExtractElem:
547 return "GenVectorExtractElem";547 return "GenVectorExtractElem";
548 case IrInstGenIdBinaryNot:548 case Stage1AirInstIdBinaryNot:
549 return "GenBinaryNot";549 return "GenBinaryNot";
550 case IrInstGenIdNegation:550 case Stage1AirInstIdNegation:
551 return "GenNegation";551 return "GenNegation";
552 case IrInstGenIdWasmMemorySize:552 case Stage1AirInstIdWasmMemorySize:
553 return "GenWasmMemorySize";553 return "GenWasmMemorySize";
554 case IrInstGenIdWasmMemoryGrow:554 case Stage1AirInstIdWasmMemoryGrow:
555 return "GenWasmMemoryGrow";555 return "GenWasmMemoryGrow";
556 case IrInstGenIdExtern:556 case Stage1AirInstIdExtern:
557 return "GenExtrern";557 return "GenExtrern";
558 }558 }
559 zig_unreachable();559 zig_unreachable();
...@@ -571,12 +571,12 @@ static void ir_print_indent_gen(IrPrintGen *irp) {...@@ -571,12 +571,12 @@ static void ir_print_indent_gen(IrPrintGen *irp) {
571 }571 }
572}572}
573573
574static void ir_print_prefix_src(IrPrintSrc *irp, IrInstSrc *instruction, bool trailing) {574static void ir_print_prefix_src(IrPrintSrc *irp, Stage1ZirInst *instruction, bool trailing) {
575 ir_print_indent_src(irp);575 ir_print_indent_src(irp);
576 const char mark = trailing ? ':' : '#';576 const char mark = trailing ? ':' : '#';
577 const char *type_name;577 const char *type_name;
578 if (instruction->id == IrInstSrcIdConst) {578 if (instruction->id == Stage1ZirInstIdConst) {
579 type_name = buf_ptr(&reinterpret_cast<IrInstSrcConst *>(instruction)->value->type->name);579 type_name = buf_ptr(&reinterpret_cast<Stage1ZirInstConst *>(instruction)->value->type->name);
580 } else {580 } else {
581 type_name = "(unknown)";581 type_name = "(unknown)";
582 }582 }
...@@ -586,7 +586,7 @@ static void ir_print_prefix_src(IrPrintSrc *irp, IrInstSrc *instruction, bool tr...@@ -586,7 +586,7 @@ static void ir_print_prefix_src(IrPrintSrc *irp, IrInstSrc *instruction, bool tr
586 ir_inst_src_type_str(instruction->id), type_name, ref_count);586 ir_inst_src_type_str(instruction->id), type_name, ref_count);
587}587}
588588
589static void ir_print_prefix_gen(IrPrintGen *irp, IrInstGen *instruction, bool trailing) {589static void ir_print_prefix_gen(IrPrintGen *irp, Stage1AirInst *instruction, bool trailing) {
590 ir_print_indent_gen(irp);590 ir_print_indent_gen(irp);
591 const char mark = trailing ? ':' : '#';591 const char mark = trailing ? ':' : '#';
592 const char *type_name = instruction->value->type ? buf_ptr(&instruction->value->type->name) : "(unknown)";592 const char *type_name = instruction->value->type ? buf_ptr(&instruction->value->type->name) : "(unknown)";
...@@ -596,11 +596,11 @@ static void ir_print_prefix_gen(IrPrintGen *irp, IrInstGen *instruction, bool tr...@@ -596,11 +596,11 @@ static void ir_print_prefix_gen(IrPrintGen *irp, IrInstGen *instruction, bool tr
596 ir_inst_gen_type_str(instruction->id), type_name, ref_count);596 ir_inst_gen_type_str(instruction->id), type_name, ref_count);
597}597}
598598
599static void ir_print_var_src(IrPrintSrc *irp, IrInstSrc *inst) {599static void ir_print_var_src(IrPrintSrc *irp, Stage1ZirInst *inst) {
600 fprintf(irp->f, "#%" PRIu32 "", inst->debug_id);600 fprintf(irp->f, "#%" PRIu32 "", inst->debug_id);
601}601}
602602
603static void ir_print_var_gen(IrPrintGen *irp, IrInstGen *inst) {603static void ir_print_var_gen(IrPrintGen *irp, Stage1AirInst *inst) {
604 fprintf(irp->f, "#%" PRIu32 "", inst->debug_id);604 fprintf(irp->f, "#%" PRIu32 "", inst->debug_id);
605 if (irp->printed.maybe_get(inst) == nullptr) {605 if (irp->printed.maybe_get(inst) == nullptr) {
606 irp->printed.put(inst, 0);606 irp->printed.put(inst, 0);
...@@ -608,7 +608,7 @@ static void ir_print_var_gen(IrPrintGen *irp, IrInstGen *inst) {...@@ -608,7 +608,7 @@ static void ir_print_var_gen(IrPrintGen *irp, IrInstGen *inst) {
608 }608 }
609}609}
610610
611static void ir_print_other_inst_src(IrPrintSrc *irp, IrInstSrc *inst) {611static void ir_print_other_inst_src(IrPrintSrc *irp, Stage1ZirInst *inst) {
612 if (inst == nullptr) {612 if (inst == nullptr) {
613 fprintf(irp->f, "(null)");613 fprintf(irp->f, "(null)");
614 return;614 return;
...@@ -623,7 +623,7 @@ static void ir_print_const_value(CodeGen *g, FILE *f, ZigValue *const_val) {...@@ -623,7 +623,7 @@ static void ir_print_const_value(CodeGen *g, FILE *f, ZigValue *const_val) {
623 fprintf(f, "%s", buf_ptr(&buf));623 fprintf(f, "%s", buf_ptr(&buf));
624}624}
625625
626static void ir_print_other_inst_gen(IrPrintGen *irp, IrInstGen *inst) {626static void ir_print_other_inst_gen(IrPrintGen *irp, Stage1AirInst *inst) {
627 if (inst == nullptr) {627 if (inst == nullptr) {
628 fprintf(irp->f, "(null)");628 fprintf(irp->f, "(null)");
629 } else {629 } else {
...@@ -639,7 +639,7 @@ static void ir_print_other_block(IrPrintSrc *irp, Stage1ZirBasicBlock *bb) {...@@ -639,7 +639,7 @@ static void ir_print_other_block(IrPrintSrc *irp, Stage1ZirBasicBlock *bb) {
639 }639 }
640}640}
641641
642static void ir_print_other_block_gen(IrPrintGen *irp, IrBasicBlockGen *bb) {642static void ir_print_other_block_gen(IrPrintGen *irp, Stage1AirBasicBlock *bb) {
643 if (bb == nullptr) {643 if (bb == nullptr) {
644 fprintf(irp->f, "(null block)");644 fprintf(irp->f, "(null block)");
645 } else {645 } else {
...@@ -647,21 +647,21 @@ static void ir_print_other_block_gen(IrPrintGen *irp, IrBasicBlockGen *bb) {...@@ -647,21 +647,21 @@ static void ir_print_other_block_gen(IrPrintGen *irp, IrBasicBlockGen *bb) {
647 }647 }
648}648}
649649
650static void ir_print_return_src(IrPrintSrc *irp, IrInstSrcReturn *inst) {650static void ir_print_return_src(IrPrintSrc *irp, Stage1ZirInstReturn *inst) {
651 fprintf(irp->f, "return ");651 fprintf(irp->f, "return ");
652 ir_print_other_inst_src(irp, inst->operand);652 ir_print_other_inst_src(irp, inst->operand);
653}653}
654654
655static void ir_print_return_gen(IrPrintGen *irp, IrInstGenReturn *inst) {655static void ir_print_return_gen(IrPrintGen *irp, Stage1AirInstReturn *inst) {
656 fprintf(irp->f, "return ");656 fprintf(irp->f, "return ");
657 ir_print_other_inst_gen(irp, inst->operand);657 ir_print_other_inst_gen(irp, inst->operand);
658}658}
659659
660static void ir_print_const(IrPrintSrc *irp, IrInstSrcConst *const_instruction) {660static void ir_print_const(IrPrintSrc *irp, Stage1ZirInstConst *const_instruction) {
661 ir_print_const_value(irp->codegen, irp->f, const_instruction->value);661 ir_print_const_value(irp->codegen, irp->f, const_instruction->value);
662}662}
663663
664static void ir_print_const(IrPrintGen *irp, IrInstGenConst *const_instruction) {664static void ir_print_const(IrPrintGen *irp, Stage1AirInstConst *const_instruction) {
665 ir_print_const_value(irp->codegen, irp->f, const_instruction->base.value);665 ir_print_const_value(irp->codegen, irp->f, const_instruction->base.value);
666}666}
667667
...@@ -751,12 +751,12 @@ static const char *ir_un_op_id_str(IrUnOp op_id) {...@@ -751,12 +751,12 @@ static const char *ir_un_op_id_str(IrUnOp op_id) {
751 zig_unreachable();751 zig_unreachable();
752}752}
753753
754static void ir_print_un_op(IrPrintSrc *irp, IrInstSrcUnOp *inst) {754static void ir_print_un_op(IrPrintSrc *irp, Stage1ZirInstUnOp *inst) {
755 fprintf(irp->f, "%s ", ir_un_op_id_str(inst->op_id));755 fprintf(irp->f, "%s ", ir_un_op_id_str(inst->op_id));
756 ir_print_other_inst_src(irp, inst->value);756 ir_print_other_inst_src(irp, inst->value);
757}757}
758758
759static void ir_print_bin_op(IrPrintSrc *irp, IrInstSrcBinOp *bin_op_instruction) {759static void ir_print_bin_op(IrPrintSrc *irp, Stage1ZirInstBinOp *bin_op_instruction) {
760 ir_print_other_inst_src(irp, bin_op_instruction->op1);760 ir_print_other_inst_src(irp, bin_op_instruction->op1);
761 fprintf(irp->f, " %s ", ir_bin_op_id_str(bin_op_instruction->op_id));761 fprintf(irp->f, " %s ", ir_bin_op_id_str(bin_op_instruction->op_id));
762 ir_print_other_inst_src(irp, bin_op_instruction->op2);762 ir_print_other_inst_src(irp, bin_op_instruction->op2);
...@@ -765,7 +765,7 @@ static void ir_print_bin_op(IrPrintSrc *irp, IrInstSrcBinOp *bin_op_instruction)...@@ -765,7 +765,7 @@ static void ir_print_bin_op(IrPrintSrc *irp, IrInstSrcBinOp *bin_op_instruction)
765 }765 }
766}766}
767767
768static void ir_print_bin_op(IrPrintGen *irp, IrInstGenBinOp *bin_op_instruction) {768static void ir_print_bin_op(IrPrintGen *irp, Stage1AirInstBinOp *bin_op_instruction) {
769 ir_print_other_inst_gen(irp, bin_op_instruction->op1);769 ir_print_other_inst_gen(irp, bin_op_instruction->op1);
770 fprintf(irp->f, " %s ", ir_bin_op_id_str(bin_op_instruction->op_id));770 fprintf(irp->f, " %s ", ir_bin_op_id_str(bin_op_instruction->op_id));
771 ir_print_other_inst_gen(irp, bin_op_instruction->op2);771 ir_print_other_inst_gen(irp, bin_op_instruction->op2);
...@@ -774,7 +774,7 @@ static void ir_print_bin_op(IrPrintGen *irp, IrInstGenBinOp *bin_op_instruction)...@@ -774,7 +774,7 @@ static void ir_print_bin_op(IrPrintGen *irp, IrInstGenBinOp *bin_op_instruction)
774 }774 }
775}775}
776776
777static void ir_print_merge_err_sets(IrPrintSrc *irp, IrInstSrcMergeErrSets *instruction) {777static void ir_print_merge_err_sets(IrPrintSrc *irp, Stage1ZirInstMergeErrSets *instruction) {
778 ir_print_other_inst_src(irp, instruction->op1);778 ir_print_other_inst_src(irp, instruction->op1);
779 fprintf(irp->f, " || ");779 fprintf(irp->f, " || ");
780 ir_print_other_inst_src(irp, instruction->op2);780 ir_print_other_inst_src(irp, instruction->op2);
...@@ -783,7 +783,7 @@ static void ir_print_merge_err_sets(IrPrintSrc *irp, IrInstSrcMergeErrSets *inst...@@ -783,7 +783,7 @@ static void ir_print_merge_err_sets(IrPrintSrc *irp, IrInstSrcMergeErrSets *inst
783 }783 }
784}784}
785785
786static void ir_print_decl_var_src(IrPrintSrc *irp, IrInstSrcDeclVar *decl_var_instruction) {786static void ir_print_decl_var_src(IrPrintSrc *irp, Stage1ZirInstDeclVar *decl_var_instruction) {
787 const char *var_or_const = decl_var_instruction->var->gen_is_const ? "const" : "var";787 const char *var_or_const = decl_var_instruction->var->gen_is_const ? "const" : "var";
788 const char *name = decl_var_instruction->var->name;788 const char *name = decl_var_instruction->var->name;
789 if (decl_var_instruction->var_type) {789 if (decl_var_instruction->var_type) {
...@@ -820,7 +820,7 @@ static const char *cast_op_str(CastOp op) {...@@ -820,7 +820,7 @@ static const char *cast_op_str(CastOp op) {
820 zig_unreachable();820 zig_unreachable();
821}821}
822822
823static void ir_print_cast(IrPrintGen *irp, IrInstGenCast *cast_instruction) {823static void ir_print_cast(IrPrintGen *irp, Stage1AirInstCast *cast_instruction) {
824 fprintf(irp->f, "%s cast ", cast_op_str(cast_instruction->cast_op));824 fprintf(irp->f, "%s cast ", cast_op_str(cast_instruction->cast_op));
825 ir_print_other_inst_gen(irp, cast_instruction->value);825 ir_print_other_inst_gen(irp, cast_instruction->value);
826}826}
...@@ -882,7 +882,7 @@ static void ir_print_result_loc(IrPrintSrc *irp, ResultLoc *result_loc) {...@@ -882,7 +882,7 @@ static void ir_print_result_loc(IrPrintSrc *irp, ResultLoc *result_loc) {
882 zig_unreachable();882 zig_unreachable();
883}883}
884884
885static void ir_print_call_extra(IrPrintSrc *irp, IrInstSrcCallExtra *instruction) {885static void ir_print_call_extra(IrPrintSrc *irp, Stage1ZirInstCallExtra *instruction) {
886 fprintf(irp->f, "opts=");886 fprintf(irp->f, "opts=");
887 ir_print_other_inst_src(irp, instruction->options);887 ir_print_other_inst_src(irp, instruction->options);
888 fprintf(irp->f, ", fn=");888 fprintf(irp->f, ", fn=");
...@@ -893,7 +893,7 @@ static void ir_print_call_extra(IrPrintSrc *irp, IrInstSrcCallExtra *instruction...@@ -893,7 +893,7 @@ static void ir_print_call_extra(IrPrintSrc *irp, IrInstSrcCallExtra *instruction
893 ir_print_result_loc(irp, instruction->result_loc);893 ir_print_result_loc(irp, instruction->result_loc);
894}894}
895895
896static void ir_print_async_call_extra(IrPrintSrc *irp, IrInstSrcAsyncCallExtra *instruction) {896static void ir_print_async_call_extra(IrPrintSrc *irp, Stage1ZirInstAsyncCallExtra *instruction) {
897 fprintf(irp->f, "modifier=");897 fprintf(irp->f, "modifier=");
898 ir_print_call_modifier(irp->f, instruction->modifier);898 ir_print_call_modifier(irp->f, instruction->modifier);
899 fprintf(irp->f, ", fn=");899 fprintf(irp->f, ", fn=");
...@@ -910,14 +910,14 @@ static void ir_print_async_call_extra(IrPrintSrc *irp, IrInstSrcAsyncCallExtra *...@@ -910,14 +910,14 @@ static void ir_print_async_call_extra(IrPrintSrc *irp, IrInstSrcAsyncCallExtra *
910 ir_print_result_loc(irp, instruction->result_loc);910 ir_print_result_loc(irp, instruction->result_loc);
911}911}
912912
913static void ir_print_call_args(IrPrintSrc *irp, IrInstSrcCallArgs *instruction) {913static void ir_print_call_args(IrPrintSrc *irp, Stage1ZirInstCallArgs *instruction) {
914 fprintf(irp->f, "opts=");914 fprintf(irp->f, "opts=");
915 ir_print_other_inst_src(irp, instruction->options);915 ir_print_other_inst_src(irp, instruction->options);
916 fprintf(irp->f, ", fn=");916 fprintf(irp->f, ", fn=");
917 ir_print_other_inst_src(irp, instruction->fn_ref);917 ir_print_other_inst_src(irp, instruction->fn_ref);
918 fprintf(irp->f, ", args=(");918 fprintf(irp->f, ", args=(");
919 for (size_t i = 0; i < instruction->args_len; i += 1) {919 for (size_t i = 0; i < instruction->args_len; i += 1) {
920 IrInstSrc *arg = instruction->args_ptr[i];920 Stage1ZirInst *arg = instruction->args_ptr[i];
921 if (i != 0)921 if (i != 0)
922 fprintf(irp->f, ", ");922 fprintf(irp->f, ", ");
923 ir_print_other_inst_src(irp, arg);923 ir_print_other_inst_src(irp, arg);
...@@ -926,7 +926,7 @@ static void ir_print_call_args(IrPrintSrc *irp, IrInstSrcCallArgs *instruction)...@@ -926,7 +926,7 @@ static void ir_print_call_args(IrPrintSrc *irp, IrInstSrcCallArgs *instruction)
926 ir_print_result_loc(irp, instruction->result_loc);926 ir_print_result_loc(irp, instruction->result_loc);
927}927}
928928
929static void ir_print_call_src(IrPrintSrc *irp, IrInstSrcCall *call_instruction) {929static void ir_print_call_src(IrPrintSrc *irp, Stage1ZirInstCall *call_instruction) {
930 ir_print_call_modifier(irp->f, call_instruction->modifier);930 ir_print_call_modifier(irp->f, call_instruction->modifier);
931 if (call_instruction->fn_entry) {931 if (call_instruction->fn_entry) {
932 fprintf(irp->f, "%s", buf_ptr(&call_instruction->fn_entry->symbol_name));932 fprintf(irp->f, "%s", buf_ptr(&call_instruction->fn_entry->symbol_name));
...@@ -936,7 +936,7 @@ static void ir_print_call_src(IrPrintSrc *irp, IrInstSrcCall *call_instruction)...@@ -936,7 +936,7 @@ static void ir_print_call_src(IrPrintSrc *irp, IrInstSrcCall *call_instruction)
936 }936 }
937 fprintf(irp->f, "(");937 fprintf(irp->f, "(");
938 for (size_t i = 0; i < call_instruction->arg_count; i += 1) {938 for (size_t i = 0; i < call_instruction->arg_count; i += 1) {
939 IrInstSrc *arg = call_instruction->args[i];939 Stage1ZirInst *arg = call_instruction->args[i];
940 if (i != 0)940 if (i != 0)
941 fprintf(irp->f, ", ");941 fprintf(irp->f, ", ");
942 ir_print_other_inst_src(irp, arg);942 ir_print_other_inst_src(irp, arg);
...@@ -945,7 +945,7 @@ static void ir_print_call_src(IrPrintSrc *irp, IrInstSrcCall *call_instruction)...@@ -945,7 +945,7 @@ static void ir_print_call_src(IrPrintSrc *irp, IrInstSrcCall *call_instruction)
945 ir_print_result_loc(irp, call_instruction->result_loc);945 ir_print_result_loc(irp, call_instruction->result_loc);
946}946}
947947
948static void ir_print_call_gen(IrPrintGen *irp, IrInstGenCall *call_instruction) {948static void ir_print_call_gen(IrPrintGen *irp, Stage1AirInstCall *call_instruction) {
949 ir_print_call_modifier(irp->f, call_instruction->modifier);949 ir_print_call_modifier(irp->f, call_instruction->modifier);
950 if (call_instruction->fn_entry) {950 if (call_instruction->fn_entry) {
951 fprintf(irp->f, "%s", buf_ptr(&call_instruction->fn_entry->symbol_name));951 fprintf(irp->f, "%s", buf_ptr(&call_instruction->fn_entry->symbol_name));
...@@ -955,7 +955,7 @@ static void ir_print_call_gen(IrPrintGen *irp, IrInstGenCall *call_instruction)...@@ -955,7 +955,7 @@ static void ir_print_call_gen(IrPrintGen *irp, IrInstGenCall *call_instruction)
955 }955 }
956 fprintf(irp->f, "(");956 fprintf(irp->f, "(");
957 for (size_t i = 0; i < call_instruction->arg_count; i += 1) {957 for (size_t i = 0; i < call_instruction->arg_count; i += 1) {
958 IrInstGen *arg = call_instruction->args[i];958 Stage1AirInst *arg = call_instruction->args[i];
959 if (i != 0)959 if (i != 0)
960 fprintf(irp->f, ", ");960 fprintf(irp->f, ", ");
961 ir_print_other_inst_gen(irp, arg);961 ir_print_other_inst_gen(irp, arg);
...@@ -964,7 +964,7 @@ static void ir_print_call_gen(IrPrintGen *irp, IrInstGenCall *call_instruction)...@@ -964,7 +964,7 @@ static void ir_print_call_gen(IrPrintGen *irp, IrInstGenCall *call_instruction)
964 ir_print_other_inst_gen(irp, call_instruction->result_loc);964 ir_print_other_inst_gen(irp, call_instruction->result_loc);
965}965}
966966
967static void ir_print_cond_br(IrPrintSrc *irp, IrInstSrcCondBr *inst) {967static void ir_print_cond_br(IrPrintSrc *irp, Stage1ZirInstCondBr *inst) {
968 fprintf(irp->f, "if (");968 fprintf(irp->f, "if (");
969 ir_print_other_inst_src(irp, inst->condition);969 ir_print_other_inst_src(irp, inst->condition);
970 fprintf(irp->f, ") ");970 fprintf(irp->f, ") ");
...@@ -977,7 +977,7 @@ static void ir_print_cond_br(IrPrintSrc *irp, IrInstSrcCondBr *inst) {...@@ -977,7 +977,7 @@ static void ir_print_cond_br(IrPrintSrc *irp, IrInstSrcCondBr *inst) {
977 }977 }
978}978}
979979
980static void ir_print_cond_br(IrPrintGen *irp, IrInstGenCondBr *inst) {980static void ir_print_cond_br(IrPrintGen *irp, Stage1AirInstCondBr *inst) {
981 fprintf(irp->f, "if (");981 fprintf(irp->f, "if (");
982 ir_print_other_inst_gen(irp, inst->condition);982 ir_print_other_inst_gen(irp, inst->condition);
983 fprintf(irp->f, ") ");983 fprintf(irp->f, ") ");
...@@ -986,7 +986,7 @@ static void ir_print_cond_br(IrPrintGen *irp, IrInstGenCondBr *inst) {...@@ -986,7 +986,7 @@ static void ir_print_cond_br(IrPrintGen *irp, IrInstGenCondBr *inst) {
986 ir_print_other_block_gen(irp, inst->else_block);986 ir_print_other_block_gen(irp, inst->else_block);
987}987}
988988
989static void ir_print_br(IrPrintSrc *irp, IrInstSrcBr *br_instruction) {989static void ir_print_br(IrPrintSrc *irp, Stage1ZirInstBr *br_instruction) {
990 fprintf(irp->f, "goto ");990 fprintf(irp->f, "goto ");
991 ir_print_other_block(irp, br_instruction->dest_block);991 ir_print_other_block(irp, br_instruction->dest_block);
992 if (br_instruction->is_comptime != nullptr) {992 if (br_instruction->is_comptime != nullptr) {
...@@ -995,17 +995,17 @@ static void ir_print_br(IrPrintSrc *irp, IrInstSrcBr *br_instruction) {...@@ -995,17 +995,17 @@ static void ir_print_br(IrPrintSrc *irp, IrInstSrcBr *br_instruction) {
995 }995 }
996}996}
997997
998static void ir_print_br(IrPrintGen *irp, IrInstGenBr *inst) {998static void ir_print_br(IrPrintGen *irp, Stage1AirInstBr *inst) {
999 fprintf(irp->f, "goto ");999 fprintf(irp->f, "goto ");
1000 ir_print_other_block_gen(irp, inst->dest_block);1000 ir_print_other_block_gen(irp, inst->dest_block);
1001}1001}
10021002
1003static void ir_print_phi(IrPrintSrc *irp, IrInstSrcPhi *phi_instruction) {1003static void ir_print_phi(IrPrintSrc *irp, Stage1ZirInstPhi *phi_instruction) {
1004 assert(phi_instruction->incoming_count != 0);1004 assert(phi_instruction->incoming_count != 0);
1005 assert(phi_instruction->incoming_count != SIZE_MAX);1005 assert(phi_instruction->incoming_count != SIZE_MAX);
1006 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {1006 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
1007 Stage1ZirBasicBlock *incoming_block = phi_instruction->incoming_blocks[i];1007 Stage1ZirBasicBlock *incoming_block = phi_instruction->incoming_blocks[i];
1008 IrInstSrc *incoming_value = phi_instruction->incoming_values[i];1008 Stage1ZirInst *incoming_value = phi_instruction->incoming_values[i];
1009 if (i != 0)1009 if (i != 0)
1010 fprintf(irp->f, " ");1010 fprintf(irp->f, " ");
1011 ir_print_other_block(irp, incoming_block);1011 ir_print_other_block(irp, incoming_block);
...@@ -1014,12 +1014,12 @@ static void ir_print_phi(IrPrintSrc *irp, IrInstSrcPhi *phi_instruction) {...@@ -1014,12 +1014,12 @@ static void ir_print_phi(IrPrintSrc *irp, IrInstSrcPhi *phi_instruction) {
1014 }1014 }
1015}1015}
10161016
1017static void ir_print_phi(IrPrintGen *irp, IrInstGenPhi *phi_instruction) {1017static void ir_print_phi(IrPrintGen *irp, Stage1AirInstPhi *phi_instruction) {
1018 assert(phi_instruction->incoming_count != 0);1018 assert(phi_instruction->incoming_count != 0);
1019 assert(phi_instruction->incoming_count != SIZE_MAX);1019 assert(phi_instruction->incoming_count != SIZE_MAX);
1020 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {1020 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
1021 IrBasicBlockGen *incoming_block = phi_instruction->incoming_blocks[i];1021 Stage1AirBasicBlock *incoming_block = phi_instruction->incoming_blocks[i];
1022 IrInstGen *incoming_value = phi_instruction->incoming_values[i];1022 Stage1AirInst *incoming_value = phi_instruction->incoming_values[i];
1023 if (i != 0)1023 if (i != 0)
1024 fprintf(irp->f, " ");1024 fprintf(irp->f, " ");
1025 ir_print_other_block_gen(irp, incoming_block);1025 ir_print_other_block_gen(irp, incoming_block);
...@@ -1028,13 +1028,13 @@ static void ir_print_phi(IrPrintGen *irp, IrInstGenPhi *phi_instruction) {...@@ -1028,13 +1028,13 @@ static void ir_print_phi(IrPrintGen *irp, IrInstGenPhi *phi_instruction) {
1028 }1028 }
1029}1029}
10301030
1031static void ir_print_container_init_list(IrPrintSrc *irp, IrInstSrcContainerInitList *instruction) {1031static void ir_print_container_init_list(IrPrintSrc *irp, Stage1ZirInstContainerInitList *instruction) {
1032 fprintf(irp->f, "{");1032 fprintf(irp->f, "{");
1033 if (instruction->item_count > 50) {1033 if (instruction->item_count > 50) {
1034 fprintf(irp->f, "...(%" ZIG_PRI_usize " items)...", instruction->item_count);1034 fprintf(irp->f, "...(%" ZIG_PRI_usize " items)...", instruction->item_count);
1035 } else {1035 } else {
1036 for (size_t i = 0; i < instruction->item_count; i += 1) {1036 for (size_t i = 0; i < instruction->item_count; i += 1) {
1037 IrInstSrc *result_loc = instruction->elem_result_loc_list[i];1037 Stage1ZirInst *result_loc = instruction->elem_result_loc_list[i];
1038 if (i != 0)1038 if (i != 0)
1039 fprintf(irp->f, ", ");1039 fprintf(irp->f, ", ");
1040 ir_print_other_inst_src(irp, result_loc);1040 ir_print_other_inst_src(irp, result_loc);
...@@ -1044,10 +1044,10 @@ static void ir_print_container_init_list(IrPrintSrc *irp, IrInstSrcContainerInit...@@ -1044,10 +1044,10 @@ static void ir_print_container_init_list(IrPrintSrc *irp, IrInstSrcContainerInit
1044 ir_print_other_inst_src(irp, instruction->result_loc);1044 ir_print_other_inst_src(irp, instruction->result_loc);
1045}1045}
10461046
1047static void ir_print_container_init_fields(IrPrintSrc *irp, IrInstSrcContainerInitFields *instruction) {1047static void ir_print_container_init_fields(IrPrintSrc *irp, Stage1ZirInstContainerInitFields *instruction) {
1048 fprintf(irp->f, "{");1048 fprintf(irp->f, "{");
1049 for (size_t i = 0; i < instruction->field_count; i += 1) {1049 for (size_t i = 0; i < instruction->field_count; i += 1) {
1050 IrInstSrcContainerInitFieldsField *field = &instruction->fields[i];1050 Stage1ZirInstContainerInitFieldsField *field = &instruction->fields[i];
1051 const char *comma = (i == 0) ? "" : ", ";1051 const char *comma = (i == 0) ? "" : ", ";
1052 fprintf(irp->f, "%s.%s = ", comma, buf_ptr(field->name));1052 fprintf(irp->f, "%s.%s = ", comma, buf_ptr(field->name));
1053 ir_print_other_inst_src(irp, field->result_loc);1053 ir_print_other_inst_src(irp, field->result_loc);
...@@ -1056,15 +1056,15 @@ static void ir_print_container_init_fields(IrPrintSrc *irp, IrInstSrcContainerIn...@@ -1056,15 +1056,15 @@ static void ir_print_container_init_fields(IrPrintSrc *irp, IrInstSrcContainerIn
1056 ir_print_other_inst_src(irp, instruction->result_loc);1056 ir_print_other_inst_src(irp, instruction->result_loc);
1057}1057}
10581058
1059static void ir_print_unreachable(IrPrintSrc *irp, IrInstSrcUnreachable *instruction) {1059static void ir_print_unreachable(IrPrintSrc *irp, Stage1ZirInstUnreachable *instruction) {
1060 fprintf(irp->f, "unreachable");1060 fprintf(irp->f, "unreachable");
1061}1061}
10621062
1063static void ir_print_unreachable(IrPrintGen *irp, IrInstGenUnreachable *instruction) {1063static void ir_print_unreachable(IrPrintGen *irp, Stage1AirInstUnreachable *instruction) {
1064 fprintf(irp->f, "unreachable");1064 fprintf(irp->f, "unreachable");
1065}1065}
10661066
1067static void ir_print_elem_ptr(IrPrintSrc *irp, IrInstSrcElemPtr *instruction) {1067static void ir_print_elem_ptr(IrPrintSrc *irp, Stage1ZirInstElemPtr *instruction) {
1068 fprintf(irp->f, "&");1068 fprintf(irp->f, "&");
1069 ir_print_other_inst_src(irp, instruction->array_ptr);1069 ir_print_other_inst_src(irp, instruction->array_ptr);
1070 fprintf(irp->f, "[");1070 fprintf(irp->f, "[");
...@@ -1075,7 +1075,7 @@ static void ir_print_elem_ptr(IrPrintSrc *irp, IrInstSrcElemPtr *instruction) {...@@ -1075,7 +1075,7 @@ static void ir_print_elem_ptr(IrPrintSrc *irp, IrInstSrcElemPtr *instruction) {
1075 }1075 }
1076}1076}
10771077
1078static void ir_print_elem_ptr(IrPrintGen *irp, IrInstGenElemPtr *instruction) {1078static void ir_print_elem_ptr(IrPrintGen *irp, Stage1AirInstElemPtr *instruction) {
1079 fprintf(irp->f, "&");1079 fprintf(irp->f, "&");
1080 ir_print_other_inst_gen(irp, instruction->array_ptr);1080 ir_print_other_inst_gen(irp, instruction->array_ptr);
1081 fprintf(irp->f, "[");1081 fprintf(irp->f, "[");
...@@ -1086,45 +1086,45 @@ static void ir_print_elem_ptr(IrPrintGen *irp, IrInstGenElemPtr *instruction) {...@@ -1086,45 +1086,45 @@ static void ir_print_elem_ptr(IrPrintGen *irp, IrInstGenElemPtr *instruction) {
1086 }1086 }
1087}1087}
10881088
1089static void ir_print_var_ptr(IrPrintSrc *irp, IrInstSrcVarPtr *instruction) {1089static void ir_print_var_ptr(IrPrintSrc *irp, Stage1ZirInstVarPtr *instruction) {
1090 fprintf(irp->f, "&%s", instruction->var->name);1090 fprintf(irp->f, "&%s", instruction->var->name);
1091}1091}
10921092
1093static void ir_print_var_ptr(IrPrintGen *irp, IrInstGenVarPtr *instruction) {1093static void ir_print_var_ptr(IrPrintGen *irp, Stage1AirInstVarPtr *instruction) {
1094 fprintf(irp->f, "&%s", instruction->var->name);1094 fprintf(irp->f, "&%s", instruction->var->name);
1095}1095}
10961096
1097static void ir_print_return_ptr(IrPrintGen *irp, IrInstGenReturnPtr *instruction) {1097static void ir_print_return_ptr(IrPrintGen *irp, Stage1AirInstReturnPtr *instruction) {
1098 fprintf(irp->f, "@ReturnPtr");1098 fprintf(irp->f, "@ReturnPtr");
1099}1099}
11001100
1101static void ir_print_load_ptr(IrPrintSrc *irp, IrInstSrcLoadPtr *instruction) {1101static void ir_print_load_ptr(IrPrintSrc *irp, Stage1ZirInstLoadPtr *instruction) {
1102 ir_print_other_inst_src(irp, instruction->ptr);1102 ir_print_other_inst_src(irp, instruction->ptr);
1103 fprintf(irp->f, ".*");1103 fprintf(irp->f, ".*");
1104}1104}
11051105
1106static void ir_print_load_ptr_gen(IrPrintGen *irp, IrInstGenLoadPtr *instruction) {1106static void ir_print_load_ptr_gen(IrPrintGen *irp, Stage1AirInstLoadPtr *instruction) {
1107 fprintf(irp->f, "loadptr(");1107 fprintf(irp->f, "loadptr(");
1108 ir_print_other_inst_gen(irp, instruction->ptr);1108 ir_print_other_inst_gen(irp, instruction->ptr);
1109 fprintf(irp->f, ")result=");1109 fprintf(irp->f, ")result=");
1110 ir_print_other_inst_gen(irp, instruction->result_loc);1110 ir_print_other_inst_gen(irp, instruction->result_loc);
1111}1111}
11121112
1113static void ir_print_store_ptr(IrPrintSrc *irp, IrInstSrcStorePtr *instruction) {1113static void ir_print_store_ptr(IrPrintSrc *irp, Stage1ZirInstStorePtr *instruction) {
1114 fprintf(irp->f, "*");1114 fprintf(irp->f, "*");
1115 ir_print_var_src(irp, instruction->ptr);1115 ir_print_var_src(irp, instruction->ptr);
1116 fprintf(irp->f, " = ");1116 fprintf(irp->f, " = ");
1117 ir_print_other_inst_src(irp, instruction->value);1117 ir_print_other_inst_src(irp, instruction->value);
1118}1118}
11191119
1120static void ir_print_store_ptr(IrPrintGen *irp, IrInstGenStorePtr *instruction) {1120static void ir_print_store_ptr(IrPrintGen *irp, Stage1AirInstStorePtr *instruction) {
1121 fprintf(irp->f, "*");1121 fprintf(irp->f, "*");
1122 ir_print_var_gen(irp, instruction->ptr);1122 ir_print_var_gen(irp, instruction->ptr);
1123 fprintf(irp->f, " = ");1123 fprintf(irp->f, " = ");
1124 ir_print_other_inst_gen(irp, instruction->value);1124 ir_print_other_inst_gen(irp, instruction->value);
1125}1125}
11261126
1127static void ir_print_vector_store_elem(IrPrintGen *irp, IrInstGenVectorStoreElem *instruction) {1127static void ir_print_vector_store_elem(IrPrintGen *irp, Stage1AirInstVectorStoreElem *instruction) {
1128 fprintf(irp->f, "vector_ptr=");1128 fprintf(irp->f, "vector_ptr=");
1129 ir_print_var_gen(irp, instruction->vector_ptr);1129 ir_print_var_gen(irp, instruction->vector_ptr);
1130 fprintf(irp->f, ",index=");1130 fprintf(irp->f, ",index=");
...@@ -1133,7 +1133,7 @@ static void ir_print_vector_store_elem(IrPrintGen *irp, IrInstGenVectorStoreElem...@@ -1133,7 +1133,7 @@ static void ir_print_vector_store_elem(IrPrintGen *irp, IrInstGenVectorStoreElem
1133 ir_print_other_inst_gen(irp, instruction->value);1133 ir_print_other_inst_gen(irp, instruction->value);
1134}1134}
11351135
1136static void ir_print_typeof(IrPrintSrc *irp, IrInstSrcTypeOf *instruction) {1136static void ir_print_typeof(IrPrintSrc *irp, Stage1ZirInstTypeOf *instruction) {
1137 fprintf(irp->f, "@TypeOf(");1137 fprintf(irp->f, "@TypeOf(");
1138 if (instruction->value_count == 1) {1138 if (instruction->value_count == 1) {
1139 ir_print_other_inst_src(irp, instruction->value.scalar);1139 ir_print_other_inst_src(irp, instruction->value.scalar);
...@@ -1145,17 +1145,17 @@ static void ir_print_typeof(IrPrintSrc *irp, IrInstSrcTypeOf *instruction) {...@@ -1145,17 +1145,17 @@ static void ir_print_typeof(IrPrintSrc *irp, IrInstSrcTypeOf *instruction) {
1145 fprintf(irp->f, ")");1145 fprintf(irp->f, ")");
1146}1146}
11471147
1148static void ir_print_binary_not(IrPrintGen *irp, IrInstGenBinaryNot *instruction) {1148static void ir_print_binary_not(IrPrintGen *irp, Stage1AirInstBinaryNot *instruction) {
1149 fprintf(irp->f, "~");1149 fprintf(irp->f, "~");
1150 ir_print_other_inst_gen(irp, instruction->operand);1150 ir_print_other_inst_gen(irp, instruction->operand);
1151}1151}
11521152
1153static void ir_print_negation(IrPrintGen *irp, IrInstGenNegation *instruction) {1153static void ir_print_negation(IrPrintGen *irp, Stage1AirInstNegation *instruction) {
1154 fprintf(irp->f, instruction->wrapping ? "-%%" : "-");1154 fprintf(irp->f, instruction->wrapping ? "-%%" : "-");
1155 ir_print_other_inst_gen(irp, instruction->operand);1155 ir_print_other_inst_gen(irp, instruction->operand);
1156}1156}
11571157
1158static void ir_print_field_ptr(IrPrintSrc *irp, IrInstSrcFieldPtr *instruction) {1158static void ir_print_field_ptr(IrPrintSrc *irp, Stage1ZirInstFieldPtr *instruction) {
1159 if (instruction->field_name_buffer) {1159 if (instruction->field_name_buffer) {
1160 fprintf(irp->f, "fieldptr ");1160 fprintf(irp->f, "fieldptr ");
1161 ir_print_other_inst_src(irp, instruction->container_ptr);1161 ir_print_other_inst_src(irp, instruction->container_ptr);
...@@ -1170,33 +1170,33 @@ static void ir_print_field_ptr(IrPrintSrc *irp, IrInstSrcFieldPtr *instruction)...@@ -1170,33 +1170,33 @@ static void ir_print_field_ptr(IrPrintSrc *irp, IrInstSrcFieldPtr *instruction)
1170 }1170 }
1171}1171}
11721172
1173static void ir_print_struct_field_ptr(IrPrintGen *irp, IrInstGenStructFieldPtr *instruction) {1173static void ir_print_struct_field_ptr(IrPrintGen *irp, Stage1AirInstStructFieldPtr *instruction) {
1174 fprintf(irp->f, "@StructFieldPtr(&");1174 fprintf(irp->f, "@StructFieldPtr(&");
1175 ir_print_other_inst_gen(irp, instruction->struct_ptr);1175 ir_print_other_inst_gen(irp, instruction->struct_ptr);
1176 fprintf(irp->f, ".%s", buf_ptr(instruction->field->name));1176 fprintf(irp->f, ".%s", buf_ptr(instruction->field->name));
1177 fprintf(irp->f, ")");1177 fprintf(irp->f, ")");
1178}1178}
11791179
1180static void ir_print_union_field_ptr(IrPrintGen *irp, IrInstGenUnionFieldPtr *instruction) {1180static void ir_print_union_field_ptr(IrPrintGen *irp, Stage1AirInstUnionFieldPtr *instruction) {
1181 fprintf(irp->f, "@UnionFieldPtr(&");1181 fprintf(irp->f, "@UnionFieldPtr(&");
1182 ir_print_other_inst_gen(irp, instruction->union_ptr);1182 ir_print_other_inst_gen(irp, instruction->union_ptr);
1183 fprintf(irp->f, ".%s", buf_ptr(instruction->field->enum_field->name));1183 fprintf(irp->f, ".%s", buf_ptr(instruction->field->enum_field->name));
1184 fprintf(irp->f, ")");1184 fprintf(irp->f, ")");
1185}1185}
11861186
1187static void ir_print_set_cold(IrPrintSrc *irp, IrInstSrcSetCold *instruction) {1187static void ir_print_set_cold(IrPrintSrc *irp, Stage1ZirInstSetCold *instruction) {
1188 fprintf(irp->f, "@setCold(");1188 fprintf(irp->f, "@setCold(");
1189 ir_print_other_inst_src(irp, instruction->is_cold);1189 ir_print_other_inst_src(irp, instruction->is_cold);
1190 fprintf(irp->f, ")");1190 fprintf(irp->f, ")");
1191}1191}
11921192
1193static void ir_print_set_runtime_safety(IrPrintSrc *irp, IrInstSrcSetRuntimeSafety *instruction) {1193static void ir_print_set_runtime_safety(IrPrintSrc *irp, Stage1ZirInstSetRuntimeSafety *instruction) {
1194 fprintf(irp->f, "@setRuntimeSafety(");1194 fprintf(irp->f, "@setRuntimeSafety(");
1195 ir_print_other_inst_src(irp, instruction->safety_on);1195 ir_print_other_inst_src(irp, instruction->safety_on);
1196 fprintf(irp->f, ")");1196 fprintf(irp->f, ")");
1197}1197}
11981198
1199static void ir_print_set_float_mode(IrPrintSrc *irp, IrInstSrcSetFloatMode *instruction) {1199static void ir_print_set_float_mode(IrPrintSrc *irp, Stage1ZirInstSetFloatMode *instruction) {
1200 fprintf(irp->f, "@setFloatMode(");1200 fprintf(irp->f, "@setFloatMode(");
1201 ir_print_other_inst_src(irp, instruction->scope_value);1201 ir_print_other_inst_src(irp, instruction->scope_value);
1202 fprintf(irp->f, ", ");1202 fprintf(irp->f, ", ");
...@@ -1204,7 +1204,7 @@ static void ir_print_set_float_mode(IrPrintSrc *irp, IrInstSrcSetFloatMode *inst...@@ -1204,7 +1204,7 @@ static void ir_print_set_float_mode(IrPrintSrc *irp, IrInstSrcSetFloatMode *inst
1204 fprintf(irp->f, ")");1204 fprintf(irp->f, ")");
1205}1205}
12061206
1207static void ir_print_array_type(IrPrintSrc *irp, IrInstSrcArrayType *instruction) {1207static void ir_print_array_type(IrPrintSrc *irp, Stage1ZirInstArrayType *instruction) {
1208 fprintf(irp->f, "[");1208 fprintf(irp->f, "[");
1209 ir_print_other_inst_src(irp, instruction->size);1209 ir_print_other_inst_src(irp, instruction->size);
1210 if (instruction->sentinel != nullptr) {1210 if (instruction->sentinel != nullptr) {
...@@ -1215,13 +1215,13 @@ static void ir_print_array_type(IrPrintSrc *irp, IrInstSrcArrayType *instruction...@@ -1215,13 +1215,13 @@ static void ir_print_array_type(IrPrintSrc *irp, IrInstSrcArrayType *instruction
1215 ir_print_other_inst_src(irp, instruction->child_type);1215 ir_print_other_inst_src(irp, instruction->child_type);
1216}1216}
12171217
1218static void ir_print_slice_type(IrPrintSrc *irp, IrInstSrcSliceType *instruction) {1218static void ir_print_slice_type(IrPrintSrc *irp, Stage1ZirInstSliceType *instruction) {
1219 const char *const_kw = instruction->is_const ? "const " : "";1219 const char *const_kw = instruction->is_const ? "const " : "";
1220 fprintf(irp->f, "[]%s", const_kw);1220 fprintf(irp->f, "[]%s", const_kw);
1221 ir_print_other_inst_src(irp, instruction->child_type);1221 ir_print_other_inst_src(irp, instruction->child_type);
1222}1222}
12231223
1224static void ir_print_any_frame_type(IrPrintSrc *irp, IrInstSrcAnyFrameType *instruction) {1224static void ir_print_any_frame_type(IrPrintSrc *irp, Stage1ZirInstAnyFrameType *instruction) {
1225 if (instruction->payload_type == nullptr) {1225 if (instruction->payload_type == nullptr) {
1226 fprintf(irp->f, "anyframe");1226 fprintf(irp->f, "anyframe");
1227 } else {1227 } else {
...@@ -1230,7 +1230,7 @@ static void ir_print_any_frame_type(IrPrintSrc *irp, IrInstSrcAnyFrameType *inst...@@ -1230,7 +1230,7 @@ static void ir_print_any_frame_type(IrPrintSrc *irp, IrInstSrcAnyFrameType *inst
1230 }1230 }
1231}1231}
12321232
1233static void ir_print_asm_src(IrPrintSrc *irp, IrInstSrcAsm *instruction) {1233static void ir_print_asm_src(IrPrintSrc *irp, Stage1ZirInstAsm *instruction) {
1234 assert(instruction->base.source_node->type == NodeTypeAsmExpr);1234 assert(instruction->base.source_node->type == NodeTypeAsmExpr);
1235 AstNodeAsmExpr *asm_expr = &instruction->base.source_node->data.asm_expr;1235 AstNodeAsmExpr *asm_expr = &instruction->base.source_node->data.asm_expr;
1236 const char *volatile_kw = instruction->has_side_effects ? " volatile" : "";1236 const char *volatile_kw = instruction->has_side_effects ? " volatile" : "";
...@@ -1273,7 +1273,7 @@ static void ir_print_asm_src(IrPrintSrc *irp, IrInstSrcAsm *instruction) {...@@ -1273,7 +1273,7 @@ static void ir_print_asm_src(IrPrintSrc *irp, IrInstSrcAsm *instruction) {
1273 fprintf(irp->f, ")");1273 fprintf(irp->f, ")");
1274}1274}
12751275
1276static void ir_print_asm_gen(IrPrintGen *irp, IrInstGenAsm *instruction) {1276static void ir_print_asm_gen(IrPrintGen *irp, Stage1AirInstAsm *instruction) {
1277 assert(instruction->base.source_node->type == NodeTypeAsmExpr);1277 assert(instruction->base.source_node->type == NodeTypeAsmExpr);
1278 AstNodeAsmExpr *asm_expr = &instruction->base.source_node->data.asm_expr;1278 AstNodeAsmExpr *asm_expr = &instruction->base.source_node->data.asm_expr;
1279 const char *volatile_kw = instruction->has_side_effects ? " volatile" : "";1279 const char *volatile_kw = instruction->has_side_effects ? " volatile" : "";
...@@ -1315,7 +1315,7 @@ static void ir_print_asm_gen(IrPrintGen *irp, IrInstGenAsm *instruction) {...@@ -1315,7 +1315,7 @@ static void ir_print_asm_gen(IrPrintGen *irp, IrInstGenAsm *instruction) {
1315 fprintf(irp->f, ")");1315 fprintf(irp->f, ")");
1316}1316}
13171317
1318static void ir_print_size_of(IrPrintSrc *irp, IrInstSrcSizeOf *instruction) {1318static void ir_print_size_of(IrPrintSrc *irp, Stage1ZirInstSizeOf *instruction) {
1319 if (instruction->bit_size)1319 if (instruction->bit_size)
1320 fprintf(irp->f, "@bitSizeOf(");1320 fprintf(irp->f, "@bitSizeOf(");
1321 else1321 else
...@@ -1324,17 +1324,17 @@ static void ir_print_size_of(IrPrintSrc *irp, IrInstSrcSizeOf *instruction) {...@@ -1324,17 +1324,17 @@ static void ir_print_size_of(IrPrintSrc *irp, IrInstSrcSizeOf *instruction) {
1324 fprintf(irp->f, ")");1324 fprintf(irp->f, ")");
1325}1325}
13261326
1327static void ir_print_test_non_null(IrPrintSrc *irp, IrInstSrcTestNonNull *instruction) {1327static void ir_print_test_non_null(IrPrintSrc *irp, Stage1ZirInstTestNonNull *instruction) {
1328 ir_print_other_inst_src(irp, instruction->value);1328 ir_print_other_inst_src(irp, instruction->value);
1329 fprintf(irp->f, " != null");1329 fprintf(irp->f, " != null");
1330}1330}
13311331
1332static void ir_print_test_non_null(IrPrintGen *irp, IrInstGenTestNonNull *instruction) {1332static void ir_print_test_non_null(IrPrintGen *irp, Stage1AirInstTestNonNull *instruction) {
1333 ir_print_other_inst_gen(irp, instruction->value);1333 ir_print_other_inst_gen(irp, instruction->value);
1334 fprintf(irp->f, " != null");1334 fprintf(irp->f, " != null");
1335}1335}
13361336
1337static void ir_print_optional_unwrap_ptr(IrPrintSrc *irp, IrInstSrcOptionalUnwrapPtr *instruction) {1337static void ir_print_optional_unwrap_ptr(IrPrintSrc *irp, Stage1ZirInstOptionalUnwrapPtr *instruction) {
1338 fprintf(irp->f, "&");1338 fprintf(irp->f, "&");
1339 ir_print_other_inst_src(irp, instruction->base_ptr);1339 ir_print_other_inst_src(irp, instruction->base_ptr);
1340 fprintf(irp->f, ".*.?");1340 fprintf(irp->f, ".*.?");
...@@ -1343,7 +1343,7 @@ static void ir_print_optional_unwrap_ptr(IrPrintSrc *irp, IrInstSrcOptionalUnwra...@@ -1343,7 +1343,7 @@ static void ir_print_optional_unwrap_ptr(IrPrintSrc *irp, IrInstSrcOptionalUnwra
1343 }1343 }
1344}1344}
13451345
1346static void ir_print_optional_unwrap_ptr(IrPrintGen *irp, IrInstGenOptionalUnwrapPtr *instruction) {1346static void ir_print_optional_unwrap_ptr(IrPrintGen *irp, Stage1AirInstOptionalUnwrapPtr *instruction) {
1347 fprintf(irp->f, "&");1347 fprintf(irp->f, "&");
1348 ir_print_other_inst_gen(irp, instruction->base_ptr);1348 ir_print_other_inst_gen(irp, instruction->base_ptr);
1349 fprintf(irp->f, ".*.?");1349 fprintf(irp->f, ".*.?");
...@@ -1352,7 +1352,7 @@ static void ir_print_optional_unwrap_ptr(IrPrintGen *irp, IrInstGenOptionalUnwra...@@ -1352,7 +1352,7 @@ static void ir_print_optional_unwrap_ptr(IrPrintGen *irp, IrInstGenOptionalUnwra
1352 }1352 }
1353}1353}
13541354
1355static void ir_print_clz(IrPrintSrc *irp, IrInstSrcClz *instruction) {1355static void ir_print_clz(IrPrintSrc *irp, Stage1ZirInstClz *instruction) {
1356 fprintf(irp->f, "@clz(");1356 fprintf(irp->f, "@clz(");
1357 ir_print_other_inst_src(irp, instruction->type);1357 ir_print_other_inst_src(irp, instruction->type);
1358 fprintf(irp->f, ",");1358 fprintf(irp->f, ",");
...@@ -1360,13 +1360,13 @@ static void ir_print_clz(IrPrintSrc *irp, IrInstSrcClz *instruction) {...@@ -1360,13 +1360,13 @@ static void ir_print_clz(IrPrintSrc *irp, IrInstSrcClz *instruction) {
1360 fprintf(irp->f, ")");1360 fprintf(irp->f, ")");
1361}1361}
13621362
1363static void ir_print_clz(IrPrintGen *irp, IrInstGenClz *instruction) {1363static void ir_print_clz(IrPrintGen *irp, Stage1AirInstClz *instruction) {
1364 fprintf(irp->f, "@clz(");1364 fprintf(irp->f, "@clz(");
1365 ir_print_other_inst_gen(irp, instruction->op);1365 ir_print_other_inst_gen(irp, instruction->op);
1366 fprintf(irp->f, ")");1366 fprintf(irp->f, ")");
1367}1367}
13681368
1369static void ir_print_ctz(IrPrintSrc *irp, IrInstSrcCtz *instruction) {1369static void ir_print_ctz(IrPrintSrc *irp, Stage1ZirInstCtz *instruction) {
1370 fprintf(irp->f, "@ctz(");1370 fprintf(irp->f, "@ctz(");
1371 ir_print_other_inst_src(irp, instruction->type);1371 ir_print_other_inst_src(irp, instruction->type);
1372 fprintf(irp->f, ",");1372 fprintf(irp->f, ",");
...@@ -1374,13 +1374,13 @@ static void ir_print_ctz(IrPrintSrc *irp, IrInstSrcCtz *instruction) {...@@ -1374,13 +1374,13 @@ static void ir_print_ctz(IrPrintSrc *irp, IrInstSrcCtz *instruction) {
1374 fprintf(irp->f, ")");1374 fprintf(irp->f, ")");
1375}1375}
13761376
1377static void ir_print_ctz(IrPrintGen *irp, IrInstGenCtz *instruction) {1377static void ir_print_ctz(IrPrintGen *irp, Stage1AirInstCtz *instruction) {
1378 fprintf(irp->f, "@ctz(");1378 fprintf(irp->f, "@ctz(");
1379 ir_print_other_inst_gen(irp, instruction->op);1379 ir_print_other_inst_gen(irp, instruction->op);
1380 fprintf(irp->f, ")");1380 fprintf(irp->f, ")");
1381}1381}
13821382
1383static void ir_print_pop_count(IrPrintSrc *irp, IrInstSrcPopCount *instruction) {1383static void ir_print_pop_count(IrPrintSrc *irp, Stage1ZirInstPopCount *instruction) {
1384 fprintf(irp->f, "@popCount(");1384 fprintf(irp->f, "@popCount(");
1385 ir_print_other_inst_src(irp, instruction->type);1385 ir_print_other_inst_src(irp, instruction->type);
1386 fprintf(irp->f, ",");1386 fprintf(irp->f, ",");
...@@ -1388,13 +1388,13 @@ static void ir_print_pop_count(IrPrintSrc *irp, IrInstSrcPopCount *instruction)...@@ -1388,13 +1388,13 @@ static void ir_print_pop_count(IrPrintSrc *irp, IrInstSrcPopCount *instruction)
1388 fprintf(irp->f, ")");1388 fprintf(irp->f, ")");
1389}1389}
13901390
1391static void ir_print_pop_count(IrPrintGen *irp, IrInstGenPopCount *instruction) {1391static void ir_print_pop_count(IrPrintGen *irp, Stage1AirInstPopCount *instruction) {
1392 fprintf(irp->f, "@popCount(");1392 fprintf(irp->f, "@popCount(");
1393 ir_print_other_inst_gen(irp, instruction->op);1393 ir_print_other_inst_gen(irp, instruction->op);
1394 fprintf(irp->f, ")");1394 fprintf(irp->f, ")");
1395}1395}
13961396
1397static void ir_print_bswap(IrPrintSrc *irp, IrInstSrcBswap *instruction) {1397static void ir_print_bswap(IrPrintSrc *irp, Stage1ZirInstBswap *instruction) {
1398 fprintf(irp->f, "@byteSwap(");1398 fprintf(irp->f, "@byteSwap(");
1399 ir_print_other_inst_src(irp, instruction->type);1399 ir_print_other_inst_src(irp, instruction->type);
1400 fprintf(irp->f, ",");1400 fprintf(irp->f, ",");
...@@ -1402,13 +1402,13 @@ static void ir_print_bswap(IrPrintSrc *irp, IrInstSrcBswap *instruction) {...@@ -1402,13 +1402,13 @@ static void ir_print_bswap(IrPrintSrc *irp, IrInstSrcBswap *instruction) {
1402 fprintf(irp->f, ")");1402 fprintf(irp->f, ")");
1403}1403}
14041404
1405static void ir_print_bswap(IrPrintGen *irp, IrInstGenBswap *instruction) {1405static void ir_print_bswap(IrPrintGen *irp, Stage1AirInstBswap *instruction) {
1406 fprintf(irp->f, "@byteSwap(");1406 fprintf(irp->f, "@byteSwap(");
1407 ir_print_other_inst_gen(irp, instruction->op);1407 ir_print_other_inst_gen(irp, instruction->op);
1408 fprintf(irp->f, ")");1408 fprintf(irp->f, ")");
1409}1409}
14101410
1411static void ir_print_bit_reverse(IrPrintSrc *irp, IrInstSrcBitReverse *instruction) {1411static void ir_print_bit_reverse(IrPrintSrc *irp, Stage1ZirInstBitReverse *instruction) {
1412 fprintf(irp->f, "@bitReverse(");1412 fprintf(irp->f, "@bitReverse(");
1413 ir_print_other_inst_src(irp, instruction->type);1413 ir_print_other_inst_src(irp, instruction->type);
1414 fprintf(irp->f, ",");1414 fprintf(irp->f, ",");
...@@ -1416,18 +1416,18 @@ static void ir_print_bit_reverse(IrPrintSrc *irp, IrInstSrcBitReverse *instructi...@@ -1416,18 +1416,18 @@ static void ir_print_bit_reverse(IrPrintSrc *irp, IrInstSrcBitReverse *instructi
1416 fprintf(irp->f, ")");1416 fprintf(irp->f, ")");
1417}1417}
14181418
1419static void ir_print_bit_reverse(IrPrintGen *irp, IrInstGenBitReverse *instruction) {1419static void ir_print_bit_reverse(IrPrintGen *irp, Stage1AirInstBitReverse *instruction) {
1420 fprintf(irp->f, "@bitReverse(");1420 fprintf(irp->f, "@bitReverse(");
1421 ir_print_other_inst_gen(irp, instruction->op);1421 ir_print_other_inst_gen(irp, instruction->op);
1422 fprintf(irp->f, ")");1422 fprintf(irp->f, ")");
1423}1423}
14241424
1425static void ir_print_switch_br(IrPrintSrc *irp, IrInstSrcSwitchBr *instruction) {1425static void ir_print_switch_br(IrPrintSrc *irp, Stage1ZirInstSwitchBr *instruction) {
1426 fprintf(irp->f, "switch (");1426 fprintf(irp->f, "switch (");
1427 ir_print_other_inst_src(irp, instruction->target_value);1427 ir_print_other_inst_src(irp, instruction->target_value);
1428 fprintf(irp->f, ") ");1428 fprintf(irp->f, ") ");
1429 for (size_t i = 0; i < instruction->case_count; i += 1) {1429 for (size_t i = 0; i < instruction->case_count; i += 1) {
1430 IrInstSrcSwitchBrCase *this_case = &instruction->cases[i];1430 Stage1ZirInstSwitchBrCase *this_case = &instruction->cases[i];
1431 ir_print_other_inst_src(irp, this_case->value);1431 ir_print_other_inst_src(irp, this_case->value);
1432 fprintf(irp->f, " => ");1432 fprintf(irp->f, " => ");
1433 ir_print_other_block(irp, this_case->block);1433 ir_print_other_block(irp, this_case->block);
...@@ -1441,12 +1441,12 @@ static void ir_print_switch_br(IrPrintSrc *irp, IrInstSrcSwitchBr *instruction)...@@ -1441,12 +1441,12 @@ static void ir_print_switch_br(IrPrintSrc *irp, IrInstSrcSwitchBr *instruction)
1441 }1441 }
1442}1442}
14431443
1444static void ir_print_switch_br(IrPrintGen *irp, IrInstGenSwitchBr *instruction) {1444static void ir_print_switch_br(IrPrintGen *irp, Stage1AirInstSwitchBr *instruction) {
1445 fprintf(irp->f, "switch (");1445 fprintf(irp->f, "switch (");
1446 ir_print_other_inst_gen(irp, instruction->target_value);1446 ir_print_other_inst_gen(irp, instruction->target_value);
1447 fprintf(irp->f, ") ");1447 fprintf(irp->f, ") ");
1448 for (size_t i = 0; i < instruction->case_count; i += 1) {1448 for (size_t i = 0; i < instruction->case_count; i += 1) {
1449 IrInstGenSwitchBrCase *this_case = &instruction->cases[i];1449 Stage1AirInstSwitchBrCase *this_case = &instruction->cases[i];
1450 ir_print_other_inst_gen(irp, this_case->value);1450 ir_print_other_inst_gen(irp, this_case->value);
1451 fprintf(irp->f, " => ");1451 fprintf(irp->f, " => ");
1452 ir_print_other_block_gen(irp, this_case->block);1452 ir_print_other_block_gen(irp, this_case->block);
...@@ -1456,7 +1456,7 @@ static void ir_print_switch_br(IrPrintGen *irp, IrInstGenSwitchBr *instruction)...@@ -1456,7 +1456,7 @@ static void ir_print_switch_br(IrPrintGen *irp, IrInstGenSwitchBr *instruction)
1456 ir_print_other_block_gen(irp, instruction->else_block);1456 ir_print_other_block_gen(irp, instruction->else_block);
1457}1457}
14581458
1459static void ir_print_switch_var(IrPrintSrc *irp, IrInstSrcSwitchVar *instruction) {1459static void ir_print_switch_var(IrPrintSrc *irp, Stage1ZirInstSwitchVar *instruction) {
1460 fprintf(irp->f, "switchvar ");1460 fprintf(irp->f, "switchvar ");
1461 ir_print_other_inst_src(irp, instruction->target_value_ptr);1461 ir_print_other_inst_src(irp, instruction->target_value_ptr);
1462 for (size_t i = 0; i < instruction->prongs_len; i += 1) {1462 for (size_t i = 0; i < instruction->prongs_len; i += 1) {
...@@ -1465,79 +1465,79 @@ static void ir_print_switch_var(IrPrintSrc *irp, IrInstSrcSwitchVar *instruction...@@ -1465,79 +1465,79 @@ static void ir_print_switch_var(IrPrintSrc *irp, IrInstSrcSwitchVar *instruction
1465 }1465 }
1466}1466}
14671467
1468static void ir_print_switch_else_var(IrPrintSrc *irp, IrInstSrcSwitchElseVar *instruction) {1468static void ir_print_switch_else_var(IrPrintSrc *irp, Stage1ZirInstSwitchElseVar *instruction) {
1469 fprintf(irp->f, "switchelsevar ");1469 fprintf(irp->f, "switchelsevar ");
1470 ir_print_other_inst_src(irp, &instruction->switch_br->base);1470 ir_print_other_inst_src(irp, &instruction->switch_br->base);
1471}1471}
14721472
1473static void ir_print_switch_target(IrPrintSrc *irp, IrInstSrcSwitchTarget *instruction) {1473static void ir_print_switch_target(IrPrintSrc *irp, Stage1ZirInstSwitchTarget *instruction) {
1474 fprintf(irp->f, "switchtarget ");1474 fprintf(irp->f, "switchtarget ");
1475 ir_print_other_inst_src(irp, instruction->target_value_ptr);1475 ir_print_other_inst_src(irp, instruction->target_value_ptr);
1476}1476}
14771477
1478static void ir_print_union_tag(IrPrintGen *irp, IrInstGenUnionTag *instruction) {1478static void ir_print_union_tag(IrPrintGen *irp, Stage1AirInstUnionTag *instruction) {
1479 fprintf(irp->f, "uniontag ");1479 fprintf(irp->f, "uniontag ");
1480 ir_print_other_inst_gen(irp, instruction->value);1480 ir_print_other_inst_gen(irp, instruction->value);
1481}1481}
14821482
1483static void ir_print_import(IrPrintSrc *irp, IrInstSrcImport *instruction) {1483static void ir_print_import(IrPrintSrc *irp, Stage1ZirInstImport *instruction) {
1484 fprintf(irp->f, "@import(");1484 fprintf(irp->f, "@import(");
1485 ir_print_other_inst_src(irp, instruction->name);1485 ir_print_other_inst_src(irp, instruction->name);
1486 fprintf(irp->f, ")");1486 fprintf(irp->f, ")");
1487}1487}
14881488
1489static void ir_print_ref(IrPrintSrc *irp, IrInstSrcRef *instruction) {1489static void ir_print_ref(IrPrintSrc *irp, Stage1ZirInstRef *instruction) {
1490 fprintf(irp->f, "ref ");1490 fprintf(irp->f, "ref ");
1491 ir_print_other_inst_src(irp, instruction->value);1491 ir_print_other_inst_src(irp, instruction->value);
1492}1492}
14931493
1494static void ir_print_ref_gen(IrPrintGen *irp, IrInstGenRef *instruction) {1494static void ir_print_ref_gen(IrPrintGen *irp, Stage1AirInstRef *instruction) {
1495 fprintf(irp->f, "@ref(");1495 fprintf(irp->f, "@ref(");
1496 ir_print_other_inst_gen(irp, instruction->operand);1496 ir_print_other_inst_gen(irp, instruction->operand);
1497 fprintf(irp->f, ")result=");1497 fprintf(irp->f, ")result=");
1498 ir_print_other_inst_gen(irp, instruction->result_loc);1498 ir_print_other_inst_gen(irp, instruction->result_loc);
1499}1499}
15001500
1501static void ir_print_compile_err(IrPrintSrc *irp, IrInstSrcCompileErr *instruction) {1501static void ir_print_compile_err(IrPrintSrc *irp, Stage1ZirInstCompileErr *instruction) {
1502 fprintf(irp->f, "@compileError(");1502 fprintf(irp->f, "@compileError(");
1503 ir_print_other_inst_src(irp, instruction->msg);1503 ir_print_other_inst_src(irp, instruction->msg);
1504 fprintf(irp->f, ")");1504 fprintf(irp->f, ")");
1505}1505}
15061506
1507static void ir_print_compile_log(IrPrintSrc *irp, IrInstSrcCompileLog *instruction) {1507static void ir_print_compile_log(IrPrintSrc *irp, Stage1ZirInstCompileLog *instruction) {
1508 fprintf(irp->f, "@compileLog(");1508 fprintf(irp->f, "@compileLog(");
1509 for (size_t i = 0; i < instruction->msg_count; i += 1) {1509 for (size_t i = 0; i < instruction->msg_count; i += 1) {
1510 if (i != 0)1510 if (i != 0)
1511 fprintf(irp->f, ",");1511 fprintf(irp->f, ",");
1512 IrInstSrc *msg = instruction->msg_list[i];1512 Stage1ZirInst *msg = instruction->msg_list[i];
1513 ir_print_other_inst_src(irp, msg);1513 ir_print_other_inst_src(irp, msg);
1514 }1514 }
1515 fprintf(irp->f, ")");1515 fprintf(irp->f, ")");
1516}1516}
15171517
1518static void ir_print_err_name(IrPrintSrc *irp, IrInstSrcErrName *instruction) {1518static void ir_print_err_name(IrPrintSrc *irp, Stage1ZirInstErrName *instruction) {
1519 fprintf(irp->f, "@errorName(");1519 fprintf(irp->f, "@errorName(");
1520 ir_print_other_inst_src(irp, instruction->value);1520 ir_print_other_inst_src(irp, instruction->value);
1521 fprintf(irp->f, ")");1521 fprintf(irp->f, ")");
1522}1522}
15231523
1524static void ir_print_err_name(IrPrintGen *irp, IrInstGenErrName *instruction) {1524static void ir_print_err_name(IrPrintGen *irp, Stage1AirInstErrName *instruction) {
1525 fprintf(irp->f, "@errorName(");1525 fprintf(irp->f, "@errorName(");
1526 ir_print_other_inst_gen(irp, instruction->value);1526 ir_print_other_inst_gen(irp, instruction->value);
1527 fprintf(irp->f, ")");1527 fprintf(irp->f, ")");
1528}1528}
15291529
1530static void ir_print_c_import(IrPrintSrc *irp, IrInstSrcCImport *instruction) {1530static void ir_print_c_import(IrPrintSrc *irp, Stage1ZirInstCImport *instruction) {
1531 fprintf(irp->f, "@cImport(...)");1531 fprintf(irp->f, "@cImport(...)");
1532}1532}
15331533
1534static void ir_print_c_include(IrPrintSrc *irp, IrInstSrcCInclude *instruction) {1534static void ir_print_c_include(IrPrintSrc *irp, Stage1ZirInstCInclude *instruction) {
1535 fprintf(irp->f, "@cInclude(");1535 fprintf(irp->f, "@cInclude(");
1536 ir_print_other_inst_src(irp, instruction->name);1536 ir_print_other_inst_src(irp, instruction->name);
1537 fprintf(irp->f, ")");1537 fprintf(irp->f, ")");
1538}1538}
15391539
1540static void ir_print_c_define(IrPrintSrc *irp, IrInstSrcCDefine *instruction) {1540static void ir_print_c_define(IrPrintSrc *irp, Stage1ZirInstCDefine *instruction) {
1541 fprintf(irp->f, "@cDefine(");1541 fprintf(irp->f, "@cDefine(");
1542 ir_print_other_inst_src(irp, instruction->name);1542 ir_print_other_inst_src(irp, instruction->name);
1543 fprintf(irp->f, ", ");1543 fprintf(irp->f, ", ");
...@@ -1545,19 +1545,19 @@ static void ir_print_c_define(IrPrintSrc *irp, IrInstSrcCDefine *instruction) {...@@ -1545,19 +1545,19 @@ static void ir_print_c_define(IrPrintSrc *irp, IrInstSrcCDefine *instruction) {
1545 fprintf(irp->f, ")");1545 fprintf(irp->f, ")");
1546}1546}
15471547
1548static void ir_print_c_undef(IrPrintSrc *irp, IrInstSrcCUndef *instruction) {1548static void ir_print_c_undef(IrPrintSrc *irp, Stage1ZirInstCUndef *instruction) {
1549 fprintf(irp->f, "@cUndef(");1549 fprintf(irp->f, "@cUndef(");
1550 ir_print_other_inst_src(irp, instruction->name);1550 ir_print_other_inst_src(irp, instruction->name);
1551 fprintf(irp->f, ")");1551 fprintf(irp->f, ")");
1552}1552}
15531553
1554static void ir_print_embed_file(IrPrintSrc *irp, IrInstSrcEmbedFile *instruction) {1554static void ir_print_embed_file(IrPrintSrc *irp, Stage1ZirInstEmbedFile *instruction) {
1555 fprintf(irp->f, "@embedFile(");1555 fprintf(irp->f, "@embedFile(");
1556 ir_print_other_inst_src(irp, instruction->name);1556 ir_print_other_inst_src(irp, instruction->name);
1557 fprintf(irp->f, ")");1557 fprintf(irp->f, ")");
1558}1558}
15591559
1560static void ir_print_cmpxchg_src(IrPrintSrc *irp, IrInstSrcCmpxchg *instruction) {1560static void ir_print_cmpxchg_src(IrPrintSrc *irp, Stage1ZirInstCmpxchg *instruction) {
1561 fprintf(irp->f, "@cmpxchg(");1561 fprintf(irp->f, "@cmpxchg(");
1562 ir_print_other_inst_src(irp, instruction->ptr);1562 ir_print_other_inst_src(irp, instruction->ptr);
1563 fprintf(irp->f, ", ");1563 fprintf(irp->f, ", ");
...@@ -1572,7 +1572,7 @@ static void ir_print_cmpxchg_src(IrPrintSrc *irp, IrInstSrcCmpxchg *instruction)...@@ -1572,7 +1572,7 @@ static void ir_print_cmpxchg_src(IrPrintSrc *irp, IrInstSrcCmpxchg *instruction)
1572 ir_print_result_loc(irp, instruction->result_loc);1572 ir_print_result_loc(irp, instruction->result_loc);
1573}1573}
15741574
1575static void ir_print_cmpxchg_gen(IrPrintGen *irp, IrInstGenCmpxchg *instruction) {1575static void ir_print_cmpxchg_gen(IrPrintGen *irp, Stage1AirInstCmpxchg *instruction) {
1576 fprintf(irp->f, "@cmpxchg(");1576 fprintf(irp->f, "@cmpxchg(");
1577 ir_print_other_inst_gen(irp, instruction->ptr);1577 ir_print_other_inst_gen(irp, instruction->ptr);
1578 fprintf(irp->f, ", ");1578 fprintf(irp->f, ", ");
...@@ -1583,13 +1583,13 @@ static void ir_print_cmpxchg_gen(IrPrintGen *irp, IrInstGenCmpxchg *instruction)...@@ -1583,13 +1583,13 @@ static void ir_print_cmpxchg_gen(IrPrintGen *irp, IrInstGenCmpxchg *instruction)
1583 ir_print_other_inst_gen(irp, instruction->result_loc);1583 ir_print_other_inst_gen(irp, instruction->result_loc);
1584}1584}
15851585
1586static void ir_print_fence(IrPrintSrc *irp, IrInstSrcFence *instruction) {1586static void ir_print_fence(IrPrintSrc *irp, Stage1ZirInstFence *instruction) {
1587 fprintf(irp->f, "@fence(");1587 fprintf(irp->f, "@fence(");
1588 ir_print_other_inst_src(irp, instruction->order);1588 ir_print_other_inst_src(irp, instruction->order);
1589 fprintf(irp->f, ")");1589 fprintf(irp->f, ")");
1590}1590}
15911591
1592static void ir_print_reduce(IrPrintSrc *irp, IrInstSrcReduce *instruction) {1592static void ir_print_reduce(IrPrintSrc *irp, Stage1ZirInstReduce *instruction) {
1593 fprintf(irp->f, "@reduce(");1593 fprintf(irp->f, "@reduce(");
1594 ir_print_other_inst_src(irp, instruction->op);1594 ir_print_other_inst_src(irp, instruction->op);
1595 fprintf(irp->f, ", ");1595 fprintf(irp->f, ", ");
...@@ -1609,7 +1609,7 @@ static const char *atomic_order_str(AtomicOrder order) {...@@ -1609,7 +1609,7 @@ static const char *atomic_order_str(AtomicOrder order) {
1609 zig_unreachable();1609 zig_unreachable();
1610}1610}
16111611
1612static void ir_print_fence(IrPrintGen *irp, IrInstGenFence *instruction) {1612static void ir_print_fence(IrPrintGen *irp, Stage1AirInstFence *instruction) {
1613 fprintf(irp->f, "fence %s", atomic_order_str(instruction->order));1613 fprintf(irp->f, "fence %s", atomic_order_str(instruction->order));
1614}1614}
16151615
...@@ -1626,13 +1626,13 @@ static const char *reduce_op_str(ReduceOp op) {...@@ -1626,13 +1626,13 @@ static const char *reduce_op_str(ReduceOp op) {
1626 zig_unreachable();1626 zig_unreachable();
1627}1627}
16281628
1629static void ir_print_reduce(IrPrintGen *irp, IrInstGenReduce *instruction) {1629static void ir_print_reduce(IrPrintGen *irp, Stage1AirInstReduce *instruction) {
1630 fprintf(irp->f, "@reduce(.%s, ", reduce_op_str(instruction->op));1630 fprintf(irp->f, "@reduce(.%s, ", reduce_op_str(instruction->op));
1631 ir_print_other_inst_gen(irp, instruction->value);1631 ir_print_other_inst_gen(irp, instruction->value);
1632 fprintf(irp->f, ")");1632 fprintf(irp->f, ")");
1633}1633}
16341634
1635static void ir_print_truncate(IrPrintSrc *irp, IrInstSrcTruncate *instruction) {1635static void ir_print_truncate(IrPrintSrc *irp, Stage1ZirInstTruncate *instruction) {
1636 fprintf(irp->f, "@truncate(");1636 fprintf(irp->f, "@truncate(");
1637 ir_print_other_inst_src(irp, instruction->dest_type);1637 ir_print_other_inst_src(irp, instruction->dest_type);
1638 fprintf(irp->f, ", ");1638 fprintf(irp->f, ", ");
...@@ -1640,13 +1640,13 @@ static void ir_print_truncate(IrPrintSrc *irp, IrInstSrcTruncate *instruction) {...@@ -1640,13 +1640,13 @@ static void ir_print_truncate(IrPrintSrc *irp, IrInstSrcTruncate *instruction) {
1640 fprintf(irp->f, ")");1640 fprintf(irp->f, ")");
1641}1641}
16421642
1643static void ir_print_truncate(IrPrintGen *irp, IrInstGenTruncate *instruction) {1643static void ir_print_truncate(IrPrintGen *irp, Stage1AirInstTruncate *instruction) {
1644 fprintf(irp->f, "@truncate(");1644 fprintf(irp->f, "@truncate(");
1645 ir_print_other_inst_gen(irp, instruction->target);1645 ir_print_other_inst_gen(irp, instruction->target);
1646 fprintf(irp->f, ")");1646 fprintf(irp->f, ")");
1647}1647}
16481648
1649static void ir_print_int_cast(IrPrintSrc *irp, IrInstSrcIntCast *instruction) {1649static void ir_print_int_cast(IrPrintSrc *irp, Stage1ZirInstIntCast *instruction) {
1650 fprintf(irp->f, "@intCast(");1650 fprintf(irp->f, "@intCast(");
1651 ir_print_other_inst_src(irp, instruction->dest_type);1651 ir_print_other_inst_src(irp, instruction->dest_type);
1652 fprintf(irp->f, ", ");1652 fprintf(irp->f, ", ");
...@@ -1654,7 +1654,7 @@ static void ir_print_int_cast(IrPrintSrc *irp, IrInstSrcIntCast *instruction) {...@@ -1654,7 +1654,7 @@ static void ir_print_int_cast(IrPrintSrc *irp, IrInstSrcIntCast *instruction) {
1654 fprintf(irp->f, ")");1654 fprintf(irp->f, ")");
1655}1655}
16561656
1657static void ir_print_float_cast(IrPrintSrc *irp, IrInstSrcFloatCast *instruction) {1657static void ir_print_float_cast(IrPrintSrc *irp, Stage1ZirInstFloatCast *instruction) {
1658 fprintf(irp->f, "@floatCast(");1658 fprintf(irp->f, "@floatCast(");
1659 ir_print_other_inst_src(irp, instruction->dest_type);1659 ir_print_other_inst_src(irp, instruction->dest_type);
1660 fprintf(irp->f, ", ");1660 fprintf(irp->f, ", ");
...@@ -1662,7 +1662,7 @@ static void ir_print_float_cast(IrPrintSrc *irp, IrInstSrcFloatCast *instruction...@@ -1662,7 +1662,7 @@ static void ir_print_float_cast(IrPrintSrc *irp, IrInstSrcFloatCast *instruction
1662 fprintf(irp->f, ")");1662 fprintf(irp->f, ")");
1663}1663}
16641664
1665static void ir_print_err_set_cast(IrPrintSrc *irp, IrInstSrcErrSetCast *instruction) {1665static void ir_print_err_set_cast(IrPrintSrc *irp, Stage1ZirInstErrSetCast *instruction) {
1666 fprintf(irp->f, "@errSetCast(");1666 fprintf(irp->f, "@errSetCast(");
1667 ir_print_other_inst_src(irp, instruction->dest_type);1667 ir_print_other_inst_src(irp, instruction->dest_type);
1668 fprintf(irp->f, ", ");1668 fprintf(irp->f, ", ");
...@@ -1670,7 +1670,7 @@ static void ir_print_err_set_cast(IrPrintSrc *irp, IrInstSrcErrSetCast *instruct...@@ -1670,7 +1670,7 @@ static void ir_print_err_set_cast(IrPrintSrc *irp, IrInstSrcErrSetCast *instruct
1670 fprintf(irp->f, ")");1670 fprintf(irp->f, ")");
1671}1671}
16721672
1673static void ir_print_int_to_float(IrPrintSrc *irp, IrInstSrcIntToFloat *instruction) {1673static void ir_print_int_to_float(IrPrintSrc *irp, Stage1ZirInstIntToFloat *instruction) {
1674 fprintf(irp->f, "@intToFloat(");1674 fprintf(irp->f, "@intToFloat(");
1675 ir_print_other_inst_src(irp, instruction->dest_type);1675 ir_print_other_inst_src(irp, instruction->dest_type);
1676 fprintf(irp->f, ", ");1676 fprintf(irp->f, ", ");
...@@ -1678,7 +1678,7 @@ static void ir_print_int_to_float(IrPrintSrc *irp, IrInstSrcIntToFloat *instruct...@@ -1678,7 +1678,7 @@ static void ir_print_int_to_float(IrPrintSrc *irp, IrInstSrcIntToFloat *instruct
1678 fprintf(irp->f, ")");1678 fprintf(irp->f, ")");
1679}1679}
16801680
1681static void ir_print_float_to_int(IrPrintSrc *irp, IrInstSrcFloatToInt *instruction) {1681static void ir_print_float_to_int(IrPrintSrc *irp, Stage1ZirInstFloatToInt *instruction) {
1682 fprintf(irp->f, "@floatToInt(");1682 fprintf(irp->f, "@floatToInt(");
1683 ir_print_other_inst_src(irp, instruction->dest_type);1683 ir_print_other_inst_src(irp, instruction->dest_type);
1684 fprintf(irp->f, ", ");1684 fprintf(irp->f, ", ");
...@@ -1686,13 +1686,13 @@ static void ir_print_float_to_int(IrPrintSrc *irp, IrInstSrcFloatToInt *instruct...@@ -1686,13 +1686,13 @@ static void ir_print_float_to_int(IrPrintSrc *irp, IrInstSrcFloatToInt *instruct
1686 fprintf(irp->f, ")");1686 fprintf(irp->f, ")");
1687}1687}
16881688
1689static void ir_print_bool_to_int(IrPrintSrc *irp, IrInstSrcBoolToInt *instruction) {1689static void ir_print_bool_to_int(IrPrintSrc *irp, Stage1ZirInstBoolToInt *instruction) {
1690 fprintf(irp->f, "@boolToInt(");1690 fprintf(irp->f, "@boolToInt(");
1691 ir_print_other_inst_src(irp, instruction->target);1691 ir_print_other_inst_src(irp, instruction->target);
1692 fprintf(irp->f, ")");1692 fprintf(irp->f, ")");
1693}1693}
16941694
1695static void ir_print_vector_type(IrPrintSrc *irp, IrInstSrcVectorType *instruction) {1695static void ir_print_vector_type(IrPrintSrc *irp, Stage1ZirInstVectorType *instruction) {
1696 fprintf(irp->f, "@Vector(");1696 fprintf(irp->f, "@Vector(");
1697 ir_print_other_inst_src(irp, instruction->len);1697 ir_print_other_inst_src(irp, instruction->len);
1698 fprintf(irp->f, ", ");1698 fprintf(irp->f, ", ");
...@@ -1700,7 +1700,7 @@ static void ir_print_vector_type(IrPrintSrc *irp, IrInstSrcVectorType *instructi...@@ -1700,7 +1700,7 @@ static void ir_print_vector_type(IrPrintSrc *irp, IrInstSrcVectorType *instructi
1700 fprintf(irp->f, ")");1700 fprintf(irp->f, ")");
1701}1701}
17021702
1703static void ir_print_shuffle_vector(IrPrintSrc *irp, IrInstSrcShuffleVector *instruction) {1703static void ir_print_shuffle_vector(IrPrintSrc *irp, Stage1ZirInstShuffleVector *instruction) {
1704 fprintf(irp->f, "@shuffle(");1704 fprintf(irp->f, "@shuffle(");
1705 ir_print_other_inst_src(irp, instruction->scalar_type);1705 ir_print_other_inst_src(irp, instruction->scalar_type);
1706 fprintf(irp->f, ", ");1706 fprintf(irp->f, ", ");
...@@ -1712,7 +1712,7 @@ static void ir_print_shuffle_vector(IrPrintSrc *irp, IrInstSrcShuffleVector *ins...@@ -1712,7 +1712,7 @@ static void ir_print_shuffle_vector(IrPrintSrc *irp, IrInstSrcShuffleVector *ins
1712 fprintf(irp->f, ")");1712 fprintf(irp->f, ")");
1713}1713}
17141714
1715static void ir_print_shuffle_vector(IrPrintGen *irp, IrInstGenShuffleVector *instruction) {1715static void ir_print_shuffle_vector(IrPrintGen *irp, Stage1AirInstShuffleVector *instruction) {
1716 fprintf(irp->f, "@shuffle(");1716 fprintf(irp->f, "@shuffle(");
1717 ir_print_other_inst_gen(irp, instruction->a);1717 ir_print_other_inst_gen(irp, instruction->a);
1718 fprintf(irp->f, ", ");1718 fprintf(irp->f, ", ");
...@@ -1722,7 +1722,7 @@ static void ir_print_shuffle_vector(IrPrintGen *irp, IrInstGenShuffleVector *ins...@@ -1722,7 +1722,7 @@ static void ir_print_shuffle_vector(IrPrintGen *irp, IrInstGenShuffleVector *ins
1722 fprintf(irp->f, ")");1722 fprintf(irp->f, ")");
1723}1723}
17241724
1725static void ir_print_splat_src(IrPrintSrc *irp, IrInstSrcSplat *instruction) {1725static void ir_print_splat_src(IrPrintSrc *irp, Stage1ZirInstSplat *instruction) {
1726 fprintf(irp->f, "@splat(");1726 fprintf(irp->f, "@splat(");
1727 ir_print_other_inst_src(irp, instruction->len);1727 ir_print_other_inst_src(irp, instruction->len);
1728 fprintf(irp->f, ", ");1728 fprintf(irp->f, ", ");
...@@ -1730,35 +1730,35 @@ static void ir_print_splat_src(IrPrintSrc *irp, IrInstSrcSplat *instruction) {...@@ -1730,35 +1730,35 @@ static void ir_print_splat_src(IrPrintSrc *irp, IrInstSrcSplat *instruction) {
1730 fprintf(irp->f, ")");1730 fprintf(irp->f, ")");
1731}1731}
17321732
1733static void ir_print_splat_gen(IrPrintGen *irp, IrInstGenSplat *instruction) {1733static void ir_print_splat_gen(IrPrintGen *irp, Stage1AirInstSplat *instruction) {
1734 fprintf(irp->f, "@splat(");1734 fprintf(irp->f, "@splat(");
1735 ir_print_other_inst_gen(irp, instruction->scalar);1735 ir_print_other_inst_gen(irp, instruction->scalar);
1736 fprintf(irp->f, ")");1736 fprintf(irp->f, ")");
1737}1737}
17381738
1739static void ir_print_bool_not(IrPrintSrc *irp, IrInstSrcBoolNot *instruction) {1739static void ir_print_bool_not(IrPrintSrc *irp, Stage1ZirInstBoolNot *instruction) {
1740 fprintf(irp->f, "! ");1740 fprintf(irp->f, "! ");
1741 ir_print_other_inst_src(irp, instruction->value);1741 ir_print_other_inst_src(irp, instruction->value);
1742}1742}
17431743
1744static void ir_print_bool_not(IrPrintGen *irp, IrInstGenBoolNot *instruction) {1744static void ir_print_bool_not(IrPrintGen *irp, Stage1AirInstBoolNot *instruction) {
1745 fprintf(irp->f, "! ");1745 fprintf(irp->f, "! ");
1746 ir_print_other_inst_gen(irp, instruction->value);1746 ir_print_other_inst_gen(irp, instruction->value);
1747}1747}
17481748
1749static void ir_print_wasm_memory_size(IrPrintSrc *irp, IrInstSrcWasmMemorySize *instruction) {1749static void ir_print_wasm_memory_size(IrPrintSrc *irp, Stage1ZirInstWasmMemorySize *instruction) {
1750 fprintf(irp->f, "@wasmMemorySize(");1750 fprintf(irp->f, "@wasmMemorySize(");
1751 ir_print_other_inst_src(irp, instruction->index);1751 ir_print_other_inst_src(irp, instruction->index);
1752 fprintf(irp->f, ")");1752 fprintf(irp->f, ")");
1753}1753}
17541754
1755static void ir_print_wasm_memory_size(IrPrintGen *irp, IrInstGenWasmMemorySize *instruction) {1755static void ir_print_wasm_memory_size(IrPrintGen *irp, Stage1AirInstWasmMemorySize *instruction) {
1756 fprintf(irp->f, "@wasmMemorySize(");1756 fprintf(irp->f, "@wasmMemorySize(");
1757 ir_print_other_inst_gen(irp, instruction->index);1757 ir_print_other_inst_gen(irp, instruction->index);
1758 fprintf(irp->f, ")");1758 fprintf(irp->f, ")");
1759}1759}
17601760
1761static void ir_print_wasm_memory_grow(IrPrintSrc *irp, IrInstSrcWasmMemoryGrow *instruction) {1761static void ir_print_wasm_memory_grow(IrPrintSrc *irp, Stage1ZirInstWasmMemoryGrow *instruction) {
1762 fprintf(irp->f, "@wasmMemoryGrow(");1762 fprintf(irp->f, "@wasmMemoryGrow(");
1763 ir_print_other_inst_src(irp, instruction->index);1763 ir_print_other_inst_src(irp, instruction->index);
1764 fprintf(irp->f, ", ");1764 fprintf(irp->f, ", ");
...@@ -1766,7 +1766,7 @@ static void ir_print_wasm_memory_grow(IrPrintSrc *irp, IrInstSrcWasmMemoryGrow *...@@ -1766,7 +1766,7 @@ static void ir_print_wasm_memory_grow(IrPrintSrc *irp, IrInstSrcWasmMemoryGrow *
1766 fprintf(irp->f, ")");1766 fprintf(irp->f, ")");
1767}1767}
17681768
1769static void ir_print_wasm_memory_grow(IrPrintGen *irp, IrInstGenWasmMemoryGrow *instruction) {1769static void ir_print_wasm_memory_grow(IrPrintGen *irp, Stage1AirInstWasmMemoryGrow *instruction) {
1770 fprintf(irp->f, "@wasmMemoryGrow(");1770 fprintf(irp->f, "@wasmMemoryGrow(");
1771 ir_print_other_inst_gen(irp, instruction->index);1771 ir_print_other_inst_gen(irp, instruction->index);
1772 fprintf(irp->f, ", ");1772 fprintf(irp->f, ", ");
...@@ -1774,11 +1774,11 @@ static void ir_print_wasm_memory_grow(IrPrintGen *irp, IrInstGenWasmMemoryGrow *...@@ -1774,11 +1774,11 @@ static void ir_print_wasm_memory_grow(IrPrintGen *irp, IrInstGenWasmMemoryGrow *
1774 fprintf(irp->f, ")");1774 fprintf(irp->f, ")");
1775}1775}
17761776
1777static void ir_print_builtin_src(IrPrintSrc *irp, IrInstSrcSrc *instruction) {1777static void ir_print_builtin_src(IrPrintSrc *irp, Stage1ZirInstSrc *instruction) {
1778 fprintf(irp->f, "@src()");1778 fprintf(irp->f, "@src()");
1779}1779}
17801780
1781static void ir_print_memset(IrPrintSrc *irp, IrInstSrcMemset *instruction) {1781static void ir_print_memset(IrPrintSrc *irp, Stage1ZirInstMemset *instruction) {
1782 fprintf(irp->f, "@memset(");1782 fprintf(irp->f, "@memset(");
1783 ir_print_other_inst_src(irp, instruction->dest_ptr);1783 ir_print_other_inst_src(irp, instruction->dest_ptr);
1784 fprintf(irp->f, ", ");1784 fprintf(irp->f, ", ");
...@@ -1788,7 +1788,7 @@ static void ir_print_memset(IrPrintSrc *irp, IrInstSrcMemset *instruction) {...@@ -1788,7 +1788,7 @@ static void ir_print_memset(IrPrintSrc *irp, IrInstSrcMemset *instruction) {
1788 fprintf(irp->f, ")");1788 fprintf(irp->f, ")");
1789}1789}
17901790
1791static void ir_print_memset(IrPrintGen *irp, IrInstGenMemset *instruction) {1791static void ir_print_memset(IrPrintGen *irp, Stage1AirInstMemset *instruction) {
1792 fprintf(irp->f, "@memset(");1792 fprintf(irp->f, "@memset(");
1793 ir_print_other_inst_gen(irp, instruction->dest_ptr);1793 ir_print_other_inst_gen(irp, instruction->dest_ptr);
1794 fprintf(irp->f, ", ");1794 fprintf(irp->f, ", ");
...@@ -1798,7 +1798,7 @@ static void ir_print_memset(IrPrintGen *irp, IrInstGenMemset *instruction) {...@@ -1798,7 +1798,7 @@ static void ir_print_memset(IrPrintGen *irp, IrInstGenMemset *instruction) {
1798 fprintf(irp->f, ")");1798 fprintf(irp->f, ")");
1799}1799}
18001800
1801static void ir_print_memcpy(IrPrintSrc *irp, IrInstSrcMemcpy *instruction) {1801static void ir_print_memcpy(IrPrintSrc *irp, Stage1ZirInstMemcpy *instruction) {
1802 fprintf(irp->f, "@memcpy(");1802 fprintf(irp->f, "@memcpy(");
1803 ir_print_other_inst_src(irp, instruction->dest_ptr);1803 ir_print_other_inst_src(irp, instruction->dest_ptr);
1804 fprintf(irp->f, ", ");1804 fprintf(irp->f, ", ");
...@@ -1808,7 +1808,7 @@ static void ir_print_memcpy(IrPrintSrc *irp, IrInstSrcMemcpy *instruction) {...@@ -1808,7 +1808,7 @@ static void ir_print_memcpy(IrPrintSrc *irp, IrInstSrcMemcpy *instruction) {
1808 fprintf(irp->f, ")");1808 fprintf(irp->f, ")");
1809}1809}
18101810
1811static void ir_print_memcpy(IrPrintGen *irp, IrInstGenMemcpy *instruction) {1811static void ir_print_memcpy(IrPrintGen *irp, Stage1AirInstMemcpy *instruction) {
1812 fprintf(irp->f, "@memcpy(");1812 fprintf(irp->f, "@memcpy(");
1813 ir_print_other_inst_gen(irp, instruction->dest_ptr);1813 ir_print_other_inst_gen(irp, instruction->dest_ptr);
1814 fprintf(irp->f, ", ");1814 fprintf(irp->f, ", ");
...@@ -1818,7 +1818,7 @@ static void ir_print_memcpy(IrPrintGen *irp, IrInstGenMemcpy *instruction) {...@@ -1818,7 +1818,7 @@ static void ir_print_memcpy(IrPrintGen *irp, IrInstGenMemcpy *instruction) {
1818 fprintf(irp->f, ")");1818 fprintf(irp->f, ")");
1819}1819}
18201820
1821static void ir_print_slice_src(IrPrintSrc *irp, IrInstSrcSlice *instruction) {1821static void ir_print_slice_src(IrPrintSrc *irp, Stage1ZirInstSlice *instruction) {
1822 ir_print_other_inst_src(irp, instruction->ptr);1822 ir_print_other_inst_src(irp, instruction->ptr);
1823 fprintf(irp->f, "[");1823 fprintf(irp->f, "[");
1824 ir_print_other_inst_src(irp, instruction->start);1824 ir_print_other_inst_src(irp, instruction->start);
...@@ -1829,7 +1829,7 @@ static void ir_print_slice_src(IrPrintSrc *irp, IrInstSrcSlice *instruction) {...@@ -1829,7 +1829,7 @@ static void ir_print_slice_src(IrPrintSrc *irp, IrInstSrcSlice *instruction) {
1829 ir_print_result_loc(irp, instruction->result_loc);1829 ir_print_result_loc(irp, instruction->result_loc);
1830}1830}
18311831
1832static void ir_print_slice_gen(IrPrintGen *irp, IrInstGenSlice *instruction) {1832static void ir_print_slice_gen(IrPrintGen *irp, Stage1AirInstSlice *instruction) {
1833 ir_print_other_inst_gen(irp, instruction->ptr);1833 ir_print_other_inst_gen(irp, instruction->ptr);
1834 fprintf(irp->f, "[");1834 fprintf(irp->f, "[");
1835 ir_print_other_inst_gen(irp, instruction->start);1835 ir_print_other_inst_gen(irp, instruction->start);
...@@ -1840,63 +1840,63 @@ static void ir_print_slice_gen(IrPrintGen *irp, IrInstGenSlice *instruction) {...@@ -1840,63 +1840,63 @@ static void ir_print_slice_gen(IrPrintGen *irp, IrInstGenSlice *instruction) {
1840 ir_print_other_inst_gen(irp, instruction->result_loc);1840 ir_print_other_inst_gen(irp, instruction->result_loc);
1841}1841}
18421842
1843static void ir_print_breakpoint(IrPrintSrc *irp, IrInstSrcBreakpoint *instruction) {1843static void ir_print_breakpoint(IrPrintSrc *irp, Stage1ZirInstBreakpoint *instruction) {
1844 fprintf(irp->f, "@breakpoint()");1844 fprintf(irp->f, "@breakpoint()");
1845}1845}
18461846
1847static void ir_print_breakpoint(IrPrintGen *irp, IrInstGenBreakpoint *instruction) {1847static void ir_print_breakpoint(IrPrintGen *irp, Stage1AirInstBreakpoint *instruction) {
1848 fprintf(irp->f, "@breakpoint()");1848 fprintf(irp->f, "@breakpoint()");
1849}1849}
18501850
1851static void ir_print_frame_address(IrPrintSrc *irp, IrInstSrcFrameAddress *instruction) {1851static void ir_print_frame_address(IrPrintSrc *irp, Stage1ZirInstFrameAddress *instruction) {
1852 fprintf(irp->f, "@frameAddress()");1852 fprintf(irp->f, "@frameAddress()");
1853}1853}
18541854
1855static void ir_print_frame_address(IrPrintGen *irp, IrInstGenFrameAddress *instruction) {1855static void ir_print_frame_address(IrPrintGen *irp, Stage1AirInstFrameAddress *instruction) {
1856 fprintf(irp->f, "@frameAddress()");1856 fprintf(irp->f, "@frameAddress()");
1857}1857}
18581858
1859static void ir_print_handle(IrPrintSrc *irp, IrInstSrcFrameHandle *instruction) {1859static void ir_print_handle(IrPrintSrc *irp, Stage1ZirInstFrameHandle *instruction) {
1860 fprintf(irp->f, "@frame()");1860 fprintf(irp->f, "@frame()");
1861}1861}
18621862
1863static void ir_print_handle(IrPrintGen *irp, IrInstGenFrameHandle *instruction) {1863static void ir_print_handle(IrPrintGen *irp, Stage1AirInstFrameHandle *instruction) {
1864 fprintf(irp->f, "@frame()");1864 fprintf(irp->f, "@frame()");
1865}1865}
18661866
1867static void ir_print_frame_type(IrPrintSrc *irp, IrInstSrcFrameType *instruction) {1867static void ir_print_frame_type(IrPrintSrc *irp, Stage1ZirInstFrameType *instruction) {
1868 fprintf(irp->f, "@Frame(");1868 fprintf(irp->f, "@Frame(");
1869 ir_print_other_inst_src(irp, instruction->fn);1869 ir_print_other_inst_src(irp, instruction->fn);
1870 fprintf(irp->f, ")");1870 fprintf(irp->f, ")");
1871}1871}
18721872
1873static void ir_print_frame_size_src(IrPrintSrc *irp, IrInstSrcFrameSize *instruction) {1873static void ir_print_frame_size_src(IrPrintSrc *irp, Stage1ZirInstFrameSize *instruction) {
1874 fprintf(irp->f, "@frameSize(");1874 fprintf(irp->f, "@frameSize(");
1875 ir_print_other_inst_src(irp, instruction->fn);1875 ir_print_other_inst_src(irp, instruction->fn);
1876 fprintf(irp->f, ")");1876 fprintf(irp->f, ")");
1877}1877}
18781878
1879static void ir_print_frame_size_gen(IrPrintGen *irp, IrInstGenFrameSize *instruction) {1879static void ir_print_frame_size_gen(IrPrintGen *irp, Stage1AirInstFrameSize *instruction) {
1880 fprintf(irp->f, "@frameSize(");1880 fprintf(irp->f, "@frameSize(");
1881 ir_print_other_inst_gen(irp, instruction->fn);1881 ir_print_other_inst_gen(irp, instruction->fn);
1882 fprintf(irp->f, ")");1882 fprintf(irp->f, ")");
1883}1883}
18841884
1885static void ir_print_return_address(IrPrintSrc *irp, IrInstSrcReturnAddress *instruction) {1885static void ir_print_return_address(IrPrintSrc *irp, Stage1ZirInstReturnAddress *instruction) {
1886 fprintf(irp->f, "@returnAddress()");1886 fprintf(irp->f, "@returnAddress()");
1887}1887}
18881888
1889static void ir_print_return_address(IrPrintGen *irp, IrInstGenReturnAddress *instruction) {1889static void ir_print_return_address(IrPrintGen *irp, Stage1AirInstReturnAddress *instruction) {
1890 fprintf(irp->f, "@returnAddress()");1890 fprintf(irp->f, "@returnAddress()");
1891}1891}
18921892
1893static void ir_print_align_of(IrPrintSrc *irp, IrInstSrcAlignOf *instruction) {1893static void ir_print_align_of(IrPrintSrc *irp, Stage1ZirInstAlignOf *instruction) {
1894 fprintf(irp->f, "@alignOf(");1894 fprintf(irp->f, "@alignOf(");
1895 ir_print_other_inst_src(irp, instruction->type_value);1895 ir_print_other_inst_src(irp, instruction->type_value);
1896 fprintf(irp->f, ")");1896 fprintf(irp->f, ")");
1897}1897}
18981898
1899static void ir_print_overflow_op(IrPrintSrc *irp, IrInstSrcOverflowOp *instruction) {1899static void ir_print_overflow_op(IrPrintSrc *irp, Stage1ZirInstOverflowOp *instruction) {
1900 switch (instruction->op) {1900 switch (instruction->op) {
1901 case IrOverflowOpAdd:1901 case IrOverflowOpAdd:
1902 fprintf(irp->f, "@addWithOverflow(");1902 fprintf(irp->f, "@addWithOverflow(");
...@@ -1921,7 +1921,7 @@ static void ir_print_overflow_op(IrPrintSrc *irp, IrInstSrcOverflowOp *instructi...@@ -1921,7 +1921,7 @@ static void ir_print_overflow_op(IrPrintSrc *irp, IrInstSrcOverflowOp *instructi
1921 fprintf(irp->f, ")");1921 fprintf(irp->f, ")");
1922}1922}
19231923
1924static void ir_print_overflow_op(IrPrintGen *irp, IrInstGenOverflowOp *instruction) {1924static void ir_print_overflow_op(IrPrintGen *irp, Stage1AirInstOverflowOp *instruction) {
1925 switch (instruction->op) {1925 switch (instruction->op) {
1926 case IrOverflowOpAdd:1926 case IrOverflowOpAdd:
1927 fprintf(irp->f, "@addWithOverflow(");1927 fprintf(irp->f, "@addWithOverflow(");
...@@ -1944,64 +1944,64 @@ static void ir_print_overflow_op(IrPrintGen *irp, IrInstGenOverflowOp *instructi...@@ -1944,64 +1944,64 @@ static void ir_print_overflow_op(IrPrintGen *irp, IrInstGenOverflowOp *instructi
1944 fprintf(irp->f, ")");1944 fprintf(irp->f, ")");
1945}1945}
19461946
1947static void ir_print_test_err_src(IrPrintSrc *irp, IrInstSrcTestErr *instruction) {1947static void ir_print_test_err_src(IrPrintSrc *irp, Stage1ZirInstTestErr *instruction) {
1948 fprintf(irp->f, "@testError(");1948 fprintf(irp->f, "@testError(");
1949 ir_print_other_inst_src(irp, instruction->base_ptr);1949 ir_print_other_inst_src(irp, instruction->base_ptr);
1950 fprintf(irp->f, ")");1950 fprintf(irp->f, ")");
1951}1951}
19521952
1953static void ir_print_test_err_gen(IrPrintGen *irp, IrInstGenTestErr *instruction) {1953static void ir_print_test_err_gen(IrPrintGen *irp, Stage1AirInstTestErr *instruction) {
1954 fprintf(irp->f, "@testError(");1954 fprintf(irp->f, "@testError(");
1955 ir_print_other_inst_gen(irp, instruction->err_union);1955 ir_print_other_inst_gen(irp, instruction->err_union);
1956 fprintf(irp->f, ")");1956 fprintf(irp->f, ")");
1957}1957}
19581958
1959static void ir_print_unwrap_err_code(IrPrintSrc *irp, IrInstSrcUnwrapErrCode *instruction) {1959static void ir_print_unwrap_err_code(IrPrintSrc *irp, Stage1ZirInstUnwrapErrCode *instruction) {
1960 fprintf(irp->f, "UnwrapErrorCode(");1960 fprintf(irp->f, "UnwrapErrorCode(");
1961 ir_print_other_inst_src(irp, instruction->err_union_ptr);1961 ir_print_other_inst_src(irp, instruction->err_union_ptr);
1962 fprintf(irp->f, ")");1962 fprintf(irp->f, ")");
1963}1963}
19641964
1965static void ir_print_unwrap_err_code(IrPrintGen *irp, IrInstGenUnwrapErrCode *instruction) {1965static void ir_print_unwrap_err_code(IrPrintGen *irp, Stage1AirInstUnwrapErrCode *instruction) {
1966 fprintf(irp->f, "UnwrapErrorCode(");1966 fprintf(irp->f, "UnwrapErrorCode(");
1967 ir_print_other_inst_gen(irp, instruction->err_union_ptr);1967 ir_print_other_inst_gen(irp, instruction->err_union_ptr);
1968 fprintf(irp->f, ")");1968 fprintf(irp->f, ")");
1969}1969}
19701970
1971static void ir_print_unwrap_err_payload(IrPrintSrc *irp, IrInstSrcUnwrapErrPayload *instruction) {1971static void ir_print_unwrap_err_payload(IrPrintSrc *irp, Stage1ZirInstUnwrapErrPayload *instruction) {
1972 fprintf(irp->f, "ErrorUnionFieldPayload(");1972 fprintf(irp->f, "ErrorUnionFieldPayload(");
1973 ir_print_other_inst_src(irp, instruction->value);1973 ir_print_other_inst_src(irp, instruction->value);
1974 fprintf(irp->f, ")safety=%d,init=%d",instruction->safety_check_on, instruction->initializing);1974 fprintf(irp->f, ")safety=%d,init=%d",instruction->safety_check_on, instruction->initializing);
1975}1975}
19761976
1977static void ir_print_unwrap_err_payload(IrPrintGen *irp, IrInstGenUnwrapErrPayload *instruction) {1977static void ir_print_unwrap_err_payload(IrPrintGen *irp, Stage1AirInstUnwrapErrPayload *instruction) {
1978 fprintf(irp->f, "ErrorUnionFieldPayload(");1978 fprintf(irp->f, "ErrorUnionFieldPayload(");
1979 ir_print_other_inst_gen(irp, instruction->value);1979 ir_print_other_inst_gen(irp, instruction->value);
1980 fprintf(irp->f, ")safety=%d,init=%d",instruction->safety_check_on, instruction->initializing);1980 fprintf(irp->f, ")safety=%d,init=%d",instruction->safety_check_on, instruction->initializing);
1981}1981}
19821982
1983static void ir_print_optional_wrap(IrPrintGen *irp, IrInstGenOptionalWrap *instruction) {1983static void ir_print_optional_wrap(IrPrintGen *irp, Stage1AirInstOptionalWrap *instruction) {
1984 fprintf(irp->f, "@optionalWrap(");1984 fprintf(irp->f, "@optionalWrap(");
1985 ir_print_other_inst_gen(irp, instruction->operand);1985 ir_print_other_inst_gen(irp, instruction->operand);
1986 fprintf(irp->f, ")result=");1986 fprintf(irp->f, ")result=");
1987 ir_print_other_inst_gen(irp, instruction->result_loc);1987 ir_print_other_inst_gen(irp, instruction->result_loc);
1988}1988}
19891989
1990static void ir_print_err_wrap_code(IrPrintGen *irp, IrInstGenErrWrapCode *instruction) {1990static void ir_print_err_wrap_code(IrPrintGen *irp, Stage1AirInstErrWrapCode *instruction) {
1991 fprintf(irp->f, "@errWrapCode(");1991 fprintf(irp->f, "@errWrapCode(");
1992 ir_print_other_inst_gen(irp, instruction->operand);1992 ir_print_other_inst_gen(irp, instruction->operand);
1993 fprintf(irp->f, ")result=");1993 fprintf(irp->f, ")result=");
1994 ir_print_other_inst_gen(irp, instruction->result_loc);1994 ir_print_other_inst_gen(irp, instruction->result_loc);
1995}1995}
19961996
1997static void ir_print_err_wrap_payload(IrPrintGen *irp, IrInstGenErrWrapPayload *instruction) {1997static void ir_print_err_wrap_payload(IrPrintGen *irp, Stage1AirInstErrWrapPayload *instruction) {
1998 fprintf(irp->f, "@errWrapPayload(");1998 fprintf(irp->f, "@errWrapPayload(");
1999 ir_print_other_inst_gen(irp, instruction->operand);1999 ir_print_other_inst_gen(irp, instruction->operand);
2000 fprintf(irp->f, ")result=");2000 fprintf(irp->f, ")result=");
2001 ir_print_other_inst_gen(irp, instruction->result_loc);2001 ir_print_other_inst_gen(irp, instruction->result_loc);
2002}2002}
20032003
2004static void ir_print_fn_proto(IrPrintSrc *irp, IrInstSrcFnProto *instruction) {2004static void ir_print_fn_proto(IrPrintSrc *irp, Stage1ZirInstFnProto *instruction) {
2005 fprintf(irp->f, "fn(");2005 fprintf(irp->f, "fn(");
2006 for (size_t i = 0; i < instruction->base.source_node->data.fn_proto.params.length; i += 1) {2006 for (size_t i = 0; i < instruction->base.source_node->data.fn_proto.params.length; i += 1) {
2007 if (i != 0)2007 if (i != 0)
...@@ -2022,13 +2022,13 @@ static void ir_print_fn_proto(IrPrintSrc *irp, IrInstSrcFnProto *instruction) {...@@ -2022,13 +2022,13 @@ static void ir_print_fn_proto(IrPrintSrc *irp, IrInstSrcFnProto *instruction) {
2022 ir_print_other_inst_src(irp, instruction->return_type);2022 ir_print_other_inst_src(irp, instruction->return_type);
2023}2023}
20242024
2025static void ir_print_test_comptime(IrPrintSrc *irp, IrInstSrcTestComptime *instruction) {2025static void ir_print_test_comptime(IrPrintSrc *irp, Stage1ZirInstTestComptime *instruction) {
2026 fprintf(irp->f, "@testComptime(");2026 fprintf(irp->f, "@testComptime(");
2027 ir_print_other_inst_src(irp, instruction->value);2027 ir_print_other_inst_src(irp, instruction->value);
2028 fprintf(irp->f, ")");2028 fprintf(irp->f, ")");
2029}2029}
20302030
2031static void ir_print_ptr_cast_src(IrPrintSrc *irp, IrInstSrcPtrCast *instruction) {2031static void ir_print_ptr_cast_src(IrPrintSrc *irp, Stage1ZirInstPtrCast *instruction) {
2032 fprintf(irp->f, "@ptrCast(");2032 fprintf(irp->f, "@ptrCast(");
2033 if (instruction->dest_type) {2033 if (instruction->dest_type) {
2034 ir_print_other_inst_src(irp, instruction->dest_type);2034 ir_print_other_inst_src(irp, instruction->dest_type);
...@@ -2038,51 +2038,51 @@ static void ir_print_ptr_cast_src(IrPrintSrc *irp, IrInstSrcPtrCast *instruction...@@ -2038,51 +2038,51 @@ static void ir_print_ptr_cast_src(IrPrintSrc *irp, IrInstSrcPtrCast *instruction
2038 fprintf(irp->f, ")");2038 fprintf(irp->f, ")");
2039}2039}
20402040
2041static void ir_print_ptr_cast_gen(IrPrintGen *irp, IrInstGenPtrCast *instruction) {2041static void ir_print_ptr_cast_gen(IrPrintGen *irp, Stage1AirInstPtrCast *instruction) {
2042 fprintf(irp->f, "@ptrCast(");2042 fprintf(irp->f, "@ptrCast(");
2043 ir_print_other_inst_gen(irp, instruction->ptr);2043 ir_print_other_inst_gen(irp, instruction->ptr);
2044 fprintf(irp->f, ")");2044 fprintf(irp->f, ")");
2045}2045}
20462046
2047static void ir_print_implicit_cast(IrPrintSrc *irp, IrInstSrcImplicitCast *instruction) {2047static void ir_print_implicit_cast(IrPrintSrc *irp, Stage1ZirInstImplicitCast *instruction) {
2048 fprintf(irp->f, "@implicitCast(");2048 fprintf(irp->f, "@implicitCast(");
2049 ir_print_other_inst_src(irp, instruction->operand);2049 ir_print_other_inst_src(irp, instruction->operand);
2050 fprintf(irp->f, ")result=");2050 fprintf(irp->f, ")result=");
2051 ir_print_result_loc(irp, &instruction->result_loc_cast->base);2051 ir_print_result_loc(irp, &instruction->result_loc_cast->base);
2052}2052}
20532053
2054static void ir_print_bit_cast_src(IrPrintSrc *irp, IrInstSrcBitCast *instruction) {2054static void ir_print_bit_cast_src(IrPrintSrc *irp, Stage1ZirInstBitCast *instruction) {
2055 fprintf(irp->f, "@bitCast(");2055 fprintf(irp->f, "@bitCast(");
2056 ir_print_other_inst_src(irp, instruction->operand);2056 ir_print_other_inst_src(irp, instruction->operand);
2057 fprintf(irp->f, ")result=");2057 fprintf(irp->f, ")result=");
2058 ir_print_result_loc(irp, &instruction->result_loc_bit_cast->base);2058 ir_print_result_loc(irp, &instruction->result_loc_bit_cast->base);
2059}2059}
20602060
2061static void ir_print_bit_cast_gen(IrPrintGen *irp, IrInstGenBitCast *instruction) {2061static void ir_print_bit_cast_gen(IrPrintGen *irp, Stage1AirInstBitCast *instruction) {
2062 fprintf(irp->f, "@bitCast(");2062 fprintf(irp->f, "@bitCast(");
2063 ir_print_other_inst_gen(irp, instruction->operand);2063 ir_print_other_inst_gen(irp, instruction->operand);
2064 fprintf(irp->f, ")");2064 fprintf(irp->f, ")");
2065}2065}
20662066
2067static void ir_print_widen_or_shorten(IrPrintGen *irp, IrInstGenWidenOrShorten *instruction) {2067static void ir_print_widen_or_shorten(IrPrintGen *irp, Stage1AirInstWidenOrShorten *instruction) {
2068 fprintf(irp->f, "WidenOrShorten(");2068 fprintf(irp->f, "WidenOrShorten(");
2069 ir_print_other_inst_gen(irp, instruction->target);2069 ir_print_other_inst_gen(irp, instruction->target);
2070 fprintf(irp->f, ")");2070 fprintf(irp->f, ")");
2071}2071}
20722072
2073static void ir_print_ptr_to_int(IrPrintSrc *irp, IrInstSrcPtrToInt *instruction) {2073static void ir_print_ptr_to_int(IrPrintSrc *irp, Stage1ZirInstPtrToInt *instruction) {
2074 fprintf(irp->f, "@ptrToInt(");2074 fprintf(irp->f, "@ptrToInt(");
2075 ir_print_other_inst_src(irp, instruction->target);2075 ir_print_other_inst_src(irp, instruction->target);
2076 fprintf(irp->f, ")");2076 fprintf(irp->f, ")");
2077}2077}
20782078
2079static void ir_print_ptr_to_int(IrPrintGen *irp, IrInstGenPtrToInt *instruction) {2079static void ir_print_ptr_to_int(IrPrintGen *irp, Stage1AirInstPtrToInt *instruction) {
2080 fprintf(irp->f, "@ptrToInt(");2080 fprintf(irp->f, "@ptrToInt(");
2081 ir_print_other_inst_gen(irp, instruction->target);2081 ir_print_other_inst_gen(irp, instruction->target);
2082 fprintf(irp->f, ")");2082 fprintf(irp->f, ")");
2083}2083}
20842084
2085static void ir_print_int_to_ptr(IrPrintSrc *irp, IrInstSrcIntToPtr *instruction) {2085static void ir_print_int_to_ptr(IrPrintSrc *irp, Stage1ZirInstIntToPtr *instruction) {
2086 fprintf(irp->f, "@intToPtr(");2086 fprintf(irp->f, "@intToPtr(");
2087 ir_print_other_inst_src(irp, instruction->dest_type);2087 ir_print_other_inst_src(irp, instruction->dest_type);
2088 fprintf(irp->f, ",");2088 fprintf(irp->f, ",");
...@@ -2090,13 +2090,13 @@ static void ir_print_int_to_ptr(IrPrintSrc *irp, IrInstSrcIntToPtr *instruction)...@@ -2090,13 +2090,13 @@ static void ir_print_int_to_ptr(IrPrintSrc *irp, IrInstSrcIntToPtr *instruction)
2090 fprintf(irp->f, ")");2090 fprintf(irp->f, ")");
2091}2091}
20922092
2093static void ir_print_int_to_ptr(IrPrintGen *irp, IrInstGenIntToPtr *instruction) {2093static void ir_print_int_to_ptr(IrPrintGen *irp, Stage1AirInstIntToPtr *instruction) {
2094 fprintf(irp->f, "@intToPtr(");2094 fprintf(irp->f, "@intToPtr(");
2095 ir_print_other_inst_gen(irp, instruction->target);2095 ir_print_other_inst_gen(irp, instruction->target);
2096 fprintf(irp->f, ")");2096 fprintf(irp->f, ")");
2097}2097}
20982098
2099static void ir_print_int_to_enum(IrPrintSrc *irp, IrInstSrcIntToEnum *instruction) {2099static void ir_print_int_to_enum(IrPrintSrc *irp, Stage1ZirInstIntToEnum *instruction) {
2100 fprintf(irp->f, "@intToEnum(");2100 fprintf(irp->f, "@intToEnum(");
2101 ir_print_other_inst_src(irp, instruction->dest_type);2101 ir_print_other_inst_src(irp, instruction->dest_type);
2102 fprintf(irp->f, ",");2102 fprintf(irp->f, ",");
...@@ -2104,19 +2104,19 @@ static void ir_print_int_to_enum(IrPrintSrc *irp, IrInstSrcIntToEnum *instructio...@@ -2104,19 +2104,19 @@ static void ir_print_int_to_enum(IrPrintSrc *irp, IrInstSrcIntToEnum *instructio
2104 fprintf(irp->f, ")");2104 fprintf(irp->f, ")");
2105}2105}
21062106
2107static void ir_print_int_to_enum(IrPrintGen *irp, IrInstGenIntToEnum *instruction) {2107static void ir_print_int_to_enum(IrPrintGen *irp, Stage1AirInstIntToEnum *instruction) {
2108 fprintf(irp->f, "@intToEnum(");2108 fprintf(irp->f, "@intToEnum(");
2109 ir_print_other_inst_gen(irp, instruction->target);2109 ir_print_other_inst_gen(irp, instruction->target);
2110 fprintf(irp->f, ")");2110 fprintf(irp->f, ")");
2111}2111}
21122112
2113static void ir_print_enum_to_int(IrPrintSrc *irp, IrInstSrcEnumToInt *instruction) {2113static void ir_print_enum_to_int(IrPrintSrc *irp, Stage1ZirInstEnumToInt *instruction) {
2114 fprintf(irp->f, "@enumToInt(");2114 fprintf(irp->f, "@enumToInt(");
2115 ir_print_other_inst_src(irp, instruction->target);2115 ir_print_other_inst_src(irp, instruction->target);
2116 fprintf(irp->f, ")");2116 fprintf(irp->f, ")");
2117}2117}
21182118
2119static void ir_print_check_runtime_scope(IrPrintSrc *irp, IrInstSrcCheckRuntimeScope *instruction) {2119static void ir_print_check_runtime_scope(IrPrintSrc *irp, Stage1ZirInstCheckRuntimeScope *instruction) {
2120 fprintf(irp->f, "@checkRuntimeScope(");2120 fprintf(irp->f, "@checkRuntimeScope(");
2121 ir_print_other_inst_src(irp, instruction->scope_is_comptime);2121 ir_print_other_inst_src(irp, instruction->scope_is_comptime);
2122 fprintf(irp->f, ",");2122 fprintf(irp->f, ",");
...@@ -2124,49 +2124,49 @@ static void ir_print_check_runtime_scope(IrPrintSrc *irp, IrInstSrcCheckRuntimeS...@@ -2124,49 +2124,49 @@ static void ir_print_check_runtime_scope(IrPrintSrc *irp, IrInstSrcCheckRuntimeS
2124 fprintf(irp->f, ")");2124 fprintf(irp->f, ")");
2125}2125}
21262126
2127static void ir_print_array_to_vector(IrPrintGen *irp, IrInstGenArrayToVector *instruction) {2127static void ir_print_array_to_vector(IrPrintGen *irp, Stage1AirInstArrayToVector *instruction) {
2128 fprintf(irp->f, "ArrayToVector(");2128 fprintf(irp->f, "ArrayToVector(");
2129 ir_print_other_inst_gen(irp, instruction->array);2129 ir_print_other_inst_gen(irp, instruction->array);
2130 fprintf(irp->f, ")");2130 fprintf(irp->f, ")");
2131}2131}
21322132
2133static void ir_print_vector_to_array(IrPrintGen *irp, IrInstGenVectorToArray *instruction) {2133static void ir_print_vector_to_array(IrPrintGen *irp, Stage1AirInstVectorToArray *instruction) {
2134 fprintf(irp->f, "VectorToArray(");2134 fprintf(irp->f, "VectorToArray(");
2135 ir_print_other_inst_gen(irp, instruction->vector);2135 ir_print_other_inst_gen(irp, instruction->vector);
2136 fprintf(irp->f, ")result=");2136 fprintf(irp->f, ")result=");
2137 ir_print_other_inst_gen(irp, instruction->result_loc);2137 ir_print_other_inst_gen(irp, instruction->result_loc);
2138}2138}
21392139
2140static void ir_print_ptr_of_array_to_slice(IrPrintGen *irp, IrInstGenPtrOfArrayToSlice *instruction) {2140static void ir_print_ptr_of_array_to_slice(IrPrintGen *irp, Stage1AirInstPtrOfArrayToSlice *instruction) {
2141 fprintf(irp->f, "PtrOfArrayToSlice(");2141 fprintf(irp->f, "PtrOfArrayToSlice(");
2142 ir_print_other_inst_gen(irp, instruction->operand);2142 ir_print_other_inst_gen(irp, instruction->operand);
2143 fprintf(irp->f, ")result=");2143 fprintf(irp->f, ")result=");
2144 ir_print_other_inst_gen(irp, instruction->result_loc);2144 ir_print_other_inst_gen(irp, instruction->result_loc);
2145}2145}
21462146
2147static void ir_print_assert_zero(IrPrintGen *irp, IrInstGenAssertZero *instruction) {2147static void ir_print_assert_zero(IrPrintGen *irp, Stage1AirInstAssertZero *instruction) {
2148 fprintf(irp->f, "AssertZero(");2148 fprintf(irp->f, "AssertZero(");
2149 ir_print_other_inst_gen(irp, instruction->target);2149 ir_print_other_inst_gen(irp, instruction->target);
2150 fprintf(irp->f, ")");2150 fprintf(irp->f, ")");
2151}2151}
21522152
2153static void ir_print_assert_non_null(IrPrintGen *irp, IrInstGenAssertNonNull *instruction) {2153static void ir_print_assert_non_null(IrPrintGen *irp, Stage1AirInstAssertNonNull *instruction) {
2154 fprintf(irp->f, "AssertNonNull(");2154 fprintf(irp->f, "AssertNonNull(");
2155 ir_print_other_inst_gen(irp, instruction->target);2155 ir_print_other_inst_gen(irp, instruction->target);
2156 fprintf(irp->f, ")");2156 fprintf(irp->f, ")");
2157}2157}
21582158
2159static void ir_print_alloca_src(IrPrintSrc *irp, IrInstSrcAlloca *instruction) {2159static void ir_print_alloca_src(IrPrintSrc *irp, Stage1ZirInstAlloca *instruction) {
2160 fprintf(irp->f, "Alloca(align=");2160 fprintf(irp->f, "Alloca(align=");
2161 ir_print_other_inst_src(irp, instruction->align);2161 ir_print_other_inst_src(irp, instruction->align);
2162 fprintf(irp->f, ",name=%s)", instruction->name_hint);2162 fprintf(irp->f, ",name=%s)", instruction->name_hint);
2163}2163}
21642164
2165static void ir_print_alloca_gen(IrPrintGen *irp, IrInstGenAlloca *instruction) {2165static void ir_print_alloca_gen(IrPrintGen *irp, Stage1AirInstAlloca *instruction) {
2166 fprintf(irp->f, "Alloca(align=%" PRIu32 ",name=%s)", instruction->align, instruction->name_hint);2166 fprintf(irp->f, "Alloca(align=%" PRIu32 ",name=%s)", instruction->align, instruction->name_hint);
2167}2167}
21682168
2169static void ir_print_end_expr(IrPrintSrc *irp, IrInstSrcEndExpr *instruction) {2169static void ir_print_end_expr(IrPrintSrc *irp, Stage1ZirInstEndExpr *instruction) {
2170 fprintf(irp->f, "EndExpr(result=");2170 fprintf(irp->f, "EndExpr(result=");
2171 ir_print_result_loc(irp, instruction->result_loc);2171 ir_print_result_loc(irp, instruction->result_loc);
2172 fprintf(irp->f, ",value=");2172 fprintf(irp->f, ",value=");
...@@ -2174,27 +2174,27 @@ static void ir_print_end_expr(IrPrintSrc *irp, IrInstSrcEndExpr *instruction) {...@@ -2174,27 +2174,27 @@ static void ir_print_end_expr(IrPrintSrc *irp, IrInstSrcEndExpr *instruction) {
2174 fprintf(irp->f, ")");2174 fprintf(irp->f, ")");
2175}2175}
21762176
2177static void ir_print_int_to_err(IrPrintSrc *irp, IrInstSrcIntToErr *instruction) {2177static void ir_print_int_to_err(IrPrintSrc *irp, Stage1ZirInstIntToErr *instruction) {
2178 fprintf(irp->f, "inttoerr ");2178 fprintf(irp->f, "inttoerr ");
2179 ir_print_other_inst_src(irp, instruction->target);2179 ir_print_other_inst_src(irp, instruction->target);
2180}2180}
21812181
2182static void ir_print_int_to_err(IrPrintGen *irp, IrInstGenIntToErr *instruction) {2182static void ir_print_int_to_err(IrPrintGen *irp, Stage1AirInstIntToErr *instruction) {
2183 fprintf(irp->f, "inttoerr ");2183 fprintf(irp->f, "inttoerr ");
2184 ir_print_other_inst_gen(irp, instruction->target);2184 ir_print_other_inst_gen(irp, instruction->target);
2185}2185}
21862186
2187static void ir_print_err_to_int(IrPrintSrc *irp, IrInstSrcErrToInt *instruction) {2187static void ir_print_err_to_int(IrPrintSrc *irp, Stage1ZirInstErrToInt *instruction) {
2188 fprintf(irp->f, "errtoint ");2188 fprintf(irp->f, "errtoint ");
2189 ir_print_other_inst_src(irp, instruction->target);2189 ir_print_other_inst_src(irp, instruction->target);
2190}2190}
21912191
2192static void ir_print_err_to_int(IrPrintGen *irp, IrInstGenErrToInt *instruction) {2192static void ir_print_err_to_int(IrPrintGen *irp, Stage1AirInstErrToInt *instruction) {
2193 fprintf(irp->f, "errtoint ");2193 fprintf(irp->f, "errtoint ");
2194 ir_print_other_inst_gen(irp, instruction->target);2194 ir_print_other_inst_gen(irp, instruction->target);
2195}2195}
21962196
2197static void ir_print_check_switch_prongs(IrPrintSrc *irp, IrInstSrcCheckSwitchProngs *instruction,2197static void ir_print_check_switch_prongs(IrPrintSrc *irp, Stage1ZirInstCheckSwitchProngs *instruction,
2198 bool have_underscore_prong)2198 bool have_underscore_prong)
2199{2199{
2200 fprintf(irp->f, "@checkSwitchProngs(");2200 fprintf(irp->f, "@checkSwitchProngs(");
...@@ -2213,28 +2213,28 @@ static void ir_print_check_switch_prongs(IrPrintSrc *irp, IrInstSrcCheckSwitchPr...@@ -2213,28 +2213,28 @@ static void ir_print_check_switch_prongs(IrPrintSrc *irp, IrInstSrcCheckSwitchPr
2213 fprintf(irp->f, " _:%s", have_under_str);2213 fprintf(irp->f, " _:%s", have_under_str);
2214}2214}
22152215
2216static void ir_print_check_statement_is_void(IrPrintSrc *irp, IrInstSrcCheckStatementIsVoid *instruction) {2216static void ir_print_check_statement_is_void(IrPrintSrc *irp, Stage1ZirInstCheckStatementIsVoid *instruction) {
2217 fprintf(irp->f, "@checkStatementIsVoid(");2217 fprintf(irp->f, "@checkStatementIsVoid(");
2218 ir_print_other_inst_src(irp, instruction->statement_value);2218 ir_print_other_inst_src(irp, instruction->statement_value);
2219 fprintf(irp->f, ")");2219 fprintf(irp->f, ")");
2220}2220}
22212221
2222static void ir_print_type_name(IrPrintSrc *irp, IrInstSrcTypeName *instruction) {2222static void ir_print_type_name(IrPrintSrc *irp, Stage1ZirInstTypeName *instruction) {
2223 fprintf(irp->f, "typename ");2223 fprintf(irp->f, "typename ");
2224 ir_print_other_inst_src(irp, instruction->type_value);2224 ir_print_other_inst_src(irp, instruction->type_value);
2225}2225}
22262226
2227static void ir_print_tag_name(IrPrintSrc *irp, IrInstSrcTagName *instruction) {2227static void ir_print_tag_name(IrPrintSrc *irp, Stage1ZirInstTagName *instruction) {
2228 fprintf(irp->f, "tagname ");2228 fprintf(irp->f, "tagname ");
2229 ir_print_other_inst_src(irp, instruction->target);2229 ir_print_other_inst_src(irp, instruction->target);
2230}2230}
22312231
2232static void ir_print_tag_name(IrPrintGen *irp, IrInstGenTagName *instruction) {2232static void ir_print_tag_name(IrPrintGen *irp, Stage1AirInstTagName *instruction) {
2233 fprintf(irp->f, "tagname ");2233 fprintf(irp->f, "tagname ");
2234 ir_print_other_inst_gen(irp, instruction->target);2234 ir_print_other_inst_gen(irp, instruction->target);
2235}2235}
22362236
2237static void ir_print_ptr_type(IrPrintSrc *irp, IrInstSrcPtrType *instruction) {2237static void ir_print_ptr_type(IrPrintSrc *irp, Stage1ZirInstPtrType *instruction) {
2238 fprintf(irp->f, "&");2238 fprintf(irp->f, "&");
2239 if (instruction->align_value != nullptr) {2239 if (instruction->align_value != nullptr) {
2240 fprintf(irp->f, "align(");2240 fprintf(irp->f, "align(");
...@@ -2248,7 +2248,7 @@ static void ir_print_ptr_type(IrPrintSrc *irp, IrInstSrcPtrType *instruction) {...@@ -2248,7 +2248,7 @@ static void ir_print_ptr_type(IrPrintSrc *irp, IrInstSrcPtrType *instruction) {
2248 ir_print_other_inst_src(irp, instruction->child_type);2248 ir_print_other_inst_src(irp, instruction->child_type);
2249}2249}
22502250
2251static void ir_print_ptr_type_simple(IrPrintSrc *irp, IrInstSrcPtrTypeSimple *instruction,2251static void ir_print_ptr_type_simple(IrPrintSrc *irp, Stage1ZirInstPtrTypeSimple *instruction,
2252 bool is_const)2252 bool is_const)
2253{2253{
2254 fprintf(irp->f, "&");2254 fprintf(irp->f, "&");
...@@ -2257,24 +2257,24 @@ static void ir_print_ptr_type_simple(IrPrintSrc *irp, IrInstSrcPtrTypeSimple *in...@@ -2257,24 +2257,24 @@ static void ir_print_ptr_type_simple(IrPrintSrc *irp, IrInstSrcPtrTypeSimple *in
2257 ir_print_other_inst_src(irp, instruction->child_type);2257 ir_print_other_inst_src(irp, instruction->child_type);
2258}2258}
22592259
2260static void ir_print_decl_ref(IrPrintSrc *irp, IrInstSrcDeclRef *instruction) {2260static void ir_print_decl_ref(IrPrintSrc *irp, Stage1ZirInstDeclRef *instruction) {
2261 const char *ptr_str = (instruction->lval != LValNone) ? "ptr " : "";2261 const char *ptr_str = (instruction->lval != LValNone) ? "ptr " : "";
2262 fprintf(irp->f, "declref %s%s", ptr_str, buf_ptr(instruction->tld->name));2262 fprintf(irp->f, "declref %s%s", ptr_str, buf_ptr(instruction->tld->name));
2263}2263}
22642264
2265static void ir_print_panic(IrPrintSrc *irp, IrInstSrcPanic *instruction) {2265static void ir_print_panic(IrPrintSrc *irp, Stage1ZirInstPanic *instruction) {
2266 fprintf(irp->f, "@panic(");2266 fprintf(irp->f, "@panic(");
2267 ir_print_other_inst_src(irp, instruction->msg);2267 ir_print_other_inst_src(irp, instruction->msg);
2268 fprintf(irp->f, ")");2268 fprintf(irp->f, ")");
2269}2269}
22702270
2271static void ir_print_panic(IrPrintGen *irp, IrInstGenPanic *instruction) {2271static void ir_print_panic(IrPrintGen *irp, Stage1AirInstPanic *instruction) {
2272 fprintf(irp->f, "@panic(");2272 fprintf(irp->f, "@panic(");
2273 ir_print_other_inst_gen(irp, instruction->msg);2273 ir_print_other_inst_gen(irp, instruction->msg);
2274 fprintf(irp->f, ")");2274 fprintf(irp->f, ")");
2275}2275}
22762276
2277static void ir_print_field_parent_ptr(IrPrintSrc *irp, IrInstSrcFieldParentPtr *instruction) {2277static void ir_print_field_parent_ptr(IrPrintSrc *irp, Stage1ZirInstFieldParentPtr *instruction) {
2278 fprintf(irp->f, "@fieldParentPtr(");2278 fprintf(irp->f, "@fieldParentPtr(");
2279 ir_print_other_inst_src(irp, instruction->type_value);2279 ir_print_other_inst_src(irp, instruction->type_value);
2280 fprintf(irp->f, ",");2280 fprintf(irp->f, ",");
...@@ -2284,13 +2284,13 @@ static void ir_print_field_parent_ptr(IrPrintSrc *irp, IrInstSrcFieldParentPtr *...@@ -2284,13 +2284,13 @@ static void ir_print_field_parent_ptr(IrPrintSrc *irp, IrInstSrcFieldParentPtr *
2284 fprintf(irp->f, ")");2284 fprintf(irp->f, ")");
2285}2285}
22862286
2287static void ir_print_field_parent_ptr(IrPrintGen *irp, IrInstGenFieldParentPtr *instruction) {2287static void ir_print_field_parent_ptr(IrPrintGen *irp, Stage1AirInstFieldParentPtr *instruction) {
2288 fprintf(irp->f, "@fieldParentPtr(%s,", buf_ptr(instruction->field->name));2288 fprintf(irp->f, "@fieldParentPtr(%s,", buf_ptr(instruction->field->name));
2289 ir_print_other_inst_gen(irp, instruction->field_ptr);2289 ir_print_other_inst_gen(irp, instruction->field_ptr);
2290 fprintf(irp->f, ")");2290 fprintf(irp->f, ")");
2291}2291}
22922292
2293static void ir_print_offset_of(IrPrintSrc *irp, IrInstSrcOffsetOf *instruction) {2293static void ir_print_offset_of(IrPrintSrc *irp, Stage1ZirInstOffsetOf *instruction) {
2294 fprintf(irp->f, "@offset_of(");2294 fprintf(irp->f, "@offset_of(");
2295 ir_print_other_inst_src(irp, instruction->type_value);2295 ir_print_other_inst_src(irp, instruction->type_value);
2296 fprintf(irp->f, ",");2296 fprintf(irp->f, ",");
...@@ -2298,7 +2298,7 @@ static void ir_print_offset_of(IrPrintSrc *irp, IrInstSrcOffsetOf *instruction)...@@ -2298,7 +2298,7 @@ static void ir_print_offset_of(IrPrintSrc *irp, IrInstSrcOffsetOf *instruction)
2298 fprintf(irp->f, ")");2298 fprintf(irp->f, ")");
2299}2299}
23002300
2301static void ir_print_bit_offset_of(IrPrintSrc *irp, IrInstSrcBitOffsetOf *instruction) {2301static void ir_print_bit_offset_of(IrPrintSrc *irp, Stage1ZirInstBitOffsetOf *instruction) {
2302 fprintf(irp->f, "@bit_offset_of(");2302 fprintf(irp->f, "@bit_offset_of(");
2303 ir_print_other_inst_src(irp, instruction->type_value);2303 ir_print_other_inst_src(irp, instruction->type_value);
2304 fprintf(irp->f, ",");2304 fprintf(irp->f, ",");
...@@ -2306,19 +2306,19 @@ static void ir_print_bit_offset_of(IrPrintSrc *irp, IrInstSrcBitOffsetOf *instru...@@ -2306,19 +2306,19 @@ static void ir_print_bit_offset_of(IrPrintSrc *irp, IrInstSrcBitOffsetOf *instru
2306 fprintf(irp->f, ")");2306 fprintf(irp->f, ")");
2307}2307}
23082308
2309static void ir_print_type_info(IrPrintSrc *irp, IrInstSrcTypeInfo *instruction) {2309static void ir_print_type_info(IrPrintSrc *irp, Stage1ZirInstTypeInfo *instruction) {
2310 fprintf(irp->f, "@typeInfo(");2310 fprintf(irp->f, "@typeInfo(");
2311 ir_print_other_inst_src(irp, instruction->type_value);2311 ir_print_other_inst_src(irp, instruction->type_value);
2312 fprintf(irp->f, ")");2312 fprintf(irp->f, ")");
2313}2313}
23142314
2315static void ir_print_type(IrPrintSrc *irp, IrInstSrcType *instruction) {2315static void ir_print_type(IrPrintSrc *irp, Stage1ZirInstType *instruction) {
2316 fprintf(irp->f, "@Type(");2316 fprintf(irp->f, "@Type(");
2317 ir_print_other_inst_src(irp, instruction->type_info);2317 ir_print_other_inst_src(irp, instruction->type_info);
2318 fprintf(irp->f, ")");2318 fprintf(irp->f, ")");
2319}2319}
23202320
2321static void ir_print_has_field(IrPrintSrc *irp, IrInstSrcHasField *instruction) {2321static void ir_print_has_field(IrPrintSrc *irp, Stage1ZirInstHasField *instruction) {
2322 fprintf(irp->f, "@hasField(");2322 fprintf(irp->f, "@hasField(");
2323 ir_print_other_inst_src(irp, instruction->container_type);2323 ir_print_other_inst_src(irp, instruction->container_type);
2324 fprintf(irp->f, ",");2324 fprintf(irp->f, ",");
...@@ -2326,13 +2326,13 @@ static void ir_print_has_field(IrPrintSrc *irp, IrInstSrcHasField *instruction)...@@ -2326,13 +2326,13 @@ static void ir_print_has_field(IrPrintSrc *irp, IrInstSrcHasField *instruction)
2326 fprintf(irp->f, ")");2326 fprintf(irp->f, ")");
2327}2327}
23282328
2329static void ir_print_set_eval_branch_quota(IrPrintSrc *irp, IrInstSrcSetEvalBranchQuota *instruction) {2329static void ir_print_set_eval_branch_quota(IrPrintSrc *irp, Stage1ZirInstSetEvalBranchQuota *instruction) {
2330 fprintf(irp->f, "@setEvalBranchQuota(");2330 fprintf(irp->f, "@setEvalBranchQuota(");
2331 ir_print_other_inst_src(irp, instruction->new_quota);2331 ir_print_other_inst_src(irp, instruction->new_quota);
2332 fprintf(irp->f, ")");2332 fprintf(irp->f, ")");
2333}2333}
23342334
2335static void ir_print_align_cast(IrPrintSrc *irp, IrInstSrcAlignCast *instruction) {2335static void ir_print_align_cast(IrPrintSrc *irp, Stage1ZirInstAlignCast *instruction) {
2336 fprintf(irp->f, "@alignCast(");2336 fprintf(irp->f, "@alignCast(");
2337 ir_print_other_inst_src(irp, instruction->align_bytes);2337 ir_print_other_inst_src(irp, instruction->align_bytes);
2338 fprintf(irp->f, ",");2338 fprintf(irp->f, ",");
...@@ -2340,31 +2340,31 @@ static void ir_print_align_cast(IrPrintSrc *irp, IrInstSrcAlignCast *instruction...@@ -2340,31 +2340,31 @@ static void ir_print_align_cast(IrPrintSrc *irp, IrInstSrcAlignCast *instruction
2340 fprintf(irp->f, ")");2340 fprintf(irp->f, ")");
2341}2341}
23422342
2343static void ir_print_align_cast(IrPrintGen *irp, IrInstGenAlignCast *instruction) {2343static void ir_print_align_cast(IrPrintGen *irp, Stage1AirInstAlignCast *instruction) {
2344 fprintf(irp->f, "@alignCast(");2344 fprintf(irp->f, "@alignCast(");
2345 ir_print_other_inst_gen(irp, instruction->target);2345 ir_print_other_inst_gen(irp, instruction->target);
2346 fprintf(irp->f, ")");2346 fprintf(irp->f, ")");
2347}2347}
23482348
2349static void ir_print_resolve_result(IrPrintSrc *irp, IrInstSrcResolveResult *instruction) {2349static void ir_print_resolve_result(IrPrintSrc *irp, Stage1ZirInstResolveResult *instruction) {
2350 fprintf(irp->f, "ResolveResult(");2350 fprintf(irp->f, "ResolveResult(");
2351 ir_print_result_loc(irp, instruction->result_loc);2351 ir_print_result_loc(irp, instruction->result_loc);
2352 fprintf(irp->f, ")");2352 fprintf(irp->f, ")");
2353}2353}
23542354
2355static void ir_print_reset_result(IrPrintSrc *irp, IrInstSrcResetResult *instruction) {2355static void ir_print_reset_result(IrPrintSrc *irp, Stage1ZirInstResetResult *instruction) {
2356 fprintf(irp->f, "ResetResult(");2356 fprintf(irp->f, "ResetResult(");
2357 ir_print_result_loc(irp, instruction->result_loc);2357 ir_print_result_loc(irp, instruction->result_loc);
2358 fprintf(irp->f, ")");2358 fprintf(irp->f, ")");
2359}2359}
23602360
2361static void ir_print_set_align_stack(IrPrintSrc *irp, IrInstSrcSetAlignStack *instruction) {2361static void ir_print_set_align_stack(IrPrintSrc *irp, Stage1ZirInstSetAlignStack *instruction) {
2362 fprintf(irp->f, "@setAlignStack(");2362 fprintf(irp->f, "@setAlignStack(");
2363 ir_print_other_inst_src(irp, instruction->align_bytes);2363 ir_print_other_inst_src(irp, instruction->align_bytes);
2364 fprintf(irp->f, ")");2364 fprintf(irp->f, ")");
2365}2365}
23662366
2367static void ir_print_arg_type(IrPrintSrc *irp, IrInstSrcArgType *instruction, bool allow_var) {2367static void ir_print_arg_type(IrPrintSrc *irp, Stage1ZirInstArgType *instruction, bool allow_var) {
2368 fprintf(irp->f, "@ArgType(");2368 fprintf(irp->f, "@ArgType(");
2369 ir_print_other_inst_src(irp, instruction->fn_type);2369 ir_print_other_inst_src(irp, instruction->fn_type);
2370 fprintf(irp->f, ",");2370 fprintf(irp->f, ",");
...@@ -2378,7 +2378,7 @@ static void ir_print_arg_type(IrPrintSrc *irp, IrInstSrcArgType *instruction, bo...@@ -2378,7 +2378,7 @@ static void ir_print_arg_type(IrPrintSrc *irp, IrInstSrcArgType *instruction, bo
2378 fprintf(irp->f, ")");2378 fprintf(irp->f, ")");
2379}2379}
23802380
2381static void ir_print_export(IrPrintSrc *irp, IrInstSrcExport *instruction) {2381static void ir_print_export(IrPrintSrc *irp, Stage1ZirInstExport *instruction) {
2382 fprintf(irp->f, "@export(");2382 fprintf(irp->f, "@export(");
2383 ir_print_other_inst_src(irp, instruction->target);2383 ir_print_other_inst_src(irp, instruction->target);
2384 fprintf(irp->f, ",");2384 fprintf(irp->f, ",");
...@@ -2386,11 +2386,11 @@ static void ir_print_export(IrPrintSrc *irp, IrInstSrcExport *instruction) {...@@ -2386,11 +2386,11 @@ static void ir_print_export(IrPrintSrc *irp, IrInstSrcExport *instruction) {
2386 fprintf(irp->f, ")");2386 fprintf(irp->f, ")");
2387}2387}
23882388
2389static void ir_print_extern(IrPrintGen *irp, IrInstGenExtern *instruction) {2389static void ir_print_extern(IrPrintGen *irp, Stage1AirInstExtern *instruction) {
2390 fprintf(irp->f, "@extern(...)");2390 fprintf(irp->f, "@extern(...)");
2391}2391}
23922392
2393static void ir_print_extern(IrPrintSrc *irp, IrInstSrcExtern *instruction) {2393static void ir_print_extern(IrPrintSrc *irp, Stage1ZirInstExtern *instruction) {
2394 fprintf(irp->f, "@extern(");2394 fprintf(irp->f, "@extern(");
2395 ir_print_other_inst_src(irp, instruction->type);2395 ir_print_other_inst_src(irp, instruction->type);
2396 fprintf(irp->f, ",");2396 fprintf(irp->f, ",");
...@@ -2398,7 +2398,7 @@ static void ir_print_extern(IrPrintSrc *irp, IrInstSrcExtern *instruction) {...@@ -2398,7 +2398,7 @@ static void ir_print_extern(IrPrintSrc *irp, IrInstSrcExtern *instruction) {
2398 fprintf(irp->f, ")");2398 fprintf(irp->f, ")");
2399}2399}
24002400
2401static void ir_print_error_return_trace(IrPrintSrc *irp, IrInstSrcErrorReturnTrace *instruction) {2401static void ir_print_error_return_trace(IrPrintSrc *irp, Stage1ZirInstErrorReturnTrace *instruction) {
2402 fprintf(irp->f, "@errorReturnTrace(");2402 fprintf(irp->f, "@errorReturnTrace(");
2403 switch (instruction->optional) {2403 switch (instruction->optional) {
2404 case IrInstErrorReturnTraceNull:2404 case IrInstErrorReturnTraceNull:
...@@ -2411,7 +2411,7 @@ static void ir_print_error_return_trace(IrPrintSrc *irp, IrInstSrcErrorReturnTra...@@ -2411,7 +2411,7 @@ static void ir_print_error_return_trace(IrPrintSrc *irp, IrInstSrcErrorReturnTra
2411 fprintf(irp->f, ")");2411 fprintf(irp->f, ")");
2412}2412}
24132413
2414static void ir_print_error_return_trace(IrPrintGen *irp, IrInstGenErrorReturnTrace *instruction) {2414static void ir_print_error_return_trace(IrPrintGen *irp, Stage1AirInstErrorReturnTrace *instruction) {
2415 fprintf(irp->f, "@errorReturnTrace(");2415 fprintf(irp->f, "@errorReturnTrace(");
2416 switch (instruction->optional) {2416 switch (instruction->optional) {
2417 case IrInstErrorReturnTraceNull:2417 case IrInstErrorReturnTraceNull:
...@@ -2424,13 +2424,13 @@ static void ir_print_error_return_trace(IrPrintGen *irp, IrInstGenErrorReturnTra...@@ -2424,13 +2424,13 @@ static void ir_print_error_return_trace(IrPrintGen *irp, IrInstGenErrorReturnTra
2424 fprintf(irp->f, ")");2424 fprintf(irp->f, ")");
2425}2425}
24262426
2427static void ir_print_error_union(IrPrintSrc *irp, IrInstSrcErrorUnion *instruction) {2427static void ir_print_error_union(IrPrintSrc *irp, Stage1ZirInstErrorUnion *instruction) {
2428 ir_print_other_inst_src(irp, instruction->err_set);2428 ir_print_other_inst_src(irp, instruction->err_set);
2429 fprintf(irp->f, "!");2429 fprintf(irp->f, "!");
2430 ir_print_other_inst_src(irp, instruction->payload);2430 ir_print_other_inst_src(irp, instruction->payload);
2431}2431}
24322432
2433static void ir_print_atomic_rmw(IrPrintSrc *irp, IrInstSrcAtomicRmw *instruction) {2433static void ir_print_atomic_rmw(IrPrintSrc *irp, Stage1ZirInstAtomicRmw *instruction) {
2434 fprintf(irp->f, "@atomicRmw(");2434 fprintf(irp->f, "@atomicRmw(");
2435 ir_print_other_inst_src(irp, instruction->operand_type);2435 ir_print_other_inst_src(irp, instruction->operand_type);
2436 fprintf(irp->f, ",");2436 fprintf(irp->f, ",");
...@@ -2444,7 +2444,7 @@ static void ir_print_atomic_rmw(IrPrintSrc *irp, IrInstSrcAtomicRmw *instruction...@@ -2444,7 +2444,7 @@ static void ir_print_atomic_rmw(IrPrintSrc *irp, IrInstSrcAtomicRmw *instruction
2444 fprintf(irp->f, ")");2444 fprintf(irp->f, ")");
2445}2445}
24462446
2447static void ir_print_atomic_rmw(IrPrintGen *irp, IrInstGenAtomicRmw *instruction) {2447static void ir_print_atomic_rmw(IrPrintGen *irp, Stage1AirInstAtomicRmw *instruction) {
2448 fprintf(irp->f, "@atomicRmw(");2448 fprintf(irp->f, "@atomicRmw(");
2449 ir_print_other_inst_gen(irp, instruction->ptr);2449 ir_print_other_inst_gen(irp, instruction->ptr);
2450 fprintf(irp->f, ",[TODO print op],");2450 fprintf(irp->f, ",[TODO print op],");
...@@ -2452,7 +2452,7 @@ static void ir_print_atomic_rmw(IrPrintGen *irp, IrInstGenAtomicRmw *instruction...@@ -2452,7 +2452,7 @@ static void ir_print_atomic_rmw(IrPrintGen *irp, IrInstGenAtomicRmw *instruction
2452 fprintf(irp->f, ",%s)", atomic_order_str(instruction->ordering));2452 fprintf(irp->f, ",%s)", atomic_order_str(instruction->ordering));
2453}2453}
24542454
2455static void ir_print_atomic_load(IrPrintSrc *irp, IrInstSrcAtomicLoad *instruction) {2455static void ir_print_atomic_load(IrPrintSrc *irp, Stage1ZirInstAtomicLoad *instruction) {
2456 fprintf(irp->f, "@atomicLoad(");2456 fprintf(irp->f, "@atomicLoad(");
2457 ir_print_other_inst_src(irp, instruction->operand_type);2457 ir_print_other_inst_src(irp, instruction->operand_type);
2458 fprintf(irp->f, ",");2458 fprintf(irp->f, ",");
...@@ -2462,13 +2462,13 @@ static void ir_print_atomic_load(IrPrintSrc *irp, IrInstSrcAtomicLoad *instructi...@@ -2462,13 +2462,13 @@ static void ir_print_atomic_load(IrPrintSrc *irp, IrInstSrcAtomicLoad *instructi
2462 fprintf(irp->f, ")");2462 fprintf(irp->f, ")");
2463}2463}
24642464
2465static void ir_print_atomic_load(IrPrintGen *irp, IrInstGenAtomicLoad *instruction) {2465static void ir_print_atomic_load(IrPrintGen *irp, Stage1AirInstAtomicLoad *instruction) {
2466 fprintf(irp->f, "@atomicLoad(");2466 fprintf(irp->f, "@atomicLoad(");
2467 ir_print_other_inst_gen(irp, instruction->ptr);2467 ir_print_other_inst_gen(irp, instruction->ptr);
2468 fprintf(irp->f, ",%s)", atomic_order_str(instruction->ordering));2468 fprintf(irp->f, ",%s)", atomic_order_str(instruction->ordering));
2469}2469}
24702470
2471static void ir_print_atomic_store(IrPrintSrc *irp, IrInstSrcAtomicStore *instruction) {2471static void ir_print_atomic_store(IrPrintSrc *irp, Stage1ZirInstAtomicStore *instruction) {
2472 fprintf(irp->f, "@atomicStore(");2472 fprintf(irp->f, "@atomicStore(");
2473 ir_print_other_inst_src(irp, instruction->operand_type);2473 ir_print_other_inst_src(irp, instruction->operand_type);
2474 fprintf(irp->f, ",");2474 fprintf(irp->f, ",");
...@@ -2480,7 +2480,7 @@ static void ir_print_atomic_store(IrPrintSrc *irp, IrInstSrcAtomicStore *instruc...@@ -2480,7 +2480,7 @@ static void ir_print_atomic_store(IrPrintSrc *irp, IrInstSrcAtomicStore *instruc
2480 fprintf(irp->f, ")");2480 fprintf(irp->f, ")");
2481}2481}
24822482
2483static void ir_print_atomic_store(IrPrintGen *irp, IrInstGenAtomicStore *instruction) {2483static void ir_print_atomic_store(IrPrintGen *irp, Stage1AirInstAtomicStore *instruction) {
2484 fprintf(irp->f, "@atomicStore(");2484 fprintf(irp->f, "@atomicStore(");
2485 ir_print_other_inst_gen(irp, instruction->ptr);2485 ir_print_other_inst_gen(irp, instruction->ptr);
2486 fprintf(irp->f, ",");2486 fprintf(irp->f, ",");
...@@ -2489,33 +2489,33 @@ static void ir_print_atomic_store(IrPrintGen *irp, IrInstGenAtomicStore *instruc...@@ -2489,33 +2489,33 @@ static void ir_print_atomic_store(IrPrintGen *irp, IrInstGenAtomicStore *instruc
2489}2489}
24902490
24912491
2492static void ir_print_save_err_ret_addr(IrPrintSrc *irp, IrInstSrcSaveErrRetAddr *instruction) {2492static void ir_print_save_err_ret_addr(IrPrintSrc *irp, Stage1ZirInstSaveErrRetAddr *instruction) {
2493 fprintf(irp->f, "@saveErrRetAddr()");2493 fprintf(irp->f, "@saveErrRetAddr()");
2494}2494}
24952495
2496static void ir_print_save_err_ret_addr(IrPrintGen *irp, IrInstGenSaveErrRetAddr *instruction) {2496static void ir_print_save_err_ret_addr(IrPrintGen *irp, Stage1AirInstSaveErrRetAddr *instruction) {
2497 fprintf(irp->f, "@saveErrRetAddr()");2497 fprintf(irp->f, "@saveErrRetAddr()");
2498}2498}
24992499
2500static void ir_print_add_implicit_return_type(IrPrintSrc *irp, IrInstSrcAddImplicitReturnType *instruction) {2500static void ir_print_add_implicit_return_type(IrPrintSrc *irp, Stage1ZirInstAddImplicitReturnType *instruction) {
2501 fprintf(irp->f, "@addImplicitReturnType(");2501 fprintf(irp->f, "@addImplicitReturnType(");
2502 ir_print_other_inst_src(irp, instruction->value);2502 ir_print_other_inst_src(irp, instruction->value);
2503 fprintf(irp->f, ")");2503 fprintf(irp->f, ")");
2504}2504}
25052505
2506static void ir_print_float_op(IrPrintSrc *irp, IrInstSrcFloatOp *instruction) {2506static void ir_print_float_op(IrPrintSrc *irp, Stage1ZirInstFloatOp *instruction) {
2507 fprintf(irp->f, "@%s(", float_op_to_name(instruction->fn_id));2507 fprintf(irp->f, "@%s(", float_op_to_name(instruction->fn_id));
2508 ir_print_other_inst_src(irp, instruction->operand);2508 ir_print_other_inst_src(irp, instruction->operand);
2509 fprintf(irp->f, ")");2509 fprintf(irp->f, ")");
2510}2510}
25112511
2512static void ir_print_float_op(IrPrintGen *irp, IrInstGenFloatOp *instruction) {2512static void ir_print_float_op(IrPrintGen *irp, Stage1AirInstFloatOp *instruction) {
2513 fprintf(irp->f, "@%s(", float_op_to_name(instruction->fn_id));2513 fprintf(irp->f, "@%s(", float_op_to_name(instruction->fn_id));
2514 ir_print_other_inst_gen(irp, instruction->operand);2514 ir_print_other_inst_gen(irp, instruction->operand);
2515 fprintf(irp->f, ")");2515 fprintf(irp->f, ")");
2516}2516}
25172517
2518static void ir_print_mul_add(IrPrintSrc *irp, IrInstSrcMulAdd *instruction) {2518static void ir_print_mul_add(IrPrintSrc *irp, Stage1ZirInstMulAdd *instruction) {
2519 fprintf(irp->f, "@mulAdd(");2519 fprintf(irp->f, "@mulAdd(");
2520 ir_print_other_inst_src(irp, instruction->type_value);2520 ir_print_other_inst_src(irp, instruction->type_value);
2521 fprintf(irp->f, ",");2521 fprintf(irp->f, ",");
...@@ -2527,7 +2527,7 @@ static void ir_print_mul_add(IrPrintSrc *irp, IrInstSrcMulAdd *instruction) {...@@ -2527,7 +2527,7 @@ static void ir_print_mul_add(IrPrintSrc *irp, IrInstSrcMulAdd *instruction) {
2527 fprintf(irp->f, ")");2527 fprintf(irp->f, ")");
2528}2528}
25292529
2530static void ir_print_mul_add(IrPrintGen *irp, IrInstGenMulAdd *instruction) {2530static void ir_print_mul_add(IrPrintGen *irp, Stage1AirInstMulAdd *instruction) {
2531 fprintf(irp->f, "@mulAdd(");2531 fprintf(irp->f, "@mulAdd(");
2532 ir_print_other_inst_gen(irp, instruction->op1);2532 ir_print_other_inst_gen(irp, instruction->op1);
2533 fprintf(irp->f, ",");2533 fprintf(irp->f, ",");
...@@ -2537,7 +2537,7 @@ static void ir_print_mul_add(IrPrintGen *irp, IrInstGenMulAdd *instruction) {...@@ -2537,7 +2537,7 @@ static void ir_print_mul_add(IrPrintGen *irp, IrInstGenMulAdd *instruction) {
2537 fprintf(irp->f, ")");2537 fprintf(irp->f, ")");
2538}2538}
25392539
2540static void ir_print_decl_var_gen(IrPrintGen *irp, IrInstGenDeclVar *decl_var_instruction) {2540static void ir_print_decl_var_gen(IrPrintGen *irp, Stage1AirInstDeclVar *decl_var_instruction) {
2541 ZigVar *var = decl_var_instruction->var;2541 ZigVar *var = decl_var_instruction->var;
2542 const char *var_or_const = decl_var_instruction->var->gen_is_const ? "const" : "var";2542 const char *var_or_const = decl_var_instruction->var->gen_is_const ? "const" : "var";
2543 const char *name = decl_var_instruction->var->name;2543 const char *name = decl_var_instruction->var->name;
...@@ -2547,7 +2547,7 @@ static void ir_print_decl_var_gen(IrPrintGen *irp, IrInstGenDeclVar *decl_var_in...@@ -2547,7 +2547,7 @@ static void ir_print_decl_var_gen(IrPrintGen *irp, IrInstGenDeclVar *decl_var_in
2547 ir_print_other_inst_gen(irp, decl_var_instruction->var_ptr);2547 ir_print_other_inst_gen(irp, decl_var_instruction->var_ptr);
2548}2548}
25492549
2550static void ir_print_has_decl(IrPrintSrc *irp, IrInstSrcHasDecl *instruction) {2550static void ir_print_has_decl(IrPrintSrc *irp, Stage1ZirInstHasDecl *instruction) {
2551 fprintf(irp->f, "@hasDecl(");2551 fprintf(irp->f, "@hasDecl(");
2552 ir_print_other_inst_src(irp, instruction->container);2552 ir_print_other_inst_src(irp, instruction->container);
2553 fprintf(irp->f, ",");2553 fprintf(irp->f, ",");
...@@ -2555,11 +2555,11 @@ static void ir_print_has_decl(IrPrintSrc *irp, IrInstSrcHasDecl *instruction) {...@@ -2555,11 +2555,11 @@ static void ir_print_has_decl(IrPrintSrc *irp, IrInstSrcHasDecl *instruction) {
2555 fprintf(irp->f, ")");2555 fprintf(irp->f, ")");
2556}2556}
25572557
2558static void ir_print_undeclared_ident(IrPrintSrc *irp, IrInstSrcUndeclaredIdent *instruction) {2558static void ir_print_undeclared_ident(IrPrintSrc *irp, Stage1ZirInstUndeclaredIdent *instruction) {
2559 fprintf(irp->f, "@undeclaredIdent(%s)", buf_ptr(instruction->name));2559 fprintf(irp->f, "@undeclaredIdent(%s)", buf_ptr(instruction->name));
2560}2560}
25612561
2562static void ir_print_union_init_named_field(IrPrintSrc *irp, IrInstSrcUnionInitNamedField *instruction) {2562static void ir_print_union_init_named_field(IrPrintSrc *irp, Stage1ZirInstUnionInitNamedField *instruction) {
2563 fprintf(irp->f, "@unionInit(");2563 fprintf(irp->f, "@unionInit(");
2564 ir_print_other_inst_src(irp, instruction->union_type);2564 ir_print_other_inst_src(irp, instruction->union_type);
2565 fprintf(irp->f, ", ");2565 fprintf(irp->f, ", ");
...@@ -2571,33 +2571,33 @@ static void ir_print_union_init_named_field(IrPrintSrc *irp, IrInstSrcUnionInitN...@@ -2571,33 +2571,33 @@ static void ir_print_union_init_named_field(IrPrintSrc *irp, IrInstSrcUnionInitN
2571 fprintf(irp->f, ")");2571 fprintf(irp->f, ")");
2572}2572}
25732573
2574static void ir_print_suspend_begin(IrPrintSrc *irp, IrInstSrcSuspendBegin *instruction) {2574static void ir_print_suspend_begin(IrPrintSrc *irp, Stage1ZirInstSuspendBegin *instruction) {
2575 fprintf(irp->f, "@suspendBegin()");2575 fprintf(irp->f, "@suspendBegin()");
2576}2576}
25772577
2578static void ir_print_suspend_begin(IrPrintGen *irp, IrInstGenSuspendBegin *instruction) {2578static void ir_print_suspend_begin(IrPrintGen *irp, Stage1AirInstSuspendBegin *instruction) {
2579 fprintf(irp->f, "@suspendBegin()");2579 fprintf(irp->f, "@suspendBegin()");
2580}2580}
25812581
2582static void ir_print_suspend_finish(IrPrintSrc *irp, IrInstSrcSuspendFinish *instruction) {2582static void ir_print_suspend_finish(IrPrintSrc *irp, Stage1ZirInstSuspendFinish *instruction) {
2583 fprintf(irp->f, "@suspendFinish()");2583 fprintf(irp->f, "@suspendFinish()");
2584}2584}
25852585
2586static void ir_print_suspend_finish(IrPrintGen *irp, IrInstGenSuspendFinish *instruction) {2586static void ir_print_suspend_finish(IrPrintGen *irp, Stage1AirInstSuspendFinish *instruction) {
2587 fprintf(irp->f, "@suspendFinish()");2587 fprintf(irp->f, "@suspendFinish()");
2588}2588}
25892589
2590static void ir_print_resume(IrPrintSrc *irp, IrInstSrcResume *instruction) {2590static void ir_print_resume(IrPrintSrc *irp, Stage1ZirInstResume *instruction) {
2591 fprintf(irp->f, "resume ");2591 fprintf(irp->f, "resume ");
2592 ir_print_other_inst_src(irp, instruction->frame);2592 ir_print_other_inst_src(irp, instruction->frame);
2593}2593}
25942594
2595static void ir_print_resume(IrPrintGen *irp, IrInstGenResume *instruction) {2595static void ir_print_resume(IrPrintGen *irp, Stage1AirInstResume *instruction) {
2596 fprintf(irp->f, "resume ");2596 fprintf(irp->f, "resume ");
2597 ir_print_other_inst_gen(irp, instruction->frame);2597 ir_print_other_inst_gen(irp, instruction->frame);
2598}2598}
25992599
2600static void ir_print_await_src(IrPrintSrc *irp, IrInstSrcAwait *instruction) {2600static void ir_print_await_src(IrPrintSrc *irp, Stage1ZirInstAwait *instruction) {
2601 fprintf(irp->f, "@await(");2601 fprintf(irp->f, "@await(");
2602 ir_print_other_inst_src(irp, instruction->frame);2602 ir_print_other_inst_src(irp, instruction->frame);
2603 fprintf(irp->f, ",");2603 fprintf(irp->f, ",");
...@@ -2605,7 +2605,7 @@ static void ir_print_await_src(IrPrintSrc *irp, IrInstSrcAwait *instruction) {...@@ -2605,7 +2605,7 @@ static void ir_print_await_src(IrPrintSrc *irp, IrInstSrcAwait *instruction) {
2605 fprintf(irp->f, ")");2605 fprintf(irp->f, ")");
2606}2606}
26072607
2608static void ir_print_await_gen(IrPrintGen *irp, IrInstGenAwait *instruction) {2608static void ir_print_await_gen(IrPrintGen *irp, Stage1AirInstAwait *instruction) {
2609 fprintf(irp->f, "@await(");2609 fprintf(irp->f, "@await(");
2610 ir_print_other_inst_gen(irp, instruction->frame);2610 ir_print_other_inst_gen(irp, instruction->frame);
2611 fprintf(irp->f, ",");2611 fprintf(irp->f, ",");
...@@ -2613,31 +2613,31 @@ static void ir_print_await_gen(IrPrintGen *irp, IrInstGenAwait *instruction) {...@@ -2613,31 +2613,31 @@ static void ir_print_await_gen(IrPrintGen *irp, IrInstGenAwait *instruction) {
2613 fprintf(irp->f, ")");2613 fprintf(irp->f, ")");
2614}2614}
26152615
2616static void ir_print_spill_begin(IrPrintSrc *irp, IrInstSrcSpillBegin *instruction) {2616static void ir_print_spill_begin(IrPrintSrc *irp, Stage1ZirInstSpillBegin *instruction) {
2617 fprintf(irp->f, "@spillBegin(");2617 fprintf(irp->f, "@spillBegin(");
2618 ir_print_other_inst_src(irp, instruction->operand);2618 ir_print_other_inst_src(irp, instruction->operand);
2619 fprintf(irp->f, ")");2619 fprintf(irp->f, ")");
2620}2620}
26212621
2622static void ir_print_spill_begin(IrPrintGen *irp, IrInstGenSpillBegin *instruction) {2622static void ir_print_spill_begin(IrPrintGen *irp, Stage1AirInstSpillBegin *instruction) {
2623 fprintf(irp->f, "@spillBegin(");2623 fprintf(irp->f, "@spillBegin(");
2624 ir_print_other_inst_gen(irp, instruction->operand);2624 ir_print_other_inst_gen(irp, instruction->operand);
2625 fprintf(irp->f, ")");2625 fprintf(irp->f, ")");
2626}2626}
26272627
2628static void ir_print_spill_end(IrPrintSrc *irp, IrInstSrcSpillEnd *instruction) {2628static void ir_print_spill_end(IrPrintSrc *irp, Stage1ZirInstSpillEnd *instruction) {
2629 fprintf(irp->f, "@spillEnd(");2629 fprintf(irp->f, "@spillEnd(");
2630 ir_print_other_inst_src(irp, &instruction->begin->base);2630 ir_print_other_inst_src(irp, &instruction->begin->base);
2631 fprintf(irp->f, ")");2631 fprintf(irp->f, ")");
2632}2632}
26332633
2634static void ir_print_spill_end(IrPrintGen *irp, IrInstGenSpillEnd *instruction) {2634static void ir_print_spill_end(IrPrintGen *irp, Stage1AirInstSpillEnd *instruction) {
2635 fprintf(irp->f, "@spillEnd(");2635 fprintf(irp->f, "@spillEnd(");
2636 ir_print_other_inst_gen(irp, &instruction->begin->base);2636 ir_print_other_inst_gen(irp, &instruction->begin->base);
2637 fprintf(irp->f, ")");2637 fprintf(irp->f, ")");
2638}2638}
26392639
2640static void ir_print_vector_extract_elem(IrPrintGen *irp, IrInstGenVectorExtractElem *instruction) {2640static void ir_print_vector_extract_elem(IrPrintGen *irp, Stage1AirInstVectorExtractElem *instruction) {
2641 fprintf(irp->f, "@vectorExtractElem(");2641 fprintf(irp->f, "@vectorExtractElem(");
2642 ir_print_other_inst_gen(irp, instruction->vector);2642 ir_print_other_inst_gen(irp, instruction->vector);
2643 fprintf(irp->f, ",");2643 fprintf(irp->f, ",");
...@@ -2645,703 +2645,703 @@ static void ir_print_vector_extract_elem(IrPrintGen *irp, IrInstGenVectorExtract...@@ -2645,703 +2645,703 @@ static void ir_print_vector_extract_elem(IrPrintGen *irp, IrInstGenVectorExtract
2645 fprintf(irp->f, ")");2645 fprintf(irp->f, ")");
2646}2646}
26472647
2648static void ir_print_inst_src(IrPrintSrc *irp, IrInstSrc *instruction, bool trailing) {2648static void ir_print_inst_src(IrPrintSrc *irp, Stage1ZirInst *instruction, bool trailing) {
2649 ir_print_prefix_src(irp, instruction, trailing);2649 ir_print_prefix_src(irp, instruction, trailing);
2650 switch (instruction->id) {2650 switch (instruction->id) {
2651 case IrInstSrcIdInvalid:2651 case Stage1ZirInstIdInvalid:
2652 zig_unreachable();2652 zig_unreachable();
2653 case IrInstSrcIdReturn:2653 case Stage1ZirInstIdReturn:
2654 ir_print_return_src(irp, (IrInstSrcReturn *)instruction);2654 ir_print_return_src(irp, (Stage1ZirInstReturn *)instruction);
2655 break;2655 break;
2656 case IrInstSrcIdConst:2656 case Stage1ZirInstIdConst:
2657 ir_print_const(irp, (IrInstSrcConst *)instruction);2657 ir_print_const(irp, (Stage1ZirInstConst *)instruction);
2658 break;2658 break;
2659 case IrInstSrcIdBinOp:2659 case Stage1ZirInstIdBinOp:
2660 ir_print_bin_op(irp, (IrInstSrcBinOp *)instruction);2660 ir_print_bin_op(irp, (Stage1ZirInstBinOp *)instruction);
2661 break;2661 break;
2662 case IrInstSrcIdMergeErrSets:2662 case Stage1ZirInstIdMergeErrSets:
2663 ir_print_merge_err_sets(irp, (IrInstSrcMergeErrSets *)instruction);2663 ir_print_merge_err_sets(irp, (Stage1ZirInstMergeErrSets *)instruction);
2664 break;2664 break;
2665 case IrInstSrcIdDeclVar:2665 case Stage1ZirInstIdDeclVar:
2666 ir_print_decl_var_src(irp, (IrInstSrcDeclVar *)instruction);2666 ir_print_decl_var_src(irp, (Stage1ZirInstDeclVar *)instruction);
2667 break;2667 break;
2668 case IrInstSrcIdCallExtra:2668 case Stage1ZirInstIdCallExtra:
2669 ir_print_call_extra(irp, (IrInstSrcCallExtra *)instruction);2669 ir_print_call_extra(irp, (Stage1ZirInstCallExtra *)instruction);
2670 break;2670 break;
2671 case IrInstSrcIdAsyncCallExtra:2671 case Stage1ZirInstIdAsyncCallExtra:
2672 ir_print_async_call_extra(irp, (IrInstSrcAsyncCallExtra *)instruction);2672 ir_print_async_call_extra(irp, (Stage1ZirInstAsyncCallExtra *)instruction);
2673 break;2673 break;
2674 case IrInstSrcIdCall:2674 case Stage1ZirInstIdCall:
2675 ir_print_call_src(irp, (IrInstSrcCall *)instruction);2675 ir_print_call_src(irp, (Stage1ZirInstCall *)instruction);
2676 break;2676 break;
2677 case IrInstSrcIdCallArgs:2677 case Stage1ZirInstIdCallArgs:
2678 ir_print_call_args(irp, (IrInstSrcCallArgs *)instruction);2678 ir_print_call_args(irp, (Stage1ZirInstCallArgs *)instruction);
2679 break;2679 break;
2680 case IrInstSrcIdUnOp:2680 case Stage1ZirInstIdUnOp:
2681 ir_print_un_op(irp, (IrInstSrcUnOp *)instruction);2681 ir_print_un_op(irp, (Stage1ZirInstUnOp *)instruction);
2682 break;2682 break;
2683 case IrInstSrcIdCondBr:2683 case Stage1ZirInstIdCondBr:
2684 ir_print_cond_br(irp, (IrInstSrcCondBr *)instruction);2684 ir_print_cond_br(irp, (Stage1ZirInstCondBr *)instruction);
2685 break;2685 break;
2686 case IrInstSrcIdBr:2686 case Stage1ZirInstIdBr:
2687 ir_print_br(irp, (IrInstSrcBr *)instruction);2687 ir_print_br(irp, (Stage1ZirInstBr *)instruction);
2688 break;2688 break;
2689 case IrInstSrcIdPhi:2689 case Stage1ZirInstIdPhi:
2690 ir_print_phi(irp, (IrInstSrcPhi *)instruction);2690 ir_print_phi(irp, (Stage1ZirInstPhi *)instruction);
2691 break;2691 break;
2692 case IrInstSrcIdContainerInitList:2692 case Stage1ZirInstIdContainerInitList:
2693 ir_print_container_init_list(irp, (IrInstSrcContainerInitList *)instruction);2693 ir_print_container_init_list(irp, (Stage1ZirInstContainerInitList *)instruction);
2694 break;2694 break;
2695 case IrInstSrcIdContainerInitFields:2695 case Stage1ZirInstIdContainerInitFields:
2696 ir_print_container_init_fields(irp, (IrInstSrcContainerInitFields *)instruction);2696 ir_print_container_init_fields(irp, (Stage1ZirInstContainerInitFields *)instruction);
2697 break;2697 break;
2698 case IrInstSrcIdUnreachable:2698 case Stage1ZirInstIdUnreachable:
2699 ir_print_unreachable(irp, (IrInstSrcUnreachable *)instruction);2699 ir_print_unreachable(irp, (Stage1ZirInstUnreachable *)instruction);
2700 break;2700 break;
2701 case IrInstSrcIdElemPtr:2701 case Stage1ZirInstIdElemPtr:
2702 ir_print_elem_ptr(irp, (IrInstSrcElemPtr *)instruction);2702 ir_print_elem_ptr(irp, (Stage1ZirInstElemPtr *)instruction);
2703 break;2703 break;
2704 case IrInstSrcIdVarPtr:2704 case Stage1ZirInstIdVarPtr:
2705 ir_print_var_ptr(irp, (IrInstSrcVarPtr *)instruction);2705 ir_print_var_ptr(irp, (Stage1ZirInstVarPtr *)instruction);
2706 break;2706 break;
2707 case IrInstSrcIdLoadPtr:2707 case Stage1ZirInstIdLoadPtr:
2708 ir_print_load_ptr(irp, (IrInstSrcLoadPtr *)instruction);2708 ir_print_load_ptr(irp, (Stage1ZirInstLoadPtr *)instruction);
2709 break;2709 break;
2710 case IrInstSrcIdStorePtr:2710 case Stage1ZirInstIdStorePtr:
2711 ir_print_store_ptr(irp, (IrInstSrcStorePtr *)instruction);2711 ir_print_store_ptr(irp, (Stage1ZirInstStorePtr *)instruction);
2712 break;2712 break;
2713 case IrInstSrcIdTypeOf:2713 case Stage1ZirInstIdTypeOf:
2714 ir_print_typeof(irp, (IrInstSrcTypeOf *)instruction);2714 ir_print_typeof(irp, (Stage1ZirInstTypeOf *)instruction);
2715 break;2715 break;
2716 case IrInstSrcIdFieldPtr:2716 case Stage1ZirInstIdFieldPtr:
2717 ir_print_field_ptr(irp, (IrInstSrcFieldPtr *)instruction);2717 ir_print_field_ptr(irp, (Stage1ZirInstFieldPtr *)instruction);
2718 break;2718 break;
2719 case IrInstSrcIdSetCold:2719 case Stage1ZirInstIdSetCold:
2720 ir_print_set_cold(irp, (IrInstSrcSetCold *)instruction);2720 ir_print_set_cold(irp, (Stage1ZirInstSetCold *)instruction);
2721 break;2721 break;
2722 case IrInstSrcIdSetRuntimeSafety:2722 case Stage1ZirInstIdSetRuntimeSafety:
2723 ir_print_set_runtime_safety(irp, (IrInstSrcSetRuntimeSafety *)instruction);2723 ir_print_set_runtime_safety(irp, (Stage1ZirInstSetRuntimeSafety *)instruction);
2724 break;2724 break;
2725 case IrInstSrcIdSetFloatMode:2725 case Stage1ZirInstIdSetFloatMode:
2726 ir_print_set_float_mode(irp, (IrInstSrcSetFloatMode *)instruction);2726 ir_print_set_float_mode(irp, (Stage1ZirInstSetFloatMode *)instruction);
2727 break;2727 break;
2728 case IrInstSrcIdArrayType:2728 case Stage1ZirInstIdArrayType:
2729 ir_print_array_type(irp, (IrInstSrcArrayType *)instruction);2729 ir_print_array_type(irp, (Stage1ZirInstArrayType *)instruction);
2730 break;2730 break;
2731 case IrInstSrcIdSliceType:2731 case Stage1ZirInstIdSliceType:
2732 ir_print_slice_type(irp, (IrInstSrcSliceType *)instruction);2732 ir_print_slice_type(irp, (Stage1ZirInstSliceType *)instruction);
2733 break;2733 break;
2734 case IrInstSrcIdAnyFrameType:2734 case Stage1ZirInstIdAnyFrameType:
2735 ir_print_any_frame_type(irp, (IrInstSrcAnyFrameType *)instruction);2735 ir_print_any_frame_type(irp, (Stage1ZirInstAnyFrameType *)instruction);
2736 break;2736 break;
2737 case IrInstSrcIdAsm:2737 case Stage1ZirInstIdAsm:
2738 ir_print_asm_src(irp, (IrInstSrcAsm *)instruction);2738 ir_print_asm_src(irp, (Stage1ZirInstAsm *)instruction);
2739 break;2739 break;
2740 case IrInstSrcIdSizeOf:2740 case Stage1ZirInstIdSizeOf:
2741 ir_print_size_of(irp, (IrInstSrcSizeOf *)instruction);2741 ir_print_size_of(irp, (Stage1ZirInstSizeOf *)instruction);
2742 break;2742 break;
2743 case IrInstSrcIdTestNonNull:2743 case Stage1ZirInstIdTestNonNull:
2744 ir_print_test_non_null(irp, (IrInstSrcTestNonNull *)instruction);2744 ir_print_test_non_null(irp, (Stage1ZirInstTestNonNull *)instruction);
2745 break;2745 break;
2746 case IrInstSrcIdOptionalUnwrapPtr:2746 case Stage1ZirInstIdOptionalUnwrapPtr:
2747 ir_print_optional_unwrap_ptr(irp, (IrInstSrcOptionalUnwrapPtr *)instruction);2747 ir_print_optional_unwrap_ptr(irp, (Stage1ZirInstOptionalUnwrapPtr *)instruction);
2748 break;2748 break;
2749 case IrInstSrcIdPopCount:2749 case Stage1ZirInstIdPopCount:
2750 ir_print_pop_count(irp, (IrInstSrcPopCount *)instruction);2750 ir_print_pop_count(irp, (Stage1ZirInstPopCount *)instruction);
2751 break;2751 break;
2752 case IrInstSrcIdCtz:2752 case Stage1ZirInstIdCtz:
2753 ir_print_ctz(irp, (IrInstSrcCtz *)instruction);2753 ir_print_ctz(irp, (Stage1ZirInstCtz *)instruction);
2754 break;2754 break;
2755 case IrInstSrcIdBswap:2755 case Stage1ZirInstIdBswap:
2756 ir_print_bswap(irp, (IrInstSrcBswap *)instruction);2756 ir_print_bswap(irp, (Stage1ZirInstBswap *)instruction);
2757 break;2757 break;
2758 case IrInstSrcIdBitReverse:2758 case Stage1ZirInstIdBitReverse:
2759 ir_print_bit_reverse(irp, (IrInstSrcBitReverse *)instruction);2759 ir_print_bit_reverse(irp, (Stage1ZirInstBitReverse *)instruction);
2760 break;2760 break;
2761 case IrInstSrcIdSwitchBr:2761 case Stage1ZirInstIdSwitchBr:
2762 ir_print_switch_br(irp, (IrInstSrcSwitchBr *)instruction);2762 ir_print_switch_br(irp, (Stage1ZirInstSwitchBr *)instruction);
2763 break;2763 break;
2764 case IrInstSrcIdSwitchVar:2764 case Stage1ZirInstIdSwitchVar:
2765 ir_print_switch_var(irp, (IrInstSrcSwitchVar *)instruction);2765 ir_print_switch_var(irp, (Stage1ZirInstSwitchVar *)instruction);
2766 break;2766 break;
2767 case IrInstSrcIdSwitchElseVar:2767 case Stage1ZirInstIdSwitchElseVar:
2768 ir_print_switch_else_var(irp, (IrInstSrcSwitchElseVar *)instruction);2768 ir_print_switch_else_var(irp, (Stage1ZirInstSwitchElseVar *)instruction);
2769 break;2769 break;
2770 case IrInstSrcIdSwitchTarget:2770 case Stage1ZirInstIdSwitchTarget:
2771 ir_print_switch_target(irp, (IrInstSrcSwitchTarget *)instruction);2771 ir_print_switch_target(irp, (Stage1ZirInstSwitchTarget *)instruction);
2772 break;2772 break;
2773 case IrInstSrcIdImport:2773 case Stage1ZirInstIdImport:
2774 ir_print_import(irp, (IrInstSrcImport *)instruction);2774 ir_print_import(irp, (Stage1ZirInstImport *)instruction);
2775 break;2775 break;
2776 case IrInstSrcIdRef:2776 case Stage1ZirInstIdRef:
2777 ir_print_ref(irp, (IrInstSrcRef *)instruction);2777 ir_print_ref(irp, (Stage1ZirInstRef *)instruction);
2778 break;2778 break;
2779 case IrInstSrcIdCompileErr:2779 case Stage1ZirInstIdCompileErr:
2780 ir_print_compile_err(irp, (IrInstSrcCompileErr *)instruction);2780 ir_print_compile_err(irp, (Stage1ZirInstCompileErr *)instruction);
2781 break;2781 break;
2782 case IrInstSrcIdCompileLog:2782 case Stage1ZirInstIdCompileLog:
2783 ir_print_compile_log(irp, (IrInstSrcCompileLog *)instruction);2783 ir_print_compile_log(irp, (Stage1ZirInstCompileLog *)instruction);
2784 break;2784 break;
2785 case IrInstSrcIdErrName:2785 case Stage1ZirInstIdErrName:
2786 ir_print_err_name(irp, (IrInstSrcErrName *)instruction);2786 ir_print_err_name(irp, (Stage1ZirInstErrName *)instruction);
2787 break;2787 break;
2788 case IrInstSrcIdCImport:2788 case Stage1ZirInstIdCImport:
2789 ir_print_c_import(irp, (IrInstSrcCImport *)instruction);2789 ir_print_c_import(irp, (Stage1ZirInstCImport *)instruction);
2790 break;2790 break;
2791 case IrInstSrcIdCInclude:2791 case Stage1ZirInstIdCInclude:
2792 ir_print_c_include(irp, (IrInstSrcCInclude *)instruction);2792 ir_print_c_include(irp, (Stage1ZirInstCInclude *)instruction);
2793 break;2793 break;
2794 case IrInstSrcIdCDefine:2794 case Stage1ZirInstIdCDefine:
2795 ir_print_c_define(irp, (IrInstSrcCDefine *)instruction);2795 ir_print_c_define(irp, (Stage1ZirInstCDefine *)instruction);
2796 break;2796 break;
2797 case IrInstSrcIdCUndef:2797 case Stage1ZirInstIdCUndef:
2798 ir_print_c_undef(irp, (IrInstSrcCUndef *)instruction);2798 ir_print_c_undef(irp, (Stage1ZirInstCUndef *)instruction);
2799 break;2799 break;
2800 case IrInstSrcIdEmbedFile:2800 case Stage1ZirInstIdEmbedFile:
2801 ir_print_embed_file(irp, (IrInstSrcEmbedFile *)instruction);2801 ir_print_embed_file(irp, (Stage1ZirInstEmbedFile *)instruction);
2802 break;2802 break;
2803 case IrInstSrcIdCmpxchg:2803 case Stage1ZirInstIdCmpxchg:
2804 ir_print_cmpxchg_src(irp, (IrInstSrcCmpxchg *)instruction);2804 ir_print_cmpxchg_src(irp, (Stage1ZirInstCmpxchg *)instruction);
2805 break;2805 break;
2806 case IrInstSrcIdFence:2806 case Stage1ZirInstIdFence:
2807 ir_print_fence(irp, (IrInstSrcFence *)instruction);2807 ir_print_fence(irp, (Stage1ZirInstFence *)instruction);
2808 break;2808 break;
2809 case IrInstSrcIdReduce:2809 case Stage1ZirInstIdReduce:
2810 ir_print_reduce(irp, (IrInstSrcReduce *)instruction);2810 ir_print_reduce(irp, (Stage1ZirInstReduce *)instruction);
2811 break;2811 break;
2812 case IrInstSrcIdTruncate:2812 case Stage1ZirInstIdTruncate:
2813 ir_print_truncate(irp, (IrInstSrcTruncate *)instruction);2813 ir_print_truncate(irp, (Stage1ZirInstTruncate *)instruction);
2814 break;2814 break;
2815 case IrInstSrcIdIntCast:2815 case Stage1ZirInstIdIntCast:
2816 ir_print_int_cast(irp, (IrInstSrcIntCast *)instruction);2816 ir_print_int_cast(irp, (Stage1ZirInstIntCast *)instruction);
2817 break;2817 break;
2818 case IrInstSrcIdFloatCast:2818 case Stage1ZirInstIdFloatCast:
2819 ir_print_float_cast(irp, (IrInstSrcFloatCast *)instruction);2819 ir_print_float_cast(irp, (Stage1ZirInstFloatCast *)instruction);
2820 break;2820 break;
2821 case IrInstSrcIdErrSetCast:2821 case Stage1ZirInstIdErrSetCast:
2822 ir_print_err_set_cast(irp, (IrInstSrcErrSetCast *)instruction);2822 ir_print_err_set_cast(irp, (Stage1ZirInstErrSetCast *)instruction);
2823 break;2823 break;
2824 case IrInstSrcIdIntToFloat:2824 case Stage1ZirInstIdIntToFloat:
2825 ir_print_int_to_float(irp, (IrInstSrcIntToFloat *)instruction);2825 ir_print_int_to_float(irp, (Stage1ZirInstIntToFloat *)instruction);
2826 break;2826 break;
2827 case IrInstSrcIdFloatToInt:2827 case Stage1ZirInstIdFloatToInt:
2828 ir_print_float_to_int(irp, (IrInstSrcFloatToInt *)instruction);2828 ir_print_float_to_int(irp, (Stage1ZirInstFloatToInt *)instruction);
2829 break;2829 break;
2830 case IrInstSrcIdBoolToInt:2830 case Stage1ZirInstIdBoolToInt:
2831 ir_print_bool_to_int(irp, (IrInstSrcBoolToInt *)instruction);2831 ir_print_bool_to_int(irp, (Stage1ZirInstBoolToInt *)instruction);
2832 break;2832 break;
2833 case IrInstSrcIdVectorType:2833 case Stage1ZirInstIdVectorType:
2834 ir_print_vector_type(irp, (IrInstSrcVectorType *)instruction);2834 ir_print_vector_type(irp, (Stage1ZirInstVectorType *)instruction);
2835 break;2835 break;
2836 case IrInstSrcIdShuffleVector:2836 case Stage1ZirInstIdShuffleVector:
2837 ir_print_shuffle_vector(irp, (IrInstSrcShuffleVector *)instruction);2837 ir_print_shuffle_vector(irp, (Stage1ZirInstShuffleVector *)instruction);
2838 break;2838 break;
2839 case IrInstSrcIdSplat:2839 case Stage1ZirInstIdSplat:
2840 ir_print_splat_src(irp, (IrInstSrcSplat *)instruction);2840 ir_print_splat_src(irp, (Stage1ZirInstSplat *)instruction);
2841 break;2841 break;
2842 case IrInstSrcIdBoolNot:2842 case Stage1ZirInstIdBoolNot:
2843 ir_print_bool_not(irp, (IrInstSrcBoolNot *)instruction);2843 ir_print_bool_not(irp, (Stage1ZirInstBoolNot *)instruction);
2844 break;2844 break;
2845 case IrInstSrcIdMemset:2845 case Stage1ZirInstIdMemset:
2846 ir_print_memset(irp, (IrInstSrcMemset *)instruction);2846 ir_print_memset(irp, (Stage1ZirInstMemset *)instruction);
2847 break;2847 break;
2848 case IrInstSrcIdMemcpy:2848 case Stage1ZirInstIdMemcpy:
2849 ir_print_memcpy(irp, (IrInstSrcMemcpy *)instruction);2849 ir_print_memcpy(irp, (Stage1ZirInstMemcpy *)instruction);
2850 break;2850 break;
2851 case IrInstSrcIdSlice:2851 case Stage1ZirInstIdSlice:
2852 ir_print_slice_src(irp, (IrInstSrcSlice *)instruction);2852 ir_print_slice_src(irp, (Stage1ZirInstSlice *)instruction);
2853 break;2853 break;
2854 case IrInstSrcIdBreakpoint:2854 case Stage1ZirInstIdBreakpoint:
2855 ir_print_breakpoint(irp, (IrInstSrcBreakpoint *)instruction);2855 ir_print_breakpoint(irp, (Stage1ZirInstBreakpoint *)instruction);
2856 break;2856 break;
2857 case IrInstSrcIdReturnAddress:2857 case Stage1ZirInstIdReturnAddress:
2858 ir_print_return_address(irp, (IrInstSrcReturnAddress *)instruction);2858 ir_print_return_address(irp, (Stage1ZirInstReturnAddress *)instruction);
2859 break;2859 break;
2860 case IrInstSrcIdFrameAddress:2860 case Stage1ZirInstIdFrameAddress:
2861 ir_print_frame_address(irp, (IrInstSrcFrameAddress *)instruction);2861 ir_print_frame_address(irp, (Stage1ZirInstFrameAddress *)instruction);
2862 break;2862 break;
2863 case IrInstSrcIdFrameHandle:2863 case Stage1ZirInstIdFrameHandle:
2864 ir_print_handle(irp, (IrInstSrcFrameHandle *)instruction);2864 ir_print_handle(irp, (Stage1ZirInstFrameHandle *)instruction);
2865 break;2865 break;
2866 case IrInstSrcIdFrameType:2866 case Stage1ZirInstIdFrameType:
2867 ir_print_frame_type(irp, (IrInstSrcFrameType *)instruction);2867 ir_print_frame_type(irp, (Stage1ZirInstFrameType *)instruction);
2868 break;2868 break;
2869 case IrInstSrcIdFrameSize:2869 case Stage1ZirInstIdFrameSize:
2870 ir_print_frame_size_src(irp, (IrInstSrcFrameSize *)instruction);2870 ir_print_frame_size_src(irp, (Stage1ZirInstFrameSize *)instruction);
2871 break;2871 break;
2872 case IrInstSrcIdAlignOf:2872 case Stage1ZirInstIdAlignOf:
2873 ir_print_align_of(irp, (IrInstSrcAlignOf *)instruction);2873 ir_print_align_of(irp, (Stage1ZirInstAlignOf *)instruction);
2874 break;2874 break;
2875 case IrInstSrcIdOverflowOp:2875 case Stage1ZirInstIdOverflowOp:
2876 ir_print_overflow_op(irp, (IrInstSrcOverflowOp *)instruction);2876 ir_print_overflow_op(irp, (Stage1ZirInstOverflowOp *)instruction);
2877 break;2877 break;
2878 case IrInstSrcIdTestErr:2878 case Stage1ZirInstIdTestErr:
2879 ir_print_test_err_src(irp, (IrInstSrcTestErr *)instruction);2879 ir_print_test_err_src(irp, (Stage1ZirInstTestErr *)instruction);
2880 break;2880 break;
2881 case IrInstSrcIdUnwrapErrCode:2881 case Stage1ZirInstIdUnwrapErrCode:
2882 ir_print_unwrap_err_code(irp, (IrInstSrcUnwrapErrCode *)instruction);2882 ir_print_unwrap_err_code(irp, (Stage1ZirInstUnwrapErrCode *)instruction);
2883 break;2883 break;
2884 case IrInstSrcIdUnwrapErrPayload:2884 case Stage1ZirInstIdUnwrapErrPayload:
2885 ir_print_unwrap_err_payload(irp, (IrInstSrcUnwrapErrPayload *)instruction);2885 ir_print_unwrap_err_payload(irp, (Stage1ZirInstUnwrapErrPayload *)instruction);
2886 break;2886 break;
2887 case IrInstSrcIdFnProto:2887 case Stage1ZirInstIdFnProto:
2888 ir_print_fn_proto(irp, (IrInstSrcFnProto *)instruction);2888 ir_print_fn_proto(irp, (Stage1ZirInstFnProto *)instruction);
2889 break;2889 break;
2890 case IrInstSrcIdTestComptime:2890 case Stage1ZirInstIdTestComptime:
2891 ir_print_test_comptime(irp, (IrInstSrcTestComptime *)instruction);2891 ir_print_test_comptime(irp, (Stage1ZirInstTestComptime *)instruction);
2892 break;2892 break;
2893 case IrInstSrcIdPtrCast:2893 case Stage1ZirInstIdPtrCast:
2894 ir_print_ptr_cast_src(irp, (IrInstSrcPtrCast *)instruction);2894 ir_print_ptr_cast_src(irp, (Stage1ZirInstPtrCast *)instruction);
2895 break;2895 break;
2896 case IrInstSrcIdBitCast:2896 case Stage1ZirInstIdBitCast:
2897 ir_print_bit_cast_src(irp, (IrInstSrcBitCast *)instruction);2897 ir_print_bit_cast_src(irp, (Stage1ZirInstBitCast *)instruction);
2898 break;2898 break;
2899 case IrInstSrcIdPtrToInt:2899 case Stage1ZirInstIdPtrToInt:
2900 ir_print_ptr_to_int(irp, (IrInstSrcPtrToInt *)instruction);2900 ir_print_ptr_to_int(irp, (Stage1ZirInstPtrToInt *)instruction);
2901 break;2901 break;
2902 case IrInstSrcIdIntToPtr:2902 case Stage1ZirInstIdIntToPtr:
2903 ir_print_int_to_ptr(irp, (IrInstSrcIntToPtr *)instruction);2903 ir_print_int_to_ptr(irp, (Stage1ZirInstIntToPtr *)instruction);
2904 break;2904 break;
2905 case IrInstSrcIdIntToEnum:2905 case Stage1ZirInstIdIntToEnum:
2906 ir_print_int_to_enum(irp, (IrInstSrcIntToEnum *)instruction);2906 ir_print_int_to_enum(irp, (Stage1ZirInstIntToEnum *)instruction);
2907 break;2907 break;
2908 case IrInstSrcIdIntToErr:2908 case Stage1ZirInstIdIntToErr:
2909 ir_print_int_to_err(irp, (IrInstSrcIntToErr *)instruction);2909 ir_print_int_to_err(irp, (Stage1ZirInstIntToErr *)instruction);
2910 break;2910 break;
2911 case IrInstSrcIdErrToInt:2911 case Stage1ZirInstIdErrToInt:
2912 ir_print_err_to_int(irp, (IrInstSrcErrToInt *)instruction);2912 ir_print_err_to_int(irp, (Stage1ZirInstErrToInt *)instruction);
2913 break;2913 break;
2914 case IrInstSrcIdCheckSwitchProngsUnderNo:2914 case Stage1ZirInstIdCheckSwitchProngsUnderNo:
2915 ir_print_check_switch_prongs(irp, (IrInstSrcCheckSwitchProngs *)instruction, false);2915 ir_print_check_switch_prongs(irp, (Stage1ZirInstCheckSwitchProngs *)instruction, false);
2916 break;2916 break;
2917 case IrInstSrcIdCheckSwitchProngsUnderYes:2917 case Stage1ZirInstIdCheckSwitchProngsUnderYes:
2918 ir_print_check_switch_prongs(irp, (IrInstSrcCheckSwitchProngs *)instruction, true);2918 ir_print_check_switch_prongs(irp, (Stage1ZirInstCheckSwitchProngs *)instruction, true);
2919 break;2919 break;
2920 case IrInstSrcIdCheckStatementIsVoid:2920 case Stage1ZirInstIdCheckStatementIsVoid:
2921 ir_print_check_statement_is_void(irp, (IrInstSrcCheckStatementIsVoid *)instruction);2921 ir_print_check_statement_is_void(irp, (Stage1ZirInstCheckStatementIsVoid *)instruction);
2922 break;2922 break;
2923 case IrInstSrcIdTypeName:2923 case Stage1ZirInstIdTypeName:
2924 ir_print_type_name(irp, (IrInstSrcTypeName *)instruction);2924 ir_print_type_name(irp, (Stage1ZirInstTypeName *)instruction);
2925 break;2925 break;
2926 case IrInstSrcIdTagName:2926 case Stage1ZirInstIdTagName:
2927 ir_print_tag_name(irp, (IrInstSrcTagName *)instruction);2927 ir_print_tag_name(irp, (Stage1ZirInstTagName *)instruction);
2928 break;2928 break;
2929 case IrInstSrcIdPtrType:2929 case Stage1ZirInstIdPtrType:
2930 ir_print_ptr_type(irp, (IrInstSrcPtrType *)instruction);2930 ir_print_ptr_type(irp, (Stage1ZirInstPtrType *)instruction);
2931 break;2931 break;
2932 case IrInstSrcIdPtrTypeSimple:2932 case Stage1ZirInstIdPtrTypeSimple:
2933 ir_print_ptr_type_simple(irp, (IrInstSrcPtrTypeSimple *)instruction, false);2933 ir_print_ptr_type_simple(irp, (Stage1ZirInstPtrTypeSimple *)instruction, false);
2934 break;2934 break;
2935 case IrInstSrcIdPtrTypeSimpleConst:2935 case Stage1ZirInstIdPtrTypeSimpleConst:
2936 ir_print_ptr_type_simple(irp, (IrInstSrcPtrTypeSimple *)instruction, true);2936 ir_print_ptr_type_simple(irp, (Stage1ZirInstPtrTypeSimple *)instruction, true);
2937 break;2937 break;
2938 case IrInstSrcIdDeclRef:2938 case Stage1ZirInstIdDeclRef:
2939 ir_print_decl_ref(irp, (IrInstSrcDeclRef *)instruction);2939 ir_print_decl_ref(irp, (Stage1ZirInstDeclRef *)instruction);
2940 break;2940 break;
2941 case IrInstSrcIdPanic:2941 case Stage1ZirInstIdPanic:
2942 ir_print_panic(irp, (IrInstSrcPanic *)instruction);2942 ir_print_panic(irp, (Stage1ZirInstPanic *)instruction);
2943 break;2943 break;
2944 case IrInstSrcIdFieldParentPtr:2944 case Stage1ZirInstIdFieldParentPtr:
2945 ir_print_field_parent_ptr(irp, (IrInstSrcFieldParentPtr *)instruction);2945 ir_print_field_parent_ptr(irp, (Stage1ZirInstFieldParentPtr *)instruction);
2946 break;2946 break;
2947 case IrInstSrcIdOffsetOf:2947 case Stage1ZirInstIdOffsetOf:
2948 ir_print_offset_of(irp, (IrInstSrcOffsetOf *)instruction);2948 ir_print_offset_of(irp, (Stage1ZirInstOffsetOf *)instruction);
2949 break;2949 break;
2950 case IrInstSrcIdBitOffsetOf:2950 case Stage1ZirInstIdBitOffsetOf:
2951 ir_print_bit_offset_of(irp, (IrInstSrcBitOffsetOf *)instruction);2951 ir_print_bit_offset_of(irp, (Stage1ZirInstBitOffsetOf *)instruction);
2952 break;2952 break;
2953 case IrInstSrcIdTypeInfo:2953 case Stage1ZirInstIdTypeInfo:
2954 ir_print_type_info(irp, (IrInstSrcTypeInfo *)instruction);2954 ir_print_type_info(irp, (Stage1ZirInstTypeInfo *)instruction);
2955 break;2955 break;
2956 case IrInstSrcIdType:2956 case Stage1ZirInstIdType:
2957 ir_print_type(irp, (IrInstSrcType *)instruction);2957 ir_print_type(irp, (Stage1ZirInstType *)instruction);
2958 break;2958 break;
2959 case IrInstSrcIdHasField:2959 case Stage1ZirInstIdHasField:
2960 ir_print_has_field(irp, (IrInstSrcHasField *)instruction);2960 ir_print_has_field(irp, (Stage1ZirInstHasField *)instruction);
2961 break;2961 break;
2962 case IrInstSrcIdSetEvalBranchQuota:2962 case Stage1ZirInstIdSetEvalBranchQuota:
2963 ir_print_set_eval_branch_quota(irp, (IrInstSrcSetEvalBranchQuota *)instruction);2963 ir_print_set_eval_branch_quota(irp, (Stage1ZirInstSetEvalBranchQuota *)instruction);
2964 break;2964 break;
2965 case IrInstSrcIdAlignCast:2965 case Stage1ZirInstIdAlignCast:
2966 ir_print_align_cast(irp, (IrInstSrcAlignCast *)instruction);2966 ir_print_align_cast(irp, (Stage1ZirInstAlignCast *)instruction);
2967 break;2967 break;
2968 case IrInstSrcIdImplicitCast:2968 case Stage1ZirInstIdImplicitCast:
2969 ir_print_implicit_cast(irp, (IrInstSrcImplicitCast *)instruction);2969 ir_print_implicit_cast(irp, (Stage1ZirInstImplicitCast *)instruction);
2970 break;2970 break;
2971 case IrInstSrcIdResolveResult:2971 case Stage1ZirInstIdResolveResult:
2972 ir_print_resolve_result(irp, (IrInstSrcResolveResult *)instruction);2972 ir_print_resolve_result(irp, (Stage1ZirInstResolveResult *)instruction);
2973 break;2973 break;
2974 case IrInstSrcIdResetResult:2974 case Stage1ZirInstIdResetResult:
2975 ir_print_reset_result(irp, (IrInstSrcResetResult *)instruction);2975 ir_print_reset_result(irp, (Stage1ZirInstResetResult *)instruction);
2976 break;2976 break;
2977 case IrInstSrcIdSetAlignStack:2977 case Stage1ZirInstIdSetAlignStack:
2978 ir_print_set_align_stack(irp, (IrInstSrcSetAlignStack *)instruction);2978 ir_print_set_align_stack(irp, (Stage1ZirInstSetAlignStack *)instruction);
2979 break;2979 break;
2980 case IrInstSrcIdArgTypeAllowVarFalse:2980 case Stage1ZirInstIdArgTypeAllowVarFalse:
2981 ir_print_arg_type(irp, (IrInstSrcArgType *)instruction, false);2981 ir_print_arg_type(irp, (Stage1ZirInstArgType *)instruction, false);
2982 break;2982 break;
2983 case IrInstSrcIdArgTypeAllowVarTrue:2983 case Stage1ZirInstIdArgTypeAllowVarTrue:
2984 ir_print_arg_type(irp, (IrInstSrcArgType *)instruction, true);2984 ir_print_arg_type(irp, (Stage1ZirInstArgType *)instruction, true);
2985 break;2985 break;
2986 case IrInstSrcIdExport:2986 case Stage1ZirInstIdExport:
2987 ir_print_export(irp, (IrInstSrcExport *)instruction);2987 ir_print_export(irp, (Stage1ZirInstExport *)instruction);
2988 break;2988 break;
2989 case IrInstSrcIdExtern:2989 case Stage1ZirInstIdExtern:
2990 ir_print_extern(irp, (IrInstSrcExtern*)instruction);2990 ir_print_extern(irp, (Stage1ZirInstExtern*)instruction);
2991 break;2991 break;
2992 case IrInstSrcIdErrorReturnTrace:2992 case Stage1ZirInstIdErrorReturnTrace:
2993 ir_print_error_return_trace(irp, (IrInstSrcErrorReturnTrace *)instruction);2993 ir_print_error_return_trace(irp, (Stage1ZirInstErrorReturnTrace *)instruction);
2994 break;2994 break;
2995 case IrInstSrcIdErrorUnion:2995 case Stage1ZirInstIdErrorUnion:
2996 ir_print_error_union(irp, (IrInstSrcErrorUnion *)instruction);2996 ir_print_error_union(irp, (Stage1ZirInstErrorUnion *)instruction);
2997 break;2997 break;
2998 case IrInstSrcIdAtomicRmw:2998 case Stage1ZirInstIdAtomicRmw:
2999 ir_print_atomic_rmw(irp, (IrInstSrcAtomicRmw *)instruction);2999 ir_print_atomic_rmw(irp, (Stage1ZirInstAtomicRmw *)instruction);
3000 break;3000 break;
3001 case IrInstSrcIdSaveErrRetAddr:3001 case Stage1ZirInstIdSaveErrRetAddr:
3002 ir_print_save_err_ret_addr(irp, (IrInstSrcSaveErrRetAddr *)instruction);3002 ir_print_save_err_ret_addr(irp, (Stage1ZirInstSaveErrRetAddr *)instruction);
3003 break;3003 break;
3004 case IrInstSrcIdAddImplicitReturnType:3004 case Stage1ZirInstIdAddImplicitReturnType:
3005 ir_print_add_implicit_return_type(irp, (IrInstSrcAddImplicitReturnType *)instruction);3005 ir_print_add_implicit_return_type(irp, (Stage1ZirInstAddImplicitReturnType *)instruction);
3006 break;3006 break;
3007 case IrInstSrcIdFloatOp:3007 case Stage1ZirInstIdFloatOp:
3008 ir_print_float_op(irp, (IrInstSrcFloatOp *)instruction);3008 ir_print_float_op(irp, (Stage1ZirInstFloatOp *)instruction);
3009 break;3009 break;
3010 case IrInstSrcIdMulAdd:3010 case Stage1ZirInstIdMulAdd:
3011 ir_print_mul_add(irp, (IrInstSrcMulAdd *)instruction);3011 ir_print_mul_add(irp, (Stage1ZirInstMulAdd *)instruction);
3012 break;3012 break;
3013 case IrInstSrcIdAtomicLoad:3013 case Stage1ZirInstIdAtomicLoad:
3014 ir_print_atomic_load(irp, (IrInstSrcAtomicLoad *)instruction);3014 ir_print_atomic_load(irp, (Stage1ZirInstAtomicLoad *)instruction);
3015 break;3015 break;
3016 case IrInstSrcIdAtomicStore:3016 case Stage1ZirInstIdAtomicStore:
3017 ir_print_atomic_store(irp, (IrInstSrcAtomicStore *)instruction);3017 ir_print_atomic_store(irp, (Stage1ZirInstAtomicStore *)instruction);
3018 break;3018 break;
3019 case IrInstSrcIdEnumToInt:3019 case Stage1ZirInstIdEnumToInt:
3020 ir_print_enum_to_int(irp, (IrInstSrcEnumToInt *)instruction);3020 ir_print_enum_to_int(irp, (Stage1ZirInstEnumToInt *)instruction);
3021 break;3021 break;
3022 case IrInstSrcIdCheckRuntimeScope:3022 case Stage1ZirInstIdCheckRuntimeScope:
3023 ir_print_check_runtime_scope(irp, (IrInstSrcCheckRuntimeScope *)instruction);3023 ir_print_check_runtime_scope(irp, (Stage1ZirInstCheckRuntimeScope *)instruction);
3024 break;3024 break;
3025 case IrInstSrcIdHasDecl:3025 case Stage1ZirInstIdHasDecl:
3026 ir_print_has_decl(irp, (IrInstSrcHasDecl *)instruction);3026 ir_print_has_decl(irp, (Stage1ZirInstHasDecl *)instruction);
3027 break;3027 break;
3028 case IrInstSrcIdUndeclaredIdent:3028 case Stage1ZirInstIdUndeclaredIdent:
3029 ir_print_undeclared_ident(irp, (IrInstSrcUndeclaredIdent *)instruction);3029 ir_print_undeclared_ident(irp, (Stage1ZirInstUndeclaredIdent *)instruction);
3030 break;3030 break;
3031 case IrInstSrcIdAlloca:3031 case Stage1ZirInstIdAlloca:
3032 ir_print_alloca_src(irp, (IrInstSrcAlloca *)instruction);3032 ir_print_alloca_src(irp, (Stage1ZirInstAlloca *)instruction);
3033 break;3033 break;
3034 case IrInstSrcIdEndExpr:3034 case Stage1ZirInstIdEndExpr:
3035 ir_print_end_expr(irp, (IrInstSrcEndExpr *)instruction);3035 ir_print_end_expr(irp, (Stage1ZirInstEndExpr *)instruction);
3036 break;3036 break;
3037 case IrInstSrcIdUnionInitNamedField:3037 case Stage1ZirInstIdUnionInitNamedField:
3038 ir_print_union_init_named_field(irp, (IrInstSrcUnionInitNamedField *)instruction);3038 ir_print_union_init_named_field(irp, (Stage1ZirInstUnionInitNamedField *)instruction);
3039 break;3039 break;
3040 case IrInstSrcIdSuspendBegin:3040 case Stage1ZirInstIdSuspendBegin:
3041 ir_print_suspend_begin(irp, (IrInstSrcSuspendBegin *)instruction);3041 ir_print_suspend_begin(irp, (Stage1ZirInstSuspendBegin *)instruction);
3042 break;3042 break;
3043 case IrInstSrcIdSuspendFinish:3043 case Stage1ZirInstIdSuspendFinish:
3044 ir_print_suspend_finish(irp, (IrInstSrcSuspendFinish *)instruction);3044 ir_print_suspend_finish(irp, (Stage1ZirInstSuspendFinish *)instruction);
3045 break;3045 break;
3046 case IrInstSrcIdResume:3046 case Stage1ZirInstIdResume:
3047 ir_print_resume(irp, (IrInstSrcResume *)instruction);3047 ir_print_resume(irp, (Stage1ZirInstResume *)instruction);
3048 break;3048 break;
3049 case IrInstSrcIdAwait:3049 case Stage1ZirInstIdAwait:
3050 ir_print_await_src(irp, (IrInstSrcAwait *)instruction);3050 ir_print_await_src(irp, (Stage1ZirInstAwait *)instruction);
3051 break;3051 break;
3052 case IrInstSrcIdSpillBegin:3052 case Stage1ZirInstIdSpillBegin:
3053 ir_print_spill_begin(irp, (IrInstSrcSpillBegin *)instruction);3053 ir_print_spill_begin(irp, (Stage1ZirInstSpillBegin *)instruction);
3054 break;3054 break;
3055 case IrInstSrcIdSpillEnd:3055 case Stage1ZirInstIdSpillEnd:
3056 ir_print_spill_end(irp, (IrInstSrcSpillEnd *)instruction);3056 ir_print_spill_end(irp, (Stage1ZirInstSpillEnd *)instruction);
3057 break;3057 break;
3058 case IrInstSrcIdClz:3058 case Stage1ZirInstIdClz:
3059 ir_print_clz(irp, (IrInstSrcClz *)instruction);3059 ir_print_clz(irp, (Stage1ZirInstClz *)instruction);
3060 break;3060 break;
3061 case IrInstSrcIdWasmMemorySize:3061 case Stage1ZirInstIdWasmMemorySize:
3062 ir_print_wasm_memory_size(irp, (IrInstSrcWasmMemorySize *)instruction);3062 ir_print_wasm_memory_size(irp, (Stage1ZirInstWasmMemorySize *)instruction);
3063 break;3063 break;
3064 case IrInstSrcIdWasmMemoryGrow:3064 case Stage1ZirInstIdWasmMemoryGrow:
3065 ir_print_wasm_memory_grow(irp, (IrInstSrcWasmMemoryGrow *)instruction);3065 ir_print_wasm_memory_grow(irp, (Stage1ZirInstWasmMemoryGrow *)instruction);
3066 break;3066 break;
3067 case IrInstSrcIdSrc:3067 case Stage1ZirInstIdSrc:
3068 ir_print_builtin_src(irp, (IrInstSrcSrc *)instruction);3068 ir_print_builtin_src(irp, (Stage1ZirInstSrc *)instruction);
3069 break;3069 break;
3070 }3070 }
3071 fprintf(irp->f, "\n");3071 fprintf(irp->f, "\n");
3072}3072}
30733073
3074static void ir_print_inst_gen(IrPrintGen *irp, IrInstGen *instruction, bool trailing) {3074static void ir_print_inst_gen(IrPrintGen *irp, Stage1AirInst *instruction, bool trailing) {
3075 ir_print_prefix_gen(irp, instruction, trailing);3075 ir_print_prefix_gen(irp, instruction, trailing);
3076 switch (instruction->id) {3076 switch (instruction->id) {
3077 case IrInstGenIdInvalid:3077 case Stage1AirInstIdInvalid:
3078 zig_unreachable();3078 zig_unreachable();
3079 case IrInstGenIdReturn:3079 case Stage1AirInstIdReturn:
3080 ir_print_return_gen(irp, (IrInstGenReturn *)instruction);3080 ir_print_return_gen(irp, (Stage1AirInstReturn *)instruction);
3081 break;3081 break;
3082 case IrInstGenIdConst:3082 case Stage1AirInstIdConst:
3083 ir_print_const(irp, (IrInstGenConst *)instruction);3083 ir_print_const(irp, (Stage1AirInstConst *)instruction);
3084 break;3084 break;
3085 case IrInstGenIdBinOp:3085 case Stage1AirInstIdBinOp:
3086 ir_print_bin_op(irp, (IrInstGenBinOp *)instruction);3086 ir_print_bin_op(irp, (Stage1AirInstBinOp *)instruction);
3087 break;3087 break;
3088 case IrInstGenIdDeclVar:3088 case Stage1AirInstIdDeclVar:
3089 ir_print_decl_var_gen(irp, (IrInstGenDeclVar *)instruction);3089 ir_print_decl_var_gen(irp, (Stage1AirInstDeclVar *)instruction);
3090 break;3090 break;
3091 case IrInstGenIdCast:3091 case Stage1AirInstIdCast:
3092 ir_print_cast(irp, (IrInstGenCast *)instruction);3092 ir_print_cast(irp, (Stage1AirInstCast *)instruction);
3093 break;3093 break;
3094 case IrInstGenIdCall:3094 case Stage1AirInstIdCall:
3095 ir_print_call_gen(irp, (IrInstGenCall *)instruction);3095 ir_print_call_gen(irp, (Stage1AirInstCall *)instruction);
3096 break;3096 break;
3097 case IrInstGenIdCondBr:3097 case Stage1AirInstIdCondBr:
3098 ir_print_cond_br(irp, (IrInstGenCondBr *)instruction);3098 ir_print_cond_br(irp, (Stage1AirInstCondBr *)instruction);
3099 break;3099 break;
3100 case IrInstGenIdBr:3100 case Stage1AirInstIdBr:
3101 ir_print_br(irp, (IrInstGenBr *)instruction);3101 ir_print_br(irp, (Stage1AirInstBr *)instruction);
3102 break;3102 break;
3103 case IrInstGenIdPhi:3103 case Stage1AirInstIdPhi:
3104 ir_print_phi(irp, (IrInstGenPhi *)instruction);3104 ir_print_phi(irp, (Stage1AirInstPhi *)instruction);
3105 break;3105 break;
3106 case IrInstGenIdUnreachable:3106 case Stage1AirInstIdUnreachable:
3107 ir_print_unreachable(irp, (IrInstGenUnreachable *)instruction);3107 ir_print_unreachable(irp, (Stage1AirInstUnreachable *)instruction);
3108 break;3108 break;
3109 case IrInstGenIdElemPtr:3109 case Stage1AirInstIdElemPtr:
3110 ir_print_elem_ptr(irp, (IrInstGenElemPtr *)instruction);3110 ir_print_elem_ptr(irp, (Stage1AirInstElemPtr *)instruction);
3111 break;3111 break;
3112 case IrInstGenIdVarPtr:3112 case Stage1AirInstIdVarPtr:
3113 ir_print_var_ptr(irp, (IrInstGenVarPtr *)instruction);3113 ir_print_var_ptr(irp, (Stage1AirInstVarPtr *)instruction);
3114 break;3114 break;
3115 case IrInstGenIdReturnPtr:3115 case Stage1AirInstIdReturnPtr:
3116 ir_print_return_ptr(irp, (IrInstGenReturnPtr *)instruction);3116 ir_print_return_ptr(irp, (Stage1AirInstReturnPtr *)instruction);
3117 break;3117 break;
3118 case IrInstGenIdLoadPtr:3118 case Stage1AirInstIdLoadPtr:
3119 ir_print_load_ptr_gen(irp, (IrInstGenLoadPtr *)instruction);3119 ir_print_load_ptr_gen(irp, (Stage1AirInstLoadPtr *)instruction);
3120 break;3120 break;
3121 case IrInstGenIdStorePtr:3121 case Stage1AirInstIdStorePtr:
3122 ir_print_store_ptr(irp, (IrInstGenStorePtr *)instruction);3122 ir_print_store_ptr(irp, (Stage1AirInstStorePtr *)instruction);
3123 break;3123 break;
3124 case IrInstGenIdStructFieldPtr:3124 case Stage1AirInstIdStructFieldPtr:
3125 ir_print_struct_field_ptr(irp, (IrInstGenStructFieldPtr *)instruction);3125 ir_print_struct_field_ptr(irp, (Stage1AirInstStructFieldPtr *)instruction);
3126 break;3126 break;
3127 case IrInstGenIdUnionFieldPtr:3127 case Stage1AirInstIdUnionFieldPtr:
3128 ir_print_union_field_ptr(irp, (IrInstGenUnionFieldPtr *)instruction);3128 ir_print_union_field_ptr(irp, (Stage1AirInstUnionFieldPtr *)instruction);
3129 break;3129 break;
3130 case IrInstGenIdAsm:3130 case Stage1AirInstIdAsm:
3131 ir_print_asm_gen(irp, (IrInstGenAsm *)instruction);3131 ir_print_asm_gen(irp, (Stage1AirInstAsm *)instruction);
3132 break;3132 break;
3133 case IrInstGenIdTestNonNull:3133 case Stage1AirInstIdTestNonNull:
3134 ir_print_test_non_null(irp, (IrInstGenTestNonNull *)instruction);3134 ir_print_test_non_null(irp, (Stage1AirInstTestNonNull *)instruction);
3135 break;3135 break;
3136 case IrInstGenIdOptionalUnwrapPtr:3136 case Stage1AirInstIdOptionalUnwrapPtr:
3137 ir_print_optional_unwrap_ptr(irp, (IrInstGenOptionalUnwrapPtr *)instruction);3137 ir_print_optional_unwrap_ptr(irp, (Stage1AirInstOptionalUnwrapPtr *)instruction);
3138 break;3138 break;
3139 case IrInstGenIdPopCount:3139 case Stage1AirInstIdPopCount:
3140 ir_print_pop_count(irp, (IrInstGenPopCount *)instruction);3140 ir_print_pop_count(irp, (Stage1AirInstPopCount *)instruction);
3141 break;3141 break;
3142 case IrInstGenIdClz:3142 case Stage1AirInstIdClz:
3143 ir_print_clz(irp, (IrInstGenClz *)instruction);3143 ir_print_clz(irp, (Stage1AirInstClz *)instruction);
3144 break;3144 break;
3145 case IrInstGenIdCtz:3145 case Stage1AirInstIdCtz:
3146 ir_print_ctz(irp, (IrInstGenCtz *)instruction);3146 ir_print_ctz(irp, (Stage1AirInstCtz *)instruction);
3147 break;3147 break;
3148 case IrInstGenIdBswap:3148 case Stage1AirInstIdBswap:
3149 ir_print_bswap(irp, (IrInstGenBswap *)instruction);3149 ir_print_bswap(irp, (Stage1AirInstBswap *)instruction);
3150 break;3150 break;
3151 case IrInstGenIdBitReverse:3151 case Stage1AirInstIdBitReverse:
3152 ir_print_bit_reverse(irp, (IrInstGenBitReverse *)instruction);3152 ir_print_bit_reverse(irp, (Stage1AirInstBitReverse *)instruction);
3153 break;3153 break;
3154 case IrInstGenIdSwitchBr:3154 case Stage1AirInstIdSwitchBr:
3155 ir_print_switch_br(irp, (IrInstGenSwitchBr *)instruction);3155 ir_print_switch_br(irp, (Stage1AirInstSwitchBr *)instruction);
3156 break;3156 break;
3157 case IrInstGenIdUnionTag:3157 case Stage1AirInstIdUnionTag:
3158 ir_print_union_tag(irp, (IrInstGenUnionTag *)instruction);3158 ir_print_union_tag(irp, (Stage1AirInstUnionTag *)instruction);
3159 break;3159 break;
3160 case IrInstGenIdRef:3160 case Stage1AirInstIdRef:
3161 ir_print_ref_gen(irp, (IrInstGenRef *)instruction);3161 ir_print_ref_gen(irp, (Stage1AirInstRef *)instruction);
3162 break;3162 break;
3163 case IrInstGenIdErrName:3163 case Stage1AirInstIdErrName:
3164 ir_print_err_name(irp, (IrInstGenErrName *)instruction);3164 ir_print_err_name(irp, (Stage1AirInstErrName *)instruction);
3165 break;3165 break;
3166 case IrInstGenIdCmpxchg:3166 case Stage1AirInstIdCmpxchg:
3167 ir_print_cmpxchg_gen(irp, (IrInstGenCmpxchg *)instruction);3167 ir_print_cmpxchg_gen(irp, (Stage1AirInstCmpxchg *)instruction);
3168 break;3168 break;
3169 case IrInstGenIdFence:3169 case Stage1AirInstIdFence:
3170 ir_print_fence(irp, (IrInstGenFence *)instruction);3170 ir_print_fence(irp, (Stage1AirInstFence *)instruction);
3171 break;3171 break;
3172 case IrInstGenIdReduce:3172 case Stage1AirInstIdReduce:
3173 ir_print_reduce(irp, (IrInstGenReduce *)instruction);3173 ir_print_reduce(irp, (Stage1AirInstReduce *)instruction);
3174 break;3174 break;
3175 case IrInstGenIdTruncate:3175 case Stage1AirInstIdTruncate:
3176 ir_print_truncate(irp, (IrInstGenTruncate *)instruction);3176 ir_print_truncate(irp, (Stage1AirInstTruncate *)instruction);
3177 break;3177 break;
3178 case IrInstGenIdShuffleVector:3178 case Stage1AirInstIdShuffleVector:
3179 ir_print_shuffle_vector(irp, (IrInstGenShuffleVector *)instruction);3179 ir_print_shuffle_vector(irp, (Stage1AirInstShuffleVector *)instruction);
3180 break;3180 break;
3181 case IrInstGenIdSplat:3181 case Stage1AirInstIdSplat:
3182 ir_print_splat_gen(irp, (IrInstGenSplat *)instruction);3182 ir_print_splat_gen(irp, (Stage1AirInstSplat *)instruction);
3183 break;3183 break;
3184 case IrInstGenIdBoolNot:3184 case Stage1AirInstIdBoolNot:
3185 ir_print_bool_not(irp, (IrInstGenBoolNot *)instruction);3185 ir_print_bool_not(irp, (Stage1AirInstBoolNot *)instruction);
3186 break;3186 break;
3187 case IrInstGenIdMemset:3187 case Stage1AirInstIdMemset:
3188 ir_print_memset(irp, (IrInstGenMemset *)instruction);3188 ir_print_memset(irp, (Stage1AirInstMemset *)instruction);
3189 break;3189 break;
3190 case IrInstGenIdMemcpy:3190 case Stage1AirInstIdMemcpy:
3191 ir_print_memcpy(irp, (IrInstGenMemcpy *)instruction);3191 ir_print_memcpy(irp, (Stage1AirInstMemcpy *)instruction);
3192 break;3192 break;
3193 case IrInstGenIdSlice:3193 case Stage1AirInstIdSlice:
3194 ir_print_slice_gen(irp, (IrInstGenSlice *)instruction);3194 ir_print_slice_gen(irp, (Stage1AirInstSlice *)instruction);
3195 break;3195 break;
3196 case IrInstGenIdBreakpoint:3196 case Stage1AirInstIdBreakpoint:
3197 ir_print_breakpoint(irp, (IrInstGenBreakpoint *)instruction);3197 ir_print_breakpoint(irp, (Stage1AirInstBreakpoint *)instruction);
3198 break;3198 break;
3199 case IrInstGenIdReturnAddress:3199 case Stage1AirInstIdReturnAddress:
3200 ir_print_return_address(irp, (IrInstGenReturnAddress *)instruction);3200 ir_print_return_address(irp, (Stage1AirInstReturnAddress *)instruction);
3201 break;3201 break;
3202 case IrInstGenIdFrameAddress:3202 case Stage1AirInstIdFrameAddress:
3203 ir_print_frame_address(irp, (IrInstGenFrameAddress *)instruction);3203 ir_print_frame_address(irp, (Stage1AirInstFrameAddress *)instruction);
3204 break;3204 break;
3205 case IrInstGenIdFrameHandle:3205 case Stage1AirInstIdFrameHandle:
3206 ir_print_handle(irp, (IrInstGenFrameHandle *)instruction);3206 ir_print_handle(irp, (Stage1AirInstFrameHandle *)instruction);
3207 break;3207 break;
3208 case IrInstGenIdFrameSize:3208 case Stage1AirInstIdFrameSize:
3209 ir_print_frame_size_gen(irp, (IrInstGenFrameSize *)instruction);3209 ir_print_frame_size_gen(irp, (Stage1AirInstFrameSize *)instruction);
3210 break;3210 break;
3211 case IrInstGenIdOverflowOp:3211 case Stage1AirInstIdOverflowOp:
3212 ir_print_overflow_op(irp, (IrInstGenOverflowOp *)instruction);3212 ir_print_overflow_op(irp, (Stage1AirInstOverflowOp *)instruction);
3213 break;3213 break;
3214 case IrInstGenIdTestErr:3214 case Stage1AirInstIdTestErr:
3215 ir_print_test_err_gen(irp, (IrInstGenTestErr *)instruction);3215 ir_print_test_err_gen(irp, (Stage1AirInstTestErr *)instruction);
3216 break;3216 break;
3217 case IrInstGenIdUnwrapErrCode:3217 case Stage1AirInstIdUnwrapErrCode:
3218 ir_print_unwrap_err_code(irp, (IrInstGenUnwrapErrCode *)instruction);3218 ir_print_unwrap_err_code(irp, (Stage1AirInstUnwrapErrCode *)instruction);
3219 break;3219 break;
3220 case IrInstGenIdUnwrapErrPayload:3220 case Stage1AirInstIdUnwrapErrPayload:
3221 ir_print_unwrap_err_payload(irp, (IrInstGenUnwrapErrPayload *)instruction);3221 ir_print_unwrap_err_payload(irp, (Stage1AirInstUnwrapErrPayload *)instruction);
3222 break;3222 break;
3223 case IrInstGenIdOptionalWrap:3223 case Stage1AirInstIdOptionalWrap:
3224 ir_print_optional_wrap(irp, (IrInstGenOptionalWrap *)instruction);3224 ir_print_optional_wrap(irp, (Stage1AirInstOptionalWrap *)instruction);
3225 break;3225 break;
3226 case IrInstGenIdErrWrapCode:3226 case Stage1AirInstIdErrWrapCode:
3227 ir_print_err_wrap_code(irp, (IrInstGenErrWrapCode *)instruction);3227 ir_print_err_wrap_code(irp, (Stage1AirInstErrWrapCode *)instruction);
3228 break;3228 break;
3229 case IrInstGenIdErrWrapPayload:3229 case Stage1AirInstIdErrWrapPayload:
3230 ir_print_err_wrap_payload(irp, (IrInstGenErrWrapPayload *)instruction);3230 ir_print_err_wrap_payload(irp, (Stage1AirInstErrWrapPayload *)instruction);
3231 break;3231 break;
3232 case IrInstGenIdPtrCast:3232 case Stage1AirInstIdPtrCast:
3233 ir_print_ptr_cast_gen(irp, (IrInstGenPtrCast *)instruction);3233 ir_print_ptr_cast_gen(irp, (Stage1AirInstPtrCast *)instruction);
3234 break;3234 break;
3235 case IrInstGenIdBitCast:3235 case Stage1AirInstIdBitCast:
3236 ir_print_bit_cast_gen(irp, (IrInstGenBitCast *)instruction);3236 ir_print_bit_cast_gen(irp, (Stage1AirInstBitCast *)instruction);
3237 break;3237 break;
3238 case IrInstGenIdWidenOrShorten:3238 case Stage1AirInstIdWidenOrShorten:
3239 ir_print_widen_or_shorten(irp, (IrInstGenWidenOrShorten *)instruction);3239 ir_print_widen_or_shorten(irp, (Stage1AirInstWidenOrShorten *)instruction);
3240 break;3240 break;
3241 case IrInstGenIdPtrToInt:3241 case Stage1AirInstIdPtrToInt:
3242 ir_print_ptr_to_int(irp, (IrInstGenPtrToInt *)instruction);3242 ir_print_ptr_to_int(irp, (Stage1AirInstPtrToInt *)instruction);
3243 break;3243 break;
3244 case IrInstGenIdIntToPtr:3244 case Stage1AirInstIdIntToPtr:
3245 ir_print_int_to_ptr(irp, (IrInstGenIntToPtr *)instruction);3245 ir_print_int_to_ptr(irp, (Stage1AirInstIntToPtr *)instruction);
3246 break;3246 break;
3247 case IrInstGenIdIntToEnum:3247 case Stage1AirInstIdIntToEnum:
3248 ir_print_int_to_enum(irp, (IrInstGenIntToEnum *)instruction);3248 ir_print_int_to_enum(irp, (Stage1AirInstIntToEnum *)instruction);
3249 break;3249 break;
3250 case IrInstGenIdIntToErr:3250 case Stage1AirInstIdIntToErr:
3251 ir_print_int_to_err(irp, (IrInstGenIntToErr *)instruction);3251 ir_print_int_to_err(irp, (Stage1AirInstIntToErr *)instruction);
3252 break;3252 break;
3253 case IrInstGenIdErrToInt:3253 case Stage1AirInstIdErrToInt:
3254 ir_print_err_to_int(irp, (IrInstGenErrToInt *)instruction);3254 ir_print_err_to_int(irp, (Stage1AirInstErrToInt *)instruction);
3255 break;3255 break;
3256 case IrInstGenIdTagName:3256 case Stage1AirInstIdTagName:
3257 ir_print_tag_name(irp, (IrInstGenTagName *)instruction);3257 ir_print_tag_name(irp, (Stage1AirInstTagName *)instruction);
3258 break;3258 break;
3259 case IrInstGenIdPanic:3259 case Stage1AirInstIdPanic:
3260 ir_print_panic(irp, (IrInstGenPanic *)instruction);3260 ir_print_panic(irp, (Stage1AirInstPanic *)instruction);
3261 break;3261 break;
3262 case IrInstGenIdFieldParentPtr:3262 case Stage1AirInstIdFieldParentPtr:
3263 ir_print_field_parent_ptr(irp, (IrInstGenFieldParentPtr *)instruction);3263 ir_print_field_parent_ptr(irp, (Stage1AirInstFieldParentPtr *)instruction);
3264 break;3264 break;
3265 case IrInstGenIdAlignCast:3265 case Stage1AirInstIdAlignCast:
3266 ir_print_align_cast(irp, (IrInstGenAlignCast *)instruction);3266 ir_print_align_cast(irp, (Stage1AirInstAlignCast *)instruction);
3267 break;3267 break;
3268 case IrInstGenIdErrorReturnTrace:3268 case Stage1AirInstIdErrorReturnTrace:
3269 ir_print_error_return_trace(irp, (IrInstGenErrorReturnTrace *)instruction);3269 ir_print_error_return_trace(irp, (Stage1AirInstErrorReturnTrace *)instruction);
3270 break;3270 break;
3271 case IrInstGenIdAtomicRmw:3271 case Stage1AirInstIdAtomicRmw:
3272 ir_print_atomic_rmw(irp, (IrInstGenAtomicRmw *)instruction);3272 ir_print_atomic_rmw(irp, (Stage1AirInstAtomicRmw *)instruction);
3273 break;3273 break;
3274 case IrInstGenIdSaveErrRetAddr:3274 case Stage1AirInstIdSaveErrRetAddr:
3275 ir_print_save_err_ret_addr(irp, (IrInstGenSaveErrRetAddr *)instruction);3275 ir_print_save_err_ret_addr(irp, (Stage1AirInstSaveErrRetAddr *)instruction);
3276 break;3276 break;
3277 case IrInstGenIdFloatOp:3277 case Stage1AirInstIdFloatOp:
3278 ir_print_float_op(irp, (IrInstGenFloatOp *)instruction);3278 ir_print_float_op(irp, (Stage1AirInstFloatOp *)instruction);
3279 break;3279 break;
3280 case IrInstGenIdMulAdd:3280 case Stage1AirInstIdMulAdd:
3281 ir_print_mul_add(irp, (IrInstGenMulAdd *)instruction);3281 ir_print_mul_add(irp, (Stage1AirInstMulAdd *)instruction);
3282 break;3282 break;
3283 case IrInstGenIdAtomicLoad:3283 case Stage1AirInstIdAtomicLoad:
3284 ir_print_atomic_load(irp, (IrInstGenAtomicLoad *)instruction);3284 ir_print_atomic_load(irp, (Stage1AirInstAtomicLoad *)instruction);
3285 break;3285 break;
3286 case IrInstGenIdAtomicStore:3286 case Stage1AirInstIdAtomicStore:
3287 ir_print_atomic_store(irp, (IrInstGenAtomicStore *)instruction);3287 ir_print_atomic_store(irp, (Stage1AirInstAtomicStore *)instruction);
3288 break;3288 break;
3289 case IrInstGenIdArrayToVector:3289 case Stage1AirInstIdArrayToVector:
3290 ir_print_array_to_vector(irp, (IrInstGenArrayToVector *)instruction);3290 ir_print_array_to_vector(irp, (Stage1AirInstArrayToVector *)instruction);
3291 break;3291 break;
3292 case IrInstGenIdVectorToArray:3292 case Stage1AirInstIdVectorToArray:
3293 ir_print_vector_to_array(irp, (IrInstGenVectorToArray *)instruction);3293 ir_print_vector_to_array(irp, (Stage1AirInstVectorToArray *)instruction);
3294 break;3294 break;
3295 case IrInstGenIdPtrOfArrayToSlice:3295 case Stage1AirInstIdPtrOfArrayToSlice:
3296 ir_print_ptr_of_array_to_slice(irp, (IrInstGenPtrOfArrayToSlice *)instruction);3296 ir_print_ptr_of_array_to_slice(irp, (Stage1AirInstPtrOfArrayToSlice *)instruction);
3297 break;3297 break;
3298 case IrInstGenIdAssertZero:3298 case Stage1AirInstIdAssertZero:
3299 ir_print_assert_zero(irp, (IrInstGenAssertZero *)instruction);3299 ir_print_assert_zero(irp, (Stage1AirInstAssertZero *)instruction);
3300 break;3300 break;
3301 case IrInstGenIdAssertNonNull:3301 case Stage1AirInstIdAssertNonNull:
3302 ir_print_assert_non_null(irp, (IrInstGenAssertNonNull *)instruction);3302 ir_print_assert_non_null(irp, (Stage1AirInstAssertNonNull *)instruction);
3303 break;3303 break;
3304 case IrInstGenIdAlloca:3304 case Stage1AirInstIdAlloca:
3305 ir_print_alloca_gen(irp, (IrInstGenAlloca *)instruction);3305 ir_print_alloca_gen(irp, (Stage1AirInstAlloca *)instruction);
3306 break;3306 break;
3307 case IrInstGenIdSuspendBegin:3307 case Stage1AirInstIdSuspendBegin:
3308 ir_print_suspend_begin(irp, (IrInstGenSuspendBegin *)instruction);3308 ir_print_suspend_begin(irp, (Stage1AirInstSuspendBegin *)instruction);
3309 break;3309 break;
3310 case IrInstGenIdSuspendFinish:3310 case Stage1AirInstIdSuspendFinish:
3311 ir_print_suspend_finish(irp, (IrInstGenSuspendFinish *)instruction);3311 ir_print_suspend_finish(irp, (Stage1AirInstSuspendFinish *)instruction);
3312 break;3312 break;
3313 case IrInstGenIdResume:3313 case Stage1AirInstIdResume:
3314 ir_print_resume(irp, (IrInstGenResume *)instruction);3314 ir_print_resume(irp, (Stage1AirInstResume *)instruction);
3315 break;3315 break;
3316 case IrInstGenIdAwait:3316 case Stage1AirInstIdAwait:
3317 ir_print_await_gen(irp, (IrInstGenAwait *)instruction);3317 ir_print_await_gen(irp, (Stage1AirInstAwait *)instruction);
3318 break;3318 break;
3319 case IrInstGenIdSpillBegin:3319 case Stage1AirInstIdSpillBegin:
3320 ir_print_spill_begin(irp, (IrInstGenSpillBegin *)instruction);3320 ir_print_spill_begin(irp, (Stage1AirInstSpillBegin *)instruction);
3321 break;3321 break;
3322 case IrInstGenIdSpillEnd:3322 case Stage1AirInstIdSpillEnd:
3323 ir_print_spill_end(irp, (IrInstGenSpillEnd *)instruction);3323 ir_print_spill_end(irp, (Stage1AirInstSpillEnd *)instruction);
3324 break;3324 break;
3325 case IrInstGenIdVectorExtractElem:3325 case Stage1AirInstIdVectorExtractElem:
3326 ir_print_vector_extract_elem(irp, (IrInstGenVectorExtractElem *)instruction);3326 ir_print_vector_extract_elem(irp, (Stage1AirInstVectorExtractElem *)instruction);
3327 break;3327 break;
3328 case IrInstGenIdVectorStoreElem:3328 case Stage1AirInstIdVectorStoreElem:
3329 ir_print_vector_store_elem(irp, (IrInstGenVectorStoreElem *)instruction);3329 ir_print_vector_store_elem(irp, (Stage1AirInstVectorStoreElem *)instruction);
3330 break;3330 break;
3331 case IrInstGenIdBinaryNot:3331 case Stage1AirInstIdBinaryNot:
3332 ir_print_binary_not(irp, (IrInstGenBinaryNot *)instruction);3332 ir_print_binary_not(irp, (Stage1AirInstBinaryNot *)instruction);
3333 break;3333 break;
3334 case IrInstGenIdNegation:3334 case Stage1AirInstIdNegation:
3335 ir_print_negation(irp, (IrInstGenNegation *)instruction);3335 ir_print_negation(irp, (Stage1AirInstNegation *)instruction);
3336 break;3336 break;
3337 case IrInstGenIdWasmMemorySize:3337 case Stage1AirInstIdWasmMemorySize:
3338 ir_print_wasm_memory_size(irp, (IrInstGenWasmMemorySize *)instruction);3338 ir_print_wasm_memory_size(irp, (Stage1AirInstWasmMemorySize *)instruction);
3339 break;3339 break;
3340 case IrInstGenIdWasmMemoryGrow:3340 case Stage1AirInstIdWasmMemoryGrow:
3341 ir_print_wasm_memory_grow(irp, (IrInstGenWasmMemoryGrow *)instruction);3341 ir_print_wasm_memory_grow(irp, (Stage1AirInstWasmMemoryGrow *)instruction);
3342 break;3342 break;
3343 case IrInstGenIdExtern:3343 case Stage1AirInstIdExtern:
3344 ir_print_extern(irp, (IrInstGenExtern *)instruction);3344 ir_print_extern(irp, (Stage1AirInstExtern *)instruction);
3345 break;3345 break;
33463346
3347 }3347 }
...@@ -3351,15 +3351,15 @@ static void ir_print_inst_gen(IrPrintGen *irp, IrInstGen *instruction, bool trai...@@ -3351,15 +3351,15 @@ static void ir_print_inst_gen(IrPrintGen *irp, IrInstGen *instruction, bool trai
3351static void irp_print_basic_block_src(IrPrintSrc *irp, Stage1ZirBasicBlock *current_block) {3351static void irp_print_basic_block_src(IrPrintSrc *irp, Stage1ZirBasicBlock *current_block) {
3352 fprintf(irp->f, "%s_%" PRIu32 ":\n", current_block->name_hint, current_block->debug_id);3352 fprintf(irp->f, "%s_%" PRIu32 ":\n", current_block->name_hint, current_block->debug_id);
3353 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {3353 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {
3354 IrInstSrc *instruction = current_block->instruction_list.at(instr_i);3354 Stage1ZirInst *instruction = current_block->instruction_list.at(instr_i);
3355 ir_print_inst_src(irp, instruction, false);3355 ir_print_inst_src(irp, instruction, false);
3356 }3356 }
3357}3357}
33583358
3359static void irp_print_basic_block_gen(IrPrintGen *irp, IrBasicBlockGen *current_block) {3359static void irp_print_basic_block_gen(IrPrintGen *irp, Stage1AirBasicBlock *current_block) {
3360 fprintf(irp->f, "%s_%" PRIu32 ":\n", current_block->name_hint, current_block->debug_id);3360 fprintf(irp->f, "%s_%" PRIu32 ":\n", current_block->name_hint, current_block->debug_id);
3361 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {3361 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {
3362 IrInstGen *instruction = current_block->instruction_list.at(instr_i);3362 Stage1AirInst *instruction = current_block->instruction_list.at(instr_i);
3363 irp->printed.put(instruction, 0);3363 irp->printed.put(instruction, 0);
3364 irp->pending.clear();3364 irp->pending.clear();
3365 ir_print_inst_gen(irp, instruction, false);3365 ir_print_inst_gen(irp, instruction, false);
...@@ -3378,7 +3378,7 @@ void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb...@@ -3378,7 +3378,7 @@ void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb
3378 irp_print_basic_block_src(&ir_print, bb);3378 irp_print_basic_block_src(&ir_print, bb);
3379}3379}
33803380
3381void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, IrBasicBlockGen *bb, int indent_size) {3381void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, Stage1AirBasicBlock *bb, int indent_size) {
3382 IrPrintGen ir_print = {};3382 IrPrintGen ir_print = {};
3383 ir_print.codegen = codegen;3383 ir_print.codegen = codegen;
3384 ir_print.f = f;3384 ir_print.f = f;
...@@ -3426,7 +3426,7 @@ void ir_print_gen(CodeGen *codegen, FILE *f, Stage1Air *executable, int indent_s...@@ -3426,7 +3426,7 @@ void ir_print_gen(CodeGen *codegen, FILE *f, Stage1Air *executable, int indent_s
3426 irp->printed.deinit();3426 irp->printed.deinit();
3427}3427}
34283428
3429void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *instruction, int indent_size) {3429void ir_print_inst_src(CodeGen *codegen, FILE *f, Stage1ZirInst *instruction, int indent_size) {
3430 IrPrintSrc ir_print = {};3430 IrPrintSrc ir_print = {};
3431 IrPrintSrc *irp = &ir_print;3431 IrPrintSrc *irp = &ir_print;
3432 irp->codegen = codegen;3432 irp->codegen = codegen;
...@@ -3437,7 +3437,7 @@ void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *instruction, int in...@@ -3437,7 +3437,7 @@ void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *instruction, int in
3437 ir_print_inst_src(irp, instruction, false);3437 ir_print_inst_src(irp, instruction, false);
3438}3438}
34393439
3440void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *instruction, int indent_size) {3440void ir_print_inst_gen(CodeGen *codegen, FILE *f, Stage1AirInst *instruction, int indent_size) {
3441 IrPrintGen ir_print = {};3441 IrPrintGen ir_print = {};
3442 IrPrintGen *irp = &ir_print;3442 IrPrintGen *irp = &ir_print;
3443 irp->codegen = codegen;3443 irp->codegen = codegen;
...@@ -3451,8 +3451,8 @@ void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *instruction, int in...@@ -3451,8 +3451,8 @@ void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *instruction, int in
3451 ir_print_inst_gen(irp, instruction, false);3451 ir_print_inst_gen(irp, instruction, false);
3452}3452}
34533453
3454void IrInstSrc::dump() {3454void Stage1ZirInst::dump() {
3455 IrInstSrc *inst = this;3455 Stage1ZirInst *inst = this;
3456 inst->src();3456 inst->src();
3457 if (inst->scope == nullptr) {3457 if (inst->scope == nullptr) {
3458 fprintf(stderr, "(null scope)\n");3458 fprintf(stderr, "(null scope)\n");
src/stage1/ir_print.hpp+5-5
...@@ -14,12 +14,12 @@...@@ -14,12 +14,12 @@
1414
15void ir_print_src(CodeGen *codegen, FILE *f, Stage1Zir *executable, int indent_size);15void ir_print_src(CodeGen *codegen, FILE *f, Stage1Zir *executable, int indent_size);
16void ir_print_gen(CodeGen *codegen, FILE *f, Stage1Air *executable, int indent_size);16void ir_print_gen(CodeGen *codegen, FILE *f, Stage1Air *executable, int indent_size);
17void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *inst, int indent_size);17void ir_print_inst_src(CodeGen *codegen, FILE *f, Stage1ZirInst *inst, int indent_size);
18void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *inst, int indent_size);18void ir_print_inst_gen(CodeGen *codegen, FILE *f, Stage1AirInst *inst, int indent_size);
19void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb, int indent_size);19void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb, int indent_size);
20void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, IrBasicBlockGen *bb, int indent_size);20void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, Stage1AirBasicBlock *bb, int indent_size);
2121
22const char* ir_inst_src_type_str(IrInstSrcId id);22const char* ir_inst_src_type_str(Stage1ZirInstId id);
23const char* ir_inst_gen_type_str(IrInstGenId id);23const char* ir_inst_gen_type_str(Stage1AirInstId id);
2424
25#endif25#endif