authorgravatar for spexguy070@gmail.comMartin Wickham <spexguy070@gmail.com> 2021-07-10 21:47:07-05:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-07-11 02:00:04-04:00
log75d1b113aa6adf983497a78a0a0e61ecac7aaa54
tree240b0c60d30190d94d672a6baacb5db479f9da74
parent968d1ecf17c0a0774d43965332d00d4ad39743b9

Rename IrInstSrc to Stage1ZirInst and IrInstGen to Stage1AirInst

10 files changed, 6201 insertions(+), 6201 deletions(-)

src/stage1/all_types.hpp+1096-1096
......@@ -31,14 +31,14 @@ struct BuiltinFnEntry;
3131struct TypeStructField;
3232struct CodeGen;
3333struct ZigValue;
34struct IrInstSrc;
35struct IrInstGen;
36struct IrInstGenCast;
37struct IrInstGenAlloca;
38struct IrInstGenCall;
39struct IrInstGenAwait;
34struct Stage1ZirInst;
35struct Stage1AirInst;
36struct Stage1AirInstCast;
37struct Stage1AirInstAlloca;
38struct Stage1AirInstCall;
39struct Stage1AirInstAwait;
4040struct Stage1ZirBasicBlock;
41struct IrBasicBlockGen;
41struct Stage1AirBasicBlock;
4242struct ScopeDecls;
4343struct ZigWindowsSDK;
4444struct Tld;
......@@ -122,7 +122,7 @@ struct Stage1Zir {
122122};
123123
124124struct Stage1Air {
125 ZigList<IrBasicBlockGen *> basic_block_list;
125 ZigList<Stage1AirBasicBlock *> basic_block_list;
126126 Buf *name;
127127 ZigFn *name_fn;
128128 size_t mem_slot_count;
......@@ -311,7 +311,7 @@ struct ConstErrValue {
311311
312312struct ConstBoundFnValue {
313313 ZigFn *fn;
314 IrInstGen *first_arg;
314 Stage1AirInst *first_arg;
315315 AstNode *first_arg_src;
316316};
317317
......@@ -400,14 +400,14 @@ struct LazyValueAlignOf {
400400 LazyValue base;
401401
402402 IrAnalyze *ira;
403 IrInstGen *target_type;
403 Stage1AirInst *target_type;
404404};
405405
406406struct LazyValueSizeOf {
407407 LazyValue base;
408408
409409 IrAnalyze *ira;
410 IrInstGen *target_type;
410 Stage1AirInst *target_type;
411411
412412 bool bit_size;
413413};
......@@ -416,9 +416,9 @@ struct LazyValueSliceType {
416416 LazyValue base;
417417
418418 IrAnalyze *ira;
419 IrInstGen *sentinel; // can be null
420 IrInstGen *elem_type;
421 IrInstGen *align_inst; // can be null
419 Stage1AirInst *sentinel; // can be null
420 Stage1AirInst *elem_type;
421 Stage1AirInst *align_inst; // can be null
422422
423423 bool is_const;
424424 bool is_volatile;
......@@ -429,8 +429,8 @@ struct LazyValueArrayType {
429429 LazyValue base;
430430
431431 IrAnalyze *ira;
432 IrInstGen *sentinel; // can be null
433 IrInstGen *elem_type;
432 Stage1AirInst *sentinel; // can be null
433 Stage1AirInst *elem_type;
434434 uint64_t length;
435435};
436436
......@@ -438,9 +438,9 @@ struct LazyValuePtrType {
438438 LazyValue base;
439439
440440 IrAnalyze *ira;
441 IrInstGen *sentinel; // can be null
442 IrInstGen *elem_type;
443 IrInstGen *align_inst; // can be null
441 Stage1AirInst *sentinel; // can be null
442 Stage1AirInst *elem_type;
443 Stage1AirInst *align_inst; // can be null
444444
445445 PtrLen ptr_len;
446446 uint32_t bit_offset_in_host;
......@@ -455,14 +455,14 @@ struct LazyValuePtrTypeSimple {
455455 LazyValue base;
456456
457457 IrAnalyze *ira;
458 IrInstGen *elem_type;
458 Stage1AirInst *elem_type;
459459};
460460
461461struct LazyValueOptType {
462462 LazyValue base;
463463
464464 IrAnalyze *ira;
465 IrInstGen *payload_type;
465 Stage1AirInst *payload_type;
466466};
467467
468468struct LazyValueFnType {
......@@ -470,9 +470,9 @@ struct LazyValueFnType {
470470
471471 IrAnalyze *ira;
472472 AstNode *proto_node;
473 IrInstGen **param_types;
474 IrInstGen *align_inst; // can be null
475 IrInstGen *return_type;
473 Stage1AirInst **param_types;
474 Stage1AirInst *align_inst; // can be null
475 Stage1AirInst *return_type;
476476
477477 CallingConvention cc;
478478 bool is_generic;
......@@ -482,8 +482,8 @@ struct LazyValueErrUnionType {
482482 LazyValue base;
483483
484484 IrAnalyze *ira;
485 IrInstGen *err_set_type;
486 IrInstGen *payload_type;
485 Stage1AirInst *err_set_type;
486 Stage1AirInst *payload_type;
487487 Buf *type_name;
488488};
489489
......@@ -1651,13 +1651,13 @@ struct ZigFn {
16511651 size_t branch_quota;
16521652 AstNode **param_source_nodes;
16531653 Buf **param_names;
1654 IrInstGen *err_code_spill;
1654 Stage1AirInst *err_code_spill;
16551655 AstNode *assumed_non_async;
16561656
16571657 AstNode *fn_no_inline_set_node;
16581658 AstNode *fn_static_eval_set_node;
16591659
1660 ZigList<IrInstGenAlloca *> alloca_gen_list;
1660 ZigList<Stage1AirInstAlloca *> alloca_gen_list;
16611661 ZigList<ZigVar *> variable_list;
16621662
16631663 Buf *section_name;
......@@ -1669,8 +1669,8 @@ struct ZigFn {
16691669 AstNode *non_async_node;
16701670
16711671 ZigList<GlobalExport> export_list;
1672 ZigList<IrInstGenCall *> call_list;
1673 ZigList<IrInstGenAwait *> await_list;
1672 ZigList<Stage1AirInstCall *> call_list;
1673 ZigList<Stage1AirInstAwait *> await_list;
16741674
16751675 LLVMValueRef valgrind_client_request_array;
16761676
......@@ -2096,9 +2096,9 @@ struct CodeGen {
20962096 Buf *builtin_zig_path;
20972097 Buf *zig_std_special_dir; // Cannot be overridden; derived from zig_lib_dir.
20982098
2099 IrInstSrc *invalid_inst_src;
2100 IrInstGen *invalid_inst_gen;
2101 IrInstGen *unreach_instruction;
2099 Stage1ZirInst *invalid_inst_src;
2100 Stage1AirInst *invalid_inst_gen;
2101 Stage1AirInst *unreach_instruction;
21022102
21032103 ZigValue panic_msg_vals[PanicMsgIdCount];
21042104
......@@ -2165,8 +2165,8 @@ struct ZigVar {
21652165 ZigValue *const_value;
21662166 ZigType *var_type;
21672167 LLVMValueRef value_ref;
2168 IrInstSrc *is_comptime;
2169 IrInstGen *ptr_instruction;
2168 Stage1ZirInst *is_comptime;
2169 Stage1AirInst *ptr_instruction;
21702170 // which node is the declaration of the variable
21712171 AstNode *decl_node;
21722172 ZigLLVMDILocalVariable *di_loc_var;
......@@ -2268,9 +2268,9 @@ struct ScopeBlock {
22682268
22692269 Buf *name;
22702270 Stage1ZirBasicBlock *end_block;
2271 IrInstSrc *is_comptime;
2271 Stage1ZirInst *is_comptime;
22722272 ResultLocPeerParent *peer_parent;
2273 ZigList<IrInstSrc *> *incoming_values;
2273 ZigList<Stage1ZirInst *> *incoming_values;
22742274 ZigList<Stage1ZirBasicBlock *> *incoming_blocks;
22752275
22762276 AstNode *safety_set_node;
......@@ -2325,8 +2325,8 @@ struct ScopeLoop {
23252325 Buf *name;
23262326 Stage1ZirBasicBlock *break_block;
23272327 Stage1ZirBasicBlock *continue_block;
2328 IrInstSrc *is_comptime;
2329 ZigList<IrInstSrc *> *incoming_values;
2328 Stage1ZirInst *is_comptime;
2329 ZigList<Stage1ZirInst *> *incoming_values;
23302330 ZigList<Stage1ZirBasicBlock *> *incoming_blocks;
23312331 ResultLocPeerParent *peer_parent;
23322332 ScopeExpr *spill_scope;
......@@ -2340,7 +2340,7 @@ struct ScopeLoop {
23402340struct ScopeRuntime {
23412341 Scope base;
23422342
2343 IrInstSrc *is_comptime;
2343 Stage1ZirInst *is_comptime;
23442344};
23452345
23462346// This scope is created for a suspend block in order to have labeled
......@@ -2439,11 +2439,11 @@ enum AtomicRmwOp {
24392439// Phi instructions must be first in a basic block.
24402440// The last instruction in a basic block must be of type unreachable.
24412441struct Stage1ZirBasicBlock {
2442 ZigList<IrInstSrc *> instruction_list;
2443 IrBasicBlockGen *child;
2442 ZigList<Stage1ZirInst *> instruction_list;
2443 Stage1AirBasicBlock *child;
24442444 Scope *scope;
24452445 const char *name_hint;
2446 IrInstSrc *suspend_instruction_ref;
2446 Stage1ZirInst *suspend_instruction_ref;
24472447
24482448 uint32_t ref_count;
24492449 uint32_t index; // index into the basic block list
......@@ -2453,8 +2453,8 @@ struct Stage1ZirBasicBlock {
24532453 bool in_resume_stack;
24542454};
24552455
2456struct IrBasicBlockGen {
2457 ZigList<IrInstGen *> instruction_list;
2456struct Stage1AirBasicBlock {
2457 ZigList<Stage1AirInst *> instruction_list;
24582458 Scope *scope;
24592459 const char *name_hint;
24602460 LLVMBasicBlockRef llvm_block;
......@@ -2462,7 +2462,7 @@ struct IrBasicBlockGen {
24622462 // The instruction that referenced this basic block and caused us to
24632463 // analyze the basic block. If the same instruction wants us to emit
24642464 // the same basic block, then we re-generate it instead of saving it.
2465 IrInstSrc *ref_instruction;
2465 Stage1ZirInst *ref_instruction;
24662466 // When this is non-null, a branch to this basic block is only allowed
24672467 // if the branch is comptime. The instruction points to the reason
24682468 // the basic block must be comptime.
......@@ -2475,246 +2475,246 @@ struct IrBasicBlockGen {
24752475// Src instructions are generated by ir_gen_* functions in ir.cpp from AST.
24762476// ir_analyze_* functions consume Src instructions and produce Gen instructions.
24772477// Src instructions do not have type information; Gen instructions do.
2478enum IrInstSrcId : uint8_t {
2479 IrInstSrcIdInvalid,
2480 IrInstSrcIdDeclVar,
2481 IrInstSrcIdBr,
2482 IrInstSrcIdCondBr,
2483 IrInstSrcIdSwitchBr,
2484 IrInstSrcIdSwitchVar,
2485 IrInstSrcIdSwitchElseVar,
2486 IrInstSrcIdSwitchTarget,
2487 IrInstSrcIdPhi,
2488 IrInstSrcIdUnOp,
2489 IrInstSrcIdBinOp,
2490 IrInstSrcIdMergeErrSets,
2491 IrInstSrcIdLoadPtr,
2492 IrInstSrcIdStorePtr,
2493 IrInstSrcIdFieldPtr,
2494 IrInstSrcIdElemPtr,
2495 IrInstSrcIdVarPtr,
2496 IrInstSrcIdCall,
2497 IrInstSrcIdCallArgs,
2498 IrInstSrcIdCallExtra,
2499 IrInstSrcIdAsyncCallExtra,
2500 IrInstSrcIdConst,
2501 IrInstSrcIdReturn,
2502 IrInstSrcIdContainerInitList,
2503 IrInstSrcIdContainerInitFields,
2504 IrInstSrcIdUnreachable,
2505 IrInstSrcIdTypeOf,
2506 IrInstSrcIdSetCold,
2507 IrInstSrcIdSetRuntimeSafety,
2508 IrInstSrcIdSetFloatMode,
2509 IrInstSrcIdArrayType,
2510 IrInstSrcIdAnyFrameType,
2511 IrInstSrcIdSliceType,
2512 IrInstSrcIdAsm,
2513 IrInstSrcIdSizeOf,
2514 IrInstSrcIdTestNonNull,
2515 IrInstSrcIdOptionalUnwrapPtr,
2516 IrInstSrcIdClz,
2517 IrInstSrcIdCtz,
2518 IrInstSrcIdPopCount,
2519 IrInstSrcIdBswap,
2520 IrInstSrcIdBitReverse,
2521 IrInstSrcIdImport,
2522 IrInstSrcIdCImport,
2523 IrInstSrcIdCInclude,
2524 IrInstSrcIdCDefine,
2525 IrInstSrcIdCUndef,
2526 IrInstSrcIdRef,
2527 IrInstSrcIdCompileErr,
2528 IrInstSrcIdCompileLog,
2529 IrInstSrcIdErrName,
2530 IrInstSrcIdEmbedFile,
2531 IrInstSrcIdCmpxchg,
2532 IrInstSrcIdFence,
2533 IrInstSrcIdReduce,
2534 IrInstSrcIdTruncate,
2535 IrInstSrcIdIntCast,
2536 IrInstSrcIdFloatCast,
2537 IrInstSrcIdIntToFloat,
2538 IrInstSrcIdFloatToInt,
2539 IrInstSrcIdBoolToInt,
2540 IrInstSrcIdVectorType,
2541 IrInstSrcIdShuffleVector,
2542 IrInstSrcIdSplat,
2543 IrInstSrcIdBoolNot,
2544 IrInstSrcIdMemset,
2545 IrInstSrcIdMemcpy,
2546 IrInstSrcIdSlice,
2547 IrInstSrcIdBreakpoint,
2548 IrInstSrcIdReturnAddress,
2549 IrInstSrcIdFrameAddress,
2550 IrInstSrcIdFrameHandle,
2551 IrInstSrcIdFrameType,
2552 IrInstSrcIdFrameSize,
2553 IrInstSrcIdAlignOf,
2554 IrInstSrcIdOverflowOp,
2555 IrInstSrcIdTestErr,
2556 IrInstSrcIdMulAdd,
2557 IrInstSrcIdFloatOp,
2558 IrInstSrcIdUnwrapErrCode,
2559 IrInstSrcIdUnwrapErrPayload,
2560 IrInstSrcIdFnProto,
2561 IrInstSrcIdTestComptime,
2562 IrInstSrcIdPtrCast,
2563 IrInstSrcIdBitCast,
2564 IrInstSrcIdIntToPtr,
2565 IrInstSrcIdPtrToInt,
2566 IrInstSrcIdIntToEnum,
2567 IrInstSrcIdEnumToInt,
2568 IrInstSrcIdIntToErr,
2569 IrInstSrcIdErrToInt,
2570 IrInstSrcIdCheckSwitchProngsUnderYes,
2571 IrInstSrcIdCheckSwitchProngsUnderNo,
2572 IrInstSrcIdCheckStatementIsVoid,
2573 IrInstSrcIdTypeName,
2574 IrInstSrcIdDeclRef,
2575 IrInstSrcIdPanic,
2576 IrInstSrcIdTagName,
2577 IrInstSrcIdFieldParentPtr,
2578 IrInstSrcIdOffsetOf,
2579 IrInstSrcIdBitOffsetOf,
2580 IrInstSrcIdTypeInfo,
2581 IrInstSrcIdType,
2582 IrInstSrcIdHasField,
2583 IrInstSrcIdSetEvalBranchQuota,
2584 IrInstSrcIdPtrType,
2585 IrInstSrcIdPtrTypeSimple,
2586 IrInstSrcIdPtrTypeSimpleConst,
2587 IrInstSrcIdAlignCast,
2588 IrInstSrcIdImplicitCast,
2589 IrInstSrcIdResolveResult,
2590 IrInstSrcIdResetResult,
2591 IrInstSrcIdSetAlignStack,
2592 IrInstSrcIdArgTypeAllowVarFalse,
2593 IrInstSrcIdArgTypeAllowVarTrue,
2594 IrInstSrcIdExport,
2595 IrInstSrcIdExtern,
2596 IrInstSrcIdErrorReturnTrace,
2597 IrInstSrcIdErrorUnion,
2598 IrInstSrcIdAtomicRmw,
2599 IrInstSrcIdAtomicLoad,
2600 IrInstSrcIdAtomicStore,
2601 IrInstSrcIdSaveErrRetAddr,
2602 IrInstSrcIdAddImplicitReturnType,
2603 IrInstSrcIdErrSetCast,
2604 IrInstSrcIdCheckRuntimeScope,
2605 IrInstSrcIdHasDecl,
2606 IrInstSrcIdUndeclaredIdent,
2607 IrInstSrcIdAlloca,
2608 IrInstSrcIdEndExpr,
2609 IrInstSrcIdUnionInitNamedField,
2610 IrInstSrcIdSuspendBegin,
2611 IrInstSrcIdSuspendFinish,
2612 IrInstSrcIdAwait,
2613 IrInstSrcIdResume,
2614 IrInstSrcIdSpillBegin,
2615 IrInstSrcIdSpillEnd,
2616 IrInstSrcIdWasmMemorySize,
2617 IrInstSrcIdWasmMemoryGrow,
2618 IrInstSrcIdSrc,
2478enum Stage1ZirInstId : uint8_t {
2479 Stage1ZirInstIdInvalid,
2480 Stage1ZirInstIdDeclVar,
2481 Stage1ZirInstIdBr,
2482 Stage1ZirInstIdCondBr,
2483 Stage1ZirInstIdSwitchBr,
2484 Stage1ZirInstIdSwitchVar,
2485 Stage1ZirInstIdSwitchElseVar,
2486 Stage1ZirInstIdSwitchTarget,
2487 Stage1ZirInstIdPhi,
2488 Stage1ZirInstIdUnOp,
2489 Stage1ZirInstIdBinOp,
2490 Stage1ZirInstIdMergeErrSets,
2491 Stage1ZirInstIdLoadPtr,
2492 Stage1ZirInstIdStorePtr,
2493 Stage1ZirInstIdFieldPtr,
2494 Stage1ZirInstIdElemPtr,
2495 Stage1ZirInstIdVarPtr,
2496 Stage1ZirInstIdCall,
2497 Stage1ZirInstIdCallArgs,
2498 Stage1ZirInstIdCallExtra,
2499 Stage1ZirInstIdAsyncCallExtra,
2500 Stage1ZirInstIdConst,
2501 Stage1ZirInstIdReturn,
2502 Stage1ZirInstIdContainerInitList,
2503 Stage1ZirInstIdContainerInitFields,
2504 Stage1ZirInstIdUnreachable,
2505 Stage1ZirInstIdTypeOf,
2506 Stage1ZirInstIdSetCold,
2507 Stage1ZirInstIdSetRuntimeSafety,
2508 Stage1ZirInstIdSetFloatMode,
2509 Stage1ZirInstIdArrayType,
2510 Stage1ZirInstIdAnyFrameType,
2511 Stage1ZirInstIdSliceType,
2512 Stage1ZirInstIdAsm,
2513 Stage1ZirInstIdSizeOf,
2514 Stage1ZirInstIdTestNonNull,
2515 Stage1ZirInstIdOptionalUnwrapPtr,
2516 Stage1ZirInstIdClz,
2517 Stage1ZirInstIdCtz,
2518 Stage1ZirInstIdPopCount,
2519 Stage1ZirInstIdBswap,
2520 Stage1ZirInstIdBitReverse,
2521 Stage1ZirInstIdImport,
2522 Stage1ZirInstIdCImport,
2523 Stage1ZirInstIdCInclude,
2524 Stage1ZirInstIdCDefine,
2525 Stage1ZirInstIdCUndef,
2526 Stage1ZirInstIdRef,
2527 Stage1ZirInstIdCompileErr,
2528 Stage1ZirInstIdCompileLog,
2529 Stage1ZirInstIdErrName,
2530 Stage1ZirInstIdEmbedFile,
2531 Stage1ZirInstIdCmpxchg,
2532 Stage1ZirInstIdFence,
2533 Stage1ZirInstIdReduce,
2534 Stage1ZirInstIdTruncate,
2535 Stage1ZirInstIdIntCast,
2536 Stage1ZirInstIdFloatCast,
2537 Stage1ZirInstIdIntToFloat,
2538 Stage1ZirInstIdFloatToInt,
2539 Stage1ZirInstIdBoolToInt,
2540 Stage1ZirInstIdVectorType,
2541 Stage1ZirInstIdShuffleVector,
2542 Stage1ZirInstIdSplat,
2543 Stage1ZirInstIdBoolNot,
2544 Stage1ZirInstIdMemset,
2545 Stage1ZirInstIdMemcpy,
2546 Stage1ZirInstIdSlice,
2547 Stage1ZirInstIdBreakpoint,
2548 Stage1ZirInstIdReturnAddress,
2549 Stage1ZirInstIdFrameAddress,
2550 Stage1ZirInstIdFrameHandle,
2551 Stage1ZirInstIdFrameType,
2552 Stage1ZirInstIdFrameSize,
2553 Stage1ZirInstIdAlignOf,
2554 Stage1ZirInstIdOverflowOp,
2555 Stage1ZirInstIdTestErr,
2556 Stage1ZirInstIdMulAdd,
2557 Stage1ZirInstIdFloatOp,
2558 Stage1ZirInstIdUnwrapErrCode,
2559 Stage1ZirInstIdUnwrapErrPayload,
2560 Stage1ZirInstIdFnProto,
2561 Stage1ZirInstIdTestComptime,
2562 Stage1ZirInstIdPtrCast,
2563 Stage1ZirInstIdBitCast,
2564 Stage1ZirInstIdIntToPtr,
2565 Stage1ZirInstIdPtrToInt,
2566 Stage1ZirInstIdIntToEnum,
2567 Stage1ZirInstIdEnumToInt,
2568 Stage1ZirInstIdIntToErr,
2569 Stage1ZirInstIdErrToInt,
2570 Stage1ZirInstIdCheckSwitchProngsUnderYes,
2571 Stage1ZirInstIdCheckSwitchProngsUnderNo,
2572 Stage1ZirInstIdCheckStatementIsVoid,
2573 Stage1ZirInstIdTypeName,
2574 Stage1ZirInstIdDeclRef,
2575 Stage1ZirInstIdPanic,
2576 Stage1ZirInstIdTagName,
2577 Stage1ZirInstIdFieldParentPtr,
2578 Stage1ZirInstIdOffsetOf,
2579 Stage1ZirInstIdBitOffsetOf,
2580 Stage1ZirInstIdTypeInfo,
2581 Stage1ZirInstIdType,
2582 Stage1ZirInstIdHasField,
2583 Stage1ZirInstIdSetEvalBranchQuota,
2584 Stage1ZirInstIdPtrType,
2585 Stage1ZirInstIdPtrTypeSimple,
2586 Stage1ZirInstIdPtrTypeSimpleConst,
2587 Stage1ZirInstIdAlignCast,
2588 Stage1ZirInstIdImplicitCast,
2589 Stage1ZirInstIdResolveResult,
2590 Stage1ZirInstIdResetResult,
2591 Stage1ZirInstIdSetAlignStack,
2592 Stage1ZirInstIdArgTypeAllowVarFalse,
2593 Stage1ZirInstIdArgTypeAllowVarTrue,
2594 Stage1ZirInstIdExport,
2595 Stage1ZirInstIdExtern,
2596 Stage1ZirInstIdErrorReturnTrace,
2597 Stage1ZirInstIdErrorUnion,
2598 Stage1ZirInstIdAtomicRmw,
2599 Stage1ZirInstIdAtomicLoad,
2600 Stage1ZirInstIdAtomicStore,
2601 Stage1ZirInstIdSaveErrRetAddr,
2602 Stage1ZirInstIdAddImplicitReturnType,
2603 Stage1ZirInstIdErrSetCast,
2604 Stage1ZirInstIdCheckRuntimeScope,
2605 Stage1ZirInstIdHasDecl,
2606 Stage1ZirInstIdUndeclaredIdent,
2607 Stage1ZirInstIdAlloca,
2608 Stage1ZirInstIdEndExpr,
2609 Stage1ZirInstIdUnionInitNamedField,
2610 Stage1ZirInstIdSuspendBegin,
2611 Stage1ZirInstIdSuspendFinish,
2612 Stage1ZirInstIdAwait,
2613 Stage1ZirInstIdResume,
2614 Stage1ZirInstIdSpillBegin,
2615 Stage1ZirInstIdSpillEnd,
2616 Stage1ZirInstIdWasmMemorySize,
2617 Stage1ZirInstIdWasmMemoryGrow,
2618 Stage1ZirInstIdSrc,
26192619};
26202620
26212621// ir_render_* functions in codegen.cpp consume Gen instructions and produce LLVM IR.
26222622// Src instructions do not have type information; Gen instructions do.
2623enum IrInstGenId : uint8_t {
2624 IrInstGenIdInvalid,
2625 IrInstGenIdDeclVar,
2626 IrInstGenIdBr,
2627 IrInstGenIdCondBr,
2628 IrInstGenIdSwitchBr,
2629 IrInstGenIdPhi,
2630 IrInstGenIdBinaryNot,
2631 IrInstGenIdNegation,
2632 IrInstGenIdBinOp,
2633 IrInstGenIdLoadPtr,
2634 IrInstGenIdStorePtr,
2635 IrInstGenIdVectorStoreElem,
2636 IrInstGenIdStructFieldPtr,
2637 IrInstGenIdUnionFieldPtr,
2638 IrInstGenIdElemPtr,
2639 IrInstGenIdVarPtr,
2640 IrInstGenIdReturnPtr,
2641 IrInstGenIdCall,
2642 IrInstGenIdReturn,
2643 IrInstGenIdCast,
2644 IrInstGenIdUnreachable,
2645 IrInstGenIdAsm,
2646 IrInstGenIdTestNonNull,
2647 IrInstGenIdOptionalUnwrapPtr,
2648 IrInstGenIdOptionalWrap,
2649 IrInstGenIdUnionTag,
2650 IrInstGenIdClz,
2651 IrInstGenIdCtz,
2652 IrInstGenIdPopCount,
2653 IrInstGenIdBswap,
2654 IrInstGenIdBitReverse,
2655 IrInstGenIdRef,
2656 IrInstGenIdErrName,
2657 IrInstGenIdCmpxchg,
2658 IrInstGenIdFence,
2659 IrInstGenIdReduce,
2660 IrInstGenIdTruncate,
2661 IrInstGenIdShuffleVector,
2662 IrInstGenIdSplat,
2663 IrInstGenIdBoolNot,
2664 IrInstGenIdMemset,
2665 IrInstGenIdMemcpy,
2666 IrInstGenIdSlice,
2667 IrInstGenIdBreakpoint,
2668 IrInstGenIdReturnAddress,
2669 IrInstGenIdFrameAddress,
2670 IrInstGenIdFrameHandle,
2671 IrInstGenIdFrameSize,
2672 IrInstGenIdOverflowOp,
2673 IrInstGenIdTestErr,
2674 IrInstGenIdMulAdd,
2675 IrInstGenIdFloatOp,
2676 IrInstGenIdUnwrapErrCode,
2677 IrInstGenIdUnwrapErrPayload,
2678 IrInstGenIdErrWrapCode,
2679 IrInstGenIdErrWrapPayload,
2680 IrInstGenIdPtrCast,
2681 IrInstGenIdBitCast,
2682 IrInstGenIdWidenOrShorten,
2683 IrInstGenIdIntToPtr,
2684 IrInstGenIdPtrToInt,
2685 IrInstGenIdIntToEnum,
2686 IrInstGenIdIntToErr,
2687 IrInstGenIdErrToInt,
2688 IrInstGenIdPanic,
2689 IrInstGenIdTagName,
2690 IrInstGenIdFieldParentPtr,
2691 IrInstGenIdAlignCast,
2692 IrInstGenIdErrorReturnTrace,
2693 IrInstGenIdAtomicRmw,
2694 IrInstGenIdAtomicLoad,
2695 IrInstGenIdAtomicStore,
2696 IrInstGenIdSaveErrRetAddr,
2697 IrInstGenIdVectorToArray,
2698 IrInstGenIdArrayToVector,
2699 IrInstGenIdAssertZero,
2700 IrInstGenIdAssertNonNull,
2701 IrInstGenIdPtrOfArrayToSlice,
2702 IrInstGenIdSuspendBegin,
2703 IrInstGenIdSuspendFinish,
2704 IrInstGenIdAwait,
2705 IrInstGenIdResume,
2706 IrInstGenIdSpillBegin,
2707 IrInstGenIdSpillEnd,
2708 IrInstGenIdVectorExtractElem,
2709 IrInstGenIdAlloca,
2710 IrInstGenIdConst,
2711 IrInstGenIdWasmMemorySize,
2712 IrInstGenIdWasmMemoryGrow,
2713 IrInstGenIdExtern,
2714};
2715
2716struct IrInstSrc {
2717 IrInstSrcId id;
2623enum Stage1AirInstId : uint8_t {
2624 Stage1AirInstIdInvalid,
2625 Stage1AirInstIdDeclVar,
2626 Stage1AirInstIdBr,
2627 Stage1AirInstIdCondBr,
2628 Stage1AirInstIdSwitchBr,
2629 Stage1AirInstIdPhi,
2630 Stage1AirInstIdBinaryNot,
2631 Stage1AirInstIdNegation,
2632 Stage1AirInstIdBinOp,
2633 Stage1AirInstIdLoadPtr,
2634 Stage1AirInstIdStorePtr,
2635 Stage1AirInstIdVectorStoreElem,
2636 Stage1AirInstIdStructFieldPtr,
2637 Stage1AirInstIdUnionFieldPtr,
2638 Stage1AirInstIdElemPtr,
2639 Stage1AirInstIdVarPtr,
2640 Stage1AirInstIdReturnPtr,
2641 Stage1AirInstIdCall,
2642 Stage1AirInstIdReturn,
2643 Stage1AirInstIdCast,
2644 Stage1AirInstIdUnreachable,
2645 Stage1AirInstIdAsm,
2646 Stage1AirInstIdTestNonNull,
2647 Stage1AirInstIdOptionalUnwrapPtr,
2648 Stage1AirInstIdOptionalWrap,
2649 Stage1AirInstIdUnionTag,
2650 Stage1AirInstIdClz,
2651 Stage1AirInstIdCtz,
2652 Stage1AirInstIdPopCount,
2653 Stage1AirInstIdBswap,
2654 Stage1AirInstIdBitReverse,
2655 Stage1AirInstIdRef,
2656 Stage1AirInstIdErrName,
2657 Stage1AirInstIdCmpxchg,
2658 Stage1AirInstIdFence,
2659 Stage1AirInstIdReduce,
2660 Stage1AirInstIdTruncate,
2661 Stage1AirInstIdShuffleVector,
2662 Stage1AirInstIdSplat,
2663 Stage1AirInstIdBoolNot,
2664 Stage1AirInstIdMemset,
2665 Stage1AirInstIdMemcpy,
2666 Stage1AirInstIdSlice,
2667 Stage1AirInstIdBreakpoint,
2668 Stage1AirInstIdReturnAddress,
2669 Stage1AirInstIdFrameAddress,
2670 Stage1AirInstIdFrameHandle,
2671 Stage1AirInstIdFrameSize,
2672 Stage1AirInstIdOverflowOp,
2673 Stage1AirInstIdTestErr,
2674 Stage1AirInstIdMulAdd,
2675 Stage1AirInstIdFloatOp,
2676 Stage1AirInstIdUnwrapErrCode,
2677 Stage1AirInstIdUnwrapErrPayload,
2678 Stage1AirInstIdErrWrapCode,
2679 Stage1AirInstIdErrWrapPayload,
2680 Stage1AirInstIdPtrCast,
2681 Stage1AirInstIdBitCast,
2682 Stage1AirInstIdWidenOrShorten,
2683 Stage1AirInstIdIntToPtr,
2684 Stage1AirInstIdPtrToInt,
2685 Stage1AirInstIdIntToEnum,
2686 Stage1AirInstIdIntToErr,
2687 Stage1AirInstIdErrToInt,
2688 Stage1AirInstIdPanic,
2689 Stage1AirInstIdTagName,
2690 Stage1AirInstIdFieldParentPtr,
2691 Stage1AirInstIdAlignCast,
2692 Stage1AirInstIdErrorReturnTrace,
2693 Stage1AirInstIdAtomicRmw,
2694 Stage1AirInstIdAtomicLoad,
2695 Stage1AirInstIdAtomicStore,
2696 Stage1AirInstIdSaveErrRetAddr,
2697 Stage1AirInstIdVectorToArray,
2698 Stage1AirInstIdArrayToVector,
2699 Stage1AirInstIdAssertZero,
2700 Stage1AirInstIdAssertNonNull,
2701 Stage1AirInstIdPtrOfArrayToSlice,
2702 Stage1AirInstIdSuspendBegin,
2703 Stage1AirInstIdSuspendFinish,
2704 Stage1AirInstIdAwait,
2705 Stage1AirInstIdResume,
2706 Stage1AirInstIdSpillBegin,
2707 Stage1AirInstIdSpillEnd,
2708 Stage1AirInstIdVectorExtractElem,
2709 Stage1AirInstIdAlloca,
2710 Stage1AirInstIdConst,
2711 Stage1AirInstIdWasmMemorySize,
2712 Stage1AirInstIdWasmMemoryGrow,
2713 Stage1AirInstIdExtern,
2714};
2715
2716struct Stage1ZirInst {
2717 Stage1ZirInstId id;
27182718 uint16_t ref_count;
27192719 uint32_t debug_id;
27202720
......@@ -2724,7 +2724,7 @@ struct IrInstSrc {
27242724 // When analyzing IR, instructions that point to this instruction in the "old ir"
27252725 // can find the instruction that corresponds to this value in the "new ir"
27262726 // with this child field.
2727 IrInstGen *child;
2727 Stage1AirInst *child;
27282728 Stage1ZirBasicBlock *owner_bb;
27292729
27302730 // for debugging purposes, these are useful to call to inspect the instruction
......@@ -2732,8 +2732,8 @@ struct IrInstSrc {
27322732 void src();
27332733};
27342734
2735struct IrInstGen {
2736 IrInstGenId id;
2735struct Stage1AirInst {
2736 Stage1AirInstId id;
27372737 // if ref_count is zero and the instruction has no side effects,
27382738 // the instruction can be omitted in codegen
27392739 uint16_t ref_count;
......@@ -2744,130 +2744,130 @@ struct IrInstGen {
27442744
27452745 LLVMValueRef llvm_value;
27462746 ZigValue *value;
2747 IrBasicBlockGen *owner_bb;
2747 Stage1AirBasicBlock *owner_bb;
27482748 // Nearly any instruction can have to be stored as a local variable before suspending
27492749 // and then loaded after resuming, in case there is an expression with a suspend point
27502750 // in it, such as: x + await y
2751 IrInstGen *spill;
2751 Stage1AirInst *spill;
27522752
27532753 // for debugging purposes, these are useful to call to inspect the instruction
27542754 void dump();
27552755 void src();
27562756};
27572757
2758struct IrInstSrcDeclVar {
2759 IrInstSrc base;
2758struct Stage1ZirInstDeclVar {
2759 Stage1ZirInst base;
27602760
27612761 ZigVar *var;
2762 IrInstSrc *var_type;
2763 IrInstSrc *align_value;
2764 IrInstSrc *ptr;
2762 Stage1ZirInst *var_type;
2763 Stage1ZirInst *align_value;
2764 Stage1ZirInst *ptr;
27652765};
27662766
2767struct IrInstGenDeclVar {
2768 IrInstGen base;
2767struct Stage1AirInstDeclVar {
2768 Stage1AirInst base;
27692769
27702770 ZigVar *var;
2771 IrInstGen *var_ptr;
2771 Stage1AirInst *var_ptr;
27722772};
27732773
2774struct IrInstSrcCondBr {
2775 IrInstSrc base;
2774struct Stage1ZirInstCondBr {
2775 Stage1ZirInst base;
27762776
2777 IrInstSrc *condition;
2777 Stage1ZirInst *condition;
27782778 Stage1ZirBasicBlock *then_block;
27792779 Stage1ZirBasicBlock *else_block;
2780 IrInstSrc *is_comptime;
2780 Stage1ZirInst *is_comptime;
27812781 ResultLoc *result_loc;
27822782};
27832783
2784struct IrInstGenCondBr {
2785 IrInstGen base;
2784struct Stage1AirInstCondBr {
2785 Stage1AirInst base;
27862786
2787 IrInstGen *condition;
2788 IrBasicBlockGen *then_block;
2789 IrBasicBlockGen *else_block;
2787 Stage1AirInst *condition;
2788 Stage1AirBasicBlock *then_block;
2789 Stage1AirBasicBlock *else_block;
27902790};
27912791
2792struct IrInstSrcBr {
2793 IrInstSrc base;
2792struct Stage1ZirInstBr {
2793 Stage1ZirInst base;
27942794
27952795 Stage1ZirBasicBlock *dest_block;
2796 IrInstSrc *is_comptime;
2796 Stage1ZirInst *is_comptime;
27972797};
27982798
2799struct IrInstGenBr {
2800 IrInstGen base;
2799struct Stage1AirInstBr {
2800 Stage1AirInst base;
28012801
2802 IrBasicBlockGen *dest_block;
2802 Stage1AirBasicBlock *dest_block;
28032803};
28042804
2805struct IrInstSrcSwitchBrCase {
2806 IrInstSrc *value;
2805struct Stage1ZirInstSwitchBrCase {
2806 Stage1ZirInst *value;
28072807 Stage1ZirBasicBlock *block;
28082808};
28092809
2810struct IrInstSrcSwitchBr {
2811 IrInstSrc base;
2810struct Stage1ZirInstSwitchBr {
2811 Stage1ZirInst base;
28122812
2813 IrInstSrc *target_value;
2813 Stage1ZirInst *target_value;
28142814 Stage1ZirBasicBlock *else_block;
28152815 size_t case_count;
2816 IrInstSrcSwitchBrCase *cases;
2817 IrInstSrc *is_comptime;
2818 IrInstSrc *switch_prongs_void;
2816 Stage1ZirInstSwitchBrCase *cases;
2817 Stage1ZirInst *is_comptime;
2818 Stage1ZirInst *switch_prongs_void;
28192819};
28202820
2821struct IrInstGenSwitchBrCase {
2822 IrInstGen *value;
2823 IrBasicBlockGen *block;
2821struct Stage1AirInstSwitchBrCase {
2822 Stage1AirInst *value;
2823 Stage1AirBasicBlock *block;
28242824};
28252825
2826struct IrInstGenSwitchBr {
2827 IrInstGen base;
2826struct Stage1AirInstSwitchBr {
2827 Stage1AirInst base;
28282828
2829 IrInstGen *target_value;
2830 IrBasicBlockGen *else_block;
2829 Stage1AirInst *target_value;
2830 Stage1AirBasicBlock *else_block;
28312831 size_t case_count;
2832 IrInstGenSwitchBrCase *cases;
2832 Stage1AirInstSwitchBrCase *cases;
28332833};
28342834
2835struct IrInstSrcSwitchVar {
2836 IrInstSrc base;
2835struct Stage1ZirInstSwitchVar {
2836 Stage1ZirInst base;
28372837
2838 IrInstSrc *target_value_ptr;
2839 IrInstSrc **prongs_ptr;
2838 Stage1ZirInst *target_value_ptr;
2839 Stage1ZirInst **prongs_ptr;
28402840 size_t prongs_len;
28412841};
28422842
2843struct IrInstSrcSwitchElseVar {
2844 IrInstSrc base;
2843struct Stage1ZirInstSwitchElseVar {
2844 Stage1ZirInst base;
28452845
2846 IrInstSrc *target_value_ptr;
2847 IrInstSrcSwitchBr *switch_br;
2846 Stage1ZirInst *target_value_ptr;
2847 Stage1ZirInstSwitchBr *switch_br;
28482848};
28492849
2850struct IrInstSrcSwitchTarget {
2851 IrInstSrc base;
2850struct Stage1ZirInstSwitchTarget {
2851 Stage1ZirInst base;
28522852
2853 IrInstSrc *target_value_ptr;
2853 Stage1ZirInst *target_value_ptr;
28542854};
28552855
2856struct IrInstSrcPhi {
2857 IrInstSrc base;
2856struct Stage1ZirInstPhi {
2857 Stage1ZirInst base;
28582858
28592859 size_t incoming_count;
28602860 Stage1ZirBasicBlock **incoming_blocks;
2861 IrInstSrc **incoming_values;
2861 Stage1ZirInst **incoming_values;
28622862 ResultLocPeerParent *peer_parent;
28632863};
28642864
2865struct IrInstGenPhi {
2866 IrInstGen base;
2865struct Stage1AirInstPhi {
2866 Stage1AirInst base;
28672867
28682868 size_t incoming_count;
2869 IrBasicBlockGen **incoming_blocks;
2870 IrInstGen **incoming_values;
2869 Stage1AirBasicBlock **incoming_blocks;
2870 Stage1AirInst **incoming_values;
28712871};
28722872
28732873enum IrUnOp {
......@@ -2879,23 +2879,23 @@ enum IrUnOp {
28792879 IrUnOpOptional,
28802880};
28812881
2882struct IrInstSrcUnOp {
2883 IrInstSrc base;
2882struct Stage1ZirInstUnOp {
2883 Stage1ZirInst base;
28842884
28852885 IrUnOp op_id;
28862886 LVal lval;
2887 IrInstSrc *value;
2887 Stage1ZirInst *value;
28882888 ResultLoc *result_loc;
28892889};
28902890
2891struct IrInstGenBinaryNot {
2892 IrInstGen base;
2893 IrInstGen *operand;
2891struct Stage1AirInstBinaryNot {
2892 Stage1AirInst base;
2893 Stage1AirInst *operand;
28942894};
28952895
2896struct IrInstGenNegation {
2897 IrInstGen base;
2898 IrInstGen *operand;
2896struct Stage1AirInstNegation {
2897 Stage1AirInst base;
2898 Stage1AirInst *operand;
28992899 bool wrapping;
29002900};
29012901
......@@ -2933,122 +2933,122 @@ enum IrBinOp {
29332933 IrBinOpArrayMult,
29342934};
29352935
2936struct IrInstSrcBinOp {
2937 IrInstSrc base;
2936struct Stage1ZirInstBinOp {
2937 Stage1ZirInst base;
29382938
2939 IrInstSrc *op1;
2940 IrInstSrc *op2;
2939 Stage1ZirInst *op1;
2940 Stage1ZirInst *op2;
29412941 IrBinOp op_id;
29422942 bool safety_check_on;
29432943};
29442944
2945struct IrInstGenBinOp {
2946 IrInstGen base;
2945struct Stage1AirInstBinOp {
2946 Stage1AirInst base;
29472947
2948 IrInstGen *op1;
2949 IrInstGen *op2;
2948 Stage1AirInst *op1;
2949 Stage1AirInst *op2;
29502950 IrBinOp op_id;
29512951 bool safety_check_on;
29522952};
29532953
2954struct IrInstSrcMergeErrSets {
2955 IrInstSrc base;
2954struct Stage1ZirInstMergeErrSets {
2955 Stage1ZirInst base;
29562956
2957 IrInstSrc *op1;
2958 IrInstSrc *op2;
2957 Stage1ZirInst *op1;
2958 Stage1ZirInst *op2;
29592959 Buf *type_name;
29602960};
29612961
2962struct IrInstSrcLoadPtr {
2963 IrInstSrc base;
2962struct Stage1ZirInstLoadPtr {
2963 Stage1ZirInst base;
29642964
2965 IrInstSrc *ptr;
2965 Stage1ZirInst *ptr;
29662966};
29672967
2968struct IrInstGenLoadPtr {
2969 IrInstGen base;
2968struct Stage1AirInstLoadPtr {
2969 Stage1AirInst base;
29702970
2971 IrInstGen *ptr;
2972 IrInstGen *result_loc;
2971 Stage1AirInst *ptr;
2972 Stage1AirInst *result_loc;
29732973};
29742974
2975struct IrInstSrcStorePtr {
2976 IrInstSrc base;
2975struct Stage1ZirInstStorePtr {
2976 Stage1ZirInst base;
29772977
2978 IrInstSrc *ptr;
2979 IrInstSrc *value;
2978 Stage1ZirInst *ptr;
2979 Stage1ZirInst *value;
29802980
29812981 bool allow_write_through_const;
29822982};
29832983
2984struct IrInstGenStorePtr {
2985 IrInstGen base;
2984struct Stage1AirInstStorePtr {
2985 Stage1AirInst base;
29862986
2987 IrInstGen *ptr;
2988 IrInstGen *value;
2987 Stage1AirInst *ptr;
2988 Stage1AirInst *value;
29892989};
29902990
2991struct IrInstGenVectorStoreElem {
2992 IrInstGen base;
2991struct Stage1AirInstVectorStoreElem {
2992 Stage1AirInst base;
29932993
2994 IrInstGen *vector_ptr;
2995 IrInstGen *index;
2996 IrInstGen *value;
2994 Stage1AirInst *vector_ptr;
2995 Stage1AirInst *index;
2996 Stage1AirInst *value;
29972997};
29982998
2999struct IrInstSrcFieldPtr {
3000 IrInstSrc base;
2999struct Stage1ZirInstFieldPtr {
3000 Stage1ZirInst base;
30013001
3002 IrInstSrc *container_ptr;
3002 Stage1ZirInst *container_ptr;
30033003 Buf *field_name_buffer;
3004 IrInstSrc *field_name_expr;
3004 Stage1ZirInst *field_name_expr;
30053005 bool initializing;
30063006};
30073007
3008struct IrInstGenStructFieldPtr {
3009 IrInstGen base;
3008struct Stage1AirInstStructFieldPtr {
3009 Stage1AirInst base;
30103010
3011 IrInstGen *struct_ptr;
3011 Stage1AirInst *struct_ptr;
30123012 TypeStructField *field;
30133013 bool is_const;
30143014};
30153015
3016struct IrInstGenUnionFieldPtr {
3017 IrInstGen base;
3016struct Stage1AirInstUnionFieldPtr {
3017 Stage1AirInst base;
30183018
3019 IrInstGen *union_ptr;
3019 Stage1AirInst *union_ptr;
30203020 TypeUnionField *field;
30213021 bool safety_check_on;
30223022 bool initializing;
30233023};
30243024
3025struct IrInstSrcElemPtr {
3026 IrInstSrc base;
3025struct Stage1ZirInstElemPtr {
3026 Stage1ZirInst base;
30273027
3028 IrInstSrc *array_ptr;
3029 IrInstSrc *elem_index;
3028 Stage1ZirInst *array_ptr;
3029 Stage1ZirInst *elem_index;
30303030 AstNode *init_array_type_source_node;
30313031 PtrLen ptr_len;
30323032 bool safety_check_on;
30333033};
30343034
3035struct IrInstGenElemPtr {
3036 IrInstGen base;
3035struct Stage1AirInstElemPtr {
3036 Stage1AirInst base;
30373037
3038 IrInstGen *array_ptr;
3039 IrInstGen *elem_index;
3038 Stage1AirInst *array_ptr;
3039 Stage1AirInst *elem_index;
30403040 bool safety_check_on;
30413041};
30423042
3043struct IrInstSrcVarPtr {
3044 IrInstSrc base;
3043struct Stage1ZirInstVarPtr {
3044 Stage1ZirInst base;
30453045
30463046 ZigVar *var;
30473047 ScopeFnDef *crossed_fndef_scope;
30483048};
30493049
3050struct IrInstGenVarPtr {
3051 IrInstGen base;
3050struct Stage1AirInstVarPtr {
3051 Stage1AirInst base;
30523052
30533053 ZigVar *var;
30543054};
......@@ -3056,21 +3056,21 @@ struct IrInstGenVarPtr {
30563056// For functions that have a return type for which handle_is_ptr is true, a
30573057// result location pointer is the secret first parameter ("sret"). This
30583058// instruction returns that pointer.
3059struct IrInstGenReturnPtr {
3060 IrInstGen base;
3059struct Stage1AirInstReturnPtr {
3060 Stage1AirInst base;
30613061};
30623062
3063struct IrInstSrcCall {
3064 IrInstSrc base;
3063struct Stage1ZirInstCall {
3064 Stage1ZirInst base;
30653065
3066 IrInstSrc *fn_ref;
3066 Stage1ZirInst *fn_ref;
30673067 ZigFn *fn_entry;
30683068 size_t arg_count;
3069 IrInstSrc **args;
3070 IrInstSrc *ret_ptr;
3069 Stage1ZirInst **args;
3070 Stage1ZirInst *ret_ptr;
30713071 ResultLoc *result_loc;
30723072
3073 IrInstSrc *new_stack;
3073 Stage1ZirInst *new_stack;
30743074
30753075 CallModifier modifier;
30763076 bool is_async_call_builtin;
......@@ -3078,12 +3078,12 @@ struct IrInstSrcCall {
30783078
30793079// This is a pass1 instruction, used by @call when the args node is
30803080// a tuple or struct literal.
3081struct IrInstSrcCallArgs {
3082 IrInstSrc base;
3081struct Stage1ZirInstCallArgs {
3082 Stage1ZirInst base;
30833083
3084 IrInstSrc *options;
3085 IrInstSrc *fn_ref;
3086 IrInstSrc **args_ptr;
3084 Stage1ZirInst *options;
3085 Stage1ZirInst *fn_ref;
3086 Stage1ZirInst **args_ptr;
30873087 size_t args_len;
30883088 ResultLoc *result_loc;
30893089};
......@@ -3091,68 +3091,68 @@ struct IrInstSrcCallArgs {
30913091// This is a pass1 instruction, used by @call, when the args node
30923092// is not a literal.
30933093// `args` is expected to be either a struct or a tuple.
3094struct IrInstSrcCallExtra {
3095 IrInstSrc base;
3094struct Stage1ZirInstCallExtra {
3095 Stage1ZirInst base;
30963096
3097 IrInstSrc *options;
3098 IrInstSrc *fn_ref;
3099 IrInstSrc *args;
3097 Stage1ZirInst *options;
3098 Stage1ZirInst *fn_ref;
3099 Stage1ZirInst *args;
31003100 ResultLoc *result_loc;
31013101};
31023102
31033103// This is a pass1 instruction, used by @asyncCall, when the args node
31043104// is not a literal.
31053105// `args` is expected to be either a struct or a tuple.
3106struct IrInstSrcAsyncCallExtra {
3107 IrInstSrc base;
3106struct Stage1ZirInstAsyncCallExtra {
3107 Stage1ZirInst base;
31083108
31093109 CallModifier modifier;
3110 IrInstSrc *fn_ref;
3111 IrInstSrc *ret_ptr;
3112 IrInstSrc *new_stack;
3113 IrInstSrc *args;
3110 Stage1ZirInst *fn_ref;
3111 Stage1ZirInst *ret_ptr;
3112 Stage1ZirInst *new_stack;
3113 Stage1ZirInst *args;
31143114 ResultLoc *result_loc;
31153115};
31163116
3117struct IrInstGenCall {
3118 IrInstGen base;
3117struct Stage1AirInstCall {
3118 Stage1AirInst base;
31193119
3120 IrInstGen *fn_ref;
3120 Stage1AirInst *fn_ref;
31213121 ZigFn *fn_entry;
31223122 size_t arg_count;
3123 IrInstGen **args;
3124 IrInstGen *result_loc;
3125 IrInstGen *frame_result_loc;
3126 IrInstGen *new_stack;
3123 Stage1AirInst **args;
3124 Stage1AirInst *result_loc;
3125 Stage1AirInst *frame_result_loc;
3126 Stage1AirInst *new_stack;
31273127
31283128 CallModifier modifier;
31293129
31303130 bool is_async_call_builtin;
31313131};
31323132
3133struct IrInstSrcConst {
3134 IrInstSrc base;
3133struct Stage1ZirInstConst {
3134 Stage1ZirInst base;
31353135
31363136 ZigValue *value;
31373137};
31383138
3139struct IrInstGenConst {
3140 IrInstGen base;
3139struct Stage1AirInstConst {
3140 Stage1AirInst base;
31413141};
31423142
3143struct IrInstSrcReturn {
3144 IrInstSrc base;
3143struct Stage1ZirInstReturn {
3144 Stage1ZirInst base;
31453145
3146 IrInstSrc *operand;
3146 Stage1ZirInst *operand;
31473147};
31483148
31493149// When an IrExecutable is not in a function, a return instruction means that
31503150// the expression returns with that value, even though a return statement from
31513151// an AST perspective is invalid.
3152struct IrInstGenReturn {
3153 IrInstGen base;
3152struct Stage1AirInstReturn {
3153 Stage1AirInst base;
31543154
3155 IrInstGen *operand;
3155 Stage1AirInst *operand;
31563156};
31573157
31583158enum CastOp {
......@@ -3167,94 +3167,94 @@ enum CastOp {
31673167};
31683168
31693169// TODO get rid of this instruction, replace with instructions for each op code
3170struct IrInstGenCast {
3171 IrInstGen base;
3170struct Stage1AirInstCast {
3171 Stage1AirInst base;
31723172
3173 IrInstGen *value;
3173 Stage1AirInst *value;
31743174 CastOp cast_op;
31753175};
31763176
3177struct IrInstSrcContainerInitList {
3178 IrInstSrc base;
3177struct Stage1ZirInstContainerInitList {
3178 Stage1ZirInst base;
31793179
3180 IrInstSrc *elem_type;
3180 Stage1ZirInst *elem_type;
31813181 size_t item_count;
3182 IrInstSrc **elem_result_loc_list;
3183 IrInstSrc *result_loc;
3182 Stage1ZirInst **elem_result_loc_list;
3183 Stage1ZirInst *result_loc;
31843184 AstNode *init_array_type_source_node;
31853185};
31863186
3187struct IrInstSrcContainerInitFieldsField {
3187struct Stage1ZirInstContainerInitFieldsField {
31883188 Buf *name;
31893189 AstNode *source_node;
3190 IrInstSrc *result_loc;
3190 Stage1ZirInst *result_loc;
31913191};
31923192
3193struct IrInstSrcContainerInitFields {
3194 IrInstSrc base;
3193struct Stage1ZirInstContainerInitFields {
3194 Stage1ZirInst base;
31953195
31963196 size_t field_count;
3197 IrInstSrcContainerInitFieldsField *fields;
3198 IrInstSrc *result_loc;
3197 Stage1ZirInstContainerInitFieldsField *fields;
3198 Stage1ZirInst *result_loc;
31993199};
32003200
3201struct IrInstSrcUnreachable {
3202 IrInstSrc base;
3201struct Stage1ZirInstUnreachable {
3202 Stage1ZirInst base;
32033203};
32043204
3205struct IrInstGenUnreachable {
3206 IrInstGen base;
3205struct Stage1AirInstUnreachable {
3206 Stage1AirInst base;
32073207};
32083208
3209struct IrInstSrcTypeOf {
3210 IrInstSrc base;
3209struct Stage1ZirInstTypeOf {
3210 Stage1ZirInst base;
32113211
32123212 union {
3213 IrInstSrc *scalar; // value_count == 1
3214 IrInstSrc **list; // value_count > 1
3213 Stage1ZirInst *scalar; // value_count == 1
3214 Stage1ZirInst **list; // value_count > 1
32153215 } value;
32163216 size_t value_count;
32173217};
32183218
3219struct IrInstSrcSetCold {
3220 IrInstSrc base;
3219struct Stage1ZirInstSetCold {
3220 Stage1ZirInst base;
32213221
3222 IrInstSrc *is_cold;
3222 Stage1ZirInst *is_cold;
32233223};
32243224
3225struct IrInstSrcSetRuntimeSafety {
3226 IrInstSrc base;
3225struct Stage1ZirInstSetRuntimeSafety {
3226 Stage1ZirInst base;
32273227
3228 IrInstSrc *safety_on;
3228 Stage1ZirInst *safety_on;
32293229};
32303230
3231struct IrInstSrcSetFloatMode {
3232 IrInstSrc base;
3231struct Stage1ZirInstSetFloatMode {
3232 Stage1ZirInst base;
32333233
3234 IrInstSrc *scope_value;
3235 IrInstSrc *mode_value;
3234 Stage1ZirInst *scope_value;
3235 Stage1ZirInst *mode_value;
32363236};
32373237
3238struct IrInstSrcArrayType {
3239 IrInstSrc base;
3238struct Stage1ZirInstArrayType {
3239 Stage1ZirInst base;
32403240
3241 IrInstSrc *size;
3242 IrInstSrc *sentinel;
3243 IrInstSrc *child_type;
3241 Stage1ZirInst *size;
3242 Stage1ZirInst *sentinel;
3243 Stage1ZirInst *child_type;
32443244};
32453245
3246struct IrInstSrcPtrTypeSimple {
3247 IrInstSrc base;
3246struct Stage1ZirInstPtrTypeSimple {
3247 Stage1ZirInst base;
32483248
3249 IrInstSrc *child_type;
3249 Stage1ZirInst *child_type;
32503250};
32513251
3252struct IrInstSrcPtrType {
3253 IrInstSrc base;
3252struct Stage1ZirInstPtrType {
3253 Stage1ZirInst base;
32543254
3255 IrInstSrc *sentinel;
3256 IrInstSrc *align_value;
3257 IrInstSrc *child_type;
3255 Stage1ZirInst *sentinel;
3256 Stage1ZirInst *align_value;
3257 Stage1ZirInst *child_type;
32583258 uint32_t bit_offset_start;
32593259 uint32_t host_int_bytes;
32603260 PtrLen ptr_len;
......@@ -3263,459 +3263,459 @@ struct IrInstSrcPtrType {
32633263 bool is_allow_zero;
32643264};
32653265
3266struct IrInstSrcAnyFrameType {
3267 IrInstSrc base;
3266struct Stage1ZirInstAnyFrameType {
3267 Stage1ZirInst base;
32683268
3269 IrInstSrc *payload_type;
3269 Stage1ZirInst *payload_type;
32703270};
32713271
3272struct IrInstSrcSliceType {
3273 IrInstSrc base;
3272struct Stage1ZirInstSliceType {
3273 Stage1ZirInst base;
32743274
3275 IrInstSrc *sentinel;
3276 IrInstSrc *align_value;
3277 IrInstSrc *child_type;
3275 Stage1ZirInst *sentinel;
3276 Stage1ZirInst *align_value;
3277 Stage1ZirInst *child_type;
32783278 bool is_const;
32793279 bool is_volatile;
32803280 bool is_allow_zero;
32813281};
32823282
3283struct IrInstSrcAsm {
3284 IrInstSrc base;
3283struct Stage1ZirInstAsm {
3284 Stage1ZirInst base;
32853285
3286 IrInstSrc *asm_template;
3287 IrInstSrc **input_list;
3288 IrInstSrc **output_types;
3286 Stage1ZirInst *asm_template;
3287 Stage1ZirInst **input_list;
3288 Stage1ZirInst **output_types;
32893289 ZigVar **output_vars;
32903290 size_t return_count;
32913291 bool has_side_effects;
32923292 bool is_global;
32933293};
32943294
3295struct IrInstGenAsm {
3296 IrInstGen base;
3295struct Stage1AirInstAsm {
3296 Stage1AirInst base;
32973297
32983298 Buf *asm_template;
32993299 AsmToken *token_list;
33003300 size_t token_list_len;
3301 IrInstGen **input_list;
3302 IrInstGen **output_types;
3301 Stage1AirInst **input_list;
3302 Stage1AirInst **output_types;
33033303 ZigVar **output_vars;
33043304 size_t return_count;
33053305 bool has_side_effects;
33063306};
33073307
3308struct IrInstSrcSizeOf {
3309 IrInstSrc base;
3308struct Stage1ZirInstSizeOf {
3309 Stage1ZirInst base;
33103310
3311 IrInstSrc *type_value;
3311 Stage1ZirInst *type_value;
33123312 bool bit_size;
33133313};
33143314
33153315// returns true if nonnull, returns false if null
3316struct IrInstSrcTestNonNull {
3317 IrInstSrc base;
3316struct Stage1ZirInstTestNonNull {
3317 Stage1ZirInst base;
33183318
3319 IrInstSrc *value;
3319 Stage1ZirInst *value;
33203320};
33213321
3322struct IrInstGenTestNonNull {
3323 IrInstGen base;
3322struct Stage1AirInstTestNonNull {
3323 Stage1AirInst base;
33243324
3325 IrInstGen *value;
3325 Stage1AirInst *value;
33263326};
33273327
33283328// Takes a pointer to an optional value, returns a pointer
33293329// to the payload.
3330struct IrInstSrcOptionalUnwrapPtr {
3331 IrInstSrc base;
3330struct Stage1ZirInstOptionalUnwrapPtr {
3331 Stage1ZirInst base;
33323332
3333 IrInstSrc *base_ptr;
3333 Stage1ZirInst *base_ptr;
33343334 bool safety_check_on;
33353335};
33363336
3337struct IrInstGenOptionalUnwrapPtr {
3338 IrInstGen base;
3337struct Stage1AirInstOptionalUnwrapPtr {
3338 Stage1AirInst base;
33393339
3340 IrInstGen *base_ptr;
3340 Stage1AirInst *base_ptr;
33413341 bool safety_check_on;
33423342 bool initializing;
33433343};
33443344
3345struct IrInstSrcCtz {
3346 IrInstSrc base;
3345struct Stage1ZirInstCtz {
3346 Stage1ZirInst base;
33473347
3348 IrInstSrc *type;
3349 IrInstSrc *op;
3348 Stage1ZirInst *type;
3349 Stage1ZirInst *op;
33503350};
33513351
3352struct IrInstGenCtz {
3353 IrInstGen base;
3352struct Stage1AirInstCtz {
3353 Stage1AirInst base;
33543354
3355 IrInstGen *op;
3355 Stage1AirInst *op;
33563356};
33573357
3358struct IrInstSrcClz {
3359 IrInstSrc base;
3358struct Stage1ZirInstClz {
3359 Stage1ZirInst base;
33603360
3361 IrInstSrc *type;
3362 IrInstSrc *op;
3361 Stage1ZirInst *type;
3362 Stage1ZirInst *op;
33633363};
33643364
3365struct IrInstGenClz {
3366 IrInstGen base;
3365struct Stage1AirInstClz {
3366 Stage1AirInst base;
33673367
3368 IrInstGen *op;
3368 Stage1AirInst *op;
33693369};
33703370
3371struct IrInstSrcPopCount {
3372 IrInstSrc base;
3371struct Stage1ZirInstPopCount {
3372 Stage1ZirInst base;
33733373
3374 IrInstSrc *type;
3375 IrInstSrc *op;
3374 Stage1ZirInst *type;
3375 Stage1ZirInst *op;
33763376};
33773377
3378struct IrInstGenPopCount {
3379 IrInstGen base;
3378struct Stage1AirInstPopCount {
3379 Stage1AirInst base;
33803380
3381 IrInstGen *op;
3381 Stage1AirInst *op;
33823382};
33833383
3384struct IrInstGenUnionTag {
3385 IrInstGen base;
3384struct Stage1AirInstUnionTag {
3385 Stage1AirInst base;
33863386
3387 IrInstGen *value;
3387 Stage1AirInst *value;
33883388};
33893389
3390struct IrInstSrcImport {
3391 IrInstSrc base;
3390struct Stage1ZirInstImport {
3391 Stage1ZirInst base;
33923392
3393 IrInstSrc *name;
3393 Stage1ZirInst *name;
33943394};
33953395
3396struct IrInstSrcRef {
3397 IrInstSrc base;
3396struct Stage1ZirInstRef {
3397 Stage1ZirInst base;
33983398
3399 IrInstSrc *value;
3399 Stage1ZirInst *value;
34003400};
34013401
3402struct IrInstGenRef {
3403 IrInstGen base;
3402struct Stage1AirInstRef {
3403 Stage1AirInst base;
34043404
3405 IrInstGen *operand;
3406 IrInstGen *result_loc;
3405 Stage1AirInst *operand;
3406 Stage1AirInst *result_loc;
34073407};
34083408
3409struct IrInstSrcCompileErr {
3410 IrInstSrc base;
3409struct Stage1ZirInstCompileErr {
3410 Stage1ZirInst base;
34113411
3412 IrInstSrc *msg;
3412 Stage1ZirInst *msg;
34133413};
34143414
3415struct IrInstSrcCompileLog {
3416 IrInstSrc base;
3415struct Stage1ZirInstCompileLog {
3416 Stage1ZirInst base;
34173417
34183418 size_t msg_count;
3419 IrInstSrc **msg_list;
3419 Stage1ZirInst **msg_list;
34203420};
34213421
3422struct IrInstSrcErrName {
3423 IrInstSrc base;
3422struct Stage1ZirInstErrName {
3423 Stage1ZirInst base;
34243424
3425 IrInstSrc *value;
3425 Stage1ZirInst *value;
34263426};
34273427
3428struct IrInstGenErrName {
3429 IrInstGen base;
3428struct Stage1AirInstErrName {
3429 Stage1AirInst base;
34303430
3431 IrInstGen *value;
3431 Stage1AirInst *value;
34323432};
34333433
3434struct IrInstSrcCImport {
3435 IrInstSrc base;
3434struct Stage1ZirInstCImport {
3435 Stage1ZirInst base;
34363436};
34373437
3438struct IrInstSrcCInclude {
3439 IrInstSrc base;
3438struct Stage1ZirInstCInclude {
3439 Stage1ZirInst base;
34403440
3441 IrInstSrc *name;
3441 Stage1ZirInst *name;
34423442};
34433443
3444struct IrInstSrcCDefine {
3445 IrInstSrc base;
3444struct Stage1ZirInstCDefine {
3445 Stage1ZirInst base;
34463446
3447 IrInstSrc *name;
3448 IrInstSrc *value;
3447 Stage1ZirInst *name;
3448 Stage1ZirInst *value;
34493449};
34503450
3451struct IrInstSrcCUndef {
3452 IrInstSrc base;
3451struct Stage1ZirInstCUndef {
3452 Stage1ZirInst base;
34533453
3454 IrInstSrc *name;
3454 Stage1ZirInst *name;
34553455};
34563456
3457struct IrInstSrcEmbedFile {
3458 IrInstSrc base;
3457struct Stage1ZirInstEmbedFile {
3458 Stage1ZirInst base;
34593459
3460 IrInstSrc *name;
3460 Stage1ZirInst *name;
34613461};
34623462
3463struct IrInstSrcCmpxchg {
3464 IrInstSrc base;
3463struct Stage1ZirInstCmpxchg {
3464 Stage1ZirInst base;
34653465
34663466 bool is_weak;
3467 IrInstSrc *type_value;
3468 IrInstSrc *ptr;
3469 IrInstSrc *cmp_value;
3470 IrInstSrc *new_value;
3471 IrInstSrc *success_order_value;
3472 IrInstSrc *failure_order_value;
3467 Stage1ZirInst *type_value;
3468 Stage1ZirInst *ptr;
3469 Stage1ZirInst *cmp_value;
3470 Stage1ZirInst *new_value;
3471 Stage1ZirInst *success_order_value;
3472 Stage1ZirInst *failure_order_value;
34733473 ResultLoc *result_loc;
34743474};
34753475
3476struct IrInstGenCmpxchg {
3477 IrInstGen base;
3476struct Stage1AirInstCmpxchg {
3477 Stage1AirInst base;
34783478
34793479 AtomicOrder success_order;
34803480 AtomicOrder failure_order;
3481 IrInstGen *ptr;
3482 IrInstGen *cmp_value;
3483 IrInstGen *new_value;
3484 IrInstGen *result_loc;
3481 Stage1AirInst *ptr;
3482 Stage1AirInst *cmp_value;
3483 Stage1AirInst *new_value;
3484 Stage1AirInst *result_loc;
34853485 bool is_weak;
34863486};
34873487
3488struct IrInstSrcFence {
3489 IrInstSrc base;
3488struct Stage1ZirInstFence {
3489 Stage1ZirInst base;
34903490
3491 IrInstSrc *order;
3491 Stage1ZirInst *order;
34923492};
34933493
3494struct IrInstGenFence {
3495 IrInstGen base;
3494struct Stage1AirInstFence {
3495 Stage1AirInst base;
34963496
34973497 AtomicOrder order;
34983498};
34993499
3500struct IrInstSrcReduce {
3501 IrInstSrc base;
3500struct Stage1ZirInstReduce {
3501 Stage1ZirInst base;
35023502
3503 IrInstSrc *op;
3504 IrInstSrc *value;
3503 Stage1ZirInst *op;
3504 Stage1ZirInst *value;
35053505};
35063506
3507struct IrInstGenReduce {
3508 IrInstGen base;
3507struct Stage1AirInstReduce {
3508 Stage1AirInst base;
35093509
35103510 ReduceOp op;
3511 IrInstGen *value;
3511 Stage1AirInst *value;
35123512};
35133513
3514struct IrInstSrcTruncate {
3515 IrInstSrc base;
3514struct Stage1ZirInstTruncate {
3515 Stage1ZirInst base;
35163516
3517 IrInstSrc *dest_type;
3518 IrInstSrc *target;
3517 Stage1ZirInst *dest_type;
3518 Stage1ZirInst *target;
35193519};
35203520
3521struct IrInstGenTruncate {
3522 IrInstGen base;
3521struct Stage1AirInstTruncate {
3522 Stage1AirInst base;
35233523
3524 IrInstGen *target;
3524 Stage1AirInst *target;
35253525};
35263526
3527struct IrInstSrcIntCast {
3528 IrInstSrc base;
3527struct Stage1ZirInstIntCast {
3528 Stage1ZirInst base;
35293529
3530 IrInstSrc *dest_type;
3531 IrInstSrc *target;
3530 Stage1ZirInst *dest_type;
3531 Stage1ZirInst *target;
35323532};
35333533
3534struct IrInstSrcFloatCast {
3535 IrInstSrc base;
3534struct Stage1ZirInstFloatCast {
3535 Stage1ZirInst base;
35363536
3537 IrInstSrc *dest_type;
3538 IrInstSrc *target;
3537 Stage1ZirInst *dest_type;
3538 Stage1ZirInst *target;
35393539};
35403540
3541struct IrInstSrcErrSetCast {
3542 IrInstSrc base;
3541struct Stage1ZirInstErrSetCast {
3542 Stage1ZirInst base;
35433543
3544 IrInstSrc *dest_type;
3545 IrInstSrc *target;
3544 Stage1ZirInst *dest_type;
3545 Stage1ZirInst *target;
35463546};
35473547
3548struct IrInstSrcIntToFloat {
3549 IrInstSrc base;
3548struct Stage1ZirInstIntToFloat {
3549 Stage1ZirInst base;
35503550
3551 IrInstSrc *dest_type;
3552 IrInstSrc *target;
3551 Stage1ZirInst *dest_type;
3552 Stage1ZirInst *target;
35533553};
35543554
3555struct IrInstSrcFloatToInt {
3556 IrInstSrc base;
3555struct Stage1ZirInstFloatToInt {
3556 Stage1ZirInst base;
35573557
3558 IrInstSrc *dest_type;
3559 IrInstSrc *target;
3558 Stage1ZirInst *dest_type;
3559 Stage1ZirInst *target;
35603560};
35613561
3562struct IrInstSrcBoolToInt {
3563 IrInstSrc base;
3562struct Stage1ZirInstBoolToInt {
3563 Stage1ZirInst base;
35643564
3565 IrInstSrc *target;
3565 Stage1ZirInst *target;
35663566};
35673567
3568struct IrInstSrcVectorType {
3569 IrInstSrc base;
3568struct Stage1ZirInstVectorType {
3569 Stage1ZirInst base;
35703570
3571 IrInstSrc *len;
3572 IrInstSrc *elem_type;
3571 Stage1ZirInst *len;
3572 Stage1ZirInst *elem_type;
35733573};
35743574
3575struct IrInstSrcBoolNot {
3576 IrInstSrc base;
3575struct Stage1ZirInstBoolNot {
3576 Stage1ZirInst base;
35773577
3578 IrInstSrc *value;
3578 Stage1ZirInst *value;
35793579};
35803580
3581struct IrInstGenBoolNot {
3582 IrInstGen base;
3581struct Stage1AirInstBoolNot {
3582 Stage1AirInst base;
35833583
3584 IrInstGen *value;
3584 Stage1AirInst *value;
35853585};
35863586
3587struct IrInstSrcMemset {
3588 IrInstSrc base;
3587struct Stage1ZirInstMemset {
3588 Stage1ZirInst base;
35893589
3590 IrInstSrc *dest_ptr;
3591 IrInstSrc *byte;
3592 IrInstSrc *count;
3590 Stage1ZirInst *dest_ptr;
3591 Stage1ZirInst *byte;
3592 Stage1ZirInst *count;
35933593};
35943594
3595struct IrInstGenMemset {
3596 IrInstGen base;
3595struct Stage1AirInstMemset {
3596 Stage1AirInst base;
35973597
3598 IrInstGen *dest_ptr;
3599 IrInstGen *byte;
3600 IrInstGen *count;
3598 Stage1AirInst *dest_ptr;
3599 Stage1AirInst *byte;
3600 Stage1AirInst *count;
36013601};
36023602
3603struct IrInstSrcMemcpy {
3604 IrInstSrc base;
3603struct Stage1ZirInstMemcpy {
3604 Stage1ZirInst base;
36053605
3606 IrInstSrc *dest_ptr;
3607 IrInstSrc *src_ptr;
3608 IrInstSrc *count;
3606 Stage1ZirInst *dest_ptr;
3607 Stage1ZirInst *src_ptr;
3608 Stage1ZirInst *count;
36093609};
36103610
3611struct IrInstGenMemcpy {
3612 IrInstGen base;
3611struct Stage1AirInstMemcpy {
3612 Stage1AirInst base;
36133613
3614 IrInstGen *dest_ptr;
3615 IrInstGen *src_ptr;
3616 IrInstGen *count;
3614 Stage1AirInst *dest_ptr;
3615 Stage1AirInst *src_ptr;
3616 Stage1AirInst *count;
36173617};
36183618
3619struct IrInstSrcWasmMemorySize {
3620 IrInstSrc base;
3619struct Stage1ZirInstWasmMemorySize {
3620 Stage1ZirInst base;
36213621
3622 IrInstSrc *index;
3622 Stage1ZirInst *index;
36233623};
36243624
3625struct IrInstGenWasmMemorySize {
3626 IrInstGen base;
3625struct Stage1AirInstWasmMemorySize {
3626 Stage1AirInst base;
36273627
3628 IrInstGen *index;
3628 Stage1AirInst *index;
36293629};
36303630
3631struct IrInstSrcWasmMemoryGrow {
3632 IrInstSrc base;
3631struct Stage1ZirInstWasmMemoryGrow {
3632 Stage1ZirInst base;
36333633
3634 IrInstSrc *index;
3635 IrInstSrc *delta;
3634 Stage1ZirInst *index;
3635 Stage1ZirInst *delta;
36363636};
36373637
3638struct IrInstGenWasmMemoryGrow {
3639 IrInstGen base;
3638struct Stage1AirInstWasmMemoryGrow {
3639 Stage1AirInst base;
36403640
3641 IrInstGen *index;
3642 IrInstGen *delta;
3641 Stage1AirInst *index;
3642 Stage1AirInst *delta;
36433643};
36443644
3645struct IrInstSrcSrc {
3646 IrInstSrc base;
3645struct Stage1ZirInstSrc {
3646 Stage1ZirInst base;
36473647};
36483648
3649struct IrInstSrcSlice {
3650 IrInstSrc base;
3649struct Stage1ZirInstSlice {
3650 Stage1ZirInst base;
36513651
3652 IrInstSrc *ptr;
3653 IrInstSrc *start;
3654 IrInstSrc *end;
3655 IrInstSrc *sentinel;
3652 Stage1ZirInst *ptr;
3653 Stage1ZirInst *start;
3654 Stage1ZirInst *end;
3655 Stage1ZirInst *sentinel;
36563656 ResultLoc *result_loc;
36573657 bool safety_check_on;
36583658};
36593659
3660struct IrInstGenSlice {
3661 IrInstGen base;
3660struct Stage1AirInstSlice {
3661 Stage1AirInst base;
36623662
3663 IrInstGen *ptr;
3664 IrInstGen *start;
3665 IrInstGen *end;
3666 IrInstGen *result_loc;
3663 Stage1AirInst *ptr;
3664 Stage1AirInst *start;
3665 Stage1AirInst *end;
3666 Stage1AirInst *result_loc;
36673667 ZigValue *sentinel;
36683668 bool safety_check_on;
36693669};
36703670
3671struct IrInstSrcBreakpoint {
3672 IrInstSrc base;
3671struct Stage1ZirInstBreakpoint {
3672 Stage1ZirInst base;
36733673};
36743674
3675struct IrInstGenBreakpoint {
3676 IrInstGen base;
3675struct Stage1AirInstBreakpoint {
3676 Stage1AirInst base;
36773677};
36783678
3679struct IrInstSrcReturnAddress {
3680 IrInstSrc base;
3679struct Stage1ZirInstReturnAddress {
3680 Stage1ZirInst base;
36813681};
36823682
3683struct IrInstGenReturnAddress {
3684 IrInstGen base;
3683struct Stage1AirInstReturnAddress {
3684 Stage1AirInst base;
36853685};
36863686
3687struct IrInstSrcFrameAddress {
3688 IrInstSrc base;
3687struct Stage1ZirInstFrameAddress {
3688 Stage1ZirInst base;
36893689};
36903690
3691struct IrInstGenFrameAddress {
3692 IrInstGen base;
3691struct Stage1AirInstFrameAddress {
3692 Stage1AirInst base;
36933693};
36943694
3695struct IrInstSrcFrameHandle {
3696 IrInstSrc base;
3695struct Stage1ZirInstFrameHandle {
3696 Stage1ZirInst base;
36973697};
36983698
3699struct IrInstGenFrameHandle {
3700 IrInstGen base;
3699struct Stage1AirInstFrameHandle {
3700 Stage1AirInst base;
37013701};
37023702
3703struct IrInstSrcFrameType {
3704 IrInstSrc base;
3703struct Stage1ZirInstFrameType {
3704 Stage1ZirInst base;
37053705
3706 IrInstSrc *fn;
3706 Stage1ZirInst *fn;
37073707};
37083708
3709struct IrInstSrcFrameSize {
3710 IrInstSrc base;
3709struct Stage1ZirInstFrameSize {
3710 Stage1ZirInst base;
37113711
3712 IrInstSrc *fn;
3712 Stage1ZirInst *fn;
37133713};
37143714
3715struct IrInstGenFrameSize {
3716 IrInstGen base;
3715struct Stage1AirInstFrameSize {
3716 Stage1AirInst base;
37173717
3718 IrInstGen *fn;
3718 Stage1AirInst *fn;
37193719};
37203720
37213721enum IrOverflowOp {
......@@ -3725,397 +3725,397 @@ enum IrOverflowOp {
37253725 IrOverflowOpShl,
37263726};
37273727
3728struct IrInstSrcOverflowOp {
3729 IrInstSrc base;
3728struct Stage1ZirInstOverflowOp {
3729 Stage1ZirInst base;
37303730
37313731 IrOverflowOp op;
3732 IrInstSrc *type_value;
3733 IrInstSrc *op1;
3734 IrInstSrc *op2;
3735 IrInstSrc *result_ptr;
3732 Stage1ZirInst *type_value;
3733 Stage1ZirInst *op1;
3734 Stage1ZirInst *op2;
3735 Stage1ZirInst *result_ptr;
37363736};
37373737
3738struct IrInstGenOverflowOp {
3739 IrInstGen base;
3738struct Stage1AirInstOverflowOp {
3739 Stage1AirInst base;
37403740
37413741 IrOverflowOp op;
3742 IrInstGen *op1;
3743 IrInstGen *op2;
3744 IrInstGen *result_ptr;
3742 Stage1AirInst *op1;
3743 Stage1AirInst *op2;
3744 Stage1AirInst *result_ptr;
37453745
37463746 // TODO can this field be removed?
37473747 ZigType *result_ptr_type;
37483748};
37493749
3750struct IrInstSrcMulAdd {
3751 IrInstSrc base;
3750struct Stage1ZirInstMulAdd {
3751 Stage1ZirInst base;
37523752
3753 IrInstSrc *type_value;
3754 IrInstSrc *op1;
3755 IrInstSrc *op2;
3756 IrInstSrc *op3;
3753 Stage1ZirInst *type_value;
3754 Stage1ZirInst *op1;
3755 Stage1ZirInst *op2;
3756 Stage1ZirInst *op3;
37573757};
37583758
3759struct IrInstGenMulAdd {
3760 IrInstGen base;
3759struct Stage1AirInstMulAdd {
3760 Stage1AirInst base;
37613761
3762 IrInstGen *op1;
3763 IrInstGen *op2;
3764 IrInstGen *op3;
3762 Stage1AirInst *op1;
3763 Stage1AirInst *op2;
3764 Stage1AirInst *op3;
37653765};
37663766
3767struct IrInstSrcAlignOf {
3768 IrInstSrc base;
3767struct Stage1ZirInstAlignOf {
3768 Stage1ZirInst base;
37693769
3770 IrInstSrc *type_value;
3770 Stage1ZirInst *type_value;
37713771};
37723772
37733773// returns true if error, returns false if not error
3774struct IrInstSrcTestErr {
3775 IrInstSrc base;
3774struct Stage1ZirInstTestErr {
3775 Stage1ZirInst base;
37763776
3777 IrInstSrc *base_ptr;
3777 Stage1ZirInst *base_ptr;
37783778 bool resolve_err_set;
37793779 bool base_ptr_is_payload;
37803780};
37813781
3782struct IrInstGenTestErr {
3783 IrInstGen base;
3782struct Stage1AirInstTestErr {
3783 Stage1AirInst base;
37843784
3785 IrInstGen *err_union;
3785 Stage1AirInst *err_union;
37863786};
37873787
37883788// Takes an error union pointer, returns a pointer to the error code.
3789struct IrInstSrcUnwrapErrCode {
3790 IrInstSrc base;
3789struct Stage1ZirInstUnwrapErrCode {
3790 Stage1ZirInst base;
37913791
3792 IrInstSrc *err_union_ptr;
3792 Stage1ZirInst *err_union_ptr;
37933793 bool initializing;
37943794};
37953795
3796struct IrInstGenUnwrapErrCode {
3797 IrInstGen base;
3796struct Stage1AirInstUnwrapErrCode {
3797 Stage1AirInst base;
37983798
3799 IrInstGen *err_union_ptr;
3799 Stage1AirInst *err_union_ptr;
38003800 bool initializing;
38013801};
38023802
3803struct IrInstSrcUnwrapErrPayload {
3804 IrInstSrc base;
3803struct Stage1ZirInstUnwrapErrPayload {
3804 Stage1ZirInst base;
38053805
3806 IrInstSrc *value;
3806 Stage1ZirInst *value;
38073807 bool safety_check_on;
38083808 bool initializing;
38093809};
38103810
3811struct IrInstGenUnwrapErrPayload {
3812 IrInstGen base;
3811struct Stage1AirInstUnwrapErrPayload {
3812 Stage1AirInst base;
38133813
3814 IrInstGen *value;
3814 Stage1AirInst *value;
38153815 bool safety_check_on;
38163816 bool initializing;
38173817};
38183818
3819struct IrInstGenOptionalWrap {
3820 IrInstGen base;
3819struct Stage1AirInstOptionalWrap {
3820 Stage1AirInst base;
38213821
3822 IrInstGen *operand;
3823 IrInstGen *result_loc;
3822 Stage1AirInst *operand;
3823 Stage1AirInst *result_loc;
38243824};
38253825
3826struct IrInstGenErrWrapPayload {
3827 IrInstGen base;
3826struct Stage1AirInstErrWrapPayload {
3827 Stage1AirInst base;
38283828
3829 IrInstGen *operand;
3830 IrInstGen *result_loc;
3829 Stage1AirInst *operand;
3830 Stage1AirInst *result_loc;
38313831};
38323832
3833struct IrInstGenErrWrapCode {
3834 IrInstGen base;
3833struct Stage1AirInstErrWrapCode {
3834 Stage1AirInst base;
38353835
3836 IrInstGen *operand;
3837 IrInstGen *result_loc;
3836 Stage1AirInst *operand;
3837 Stage1AirInst *result_loc;
38383838};
38393839
3840struct IrInstSrcFnProto {
3841 IrInstSrc base;
3840struct Stage1ZirInstFnProto {
3841 Stage1ZirInst base;
38423842
3843 IrInstSrc **param_types;
3844 IrInstSrc *align_value;
3845 IrInstSrc *callconv_value;
3846 IrInstSrc *return_type;
3843 Stage1ZirInst **param_types;
3844 Stage1ZirInst *align_value;
3845 Stage1ZirInst *callconv_value;
3846 Stage1ZirInst *return_type;
38473847 bool is_var_args;
38483848};
38493849
38503850// true if the target value is compile time known, false otherwise
3851struct IrInstSrcTestComptime {
3852 IrInstSrc base;
3851struct Stage1ZirInstTestComptime {
3852 Stage1ZirInst base;
38533853
3854 IrInstSrc *value;
3854 Stage1ZirInst *value;
38553855};
38563856
3857struct IrInstSrcPtrCast {
3858 IrInstSrc base;
3857struct Stage1ZirInstPtrCast {
3858 Stage1ZirInst base;
38593859
3860 IrInstSrc *dest_type;
3861 IrInstSrc *ptr;
3860 Stage1ZirInst *dest_type;
3861 Stage1ZirInst *ptr;
38623862 bool safety_check_on;
38633863};
38643864
3865struct IrInstGenPtrCast {
3866 IrInstGen base;
3865struct Stage1AirInstPtrCast {
3866 Stage1AirInst base;
38673867
3868 IrInstGen *ptr;
3868 Stage1AirInst *ptr;
38693869 bool safety_check_on;
38703870};
38713871
3872struct IrInstSrcImplicitCast {
3873 IrInstSrc base;
3872struct Stage1ZirInstImplicitCast {
3873 Stage1ZirInst base;
38743874
3875 IrInstSrc *operand;
3875 Stage1ZirInst *operand;
38763876 ResultLocCast *result_loc_cast;
38773877};
38783878
3879struct IrInstSrcBitCast {
3880 IrInstSrc base;
3879struct Stage1ZirInstBitCast {
3880 Stage1ZirInst base;
38813881
3882 IrInstSrc *operand;
3882 Stage1ZirInst *operand;
38833883 ResultLocBitCast *result_loc_bit_cast;
38843884};
38853885
3886struct IrInstGenBitCast {
3887 IrInstGen base;
3886struct Stage1AirInstBitCast {
3887 Stage1AirInst base;
38883888
3889 IrInstGen *operand;
3889 Stage1AirInst *operand;
38903890};
38913891
3892struct IrInstGenWidenOrShorten {
3893 IrInstGen base;
3892struct Stage1AirInstWidenOrShorten {
3893 Stage1AirInst base;
38943894
3895 IrInstGen *target;
3895 Stage1AirInst *target;
38963896};
38973897
3898struct IrInstSrcPtrToInt {
3899 IrInstSrc base;
3898struct Stage1ZirInstPtrToInt {
3899 Stage1ZirInst base;
39003900
3901 IrInstSrc *target;
3901 Stage1ZirInst *target;
39023902};
39033903
3904struct IrInstGenPtrToInt {
3905 IrInstGen base;
3904struct Stage1AirInstPtrToInt {
3905 Stage1AirInst base;
39063906
3907 IrInstGen *target;
3907 Stage1AirInst *target;
39083908};
39093909
3910struct IrInstSrcIntToPtr {
3911 IrInstSrc base;
3910struct Stage1ZirInstIntToPtr {
3911 Stage1ZirInst base;
39123912
3913 IrInstSrc *dest_type;
3914 IrInstSrc *target;
3913 Stage1ZirInst *dest_type;
3914 Stage1ZirInst *target;
39153915};
39163916
3917struct IrInstGenIntToPtr {
3918 IrInstGen base;
3917struct Stage1AirInstIntToPtr {
3918 Stage1AirInst base;
39193919
3920 IrInstGen *target;
3920 Stage1AirInst *target;
39213921};
39223922
3923struct IrInstSrcIntToEnum {
3924 IrInstSrc base;
3923struct Stage1ZirInstIntToEnum {
3924 Stage1ZirInst base;
39253925
3926 IrInstSrc *dest_type;
3927 IrInstSrc *target;
3926 Stage1ZirInst *dest_type;
3927 Stage1ZirInst *target;
39283928};
39293929
3930struct IrInstGenIntToEnum {
3931 IrInstGen base;
3930struct Stage1AirInstIntToEnum {
3931 Stage1AirInst base;
39323932
3933 IrInstGen *target;
3933 Stage1AirInst *target;
39343934};
39353935
3936struct IrInstSrcEnumToInt {
3937 IrInstSrc base;
3936struct Stage1ZirInstEnumToInt {
3937 Stage1ZirInst base;
39383938
3939 IrInstSrc *target;
3939 Stage1ZirInst *target;
39403940};
39413941
3942struct IrInstSrcIntToErr {
3943 IrInstSrc base;
3942struct Stage1ZirInstIntToErr {
3943 Stage1ZirInst base;
39443944
3945 IrInstSrc *target;
3945 Stage1ZirInst *target;
39463946};
39473947
3948struct IrInstGenIntToErr {
3949 IrInstGen base;
3948struct Stage1AirInstIntToErr {
3949 Stage1AirInst base;
39503950
3951 IrInstGen *target;
3951 Stage1AirInst *target;
39523952};
39533953
3954struct IrInstSrcErrToInt {
3955 IrInstSrc base;
3954struct Stage1ZirInstErrToInt {
3955 Stage1ZirInst base;
39563956
3957 IrInstSrc *target;
3957 Stage1ZirInst *target;
39583958};
39593959
3960struct IrInstGenErrToInt {
3961 IrInstGen base;
3960struct Stage1AirInstErrToInt {
3961 Stage1AirInst base;
39623962
3963 IrInstGen *target;
3963 Stage1AirInst *target;
39643964};
39653965
3966struct IrInstSrcCheckSwitchProngsRange {
3967 IrInstSrc *start;
3968 IrInstSrc *end;
3966struct Stage1ZirInstCheckSwitchProngsRange {
3967 Stage1ZirInst *start;
3968 Stage1ZirInst *end;
39693969};
39703970
3971struct IrInstSrcCheckSwitchProngs {
3972 IrInstSrc base;
3971struct Stage1ZirInstCheckSwitchProngs {
3972 Stage1ZirInst base;
39733973
3974 IrInstSrc *target_value;
3975 IrInstSrcCheckSwitchProngsRange *ranges;
3974 Stage1ZirInst *target_value;
3975 Stage1ZirInstCheckSwitchProngsRange *ranges;
39763976 size_t range_count;
39773977 AstNode* else_prong;
39783978};
39793979
3980struct IrInstSrcCheckStatementIsVoid {
3981 IrInstSrc base;
3980struct Stage1ZirInstCheckStatementIsVoid {
3981 Stage1ZirInst base;
39823982
3983 IrInstSrc *statement_value;
3983 Stage1ZirInst *statement_value;
39843984};
39853985
3986struct IrInstSrcTypeName {
3987 IrInstSrc base;
3986struct Stage1ZirInstTypeName {
3987 Stage1ZirInst base;
39883988
3989 IrInstSrc *type_value;
3989 Stage1ZirInst *type_value;
39903990};
39913991
3992struct IrInstSrcDeclRef {
3993 IrInstSrc base;
3992struct Stage1ZirInstDeclRef {
3993 Stage1ZirInst base;
39943994
39953995 LVal lval;
39963996 Tld *tld;
39973997};
39983998
3999struct IrInstSrcPanic {
4000 IrInstSrc base;
3999struct Stage1ZirInstPanic {
4000 Stage1ZirInst base;
40014001
4002 IrInstSrc *msg;
4002 Stage1ZirInst *msg;
40034003};
40044004
4005struct IrInstGenPanic {
4006 IrInstGen base;
4005struct Stage1AirInstPanic {
4006 Stage1AirInst base;
40074007
4008 IrInstGen *msg;
4008 Stage1AirInst *msg;
40094009};
40104010
4011struct IrInstSrcTagName {
4012 IrInstSrc base;
4011struct Stage1ZirInstTagName {
4012 Stage1ZirInst base;
40134013
4014 IrInstSrc *target;
4014 Stage1ZirInst *target;
40154015};
40164016
4017struct IrInstGenTagName {
4018 IrInstGen base;
4017struct Stage1AirInstTagName {
4018 Stage1AirInst base;
40194019
4020 IrInstGen *target;
4020 Stage1AirInst *target;
40214021};
40224022
4023struct IrInstSrcFieldParentPtr {
4024 IrInstSrc base;
4023struct Stage1ZirInstFieldParentPtr {
4024 Stage1ZirInst base;
40254025
4026 IrInstSrc *type_value;
4027 IrInstSrc *field_name;
4028 IrInstSrc *field_ptr;
4026 Stage1ZirInst *type_value;
4027 Stage1ZirInst *field_name;
4028 Stage1ZirInst *field_ptr;
40294029};
40304030
4031struct IrInstGenFieldParentPtr {
4032 IrInstGen base;
4031struct Stage1AirInstFieldParentPtr {
4032 Stage1AirInst base;
40334033
4034 IrInstGen *field_ptr;
4034 Stage1AirInst *field_ptr;
40354035 TypeStructField *field;
40364036};
40374037
4038struct IrInstSrcOffsetOf {
4039 IrInstSrc base;
4038struct Stage1ZirInstOffsetOf {
4039 Stage1ZirInst base;
40404040
4041 IrInstSrc *type_value;
4042 IrInstSrc *field_name;
4041 Stage1ZirInst *type_value;
4042 Stage1ZirInst *field_name;
40434043};
40444044
4045struct IrInstSrcBitOffsetOf {
4046 IrInstSrc base;
4045struct Stage1ZirInstBitOffsetOf {
4046 Stage1ZirInst base;
40474047
4048 IrInstSrc *type_value;
4049 IrInstSrc *field_name;
4048 Stage1ZirInst *type_value;
4049 Stage1ZirInst *field_name;
40504050};
40514051
4052struct IrInstSrcTypeInfo {
4053 IrInstSrc base;
4052struct Stage1ZirInstTypeInfo {
4053 Stage1ZirInst base;
40544054
4055 IrInstSrc *type_value;
4055 Stage1ZirInst *type_value;
40564056};
40574057
4058struct IrInstSrcType {
4059 IrInstSrc base;
4058struct Stage1ZirInstType {
4059 Stage1ZirInst base;
40604060
4061 IrInstSrc *type_info;
4061 Stage1ZirInst *type_info;
40624062};
40634063
4064struct IrInstSrcHasField {
4065 IrInstSrc base;
4064struct Stage1ZirInstHasField {
4065 Stage1ZirInst base;
40664066
4067 IrInstSrc *container_type;
4068 IrInstSrc *field_name;
4067 Stage1ZirInst *container_type;
4068 Stage1ZirInst *field_name;
40694069};
40704070
4071struct IrInstSrcSetEvalBranchQuota {
4072 IrInstSrc base;
4071struct Stage1ZirInstSetEvalBranchQuota {
4072 Stage1ZirInst base;
40734073
4074 IrInstSrc *new_quota;
4074 Stage1ZirInst *new_quota;
40754075};
40764076
4077struct IrInstSrcAlignCast {
4078 IrInstSrc base;
4077struct Stage1ZirInstAlignCast {
4078 Stage1ZirInst base;
40794079
4080 IrInstSrc *align_bytes;
4081 IrInstSrc *target;
4080 Stage1ZirInst *align_bytes;
4081 Stage1ZirInst *target;
40824082};
40834083
4084struct IrInstGenAlignCast {
4085 IrInstGen base;
4084struct Stage1AirInstAlignCast {
4085 Stage1AirInst base;
40864086
4087 IrInstGen *target;
4087 Stage1AirInst *target;
40884088};
40894089
4090struct IrInstSrcSetAlignStack {
4091 IrInstSrc base;
4090struct Stage1ZirInstSetAlignStack {
4091 Stage1ZirInst base;
40924092
4093 IrInstSrc *align_bytes;
4093 Stage1ZirInst *align_bytes;
40944094};
40954095
4096struct IrInstSrcArgType {
4097 IrInstSrc base;
4096struct Stage1ZirInstArgType {
4097 Stage1ZirInst base;
40984098
4099 IrInstSrc *fn_type;
4100 IrInstSrc *arg_index;
4099 Stage1ZirInst *fn_type;
4100 Stage1ZirInst *arg_index;
41014101};
41024102
4103struct IrInstSrcExport {
4104 IrInstSrc base;
4103struct Stage1ZirInstExport {
4104 Stage1ZirInst base;
41054105
4106 IrInstSrc *target;
4107 IrInstSrc *options;
4106 Stage1ZirInst *target;
4107 Stage1ZirInst *options;
41084108};
41094109
4110struct IrInstSrcExtern {
4111 IrInstSrc base;
4110struct Stage1ZirInstExtern {
4111 Stage1ZirInst base;
41124112
4113 IrInstSrc *type;
4114 IrInstSrc *options;
4113 Stage1ZirInst *type;
4114 Stage1ZirInst *options;
41154115};
41164116
4117struct IrInstGenExtern {
4118 IrInstGen base;
4117struct Stage1AirInstExtern {
4118 Stage1AirInst base;
41194119
41204120 Buf *name;
41214121 GlobalLinkageId linkage;
......@@ -4127,310 +4127,310 @@ enum IrInstErrorReturnTraceOptional {
41274127 IrInstErrorReturnTraceNonNull,
41284128};
41294129
4130struct IrInstSrcErrorReturnTrace {
4131 IrInstSrc base;
4130struct Stage1ZirInstErrorReturnTrace {
4131 Stage1ZirInst base;
41324132
41334133 IrInstErrorReturnTraceOptional optional;
41344134};
41354135
4136struct IrInstGenErrorReturnTrace {
4137 IrInstGen base;
4136struct Stage1AirInstErrorReturnTrace {
4137 Stage1AirInst base;
41384138
41394139 IrInstErrorReturnTraceOptional optional;
41404140};
41414141
4142struct IrInstSrcErrorUnion {
4143 IrInstSrc base;
4142struct Stage1ZirInstErrorUnion {
4143 Stage1ZirInst base;
41444144
4145 IrInstSrc *err_set;
4146 IrInstSrc *payload;
4145 Stage1ZirInst *err_set;
4146 Stage1ZirInst *payload;
41474147 Buf *type_name;
41484148};
41494149
4150struct IrInstSrcAtomicRmw {
4151 IrInstSrc base;
4150struct Stage1ZirInstAtomicRmw {
4151 Stage1ZirInst base;
41524152
4153 IrInstSrc *operand_type;
4154 IrInstSrc *ptr;
4155 IrInstSrc *op;
4156 IrInstSrc *operand;
4157 IrInstSrc *ordering;
4153 Stage1ZirInst *operand_type;
4154 Stage1ZirInst *ptr;
4155 Stage1ZirInst *op;
4156 Stage1ZirInst *operand;
4157 Stage1ZirInst *ordering;
41584158};
41594159
4160struct IrInstGenAtomicRmw {
4161 IrInstGen base;
4160struct Stage1AirInstAtomicRmw {
4161 Stage1AirInst base;
41624162
4163 IrInstGen *ptr;
4164 IrInstGen *operand;
4163 Stage1AirInst *ptr;
4164 Stage1AirInst *operand;
41654165 AtomicRmwOp op;
41664166 AtomicOrder ordering;
41674167};
41684168
4169struct IrInstSrcAtomicLoad {
4170 IrInstSrc base;
4169struct Stage1ZirInstAtomicLoad {
4170 Stage1ZirInst base;
41714171
4172 IrInstSrc *operand_type;
4173 IrInstSrc *ptr;
4174 IrInstSrc *ordering;
4172 Stage1ZirInst *operand_type;
4173 Stage1ZirInst *ptr;
4174 Stage1ZirInst *ordering;
41754175};
41764176
4177struct IrInstGenAtomicLoad {
4178 IrInstGen base;
4177struct Stage1AirInstAtomicLoad {
4178 Stage1AirInst base;
41794179
4180 IrInstGen *ptr;
4180 Stage1AirInst *ptr;
41814181 AtomicOrder ordering;
41824182};
41834183
4184struct IrInstSrcAtomicStore {
4185 IrInstSrc base;
4184struct Stage1ZirInstAtomicStore {
4185 Stage1ZirInst base;
41864186
4187 IrInstSrc *operand_type;
4188 IrInstSrc *ptr;
4189 IrInstSrc *value;
4190 IrInstSrc *ordering;
4187 Stage1ZirInst *operand_type;
4188 Stage1ZirInst *ptr;
4189 Stage1ZirInst *value;
4190 Stage1ZirInst *ordering;
41914191};
41924192
4193struct IrInstGenAtomicStore {
4194 IrInstGen base;
4193struct Stage1AirInstAtomicStore {
4194 Stage1AirInst base;
41954195
4196 IrInstGen *ptr;
4197 IrInstGen *value;
4196 Stage1AirInst *ptr;
4197 Stage1AirInst *value;
41984198 AtomicOrder ordering;
41994199};
42004200
4201struct IrInstSrcSaveErrRetAddr {
4202 IrInstSrc base;
4201struct Stage1ZirInstSaveErrRetAddr {
4202 Stage1ZirInst base;
42034203};
42044204
4205struct IrInstGenSaveErrRetAddr {
4206 IrInstGen base;
4205struct Stage1AirInstSaveErrRetAddr {
4206 Stage1AirInst base;
42074207};
42084208
4209struct IrInstSrcAddImplicitReturnType {
4210 IrInstSrc base;
4209struct Stage1ZirInstAddImplicitReturnType {
4210 Stage1ZirInst base;
42114211
4212 IrInstSrc *value;
4212 Stage1ZirInst *value;
42134213 ResultLocReturn *result_loc_ret;
42144214};
42154215
42164216// For float ops that take a single argument
4217struct IrInstSrcFloatOp {
4218 IrInstSrc base;
4217struct Stage1ZirInstFloatOp {
4218 Stage1ZirInst base;
42194219
4220 IrInstSrc *operand;
4220 Stage1ZirInst *operand;
42214221 BuiltinFnId fn_id;
42224222};
42234223
4224struct IrInstGenFloatOp {
4225 IrInstGen base;
4224struct Stage1AirInstFloatOp {
4225 Stage1AirInst base;
42264226
4227 IrInstGen *operand;
4227 Stage1AirInst *operand;
42284228 BuiltinFnId fn_id;
42294229};
42304230
4231struct IrInstSrcCheckRuntimeScope {
4232 IrInstSrc base;
4231struct Stage1ZirInstCheckRuntimeScope {
4232 Stage1ZirInst base;
42334233
4234 IrInstSrc *scope_is_comptime;
4235 IrInstSrc *is_comptime;
4234 Stage1ZirInst *scope_is_comptime;
4235 Stage1ZirInst *is_comptime;
42364236};
42374237
4238struct IrInstSrcBswap {
4239 IrInstSrc base;
4238struct Stage1ZirInstBswap {
4239 Stage1ZirInst base;
42404240
4241 IrInstSrc *type;
4242 IrInstSrc *op;
4241 Stage1ZirInst *type;
4242 Stage1ZirInst *op;
42434243};
42444244
4245struct IrInstGenBswap {
4246 IrInstGen base;
4245struct Stage1AirInstBswap {
4246 Stage1AirInst base;
42474247
4248 IrInstGen *op;
4248 Stage1AirInst *op;
42494249};
42504250
4251struct IrInstSrcBitReverse {
4252 IrInstSrc base;
4251struct Stage1ZirInstBitReverse {
4252 Stage1ZirInst base;
42534253
4254 IrInstSrc *type;
4255 IrInstSrc *op;
4254 Stage1ZirInst *type;
4255 Stage1ZirInst *op;
42564256};
42574257
4258struct IrInstGenBitReverse {
4259 IrInstGen base;
4258struct Stage1AirInstBitReverse {
4259 Stage1AirInst base;
42604260
4261 IrInstGen *op;
4261 Stage1AirInst *op;
42624262};
42634263
4264struct IrInstGenArrayToVector {
4265 IrInstGen base;
4264struct Stage1AirInstArrayToVector {
4265 Stage1AirInst base;
42664266
4267 IrInstGen *array;
4267 Stage1AirInst *array;
42684268};
42694269
4270struct IrInstGenVectorToArray {
4271 IrInstGen base;
4270struct Stage1AirInstVectorToArray {
4271 Stage1AirInst base;
42724272
4273 IrInstGen *vector;
4274 IrInstGen *result_loc;
4273 Stage1AirInst *vector;
4274 Stage1AirInst *result_loc;
42754275};
42764276
4277struct IrInstSrcShuffleVector {
4278 IrInstSrc base;
4277struct Stage1ZirInstShuffleVector {
4278 Stage1ZirInst base;
42794279
4280 IrInstSrc *scalar_type;
4281 IrInstSrc *a;
4282 IrInstSrc *b;
4283 IrInstSrc *mask; // This is in zig-format, not llvm format
4280 Stage1ZirInst *scalar_type;
4281 Stage1ZirInst *a;
4282 Stage1ZirInst *b;
4283 Stage1ZirInst *mask; // This is in zig-format, not llvm format
42844284};
42854285
4286struct IrInstGenShuffleVector {
4287 IrInstGen base;
4286struct Stage1AirInstShuffleVector {
4287 Stage1AirInst base;
42884288
4289 IrInstGen *a;
4290 IrInstGen *b;
4291 IrInstGen *mask; // This is in zig-format, not llvm format
4289 Stage1AirInst *a;
4290 Stage1AirInst *b;
4291 Stage1AirInst *mask; // This is in zig-format, not llvm format
42924292};
42934293
4294struct IrInstSrcSplat {
4295 IrInstSrc base;
4294struct Stage1ZirInstSplat {
4295 Stage1ZirInst base;
42964296
4297 IrInstSrc *len;
4298 IrInstSrc *scalar;
4297 Stage1ZirInst *len;
4298 Stage1ZirInst *scalar;
42994299};
43004300
4301struct IrInstGenSplat {
4302 IrInstGen base;
4301struct Stage1AirInstSplat {
4302 Stage1AirInst base;
43034303
4304 IrInstGen *scalar;
4304 Stage1AirInst *scalar;
43054305};
43064306
4307struct IrInstGenAssertZero {
4308 IrInstGen base;
4307struct Stage1AirInstAssertZero {
4308 Stage1AirInst base;
43094309
4310 IrInstGen *target;
4310 Stage1AirInst *target;
43114311};
43124312
4313struct IrInstGenAssertNonNull {
4314 IrInstGen base;
4313struct Stage1AirInstAssertNonNull {
4314 Stage1AirInst base;
43154315
4316 IrInstGen *target;
4316 Stage1AirInst *target;
43174317};
43184318
4319struct IrInstSrcUnionInitNamedField {
4320 IrInstSrc base;
4319struct Stage1ZirInstUnionInitNamedField {
4320 Stage1ZirInst base;
43214321
4322 IrInstSrc *union_type;
4323 IrInstSrc *field_name;
4324 IrInstSrc *field_result_loc;
4325 IrInstSrc *result_loc;
4322 Stage1ZirInst *union_type;
4323 Stage1ZirInst *field_name;
4324 Stage1ZirInst *field_result_loc;
4325 Stage1ZirInst *result_loc;
43264326};
43274327
4328struct IrInstSrcHasDecl {
4329 IrInstSrc base;
4328struct Stage1ZirInstHasDecl {
4329 Stage1ZirInst base;
43304330
4331 IrInstSrc *container;
4332 IrInstSrc *name;
4331 Stage1ZirInst *container;
4332 Stage1ZirInst *name;
43334333};
43344334
4335struct IrInstSrcUndeclaredIdent {
4336 IrInstSrc base;
4335struct Stage1ZirInstUndeclaredIdent {
4336 Stage1ZirInst base;
43374337
43384338 Buf *name;
43394339};
43404340
4341struct IrInstSrcAlloca {
4342 IrInstSrc base;
4341struct Stage1ZirInstAlloca {
4342 Stage1ZirInst base;
43434343
4344 IrInstSrc *align;
4345 IrInstSrc *is_comptime;
4344 Stage1ZirInst *align;
4345 Stage1ZirInst *is_comptime;
43464346 const char *name_hint;
43474347};
43484348
4349struct IrInstGenAlloca {
4350 IrInstGen base;
4349struct Stage1AirInstAlloca {
4350 Stage1AirInst base;
43514351
43524352 uint32_t align;
43534353 const char *name_hint;
43544354 size_t field_index;
43554355};
43564356
4357struct IrInstSrcEndExpr {
4358 IrInstSrc base;
4357struct Stage1ZirInstEndExpr {
4358 Stage1ZirInst base;
43594359
4360 IrInstSrc *value;
4360 Stage1ZirInst *value;
43614361 ResultLoc *result_loc;
43624362};
43634363
43644364// This one is for writing through the result pointer.
4365struct IrInstSrcResolveResult {
4366 IrInstSrc base;
4365struct Stage1ZirInstResolveResult {
4366 Stage1ZirInst base;
43674367
43684368 ResultLoc *result_loc;
4369 IrInstSrc *ty;
4369 Stage1ZirInst *ty;
43704370};
43714371
4372struct IrInstSrcResetResult {
4373 IrInstSrc base;
4372struct Stage1ZirInstResetResult {
4373 Stage1ZirInst base;
43744374
43754375 ResultLoc *result_loc;
43764376};
43774377
4378struct IrInstGenPtrOfArrayToSlice {
4379 IrInstGen base;
4378struct Stage1AirInstPtrOfArrayToSlice {
4379 Stage1AirInst base;
43804380
4381 IrInstGen *operand;
4382 IrInstGen *result_loc;
4381 Stage1AirInst *operand;
4382 Stage1AirInst *result_loc;
43834383};
43844384
4385struct IrInstSrcSuspendBegin {
4386 IrInstSrc base;
4385struct Stage1ZirInstSuspendBegin {
4386 Stage1ZirInst base;
43874387};
43884388
4389struct IrInstGenSuspendBegin {
4390 IrInstGen base;
4389struct Stage1AirInstSuspendBegin {
4390 Stage1AirInst base;
43914391
43924392 LLVMBasicBlockRef resume_bb;
43934393};
43944394
4395struct IrInstSrcSuspendFinish {
4396 IrInstSrc base;
4395struct Stage1ZirInstSuspendFinish {
4396 Stage1ZirInst base;
43974397
4398 IrInstSrcSuspendBegin *begin;
4398 Stage1ZirInstSuspendBegin *begin;
43994399};
44004400
4401struct IrInstGenSuspendFinish {
4402 IrInstGen base;
4401struct Stage1AirInstSuspendFinish {
4402 Stage1AirInst base;
44034403
4404 IrInstGenSuspendBegin *begin;
4404 Stage1AirInstSuspendBegin *begin;
44054405};
44064406
4407struct IrInstSrcAwait {
4408 IrInstSrc base;
4407struct Stage1ZirInstAwait {
4408 Stage1ZirInst base;
44094409
4410 IrInstSrc *frame;
4410 Stage1ZirInst *frame;
44114411 ResultLoc *result_loc;
44124412 bool is_nosuspend;
44134413};
44144414
4415struct IrInstGenAwait {
4416 IrInstGen base;
4415struct Stage1AirInstAwait {
4416 Stage1AirInst base;
44174417
4418 IrInstGen *frame;
4419 IrInstGen *result_loc;
4418 Stage1AirInst *frame;
4419 Stage1AirInst *result_loc;
44204420 ZigFn *target_fn;
44214421 bool is_nosuspend;
44224422};
44234423
4424struct IrInstSrcResume {
4425 IrInstSrc base;
4424struct Stage1ZirInstResume {
4425 Stage1ZirInst base;
44264426
4427 IrInstSrc *frame;
4427 Stage1ZirInst *frame;
44284428};
44294429
4430struct IrInstGenResume {
4431 IrInstGen base;
4430struct Stage1AirInstResume {
4431 Stage1AirInst base;
44324432
4433 IrInstGen *frame;
4433 Stage1AirInst *frame;
44344434};
44354435
44364436enum SpillId {
......@@ -4438,37 +4438,37 @@ enum SpillId {
44384438 SpillIdRetErrCode,
44394439};
44404440
4441struct IrInstSrcSpillBegin {
4442 IrInstSrc base;
4441struct Stage1ZirInstSpillBegin {
4442 Stage1ZirInst base;
44434443
4444 IrInstSrc *operand;
4444 Stage1ZirInst *operand;
44454445 SpillId spill_id;
44464446};
44474447
4448struct IrInstGenSpillBegin {
4449 IrInstGen base;
4448struct Stage1AirInstSpillBegin {
4449 Stage1AirInst base;
44504450
44514451 SpillId spill_id;
4452 IrInstGen *operand;
4452 Stage1AirInst *operand;
44534453};
44544454
4455struct IrInstSrcSpillEnd {
4456 IrInstSrc base;
4455struct Stage1ZirInstSpillEnd {
4456 Stage1ZirInst base;
44574457
4458 IrInstSrcSpillBegin *begin;
4458 Stage1ZirInstSpillBegin *begin;
44594459};
44604460
4461struct IrInstGenSpillEnd {
4462 IrInstGen base;
4461struct Stage1AirInstSpillEnd {
4462 Stage1AirInst base;
44634463
4464 IrInstGenSpillBegin *begin;
4464 Stage1AirInstSpillBegin *begin;
44654465};
44664466
4467struct IrInstGenVectorExtractElem {
4468 IrInstGen base;
4467struct Stage1AirInstVectorExtractElem {
4468 Stage1AirInst base;
44694469
4470 IrInstGen *vector;
4471 IrInstGen *index;
4470 Stage1AirInst *vector;
4471 Stage1AirInst *index;
44724472};
44734473
44744474enum ResultLocId {
......@@ -4489,9 +4489,9 @@ struct ResultLoc {
44894489 ResultLocId id;
44904490 bool written;
44914491 bool allow_write_through_const;
4492 IrInstGen *resolved_loc; // result ptr
4493 IrInstSrc *source_instruction;
4494 IrInstGen *gen_instruction; // value to store to the result loc
4492 Stage1AirInst *resolved_loc; // result ptr
4493 Stage1ZirInst *source_instruction;
4494 Stage1AirInst *gen_instruction; // value to store to the result loc
44954495 ZigType *implicit_elem_type;
44964496};
44974497
......@@ -4525,7 +4525,7 @@ struct ResultLocPeerParent {
45254525 ResultLoc *parent;
45264526 ZigList<ResultLocPeer *> peers;
45274527 ZigType *resolved_type;
4528 IrInstSrc *is_comptime;
4528 Stage1ZirInst *is_comptime;
45294529};
45304530
45314531struct ResultLocPeer {
......@@ -4603,7 +4603,7 @@ struct FnWalkAttrs {
46034603struct FnWalkCall {
46044604 ZigList<LLVMValueRef> *gen_param_values;
46054605 ZigList<ZigType *> *gen_param_types;
4606 IrInstGenCall *inst;
4606 Stage1AirInstCall *inst;
46074607 bool is_var_args;
46084608};
46094609
src/stage1/analyze.cpp+23-23
......@@ -206,7 +206,7 @@ ScopeLoop *create_loop_scope(CodeGen *g, AstNode *node, Scope *parent) {
206206 return scope;
207207}
208208
209Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, IrInstSrc *is_comptime) {
209Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, Stage1ZirInst *is_comptime) {
210210 ScopeRuntime *scope = heap::c_allocator.create<ScopeRuntime>();
211211 scope->is_comptime = is_comptime;
212212 init_scope(g, &scope->base, ScopeIdRuntime, node, parent);
......@@ -5071,7 +5071,7 @@ static void analyze_fn_async(CodeGen *g, ZigFn *fn, bool resolve_frame) {
50715071 }
50725072
50735073 for (size_t i = 0; i < fn->call_list.length; i += 1) {
5074 IrInstGenCall *call = fn->call_list.at(i);
5074 Stage1AirInstCall *call = fn->call_list.at(i);
50755075 if (call->fn_entry == nullptr) {
50765076 // TODO function pointer call here, could be anything
50775077 continue;
......@@ -5094,7 +5094,7 @@ static void analyze_fn_async(CodeGen *g, ZigFn *fn, bool resolve_frame) {
50945094 }
50955095 }
50965096 for (size_t i = 0; i < fn->await_list.length; i += 1) {
5097 IrInstGenAwait *await = fn->await_list.at(i);
5097 Stage1AirInstAwait *await = fn->await_list.at(i);
50985098 if (await->is_nosuspend) continue;
50995099 switch (analyze_callee_async(g, fn, await->target_fn, await->base.source_node, must_not_be_async,
51005100 CallModifierNone))
......@@ -6755,8 +6755,8 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
67556755 ZigType *fn_type = get_async_fn_type(g, fn->type_entry);
67566756
67576757 if (fn->analyzed_executable.need_err_code_spill) {
6758 IrInstGenAlloca *alloca_gen = heap::c_allocator.create<IrInstGenAlloca>();
6759 alloca_gen->base.id = IrInstGenIdAlloca;
6758 Stage1AirInstAlloca *alloca_gen = heap::c_allocator.create<Stage1AirInstAlloca>();
6759 alloca_gen->base.id = Stage1AirInstIdAlloca;
67606760 alloca_gen->base.source_node = fn->proto_node;
67616761 alloca_gen->base.scope = fn->child_scope;
67626762 alloca_gen->base.value = g->pass1_arena->create<ZigValue>();
......@@ -6769,11 +6769,11 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
67696769
67706770 ZigType *largest_call_frame_type = nullptr;
67716771 // Later we'll change this to be largest_call_frame_type instead of void.
6772 IrInstGen *all_calls_alloca = ir_create_alloca(g, &fn->fndef_scope->base, fn->body_node,
6772 Stage1AirInst *all_calls_alloca = ir_create_alloca(g, &fn->fndef_scope->base, fn->body_node,
67736773 fn, g->builtin_types.entry_void, "@async_call_frame");
67746774
67756775 for (size_t i = 0; i < fn->call_list.length; i += 1) {
6776 IrInstGenCall *call = fn->call_list.at(i);
6776 Stage1AirInstCall *call = fn->call_list.at(i);
67776777 if (call->new_stack != nullptr) {
67786778 // don't need to allocate a frame for this
67796779 continue;
......@@ -6838,7 +6838,7 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
68386838 // For example: foo() + await z
68396839 // The funtion call result of foo() must be spilled.
68406840 for (size_t i = 0; i < fn->await_list.length; i += 1) {
6841 IrInstGenAwait *await = fn->await_list.at(i);
6841 Stage1AirInstAwait *await = fn->await_list.at(i);
68426842 if (await->is_nosuspend) {
68436843 continue;
68446844 }
......@@ -6875,10 +6875,10 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
68756875 await->base.value->type, "");
68766876 }
68776877 for (size_t block_i = 0; block_i < fn->analyzed_executable.basic_block_list.length; block_i += 1) {
6878 IrBasicBlockGen *block = fn->analyzed_executable.basic_block_list.at(block_i);
6878 Stage1AirBasicBlock *block = fn->analyzed_executable.basic_block_list.at(block_i);
68796879 for (size_t instr_i = 0; instr_i < block->instruction_list.length; instr_i += 1) {
6880 IrInstGen *instruction = block->instruction_list.at(instr_i);
6881 if (instruction->id == IrInstGenIdSuspendFinish) {
6880 Stage1AirInst *instruction = block->instruction_list.at(instr_i);
6881 if (instruction->id == Stage1AirInstIdSuspendFinish) {
68826882 mark_suspension_point(instruction->scope);
68836883 }
68846884 }
......@@ -6886,20 +6886,20 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
68866886 // Now that we've marked all the expr scopes that have to spill, we go over the instructions
68876887 // and spill the relevant ones.
68886888 for (size_t block_i = 0; block_i < fn->analyzed_executable.basic_block_list.length; block_i += 1) {
6889 IrBasicBlockGen *block = fn->analyzed_executable.basic_block_list.at(block_i);
6889 Stage1AirBasicBlock *block = fn->analyzed_executable.basic_block_list.at(block_i);
68906890 for (size_t instr_i = 0; instr_i < block->instruction_list.length; instr_i += 1) {
6891 IrInstGen *instruction = block->instruction_list.at(instr_i);
6892 if (instruction->id == IrInstGenIdAwait ||
6893 instruction->id == IrInstGenIdVarPtr ||
6894 instruction->id == IrInstGenIdAlloca ||
6895 instruction->id == IrInstGenIdSpillBegin ||
6896 instruction->id == IrInstGenIdSpillEnd)
6891 Stage1AirInst *instruction = block->instruction_list.at(instr_i);
6892 if (instruction->id == Stage1AirInstIdAwait ||
6893 instruction->id == Stage1AirInstIdVarPtr ||
6894 instruction->id == Stage1AirInstIdAlloca ||
6895 instruction->id == Stage1AirInstIdSpillBegin ||
6896 instruction->id == Stage1AirInstIdSpillEnd)
68976897 {
68986898 // This instruction does its own spilling specially, or otherwise doesn't need it.
68996899 continue;
69006900 }
6901 if (instruction->id == IrInstGenIdCast &&
6902 reinterpret_cast<IrInstGenCast *>(instruction)->cast_op == CastOpNoop)
6901 if (instruction->id == Stage1AirInstIdCast &&
6902 reinterpret_cast<Stage1AirInstCast *>(instruction)->cast_op == CastOpNoop)
69036903 {
69046904 // The IR instruction exists only to change the type according to Zig. No spill needed.
69056905 continue;
......@@ -6964,7 +6964,7 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) {
69646964 }
69656965
69666966 for (size_t alloca_i = 0; alloca_i < fn->alloca_gen_list.length; alloca_i += 1) {
6967 IrInstGenAlloca *instruction = fn->alloca_gen_list.at(alloca_i);
6967 Stage1AirInstAlloca *instruction = fn->alloca_gen_list.at(alloca_i);
69686968 instruction->field_index = SIZE_MAX;
69696969 ZigType *ptr_type = instruction->base.value->type;
69706970 assert(ptr_type->id == ZigTypeIdPointer);
......@@ -7146,8 +7146,8 @@ bool ir_get_var_is_comptime(ZigVar *var) {
71467146 // As an optimization, is_comptime values which are constant are allowed
71477147 // to be omitted from analysis. In this case, there is no child instruction
71487148 // and we simply look at the unanalyzed const parent instruction.
7149 assert(var->is_comptime->id == IrInstSrcIdConst);
7150 IrInstSrcConst *const_inst = reinterpret_cast<IrInstSrcConst *>(var->is_comptime);
7149 assert(var->is_comptime->id == Stage1ZirInstIdConst);
7150 Stage1ZirInstConst *const_inst = reinterpret_cast<Stage1ZirInstConst *>(var->is_comptime);
71517151 assert(const_inst->value->type->id == ZigTypeIdBool);
71527152 var->is_comptime_memoized_value = const_inst->value->data.x_bool;
71537153 var->is_comptime = nullptr;
src/stage1/analyze.hpp+1-1
......@@ -138,7 +138,7 @@ ScopeSuspend *create_suspend_scope(CodeGen *g, AstNode *node, Scope *parent);
138138ScopeFnDef *create_fndef_scope(CodeGen *g, AstNode *node, Scope *parent, ZigFn *fn_entry);
139139Scope *create_comptime_scope(CodeGen *g, AstNode *node, Scope *parent);
140140Scope *create_nosuspend_scope(CodeGen *g, AstNode *node, Scope *parent);
141Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, IrInstSrc *is_comptime);
141Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, Stage1ZirInst *is_comptime);
142142Scope *create_typeof_scope(CodeGen *g, AstNode *node, Scope *parent);
143143ScopeExpr *create_expr_scope(CodeGen *g, AstNode *node, Scope *parent);
144144
src/stage1/astgen.cpp+1569-1569
......@@ -21,25 +21,25 @@ struct Stage1AstGen {
2121 bool in_c_import_scope;
2222};
2323
24static IrInstSrc *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope);
25static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval,
24static Stage1ZirInst *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope);
25static Stage1ZirInst *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval,
2626 ResultLoc *result_loc);
2727
28static IrInstSrc *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *value, LVal lval,
28static Stage1ZirInst *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *value, LVal lval,
2929 ResultLoc *result_loc);
30static IrInstSrc *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *inst,
30static Stage1ZirInst *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *inst,
3131 ResultLoc *result_loc);
32static IrInstSrc *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
33 IrInstSrc *union_type, IrInstSrc *field_name, AstNode *expr_node,
32static Stage1ZirInst *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
33 Stage1ZirInst *union_type, Stage1ZirInst *field_name, AstNode *expr_node,
3434 LVal lval, ResultLoc *parent_result_loc);
35static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, IrInstSrc *dest_type,
35static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, Stage1ZirInst *dest_type,
3636 ResultLoc *parent_result_loc);
3737static ZigVar *ir_create_var(Stage1AstGen *ag, AstNode *node, Scope *scope, Buf *name,
38 bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime);
38 bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime);
3939static void build_decl_var_and_init(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
40 ZigVar *var, IrInstSrc *init, const char *name_hint, IrInstSrc *is_comptime);
40 ZigVar *var, Stage1ZirInst *init, const char *name_hint, Stage1ZirInst *is_comptime);
4141
42static void ir_assert_impl(bool ok, IrInstSrc *source_instruction, char const *file, unsigned int line) {
42static void ir_assert_impl(bool ok, Stage1ZirInst *source_instruction, char const *file, unsigned int line) {
4343 if (ok) return;
4444 src_assert_impl(ok, source_instruction->source_node, file, line);
4545}
......@@ -54,299 +54,299 @@ static ErrorMsg *exec_add_error_node(CodeGen *codegen, Stage1Zir *exec, AstNode
5454#define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__)
5555
5656
57static bool instr_is_unreachable(IrInstSrc *instruction) {
57static bool instr_is_unreachable(Stage1ZirInst *instruction) {
5858 switch (instruction->id) {
59 case IrInstSrcIdCondBr:
60 case IrInstSrcIdReturn:
61 case IrInstSrcIdBr:
62 case IrInstSrcIdUnreachable:
63 case IrInstSrcIdSwitchBr:
64 case IrInstSrcIdPanic:
59 case Stage1ZirInstIdCondBr:
60 case Stage1ZirInstIdReturn:
61 case Stage1ZirInstIdBr:
62 case Stage1ZirInstIdUnreachable:
63 case Stage1ZirInstIdSwitchBr:
64 case Stage1ZirInstIdPanic:
6565 return true;
6666 default:
6767 return false;
6868 }
6969}
7070
71void destroy_instruction_src(IrInstSrc *inst) {
71void destroy_instruction_src(Stage1ZirInst *inst) {
7272 switch (inst->id) {
73 case IrInstSrcIdInvalid:
73 case Stage1ZirInstIdInvalid:
7474 zig_unreachable();
75 case IrInstSrcIdReturn:
76 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcReturn *>(inst));
77 case IrInstSrcIdConst:
78 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcConst *>(inst));
79 case IrInstSrcIdBinOp:
80 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBinOp *>(inst));
81 case IrInstSrcIdMergeErrSets:
82 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcMergeErrSets *>(inst));
83 case IrInstSrcIdDeclVar:
84 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcDeclVar *>(inst));
85 case IrInstSrcIdCall:
86 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCall *>(inst));
87 case IrInstSrcIdCallExtra:
88 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCallExtra *>(inst));
89 case IrInstSrcIdAsyncCallExtra:
90 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAsyncCallExtra *>(inst));
91 case IrInstSrcIdUnOp:
92 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUnOp *>(inst));
93 case IrInstSrcIdCondBr:
94 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCondBr *>(inst));
95 case IrInstSrcIdBr:
96 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBr *>(inst));
97 case IrInstSrcIdPhi:
98 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPhi *>(inst));
99 case IrInstSrcIdContainerInitList:
100 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcContainerInitList *>(inst));
101 case IrInstSrcIdContainerInitFields:
102 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcContainerInitFields *>(inst));
103 case IrInstSrcIdUnreachable:
104 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUnreachable *>(inst));
105 case IrInstSrcIdElemPtr:
106 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcElemPtr *>(inst));
107 case IrInstSrcIdVarPtr:
108 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcVarPtr *>(inst));
109 case IrInstSrcIdLoadPtr:
110 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcLoadPtr *>(inst));
111 case IrInstSrcIdStorePtr:
112 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcStorePtr *>(inst));
113 case IrInstSrcIdTypeOf:
114 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTypeOf *>(inst));
115 case IrInstSrcIdFieldPtr:
116 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFieldPtr *>(inst));
117 case IrInstSrcIdSetCold:
118 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSetCold *>(inst));
119 case IrInstSrcIdSetRuntimeSafety:
120 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSetRuntimeSafety *>(inst));
121 case IrInstSrcIdSetFloatMode:
122 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSetFloatMode *>(inst));
123 case IrInstSrcIdArrayType:
124 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcArrayType *>(inst));
125 case IrInstSrcIdSliceType:
126 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSliceType *>(inst));
127 case IrInstSrcIdAnyFrameType:
128 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAnyFrameType *>(inst));
129 case IrInstSrcIdAsm:
130 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAsm *>(inst));
131 case IrInstSrcIdSizeOf:
132 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSizeOf *>(inst));
133 case IrInstSrcIdTestNonNull:
134 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTestNonNull *>(inst));
135 case IrInstSrcIdOptionalUnwrapPtr:
136 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcOptionalUnwrapPtr *>(inst));
137 case IrInstSrcIdPopCount:
138 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPopCount *>(inst));
139 case IrInstSrcIdClz:
140 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcClz *>(inst));
141 case IrInstSrcIdCtz:
142 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCtz *>(inst));
143 case IrInstSrcIdBswap:
144 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBswap *>(inst));
145 case IrInstSrcIdBitReverse:
146 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBitReverse *>(inst));
147 case IrInstSrcIdSwitchBr:
148 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSwitchBr *>(inst));
149 case IrInstSrcIdSwitchVar:
150 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSwitchVar *>(inst));
151 case IrInstSrcIdSwitchElseVar:
152 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSwitchElseVar *>(inst));
153 case IrInstSrcIdSwitchTarget:
154 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSwitchTarget *>(inst));
155 case IrInstSrcIdImport:
156 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcImport *>(inst));
157 case IrInstSrcIdRef:
158 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcRef *>(inst));
159 case IrInstSrcIdCompileErr:
160 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCompileErr *>(inst));
161 case IrInstSrcIdCompileLog:
162 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCompileLog *>(inst));
163 case IrInstSrcIdErrName:
164 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcErrName *>(inst));
165 case IrInstSrcIdCImport:
166 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCImport *>(inst));
167 case IrInstSrcIdCInclude:
168 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCInclude *>(inst));
169 case IrInstSrcIdCDefine:
170 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCDefine *>(inst));
171 case IrInstSrcIdCUndef:
172 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCUndef *>(inst));
173 case IrInstSrcIdEmbedFile:
174 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcEmbedFile *>(inst));
175 case IrInstSrcIdCmpxchg:
176 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCmpxchg *>(inst));
177 case IrInstSrcIdFence:
178 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFence *>(inst));
179 case IrInstSrcIdReduce:
180 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcReduce *>(inst));
181 case IrInstSrcIdTruncate:
182 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTruncate *>(inst));
183 case IrInstSrcIdIntCast:
184 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcIntCast *>(inst));
185 case IrInstSrcIdFloatCast:
186 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFloatCast *>(inst));
187 case IrInstSrcIdErrSetCast:
188 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcErrSetCast *>(inst));
189 case IrInstSrcIdIntToFloat:
190 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcIntToFloat *>(inst));
191 case IrInstSrcIdFloatToInt:
192 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFloatToInt *>(inst));
193 case IrInstSrcIdBoolToInt:
194 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBoolToInt *>(inst));
195 case IrInstSrcIdVectorType:
196 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcVectorType *>(inst));
197 case IrInstSrcIdShuffleVector:
198 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcShuffleVector *>(inst));
199 case IrInstSrcIdSplat:
200 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSplat *>(inst));
201 case IrInstSrcIdBoolNot:
202 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBoolNot *>(inst));
203 case IrInstSrcIdMemset:
204 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcMemset *>(inst));
205 case IrInstSrcIdMemcpy:
206 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcMemcpy *>(inst));
207 case IrInstSrcIdSlice:
208 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSlice *>(inst));
209 case IrInstSrcIdBreakpoint:
210 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBreakpoint *>(inst));
211 case IrInstSrcIdReturnAddress:
212 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcReturnAddress *>(inst));
213 case IrInstSrcIdFrameAddress:
214 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFrameAddress *>(inst));
215 case IrInstSrcIdFrameHandle:
216 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFrameHandle *>(inst));
217 case IrInstSrcIdFrameType:
218 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFrameType *>(inst));
219 case IrInstSrcIdFrameSize:
220 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFrameSize *>(inst));
221 case IrInstSrcIdAlignOf:
222 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAlignOf *>(inst));
223 case IrInstSrcIdOverflowOp:
224 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcOverflowOp *>(inst));
225 case IrInstSrcIdTestErr:
226 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTestErr *>(inst));
227 case IrInstSrcIdUnwrapErrCode:
228 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUnwrapErrCode *>(inst));
229 case IrInstSrcIdUnwrapErrPayload:
230 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUnwrapErrPayload *>(inst));
231 case IrInstSrcIdFnProto:
232 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFnProto *>(inst));
233 case IrInstSrcIdTestComptime:
234 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTestComptime *>(inst));
235 case IrInstSrcIdPtrCast:
236 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPtrCast *>(inst));
237 case IrInstSrcIdBitCast:
238 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBitCast *>(inst));
239 case IrInstSrcIdPtrToInt:
240 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPtrToInt *>(inst));
241 case IrInstSrcIdIntToPtr:
242 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcIntToPtr *>(inst));
243 case IrInstSrcIdIntToEnum:
244 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcIntToEnum *>(inst));
245 case IrInstSrcIdIntToErr:
246 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcIntToErr *>(inst));
247 case IrInstSrcIdErrToInt:
248 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcErrToInt *>(inst));
249 case IrInstSrcIdCheckSwitchProngsUnderNo:
250 case IrInstSrcIdCheckSwitchProngsUnderYes:
251 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCheckSwitchProngs *>(inst));
252 case IrInstSrcIdCheckStatementIsVoid:
253 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCheckStatementIsVoid *>(inst));
254 case IrInstSrcIdTypeName:
255 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTypeName *>(inst));
256 case IrInstSrcIdTagName:
257 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTagName *>(inst));
258 case IrInstSrcIdPtrType:
259 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPtrType *>(inst));
260 case IrInstSrcIdPtrTypeSimple:
261 case IrInstSrcIdPtrTypeSimpleConst:
262 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPtrTypeSimple *>(inst));
263 case IrInstSrcIdDeclRef:
264 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcDeclRef *>(inst));
265 case IrInstSrcIdPanic:
266 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcPanic *>(inst));
267 case IrInstSrcIdFieldParentPtr:
268 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFieldParentPtr *>(inst));
269 case IrInstSrcIdOffsetOf:
270 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcOffsetOf *>(inst));
271 case IrInstSrcIdBitOffsetOf:
272 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBitOffsetOf *>(inst));
273 case IrInstSrcIdTypeInfo:
274 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcTypeInfo *>(inst));
275 case IrInstSrcIdType:
276 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcType *>(inst));
277 case IrInstSrcIdHasField:
278 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcHasField *>(inst));
279 case IrInstSrcIdSetEvalBranchQuota:
280 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSetEvalBranchQuota *>(inst));
281 case IrInstSrcIdAlignCast:
282 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAlignCast *>(inst));
283 case IrInstSrcIdImplicitCast:
284 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcImplicitCast *>(inst));
285 case IrInstSrcIdResolveResult:
286 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcResolveResult *>(inst));
287 case IrInstSrcIdResetResult:
288 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcResetResult *>(inst));
289 case IrInstSrcIdSetAlignStack:
290 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSetAlignStack *>(inst));
291 case IrInstSrcIdArgTypeAllowVarFalse:
292 case IrInstSrcIdArgTypeAllowVarTrue:
293 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcArgType *>(inst));
294 case IrInstSrcIdExport:
295 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcExport *>(inst));
296 case IrInstSrcIdExtern:
297 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcExtern *>(inst));
298 case IrInstSrcIdErrorReturnTrace:
299 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcErrorReturnTrace *>(inst));
300 case IrInstSrcIdErrorUnion:
301 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcErrorUnion *>(inst));
302 case IrInstSrcIdAtomicRmw:
303 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAtomicRmw *>(inst));
304 case IrInstSrcIdSaveErrRetAddr:
305 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSaveErrRetAddr *>(inst));
306 case IrInstSrcIdAddImplicitReturnType:
307 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAddImplicitReturnType *>(inst));
308 case IrInstSrcIdFloatOp:
309 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFloatOp *>(inst));
310 case IrInstSrcIdMulAdd:
311 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcMulAdd *>(inst));
312 case IrInstSrcIdAtomicLoad:
313 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAtomicLoad *>(inst));
314 case IrInstSrcIdAtomicStore:
315 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAtomicStore *>(inst));
316 case IrInstSrcIdEnumToInt:
317 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcEnumToInt *>(inst));
318 case IrInstSrcIdCheckRuntimeScope:
319 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCheckRuntimeScope *>(inst));
320 case IrInstSrcIdHasDecl:
321 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcHasDecl *>(inst));
322 case IrInstSrcIdUndeclaredIdent:
323 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUndeclaredIdent *>(inst));
324 case IrInstSrcIdAlloca:
325 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAlloca *>(inst));
326 case IrInstSrcIdEndExpr:
327 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcEndExpr *>(inst));
328 case IrInstSrcIdUnionInitNamedField:
329 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcUnionInitNamedField *>(inst));
330 case IrInstSrcIdSuspendBegin:
331 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSuspendBegin *>(inst));
332 case IrInstSrcIdSuspendFinish:
333 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSuspendFinish *>(inst));
334 case IrInstSrcIdResume:
335 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcResume *>(inst));
336 case IrInstSrcIdAwait:
337 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcAwait *>(inst));
338 case IrInstSrcIdSpillBegin:
339 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSpillBegin *>(inst));
340 case IrInstSrcIdSpillEnd:
341 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSpillEnd *>(inst));
342 case IrInstSrcIdCallArgs:
343 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCallArgs *>(inst));
344 case IrInstSrcIdWasmMemorySize:
345 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcWasmMemorySize *>(inst));
346 case IrInstSrcIdWasmMemoryGrow:
347 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcWasmMemoryGrow *>(inst));
348 case IrInstSrcIdSrc:
349 return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcSrc *>(inst));
75 case Stage1ZirInstIdReturn:
76 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstReturn *>(inst));
77 case Stage1ZirInstIdConst:
78 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstConst *>(inst));
79 case Stage1ZirInstIdBinOp:
80 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBinOp *>(inst));
81 case Stage1ZirInstIdMergeErrSets:
82 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstMergeErrSets *>(inst));
83 case Stage1ZirInstIdDeclVar:
84 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstDeclVar *>(inst));
85 case Stage1ZirInstIdCall:
86 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCall *>(inst));
87 case Stage1ZirInstIdCallExtra:
88 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCallExtra *>(inst));
89 case Stage1ZirInstIdAsyncCallExtra:
90 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAsyncCallExtra *>(inst));
91 case Stage1ZirInstIdUnOp:
92 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUnOp *>(inst));
93 case Stage1ZirInstIdCondBr:
94 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCondBr *>(inst));
95 case Stage1ZirInstIdBr:
96 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBr *>(inst));
97 case Stage1ZirInstIdPhi:
98 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPhi *>(inst));
99 case Stage1ZirInstIdContainerInitList:
100 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstContainerInitList *>(inst));
101 case Stage1ZirInstIdContainerInitFields:
102 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstContainerInitFields *>(inst));
103 case Stage1ZirInstIdUnreachable:
104 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUnreachable *>(inst));
105 case Stage1ZirInstIdElemPtr:
106 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstElemPtr *>(inst));
107 case Stage1ZirInstIdVarPtr:
108 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstVarPtr *>(inst));
109 case Stage1ZirInstIdLoadPtr:
110 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstLoadPtr *>(inst));
111 case Stage1ZirInstIdStorePtr:
112 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstStorePtr *>(inst));
113 case Stage1ZirInstIdTypeOf:
114 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTypeOf *>(inst));
115 case Stage1ZirInstIdFieldPtr:
116 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFieldPtr *>(inst));
117 case Stage1ZirInstIdSetCold:
118 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSetCold *>(inst));
119 case Stage1ZirInstIdSetRuntimeSafety:
120 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSetRuntimeSafety *>(inst));
121 case Stage1ZirInstIdSetFloatMode:
122 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSetFloatMode *>(inst));
123 case Stage1ZirInstIdArrayType:
124 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstArrayType *>(inst));
125 case Stage1ZirInstIdSliceType:
126 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSliceType *>(inst));
127 case Stage1ZirInstIdAnyFrameType:
128 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAnyFrameType *>(inst));
129 case Stage1ZirInstIdAsm:
130 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAsm *>(inst));
131 case Stage1ZirInstIdSizeOf:
132 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSizeOf *>(inst));
133 case Stage1ZirInstIdTestNonNull:
134 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTestNonNull *>(inst));
135 case Stage1ZirInstIdOptionalUnwrapPtr:
136 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstOptionalUnwrapPtr *>(inst));
137 case Stage1ZirInstIdPopCount:
138 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPopCount *>(inst));
139 case Stage1ZirInstIdClz:
140 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstClz *>(inst));
141 case Stage1ZirInstIdCtz:
142 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCtz *>(inst));
143 case Stage1ZirInstIdBswap:
144 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBswap *>(inst));
145 case Stage1ZirInstIdBitReverse:
146 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBitReverse *>(inst));
147 case Stage1ZirInstIdSwitchBr:
148 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSwitchBr *>(inst));
149 case Stage1ZirInstIdSwitchVar:
150 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSwitchVar *>(inst));
151 case Stage1ZirInstIdSwitchElseVar:
152 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSwitchElseVar *>(inst));
153 case Stage1ZirInstIdSwitchTarget:
154 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSwitchTarget *>(inst));
155 case Stage1ZirInstIdImport:
156 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstImport *>(inst));
157 case Stage1ZirInstIdRef:
158 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstRef *>(inst));
159 case Stage1ZirInstIdCompileErr:
160 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCompileErr *>(inst));
161 case Stage1ZirInstIdCompileLog:
162 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCompileLog *>(inst));
163 case Stage1ZirInstIdErrName:
164 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstErrName *>(inst));
165 case Stage1ZirInstIdCImport:
166 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCImport *>(inst));
167 case Stage1ZirInstIdCInclude:
168 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCInclude *>(inst));
169 case Stage1ZirInstIdCDefine:
170 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCDefine *>(inst));
171 case Stage1ZirInstIdCUndef:
172 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCUndef *>(inst));
173 case Stage1ZirInstIdEmbedFile:
174 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstEmbedFile *>(inst));
175 case Stage1ZirInstIdCmpxchg:
176 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCmpxchg *>(inst));
177 case Stage1ZirInstIdFence:
178 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFence *>(inst));
179 case Stage1ZirInstIdReduce:
180 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstReduce *>(inst));
181 case Stage1ZirInstIdTruncate:
182 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTruncate *>(inst));
183 case Stage1ZirInstIdIntCast:
184 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstIntCast *>(inst));
185 case Stage1ZirInstIdFloatCast:
186 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFloatCast *>(inst));
187 case Stage1ZirInstIdErrSetCast:
188 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstErrSetCast *>(inst));
189 case Stage1ZirInstIdIntToFloat:
190 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstIntToFloat *>(inst));
191 case Stage1ZirInstIdFloatToInt:
192 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFloatToInt *>(inst));
193 case Stage1ZirInstIdBoolToInt:
194 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBoolToInt *>(inst));
195 case Stage1ZirInstIdVectorType:
196 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstVectorType *>(inst));
197 case Stage1ZirInstIdShuffleVector:
198 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstShuffleVector *>(inst));
199 case Stage1ZirInstIdSplat:
200 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSplat *>(inst));
201 case Stage1ZirInstIdBoolNot:
202 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBoolNot *>(inst));
203 case Stage1ZirInstIdMemset:
204 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstMemset *>(inst));
205 case Stage1ZirInstIdMemcpy:
206 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstMemcpy *>(inst));
207 case Stage1ZirInstIdSlice:
208 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSlice *>(inst));
209 case Stage1ZirInstIdBreakpoint:
210 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBreakpoint *>(inst));
211 case Stage1ZirInstIdReturnAddress:
212 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstReturnAddress *>(inst));
213 case Stage1ZirInstIdFrameAddress:
214 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFrameAddress *>(inst));
215 case Stage1ZirInstIdFrameHandle:
216 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFrameHandle *>(inst));
217 case Stage1ZirInstIdFrameType:
218 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFrameType *>(inst));
219 case Stage1ZirInstIdFrameSize:
220 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFrameSize *>(inst));
221 case Stage1ZirInstIdAlignOf:
222 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAlignOf *>(inst));
223 case Stage1ZirInstIdOverflowOp:
224 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstOverflowOp *>(inst));
225 case Stage1ZirInstIdTestErr:
226 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTestErr *>(inst));
227 case Stage1ZirInstIdUnwrapErrCode:
228 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUnwrapErrCode *>(inst));
229 case Stage1ZirInstIdUnwrapErrPayload:
230 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUnwrapErrPayload *>(inst));
231 case Stage1ZirInstIdFnProto:
232 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFnProto *>(inst));
233 case Stage1ZirInstIdTestComptime:
234 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTestComptime *>(inst));
235 case Stage1ZirInstIdPtrCast:
236 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPtrCast *>(inst));
237 case Stage1ZirInstIdBitCast:
238 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBitCast *>(inst));
239 case Stage1ZirInstIdPtrToInt:
240 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPtrToInt *>(inst));
241 case Stage1ZirInstIdIntToPtr:
242 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstIntToPtr *>(inst));
243 case Stage1ZirInstIdIntToEnum:
244 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstIntToEnum *>(inst));
245 case Stage1ZirInstIdIntToErr:
246 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstIntToErr *>(inst));
247 case Stage1ZirInstIdErrToInt:
248 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstErrToInt *>(inst));
249 case Stage1ZirInstIdCheckSwitchProngsUnderNo:
250 case Stage1ZirInstIdCheckSwitchProngsUnderYes:
251 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCheckSwitchProngs *>(inst));
252 case Stage1ZirInstIdCheckStatementIsVoid:
253 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCheckStatementIsVoid *>(inst));
254 case Stage1ZirInstIdTypeName:
255 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTypeName *>(inst));
256 case Stage1ZirInstIdTagName:
257 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTagName *>(inst));
258 case Stage1ZirInstIdPtrType:
259 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPtrType *>(inst));
260 case Stage1ZirInstIdPtrTypeSimple:
261 case Stage1ZirInstIdPtrTypeSimpleConst:
262 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPtrTypeSimple *>(inst));
263 case Stage1ZirInstIdDeclRef:
264 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstDeclRef *>(inst));
265 case Stage1ZirInstIdPanic:
266 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstPanic *>(inst));
267 case Stage1ZirInstIdFieldParentPtr:
268 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFieldParentPtr *>(inst));
269 case Stage1ZirInstIdOffsetOf:
270 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstOffsetOf *>(inst));
271 case Stage1ZirInstIdBitOffsetOf:
272 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstBitOffsetOf *>(inst));
273 case Stage1ZirInstIdTypeInfo:
274 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstTypeInfo *>(inst));
275 case Stage1ZirInstIdType:
276 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstType *>(inst));
277 case Stage1ZirInstIdHasField:
278 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstHasField *>(inst));
279 case Stage1ZirInstIdSetEvalBranchQuota:
280 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSetEvalBranchQuota *>(inst));
281 case Stage1ZirInstIdAlignCast:
282 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAlignCast *>(inst));
283 case Stage1ZirInstIdImplicitCast:
284 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstImplicitCast *>(inst));
285 case Stage1ZirInstIdResolveResult:
286 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstResolveResult *>(inst));
287 case Stage1ZirInstIdResetResult:
288 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstResetResult *>(inst));
289 case Stage1ZirInstIdSetAlignStack:
290 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSetAlignStack *>(inst));
291 case Stage1ZirInstIdArgTypeAllowVarFalse:
292 case Stage1ZirInstIdArgTypeAllowVarTrue:
293 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstArgType *>(inst));
294 case Stage1ZirInstIdExport:
295 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstExport *>(inst));
296 case Stage1ZirInstIdExtern:
297 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstExtern *>(inst));
298 case Stage1ZirInstIdErrorReturnTrace:
299 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstErrorReturnTrace *>(inst));
300 case Stage1ZirInstIdErrorUnion:
301 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstErrorUnion *>(inst));
302 case Stage1ZirInstIdAtomicRmw:
303 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAtomicRmw *>(inst));
304 case Stage1ZirInstIdSaveErrRetAddr:
305 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSaveErrRetAddr *>(inst));
306 case Stage1ZirInstIdAddImplicitReturnType:
307 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAddImplicitReturnType *>(inst));
308 case Stage1ZirInstIdFloatOp:
309 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstFloatOp *>(inst));
310 case Stage1ZirInstIdMulAdd:
311 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstMulAdd *>(inst));
312 case Stage1ZirInstIdAtomicLoad:
313 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAtomicLoad *>(inst));
314 case Stage1ZirInstIdAtomicStore:
315 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAtomicStore *>(inst));
316 case Stage1ZirInstIdEnumToInt:
317 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstEnumToInt *>(inst));
318 case Stage1ZirInstIdCheckRuntimeScope:
319 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCheckRuntimeScope *>(inst));
320 case Stage1ZirInstIdHasDecl:
321 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstHasDecl *>(inst));
322 case Stage1ZirInstIdUndeclaredIdent:
323 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUndeclaredIdent *>(inst));
324 case Stage1ZirInstIdAlloca:
325 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAlloca *>(inst));
326 case Stage1ZirInstIdEndExpr:
327 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstEndExpr *>(inst));
328 case Stage1ZirInstIdUnionInitNamedField:
329 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstUnionInitNamedField *>(inst));
330 case Stage1ZirInstIdSuspendBegin:
331 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSuspendBegin *>(inst));
332 case Stage1ZirInstIdSuspendFinish:
333 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSuspendFinish *>(inst));
334 case Stage1ZirInstIdResume:
335 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstResume *>(inst));
336 case Stage1ZirInstIdAwait:
337 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstAwait *>(inst));
338 case Stage1ZirInstIdSpillBegin:
339 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSpillBegin *>(inst));
340 case Stage1ZirInstIdSpillEnd:
341 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSpillEnd *>(inst));
342 case Stage1ZirInstIdCallArgs:
343 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstCallArgs *>(inst));
344 case Stage1ZirInstIdWasmMemorySize:
345 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstWasmMemorySize *>(inst));
346 case Stage1ZirInstIdWasmMemoryGrow:
347 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstWasmMemoryGrow *>(inst));
348 case Stage1ZirInstIdSrc:
349 return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSrc *>(inst));
350350 }
351351 zig_unreachable();
352352}
......@@ -368,7 +368,7 @@ bool ir_should_inline(Stage1Zir *exec, Scope *scope) {
368368 return false;
369369}
370370
371static void ir_instruction_append(Stage1ZirBasicBlock *basic_block, IrInstSrc *instruction) {
371static void ir_instruction_append(Stage1ZirBasicBlock *basic_block, Stage1ZirInst *instruction) {
372372 assert(basic_block);
373373 assert(instruction);
374374 basic_block->instruction_list.append(instruction);
......@@ -384,11 +384,11 @@ static void ir_ref_bb(Stage1ZirBasicBlock *bb) {
384384 bb->ref_count += 1;
385385}
386386
387static void ir_ref_instruction(IrInstSrc *instruction, Stage1ZirBasicBlock *cur_bb) {
388 assert(instruction->id != IrInstSrcIdInvalid);
387static void ir_ref_instruction(Stage1ZirInst *instruction, Stage1ZirBasicBlock *cur_bb) {
388 assert(instruction->id != Stage1ZirInstIdInvalid);
389389 instruction->ref_count += 1;
390390 if (instruction->owner_bb != cur_bb && !instr_is_unreachable(instruction)
391 && instruction->id != IrInstSrcIdConst)
391 && instruction->id != Stage1ZirInstIdConst)
392392 {
393393 ir_ref_bb(instruction->owner_bb);
394394 }
......@@ -403,536 +403,536 @@ static Stage1ZirBasicBlock *ir_create_basic_block(Stage1AstGen *ag, Scope *scope
403403 return result;
404404}
405405
406static constexpr IrInstSrcId ir_inst_id(IrInstSrcDeclVar *) {
407 return IrInstSrcIdDeclVar;
406static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstDeclVar *) {
407 return Stage1ZirInstIdDeclVar;
408408}
409409
410static constexpr IrInstSrcId ir_inst_id(IrInstSrcBr *) {
411 return IrInstSrcIdBr;
410static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBr *) {
411 return Stage1ZirInstIdBr;
412412}
413413
414static constexpr IrInstSrcId ir_inst_id(IrInstSrcCondBr *) {
415 return IrInstSrcIdCondBr;
414static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCondBr *) {
415 return Stage1ZirInstIdCondBr;
416416}
417417
418static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchBr *) {
419 return IrInstSrcIdSwitchBr;
418static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchBr *) {
419 return Stage1ZirInstIdSwitchBr;
420420}
421421
422static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchVar *) {
423 return IrInstSrcIdSwitchVar;
422static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchVar *) {
423 return Stage1ZirInstIdSwitchVar;
424424}
425425
426static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchElseVar *) {
427 return IrInstSrcIdSwitchElseVar;
426static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchElseVar *) {
427 return Stage1ZirInstIdSwitchElseVar;
428428}
429429
430static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchTarget *) {
431 return IrInstSrcIdSwitchTarget;
430static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchTarget *) {
431 return Stage1ZirInstIdSwitchTarget;
432432}
433433
434static constexpr IrInstSrcId ir_inst_id(IrInstSrcPhi *) {
435 return IrInstSrcIdPhi;
434static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPhi *) {
435 return Stage1ZirInstIdPhi;
436436}
437437
438static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnOp *) {
439 return IrInstSrcIdUnOp;
438static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnOp *) {
439 return Stage1ZirInstIdUnOp;
440440}
441441
442static constexpr IrInstSrcId ir_inst_id(IrInstSrcBinOp *) {
443 return IrInstSrcIdBinOp;
442static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBinOp *) {
443 return Stage1ZirInstIdBinOp;
444444}
445445
446static constexpr IrInstSrcId ir_inst_id(IrInstSrcMergeErrSets *) {
447 return IrInstSrcIdMergeErrSets;
446static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMergeErrSets *) {
447 return Stage1ZirInstIdMergeErrSets;
448448}
449449
450static constexpr IrInstSrcId ir_inst_id(IrInstSrcLoadPtr *) {
451 return IrInstSrcIdLoadPtr;
450static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstLoadPtr *) {
451 return Stage1ZirInstIdLoadPtr;
452452}
453453
454static constexpr IrInstSrcId ir_inst_id(IrInstSrcStorePtr *) {
455 return IrInstSrcIdStorePtr;
454static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstStorePtr *) {
455 return Stage1ZirInstIdStorePtr;
456456}
457457
458static constexpr IrInstSrcId ir_inst_id(IrInstSrcFieldPtr *) {
459 return IrInstSrcIdFieldPtr;
458static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFieldPtr *) {
459 return Stage1ZirInstIdFieldPtr;
460460}
461461
462static constexpr IrInstSrcId ir_inst_id(IrInstSrcElemPtr *) {
463 return IrInstSrcIdElemPtr;
462static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstElemPtr *) {
463 return Stage1ZirInstIdElemPtr;
464464}
465465
466static constexpr IrInstSrcId ir_inst_id(IrInstSrcVarPtr *) {
467 return IrInstSrcIdVarPtr;
466static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstVarPtr *) {
467 return Stage1ZirInstIdVarPtr;
468468}
469469
470static constexpr IrInstSrcId ir_inst_id(IrInstSrcCall *) {
471 return IrInstSrcIdCall;
470static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCall *) {
471 return Stage1ZirInstIdCall;
472472}
473473
474static constexpr IrInstSrcId ir_inst_id(IrInstSrcCallArgs *) {
475 return IrInstSrcIdCallArgs;
474static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCallArgs *) {
475 return Stage1ZirInstIdCallArgs;
476476}
477477
478static constexpr IrInstSrcId ir_inst_id(IrInstSrcCallExtra *) {
479 return IrInstSrcIdCallExtra;
478static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCallExtra *) {
479 return Stage1ZirInstIdCallExtra;
480480}
481481
482static constexpr IrInstSrcId ir_inst_id(IrInstSrcAsyncCallExtra *) {
483 return IrInstSrcIdAsyncCallExtra;
482static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAsyncCallExtra *) {
483 return Stage1ZirInstIdAsyncCallExtra;
484484}
485485
486static constexpr IrInstSrcId ir_inst_id(IrInstSrcConst *) {
487 return IrInstSrcIdConst;
486static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstConst *) {
487 return Stage1ZirInstIdConst;
488488}
489489
490static constexpr IrInstSrcId ir_inst_id(IrInstSrcReturn *) {
491 return IrInstSrcIdReturn;
490static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstReturn *) {
491 return Stage1ZirInstIdReturn;
492492}
493493
494static constexpr IrInstSrcId ir_inst_id(IrInstSrcContainerInitList *) {
495 return IrInstSrcIdContainerInitList;
494static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstContainerInitList *) {
495 return Stage1ZirInstIdContainerInitList;
496496}
497497
498static constexpr IrInstSrcId ir_inst_id(IrInstSrcContainerInitFields *) {
499 return IrInstSrcIdContainerInitFields;
498static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstContainerInitFields *) {
499 return Stage1ZirInstIdContainerInitFields;
500500}
501501
502static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnreachable *) {
503 return IrInstSrcIdUnreachable;
502static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnreachable *) {
503 return Stage1ZirInstIdUnreachable;
504504}
505505
506static constexpr IrInstSrcId ir_inst_id(IrInstSrcTypeOf *) {
507 return IrInstSrcIdTypeOf;
506static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTypeOf *) {
507 return Stage1ZirInstIdTypeOf;
508508}
509509
510static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetCold *) {
511 return IrInstSrcIdSetCold;
510static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetCold *) {
511 return Stage1ZirInstIdSetCold;
512512}
513513
514static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetRuntimeSafety *) {
515 return IrInstSrcIdSetRuntimeSafety;
514static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetRuntimeSafety *) {
515 return Stage1ZirInstIdSetRuntimeSafety;
516516}
517517
518static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetFloatMode *) {
519 return IrInstSrcIdSetFloatMode;
518static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetFloatMode *) {
519 return Stage1ZirInstIdSetFloatMode;
520520}
521521
522static constexpr IrInstSrcId ir_inst_id(IrInstSrcArrayType *) {
523 return IrInstSrcIdArrayType;
522static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstArrayType *) {
523 return Stage1ZirInstIdArrayType;
524524}
525525
526static constexpr IrInstSrcId ir_inst_id(IrInstSrcAnyFrameType *) {
527 return IrInstSrcIdAnyFrameType;
526static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAnyFrameType *) {
527 return Stage1ZirInstIdAnyFrameType;
528528}
529529
530static constexpr IrInstSrcId ir_inst_id(IrInstSrcSliceType *) {
531 return IrInstSrcIdSliceType;
530static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSliceType *) {
531 return Stage1ZirInstIdSliceType;
532532}
533533
534static constexpr IrInstSrcId ir_inst_id(IrInstSrcAsm *) {
535 return IrInstSrcIdAsm;
534static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAsm *) {
535 return Stage1ZirInstIdAsm;
536536}
537537
538static constexpr IrInstSrcId ir_inst_id(IrInstSrcSizeOf *) {
539 return IrInstSrcIdSizeOf;
538static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSizeOf *) {
539 return Stage1ZirInstIdSizeOf;
540540}
541541
542static constexpr IrInstSrcId ir_inst_id(IrInstSrcTestNonNull *) {
543 return IrInstSrcIdTestNonNull;
542static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTestNonNull *) {
543 return Stage1ZirInstIdTestNonNull;
544544}
545545
546static constexpr IrInstSrcId ir_inst_id(IrInstSrcOptionalUnwrapPtr *) {
547 return IrInstSrcIdOptionalUnwrapPtr;
546static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstOptionalUnwrapPtr *) {
547 return Stage1ZirInstIdOptionalUnwrapPtr;
548548}
549549
550static constexpr IrInstSrcId ir_inst_id(IrInstSrcClz *) {
551 return IrInstSrcIdClz;
550static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstClz *) {
551 return Stage1ZirInstIdClz;
552552}
553553
554static constexpr IrInstSrcId ir_inst_id(IrInstSrcCtz *) {
555 return IrInstSrcIdCtz;
554static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCtz *) {
555 return Stage1ZirInstIdCtz;
556556}
557557
558static constexpr IrInstSrcId ir_inst_id(IrInstSrcPopCount *) {
559 return IrInstSrcIdPopCount;
558static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPopCount *) {
559 return Stage1ZirInstIdPopCount;
560560}
561561
562static constexpr IrInstSrcId ir_inst_id(IrInstSrcBswap *) {
563 return IrInstSrcIdBswap;
562static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBswap *) {
563 return Stage1ZirInstIdBswap;
564564}
565565
566static constexpr IrInstSrcId ir_inst_id(IrInstSrcBitReverse *) {
567 return IrInstSrcIdBitReverse;
566static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBitReverse *) {
567 return Stage1ZirInstIdBitReverse;
568568}
569569
570static constexpr IrInstSrcId ir_inst_id(IrInstSrcImport *) {
571 return IrInstSrcIdImport;
570static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstImport *) {
571 return Stage1ZirInstIdImport;
572572}
573573
574static constexpr IrInstSrcId ir_inst_id(IrInstSrcCImport *) {
575 return IrInstSrcIdCImport;
574static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCImport *) {
575 return Stage1ZirInstIdCImport;
576576}
577577
578static constexpr IrInstSrcId ir_inst_id(IrInstSrcCInclude *) {
579 return IrInstSrcIdCInclude;
578static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCInclude *) {
579 return Stage1ZirInstIdCInclude;
580580}
581581
582static constexpr IrInstSrcId ir_inst_id(IrInstSrcCDefine *) {
583 return IrInstSrcIdCDefine;
582static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCDefine *) {
583 return Stage1ZirInstIdCDefine;
584584}
585585
586static constexpr IrInstSrcId ir_inst_id(IrInstSrcCUndef *) {
587 return IrInstSrcIdCUndef;
586static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCUndef *) {
587 return Stage1ZirInstIdCUndef;
588588}
589589
590static constexpr IrInstSrcId ir_inst_id(IrInstSrcRef *) {
591 return IrInstSrcIdRef;
590static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstRef *) {
591 return Stage1ZirInstIdRef;
592592}
593593
594static constexpr IrInstSrcId ir_inst_id(IrInstSrcCompileErr *) {
595 return IrInstSrcIdCompileErr;
594static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCompileErr *) {
595 return Stage1ZirInstIdCompileErr;
596596}
597597
598static constexpr IrInstSrcId ir_inst_id(IrInstSrcCompileLog *) {
599 return IrInstSrcIdCompileLog;
598static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCompileLog *) {
599 return Stage1ZirInstIdCompileLog;
600600}
601601
602static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrName *) {
603 return IrInstSrcIdErrName;
602static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrName *) {
603 return Stage1ZirInstIdErrName;
604604}
605605
606static constexpr IrInstSrcId ir_inst_id(IrInstSrcEmbedFile *) {
607 return IrInstSrcIdEmbedFile;
606static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstEmbedFile *) {
607 return Stage1ZirInstIdEmbedFile;
608608}
609609
610static constexpr IrInstSrcId ir_inst_id(IrInstSrcCmpxchg *) {
611 return IrInstSrcIdCmpxchg;
610static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCmpxchg *) {
611 return Stage1ZirInstIdCmpxchg;
612612}
613613
614static constexpr IrInstSrcId ir_inst_id(IrInstSrcFence *) {
615 return IrInstSrcIdFence;
614static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFence *) {
615 return Stage1ZirInstIdFence;
616616}
617617
618static constexpr IrInstSrcId ir_inst_id(IrInstSrcReduce *) {
619 return IrInstSrcIdReduce;
618static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstReduce *) {
619 return Stage1ZirInstIdReduce;
620620}
621621
622static constexpr IrInstSrcId ir_inst_id(IrInstSrcTruncate *) {
623 return IrInstSrcIdTruncate;
622static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTruncate *) {
623 return Stage1ZirInstIdTruncate;
624624}
625625
626static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntCast *) {
627 return IrInstSrcIdIntCast;
626static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntCast *) {
627 return Stage1ZirInstIdIntCast;
628628}
629629
630static constexpr IrInstSrcId ir_inst_id(IrInstSrcFloatCast *) {
631 return IrInstSrcIdFloatCast;
630static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFloatCast *) {
631 return Stage1ZirInstIdFloatCast;
632632}
633633
634static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToFloat *) {
635 return IrInstSrcIdIntToFloat;
634static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToFloat *) {
635 return Stage1ZirInstIdIntToFloat;
636636}
637637
638static constexpr IrInstSrcId ir_inst_id(IrInstSrcFloatToInt *) {
639 return IrInstSrcIdFloatToInt;
638static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFloatToInt *) {
639 return Stage1ZirInstIdFloatToInt;
640640}
641641
642static constexpr IrInstSrcId ir_inst_id(IrInstSrcBoolToInt *) {
643 return IrInstSrcIdBoolToInt;
642static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBoolToInt *) {
643 return Stage1ZirInstIdBoolToInt;
644644}
645645
646static constexpr IrInstSrcId ir_inst_id(IrInstSrcVectorType *) {
647 return IrInstSrcIdVectorType;
646static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstVectorType *) {
647 return Stage1ZirInstIdVectorType;
648648}
649649
650static constexpr IrInstSrcId ir_inst_id(IrInstSrcShuffleVector *) {
651 return IrInstSrcIdShuffleVector;
650static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstShuffleVector *) {
651 return Stage1ZirInstIdShuffleVector;
652652}
653653
654static constexpr IrInstSrcId ir_inst_id(IrInstSrcSplat *) {
655 return IrInstSrcIdSplat;
654static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSplat *) {
655 return Stage1ZirInstIdSplat;
656656}
657657
658static constexpr IrInstSrcId ir_inst_id(IrInstSrcBoolNot *) {
659 return IrInstSrcIdBoolNot;
658static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBoolNot *) {
659 return Stage1ZirInstIdBoolNot;
660660}
661661
662static constexpr IrInstSrcId ir_inst_id(IrInstSrcMemset *) {
663 return IrInstSrcIdMemset;
662static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMemset *) {
663 return Stage1ZirInstIdMemset;
664664}
665665
666static constexpr IrInstSrcId ir_inst_id(IrInstSrcMemcpy *) {
667 return IrInstSrcIdMemcpy;
666static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMemcpy *) {
667 return Stage1ZirInstIdMemcpy;
668668}
669669
670static constexpr IrInstSrcId ir_inst_id(IrInstSrcSlice *) {
671 return IrInstSrcIdSlice;
670static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSlice *) {
671 return Stage1ZirInstIdSlice;
672672}
673673
674static constexpr IrInstSrcId ir_inst_id(IrInstSrcBreakpoint *) {
675 return IrInstSrcIdBreakpoint;
674static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBreakpoint *) {
675 return Stage1ZirInstIdBreakpoint;
676676}
677677
678static constexpr IrInstSrcId ir_inst_id(IrInstSrcReturnAddress *) {
679 return IrInstSrcIdReturnAddress;
678static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstReturnAddress *) {
679 return Stage1ZirInstIdReturnAddress;
680680}
681681
682static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameAddress *) {
683 return IrInstSrcIdFrameAddress;
682static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameAddress *) {
683 return Stage1ZirInstIdFrameAddress;
684684}
685685
686static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameHandle *) {
687 return IrInstSrcIdFrameHandle;
686static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameHandle *) {
687 return Stage1ZirInstIdFrameHandle;
688688}
689689
690static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameType *) {
691 return IrInstSrcIdFrameType;
690static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameType *) {
691 return Stage1ZirInstIdFrameType;
692692}
693693
694static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameSize *) {
695 return IrInstSrcIdFrameSize;
694static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameSize *) {
695 return Stage1ZirInstIdFrameSize;
696696}
697697
698static constexpr IrInstSrcId ir_inst_id(IrInstSrcAlignOf *) {
699 return IrInstSrcIdAlignOf;
698static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAlignOf *) {
699 return Stage1ZirInstIdAlignOf;
700700}
701701
702static constexpr IrInstSrcId ir_inst_id(IrInstSrcOverflowOp *) {
703 return IrInstSrcIdOverflowOp;
702static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstOverflowOp *) {
703 return Stage1ZirInstIdOverflowOp;
704704}
705705
706static constexpr IrInstSrcId ir_inst_id(IrInstSrcTestErr *) {
707 return IrInstSrcIdTestErr;
706static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTestErr *) {
707 return Stage1ZirInstIdTestErr;
708708}
709709
710static constexpr IrInstSrcId ir_inst_id(IrInstSrcMulAdd *) {
711 return IrInstSrcIdMulAdd;
710static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMulAdd *) {
711 return Stage1ZirInstIdMulAdd;
712712}
713713
714static constexpr IrInstSrcId ir_inst_id(IrInstSrcFloatOp *) {
715 return IrInstSrcIdFloatOp;
714static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFloatOp *) {
715 return Stage1ZirInstIdFloatOp;
716716}
717717
718static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnwrapErrCode *) {
719 return IrInstSrcIdUnwrapErrCode;
718static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnwrapErrCode *) {
719 return Stage1ZirInstIdUnwrapErrCode;
720720}
721721
722static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnwrapErrPayload *) {
723 return IrInstSrcIdUnwrapErrPayload;
722static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnwrapErrPayload *) {
723 return Stage1ZirInstIdUnwrapErrPayload;
724724}
725725
726static constexpr IrInstSrcId ir_inst_id(IrInstSrcFnProto *) {
727 return IrInstSrcIdFnProto;
726static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFnProto *) {
727 return Stage1ZirInstIdFnProto;
728728}
729729
730static constexpr IrInstSrcId ir_inst_id(IrInstSrcTestComptime *) {
731 return IrInstSrcIdTestComptime;
730static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTestComptime *) {
731 return Stage1ZirInstIdTestComptime;
732732}
733733
734static constexpr IrInstSrcId ir_inst_id(IrInstSrcPtrCast *) {
735 return IrInstSrcIdPtrCast;
734static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPtrCast *) {
735 return Stage1ZirInstIdPtrCast;
736736}
737737
738static constexpr IrInstSrcId ir_inst_id(IrInstSrcBitCast *) {
739 return IrInstSrcIdBitCast;
738static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBitCast *) {
739 return Stage1ZirInstIdBitCast;
740740}
741741
742static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToPtr *) {
743 return IrInstSrcIdIntToPtr;
742static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToPtr *) {
743 return Stage1ZirInstIdIntToPtr;
744744}
745745
746static constexpr IrInstSrcId ir_inst_id(IrInstSrcPtrToInt *) {
747 return IrInstSrcIdPtrToInt;
746static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPtrToInt *) {
747 return Stage1ZirInstIdPtrToInt;
748748}
749749
750static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToEnum *) {
751 return IrInstSrcIdIntToEnum;
750static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToEnum *) {
751 return Stage1ZirInstIdIntToEnum;
752752}
753753
754static constexpr IrInstSrcId ir_inst_id(IrInstSrcEnumToInt *) {
755 return IrInstSrcIdEnumToInt;
754static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstEnumToInt *) {
755 return Stage1ZirInstIdEnumToInt;
756756}
757757
758static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToErr *) {
759 return IrInstSrcIdIntToErr;
758static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToErr *) {
759 return Stage1ZirInstIdIntToErr;
760760}
761761
762static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrToInt *) {
763 return IrInstSrcIdErrToInt;
762static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrToInt *) {
763 return Stage1ZirInstIdErrToInt;
764764}
765765
766static constexpr IrInstSrcId ir_inst_id(IrInstSrcCheckStatementIsVoid *) {
767 return IrInstSrcIdCheckStatementIsVoid;
766static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCheckStatementIsVoid *) {
767 return Stage1ZirInstIdCheckStatementIsVoid;
768768}
769769
770static constexpr IrInstSrcId ir_inst_id(IrInstSrcTypeName *) {
771 return IrInstSrcIdTypeName;
770static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTypeName *) {
771 return Stage1ZirInstIdTypeName;
772772}
773773
774static constexpr IrInstSrcId ir_inst_id(IrInstSrcDeclRef *) {
775 return IrInstSrcIdDeclRef;
774static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstDeclRef *) {
775 return Stage1ZirInstIdDeclRef;
776776}
777777
778static constexpr IrInstSrcId ir_inst_id(IrInstSrcPanic *) {
779 return IrInstSrcIdPanic;
778static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPanic *) {
779 return Stage1ZirInstIdPanic;
780780}
781781
782static constexpr IrInstSrcId ir_inst_id(IrInstSrcTagName *) {
783 return IrInstSrcIdTagName;
782static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTagName *) {
783 return Stage1ZirInstIdTagName;
784784}
785785
786static constexpr IrInstSrcId ir_inst_id(IrInstSrcFieldParentPtr *) {
787 return IrInstSrcIdFieldParentPtr;
786static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFieldParentPtr *) {
787 return Stage1ZirInstIdFieldParentPtr;
788788}
789789
790static constexpr IrInstSrcId ir_inst_id(IrInstSrcOffsetOf *) {
791 return IrInstSrcIdOffsetOf;
790static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstOffsetOf *) {
791 return Stage1ZirInstIdOffsetOf;
792792}
793793
794static constexpr IrInstSrcId ir_inst_id(IrInstSrcBitOffsetOf *) {
795 return IrInstSrcIdBitOffsetOf;
794static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBitOffsetOf *) {
795 return Stage1ZirInstIdBitOffsetOf;
796796}
797797
798static constexpr IrInstSrcId ir_inst_id(IrInstSrcTypeInfo *) {
799 return IrInstSrcIdTypeInfo;
798static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTypeInfo *) {
799 return Stage1ZirInstIdTypeInfo;
800800}
801801
802static constexpr IrInstSrcId ir_inst_id(IrInstSrcType *) {
803 return IrInstSrcIdType;
802static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstType *) {
803 return Stage1ZirInstIdType;
804804}
805805
806static constexpr IrInstSrcId ir_inst_id(IrInstSrcHasField *) {
807 return IrInstSrcIdHasField;
806static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstHasField *) {
807 return Stage1ZirInstIdHasField;
808808}
809809
810static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetEvalBranchQuota *) {
811 return IrInstSrcIdSetEvalBranchQuota;
810static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetEvalBranchQuota *) {
811 return Stage1ZirInstIdSetEvalBranchQuota;
812812}
813813
814static constexpr IrInstSrcId ir_inst_id(IrInstSrcPtrType *) {
815 return IrInstSrcIdPtrType;
814static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPtrType *) {
815 return Stage1ZirInstIdPtrType;
816816}
817817
818static constexpr IrInstSrcId ir_inst_id(IrInstSrcAlignCast *) {
819 return IrInstSrcIdAlignCast;
818static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAlignCast *) {
819 return Stage1ZirInstIdAlignCast;
820820}
821821
822static constexpr IrInstSrcId ir_inst_id(IrInstSrcImplicitCast *) {
823 return IrInstSrcIdImplicitCast;
822static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstImplicitCast *) {
823 return Stage1ZirInstIdImplicitCast;
824824}
825825
826static constexpr IrInstSrcId ir_inst_id(IrInstSrcResolveResult *) {
827 return IrInstSrcIdResolveResult;
826static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstResolveResult *) {
827 return Stage1ZirInstIdResolveResult;
828828}
829829
830static constexpr IrInstSrcId ir_inst_id(IrInstSrcResetResult *) {
831 return IrInstSrcIdResetResult;
830static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstResetResult *) {
831 return Stage1ZirInstIdResetResult;
832832}
833833
834static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetAlignStack *) {
835 return IrInstSrcIdSetAlignStack;
834static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetAlignStack *) {
835 return Stage1ZirInstIdSetAlignStack;
836836}
837837
838static constexpr IrInstSrcId ir_inst_id(IrInstSrcExport *) {
839 return IrInstSrcIdExport;
838static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstExport *) {
839 return Stage1ZirInstIdExport;
840840}
841841
842static constexpr IrInstSrcId ir_inst_id(IrInstSrcExtern *) {
843 return IrInstSrcIdExtern;
842static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstExtern *) {
843 return Stage1ZirInstIdExtern;
844844}
845845
846static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrorReturnTrace *) {
847 return IrInstSrcIdErrorReturnTrace;
846static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrorReturnTrace *) {
847 return Stage1ZirInstIdErrorReturnTrace;
848848}
849849
850static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrorUnion *) {
851 return IrInstSrcIdErrorUnion;
850static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrorUnion *) {
851 return Stage1ZirInstIdErrorUnion;
852852}
853853
854static constexpr IrInstSrcId ir_inst_id(IrInstSrcAtomicRmw *) {
855 return IrInstSrcIdAtomicRmw;
854static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAtomicRmw *) {
855 return Stage1ZirInstIdAtomicRmw;
856856}
857857
858static constexpr IrInstSrcId ir_inst_id(IrInstSrcAtomicLoad *) {
859 return IrInstSrcIdAtomicLoad;
858static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAtomicLoad *) {
859 return Stage1ZirInstIdAtomicLoad;
860860}
861861
862static constexpr IrInstSrcId ir_inst_id(IrInstSrcAtomicStore *) {
863 return IrInstSrcIdAtomicStore;
862static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAtomicStore *) {
863 return Stage1ZirInstIdAtomicStore;
864864}
865865
866static constexpr IrInstSrcId ir_inst_id(IrInstSrcSaveErrRetAddr *) {
867 return IrInstSrcIdSaveErrRetAddr;
866static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSaveErrRetAddr *) {
867 return Stage1ZirInstIdSaveErrRetAddr;
868868}
869869
870static constexpr IrInstSrcId ir_inst_id(IrInstSrcAddImplicitReturnType *) {
871 return IrInstSrcIdAddImplicitReturnType;
870static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAddImplicitReturnType *) {
871 return Stage1ZirInstIdAddImplicitReturnType;
872872}
873873
874static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrSetCast *) {
875 return IrInstSrcIdErrSetCast;
874static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrSetCast *) {
875 return Stage1ZirInstIdErrSetCast;
876876}
877877
878static constexpr IrInstSrcId ir_inst_id(IrInstSrcCheckRuntimeScope *) {
879 return IrInstSrcIdCheckRuntimeScope;
878static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCheckRuntimeScope *) {
879 return Stage1ZirInstIdCheckRuntimeScope;
880880}
881881
882static constexpr IrInstSrcId ir_inst_id(IrInstSrcHasDecl *) {
883 return IrInstSrcIdHasDecl;
882static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstHasDecl *) {
883 return Stage1ZirInstIdHasDecl;
884884}
885885
886static constexpr IrInstSrcId ir_inst_id(IrInstSrcUndeclaredIdent *) {
887 return IrInstSrcIdUndeclaredIdent;
886static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUndeclaredIdent *) {
887 return Stage1ZirInstIdUndeclaredIdent;
888888}
889889
890static constexpr IrInstSrcId ir_inst_id(IrInstSrcAlloca *) {
891 return IrInstSrcIdAlloca;
890static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAlloca *) {
891 return Stage1ZirInstIdAlloca;
892892}
893893
894static constexpr IrInstSrcId ir_inst_id(IrInstSrcEndExpr *) {
895 return IrInstSrcIdEndExpr;
894static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstEndExpr *) {
895 return Stage1ZirInstIdEndExpr;
896896}
897897
898static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnionInitNamedField *) {
899 return IrInstSrcIdUnionInitNamedField;
898static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnionInitNamedField *) {
899 return Stage1ZirInstIdUnionInitNamedField;
900900}
901901
902static constexpr IrInstSrcId ir_inst_id(IrInstSrcSuspendBegin *) {
903 return IrInstSrcIdSuspendBegin;
902static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSuspendBegin *) {
903 return Stage1ZirInstIdSuspendBegin;
904904}
905905
906static constexpr IrInstSrcId ir_inst_id(IrInstSrcSuspendFinish *) {
907 return IrInstSrcIdSuspendFinish;
906static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSuspendFinish *) {
907 return Stage1ZirInstIdSuspendFinish;
908908}
909909
910static constexpr IrInstSrcId ir_inst_id(IrInstSrcAwait *) {
911 return IrInstSrcIdAwait;
910static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAwait *) {
911 return Stage1ZirInstIdAwait;
912912}
913913
914static constexpr IrInstSrcId ir_inst_id(IrInstSrcResume *) {
915 return IrInstSrcIdResume;
914static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstResume *) {
915 return Stage1ZirInstIdResume;
916916}
917917
918static constexpr IrInstSrcId ir_inst_id(IrInstSrcSpillBegin *) {
919 return IrInstSrcIdSpillBegin;
918static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSpillBegin *) {
919 return Stage1ZirInstIdSpillBegin;
920920}
921921
922static constexpr IrInstSrcId ir_inst_id(IrInstSrcSpillEnd *) {
923 return IrInstSrcIdSpillEnd;
922static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSpillEnd *) {
923 return Stage1ZirInstIdSpillEnd;
924924}
925925
926static constexpr IrInstSrcId ir_inst_id(IrInstSrcWasmMemorySize *) {
927 return IrInstSrcIdWasmMemorySize;
926static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstWasmMemorySize *) {
927 return Stage1ZirInstIdWasmMemorySize;
928928}
929929
930static constexpr IrInstSrcId ir_inst_id(IrInstSrcWasmMemoryGrow *) {
931 return IrInstSrcIdWasmMemoryGrow;
930static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstWasmMemoryGrow *) {
931 return Stage1ZirInstIdWasmMemoryGrow;
932932}
933933
934static constexpr IrInstSrcId ir_inst_id(IrInstSrcSrc *) {
935 return IrInstSrcIdSrc;
934static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSrc *) {
935 return Stage1ZirInstIdSrc;
936936}
937937
938938template<typename T>
......@@ -953,10 +953,10 @@ static T *ir_build_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_n
953953 return special_instruction;
954954}
955955
956static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *condition,
957 Stage1ZirBasicBlock *then_block, Stage1ZirBasicBlock *else_block, IrInstSrc *is_comptime)
956static Stage1ZirInst *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *condition,
957 Stage1ZirBasicBlock *then_block, Stage1ZirBasicBlock *else_block, Stage1ZirInst *is_comptime)
958958{
959 IrInstSrcCondBr *inst = ir_build_instruction<IrInstSrcCondBr>(ag, scope, source_node);
959 Stage1ZirInstCondBr *inst = ir_build_instruction<Stage1ZirInstCondBr>(ag, scope, source_node);
960960 inst->condition = condition;
961961 inst->then_block = then_block;
962962 inst->else_block = else_block;
......@@ -970,8 +970,8 @@ static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *sour
970970 return &inst->base;
971971}
972972
973static IrInstSrc *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *operand) {
974 IrInstSrcReturn *inst = ir_build_instruction<IrInstSrcReturn>(ag, scope, source_node);
973static Stage1ZirInst *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *operand) {
974 Stage1ZirInstReturn *inst = ir_build_instruction<Stage1ZirInstReturn>(ag, scope, source_node);
975975 inst->operand = operand;
976976
977977 if (operand != nullptr) ir_ref_instruction(operand, ag->current_basic_block);
......@@ -979,23 +979,23 @@ static IrInstSrc *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *s
979979 return &inst->base;
980980}
981981
982static IrInstSrc *ir_build_const_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
983 IrInstSrcConst *const_instruction = ir_create_instruction<IrInstSrcConst>(ag, scope, source_node);
982static Stage1ZirInst *ir_build_const_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
983 Stage1ZirInstConst *const_instruction = ir_create_instruction<Stage1ZirInstConst>(ag, scope, source_node);
984984 ir_instruction_append(ag->current_basic_block, &const_instruction->base);
985985 const_instruction->value = ag->codegen->intern.for_void();
986986 return &const_instruction->base;
987987}
988988
989static IrInstSrc *ir_build_const_undefined(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
990 IrInstSrcConst *const_instruction = ir_create_instruction<IrInstSrcConst>(ag, scope, source_node);
989static Stage1ZirInst *ir_build_const_undefined(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
990 Stage1ZirInstConst *const_instruction = ir_create_instruction<Stage1ZirInstConst>(ag, scope, source_node);
991991 ir_instruction_append(ag->current_basic_block, &const_instruction->base);
992992 const_instruction->value = ag->codegen->intern.for_undefined();
993993 const_instruction->value->special = ConstValSpecialUndef;
994994 return &const_instruction->base;
995995}
996996
997static IrInstSrc *ir_build_const_uint(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) {
998 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);
997static Stage1ZirInst *ir_build_const_uint(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) {
998 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
999999 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
10001000 const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_int;
10011001 const_instruction->value->special = ConstValSpecialStatic;
......@@ -1003,10 +1003,10 @@ static IrInstSrc *ir_build_const_uint(Stage1AstGen *ag, Scope *scope, AstNode *s
10031003 return &const_instruction->base;
10041004}
10051005
1006static IrInstSrc *ir_build_const_bigint(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1006static Stage1ZirInst *ir_build_const_bigint(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
10071007 BigInt bigint)
10081008{
1009 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);
1009 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
10101010 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
10111011 const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_int;
10121012 const_instruction->value->special = ConstValSpecialStatic;
......@@ -1014,10 +1014,10 @@ static IrInstSrc *ir_build_const_bigint(Stage1AstGen *ag, Scope *scope, AstNode
10141014 return &const_instruction->base;
10151015}
10161016
1017static IrInstSrc *ir_build_const_bigfloat(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1017static Stage1ZirInst *ir_build_const_bigfloat(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
10181018 BigFloat bigfloat)
10191019{
1020 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);
1020 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
10211021 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
10221022 const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_float;
10231023 const_instruction->value->special = ConstValSpecialStatic;
......@@ -1025,15 +1025,15 @@ static IrInstSrc *ir_build_const_bigfloat(Stage1AstGen *ag, Scope *scope, AstNod
10251025 return &const_instruction->base;
10261026}
10271027
1028static IrInstSrc *ir_build_const_null(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
1029 IrInstSrcConst *const_instruction = ir_create_instruction<IrInstSrcConst>(ag, scope, source_node);
1028static Stage1ZirInst *ir_build_const_null(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
1029 Stage1ZirInstConst *const_instruction = ir_create_instruction<Stage1ZirInstConst>(ag, scope, source_node);
10301030 ir_instruction_append(ag->current_basic_block, &const_instruction->base);
10311031 const_instruction->value = ag->codegen->intern.for_null();
10321032 return &const_instruction->base;
10331033}
10341034
1035static IrInstSrc *ir_build_const_usize(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) {
1036 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);
1035static Stage1ZirInst *ir_build_const_usize(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) {
1036 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
10371037 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
10381038 const_instruction->value->type = ag->codegen->builtin_types.entry_usize;
10391039 const_instruction->value->special = ConstValSpecialStatic;
......@@ -1041,10 +1041,10 @@ static IrInstSrc *ir_build_const_usize(Stage1AstGen *ag, Scope *scope, AstNode *
10411041 return &const_instruction->base;
10421042}
10431043
1044static IrInstSrc *ir_create_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1044static Stage1ZirInst *ir_create_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
10451045 ZigType *type_entry)
10461046{
1047 IrInstSrcConst *const_instruction = ir_create_instruction<IrInstSrcConst>(ag, scope, source_node);
1047 Stage1ZirInstConst *const_instruction = ir_create_instruction<Stage1ZirInstConst>(ag, scope, source_node);
10481048 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
10491049 const_instruction->value->type = ag->codegen->builtin_types.entry_type;
10501050 const_instruction->value->special = ConstValSpecialStatic;
......@@ -1052,16 +1052,16 @@ static IrInstSrc *ir_create_const_type(Stage1AstGen *ag, Scope *scope, AstNode *
10521052 return &const_instruction->base;
10531053}
10541054
1055static IrInstSrc *ir_build_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1055static Stage1ZirInst *ir_build_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
10561056 ZigType *type_entry)
10571057{
1058 IrInstSrc *instruction = ir_create_const_type(ag, scope, source_node, type_entry);
1058 Stage1ZirInst *instruction = ir_create_const_type(ag, scope, source_node, type_entry);
10591059 ir_instruction_append(ag->current_basic_block, instruction);
10601060 return instruction;
10611061}
10621062
1063static IrInstSrc *ir_build_const_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigType *import) {
1064 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);
1063static Stage1ZirInst *ir_build_const_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigType *import) {
1064 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
10651065 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
10661066 const_instruction->value->type = ag->codegen->builtin_types.entry_type;
10671067 const_instruction->value->special = ConstValSpecialStatic;
......@@ -1069,8 +1069,8 @@ static IrInstSrc *ir_build_const_import(Stage1AstGen *ag, Scope *scope, AstNode
10691069 return &const_instruction->base;
10701070}
10711071
1072static IrInstSrc *ir_build_const_bool(Stage1AstGen *ag, Scope *scope, AstNode *source_node, bool value) {
1073 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);
1072static Stage1ZirInst *ir_build_const_bool(Stage1AstGen *ag, Scope *scope, AstNode *source_node, bool value) {
1073 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
10741074 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
10751075 const_instruction->value->type = ag->codegen->builtin_types.entry_bool;
10761076 const_instruction->value->special = ConstValSpecialStatic;
......@@ -1078,8 +1078,8 @@ static IrInstSrc *ir_build_const_bool(Stage1AstGen *ag, Scope *scope, AstNode *s
10781078 return &const_instruction->base;
10791079}
10801080
1081static IrInstSrc *ir_build_const_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) {
1082 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, source_node);
1081static Stage1ZirInst *ir_build_const_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) {
1082 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, source_node);
10831083 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
10841084 const_instruction->value->type = ag->codegen->builtin_types.entry_enum_literal;
10851085 const_instruction->value->special = ConstValSpecialStatic;
......@@ -1088,8 +1088,8 @@ static IrInstSrc *ir_build_const_enum_literal(Stage1AstGen *ag, Scope *scope, As
10881088}
10891089
10901090// Consumes `str`.
1091static IrInstSrc *ir_create_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) {
1092 IrInstSrcConst *const_instruction = ir_create_instruction<IrInstSrcConst>(ag, scope, source_node);
1091static Stage1ZirInst *ir_create_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) {
1092 Stage1ZirInstConst *const_instruction = ir_create_instruction<Stage1ZirInstConst>(ag, scope, source_node);
10931093 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
10941094 init_const_str_lit(ag->codegen, const_instruction->value, str, true);
10951095
......@@ -1097,16 +1097,16 @@ static IrInstSrc *ir_create_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNod
10971097}
10981098
10991099// Consumes `str`.
1100static IrInstSrc *ir_build_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) {
1101 IrInstSrc *instruction = ir_create_const_str_lit(ag, scope, source_node, str);
1100static Stage1ZirInst *ir_build_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) {
1101 Stage1ZirInst *instruction = ir_create_const_str_lit(ag, scope, source_node, str);
11021102 ir_instruction_append(ag->current_basic_block, instruction);
11031103 return instruction;
11041104}
11051105
1106static IrInstSrc *ir_build_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrBinOp op_id,
1107 IrInstSrc *op1, IrInstSrc *op2, bool safety_check_on)
1106static Stage1ZirInst *ir_build_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrBinOp op_id,
1107 Stage1ZirInst *op1, Stage1ZirInst *op2, bool safety_check_on)
11081108{
1109 IrInstSrcBinOp *inst = ir_build_instruction<IrInstSrcBinOp>(ag, scope, source_node);
1109 Stage1ZirInstBinOp *inst = ir_build_instruction<Stage1ZirInstBinOp>(ag, scope, source_node);
11101110 inst->op_id = op_id;
11111111 inst->op1 = op1;
11121112 inst->op2 = op2;
......@@ -1118,10 +1118,10 @@ static IrInstSrc *ir_build_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *sourc
11181118 return &inst->base;
11191119}
11201120
1121static IrInstSrc *ir_build_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1122 IrInstSrc *op1, IrInstSrc *op2, Buf *type_name)
1121static Stage1ZirInst *ir_build_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1122 Stage1ZirInst *op1, Stage1ZirInst *op2, Buf *type_name)
11231123{
1124 IrInstSrcMergeErrSets *inst = ir_build_instruction<IrInstSrcMergeErrSets>(ag, scope, source_node);
1124 Stage1ZirInstMergeErrSets *inst = ir_build_instruction<Stage1ZirInstMergeErrSets>(ag, scope, source_node);
11251125 inst->op1 = op1;
11261126 inst->op2 = op2;
11271127 inst->type_name = type_name;
......@@ -1132,10 +1132,10 @@ static IrInstSrc *ir_build_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNod
11321132 return &inst->base;
11331133}
11341134
1135static IrInstSrc *ir_build_var_ptr_x(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var,
1135static Stage1ZirInst *ir_build_var_ptr_x(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var,
11361136 ScopeFnDef *crossed_fndef_scope)
11371137{
1138 IrInstSrcVarPtr *instruction = ir_build_instruction<IrInstSrcVarPtr>(ag, scope, source_node);
1138 Stage1ZirInstVarPtr *instruction = ir_build_instruction<Stage1ZirInstVarPtr>(ag, scope, source_node);
11391139 instruction->var = var;
11401140 instruction->crossed_fndef_scope = crossed_fndef_scope;
11411141
......@@ -1144,15 +1144,15 @@ static IrInstSrc *ir_build_var_ptr_x(Stage1AstGen *ag, Scope *scope, AstNode *so
11441144 return &instruction->base;
11451145}
11461146
1147static IrInstSrc *ir_build_var_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var) {
1147static Stage1ZirInst *ir_build_var_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var) {
11481148 return ir_build_var_ptr_x(ag, scope, source_node, var, nullptr);
11491149}
11501150
1151static IrInstSrc *ir_build_elem_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1152 IrInstSrc *array_ptr, IrInstSrc *elem_index, bool safety_check_on, PtrLen ptr_len,
1151static Stage1ZirInst *ir_build_elem_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1152 Stage1ZirInst *array_ptr, Stage1ZirInst *elem_index, bool safety_check_on, PtrLen ptr_len,
11531153 AstNode *init_array_type_source_node)
11541154{
1155 IrInstSrcElemPtr *instruction = ir_build_instruction<IrInstSrcElemPtr>(ag, scope, source_node);
1155 Stage1ZirInstElemPtr *instruction = ir_build_instruction<Stage1ZirInstElemPtr>(ag, scope, source_node);
11561156 instruction->array_ptr = array_ptr;
11571157 instruction->elem_index = elem_index;
11581158 instruction->safety_check_on = safety_check_on;
......@@ -1165,10 +1165,10 @@ static IrInstSrc *ir_build_elem_ptr(Stage1AstGen *ag, Scope *scope, AstNode *sou
11651165 return &instruction->base;
11661166}
11671167
1168static IrInstSrc *ir_build_field_ptr_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1169 IrInstSrc *container_ptr, IrInstSrc *field_name_expr, bool initializing)
1168static Stage1ZirInst *ir_build_field_ptr_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1169 Stage1ZirInst *container_ptr, Stage1ZirInst *field_name_expr, bool initializing)
11701170{
1171 IrInstSrcFieldPtr *instruction = ir_build_instruction<IrInstSrcFieldPtr>(ag, scope, source_node);
1171 Stage1ZirInstFieldPtr *instruction = ir_build_instruction<Stage1ZirInstFieldPtr>(ag, scope, source_node);
11721172 instruction->container_ptr = container_ptr;
11731173 instruction->field_name_buffer = nullptr;
11741174 instruction->field_name_expr = field_name_expr;
......@@ -1180,10 +1180,10 @@ static IrInstSrc *ir_build_field_ptr_instruction(Stage1AstGen *ag, Scope *scope,
11801180 return &instruction->base;
11811181}
11821182
1183static IrInstSrc *ir_build_field_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1184 IrInstSrc *container_ptr, Buf *field_name, bool initializing)
1183static Stage1ZirInst *ir_build_field_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1184 Stage1ZirInst *container_ptr, Buf *field_name, bool initializing)
11851185{
1186 IrInstSrcFieldPtr *instruction = ir_build_instruction<IrInstSrcFieldPtr>(ag, scope, source_node);
1186 Stage1ZirInstFieldPtr *instruction = ir_build_instruction<Stage1ZirInstFieldPtr>(ag, scope, source_node);
11871187 instruction->container_ptr = container_ptr;
11881188 instruction->field_name_buffer = field_name;
11891189 instruction->field_name_expr = nullptr;
......@@ -1194,10 +1194,10 @@ static IrInstSrc *ir_build_field_ptr(Stage1AstGen *ag, Scope *scope, AstNode *so
11941194 return &instruction->base;
11951195}
11961196
1197static IrInstSrc *ir_build_has_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1198 IrInstSrc *container_type, IrInstSrc *field_name)
1197static Stage1ZirInst *ir_build_has_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1198 Stage1ZirInst *container_type, Stage1ZirInst *field_name)
11991199{
1200 IrInstSrcHasField *instruction = ir_build_instruction<IrInstSrcHasField>(ag, scope, source_node);
1200 Stage1ZirInstHasField *instruction = ir_build_instruction<Stage1ZirInstHasField>(ag, scope, source_node);
12011201 instruction->container_type = container_type;
12021202 instruction->field_name = field_name;
12031203
......@@ -1207,10 +1207,10 @@ static IrInstSrc *ir_build_has_field(Stage1AstGen *ag, Scope *scope, AstNode *so
12071207 return &instruction->base;
12081208}
12091209
1210static IrInstSrc *ir_build_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1211 IrInstSrc *options, IrInstSrc *fn_ref, IrInstSrc *args, ResultLoc *result_loc)
1210static Stage1ZirInst *ir_build_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1211 Stage1ZirInst *options, Stage1ZirInst *fn_ref, Stage1ZirInst *args, ResultLoc *result_loc)
12121212{
1213 IrInstSrcCallExtra *call_instruction = ir_build_instruction<IrInstSrcCallExtra>(ag, scope, source_node);
1213 Stage1ZirInstCallExtra *call_instruction = ir_build_instruction<Stage1ZirInstCallExtra>(ag, scope, source_node);
12141214 call_instruction->options = options;
12151215 call_instruction->fn_ref = fn_ref;
12161216 call_instruction->args = args;
......@@ -1223,10 +1223,10 @@ static IrInstSrc *ir_build_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *s
12231223 return &call_instruction->base;
12241224}
12251225
1226static IrInstSrc *ir_build_async_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1227 CallModifier modifier, IrInstSrc *fn_ref, IrInstSrc *ret_ptr, IrInstSrc *new_stack, IrInstSrc *args, ResultLoc *result_loc)
1226static Stage1ZirInst *ir_build_async_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1227 CallModifier modifier, Stage1ZirInst *fn_ref, Stage1ZirInst *ret_ptr, Stage1ZirInst *new_stack, Stage1ZirInst *args, ResultLoc *result_loc)
12281228{
1229 IrInstSrcAsyncCallExtra *call_instruction = ir_build_instruction<IrInstSrcAsyncCallExtra>(ag, scope, source_node);
1229 Stage1ZirInstAsyncCallExtra *call_instruction = ir_build_instruction<Stage1ZirInstAsyncCallExtra>(ag, scope, source_node);
12301230 call_instruction->modifier = modifier;
12311231 call_instruction->fn_ref = fn_ref;
12321232 call_instruction->ret_ptr = ret_ptr;
......@@ -1242,11 +1242,11 @@ static IrInstSrc *ir_build_async_call_extra(Stage1AstGen *ag, Scope *scope, AstN
12421242 return &call_instruction->base;
12431243}
12441244
1245static IrInstSrc *ir_build_call_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1246 IrInstSrc *options, IrInstSrc *fn_ref, IrInstSrc **args_ptr, size_t args_len,
1245static Stage1ZirInst *ir_build_call_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1246 Stage1ZirInst *options, Stage1ZirInst *fn_ref, Stage1ZirInst **args_ptr, size_t args_len,
12471247 ResultLoc *result_loc)
12481248{
1249 IrInstSrcCallArgs *call_instruction = ir_build_instruction<IrInstSrcCallArgs>(ag, scope, source_node);
1249 Stage1ZirInstCallArgs *call_instruction = ir_build_instruction<Stage1ZirInstCallArgs>(ag, scope, source_node);
12501250 call_instruction->options = options;
12511251 call_instruction->fn_ref = fn_ref;
12521252 call_instruction->args_ptr = args_ptr;
......@@ -1261,12 +1261,12 @@ static IrInstSrc *ir_build_call_args(Stage1AstGen *ag, Scope *scope, AstNode *so
12611261 return &call_instruction->base;
12621262}
12631263
1264static IrInstSrc *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1265 ZigFn *fn_entry, IrInstSrc *fn_ref, size_t arg_count, IrInstSrc **args,
1266 IrInstSrc *ret_ptr, CallModifier modifier, bool is_async_call_builtin,
1267 IrInstSrc *new_stack, ResultLoc *result_loc)
1264static Stage1ZirInst *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1265 ZigFn *fn_entry, Stage1ZirInst *fn_ref, size_t arg_count, Stage1ZirInst **args,
1266 Stage1ZirInst *ret_ptr, CallModifier modifier, bool is_async_call_builtin,
1267 Stage1ZirInst *new_stack, ResultLoc *result_loc)
12681268{
1269 IrInstSrcCall *call_instruction = ir_build_instruction<IrInstSrcCall>(ag, scope, source_node);
1269 Stage1ZirInstCall *call_instruction = ir_build_instruction<Stage1ZirInstCall>(ag, scope, source_node);
12701270 call_instruction->fn_entry = fn_entry;
12711271 call_instruction->fn_ref = fn_ref;
12721272 call_instruction->args = args;
......@@ -1286,14 +1286,14 @@ static IrInstSrc *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *sou
12861286 return &call_instruction->base;
12871287}
12881288
1289static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1290 size_t incoming_count, Stage1ZirBasicBlock **incoming_blocks, IrInstSrc **incoming_values,
1289static Stage1ZirInst *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1290 size_t incoming_count, Stage1ZirBasicBlock **incoming_blocks, Stage1ZirInst **incoming_values,
12911291 ResultLocPeerParent *peer_parent)
12921292{
12931293 assert(incoming_count != 0);
12941294 assert(incoming_count != SIZE_MAX);
12951295
1296 IrInstSrcPhi *phi_instruction = ir_build_instruction<IrInstSrcPhi>(ag, scope, source_node);
1296 Stage1ZirInstPhi *phi_instruction = ir_build_instruction<Stage1ZirInstPhi>(ag, scope, source_node);
12971297 phi_instruction->incoming_count = incoming_count;
12981298 phi_instruction->incoming_blocks = incoming_blocks;
12991299 phi_instruction->incoming_values = incoming_values;
......@@ -1307,10 +1307,10 @@ static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_n
13071307 return &phi_instruction->base;
13081308}
13091309
1310static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1311 Stage1ZirBasicBlock *dest_block, IrInstSrc *is_comptime)
1310static Stage1ZirInst *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1311 Stage1ZirBasicBlock *dest_block, Stage1ZirInst *is_comptime)
13121312{
1313 IrInstSrcBr *inst = ir_build_instruction<IrInstSrcBr>(ag, scope, source_node);
1313 Stage1ZirInstBr *inst = ir_build_instruction<Stage1ZirInstBr>(ag, scope, source_node);
13141314 inst->dest_block = dest_block;
13151315 inst->is_comptime = is_comptime;
13161316
......@@ -1320,11 +1320,11 @@ static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_no
13201320 return &inst->base;
13211321}
13221322
1323static IrInstSrc *ir_build_ptr_type_simple(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1324 IrInstSrc *child_type, bool is_const)
1323static Stage1ZirInst *ir_build_ptr_type_simple(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1324 Stage1ZirInst *child_type, bool is_const)
13251325{
1326 IrInstSrcPtrTypeSimple *inst = heap::c_allocator.create<IrInstSrcPtrTypeSimple>();
1327 inst->base.id = is_const ? IrInstSrcIdPtrTypeSimpleConst : IrInstSrcIdPtrTypeSimple;
1326 Stage1ZirInstPtrTypeSimple *inst = heap::c_allocator.create<Stage1ZirInstPtrTypeSimple>();
1327 inst->base.id = is_const ? Stage1ZirInstIdPtrTypeSimpleConst : Stage1ZirInstIdPtrTypeSimple;
13281328 inst->base.scope = scope;
13291329 inst->base.source_node = source_node;
13301330 inst->base.debug_id = irb_next_debug_id(ag);
......@@ -1338,9 +1338,9 @@ static IrInstSrc *ir_build_ptr_type_simple(Stage1AstGen *ag, Scope *scope, AstNo
13381338 return &inst->base;
13391339}
13401340
1341static IrInstSrc *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1342 IrInstSrc *child_type, bool is_const, bool is_volatile, PtrLen ptr_len,
1343 IrInstSrc *sentinel, IrInstSrc *align_value,
1341static Stage1ZirInst *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1342 Stage1ZirInst *child_type, bool is_const, bool is_volatile, PtrLen ptr_len,
1343 Stage1ZirInst *sentinel, Stage1ZirInst *align_value,
13441344 uint32_t bit_offset_start, uint32_t host_int_bytes, bool is_allow_zero)
13451345{
13461346 if (!is_volatile && ptr_len == PtrLenSingle && sentinel == nullptr && align_value == nullptr &&
......@@ -1349,7 +1349,7 @@ static IrInstSrc *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *sou
13491349 return ir_build_ptr_type_simple(ag, scope, source_node, child_type, is_const);
13501350 }
13511351
1352 IrInstSrcPtrType *inst = ir_build_instruction<IrInstSrcPtrType>(ag, scope, source_node);
1352 Stage1ZirInstPtrType *inst = ir_build_instruction<Stage1ZirInstPtrType>(ag, scope, source_node);
13531353 inst->sentinel = sentinel;
13541354 inst->align_value = align_value;
13551355 inst->child_type = child_type;
......@@ -1367,10 +1367,10 @@ static IrInstSrc *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *sou
13671367 return &inst->base;
13681368}
13691369
1370static IrInstSrc *ir_build_un_op_lval(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id,
1371 IrInstSrc *value, LVal lval, ResultLoc *result_loc)
1370static Stage1ZirInst *ir_build_un_op_lval(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id,
1371 Stage1ZirInst *value, LVal lval, ResultLoc *result_loc)
13721372{
1373 IrInstSrcUnOp *instruction = ir_build_instruction<IrInstSrcUnOp>(ag, scope, source_node);
1373 Stage1ZirInstUnOp *instruction = ir_build_instruction<Stage1ZirInstUnOp>(ag, scope, source_node);
13741374 instruction->op_id = op_id;
13751375 instruction->value = value;
13761376 instruction->lval = lval;
......@@ -1381,18 +1381,18 @@ static IrInstSrc *ir_build_un_op_lval(Stage1AstGen *ag, Scope *scope, AstNode *s
13811381 return &instruction->base;
13821382}
13831383
1384static IrInstSrc *ir_build_un_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id,
1385 IrInstSrc *value)
1384static Stage1ZirInst *ir_build_un_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id,
1385 Stage1ZirInst *value)
13861386{
13871387 return ir_build_un_op_lval(ag, scope, source_node, op_id, value, LValNone, nullptr);
13881388}
13891389
1390static IrInstSrc *ir_build_container_init_list(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1391 size_t item_count, IrInstSrc **elem_result_loc_list, IrInstSrc *result_loc,
1390static Stage1ZirInst *ir_build_container_init_list(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1391 size_t item_count, Stage1ZirInst **elem_result_loc_list, Stage1ZirInst *result_loc,
13921392 AstNode *init_array_type_source_node)
13931393{
1394 IrInstSrcContainerInitList *container_init_list_instruction =
1395 ir_build_instruction<IrInstSrcContainerInitList>(ag, scope, source_node);
1394 Stage1ZirInstContainerInitList *container_init_list_instruction =
1395 ir_build_instruction<Stage1ZirInstContainerInitList>(ag, scope, source_node);
13961396 container_init_list_instruction->item_count = item_count;
13971397 container_init_list_instruction->elem_result_loc_list = elem_result_loc_list;
13981398 container_init_list_instruction->result_loc = result_loc;
......@@ -1406,11 +1406,11 @@ static IrInstSrc *ir_build_container_init_list(Stage1AstGen *ag, Scope *scope, A
14061406 return &container_init_list_instruction->base;
14071407}
14081408
1409static IrInstSrc *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1410 size_t field_count, IrInstSrcContainerInitFieldsField *fields, IrInstSrc *result_loc)
1409static Stage1ZirInst *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1410 size_t field_count, Stage1ZirInstContainerInitFieldsField *fields, Stage1ZirInst *result_loc)
14111411{
1412 IrInstSrcContainerInitFields *container_init_fields_instruction =
1413 ir_build_instruction<IrInstSrcContainerInitFields>(ag, scope, source_node);
1412 Stage1ZirInstContainerInitFields *container_init_fields_instruction =
1413 ir_build_instruction<Stage1ZirInstContainerInitFields>(ag, scope, source_node);
14141414 container_init_fields_instruction->field_count = field_count;
14151415 container_init_fields_instruction->fields = fields;
14161416 container_init_fields_instruction->result_loc = result_loc;
......@@ -1423,15 +1423,15 @@ static IrInstSrc *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope,
14231423 return &container_init_fields_instruction->base;
14241424}
14251425
1426static IrInstSrc *ir_build_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
1427 IrInstSrcUnreachable *inst = ir_build_instruction<IrInstSrcUnreachable>(ag, scope, source_node);
1426static Stage1ZirInst *ir_build_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
1427 Stage1ZirInstUnreachable *inst = ir_build_instruction<Stage1ZirInstUnreachable>(ag, scope, source_node);
14281428 return &inst->base;
14291429}
14301430
1431static IrInstSrcStorePtr *ir_build_store_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1432 IrInstSrc *ptr, IrInstSrc *value)
1431static Stage1ZirInstStorePtr *ir_build_store_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1432 Stage1ZirInst *ptr, Stage1ZirInst *value)
14331433{
1434 IrInstSrcStorePtr *instruction = ir_build_instruction<IrInstSrcStorePtr>(ag, scope, source_node);
1434 Stage1ZirInstStorePtr *instruction = ir_build_instruction<Stage1ZirInstStorePtr>(ag, scope, source_node);
14351435 instruction->ptr = ptr;
14361436 instruction->value = value;
14371437
......@@ -1441,10 +1441,10 @@ static IrInstSrcStorePtr *ir_build_store_ptr(Stage1AstGen *ag, Scope *scope, Ast
14411441 return instruction;
14421442}
14431443
1444static IrInstSrc *ir_build_var_decl_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1445 ZigVar *var, IrInstSrc *align_value, IrInstSrc *ptr)
1444static Stage1ZirInst *ir_build_var_decl_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1445 ZigVar *var, Stage1ZirInst *align_value, Stage1ZirInst *ptr)
14461446{
1447 IrInstSrcDeclVar *inst = ir_build_instruction<IrInstSrcDeclVar>(ag, scope, source_node);
1447 Stage1ZirInstDeclVar *inst = ir_build_instruction<Stage1ZirInstDeclVar>(ag, scope, source_node);
14481448 inst->var = var;
14491449 inst->align_value = align_value;
14501450 inst->ptr = ptr;
......@@ -1455,10 +1455,10 @@ static IrInstSrc *ir_build_var_decl_src(Stage1AstGen *ag, Scope *scope, AstNode
14551455 return &inst->base;
14561456}
14571457
1458static IrInstSrc *ir_build_export(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1459 IrInstSrc *target, IrInstSrc *options)
1458static Stage1ZirInst *ir_build_export(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1459 Stage1ZirInst *target, Stage1ZirInst *options)
14601460{
1461 IrInstSrcExport *export_instruction = ir_build_instruction<IrInstSrcExport>(
1461 Stage1ZirInstExport *export_instruction = ir_build_instruction<Stage1ZirInstExport>(
14621462 ag, scope, source_node);
14631463 export_instruction->target = target;
14641464 export_instruction->options = options;
......@@ -1469,10 +1469,10 @@ static IrInstSrc *ir_build_export(Stage1AstGen *ag, Scope *scope, AstNode *sourc
14691469 return &export_instruction->base;
14701470}
14711471
1472static IrInstSrc *ir_build_extern(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1473 IrInstSrc *type, IrInstSrc *options)
1472static Stage1ZirInst *ir_build_extern(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1473 Stage1ZirInst *type, Stage1ZirInst *options)
14741474{
1475 IrInstSrcExtern *extern_instruction = ir_build_instruction<IrInstSrcExtern>(
1475 Stage1ZirInstExtern *extern_instruction = ir_build_instruction<Stage1ZirInstExtern>(
14761476 ag, scope, source_node);
14771477 extern_instruction->type = type;
14781478 extern_instruction->options = options;
......@@ -1483,8 +1483,8 @@ static IrInstSrc *ir_build_extern(Stage1AstGen *ag, Scope *scope, AstNode *sourc
14831483 return &extern_instruction->base;
14841484}
14851485
1486static IrInstSrc *ir_build_load_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *ptr) {
1487 IrInstSrcLoadPtr *instruction = ir_build_instruction<IrInstSrcLoadPtr>(ag, scope, source_node);
1486static Stage1ZirInst *ir_build_load_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *ptr) {
1487 Stage1ZirInstLoadPtr *instruction = ir_build_instruction<Stage1ZirInstLoadPtr>(ag, scope, source_node);
14881488 instruction->ptr = ptr;
14891489
14901490 ir_ref_instruction(ptr, ag->current_basic_block);
......@@ -1492,12 +1492,12 @@ static IrInstSrc *ir_build_load_ptr(Stage1AstGen *ag, Scope *scope, AstNode *sou
14921492 return &instruction->base;
14931493}
14941494
1495static IrInstSrc *ir_build_typeof_n(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1496 IrInstSrc **values, size_t value_count)
1495static Stage1ZirInst *ir_build_typeof_n(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1496 Stage1ZirInst **values, size_t value_count)
14971497{
14981498 assert(value_count >= 2);
14991499
1500 IrInstSrcTypeOf *instruction = ir_build_instruction<IrInstSrcTypeOf>(ag, scope, source_node);
1500 Stage1ZirInstTypeOf *instruction = ir_build_instruction<Stage1ZirInstTypeOf>(ag, scope, source_node);
15011501 instruction->value.list = values;
15021502 instruction->value_count = value_count;
15031503
......@@ -1507,8 +1507,8 @@ static IrInstSrc *ir_build_typeof_n(Stage1AstGen *ag, Scope *scope, AstNode *sou
15071507 return &instruction->base;
15081508}
15091509
1510static IrInstSrc *ir_build_typeof_1(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) {
1511 IrInstSrcTypeOf *instruction = ir_build_instruction<IrInstSrcTypeOf>(ag, scope, source_node);
1510static Stage1ZirInst *ir_build_typeof_1(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) {
1511 Stage1ZirInstTypeOf *instruction = ir_build_instruction<Stage1ZirInstTypeOf>(ag, scope, source_node);
15121512 instruction->value.scalar = value;
15131513
15141514 ir_ref_instruction(value, ag->current_basic_block);
......@@ -1516,8 +1516,8 @@ static IrInstSrc *ir_build_typeof_1(Stage1AstGen *ag, Scope *scope, AstNode *sou
15161516 return &instruction->base;
15171517}
15181518
1519static IrInstSrc *ir_build_set_cold(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *is_cold) {
1520 IrInstSrcSetCold *instruction = ir_build_instruction<IrInstSrcSetCold>(ag, scope, source_node);
1519static Stage1ZirInst *ir_build_set_cold(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *is_cold) {
1520 Stage1ZirInstSetCold *instruction = ir_build_instruction<Stage1ZirInstSetCold>(ag, scope, source_node);
15211521 instruction->is_cold = is_cold;
15221522
15231523 ir_ref_instruction(is_cold, ag->current_basic_block);
......@@ -1525,10 +1525,10 @@ static IrInstSrc *ir_build_set_cold(Stage1AstGen *ag, Scope *scope, AstNode *sou
15251525 return &instruction->base;
15261526}
15271527
1528static IrInstSrc *ir_build_set_runtime_safety(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1529 IrInstSrc *safety_on)
1528static Stage1ZirInst *ir_build_set_runtime_safety(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1529 Stage1ZirInst *safety_on)
15301530{
1531 IrInstSrcSetRuntimeSafety *inst = ir_build_instruction<IrInstSrcSetRuntimeSafety>(ag, scope, source_node);
1531 Stage1ZirInstSetRuntimeSafety *inst = ir_build_instruction<Stage1ZirInstSetRuntimeSafety>(ag, scope, source_node);
15321532 inst->safety_on = safety_on;
15331533
15341534 ir_ref_instruction(safety_on, ag->current_basic_block);
......@@ -1536,10 +1536,10 @@ static IrInstSrc *ir_build_set_runtime_safety(Stage1AstGen *ag, Scope *scope, As
15361536 return &inst->base;
15371537}
15381538
1539static IrInstSrc *ir_build_set_float_mode(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1540 IrInstSrc *mode_value)
1539static Stage1ZirInst *ir_build_set_float_mode(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1540 Stage1ZirInst *mode_value)
15411541{
1542 IrInstSrcSetFloatMode *instruction = ir_build_instruction<IrInstSrcSetFloatMode>(ag, scope, source_node);
1542 Stage1ZirInstSetFloatMode *instruction = ir_build_instruction<Stage1ZirInstSetFloatMode>(ag, scope, source_node);
15431543 instruction->mode_value = mode_value;
15441544
15451545 ir_ref_instruction(mode_value, ag->current_basic_block);
......@@ -1547,10 +1547,10 @@ static IrInstSrc *ir_build_set_float_mode(Stage1AstGen *ag, Scope *scope, AstNod
15471547 return &instruction->base;
15481548}
15491549
1550static IrInstSrc *ir_build_array_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *size,
1551 IrInstSrc *sentinel, IrInstSrc *child_type)
1550static Stage1ZirInst *ir_build_array_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *size,
1551 Stage1ZirInst *sentinel, Stage1ZirInst *child_type)
15521552{
1553 IrInstSrcArrayType *instruction = ir_build_instruction<IrInstSrcArrayType>(ag, scope, source_node);
1553 Stage1ZirInstArrayType *instruction = ir_build_instruction<Stage1ZirInstArrayType>(ag, scope, source_node);
15541554 instruction->size = size;
15551555 instruction->sentinel = sentinel;
15561556 instruction->child_type = child_type;
......@@ -1562,10 +1562,10 @@ static IrInstSrc *ir_build_array_type(Stage1AstGen *ag, Scope *scope, AstNode *s
15621562 return &instruction->base;
15631563}
15641564
1565static IrInstSrc *ir_build_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1566 IrInstSrc *payload_type)
1565static Stage1ZirInst *ir_build_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1566 Stage1ZirInst *payload_type)
15671567{
1568 IrInstSrcAnyFrameType *instruction = ir_build_instruction<IrInstSrcAnyFrameType>(ag, scope, source_node);
1568 Stage1ZirInstAnyFrameType *instruction = ir_build_instruction<Stage1ZirInstAnyFrameType>(ag, scope, source_node);
15691569 instruction->payload_type = payload_type;
15701570
15711571 if (payload_type != nullptr) ir_ref_instruction(payload_type, ag->current_basic_block);
......@@ -1573,11 +1573,11 @@ static IrInstSrc *ir_build_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode
15731573 return &instruction->base;
15741574}
15751575
1576static IrInstSrc *ir_build_slice_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1577 IrInstSrc *child_type, bool is_const, bool is_volatile,
1578 IrInstSrc *sentinel, IrInstSrc *align_value, bool is_allow_zero)
1576static Stage1ZirInst *ir_build_slice_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1577 Stage1ZirInst *child_type, bool is_const, bool is_volatile,
1578 Stage1ZirInst *sentinel, Stage1ZirInst *align_value, bool is_allow_zero)
15791579{
1580 IrInstSrcSliceType *instruction = ir_build_instruction<IrInstSrcSliceType>(ag, scope, source_node);
1580 Stage1ZirInstSliceType *instruction = ir_build_instruction<Stage1ZirInstSliceType>(ag, scope, source_node);
15811581 instruction->is_const = is_const;
15821582 instruction->is_volatile = is_volatile;
15831583 instruction->child_type = child_type;
......@@ -1592,11 +1592,11 @@ static IrInstSrc *ir_build_slice_type(Stage1AstGen *ag, Scope *scope, AstNode *s
15921592 return &instruction->base;
15931593}
15941594
1595static IrInstSrc *ir_build_asm_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1596 IrInstSrc *asm_template, IrInstSrc **input_list, IrInstSrc **output_types,
1595static Stage1ZirInst *ir_build_asm_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1596 Stage1ZirInst *asm_template, Stage1ZirInst **input_list, Stage1ZirInst **output_types,
15971597 ZigVar **output_vars, size_t return_count, bool has_side_effects, bool is_global)
15981598{
1599 IrInstSrcAsm *instruction = ir_build_instruction<IrInstSrcAsm>(ag, scope, source_node);
1599 Stage1ZirInstAsm *instruction = ir_build_instruction<Stage1ZirInstAsm>(ag, scope, source_node);
16001600 instruction->asm_template = asm_template;
16011601 instruction->input_list = input_list;
16021602 instruction->output_types = output_types;
......@@ -1607,22 +1607,22 @@ static IrInstSrc *ir_build_asm_src(Stage1AstGen *ag, Scope *scope, AstNode *sour
16071607
16081608 assert(source_node->type == NodeTypeAsmExpr);
16091609 for (size_t i = 0; i < source_node->data.asm_expr.output_list.length; i += 1) {
1610 IrInstSrc *output_type = output_types[i];
1610 Stage1ZirInst *output_type = output_types[i];
16111611 if (output_type) ir_ref_instruction(output_type, ag->current_basic_block);
16121612 }
16131613
16141614 for (size_t i = 0; i < source_node->data.asm_expr.input_list.length; i += 1) {
1615 IrInstSrc *input_value = input_list[i];
1615 Stage1ZirInst *input_value = input_list[i];
16161616 ir_ref_instruction(input_value, ag->current_basic_block);
16171617 }
16181618
16191619 return &instruction->base;
16201620}
16211621
1622static IrInstSrc *ir_build_size_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_value,
1622static Stage1ZirInst *ir_build_size_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_value,
16231623 bool bit_size)
16241624{
1625 IrInstSrcSizeOf *instruction = ir_build_instruction<IrInstSrcSizeOf>(ag, scope, source_node);
1625 Stage1ZirInstSizeOf *instruction = ir_build_instruction<Stage1ZirInstSizeOf>(ag, scope, source_node);
16261626 instruction->type_value = type_value;
16271627 instruction->bit_size = bit_size;
16281628
......@@ -1631,10 +1631,10 @@ static IrInstSrc *ir_build_size_of(Stage1AstGen *ag, Scope *scope, AstNode *sour
16311631 return &instruction->base;
16321632}
16331633
1634static IrInstSrc *ir_build_test_non_null_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1635 IrInstSrc *value)
1634static Stage1ZirInst *ir_build_test_non_null_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1635 Stage1ZirInst *value)
16361636{
1637 IrInstSrcTestNonNull *instruction = ir_build_instruction<IrInstSrcTestNonNull>(ag, scope, source_node);
1637 Stage1ZirInstTestNonNull *instruction = ir_build_instruction<Stage1ZirInstTestNonNull>(ag, scope, source_node);
16381638 instruction->value = value;
16391639
16401640 ir_ref_instruction(value, ag->current_basic_block);
......@@ -1642,10 +1642,10 @@ static IrInstSrc *ir_build_test_non_null_src(Stage1AstGen *ag, Scope *scope, Ast
16421642 return &instruction->base;
16431643}
16441644
1645static IrInstSrc *ir_build_optional_unwrap_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1646 IrInstSrc *base_ptr, bool safety_check_on)
1645static Stage1ZirInst *ir_build_optional_unwrap_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1646 Stage1ZirInst *base_ptr, bool safety_check_on)
16471647{
1648 IrInstSrcOptionalUnwrapPtr *instruction = ir_build_instruction<IrInstSrcOptionalUnwrapPtr>(ag, scope, source_node);
1648 Stage1ZirInstOptionalUnwrapPtr *instruction = ir_build_instruction<Stage1ZirInstOptionalUnwrapPtr>(ag, scope, source_node);
16491649 instruction->base_ptr = base_ptr;
16501650 instruction->safety_check_on = safety_check_on;
16511651
......@@ -1654,10 +1654,10 @@ static IrInstSrc *ir_build_optional_unwrap_ptr(Stage1AstGen *ag, Scope *scope, A
16541654 return &instruction->base;
16551655}
16561656
1657static IrInstSrc *ir_build_clz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type,
1658 IrInstSrc *op)
1657static Stage1ZirInst *ir_build_clz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type,
1658 Stage1ZirInst *op)
16591659{
1660 IrInstSrcClz *instruction = ir_build_instruction<IrInstSrcClz>(ag, scope, source_node);
1660 Stage1ZirInstClz *instruction = ir_build_instruction<Stage1ZirInstClz>(ag, scope, source_node);
16611661 instruction->type = type;
16621662 instruction->op = op;
16631663
......@@ -1667,10 +1667,10 @@ static IrInstSrc *ir_build_clz(Stage1AstGen *ag, Scope *scope, AstNode *source_n
16671667 return &instruction->base;
16681668}
16691669
1670static IrInstSrc *ir_build_ctz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type,
1671 IrInstSrc *op)
1670static Stage1ZirInst *ir_build_ctz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type,
1671 Stage1ZirInst *op)
16721672{
1673 IrInstSrcCtz *instruction = ir_build_instruction<IrInstSrcCtz>(ag, scope, source_node);
1673 Stage1ZirInstCtz *instruction = ir_build_instruction<Stage1ZirInstCtz>(ag, scope, source_node);
16741674 instruction->type = type;
16751675 instruction->op = op;
16761676
......@@ -1680,10 +1680,10 @@ static IrInstSrc *ir_build_ctz(Stage1AstGen *ag, Scope *scope, AstNode *source_n
16801680 return &instruction->base;
16811681}
16821682
1683static IrInstSrc *ir_build_pop_count(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type,
1684 IrInstSrc *op)
1683static Stage1ZirInst *ir_build_pop_count(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type,
1684 Stage1ZirInst *op)
16851685{
1686 IrInstSrcPopCount *instruction = ir_build_instruction<IrInstSrcPopCount>(ag, scope, source_node);
1686 Stage1ZirInstPopCount *instruction = ir_build_instruction<Stage1ZirInstPopCount>(ag, scope, source_node);
16871687 instruction->type = type;
16881688 instruction->op = op;
16891689
......@@ -1693,10 +1693,10 @@ static IrInstSrc *ir_build_pop_count(Stage1AstGen *ag, Scope *scope, AstNode *so
16931693 return &instruction->base;
16941694}
16951695
1696static IrInstSrc *ir_build_bswap(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type,
1697 IrInstSrc *op)
1696static Stage1ZirInst *ir_build_bswap(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type,
1697 Stage1ZirInst *op)
16981698{
1699 IrInstSrcBswap *instruction = ir_build_instruction<IrInstSrcBswap>(ag, scope, source_node);
1699 Stage1ZirInstBswap *instruction = ir_build_instruction<Stage1ZirInstBswap>(ag, scope, source_node);
17001700 instruction->type = type;
17011701 instruction->op = op;
17021702
......@@ -1706,10 +1706,10 @@ static IrInstSrc *ir_build_bswap(Stage1AstGen *ag, Scope *scope, AstNode *source
17061706 return &instruction->base;
17071707}
17081708
1709static IrInstSrc *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type,
1710 IrInstSrc *op)
1709static Stage1ZirInst *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type,
1710 Stage1ZirInst *op)
17111711{
1712 IrInstSrcBitReverse *instruction = ir_build_instruction<IrInstSrcBitReverse>(ag, scope, source_node);
1712 Stage1ZirInstBitReverse *instruction = ir_build_instruction<Stage1ZirInstBitReverse>(ag, scope, source_node);
17131713 instruction->type = type;
17141714 instruction->op = op;
17151715
......@@ -1719,11 +1719,11 @@ static IrInstSrc *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *
17191719 return &instruction->base;
17201720}
17211721
1722static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1723 IrInstSrc *target_value, Stage1ZirBasicBlock *else_block, size_t case_count, IrInstSrcSwitchBrCase *cases,
1724 IrInstSrc *is_comptime, IrInstSrc *switch_prongs_void)
1722static Stage1ZirInstSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1723 Stage1ZirInst *target_value, Stage1ZirBasicBlock *else_block, size_t case_count, Stage1ZirInstSwitchBrCase *cases,
1724 Stage1ZirInst *is_comptime, Stage1ZirInst *switch_prongs_void)
17251725{
1726 IrInstSrcSwitchBr *instruction = ir_build_instruction<IrInstSrcSwitchBr>(ag, scope, source_node);
1726 Stage1ZirInstSwitchBr *instruction = ir_build_instruction<Stage1ZirInstSwitchBr>(ag, scope, source_node);
17271727 instruction->target_value = target_value;
17281728 instruction->else_block = else_block;
17291729 instruction->case_count = case_count;
......@@ -1744,10 +1744,10 @@ static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope,
17441744 return instruction;
17451745}
17461746
1747static IrInstSrc *ir_build_switch_target(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1748 IrInstSrc *target_value_ptr)
1747static Stage1ZirInst *ir_build_switch_target(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1748 Stage1ZirInst *target_value_ptr)
17491749{
1750 IrInstSrcSwitchTarget *instruction = ir_build_instruction<IrInstSrcSwitchTarget>(ag, scope, source_node);
1750 Stage1ZirInstSwitchTarget *instruction = ir_build_instruction<Stage1ZirInstSwitchTarget>(ag, scope, source_node);
17511751 instruction->target_value_ptr = target_value_ptr;
17521752
17531753 ir_ref_instruction(target_value_ptr, ag->current_basic_block);
......@@ -1755,10 +1755,10 @@ static IrInstSrc *ir_build_switch_target(Stage1AstGen *ag, Scope *scope, AstNode
17551755 return &instruction->base;
17561756}
17571757
1758static IrInstSrc *ir_build_switch_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1759 IrInstSrc *target_value_ptr, IrInstSrc **prongs_ptr, size_t prongs_len)
1758static Stage1ZirInst *ir_build_switch_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1759 Stage1ZirInst *target_value_ptr, Stage1ZirInst **prongs_ptr, size_t prongs_len)
17601760{
1761 IrInstSrcSwitchVar *instruction = ir_build_instruction<IrInstSrcSwitchVar>(ag, scope, source_node);
1761 Stage1ZirInstSwitchVar *instruction = ir_build_instruction<Stage1ZirInstSwitchVar>(ag, scope, source_node);
17621762 instruction->target_value_ptr = target_value_ptr;
17631763 instruction->prongs_ptr = prongs_ptr;
17641764 instruction->prongs_len = prongs_len;
......@@ -1772,10 +1772,10 @@ static IrInstSrc *ir_build_switch_var(Stage1AstGen *ag, Scope *scope, AstNode *s
17721772}
17731773
17741774// For this instruction the switch_br must be set later.
1775static IrInstSrcSwitchElseVar *ir_build_switch_else_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1776 IrInstSrc *target_value_ptr)
1775static Stage1ZirInstSwitchElseVar *ir_build_switch_else_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1776 Stage1ZirInst *target_value_ptr)
17771777{
1778 IrInstSrcSwitchElseVar *instruction = ir_build_instruction<IrInstSrcSwitchElseVar>(ag, scope, source_node);
1778 Stage1ZirInstSwitchElseVar *instruction = ir_build_instruction<Stage1ZirInstSwitchElseVar>(ag, scope, source_node);
17791779 instruction->target_value_ptr = target_value_ptr;
17801780
17811781 ir_ref_instruction(target_value_ptr, ag->current_basic_block);
......@@ -1783,8 +1783,8 @@ static IrInstSrcSwitchElseVar *ir_build_switch_else_var(Stage1AstGen *ag, Scope
17831783 return instruction;
17841784}
17851785
1786static IrInstSrc *ir_build_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) {
1787 IrInstSrcImport *instruction = ir_build_instruction<IrInstSrcImport>(ag, scope, source_node);
1786static Stage1ZirInst *ir_build_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) {
1787 Stage1ZirInstImport *instruction = ir_build_instruction<Stage1ZirInstImport>(ag, scope, source_node);
17881788 instruction->name = name;
17891789
17901790 ir_ref_instruction(name, ag->current_basic_block);
......@@ -1792,8 +1792,8 @@ static IrInstSrc *ir_build_import(Stage1AstGen *ag, Scope *scope, AstNode *sourc
17921792 return &instruction->base;
17931793}
17941794
1795static IrInstSrc *ir_build_ref_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) {
1796 IrInstSrcRef *instruction = ir_build_instruction<IrInstSrcRef>(ag, scope, source_node);
1795static Stage1ZirInst *ir_build_ref_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) {
1796 Stage1ZirInstRef *instruction = ir_build_instruction<Stage1ZirInstRef>(ag, scope, source_node);
17971797 instruction->value = value;
17981798
17991799 ir_ref_instruction(value, ag->current_basic_block);
......@@ -1801,8 +1801,8 @@ static IrInstSrc *ir_build_ref_src(Stage1AstGen *ag, Scope *scope, AstNode *sour
18011801 return &instruction->base;
18021802}
18031803
1804static IrInstSrc *ir_build_compile_err(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *msg) {
1805 IrInstSrcCompileErr *instruction = ir_build_instruction<IrInstSrcCompileErr>(ag, scope, source_node);
1804static Stage1ZirInst *ir_build_compile_err(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *msg) {
1805 Stage1ZirInstCompileErr *instruction = ir_build_instruction<Stage1ZirInstCompileErr>(ag, scope, source_node);
18061806 instruction->msg = msg;
18071807
18081808 ir_ref_instruction(msg, ag->current_basic_block);
......@@ -1810,10 +1810,10 @@ static IrInstSrc *ir_build_compile_err(Stage1AstGen *ag, Scope *scope, AstNode *
18101810 return &instruction->base;
18111811}
18121812
1813static IrInstSrc *ir_build_compile_log(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1814 size_t msg_count, IrInstSrc **msg_list)
1813static Stage1ZirInst *ir_build_compile_log(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1814 size_t msg_count, Stage1ZirInst **msg_list)
18151815{
1816 IrInstSrcCompileLog *instruction = ir_build_instruction<IrInstSrcCompileLog>(ag, scope, source_node);
1816 Stage1ZirInstCompileLog *instruction = ir_build_instruction<Stage1ZirInstCompileLog>(ag, scope, source_node);
18171817 instruction->msg_count = msg_count;
18181818 instruction->msg_list = msg_list;
18191819
......@@ -1824,8 +1824,8 @@ static IrInstSrc *ir_build_compile_log(Stage1AstGen *ag, Scope *scope, AstNode *
18241824 return &instruction->base;
18251825}
18261826
1827static IrInstSrc *ir_build_err_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) {
1828 IrInstSrcErrName *instruction = ir_build_instruction<IrInstSrcErrName>(ag, scope, source_node);
1827static Stage1ZirInst *ir_build_err_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) {
1828 Stage1ZirInstErrName *instruction = ir_build_instruction<Stage1ZirInstErrName>(ag, scope, source_node);
18291829 instruction->value = value;
18301830
18311831 ir_ref_instruction(value, ag->current_basic_block);
......@@ -1833,13 +1833,13 @@ static IrInstSrc *ir_build_err_name(Stage1AstGen *ag, Scope *scope, AstNode *sou
18331833 return &instruction->base;
18341834}
18351835
1836static IrInstSrc *ir_build_c_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
1837 IrInstSrcCImport *instruction = ir_build_instruction<IrInstSrcCImport>(ag, scope, source_node);
1836static Stage1ZirInst *ir_build_c_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
1837 Stage1ZirInstCImport *instruction = ir_build_instruction<Stage1ZirInstCImport>(ag, scope, source_node);
18381838 return &instruction->base;
18391839}
18401840
1841static IrInstSrc *ir_build_c_include(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) {
1842 IrInstSrcCInclude *instruction = ir_build_instruction<IrInstSrcCInclude>(ag, scope, source_node);
1841static Stage1ZirInst *ir_build_c_include(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) {
1842 Stage1ZirInstCInclude *instruction = ir_build_instruction<Stage1ZirInstCInclude>(ag, scope, source_node);
18431843 instruction->name = name;
18441844
18451845 ir_ref_instruction(name, ag->current_basic_block);
......@@ -1847,8 +1847,8 @@ static IrInstSrc *ir_build_c_include(Stage1AstGen *ag, Scope *scope, AstNode *so
18471847 return &instruction->base;
18481848}
18491849
1850static IrInstSrc *ir_build_c_define(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name, IrInstSrc *value) {
1851 IrInstSrcCDefine *instruction = ir_build_instruction<IrInstSrcCDefine>(ag, scope, source_node);
1850static Stage1ZirInst *ir_build_c_define(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name, Stage1ZirInst *value) {
1851 Stage1ZirInstCDefine *instruction = ir_build_instruction<Stage1ZirInstCDefine>(ag, scope, source_node);
18521852 instruction->name = name;
18531853 instruction->value = value;
18541854
......@@ -1858,8 +1858,8 @@ static IrInstSrc *ir_build_c_define(Stage1AstGen *ag, Scope *scope, AstNode *sou
18581858 return &instruction->base;
18591859}
18601860
1861static IrInstSrc *ir_build_c_undef(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) {
1862 IrInstSrcCUndef *instruction = ir_build_instruction<IrInstSrcCUndef>(ag, scope, source_node);
1861static Stage1ZirInst *ir_build_c_undef(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) {
1862 Stage1ZirInstCUndef *instruction = ir_build_instruction<Stage1ZirInstCUndef>(ag, scope, source_node);
18631863 instruction->name = name;
18641864
18651865 ir_ref_instruction(name, ag->current_basic_block);
......@@ -1867,8 +1867,8 @@ static IrInstSrc *ir_build_c_undef(Stage1AstGen *ag, Scope *scope, AstNode *sour
18671867 return &instruction->base;
18681868}
18691869
1870static IrInstSrc *ir_build_embed_file(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) {
1871 IrInstSrcEmbedFile *instruction = ir_build_instruction<IrInstSrcEmbedFile>(ag, scope, source_node);
1870static Stage1ZirInst *ir_build_embed_file(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) {
1871 Stage1ZirInstEmbedFile *instruction = ir_build_instruction<Stage1ZirInstEmbedFile>(ag, scope, source_node);
18721872 instruction->name = name;
18731873
18741874 ir_ref_instruction(name, ag->current_basic_block);
......@@ -1876,11 +1876,11 @@ static IrInstSrc *ir_build_embed_file(Stage1AstGen *ag, Scope *scope, AstNode *s
18761876 return &instruction->base;
18771877}
18781878
1879static IrInstSrc *ir_build_cmpxchg_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1880 IrInstSrc *type_value, IrInstSrc *ptr, IrInstSrc *cmp_value, IrInstSrc *new_value,
1881 IrInstSrc *success_order_value, IrInstSrc *failure_order_value, bool is_weak, ResultLoc *result_loc)
1879static Stage1ZirInst *ir_build_cmpxchg_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1880 Stage1ZirInst *type_value, Stage1ZirInst *ptr, Stage1ZirInst *cmp_value, Stage1ZirInst *new_value,
1881 Stage1ZirInst *success_order_value, Stage1ZirInst *failure_order_value, bool is_weak, ResultLoc *result_loc)
18821882{
1883 IrInstSrcCmpxchg *instruction = ir_build_instruction<IrInstSrcCmpxchg>(ag, scope, source_node);
1883 Stage1ZirInstCmpxchg *instruction = ir_build_instruction<Stage1ZirInstCmpxchg>(ag, scope, source_node);
18841884 instruction->type_value = type_value;
18851885 instruction->ptr = ptr;
18861886 instruction->cmp_value = cmp_value;
......@@ -1900,8 +1900,8 @@ static IrInstSrc *ir_build_cmpxchg_src(Stage1AstGen *ag, Scope *scope, AstNode *
19001900 return &instruction->base;
19011901}
19021902
1903static IrInstSrc *ir_build_fence(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *order) {
1904 IrInstSrcFence *instruction = ir_build_instruction<IrInstSrcFence>(ag, scope, source_node);
1903static Stage1ZirInst *ir_build_fence(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *order) {
1904 Stage1ZirInstFence *instruction = ir_build_instruction<Stage1ZirInstFence>(ag, scope, source_node);
19051905 instruction->order = order;
19061906
19071907 ir_ref_instruction(order, ag->current_basic_block);
......@@ -1909,8 +1909,8 @@ static IrInstSrc *ir_build_fence(Stage1AstGen *ag, Scope *scope, AstNode *source
19091909 return &instruction->base;
19101910}
19111911
1912static IrInstSrc *ir_build_reduce(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *op, IrInstSrc *value) {
1913 IrInstSrcReduce *instruction = ir_build_instruction<IrInstSrcReduce>(ag, scope, source_node);
1912static Stage1ZirInst *ir_build_reduce(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *op, Stage1ZirInst *value) {
1913 Stage1ZirInstReduce *instruction = ir_build_instruction<Stage1ZirInstReduce>(ag, scope, source_node);
19141914 instruction->op = op;
19151915 instruction->value = value;
19161916
......@@ -1920,10 +1920,10 @@ static IrInstSrc *ir_build_reduce(Stage1AstGen *ag, Scope *scope, AstNode *sourc
19201920 return &instruction->base;
19211921}
19221922
1923static IrInstSrc *ir_build_truncate(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1924 IrInstSrc *dest_type, IrInstSrc *target)
1923static Stage1ZirInst *ir_build_truncate(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1924 Stage1ZirInst *dest_type, Stage1ZirInst *target)
19251925{
1926 IrInstSrcTruncate *instruction = ir_build_instruction<IrInstSrcTruncate>(ag, scope, source_node);
1926 Stage1ZirInstTruncate *instruction = ir_build_instruction<Stage1ZirInstTruncate>(ag, scope, source_node);
19271927 instruction->dest_type = dest_type;
19281928 instruction->target = target;
19291929
......@@ -1933,10 +1933,10 @@ static IrInstSrc *ir_build_truncate(Stage1AstGen *ag, Scope *scope, AstNode *sou
19331933 return &instruction->base;
19341934}
19351935
1936static IrInstSrc *ir_build_int_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *dest_type,
1937 IrInstSrc *target)
1936static Stage1ZirInst *ir_build_int_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *dest_type,
1937 Stage1ZirInst *target)
19381938{
1939 IrInstSrcIntCast *instruction = ir_build_instruction<IrInstSrcIntCast>(ag, scope, source_node);
1939 Stage1ZirInstIntCast *instruction = ir_build_instruction<Stage1ZirInstIntCast>(ag, scope, source_node);
19401940 instruction->dest_type = dest_type;
19411941 instruction->target = target;
19421942
......@@ -1946,10 +1946,10 @@ static IrInstSrc *ir_build_int_cast(Stage1AstGen *ag, Scope *scope, AstNode *sou
19461946 return &instruction->base;
19471947}
19481948
1949static IrInstSrc *ir_build_float_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *dest_type,
1950 IrInstSrc *target)
1949static Stage1ZirInst *ir_build_float_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *dest_type,
1950 Stage1ZirInst *target)
19511951{
1952 IrInstSrcFloatCast *instruction = ir_build_instruction<IrInstSrcFloatCast>(ag, scope, source_node);
1952 Stage1ZirInstFloatCast *instruction = ir_build_instruction<Stage1ZirInstFloatCast>(ag, scope, source_node);
19531953 instruction->dest_type = dest_type;
19541954 instruction->target = target;
19551955
......@@ -1959,10 +1959,10 @@ static IrInstSrc *ir_build_float_cast(Stage1AstGen *ag, Scope *scope, AstNode *s
19591959 return &instruction->base;
19601960}
19611961
1962static IrInstSrc *ir_build_err_set_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1963 IrInstSrc *dest_type, IrInstSrc *target)
1962static Stage1ZirInst *ir_build_err_set_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1963 Stage1ZirInst *dest_type, Stage1ZirInst *target)
19641964{
1965 IrInstSrcErrSetCast *instruction = ir_build_instruction<IrInstSrcErrSetCast>(ag, scope, source_node);
1965 Stage1ZirInstErrSetCast *instruction = ir_build_instruction<Stage1ZirInstErrSetCast>(ag, scope, source_node);
19661966 instruction->dest_type = dest_type;
19671967 instruction->target = target;
19681968
......@@ -1972,10 +1972,10 @@ static IrInstSrc *ir_build_err_set_cast(Stage1AstGen *ag, Scope *scope, AstNode
19721972 return &instruction->base;
19731973}
19741974
1975static IrInstSrc *ir_build_int_to_float(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1976 IrInstSrc *dest_type, IrInstSrc *target)
1975static Stage1ZirInst *ir_build_int_to_float(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1976 Stage1ZirInst *dest_type, Stage1ZirInst *target)
19771977{
1978 IrInstSrcIntToFloat *instruction = ir_build_instruction<IrInstSrcIntToFloat>(ag, scope, source_node);
1978 Stage1ZirInstIntToFloat *instruction = ir_build_instruction<Stage1ZirInstIntToFloat>(ag, scope, source_node);
19791979 instruction->dest_type = dest_type;
19801980 instruction->target = target;
19811981
......@@ -1985,10 +1985,10 @@ static IrInstSrc *ir_build_int_to_float(Stage1AstGen *ag, Scope *scope, AstNode
19851985 return &instruction->base;
19861986}
19871987
1988static IrInstSrc *ir_build_float_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1989 IrInstSrc *dest_type, IrInstSrc *target)
1988static Stage1ZirInst *ir_build_float_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1989 Stage1ZirInst *dest_type, Stage1ZirInst *target)
19901990{
1991 IrInstSrcFloatToInt *instruction = ir_build_instruction<IrInstSrcFloatToInt>(ag, scope, source_node);
1991 Stage1ZirInstFloatToInt *instruction = ir_build_instruction<Stage1ZirInstFloatToInt>(ag, scope, source_node);
19921992 instruction->dest_type = dest_type;
19931993 instruction->target = target;
19941994
......@@ -1998,8 +1998,8 @@ static IrInstSrc *ir_build_float_to_int(Stage1AstGen *ag, Scope *scope, AstNode
19981998 return &instruction->base;
19991999}
20002000
2001static IrInstSrc *ir_build_bool_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *target) {
2002 IrInstSrcBoolToInt *instruction = ir_build_instruction<IrInstSrcBoolToInt>(ag, scope, source_node);
2001static Stage1ZirInst *ir_build_bool_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *target) {
2002 Stage1ZirInstBoolToInt *instruction = ir_build_instruction<Stage1ZirInstBoolToInt>(ag, scope, source_node);
20032003 instruction->target = target;
20042004
20052005 ir_ref_instruction(target, ag->current_basic_block);
......@@ -2007,10 +2007,10 @@ static IrInstSrc *ir_build_bool_to_int(Stage1AstGen *ag, Scope *scope, AstNode *
20072007 return &instruction->base;
20082008}
20092009
2010static IrInstSrc *ir_build_vector_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *len,
2011 IrInstSrc *elem_type)
2010static Stage1ZirInst *ir_build_vector_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *len,
2011 Stage1ZirInst *elem_type)
20122012{
2013 IrInstSrcVectorType *instruction = ir_build_instruction<IrInstSrcVectorType>(ag, scope, source_node);
2013 Stage1ZirInstVectorType *instruction = ir_build_instruction<Stage1ZirInstVectorType>(ag, scope, source_node);
20142014 instruction->len = len;
20152015 instruction->elem_type = elem_type;
20162016
......@@ -2020,10 +2020,10 @@ static IrInstSrc *ir_build_vector_type(Stage1AstGen *ag, Scope *scope, AstNode *
20202020 return &instruction->base;
20212021}
20222022
2023static IrInstSrc *ir_build_shuffle_vector(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2024 IrInstSrc *scalar_type, IrInstSrc *a, IrInstSrc *b, IrInstSrc *mask)
2023static Stage1ZirInst *ir_build_shuffle_vector(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2024 Stage1ZirInst *scalar_type, Stage1ZirInst *a, Stage1ZirInst *b, Stage1ZirInst *mask)
20252025{
2026 IrInstSrcShuffleVector *instruction = ir_build_instruction<IrInstSrcShuffleVector>(ag, scope, source_node);
2026 Stage1ZirInstShuffleVector *instruction = ir_build_instruction<Stage1ZirInstShuffleVector>(ag, scope, source_node);
20272027 instruction->scalar_type = scalar_type;
20282028 instruction->a = a;
20292029 instruction->b = b;
......@@ -2037,10 +2037,10 @@ static IrInstSrc *ir_build_shuffle_vector(Stage1AstGen *ag, Scope *scope, AstNod
20372037 return &instruction->base;
20382038}
20392039
2040static IrInstSrc *ir_build_splat_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2041 IrInstSrc *len, IrInstSrc *scalar)
2040static Stage1ZirInst *ir_build_splat_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2041 Stage1ZirInst *len, Stage1ZirInst *scalar)
20422042{
2043 IrInstSrcSplat *instruction = ir_build_instruction<IrInstSrcSplat>(ag, scope, source_node);
2043 Stage1ZirInstSplat *instruction = ir_build_instruction<Stage1ZirInstSplat>(ag, scope, source_node);
20442044 instruction->len = len;
20452045 instruction->scalar = scalar;
20462046
......@@ -2050,8 +2050,8 @@ static IrInstSrc *ir_build_splat_src(Stage1AstGen *ag, Scope *scope, AstNode *so
20502050 return &instruction->base;
20512051}
20522052
2053static IrInstSrc *ir_build_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) {
2054 IrInstSrcBoolNot *instruction = ir_build_instruction<IrInstSrcBoolNot>(ag, scope, source_node);
2053static Stage1ZirInst *ir_build_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) {
2054 Stage1ZirInstBoolNot *instruction = ir_build_instruction<Stage1ZirInstBoolNot>(ag, scope, source_node);
20552055 instruction->value = value;
20562056
20572057 ir_ref_instruction(value, ag->current_basic_block);
......@@ -2059,10 +2059,10 @@ static IrInstSrc *ir_build_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *sou
20592059 return &instruction->base;
20602060}
20612061
2062static IrInstSrc *ir_build_memset_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2063 IrInstSrc *dest_ptr, IrInstSrc *byte, IrInstSrc *count)
2062static Stage1ZirInst *ir_build_memset_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2063 Stage1ZirInst *dest_ptr, Stage1ZirInst *byte, Stage1ZirInst *count)
20642064{
2065 IrInstSrcMemset *instruction = ir_build_instruction<IrInstSrcMemset>(ag, scope, source_node);
2065 Stage1ZirInstMemset *instruction = ir_build_instruction<Stage1ZirInstMemset>(ag, scope, source_node);
20662066 instruction->dest_ptr = dest_ptr;
20672067 instruction->byte = byte;
20682068 instruction->count = count;
......@@ -2074,10 +2074,10 @@ static IrInstSrc *ir_build_memset_src(Stage1AstGen *ag, Scope *scope, AstNode *s
20742074 return &instruction->base;
20752075}
20762076
2077static IrInstSrc *ir_build_memcpy_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2078 IrInstSrc *dest_ptr, IrInstSrc *src_ptr, IrInstSrc *count)
2077static Stage1ZirInst *ir_build_memcpy_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2078 Stage1ZirInst *dest_ptr, Stage1ZirInst *src_ptr, Stage1ZirInst *count)
20792079{
2080 IrInstSrcMemcpy *instruction = ir_build_instruction<IrInstSrcMemcpy>(ag, scope, source_node);
2080 Stage1ZirInstMemcpy *instruction = ir_build_instruction<Stage1ZirInstMemcpy>(ag, scope, source_node);
20812081 instruction->dest_ptr = dest_ptr;
20822082 instruction->src_ptr = src_ptr;
20832083 instruction->count = count;
......@@ -2089,11 +2089,11 @@ static IrInstSrc *ir_build_memcpy_src(Stage1AstGen *ag, Scope *scope, AstNode *s
20892089 return &instruction->base;
20902090}
20912091
2092static IrInstSrc *ir_build_slice_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2093 IrInstSrc *ptr, IrInstSrc *start, IrInstSrc *end, IrInstSrc *sentinel,
2092static Stage1ZirInst *ir_build_slice_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2093 Stage1ZirInst *ptr, Stage1ZirInst *start, Stage1ZirInst *end, Stage1ZirInst *sentinel,
20942094 bool safety_check_on, ResultLoc *result_loc)
20952095{
2096 IrInstSrcSlice *instruction = ir_build_instruction<IrInstSrcSlice>(ag, scope, source_node);
2096 Stage1ZirInstSlice *instruction = ir_build_instruction<Stage1ZirInstSlice>(ag, scope, source_node);
20972097 instruction->ptr = ptr;
20982098 instruction->start = start;
20992099 instruction->end = end;
......@@ -2109,28 +2109,28 @@ static IrInstSrc *ir_build_slice_src(Stage1AstGen *ag, Scope *scope, AstNode *so
21092109 return &instruction->base;
21102110}
21112111
2112static IrInstSrc *ir_build_breakpoint(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2113 IrInstSrcBreakpoint *instruction = ir_build_instruction<IrInstSrcBreakpoint>(ag, scope, source_node);
2112static Stage1ZirInst *ir_build_breakpoint(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2113 Stage1ZirInstBreakpoint *instruction = ir_build_instruction<Stage1ZirInstBreakpoint>(ag, scope, source_node);
21142114 return &instruction->base;
21152115}
21162116
2117static IrInstSrc *ir_build_return_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2118 IrInstSrcReturnAddress *instruction = ir_build_instruction<IrInstSrcReturnAddress>(ag, scope, source_node);
2117static Stage1ZirInst *ir_build_return_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2118 Stage1ZirInstReturnAddress *instruction = ir_build_instruction<Stage1ZirInstReturnAddress>(ag, scope, source_node);
21192119 return &instruction->base;
21202120}
21212121
2122static IrInstSrc *ir_build_frame_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2123 IrInstSrcFrameAddress *inst = ir_build_instruction<IrInstSrcFrameAddress>(ag, scope, source_node);
2122static Stage1ZirInst *ir_build_frame_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2123 Stage1ZirInstFrameAddress *inst = ir_build_instruction<Stage1ZirInstFrameAddress>(ag, scope, source_node);
21242124 return &inst->base;
21252125}
21262126
2127static IrInstSrc *ir_build_handle_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2128 IrInstSrcFrameHandle *inst = ir_build_instruction<IrInstSrcFrameHandle>(ag, scope, source_node);
2127static Stage1ZirInst *ir_build_handle_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2128 Stage1ZirInstFrameHandle *inst = ir_build_instruction<Stage1ZirInstFrameHandle>(ag, scope, source_node);
21292129 return &inst->base;
21302130}
21312131
2132static IrInstSrc *ir_build_frame_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *fn) {
2133 IrInstSrcFrameType *inst = ir_build_instruction<IrInstSrcFrameType>(ag, scope, source_node);
2132static Stage1ZirInst *ir_build_frame_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *fn) {
2133 Stage1ZirInstFrameType *inst = ir_build_instruction<Stage1ZirInstFrameType>(ag, scope, source_node);
21342134 inst->fn = fn;
21352135
21362136 ir_ref_instruction(fn, ag->current_basic_block);
......@@ -2138,8 +2138,8 @@ static IrInstSrc *ir_build_frame_type(Stage1AstGen *ag, Scope *scope, AstNode *s
21382138 return &inst->base;
21392139}
21402140
2141static IrInstSrc *ir_build_frame_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *fn) {
2142 IrInstSrcFrameSize *inst = ir_build_instruction<IrInstSrcFrameSize>(ag, scope, source_node);
2141static Stage1ZirInst *ir_build_frame_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *fn) {
2142 Stage1ZirInstFrameSize *inst = ir_build_instruction<Stage1ZirInstFrameSize>(ag, scope, source_node);
21432143 inst->fn = fn;
21442144
21452145 ir_ref_instruction(fn, ag->current_basic_block);
......@@ -2147,10 +2147,10 @@ static IrInstSrc *ir_build_frame_size_src(Stage1AstGen *ag, Scope *scope, AstNod
21472147 return &inst->base;
21482148}
21492149
2150static IrInstSrc *ir_build_overflow_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2151 IrOverflowOp op, IrInstSrc *type_value, IrInstSrc *op1, IrInstSrc *op2, IrInstSrc *result_ptr)
2150static Stage1ZirInst *ir_build_overflow_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2151 IrOverflowOp op, Stage1ZirInst *type_value, Stage1ZirInst *op1, Stage1ZirInst *op2, Stage1ZirInst *result_ptr)
21522152{
2153 IrInstSrcOverflowOp *instruction = ir_build_instruction<IrInstSrcOverflowOp>(ag, scope, source_node);
2153 Stage1ZirInstOverflowOp *instruction = ir_build_instruction<Stage1ZirInstOverflowOp>(ag, scope, source_node);
21542154 instruction->op = op;
21552155 instruction->type_value = type_value;
21562156 instruction->op1 = op1;
......@@ -2165,10 +2165,10 @@ static IrInstSrc *ir_build_overflow_op_src(Stage1AstGen *ag, Scope *scope, AstNo
21652165 return &instruction->base;
21662166}
21672167
2168static IrInstSrc *ir_build_float_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *operand,
2168static Stage1ZirInst *ir_build_float_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *operand,
21692169 BuiltinFnId fn_id)
21702170{
2171 IrInstSrcFloatOp *instruction = ir_build_instruction<IrInstSrcFloatOp>(ag, scope, source_node);
2171 Stage1ZirInstFloatOp *instruction = ir_build_instruction<Stage1ZirInstFloatOp>(ag, scope, source_node);
21722172 instruction->operand = operand;
21732173 instruction->fn_id = fn_id;
21742174
......@@ -2177,10 +2177,10 @@ static IrInstSrc *ir_build_float_op_src(Stage1AstGen *ag, Scope *scope, AstNode
21772177 return &instruction->base;
21782178}
21792179
2180static IrInstSrc *ir_build_mul_add_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2181 IrInstSrc *type_value, IrInstSrc *op1, IrInstSrc *op2, IrInstSrc *op3)
2180static Stage1ZirInst *ir_build_mul_add_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2181 Stage1ZirInst *type_value, Stage1ZirInst *op1, Stage1ZirInst *op2, Stage1ZirInst *op3)
21822182{
2183 IrInstSrcMulAdd *instruction = ir_build_instruction<IrInstSrcMulAdd>(ag, scope, source_node);
2183 Stage1ZirInstMulAdd *instruction = ir_build_instruction<Stage1ZirInstMulAdd>(ag, scope, source_node);
21842184 instruction->type_value = type_value;
21852185 instruction->op1 = op1;
21862186 instruction->op2 = op2;
......@@ -2194,8 +2194,8 @@ static IrInstSrc *ir_build_mul_add_src(Stage1AstGen *ag, Scope *scope, AstNode *
21942194 return &instruction->base;
21952195}
21962196
2197static IrInstSrc *ir_build_align_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_value) {
2198 IrInstSrcAlignOf *instruction = ir_build_instruction<IrInstSrcAlignOf>(ag, scope, source_node);
2197static Stage1ZirInst *ir_build_align_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_value) {
2198 Stage1ZirInstAlignOf *instruction = ir_build_instruction<Stage1ZirInstAlignOf>(ag, scope, source_node);
21992199 instruction->type_value = type_value;
22002200
22012201 ir_ref_instruction(type_value, ag->current_basic_block);
......@@ -2203,10 +2203,10 @@ static IrInstSrc *ir_build_align_of(Stage1AstGen *ag, Scope *scope, AstNode *sou
22032203 return &instruction->base;
22042204}
22052205
2206static IrInstSrc *ir_build_test_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2207 IrInstSrc *base_ptr, bool resolve_err_set, bool base_ptr_is_payload)
2206static Stage1ZirInst *ir_build_test_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2207 Stage1ZirInst *base_ptr, bool resolve_err_set, bool base_ptr_is_payload)
22082208{
2209 IrInstSrcTestErr *instruction = ir_build_instruction<IrInstSrcTestErr>(ag, scope, source_node);
2209 Stage1ZirInstTestErr *instruction = ir_build_instruction<Stage1ZirInstTestErr>(ag, scope, source_node);
22102210 instruction->base_ptr = base_ptr;
22112211 instruction->resolve_err_set = resolve_err_set;
22122212 instruction->base_ptr_is_payload = base_ptr_is_payload;
......@@ -2216,10 +2216,10 @@ static IrInstSrc *ir_build_test_err_src(Stage1AstGen *ag, Scope *scope, AstNode
22162216 return &instruction->base;
22172217}
22182218
2219static IrInstSrc *ir_build_unwrap_err_code_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2220 IrInstSrc *err_union_ptr)
2219static Stage1ZirInst *ir_build_unwrap_err_code_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2220 Stage1ZirInst *err_union_ptr)
22212221{
2222 IrInstSrcUnwrapErrCode *inst = ir_build_instruction<IrInstSrcUnwrapErrCode>(ag, scope, source_node);
2222 Stage1ZirInstUnwrapErrCode *inst = ir_build_instruction<Stage1ZirInstUnwrapErrCode>(ag, scope, source_node);
22232223 inst->err_union_ptr = err_union_ptr;
22242224
22252225 ir_ref_instruction(err_union_ptr, ag->current_basic_block);
......@@ -2227,10 +2227,10 @@ static IrInstSrc *ir_build_unwrap_err_code_src(Stage1AstGen *ag, Scope *scope, A
22272227 return &inst->base;
22282228}
22292229
2230static IrInstSrc *ir_build_unwrap_err_payload_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2231 IrInstSrc *value, bool safety_check_on, bool initializing)
2230static Stage1ZirInst *ir_build_unwrap_err_payload_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2231 Stage1ZirInst *value, bool safety_check_on, bool initializing)
22322232{
2233 IrInstSrcUnwrapErrPayload *inst = ir_build_instruction<IrInstSrcUnwrapErrPayload>(ag, scope, source_node);
2233 Stage1ZirInstUnwrapErrPayload *inst = ir_build_instruction<Stage1ZirInstUnwrapErrPayload>(ag, scope, source_node);
22342234 inst->value = value;
22352235 inst->safety_check_on = safety_check_on;
22362236 inst->initializing = initializing;
......@@ -2240,11 +2240,11 @@ static IrInstSrc *ir_build_unwrap_err_payload_src(Stage1AstGen *ag, Scope *scope
22402240 return &inst->base;
22412241}
22422242
2243static IrInstSrc *ir_build_fn_proto(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2244 IrInstSrc **param_types, IrInstSrc *align_value, IrInstSrc *callconv_value,
2245 IrInstSrc *return_type, bool is_var_args)
2243static Stage1ZirInst *ir_build_fn_proto(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2244 Stage1ZirInst **param_types, Stage1ZirInst *align_value, Stage1ZirInst *callconv_value,
2245 Stage1ZirInst *return_type, bool is_var_args)
22462246{
2247 IrInstSrcFnProto *instruction = ir_build_instruction<IrInstSrcFnProto>(ag, scope, source_node);
2247 Stage1ZirInstFnProto *instruction = ir_build_instruction<Stage1ZirInstFnProto>(ag, scope, source_node);
22482248 instruction->param_types = param_types;
22492249 instruction->align_value = align_value;
22502250 instruction->callconv_value = callconv_value;
......@@ -2264,8 +2264,8 @@ static IrInstSrc *ir_build_fn_proto(Stage1AstGen *ag, Scope *scope, AstNode *sou
22642264 return &instruction->base;
22652265}
22662266
2267static IrInstSrc *ir_build_test_comptime(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) {
2268 IrInstSrcTestComptime *instruction = ir_build_instruction<IrInstSrcTestComptime>(ag, scope, source_node);
2267static Stage1ZirInst *ir_build_test_comptime(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) {
2268 Stage1ZirInstTestComptime *instruction = ir_build_instruction<Stage1ZirInstTestComptime>(ag, scope, source_node);
22692269 instruction->value = value;
22702270
22712271 ir_ref_instruction(value, ag->current_basic_block);
......@@ -2273,10 +2273,10 @@ static IrInstSrc *ir_build_test_comptime(Stage1AstGen *ag, Scope *scope, AstNode
22732273 return &instruction->base;
22742274}
22752275
2276static IrInstSrc *ir_build_ptr_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2277 IrInstSrc *dest_type, IrInstSrc *ptr, bool safety_check_on)
2276static Stage1ZirInst *ir_build_ptr_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2277 Stage1ZirInst *dest_type, Stage1ZirInst *ptr, bool safety_check_on)
22782278{
2279 IrInstSrcPtrCast *instruction = ir_build_instruction<IrInstSrcPtrCast>(
2279 Stage1ZirInstPtrCast *instruction = ir_build_instruction<Stage1ZirInstPtrCast>(
22802280 ag, scope, source_node);
22812281 instruction->dest_type = dest_type;
22822282 instruction->ptr = ptr;
......@@ -2288,10 +2288,10 @@ static IrInstSrc *ir_build_ptr_cast_src(Stage1AstGen *ag, Scope *scope, AstNode
22882288 return &instruction->base;
22892289}
22902290
2291static IrInstSrc *ir_build_implicit_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2292 IrInstSrc *operand, ResultLocCast *result_loc_cast)
2291static Stage1ZirInst *ir_build_implicit_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2292 Stage1ZirInst *operand, ResultLocCast *result_loc_cast)
22932293{
2294 IrInstSrcImplicitCast *instruction = ir_build_instruction<IrInstSrcImplicitCast>(ag, scope, source_node);
2294 Stage1ZirInstImplicitCast *instruction = ir_build_instruction<Stage1ZirInstImplicitCast>(ag, scope, source_node);
22952295 instruction->operand = operand;
22962296 instruction->result_loc_cast = result_loc_cast;
22972297
......@@ -2300,10 +2300,10 @@ static IrInstSrc *ir_build_implicit_cast(Stage1AstGen *ag, Scope *scope, AstNode
23002300 return &instruction->base;
23012301}
23022302
2303static IrInstSrc *ir_build_bit_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2304 IrInstSrc *operand, ResultLocBitCast *result_loc_bit_cast)
2303static Stage1ZirInst *ir_build_bit_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2304 Stage1ZirInst *operand, ResultLocBitCast *result_loc_bit_cast)
23052305{
2306 IrInstSrcBitCast *instruction = ir_build_instruction<IrInstSrcBitCast>(ag, scope, source_node);
2306 Stage1ZirInstBitCast *instruction = ir_build_instruction<Stage1ZirInstBitCast>(ag, scope, source_node);
23072307 instruction->operand = operand;
23082308 instruction->result_loc_bit_cast = result_loc_bit_cast;
23092309
......@@ -2312,10 +2312,10 @@ static IrInstSrc *ir_build_bit_cast_src(Stage1AstGen *ag, Scope *scope, AstNode
23122312 return &instruction->base;
23132313}
23142314
2315static IrInstSrc *ir_build_int_to_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2316 IrInstSrc *dest_type, IrInstSrc *target)
2315static Stage1ZirInst *ir_build_int_to_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2316 Stage1ZirInst *dest_type, Stage1ZirInst *target)
23172317{
2318 IrInstSrcIntToPtr *instruction = ir_build_instruction<IrInstSrcIntToPtr>(ag, scope, source_node);
2318 Stage1ZirInstIntToPtr *instruction = ir_build_instruction<Stage1ZirInstIntToPtr>(ag, scope, source_node);
23192319 instruction->dest_type = dest_type;
23202320 instruction->target = target;
23212321
......@@ -2325,10 +2325,10 @@ static IrInstSrc *ir_build_int_to_ptr_src(Stage1AstGen *ag, Scope *scope, AstNod
23252325 return &instruction->base;
23262326}
23272327
2328static IrInstSrc *ir_build_ptr_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2329 IrInstSrc *target)
2328static Stage1ZirInst *ir_build_ptr_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2329 Stage1ZirInst *target)
23302330{
2331 IrInstSrcPtrToInt *inst = ir_build_instruction<IrInstSrcPtrToInt>(ag, scope, source_node);
2331 Stage1ZirInstPtrToInt *inst = ir_build_instruction<Stage1ZirInstPtrToInt>(ag, scope, source_node);
23322332 inst->target = target;
23332333
23342334 ir_ref_instruction(target, ag->current_basic_block);
......@@ -2336,10 +2336,10 @@ static IrInstSrc *ir_build_ptr_to_int_src(Stage1AstGen *ag, Scope *scope, AstNod
23362336 return &inst->base;
23372337}
23382338
2339static IrInstSrc *ir_build_int_to_enum_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2340 IrInstSrc *dest_type, IrInstSrc *target)
2339static Stage1ZirInst *ir_build_int_to_enum_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2340 Stage1ZirInst *dest_type, Stage1ZirInst *target)
23412341{
2342 IrInstSrcIntToEnum *instruction = ir_build_instruction<IrInstSrcIntToEnum>(ag, scope, source_node);
2342 Stage1ZirInstIntToEnum *instruction = ir_build_instruction<Stage1ZirInstIntToEnum>(ag, scope, source_node);
23432343 instruction->dest_type = dest_type;
23442344 instruction->target = target;
23452345
......@@ -2349,10 +2349,10 @@ static IrInstSrc *ir_build_int_to_enum_src(Stage1AstGen *ag, Scope *scope, AstNo
23492349 return &instruction->base;
23502350}
23512351
2352static IrInstSrc *ir_build_enum_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2353 IrInstSrc *target)
2352static Stage1ZirInst *ir_build_enum_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2353 Stage1ZirInst *target)
23542354{
2355 IrInstSrcEnumToInt *instruction = ir_build_instruction<IrInstSrcEnumToInt>(
2355 Stage1ZirInstEnumToInt *instruction = ir_build_instruction<Stage1ZirInstEnumToInt>(
23562356 ag, scope, source_node);
23572357 instruction->target = target;
23582358
......@@ -2361,10 +2361,10 @@ static IrInstSrc *ir_build_enum_to_int(Stage1AstGen *ag, Scope *scope, AstNode *
23612361 return &instruction->base;
23622362}
23632363
2364static IrInstSrc *ir_build_int_to_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2365 IrInstSrc *target)
2364static Stage1ZirInst *ir_build_int_to_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2365 Stage1ZirInst *target)
23662366{
2367 IrInstSrcIntToErr *instruction = ir_build_instruction<IrInstSrcIntToErr>(ag, scope, source_node);
2367 Stage1ZirInstIntToErr *instruction = ir_build_instruction<Stage1ZirInstIntToErr>(ag, scope, source_node);
23682368 instruction->target = target;
23692369
23702370 ir_ref_instruction(target, ag->current_basic_block);
......@@ -2372,10 +2372,10 @@ static IrInstSrc *ir_build_int_to_err_src(Stage1AstGen *ag, Scope *scope, AstNod
23722372 return &instruction->base;
23732373}
23742374
2375static IrInstSrc *ir_build_err_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2376 IrInstSrc *target)
2375static Stage1ZirInst *ir_build_err_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2376 Stage1ZirInst *target)
23772377{
2378 IrInstSrcErrToInt *instruction = ir_build_instruction<IrInstSrcErrToInt>(
2378 Stage1ZirInstErrToInt *instruction = ir_build_instruction<Stage1ZirInstErrToInt>(
23792379 ag, scope, source_node);
23802380 instruction->target = target;
23812381
......@@ -2384,13 +2384,13 @@ static IrInstSrc *ir_build_err_to_int_src(Stage1AstGen *ag, Scope *scope, AstNod
23842384 return &instruction->base;
23852385}
23862386
2387static IrInstSrc *ir_build_check_switch_prongs(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2388 IrInstSrc *target_value, IrInstSrcCheckSwitchProngsRange *ranges, size_t range_count,
2387static Stage1ZirInst *ir_build_check_switch_prongs(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2388 Stage1ZirInst *target_value, Stage1ZirInstCheckSwitchProngsRange *ranges, size_t range_count,
23892389 AstNode* else_prong, bool have_underscore_prong)
23902390{
2391 IrInstSrcCheckSwitchProngs *instruction = heap::c_allocator.create<IrInstSrcCheckSwitchProngs>();
2391 Stage1ZirInstCheckSwitchProngs *instruction = heap::c_allocator.create<Stage1ZirInstCheckSwitchProngs>();
23922392 instruction->base.id = have_underscore_prong ?
2393 IrInstSrcIdCheckSwitchProngsUnderYes : IrInstSrcIdCheckSwitchProngsUnderNo;
2393 Stage1ZirInstIdCheckSwitchProngsUnderYes : Stage1ZirInstIdCheckSwitchProngsUnderNo;
23942394 instruction->base.scope = scope;
23952395 instruction->base.source_node = source_node;
23962396 instruction->base.debug_id = irb_next_debug_id(ag);
......@@ -2411,10 +2411,10 @@ static IrInstSrc *ir_build_check_switch_prongs(Stage1AstGen *ag, Scope *scope, A
24112411 return &instruction->base;
24122412}
24132413
2414static IrInstSrc *ir_build_check_statement_is_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2415 IrInstSrc* statement_value)
2414static Stage1ZirInst *ir_build_check_statement_is_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2415 Stage1ZirInst* statement_value)
24162416{
2417 IrInstSrcCheckStatementIsVoid *instruction = ir_build_instruction<IrInstSrcCheckStatementIsVoid>(
2417 Stage1ZirInstCheckStatementIsVoid *instruction = ir_build_instruction<Stage1ZirInstCheckStatementIsVoid>(
24182418 ag, scope, source_node);
24192419 instruction->statement_value = statement_value;
24202420
......@@ -2423,10 +2423,10 @@ static IrInstSrc *ir_build_check_statement_is_void(Stage1AstGen *ag, Scope *scop
24232423 return &instruction->base;
24242424}
24252425
2426static IrInstSrc *ir_build_type_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2427 IrInstSrc *type_value)
2426static Stage1ZirInst *ir_build_type_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2427 Stage1ZirInst *type_value)
24282428{
2429 IrInstSrcTypeName *instruction = ir_build_instruction<IrInstSrcTypeName>(ag, scope, source_node);
2429 Stage1ZirInstTypeName *instruction = ir_build_instruction<Stage1ZirInstTypeName>(ag, scope, source_node);
24302430 instruction->type_value = type_value;
24312431
24322432 ir_ref_instruction(type_value, ag->current_basic_block);
......@@ -2434,16 +2434,16 @@ static IrInstSrc *ir_build_type_name(Stage1AstGen *ag, Scope *scope, AstNode *so
24342434 return &instruction->base;
24352435}
24362436
2437static IrInstSrc *ir_build_decl_ref(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Tld *tld, LVal lval) {
2438 IrInstSrcDeclRef *instruction = ir_build_instruction<IrInstSrcDeclRef>(ag, scope, source_node);
2437static Stage1ZirInst *ir_build_decl_ref(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Tld *tld, LVal lval) {
2438 Stage1ZirInstDeclRef *instruction = ir_build_instruction<Stage1ZirInstDeclRef>(ag, scope, source_node);
24392439 instruction->tld = tld;
24402440 instruction->lval = lval;
24412441
24422442 return &instruction->base;
24432443}
24442444
2445static IrInstSrc *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *msg) {
2446 IrInstSrcPanic *instruction = ir_build_instruction<IrInstSrcPanic>(ag, scope, source_node);
2445static Stage1ZirInst *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *msg) {
2446 Stage1ZirInstPanic *instruction = ir_build_instruction<Stage1ZirInstPanic>(ag, scope, source_node);
24472447 instruction->msg = msg;
24482448
24492449 ir_ref_instruction(msg, ag->current_basic_block);
......@@ -2451,8 +2451,8 @@ static IrInstSrc *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *so
24512451 return &instruction->base;
24522452}
24532453
2454static IrInstSrc *ir_build_tag_name_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *target) {
2455 IrInstSrcTagName *instruction = ir_build_instruction<IrInstSrcTagName>(ag, scope, source_node);
2454static Stage1ZirInst *ir_build_tag_name_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *target) {
2455 Stage1ZirInstTagName *instruction = ir_build_instruction<Stage1ZirInstTagName>(ag, scope, source_node);
24562456 instruction->target = target;
24572457
24582458 ir_ref_instruction(target, ag->current_basic_block);
......@@ -2460,10 +2460,10 @@ static IrInstSrc *ir_build_tag_name_src(Stage1AstGen *ag, Scope *scope, AstNode
24602460 return &instruction->base;
24612461}
24622462
2463static IrInstSrc *ir_build_field_parent_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2464 IrInstSrc *type_value, IrInstSrc *field_name, IrInstSrc *field_ptr)
2463static Stage1ZirInst *ir_build_field_parent_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2464 Stage1ZirInst *type_value, Stage1ZirInst *field_name, Stage1ZirInst *field_ptr)
24652465{
2466 IrInstSrcFieldParentPtr *inst = ir_build_instruction<IrInstSrcFieldParentPtr>(
2466 Stage1ZirInstFieldParentPtr *inst = ir_build_instruction<Stage1ZirInstFieldParentPtr>(
24672467 ag, scope, source_node);
24682468 inst->type_value = type_value;
24692469 inst->field_name = field_name;
......@@ -2476,10 +2476,10 @@ static IrInstSrc *ir_build_field_parent_ptr_src(Stage1AstGen *ag, Scope *scope,
24762476 return &inst->base;
24772477}
24782478
2479static IrInstSrc *ir_build_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2480 IrInstSrc *type_value, IrInstSrc *field_name)
2479static Stage1ZirInst *ir_build_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2480 Stage1ZirInst *type_value, Stage1ZirInst *field_name)
24812481{
2482 IrInstSrcOffsetOf *instruction = ir_build_instruction<IrInstSrcOffsetOf>(ag, scope, source_node);
2482 Stage1ZirInstOffsetOf *instruction = ir_build_instruction<Stage1ZirInstOffsetOf>(ag, scope, source_node);
24832483 instruction->type_value = type_value;
24842484 instruction->field_name = field_name;
24852485
......@@ -2489,10 +2489,10 @@ static IrInstSrc *ir_build_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *so
24892489 return &instruction->base;
24902490}
24912491
2492static IrInstSrc *ir_build_bit_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2493 IrInstSrc *type_value, IrInstSrc *field_name)
2492static Stage1ZirInst *ir_build_bit_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2493 Stage1ZirInst *type_value, Stage1ZirInst *field_name)
24942494{
2495 IrInstSrcBitOffsetOf *instruction = ir_build_instruction<IrInstSrcBitOffsetOf>(ag, scope, source_node);
2495 Stage1ZirInstBitOffsetOf *instruction = ir_build_instruction<Stage1ZirInstBitOffsetOf>(ag, scope, source_node);
24962496 instruction->type_value = type_value;
24972497 instruction->field_name = field_name;
24982498
......@@ -2502,8 +2502,8 @@ static IrInstSrc *ir_build_bit_offset_of(Stage1AstGen *ag, Scope *scope, AstNode
25022502 return &instruction->base;
25032503}
25042504
2505static IrInstSrc *ir_build_type_info(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_value) {
2506 IrInstSrcTypeInfo *instruction = ir_build_instruction<IrInstSrcTypeInfo>(ag, scope, source_node);
2505static Stage1ZirInst *ir_build_type_info(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_value) {
2506 Stage1ZirInstTypeInfo *instruction = ir_build_instruction<Stage1ZirInstTypeInfo>(ag, scope, source_node);
25072507 instruction->type_value = type_value;
25082508
25092509 ir_ref_instruction(type_value, ag->current_basic_block);
......@@ -2511,8 +2511,8 @@ static IrInstSrc *ir_build_type_info(Stage1AstGen *ag, Scope *scope, AstNode *so
25112511 return &instruction->base;
25122512}
25132513
2514static IrInstSrc *ir_build_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_info) {
2515 IrInstSrcType *instruction = ir_build_instruction<IrInstSrcType>(ag, scope, source_node);
2514static Stage1ZirInst *ir_build_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_info) {
2515 Stage1ZirInstType *instruction = ir_build_instruction<Stage1ZirInstType>(ag, scope, source_node);
25162516 instruction->type_info = type_info;
25172517
25182518 ir_ref_instruction(type_info, ag->current_basic_block);
......@@ -2520,10 +2520,10 @@ static IrInstSrc *ir_build_type(Stage1AstGen *ag, Scope *scope, AstNode *source_
25202520 return &instruction->base;
25212521}
25222522
2523static IrInstSrc *ir_build_set_eval_branch_quota(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2524 IrInstSrc *new_quota)
2523static Stage1ZirInst *ir_build_set_eval_branch_quota(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2524 Stage1ZirInst *new_quota)
25252525{
2526 IrInstSrcSetEvalBranchQuota *instruction = ir_build_instruction<IrInstSrcSetEvalBranchQuota>(ag, scope, source_node);
2526 Stage1ZirInstSetEvalBranchQuota *instruction = ir_build_instruction<Stage1ZirInstSetEvalBranchQuota>(ag, scope, source_node);
25272527 instruction->new_quota = new_quota;
25282528
25292529 ir_ref_instruction(new_quota, ag->current_basic_block);
......@@ -2531,10 +2531,10 @@ static IrInstSrc *ir_build_set_eval_branch_quota(Stage1AstGen *ag, Scope *scope,
25312531 return &instruction->base;
25322532}
25332533
2534static IrInstSrc *ir_build_align_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2535 IrInstSrc *align_bytes, IrInstSrc *target)
2534static Stage1ZirInst *ir_build_align_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2535 Stage1ZirInst *align_bytes, Stage1ZirInst *target)
25362536{
2537 IrInstSrcAlignCast *instruction = ir_build_instruction<IrInstSrcAlignCast>(ag, scope, source_node);
2537 Stage1ZirInstAlignCast *instruction = ir_build_instruction<Stage1ZirInstAlignCast>(ag, scope, source_node);
25382538 instruction->align_bytes = align_bytes;
25392539 instruction->target = target;
25402540
......@@ -2544,10 +2544,10 @@ static IrInstSrc *ir_build_align_cast_src(Stage1AstGen *ag, Scope *scope, AstNod
25442544 return &instruction->base;
25452545}
25462546
2547static IrInstSrc *ir_build_resolve_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2548 ResultLoc *result_loc, IrInstSrc *ty)
2547static Stage1ZirInst *ir_build_resolve_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2548 ResultLoc *result_loc, Stage1ZirInst *ty)
25492549{
2550 IrInstSrcResolveResult *instruction = ir_build_instruction<IrInstSrcResolveResult>(ag, scope, source_node);
2550 Stage1ZirInstResolveResult *instruction = ir_build_instruction<Stage1ZirInstResolveResult>(ag, scope, source_node);
25512551 instruction->result_loc = result_loc;
25522552 instruction->ty = ty;
25532553
......@@ -2556,19 +2556,19 @@ static IrInstSrc *ir_build_resolve_result(Stage1AstGen *ag, Scope *scope, AstNod
25562556 return &instruction->base;
25572557}
25582558
2559static IrInstSrc *ir_build_reset_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2559static Stage1ZirInst *ir_build_reset_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
25602560 ResultLoc *result_loc)
25612561{
2562 IrInstSrcResetResult *instruction = ir_build_instruction<IrInstSrcResetResult>(ag, scope, source_node);
2562 Stage1ZirInstResetResult *instruction = ir_build_instruction<Stage1ZirInstResetResult>(ag, scope, source_node);
25632563 instruction->result_loc = result_loc;
25642564
25652565 return &instruction->base;
25662566}
25672567
2568static IrInstSrc *ir_build_set_align_stack(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2569 IrInstSrc *align_bytes)
2568static Stage1ZirInst *ir_build_set_align_stack(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2569 Stage1ZirInst *align_bytes)
25702570{
2571 IrInstSrcSetAlignStack *instruction = ir_build_instruction<IrInstSrcSetAlignStack>(ag, scope, source_node);
2571 Stage1ZirInstSetAlignStack *instruction = ir_build_instruction<Stage1ZirInstSetAlignStack>(ag, scope, source_node);
25722572 instruction->align_bytes = align_bytes;
25732573
25742574 ir_ref_instruction(align_bytes, ag->current_basic_block);
......@@ -2576,12 +2576,12 @@ static IrInstSrc *ir_build_set_align_stack(Stage1AstGen *ag, Scope *scope, AstNo
25762576 return &instruction->base;
25772577}
25782578
2579static IrInstSrc *ir_build_arg_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2580 IrInstSrc *fn_type, IrInstSrc *arg_index, bool allow_var)
2579static Stage1ZirInst *ir_build_arg_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2580 Stage1ZirInst *fn_type, Stage1ZirInst *arg_index, bool allow_var)
25812581{
2582 IrInstSrcArgType *instruction = heap::c_allocator.create<IrInstSrcArgType>();
2582 Stage1ZirInstArgType *instruction = heap::c_allocator.create<Stage1ZirInstArgType>();
25832583 instruction->base.id = allow_var ?
2584 IrInstSrcIdArgTypeAllowVarTrue : IrInstSrcIdArgTypeAllowVarFalse;
2584 Stage1ZirInstIdArgTypeAllowVarTrue : Stage1ZirInstIdArgTypeAllowVarFalse;
25852585 instruction->base.scope = scope;
25862586 instruction->base.source_node = source_node;
25872587 instruction->base.debug_id = irb_next_debug_id(ag);
......@@ -2597,19 +2597,19 @@ static IrInstSrc *ir_build_arg_type(Stage1AstGen *ag, Scope *scope, AstNode *sou
25972597 return &instruction->base;
25982598}
25992599
2600static IrInstSrc *ir_build_error_return_trace_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2600static Stage1ZirInst *ir_build_error_return_trace_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
26012601 IrInstErrorReturnTraceOptional optional)
26022602{
2603 IrInstSrcErrorReturnTrace *inst = ir_build_instruction<IrInstSrcErrorReturnTrace>(ag, scope, source_node);
2603 Stage1ZirInstErrorReturnTrace *inst = ir_build_instruction<Stage1ZirInstErrorReturnTrace>(ag, scope, source_node);
26042604 inst->optional = optional;
26052605
26062606 return &inst->base;
26072607}
26082608
2609static IrInstSrc *ir_build_error_union(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2610 IrInstSrc *err_set, IrInstSrc *payload)
2609static Stage1ZirInst *ir_build_error_union(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2610 Stage1ZirInst *err_set, Stage1ZirInst *payload)
26112611{
2612 IrInstSrcErrorUnion *instruction = ir_build_instruction<IrInstSrcErrorUnion>(ag, scope, source_node);
2612 Stage1ZirInstErrorUnion *instruction = ir_build_instruction<Stage1ZirInstErrorUnion>(ag, scope, source_node);
26132613 instruction->err_set = err_set;
26142614 instruction->payload = payload;
26152615
......@@ -2619,11 +2619,11 @@ static IrInstSrc *ir_build_error_union(Stage1AstGen *ag, Scope *scope, AstNode *
26192619 return &instruction->base;
26202620}
26212621
2622static IrInstSrc *ir_build_atomic_rmw_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2623 IrInstSrc *operand_type, IrInstSrc *ptr, IrInstSrc *op, IrInstSrc *operand,
2624 IrInstSrc *ordering)
2622static Stage1ZirInst *ir_build_atomic_rmw_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2623 Stage1ZirInst *operand_type, Stage1ZirInst *ptr, Stage1ZirInst *op, Stage1ZirInst *operand,
2624 Stage1ZirInst *ordering)
26252625{
2626 IrInstSrcAtomicRmw *instruction = ir_build_instruction<IrInstSrcAtomicRmw>(ag, scope, source_node);
2626 Stage1ZirInstAtomicRmw *instruction = ir_build_instruction<Stage1ZirInstAtomicRmw>(ag, scope, source_node);
26272627 instruction->operand_type = operand_type;
26282628 instruction->ptr = ptr;
26292629 instruction->op = op;
......@@ -2639,10 +2639,10 @@ static IrInstSrc *ir_build_atomic_rmw_src(Stage1AstGen *ag, Scope *scope, AstNod
26392639 return &instruction->base;
26402640}
26412641
2642static IrInstSrc *ir_build_atomic_load_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2643 IrInstSrc *operand_type, IrInstSrc *ptr, IrInstSrc *ordering)
2642static Stage1ZirInst *ir_build_atomic_load_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2643 Stage1ZirInst *operand_type, Stage1ZirInst *ptr, Stage1ZirInst *ordering)
26442644{
2645 IrInstSrcAtomicLoad *instruction = ir_build_instruction<IrInstSrcAtomicLoad>(ag, scope, source_node);
2645 Stage1ZirInstAtomicLoad *instruction = ir_build_instruction<Stage1ZirInstAtomicLoad>(ag, scope, source_node);
26462646 instruction->operand_type = operand_type;
26472647 instruction->ptr = ptr;
26482648 instruction->ordering = ordering;
......@@ -2654,10 +2654,10 @@ static IrInstSrc *ir_build_atomic_load_src(Stage1AstGen *ag, Scope *scope, AstNo
26542654 return &instruction->base;
26552655}
26562656
2657static IrInstSrc *ir_build_atomic_store_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2658 IrInstSrc *operand_type, IrInstSrc *ptr, IrInstSrc *value, IrInstSrc *ordering)
2657static Stage1ZirInst *ir_build_atomic_store_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2658 Stage1ZirInst *operand_type, Stage1ZirInst *ptr, Stage1ZirInst *value, Stage1ZirInst *ordering)
26592659{
2660 IrInstSrcAtomicStore *instruction = ir_build_instruction<IrInstSrcAtomicStore>(ag, scope, source_node);
2660 Stage1ZirInstAtomicStore *instruction = ir_build_instruction<Stage1ZirInstAtomicStore>(ag, scope, source_node);
26612661 instruction->operand_type = operand_type;
26622662 instruction->ptr = ptr;
26632663 instruction->value = value;
......@@ -2671,15 +2671,15 @@ static IrInstSrc *ir_build_atomic_store_src(Stage1AstGen *ag, Scope *scope, AstN
26712671 return &instruction->base;
26722672}
26732673
2674static IrInstSrc *ir_build_save_err_ret_addr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2675 IrInstSrcSaveErrRetAddr *inst = ir_build_instruction<IrInstSrcSaveErrRetAddr>(ag, scope, source_node);
2674static Stage1ZirInst *ir_build_save_err_ret_addr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2675 Stage1ZirInstSaveErrRetAddr *inst = ir_build_instruction<Stage1ZirInstSaveErrRetAddr>(ag, scope, source_node);
26762676 return &inst->base;
26772677}
26782678
2679static IrInstSrc *ir_build_add_implicit_return_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2680 IrInstSrc *value, ResultLocReturn *result_loc_ret)
2679static Stage1ZirInst *ir_build_add_implicit_return_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2680 Stage1ZirInst *value, ResultLocReturn *result_loc_ret)
26812681{
2682 IrInstSrcAddImplicitReturnType *inst = ir_build_instruction<IrInstSrcAddImplicitReturnType>(ag, scope, source_node);
2682 Stage1ZirInstAddImplicitReturnType *inst = ir_build_instruction<Stage1ZirInstAddImplicitReturnType>(ag, scope, source_node);
26832683 inst->value = value;
26842684 inst->result_loc_ret = result_loc_ret;
26852685
......@@ -2688,10 +2688,10 @@ static IrInstSrc *ir_build_add_implicit_return_type(Stage1AstGen *ag, Scope *sco
26882688 return &inst->base;
26892689}
26902690
2691static IrInstSrc *ir_build_has_decl(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2692 IrInstSrc *container, IrInstSrc *name)
2691static Stage1ZirInst *ir_build_has_decl(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2692 Stage1ZirInst *container, Stage1ZirInst *name)
26932693{
2694 IrInstSrcHasDecl *instruction = ir_build_instruction<IrInstSrcHasDecl>(ag, scope, source_node);
2694 Stage1ZirInstHasDecl *instruction = ir_build_instruction<Stage1ZirInstHasDecl>(ag, scope, source_node);
26952695 instruction->container = container;
26962696 instruction->name = name;
26972697
......@@ -2701,15 +2701,15 @@ static IrInstSrc *ir_build_has_decl(Stage1AstGen *ag, Scope *scope, AstNode *sou
27012701 return &instruction->base;
27022702}
27032703
2704static IrInstSrc *ir_build_undeclared_identifier(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) {
2705 IrInstSrcUndeclaredIdent *instruction = ir_build_instruction<IrInstSrcUndeclaredIdent>(ag, scope, source_node);
2704static Stage1ZirInst *ir_build_undeclared_identifier(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) {
2705 Stage1ZirInstUndeclaredIdent *instruction = ir_build_instruction<Stage1ZirInstUndeclaredIdent>(ag, scope, source_node);
27062706 instruction->name = name;
27072707
27082708 return &instruction->base;
27092709}
27102710
2711static IrInstSrc *ir_build_check_runtime_scope(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *scope_is_comptime, IrInstSrc *is_comptime) {
2712 IrInstSrcCheckRuntimeScope *instruction = ir_build_instruction<IrInstSrcCheckRuntimeScope>(ag, scope, source_node);
2711static Stage1ZirInst *ir_build_check_runtime_scope(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *scope_is_comptime, Stage1ZirInst *is_comptime) {
2712 Stage1ZirInstCheckRuntimeScope *instruction = ir_build_instruction<Stage1ZirInstCheckRuntimeScope>(ag, scope, source_node);
27132713 instruction->scope_is_comptime = scope_is_comptime;
27142714 instruction->is_comptime = is_comptime;
27152715
......@@ -2719,10 +2719,10 @@ static IrInstSrc *ir_build_check_runtime_scope(Stage1AstGen *ag, Scope *scope, A
27192719 return &instruction->base;
27202720}
27212721
2722static IrInstSrc *ir_build_union_init_named_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2723 IrInstSrc *union_type, IrInstSrc *field_name, IrInstSrc *field_result_loc, IrInstSrc *result_loc)
2722static Stage1ZirInst *ir_build_union_init_named_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2723 Stage1ZirInst *union_type, Stage1ZirInst *field_name, Stage1ZirInst *field_result_loc, Stage1ZirInst *result_loc)
27242724{
2725 IrInstSrcUnionInitNamedField *instruction = ir_build_instruction<IrInstSrcUnionInitNamedField>(ag, scope, source_node);
2725 Stage1ZirInstUnionInitNamedField *instruction = ir_build_instruction<Stage1ZirInstUnionInitNamedField>(ag, scope, source_node);
27262726 instruction->union_type = union_type;
27272727 instruction->field_name = field_name;
27282728 instruction->field_result_loc = field_result_loc;
......@@ -2736,10 +2736,10 @@ static IrInstSrc *ir_build_union_init_named_field(Stage1AstGen *ag, Scope *scope
27362736 return &instruction->base;
27372737}
27382738
2739static IrInstSrc *ir_build_alloca_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2740 IrInstSrc *align, const char *name_hint, IrInstSrc *is_comptime)
2739static Stage1ZirInst *ir_build_alloca_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2740 Stage1ZirInst *align, const char *name_hint, Stage1ZirInst *is_comptime)
27412741{
2742 IrInstSrcAlloca *instruction = ir_build_instruction<IrInstSrcAlloca>(ag, scope, source_node);
2742 Stage1ZirInstAlloca *instruction = ir_build_instruction<Stage1ZirInstAlloca>(ag, scope, source_node);
27432743 instruction->align = align;
27442744 instruction->name_hint = name_hint;
27452745 instruction->is_comptime = is_comptime;
......@@ -2750,10 +2750,10 @@ static IrInstSrc *ir_build_alloca_src(Stage1AstGen *ag, Scope *scope, AstNode *s
27502750 return &instruction->base;
27512751}
27522752
2753static IrInstSrc *ir_build_end_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2754 IrInstSrc *value, ResultLoc *result_loc)
2753static Stage1ZirInst *ir_build_end_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2754 Stage1ZirInst *value, ResultLoc *result_loc)
27552755{
2756 IrInstSrcEndExpr *instruction = ir_build_instruction<IrInstSrcEndExpr>(ag, scope, source_node);
2756 Stage1ZirInstEndExpr *instruction = ir_build_instruction<Stage1ZirInstEndExpr>(ag, scope, source_node);
27572757 instruction->value = value;
27582758 instruction->result_loc = result_loc;
27592759
......@@ -2762,14 +2762,14 @@ static IrInstSrc *ir_build_end_expr(Stage1AstGen *ag, Scope *scope, AstNode *sou
27622762 return &instruction->base;
27632763}
27642764
2765static IrInstSrcSuspendBegin *ir_build_suspend_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2766 return ir_build_instruction<IrInstSrcSuspendBegin>(ag, scope, source_node);
2765static Stage1ZirInstSuspendBegin *ir_build_suspend_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2766 return ir_build_instruction<Stage1ZirInstSuspendBegin>(ag, scope, source_node);
27672767}
27682768
2769static IrInstSrc *ir_build_suspend_finish_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2770 IrInstSrcSuspendBegin *begin)
2769static Stage1ZirInst *ir_build_suspend_finish_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2770 Stage1ZirInstSuspendBegin *begin)
27712771{
2772 IrInstSrcSuspendFinish *inst = ir_build_instruction<IrInstSrcSuspendFinish>(ag, scope, source_node);
2772 Stage1ZirInstSuspendFinish *inst = ir_build_instruction<Stage1ZirInstSuspendFinish>(ag, scope, source_node);
27732773 inst->begin = begin;
27742774
27752775 ir_ref_instruction(&begin->base, ag->current_basic_block);
......@@ -2777,10 +2777,10 @@ static IrInstSrc *ir_build_suspend_finish_src(Stage1AstGen *ag, Scope *scope, As
27772777 return &inst->base;
27782778}
27792779
2780static IrInstSrc *ir_build_await_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2781 IrInstSrc *frame, ResultLoc *result_loc, bool is_nosuspend)
2780static Stage1ZirInst *ir_build_await_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2781 Stage1ZirInst *frame, ResultLoc *result_loc, bool is_nosuspend)
27822782{
2783 IrInstSrcAwait *instruction = ir_build_instruction<IrInstSrcAwait>(ag, scope, source_node);
2783 Stage1ZirInstAwait *instruction = ir_build_instruction<Stage1ZirInstAwait>(ag, scope, source_node);
27842784 instruction->frame = frame;
27852785 instruction->result_loc = result_loc;
27862786 instruction->is_nosuspend = is_nosuspend;
......@@ -2790,8 +2790,8 @@ static IrInstSrc *ir_build_await_src(Stage1AstGen *ag, Scope *scope, AstNode *so
27902790 return &instruction->base;
27912791}
27922792
2793static IrInstSrc *ir_build_resume_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *frame) {
2794 IrInstSrcResume *instruction = ir_build_instruction<IrInstSrcResume>(ag, scope, source_node);
2793static Stage1ZirInst *ir_build_resume_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *frame) {
2794 Stage1ZirInstResume *instruction = ir_build_instruction<Stage1ZirInstResume>(ag, scope, source_node);
27952795 instruction->frame = frame;
27962796
27972797 ir_ref_instruction(frame, ag->current_basic_block);
......@@ -2799,10 +2799,10 @@ static IrInstSrc *ir_build_resume_src(Stage1AstGen *ag, Scope *scope, AstNode *s
27992799 return &instruction->base;
28002800}
28012801
2802static IrInstSrcSpillBegin *ir_build_spill_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2803 IrInstSrc *operand, SpillId spill_id)
2802static Stage1ZirInstSpillBegin *ir_build_spill_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2803 Stage1ZirInst *operand, SpillId spill_id)
28042804{
2805 IrInstSrcSpillBegin *instruction = ir_build_instruction<IrInstSrcSpillBegin>(ag, scope, source_node);
2805 Stage1ZirInstSpillBegin *instruction = ir_build_instruction<Stage1ZirInstSpillBegin>(ag, scope, source_node);
28062806 instruction->operand = operand;
28072807 instruction->spill_id = spill_id;
28082808
......@@ -2811,10 +2811,10 @@ static IrInstSrcSpillBegin *ir_build_spill_begin_src(Stage1AstGen *ag, Scope *sc
28112811 return instruction;
28122812}
28132813
2814static IrInstSrc *ir_build_spill_end_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2815 IrInstSrcSpillBegin *begin)
2814static Stage1ZirInst *ir_build_spill_end_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
2815 Stage1ZirInstSpillBegin *begin)
28162816{
2817 IrInstSrcSpillEnd *instruction = ir_build_instruction<IrInstSrcSpillEnd>(ag, scope, source_node);
2817 Stage1ZirInstSpillEnd *instruction = ir_build_instruction<Stage1ZirInstSpillEnd>(ag, scope, source_node);
28182818 instruction->begin = begin;
28192819
28202820 ir_ref_instruction(&begin->base, ag->current_basic_block);
......@@ -2822,8 +2822,8 @@ static IrInstSrc *ir_build_spill_end_src(Stage1AstGen *ag, Scope *scope, AstNode
28222822 return &instruction->base;
28232823}
28242824
2825static IrInstSrc *ir_build_wasm_memory_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *index) {
2826 IrInstSrcWasmMemorySize *instruction = ir_build_instruction<IrInstSrcWasmMemorySize>(ag, scope, source_node);
2825static Stage1ZirInst *ir_build_wasm_memory_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *index) {
2826 Stage1ZirInstWasmMemorySize *instruction = ir_build_instruction<Stage1ZirInstWasmMemorySize>(ag, scope, source_node);
28272827 instruction->index = index;
28282828
28292829 ir_ref_instruction(index, ag->current_basic_block);
......@@ -2831,8 +2831,8 @@ static IrInstSrc *ir_build_wasm_memory_size_src(Stage1AstGen *ag, Scope *scope,
28312831 return &instruction->base;
28322832}
28332833
2834static IrInstSrc *ir_build_wasm_memory_grow_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *index, IrInstSrc *delta) {
2835 IrInstSrcWasmMemoryGrow *instruction = ir_build_instruction<IrInstSrcWasmMemoryGrow>(ag, scope, source_node);
2834static Stage1ZirInst *ir_build_wasm_memory_grow_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *index, Stage1ZirInst *delta) {
2835 Stage1ZirInstWasmMemoryGrow *instruction = ir_build_instruction<Stage1ZirInstWasmMemoryGrow>(ag, scope, source_node);
28362836 instruction->index = index;
28372837 instruction->delta = delta;
28382838
......@@ -2842,8 +2842,8 @@ static IrInstSrc *ir_build_wasm_memory_grow_src(Stage1AstGen *ag, Scope *scope,
28422842 return &instruction->base;
28432843}
28442844
2845static IrInstSrc *ir_build_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2846 IrInstSrcSrc *instruction = ir_build_instruction<IrInstSrcSrc>(ag, scope, source_node);
2845static Stage1ZirInst *ir_build_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) {
2846 Stage1ZirInstSrc *instruction = ir_build_instruction<Stage1ZirInstSrc>(ag, scope, source_node);
28472847
28482848 return &instruction->base;
28492849}
......@@ -2886,7 +2886,7 @@ static void ir_count_defers(Stage1AstGen *ag, Scope *inner_scope, Scope *outer_s
28862886 }
28872887}
28882888
2889static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope *outer_scope, bool *is_noreturn, IrInstSrc *err_value) {
2889static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope *outer_scope, bool *is_noreturn, Stage1ZirInst *err_value) {
28902890 Scope *scope = inner_scope;
28912891 if (is_noreturn != nullptr) *is_noreturn = false;
28922892 while (scope != outer_scope) {
......@@ -2920,7 +2920,7 @@ static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope
29202920 return false;
29212921 }
29222922
2923 IrInstSrc *is_comptime;
2923 Stage1ZirInst *is_comptime;
29242924 if (ir_should_inline(ag->exec, defer_expr_scope)) {
29252925 is_comptime = ir_build_const_bool(ag, defer_expr_scope,
29262926 defer_expr_node, true);
......@@ -2937,7 +2937,7 @@ static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope
29372937 defer_expr_scope = err_var->child_scope;
29382938 }
29392939
2940 IrInstSrc *defer_expr_value = astgen_node(ag, defer_expr_node, defer_expr_scope);
2940 Stage1ZirInst *defer_expr_value = astgen_node(ag, defer_expr_node, defer_expr_scope);
29412941 if (defer_expr_value == ag->codegen->invalid_inst_src)
29422942 return ag->codegen->invalid_inst_src;
29432943
......@@ -3007,7 +3007,7 @@ static ScopeDeferExpr *get_scope_defer_expr(Scope *scope) {
30073007 return nullptr;
30083008}
30093009
3010static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {
3010static Stage1ZirInst *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {
30113011 assert(node->type == NodeTypeReturnExpr);
30123012
30133013 ScopeDeferExpr *scope_defer_expr = get_scope_defer_expr(scope);
......@@ -3029,7 +3029,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
30293029 result_loc_ret->base.id = ResultLocIdReturn;
30303030 ir_build_reset_result(ag, scope, node, &result_loc_ret->base);
30313031
3032 IrInstSrc *return_value;
3032 Stage1ZirInst *return_value;
30333033 if (expr_node) {
30343034 // Temporarily set this so that if we return a type it gets the name of the function
30353035 ZigFn *prev_name_fn = ag->exec->name_fn;
......@@ -3052,7 +3052,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
30523052 // only generate unconditional defers
30533053 if (!astgen_defers_for_block(ag, scope, outer_scope, nullptr, nullptr))
30543054 return ag->codegen->invalid_inst_src;
3055 IrInstSrc *result = ir_build_return_src(ag, scope, node, nullptr);
3055 Stage1ZirInst *result = ir_build_return_src(ag, scope, node, nullptr);
30563056 result_loc_ret->base.source_instruction = result;
30573057 return result;
30583058 }
......@@ -3061,9 +3061,9 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
30613061 Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, scope, "ErrRetErr");
30623062 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "ErrRetOk");
30633063
3064 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, return_value, false, true);
3064 Stage1ZirInst *is_err = ir_build_test_err_src(ag, scope, node, return_value, false, true);
30653065
3066 IrInstSrc *is_comptime;
3066 Stage1ZirInst *is_comptime;
30673067 if (should_inline) {
30683068 is_comptime = ir_build_const_bool(ag, scope, node, should_inline);
30693069 } else {
......@@ -3087,21 +3087,21 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
30873087 ir_build_br(ag, scope, node, ret_stmt_block, is_comptime);
30883088
30893089 ir_set_cursor_at_end_and_append_block(ag, ret_stmt_block);
3090 IrInstSrc *result = ir_build_return_src(ag, scope, node, nullptr);
3090 Stage1ZirInst *result = ir_build_return_src(ag, scope, node, nullptr);
30913091 result_loc_ret->base.source_instruction = result;
30923092 return result;
30933093 }
30943094 case ReturnKindError:
30953095 {
30963096 assert(expr_node);
3097 IrInstSrc *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
3097 Stage1ZirInst *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
30983098 if (err_union_ptr == ag->codegen->invalid_inst_src)
30993099 return ag->codegen->invalid_inst_src;
3100 IrInstSrc *is_err_val = ir_build_test_err_src(ag, scope, node, err_union_ptr, true, false);
3100 Stage1ZirInst *is_err_val = ir_build_test_err_src(ag, scope, node, err_union_ptr, true, false);
31013101
31023102 Stage1ZirBasicBlock *return_block = ir_create_basic_block(ag, scope, "ErrRetReturn");
31033103 Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, scope, "ErrRetContinue");
3104 IrInstSrc *is_comptime;
3104 Stage1ZirInst *is_comptime;
31053105 bool should_inline = ir_should_inline(ag->exec, scope);
31063106 if (should_inline) {
31073107 is_comptime = ir_build_const_bool(ag, scope, node, true);
......@@ -3111,10 +3111,10 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
31113111 ir_build_cond_br(ag, scope, node, is_err_val, return_block, continue_block, is_comptime);
31123112
31133113 ir_set_cursor_at_end_and_append_block(ag, return_block);
3114 IrInstSrc *err_val_ptr = ir_build_unwrap_err_code_src(ag, scope, node, err_union_ptr);
3115 IrInstSrc *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr);
3114 Stage1ZirInst *err_val_ptr = ir_build_unwrap_err_code_src(ag, scope, node, err_union_ptr);
3115 Stage1ZirInst *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr);
31163116 ir_build_add_implicit_return_type(ag, scope, node, err_val, nullptr);
3117 IrInstSrcSpillBegin *spill_begin = ir_build_spill_begin_src(ag, scope, node, err_val,
3117 Stage1ZirInstSpillBegin *spill_begin = ir_build_spill_begin_src(ag, scope, node, err_val,
31183118 SpillIdRetErrCode);
31193119 ResultLocReturn *result_loc_ret = heap::c_allocator.create<ResultLocReturn>();
31203120 result_loc_ret->base.id = ResultLocIdReturn;
......@@ -3130,12 +3130,12 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
31303130 ir_build_save_err_ret_addr_src(ag, scope, node);
31313131 }
31323132 err_val = ir_build_spill_end_src(ag, scope, node, spill_begin);
3133 IrInstSrc *ret_inst = ir_build_return_src(ag, scope, node, err_val);
3133 Stage1ZirInst *ret_inst = ir_build_return_src(ag, scope, node, err_val);
31343134 result_loc_ret->base.source_instruction = ret_inst;
31353135 }
31363136
31373137 ir_set_cursor_at_end_and_append_block(ag, continue_block);
3138 IrInstSrc *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, scope, node, err_union_ptr, false, false);
3138 Stage1ZirInst *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, scope, node, err_union_ptr, false, false);
31393139 if (lval == LValPtr)
31403140 return unwrapped_ptr;
31413141 else
......@@ -3146,7 +3146,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
31463146}
31473147
31483148ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope,
3149 Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime,
3149 Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime,
31503150 bool skip_name_check)
31513151{
31523152 ZigVar *variable_entry = heap::c_allocator.create<ZigVar>();
......@@ -3218,7 +3218,7 @@ ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope,
32183218// Set name to nullptr to make the variable anonymous (not visible to programmer).
32193219// After you call this function var->child_scope has the variable in scope
32203220static ZigVar *ir_create_var(Stage1AstGen *ag, AstNode *node, Scope *scope, Buf *name,
3221 bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime)
3221 bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime)
32223222{
32233223 bool is_underscored = name ? buf_eql_str(name, "_") : false;
32243224 ZigVar *var = create_local_var(ag->codegen, node, scope,
......@@ -3256,12 +3256,12 @@ static bool is_duplicate_label(CodeGen *g, Scope *scope, AstNode *node, Buf *nam
32563256 return false;
32573257}
32583258
3259static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *block_node, LVal lval,
3259static Stage1ZirInst *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *block_node, LVal lval,
32603260 ResultLoc *result_loc)
32613261{
32623262 assert(block_node->type == NodeTypeBlock);
32633263
3264 ZigList<IrInstSrc *> incoming_values = {0};
3264 ZigList<Stage1ZirInst *> incoming_values = {0};
32653265 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
32663266
32673267 if (is_duplicate_label(ag->codegen, parent_scope, block_node, block_node->data.block.name))
......@@ -3305,11 +3305,11 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
33053305
33063306 bool is_continuation_unreachable = false;
33073307 bool found_invalid_inst = false;
3308 IrInstSrc *noreturn_return_value = nullptr;
3308 Stage1ZirInst *noreturn_return_value = nullptr;
33093309 for (size_t i = 0; i < block_node->data.block.statements.length; i += 1) {
33103310 AstNode *statement_node = block_node->data.block.statements.at(i);
33113311
3312 IrInstSrc *statement_value = astgen_node(ag, statement_node, child_scope);
3312 Stage1ZirInst *statement_value = astgen_node(ag, statement_node, child_scope);
33133313 if (statement_value == ag->codegen->invalid_inst_src) {
33143314 // keep generating all the elements of the block in case of error,
33153315 // we want to collect other compile errors
......@@ -3328,9 +3328,9 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
33283328 // defer starts a new scope
33293329 child_scope = statement_node->data.defer.child_scope;
33303330 assert(child_scope);
3331 } else if (statement_value->id == IrInstSrcIdDeclVar) {
3331 } else if (statement_value->id == Stage1ZirInstIdDeclVar) {
33323332 // variable declarations start a new scope
3333 IrInstSrcDeclVar *decl_var_instruction = (IrInstSrcDeclVar *)statement_value;
3333 Stage1ZirInstDeclVar *decl_var_instruction = (Stage1ZirInstDeclVar *)statement_value;
33343334 child_scope = decl_var_instruction->var->child_scope;
33353335 } else if (!is_continuation_unreachable) {
33363336 // this statement's value must be void
......@@ -3355,12 +3355,12 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
33553355 scope_block->peer_parent->peers.last()->next_bb = scope_block->end_block;
33563356 }
33573357 ir_set_cursor_at_end_and_append_block(ag, scope_block->end_block);
3358 IrInstSrc *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length,
3358 Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length,
33593359 incoming_blocks.items, incoming_values.items, scope_block->peer_parent);
33603360 return ir_expr_wrap(ag, parent_scope, phi, result_loc);
33613361 } else {
33623362 incoming_blocks.append(ag->current_basic_block);
3363 IrInstSrc *else_expr_result = ir_build_const_void(ag, parent_scope, block_node);
3363 Stage1ZirInst *else_expr_result = ir_build_const_void(ag, parent_scope, block_node);
33643364
33653365 if (scope_block->peer_parent != nullptr) {
33663366 ResultLocPeer *peer_result = create_peer_result(scope_block->peer_parent);
......@@ -3381,15 +3381,15 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
33813381 return ag->codegen->invalid_inst_src;
33823382 }
33833383
3384 IrInstSrc *result;
3384 Stage1ZirInst *result;
33853385 if (block_node->data.block.name != nullptr) {
33863386 ir_build_br(ag, parent_scope, block_node, scope_block->end_block, scope_block->is_comptime);
33873387 ir_set_cursor_at_end_and_append_block(ag, scope_block->end_block);
3388 IrInstSrc *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length,
3388 Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length,
33893389 incoming_blocks.items, incoming_values.items, scope_block->peer_parent);
33903390 result = ir_expr_wrap(ag, parent_scope, phi, result_loc);
33913391 } else {
3392 IrInstSrc *void_inst = ir_build_const_void(ag, child_scope, block_node);
3392 Stage1ZirInst *void_inst = ir_build_const_void(ag, child_scope, block_node);
33933393 result = ir_lval_wrap(ag, parent_scope, void_inst, lval, result_loc);
33943394 }
33953395 if (!is_return_from_fn)
......@@ -3408,14 +3408,14 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
34083408 return ir_build_return_src(ag, child_scope, result->source_node, result);
34093409}
34103410
3411static IrInstSrc *astgen_bin_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) {
3411static Stage1ZirInst *astgen_bin_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) {
34123412 Scope *inner_scope = scope;
34133413 if (op_id == IrBinOpArrayCat || op_id == IrBinOpArrayMult) {
34143414 inner_scope = create_comptime_scope(ag->codegen, node, scope);
34153415 }
34163416
3417 IrInstSrc *op1 = astgen_node(ag, node->data.bin_op_expr.op1, inner_scope);
3418 IrInstSrc *op2 = astgen_node(ag, node->data.bin_op_expr.op2, inner_scope);
3417 Stage1ZirInst *op1 = astgen_node(ag, node->data.bin_op_expr.op1, inner_scope);
3418 Stage1ZirInst *op2 = astgen_node(ag, node->data.bin_op_expr.op2, inner_scope);
34193419
34203420 if (op1 == ag->codegen->invalid_inst_src || op2 == ag->codegen->invalid_inst_src)
34213421 return ag->codegen->invalid_inst_src;
......@@ -3423,9 +3423,9 @@ static IrInstSrc *astgen_bin_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node
34233423 return ir_build_bin_op(ag, scope, node, op_id, op1, op2, true);
34243424}
34253425
3426static IrInstSrc *astgen_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3427 IrInstSrc *op1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);
3428 IrInstSrc *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
3426static Stage1ZirInst *astgen_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3427 Stage1ZirInst *op1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);
3428 Stage1ZirInst *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
34293429
34303430 if (op1 == ag->codegen->invalid_inst_src || op2 == ag->codegen->invalid_inst_src)
34313431 return ag->codegen->invalid_inst_src;
......@@ -3437,8 +3437,8 @@ static IrInstSrc *astgen_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode
34373437 return ir_build_merge_err_sets(ag, scope, node, op1, op2, type_name);
34383438}
34393439
3440static IrInstSrc *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3441 IrInstSrc *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr);
3440static Stage1ZirInst *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3441 Stage1ZirInst *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr);
34423442 if (lvalue == ag->codegen->invalid_inst_src)
34433443 return ag->codegen->invalid_inst_src;
34443444
......@@ -3448,7 +3448,7 @@ static IrInstSrc *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) {
34483448 ir_ref_instruction(lvalue, ag->current_basic_block);
34493449 ir_build_reset_result(ag, scope, node, &result_loc_inst->base);
34503450
3451 IrInstSrc *rvalue = astgen_node_extra(ag, node->data.bin_op_expr.op2, scope, LValNone,
3451 Stage1ZirInst *rvalue = astgen_node_extra(ag, node->data.bin_op_expr.op2, scope, LValNone,
34523452 &result_loc_inst->base);
34533453 if (rvalue == ag->codegen->invalid_inst_src)
34543454 return ag->codegen->invalid_inst_src;
......@@ -3456,28 +3456,28 @@ static IrInstSrc *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) {
34563456 return ir_build_const_void(ag, scope, node);
34573457}
34583458
3459static IrInstSrc *astgen_assign_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) {
3460 IrInstSrc *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr);
3459static Stage1ZirInst *astgen_assign_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) {
3460 Stage1ZirInst *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr);
34613461 if (lvalue == ag->codegen->invalid_inst_src)
34623462 return lvalue;
3463 IrInstSrc *op1 = ir_build_load_ptr(ag, scope, node->data.bin_op_expr.op1, lvalue);
3464 IrInstSrc *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
3463 Stage1ZirInst *op1 = ir_build_load_ptr(ag, scope, node->data.bin_op_expr.op1, lvalue);
3464 Stage1ZirInst *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
34653465 if (op2 == ag->codegen->invalid_inst_src)
34663466 return op2;
3467 IrInstSrc *result = ir_build_bin_op(ag, scope, node, op_id, op1, op2, true);
3467 Stage1ZirInst *result = ir_build_bin_op(ag, scope, node, op_id, op1, op2, true);
34683468 ir_build_store_ptr(ag, scope, node, lvalue, result);
34693469 return ir_build_const_void(ag, scope, node);
34703470}
34713471
3472static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3472static Stage1ZirInst *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node) {
34733473 assert(node->type == NodeTypeBinOpExpr);
34743474
3475 IrInstSrc *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);
3475 Stage1ZirInst *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);
34763476 if (val1 == ag->codegen->invalid_inst_src)
34773477 return ag->codegen->invalid_inst_src;
34783478 Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block;
34793479
3480 IrInstSrc *is_comptime;
3480 Stage1ZirInst *is_comptime;
34813481 if (ir_should_inline(ag->exec, scope)) {
34823482 is_comptime = ir_build_const_bool(ag, scope, node, true);
34833483 } else {
......@@ -3492,7 +3492,7 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
34923492 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);
34933493
34943494 ir_set_cursor_at_end_and_append_block(ag, false_block);
3495 IrInstSrc *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
3495 Stage1ZirInst *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
34963496 if (val2 == ag->codegen->invalid_inst_src)
34973497 return ag->codegen->invalid_inst_src;
34983498 Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block;
......@@ -3501,7 +3501,7 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
35013501
35023502 ir_set_cursor_at_end_and_append_block(ag, true_block);
35033503
3504 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
3504 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
35053505 incoming_values[0] = val1;
35063506 incoming_values[1] = val2;
35073507 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
......@@ -3511,15 +3511,15 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
35113511 return ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, nullptr);
35123512}
35133513
3514static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3514static Stage1ZirInst *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node) {
35153515 assert(node->type == NodeTypeBinOpExpr);
35163516
3517 IrInstSrc *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);
3517 Stage1ZirInst *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope);
35183518 if (val1 == ag->codegen->invalid_inst_src)
35193519 return ag->codegen->invalid_inst_src;
35203520 Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block;
35213521
3522 IrInstSrc *is_comptime;
3522 Stage1ZirInst *is_comptime;
35233523 if (ir_should_inline(ag->exec, scope)) {
35243524 is_comptime = ir_build_const_bool(ag, scope, node, true);
35253525 } else {
......@@ -3534,7 +3534,7 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
35343534 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);
35353535
35363536 ir_set_cursor_at_end_and_append_block(ag, true_block);
3537 IrInstSrc *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
3537 Stage1ZirInst *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope);
35383538 if (val2 == ag->codegen->invalid_inst_src)
35393539 return ag->codegen->invalid_inst_src;
35403540 Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block;
......@@ -3543,7 +3543,7 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
35433543
35443544 ir_set_cursor_at_end_and_append_block(ag, false_block);
35453545
3546 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
3546 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
35473547 incoming_values[0] = val1;
35483548 incoming_values[1] = val2;
35493549 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
......@@ -3553,8 +3553,8 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
35533553 return ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, nullptr);
35543554}
35553555
3556static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst,
3557 Stage1ZirBasicBlock *end_block, ResultLoc *parent, IrInstSrc *is_comptime)
3556static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, Stage1ZirInst *cond_br_inst,
3557 Stage1ZirBasicBlock *end_block, ResultLoc *parent, Stage1ZirInst *is_comptime)
35583558{
35593559 ResultLocPeerParent *peer_parent = heap::c_allocator.create<ResultLocPeerParent>();
35603560 peer_parent->base.id = ResultLocIdPeerParent;
......@@ -3564,7 +3564,7 @@ static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *c
35643564 peer_parent->is_comptime = is_comptime;
35653565 peer_parent->parent = parent;
35663566
3567 IrInstSrc *popped_inst = ag->current_basic_block->instruction_list.pop();
3567 Stage1ZirInst *popped_inst = ag->current_basic_block->instruction_list.pop();
35683568 ir_assert(popped_inst == cond_br_inst, cond_br_inst);
35693569
35703570 ir_build_reset_result(ag, cond_br_inst->scope, cond_br_inst->source_node, &peer_parent->base);
......@@ -3573,8 +3573,8 @@ static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *c
35733573 return peer_parent;
35743574}
35753575
3576static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst,
3577 Stage1ZirBasicBlock *else_block, Stage1ZirBasicBlock *end_block, ResultLoc *parent, IrInstSrc *is_comptime)
3576static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, Stage1ZirInst *cond_br_inst,
3577 Stage1ZirBasicBlock *else_block, Stage1ZirBasicBlock *end_block, ResultLoc *parent, Stage1ZirInst *is_comptime)
35783578{
35793579 ResultLocPeerParent *peer_parent = ir_build_result_peers(ag, cond_br_inst, end_block, parent, is_comptime);
35803580
......@@ -3587,7 +3587,7 @@ static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, IrIns
35873587 return peer_parent;
35883588}
35893589
3590static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,
3590static Stage1ZirInst *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,
35913591 ResultLoc *result_loc)
35923592{
35933593 assert(node->type == NodeTypeBinOpExpr);
......@@ -3595,14 +3595,14 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
35953595 AstNode *op1_node = node->data.bin_op_expr.op1;
35963596 AstNode *op2_node = node->data.bin_op_expr.op2;
35973597
3598 IrInstSrc *maybe_ptr = astgen_node_extra(ag, op1_node, parent_scope, LValPtr, nullptr);
3598 Stage1ZirInst *maybe_ptr = astgen_node_extra(ag, op1_node, parent_scope, LValPtr, nullptr);
35993599 if (maybe_ptr == ag->codegen->invalid_inst_src)
36003600 return ag->codegen->invalid_inst_src;
36013601
3602 IrInstSrc *maybe_val = ir_build_load_ptr(ag, parent_scope, node, maybe_ptr);
3603 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, parent_scope, node, maybe_val);
3602 Stage1ZirInst *maybe_val = ir_build_load_ptr(ag, parent_scope, node, maybe_ptr);
3603 Stage1ZirInst *is_non_null = ir_build_test_non_null_src(ag, parent_scope, node, maybe_val);
36043604
3605 IrInstSrc *is_comptime;
3605 Stage1ZirInst *is_comptime;
36063606 if (ir_should_inline(ag->exec, parent_scope)) {
36073607 is_comptime = ir_build_const_bool(ag, parent_scope, node, true);
36083608 } else {
......@@ -3612,13 +3612,13 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
36123612 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "OptionalNonNull");
36133613 Stage1ZirBasicBlock *null_block = ir_create_basic_block(ag, parent_scope, "OptionalNull");
36143614 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "OptionalEnd");
3615 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_non_null, ok_block, null_block, is_comptime);
3615 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_non_null, ok_block, null_block, is_comptime);
36163616
36173617 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block,
36183618 result_loc, is_comptime);
36193619
36203620 ir_set_cursor_at_end_and_append_block(ag, null_block);
3621 IrInstSrc *null_result = astgen_node_extra(ag, op2_node, parent_scope, LValNone,
3621 Stage1ZirInst *null_result = astgen_node_extra(ag, op2_node, parent_scope, LValNone,
36223622 &peer_parent->peers.at(0)->base);
36233623 if (null_result == ag->codegen->invalid_inst_src)
36243624 return ag->codegen->invalid_inst_src;
......@@ -3627,41 +3627,41 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
36273627 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
36283628
36293629 ir_set_cursor_at_end_and_append_block(ag, ok_block);
3630 IrInstSrc *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, parent_scope, node, maybe_ptr, false);
3631 IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);
3630 Stage1ZirInst *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, parent_scope, node, maybe_ptr, false);
3631 Stage1ZirInst *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);
36323632 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);
36333633 Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block;
36343634 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
36353635
36363636 ir_set_cursor_at_end_and_append_block(ag, end_block);
3637 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
3637 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
36383638 incoming_values[0] = null_result;
36393639 incoming_values[1] = unwrapped_payload;
36403640 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
36413641 incoming_blocks[0] = after_null_block;
36423642 incoming_blocks[1] = after_ok_block;
3643 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);
3643 Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);
36443644 return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc);
36453645}
36463646
3647static IrInstSrc *astgen_error_union(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
3647static Stage1ZirInst *astgen_error_union(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
36483648 assert(node->type == NodeTypeBinOpExpr);
36493649
36503650 AstNode *op1_node = node->data.bin_op_expr.op1;
36513651 AstNode *op2_node = node->data.bin_op_expr.op2;
36523652
3653 IrInstSrc *err_set = astgen_node(ag, op1_node, parent_scope);
3653 Stage1ZirInst *err_set = astgen_node(ag, op1_node, parent_scope);
36543654 if (err_set == ag->codegen->invalid_inst_src)
36553655 return ag->codegen->invalid_inst_src;
36563656
3657 IrInstSrc *payload = astgen_node(ag, op2_node, parent_scope);
3657 Stage1ZirInst *payload = astgen_node(ag, op2_node, parent_scope);
36583658 if (payload == ag->codegen->invalid_inst_src)
36593659 return ag->codegen->invalid_inst_src;
36603660
36613661 return ir_build_error_union(ag, parent_scope, node, err_set, payload);
36623662}
36633663
3664static IrInstSrc *astgen_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {
3664static Stage1ZirInst *astgen_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {
36653665 assert(node->type == NodeTypeBinOpExpr);
36663666
36673667 BinOpType bin_op_type = node->data.bin_op_expr.bin_op;
......@@ -3752,7 +3752,7 @@ static IrInstSrc *astgen_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *node, L
37523752 zig_unreachable();
37533753}
37543754
3755static IrInstSrc *astgen_int_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3755static Stage1ZirInst *astgen_int_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {
37563756 assert(node->type == NodeTypeIntLiteral);
37573757
37583758 RootStruct *root_struct = node->owner->data.structure.root_struct;
......@@ -3761,7 +3761,7 @@ static IrInstSrc *astgen_int_lit(Stage1AstGen *ag, Scope *scope, AstNode *node)
37613761 return ir_build_const_bigint(ag, scope, node, bigint);
37623762}
37633763
3764static IrInstSrc *astgen_float_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3764static Stage1ZirInst *astgen_float_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {
37653765 Error err;
37663766 assert(node->type == NodeTypeFloatLiteral);
37673767
......@@ -3778,7 +3778,7 @@ static IrInstSrc *astgen_float_lit(Stage1AstGen *ag, Scope *scope, AstNode *node
37783778 return ir_build_const_bigfloat(ag, scope, node, bigfloat);
37793779}
37803780
3781static IrInstSrc *astgen_char_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3781static Stage1ZirInst *astgen_char_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) {
37823782 Error err;
37833783 assert(node->type == NodeTypeCharLiteral);
37843784
......@@ -3798,13 +3798,13 @@ static IrInstSrc *astgen_char_lit(Stage1AstGen *ag, Scope *scope, AstNode *node)
37983798 return ir_build_const_uint(ag, scope, node, codepoint);
37993799}
38003800
3801static IrInstSrc *astgen_null_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3801static Stage1ZirInst *astgen_null_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
38023802 assert(node->type == NodeTypeNullLiteral);
38033803
38043804 return ir_build_const_null(ag, scope, node);
38053805}
38063806
3807static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
3807static Stage1ZirInst *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
38083808 ResultLoc *result_loc)
38093809{
38103810 Error err;
......@@ -3814,7 +3814,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod
38143814
38153815 if (buf_eql_str(variable_name, "_")) {
38163816 if (lval == LValAssign) {
3817 IrInstSrcConst *const_instruction = ir_build_instruction<IrInstSrcConst>(ag, scope, node);
3817 Stage1ZirInstConst *const_instruction = ir_build_instruction<Stage1ZirInstConst>(ag, scope, node);
38183818 const_instruction->value = ag->codegen->pass1_arena->create<ZigValue>();
38193819 const_instruction->value->type = get_pointer_to_type(ag->codegen,
38203820 ag->codegen->builtin_types.entry_void, false);
......@@ -3837,7 +3837,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod
38373837 }
38383838 assert(err == ErrorPrimitiveTypeNotFound);
38393839 } else {
3840 IrInstSrc *value = ir_build_const_type(ag, scope, node, primitive_type);
3840 Stage1ZirInst *value = ir_build_const_type(ag, scope, node, primitive_type);
38413841 if (lval == LValPtr || lval == LValAssign) {
38423842 return ir_build_ref_src(ag, scope, node, value);
38433843 } else {
......@@ -3848,7 +3848,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod
38483848 ScopeFnDef *crossed_fndef_scope;
38493849 ZigVar *var = find_variable(ag->codegen, scope, variable_name, &crossed_fndef_scope);
38503850 if (var) {
3851 IrInstSrc *var_ptr = ir_build_var_ptr_x(ag, scope, node, var, crossed_fndef_scope);
3851 Stage1ZirInst *var_ptr = ir_build_var_ptr_x(ag, scope, node, var, crossed_fndef_scope);
38523852 if (lval == LValPtr || lval == LValAssign) {
38533853 return var_ptr;
38543854 } else {
......@@ -3858,7 +3858,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod
38583858
38593859 Tld *tld = find_decl(ag->codegen, scope, variable_name);
38603860 if (tld) {
3861 IrInstSrc *decl_ref = ir_build_decl_ref(ag, scope, node, tld, lval);
3861 Stage1ZirInst *decl_ref = ir_build_decl_ref(ag, scope, node, tld, lval);
38623862 if (lval == LValPtr || lval == LValAssign) {
38633863 return decl_ref;
38643864 } else {
......@@ -3875,52 +3875,52 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod
38753875 return ir_build_undeclared_identifier(ag, scope, node, variable_name);
38763876}
38773877
3878static IrInstSrc *astgen_array_access(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
3878static Stage1ZirInst *astgen_array_access(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
38793879 ResultLoc *result_loc)
38803880{
38813881 assert(node->type == NodeTypeArrayAccessExpr);
38823882
38833883 AstNode *array_ref_node = node->data.array_access_expr.array_ref_expr;
3884 IrInstSrc *array_ref_instruction = astgen_node_extra(ag, array_ref_node, scope, LValPtr, nullptr);
3884 Stage1ZirInst *array_ref_instruction = astgen_node_extra(ag, array_ref_node, scope, LValPtr, nullptr);
38853885 if (array_ref_instruction == ag->codegen->invalid_inst_src)
38863886 return array_ref_instruction;
38873887
38883888 // Create an usize-typed result location to hold the subscript value, this
38893889 // makes it possible for the compiler to infer the subscript expression type
38903890 // if needed
3891 IrInstSrc *usize_type_inst = ir_build_const_type(ag, scope, node, ag->codegen->builtin_types.entry_usize);
3891 Stage1ZirInst *usize_type_inst = ir_build_const_type(ag, scope, node, ag->codegen->builtin_types.entry_usize);
38923892 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, usize_type_inst, no_result_loc());
38933893
38943894 AstNode *subscript_node = node->data.array_access_expr.subscript;
3895 IrInstSrc *subscript_value = astgen_node_extra(ag, subscript_node, scope, LValNone, &result_loc_cast->base);
3895 Stage1ZirInst *subscript_value = astgen_node_extra(ag, subscript_node, scope, LValNone, &result_loc_cast->base);
38963896 if (subscript_value == ag->codegen->invalid_inst_src)
38973897 return ag->codegen->invalid_inst_src;
38983898
3899 IrInstSrc *subscript_instruction = ir_build_implicit_cast(ag, scope, subscript_node, subscript_value, result_loc_cast);
3899 Stage1ZirInst *subscript_instruction = ir_build_implicit_cast(ag, scope, subscript_node, subscript_value, result_loc_cast);
39003900
3901 IrInstSrc *ptr_instruction = ir_build_elem_ptr(ag, scope, node, array_ref_instruction,
3901 Stage1ZirInst *ptr_instruction = ir_build_elem_ptr(ag, scope, node, array_ref_instruction,
39023902 subscript_instruction, true, PtrLenSingle, nullptr);
39033903 if (lval == LValPtr || lval == LValAssign)
39043904 return ptr_instruction;
39053905
3906 IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);
3906 Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);
39073907 return ir_expr_wrap(ag, scope, load_ptr, result_loc);
39083908}
39093909
3910static IrInstSrc *astgen_field_access(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3910static Stage1ZirInst *astgen_field_access(Stage1AstGen *ag, Scope *scope, AstNode *node) {
39113911 assert(node->type == NodeTypeFieldAccessExpr);
39123912
39133913 AstNode *container_ref_node = node->data.field_access_expr.struct_expr;
39143914 Buf *field_name = node->data.field_access_expr.field_name;
39153915
3916 IrInstSrc *container_ref_instruction = astgen_node_extra(ag, container_ref_node, scope, LValPtr, nullptr);
3916 Stage1ZirInst *container_ref_instruction = astgen_node_extra(ag, container_ref_node, scope, LValPtr, nullptr);
39173917 if (container_ref_instruction == ag->codegen->invalid_inst_src)
39183918 return container_ref_instruction;
39193919
39203920 return ir_build_field_ptr(ag, scope, node, container_ref_instruction, field_name, false);
39213921}
39223922
3923static IrInstSrc *astgen_overflow_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrOverflowOp op) {
3923static Stage1ZirInst *astgen_overflow_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrOverflowOp op) {
39243924 assert(node->type == NodeTypeFnCallExpr);
39253925
39263926 AstNode *type_node = node->data.fn_call_expr.params.at(0);
......@@ -3929,26 +3929,26 @@ static IrInstSrc *astgen_overflow_op(Stage1AstGen *ag, Scope *scope, AstNode *no
39293929 AstNode *result_ptr_node = node->data.fn_call_expr.params.at(3);
39303930
39313931
3932 IrInstSrc *type_value = astgen_node(ag, type_node, scope);
3932 Stage1ZirInst *type_value = astgen_node(ag, type_node, scope);
39333933 if (type_value == ag->codegen->invalid_inst_src)
39343934 return ag->codegen->invalid_inst_src;
39353935
3936 IrInstSrc *op1 = astgen_node(ag, op1_node, scope);
3936 Stage1ZirInst *op1 = astgen_node(ag, op1_node, scope);
39373937 if (op1 == ag->codegen->invalid_inst_src)
39383938 return ag->codegen->invalid_inst_src;
39393939
3940 IrInstSrc *op2 = astgen_node(ag, op2_node, scope);
3940 Stage1ZirInst *op2 = astgen_node(ag, op2_node, scope);
39413941 if (op2 == ag->codegen->invalid_inst_src)
39423942 return ag->codegen->invalid_inst_src;
39433943
3944 IrInstSrc *result_ptr = astgen_node(ag, result_ptr_node, scope);
3944 Stage1ZirInst *result_ptr = astgen_node(ag, result_ptr_node, scope);
39453945 if (result_ptr == ag->codegen->invalid_inst_src)
39463946 return ag->codegen->invalid_inst_src;
39473947
39483948 return ir_build_overflow_op_src(ag, scope, node, op, type_value, op1, op2, result_ptr);
39493949}
39503950
3951static IrInstSrc *astgen_mul_add(Stage1AstGen *ag, Scope *scope, AstNode *node) {
3951static Stage1ZirInst *astgen_mul_add(Stage1AstGen *ag, Scope *scope, AstNode *node) {
39523952 assert(node->type == NodeTypeFnCallExpr);
39533953
39543954 AstNode *type_node = node->data.fn_call_expr.params.at(0);
......@@ -3956,26 +3956,26 @@ static IrInstSrc *astgen_mul_add(Stage1AstGen *ag, Scope *scope, AstNode *node)
39563956 AstNode *op2_node = node->data.fn_call_expr.params.at(2);
39573957 AstNode *op3_node = node->data.fn_call_expr.params.at(3);
39583958
3959 IrInstSrc *type_value = astgen_node(ag, type_node, scope);
3959 Stage1ZirInst *type_value = astgen_node(ag, type_node, scope);
39603960 if (type_value == ag->codegen->invalid_inst_src)
39613961 return ag->codegen->invalid_inst_src;
39623962
3963 IrInstSrc *op1 = astgen_node(ag, op1_node, scope);
3963 Stage1ZirInst *op1 = astgen_node(ag, op1_node, scope);
39643964 if (op1 == ag->codegen->invalid_inst_src)
39653965 return ag->codegen->invalid_inst_src;
39663966
3967 IrInstSrc *op2 = astgen_node(ag, op2_node, scope);
3967 Stage1ZirInst *op2 = astgen_node(ag, op2_node, scope);
39683968 if (op2 == ag->codegen->invalid_inst_src)
39693969 return ag->codegen->invalid_inst_src;
39703970
3971 IrInstSrc *op3 = astgen_node(ag, op3_node, scope);
3971 Stage1ZirInst *op3 = astgen_node(ag, op3_node, scope);
39723972 if (op3 == ag->codegen->invalid_inst_src)
39733973 return ag->codegen->invalid_inst_src;
39743974
39753975 return ir_build_mul_add_src(ag, scope, node, type_value, op1, op2, op3);
39763976}
39773977
3978static IrInstSrc *astgen_this(Stage1AstGen *ag, Scope *orig_scope, AstNode *node) {
3978static Stage1ZirInst *astgen_this(Stage1AstGen *ag, Scope *orig_scope, AstNode *node) {
39793979 for (Scope *it_scope = orig_scope; it_scope != nullptr; it_scope = it_scope->parent) {
39803980 if (it_scope->id == ScopeIdDecls) {
39813981 ScopeDecls *decls_scope = (ScopeDecls *)it_scope;
......@@ -3990,7 +3990,7 @@ static IrInstSrc *astgen_this(Stage1AstGen *ag, Scope *orig_scope, AstNode *node
39903990 zig_unreachable();
39913991}
39923992
3993static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *await_node, AstNode *call_node,
3993static Stage1ZirInst *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *await_node, AstNode *call_node,
39943994 LVal lval, ResultLoc *result_loc)
39953995{
39963996 if (call_node->data.fn_call_expr.params.length != 4) {
......@@ -4001,17 +4001,17 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa
40014001 }
40024002
40034003 AstNode *bytes_node = call_node->data.fn_call_expr.params.at(0);
4004 IrInstSrc *bytes = astgen_node(ag, bytes_node, scope);
4004 Stage1ZirInst *bytes = astgen_node(ag, bytes_node, scope);
40054005 if (bytes == ag->codegen->invalid_inst_src)
40064006 return bytes;
40074007
40084008 AstNode *ret_ptr_node = call_node->data.fn_call_expr.params.at(1);
4009 IrInstSrc *ret_ptr = astgen_node(ag, ret_ptr_node, scope);
4009 Stage1ZirInst *ret_ptr = astgen_node(ag, ret_ptr_node, scope);
40104010 if (ret_ptr == ag->codegen->invalid_inst_src)
40114011 return ret_ptr;
40124012
40134013 AstNode *fn_ref_node = call_node->data.fn_call_expr.params.at(2);
4014 IrInstSrc *fn_ref = astgen_node(ag, fn_ref_node, scope);
4014 Stage1ZirInst *fn_ref = astgen_node(ag, fn_ref_node, scope);
40154015 if (fn_ref == ag->codegen->invalid_inst_src)
40164016 return fn_ref;
40174017
......@@ -4023,16 +4023,16 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa
40234023 args_node->data.container_init_expr.entries.length == 0)
40244024 {
40254025 size_t arg_count = args_node->data.container_init_expr.entries.length;
4026 IrInstSrc **args = heap::c_allocator.allocate<IrInstSrc*>(arg_count);
4026 Stage1ZirInst **args = heap::c_allocator.allocate<Stage1ZirInst*>(arg_count);
40274027 for (size_t i = 0; i < arg_count; i += 1) {
40284028 AstNode *arg_node = args_node->data.container_init_expr.entries.at(i);
4029 IrInstSrc *arg = astgen_node(ag, arg_node, scope);
4029 Stage1ZirInst *arg = astgen_node(ag, arg_node, scope);
40304030 if (arg == ag->codegen->invalid_inst_src)
40314031 return arg;
40324032 args[i] = arg;
40334033 }
40344034
4035 IrInstSrc *call = ir_build_call_src(ag, scope, call_node, nullptr, fn_ref, arg_count, args,
4035 Stage1ZirInst *call = ir_build_call_src(ag, scope, call_node, nullptr, fn_ref, arg_count, args,
40364036 ret_ptr, modifier, is_async_call_builtin, bytes, result_loc);
40374037 return ir_lval_wrap(ag, scope, call, lval, result_loc);
40384038 } else {
......@@ -4041,42 +4041,42 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa
40414041 return ag->codegen->invalid_inst_src;
40424042 }
40434043 }
4044 IrInstSrc *args = astgen_node(ag, args_node, scope);
4044 Stage1ZirInst *args = astgen_node(ag, args_node, scope);
40454045 if (args == ag->codegen->invalid_inst_src)
40464046 return args;
40474047
4048 IrInstSrc *call = ir_build_async_call_extra(ag, scope, call_node, modifier, fn_ref, ret_ptr, bytes, args, result_loc);
4048 Stage1ZirInst *call = ir_build_async_call_extra(ag, scope, call_node, modifier, fn_ref, ret_ptr, bytes, args, result_loc);
40494049 return ir_lval_wrap(ag, scope, call, lval, result_loc);
40504050}
40514051
4052static IrInstSrc *astgen_fn_call_with_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
4053 AstNode *fn_ref_node, CallModifier modifier, IrInstSrc *options,
4052static Stage1ZirInst *astgen_fn_call_with_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
4053 AstNode *fn_ref_node, CallModifier modifier, Stage1ZirInst *options,
40544054 AstNode **args_ptr, size_t args_len, LVal lval, ResultLoc *result_loc)
40554055{
4056 IrInstSrc *fn_ref = astgen_node(ag, fn_ref_node, scope);
4056 Stage1ZirInst *fn_ref = astgen_node(ag, fn_ref_node, scope);
40574057 if (fn_ref == ag->codegen->invalid_inst_src)
40584058 return fn_ref;
40594059
4060 IrInstSrc *fn_type = ir_build_typeof_1(ag, scope, source_node, fn_ref);
4060 Stage1ZirInst *fn_type = ir_build_typeof_1(ag, scope, source_node, fn_ref);
40614061
4062 IrInstSrc **args = heap::c_allocator.allocate<IrInstSrc*>(args_len);
4062 Stage1ZirInst **args = heap::c_allocator.allocate<Stage1ZirInst*>(args_len);
40634063 for (size_t i = 0; i < args_len; i += 1) {
40644064 AstNode *arg_node = args_ptr[i];
40654065
4066 IrInstSrc *arg_index = ir_build_const_usize(ag, scope, arg_node, i);
4067 IrInstSrc *arg_type = ir_build_arg_type(ag, scope, source_node, fn_type, arg_index, true);
4066 Stage1ZirInst *arg_index = ir_build_const_usize(ag, scope, arg_node, i);
4067 Stage1ZirInst *arg_type = ir_build_arg_type(ag, scope, source_node, fn_type, arg_index, true);
40684068 ResultLoc *no_result = no_result_loc();
40694069 ir_build_reset_result(ag, scope, source_node, no_result);
40704070 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, arg_type, no_result);
40714071
4072 IrInstSrc *arg = astgen_node_extra(ag, arg_node, scope, LValNone, &result_loc_cast->base);
4072 Stage1ZirInst *arg = astgen_node_extra(ag, arg_node, scope, LValNone, &result_loc_cast->base);
40734073 if (arg == ag->codegen->invalid_inst_src)
40744074 return arg;
40754075
40764076 args[i] = ir_build_implicit_cast(ag, scope, arg_node, arg, result_loc_cast);
40774077 }
40784078
4079 IrInstSrc *fn_call;
4079 Stage1ZirInst *fn_call;
40804080 if (options != nullptr) {
40814081 fn_call = ir_build_call_args(ag, scope, source_node, options, fn_ref, args, args_len, result_loc);
40824082 } else {
......@@ -4086,7 +4086,7 @@ static IrInstSrc *astgen_fn_call_with_args(Stage1AstGen *ag, Scope *scope, AstNo
40864086 return ir_lval_wrap(ag, scope, fn_call, lval, result_loc);
40874087}
40884088
4089static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
4089static Stage1ZirInst *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
40904090 ResultLoc *result_loc)
40914091{
40924092 assert(node->type == NodeTypeFnCallExpr);
......@@ -4120,7 +4120,7 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
41204120
41214121 size_t arg_count = node->data.fn_call_expr.params.length;
41224122
4123 IrInstSrc *type_of;
4123 Stage1ZirInst *type_of;
41244124
41254125 if (arg_count == 0) {
41264126 add_node_error(ag->codegen, node,
......@@ -4128,16 +4128,16 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
41284128 return ag->codegen->invalid_inst_src;
41294129 } else if (arg_count == 1) {
41304130 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4131 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, sub_scope);
4131 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, sub_scope);
41324132 if (arg0_value == ag->codegen->invalid_inst_src)
41334133 return arg0_value;
41344134
41354135 type_of = ir_build_typeof_1(ag, scope, node, arg0_value);
41364136 } else {
4137 IrInstSrc **args = heap::c_allocator.allocate<IrInstSrc*>(arg_count);
4137 Stage1ZirInst **args = heap::c_allocator.allocate<Stage1ZirInst*>(arg_count);
41384138 for (size_t i = 0; i < arg_count; i += 1) {
41394139 AstNode *arg_node = node->data.fn_call_expr.params.at(i);
4140 IrInstSrc *arg = astgen_node(ag, arg_node, sub_scope);
4140 Stage1ZirInst *arg = astgen_node(ag, arg_node, sub_scope);
41414141 if (arg == ag->codegen->invalid_inst_src)
41424142 return ag->codegen->invalid_inst_src;
41434143 args[i] = arg;
......@@ -4150,63 +4150,63 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
41504150 case BuiltinFnIdSetCold:
41514151 {
41524152 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4153 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4153 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
41544154 if (arg0_value == ag->codegen->invalid_inst_src)
41554155 return arg0_value;
41564156
4157 IrInstSrc *set_cold = ir_build_set_cold(ag, scope, node, arg0_value);
4157 Stage1ZirInst *set_cold = ir_build_set_cold(ag, scope, node, arg0_value);
41584158 return ir_lval_wrap(ag, scope, set_cold, lval, result_loc);
41594159 }
41604160 case BuiltinFnIdSetRuntimeSafety:
41614161 {
41624162 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4163 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4163 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
41644164 if (arg0_value == ag->codegen->invalid_inst_src)
41654165 return arg0_value;
41664166
4167 IrInstSrc *set_safety = ir_build_set_runtime_safety(ag, scope, node, arg0_value);
4167 Stage1ZirInst *set_safety = ir_build_set_runtime_safety(ag, scope, node, arg0_value);
41684168 return ir_lval_wrap(ag, scope, set_safety, lval, result_loc);
41694169 }
41704170 case BuiltinFnIdSetFloatMode:
41714171 {
41724172 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4173 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4173 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
41744174 if (arg0_value == ag->codegen->invalid_inst_src)
41754175 return arg0_value;
41764176
4177 IrInstSrc *set_float_mode = ir_build_set_float_mode(ag, scope, node, arg0_value);
4177 Stage1ZirInst *set_float_mode = ir_build_set_float_mode(ag, scope, node, arg0_value);
41784178 return ir_lval_wrap(ag, scope, set_float_mode, lval, result_loc);
41794179 }
41804180 case BuiltinFnIdSizeof:
41814181 case BuiltinFnIdBitSizeof:
41824182 {
41834183 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4184 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4184 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
41854185 if (arg0_value == ag->codegen->invalid_inst_src)
41864186 return arg0_value;
41874187
4188 IrInstSrc *size_of = ir_build_size_of(ag, scope, node, arg0_value, builtin_fn->id == BuiltinFnIdBitSizeof);
4188 Stage1ZirInst *size_of = ir_build_size_of(ag, scope, node, arg0_value, builtin_fn->id == BuiltinFnIdBitSizeof);
41894189 return ir_lval_wrap(ag, scope, size_of, lval, result_loc);
41904190 }
41914191 case BuiltinFnIdImport:
41924192 {
41934193 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4194 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4194 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
41954195 if (arg0_value == ag->codegen->invalid_inst_src)
41964196 return arg0_value;
41974197
4198 IrInstSrc *import = ir_build_import(ag, scope, node, arg0_value);
4198 Stage1ZirInst *import = ir_build_import(ag, scope, node, arg0_value);
41994199 return ir_lval_wrap(ag, scope, import, lval, result_loc);
42004200 }
42014201 case BuiltinFnIdCImport:
42024202 {
4203 IrInstSrc *c_import = ir_build_c_import(ag, scope, node);
4203 Stage1ZirInst *c_import = ir_build_c_import(ag, scope, node);
42044204 return ir_lval_wrap(ag, scope, c_import, lval, result_loc);
42054205 }
42064206 case BuiltinFnIdCInclude:
42074207 {
42084208 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4209 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4209 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
42104210 if (arg0_value == ag->codegen->invalid_inst_src)
42114211 return arg0_value;
42124212
......@@ -4215,18 +4215,18 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
42154215 return ag->codegen->invalid_inst_src;
42164216 }
42174217
4218 IrInstSrc *c_include = ir_build_c_include(ag, scope, node, arg0_value);
4218 Stage1ZirInst *c_include = ir_build_c_include(ag, scope, node, arg0_value);
42194219 return ir_lval_wrap(ag, scope, c_include, lval, result_loc);
42204220 }
42214221 case BuiltinFnIdCDefine:
42224222 {
42234223 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4224 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4224 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
42254225 if (arg0_value == ag->codegen->invalid_inst_src)
42264226 return arg0_value;
42274227
42284228 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4229 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4229 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
42304230 if (arg1_value == ag->codegen->invalid_inst_src)
42314231 return arg1_value;
42324232
......@@ -4235,13 +4235,13 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
42354235 return ag->codegen->invalid_inst_src;
42364236 }
42374237
4238 IrInstSrc *c_define = ir_build_c_define(ag, scope, node, arg0_value, arg1_value);
4238 Stage1ZirInst *c_define = ir_build_c_define(ag, scope, node, arg0_value, arg1_value);
42394239 return ir_lval_wrap(ag, scope, c_define, lval, result_loc);
42404240 }
42414241 case BuiltinFnIdCUndef:
42424242 {
42434243 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4244 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4244 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
42454245 if (arg0_value == ag->codegen->invalid_inst_src)
42464246 return arg0_value;
42474247
......@@ -4250,22 +4250,22 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
42504250 return ag->codegen->invalid_inst_src;
42514251 }
42524252
4253 IrInstSrc *c_undef = ir_build_c_undef(ag, scope, node, arg0_value);
4253 Stage1ZirInst *c_undef = ir_build_c_undef(ag, scope, node, arg0_value);
42544254 return ir_lval_wrap(ag, scope, c_undef, lval, result_loc);
42554255 }
42564256 case BuiltinFnIdCompileErr:
42574257 {
42584258 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4259 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4259 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
42604260 if (arg0_value == ag->codegen->invalid_inst_src)
42614261 return arg0_value;
42624262
4263 IrInstSrc *compile_err = ir_build_compile_err(ag, scope, node, arg0_value);
4263 Stage1ZirInst *compile_err = ir_build_compile_err(ag, scope, node, arg0_value);
42644264 return ir_lval_wrap(ag, scope, compile_err, lval, result_loc);
42654265 }
42664266 case BuiltinFnIdCompileLog:
42674267 {
4268 IrInstSrc **args = heap::c_allocator.allocate<IrInstSrc*>(actual_param_count);
4268 Stage1ZirInst **args = heap::c_allocator.allocate<Stage1ZirInst*>(actual_param_count);
42694269
42704270 for (size_t i = 0; i < actual_param_count; i += 1) {
42714271 AstNode *arg_node = node->data.fn_call_expr.params.at(i);
......@@ -4274,63 +4274,63 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
42744274 return ag->codegen->invalid_inst_src;
42754275 }
42764276
4277 IrInstSrc *compile_log = ir_build_compile_log(ag, scope, node, actual_param_count, args);
4277 Stage1ZirInst *compile_log = ir_build_compile_log(ag, scope, node, actual_param_count, args);
42784278 return ir_lval_wrap(ag, scope, compile_log, lval, result_loc);
42794279 }
42804280 case BuiltinFnIdErrName:
42814281 {
42824282 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4283 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4283 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
42844284 if (arg0_value == ag->codegen->invalid_inst_src)
42854285 return arg0_value;
42864286
4287 IrInstSrc *err_name = ir_build_err_name(ag, scope, node, arg0_value);
4287 Stage1ZirInst *err_name = ir_build_err_name(ag, scope, node, arg0_value);
42884288 return ir_lval_wrap(ag, scope, err_name, lval, result_loc);
42894289 }
42904290 case BuiltinFnIdEmbedFile:
42914291 {
42924292 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4293 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4293 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
42944294 if (arg0_value == ag->codegen->invalid_inst_src)
42954295 return arg0_value;
42964296
4297 IrInstSrc *embed_file = ir_build_embed_file(ag, scope, node, arg0_value);
4297 Stage1ZirInst *embed_file = ir_build_embed_file(ag, scope, node, arg0_value);
42984298 return ir_lval_wrap(ag, scope, embed_file, lval, result_loc);
42994299 }
43004300 case BuiltinFnIdCmpxchgWeak:
43014301 case BuiltinFnIdCmpxchgStrong:
43024302 {
43034303 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4304 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4304 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
43054305 if (arg0_value == ag->codegen->invalid_inst_src)
43064306 return arg0_value;
43074307
43084308 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4309 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4309 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
43104310 if (arg1_value == ag->codegen->invalid_inst_src)
43114311 return arg1_value;
43124312
43134313 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
4314 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);
4314 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
43154315 if (arg2_value == ag->codegen->invalid_inst_src)
43164316 return arg2_value;
43174317
43184318 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);
4319 IrInstSrc *arg3_value = astgen_node(ag, arg3_node, scope);
4319 Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, scope);
43204320 if (arg3_value == ag->codegen->invalid_inst_src)
43214321 return arg3_value;
43224322
43234323 AstNode *arg4_node = node->data.fn_call_expr.params.at(4);
4324 IrInstSrc *arg4_value = astgen_node(ag, arg4_node, scope);
4324 Stage1ZirInst *arg4_value = astgen_node(ag, arg4_node, scope);
43254325 if (arg4_value == ag->codegen->invalid_inst_src)
43264326 return arg4_value;
43274327
43284328 AstNode *arg5_node = node->data.fn_call_expr.params.at(5);
4329 IrInstSrc *arg5_value = astgen_node(ag, arg5_node, scope);
4329 Stage1ZirInst *arg5_value = astgen_node(ag, arg5_node, scope);
43304330 if (arg5_value == ag->codegen->invalid_inst_src)
43314331 return arg5_value;
43324332
4333 IrInstSrc *cmpxchg = ir_build_cmpxchg_src(ag, scope, node, arg0_value, arg1_value,
4333 Stage1ZirInst *cmpxchg = ir_build_cmpxchg_src(ag, scope, node, arg0_value, arg1_value,
43344334 arg2_value, arg3_value, arg4_value, arg5_value, (builtin_fn->id == BuiltinFnIdCmpxchgWeak),
43354335 result_loc);
43364336 return ir_lval_wrap(ag, scope, cmpxchg, lval, result_loc);
......@@ -4338,101 +4338,101 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
43384338 case BuiltinFnIdFence:
43394339 {
43404340 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4341 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4341 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
43424342 if (arg0_value == ag->codegen->invalid_inst_src)
43434343 return arg0_value;
43444344
4345 IrInstSrc *fence = ir_build_fence(ag, scope, node, arg0_value);
4345 Stage1ZirInst *fence = ir_build_fence(ag, scope, node, arg0_value);
43464346 return ir_lval_wrap(ag, scope, fence, lval, result_loc);
43474347 }
43484348 case BuiltinFnIdReduce:
43494349 {
43504350 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4351 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4351 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
43524352 if (arg0_value == ag->codegen->invalid_inst_src)
43534353 return arg0_value;
43544354
43554355 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4356 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4356 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
43574357 if (arg1_value == ag->codegen->invalid_inst_src)
43584358 return arg1_value;
43594359
4360 IrInstSrc *reduce = ir_build_reduce(ag, scope, node, arg0_value, arg1_value);
4360 Stage1ZirInst *reduce = ir_build_reduce(ag, scope, node, arg0_value, arg1_value);
43614361 return ir_lval_wrap(ag, scope, reduce, lval, result_loc);
43624362 }
43634363 case BuiltinFnIdDivExact:
43644364 {
43654365 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4366 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4366 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
43674367 if (arg0_value == ag->codegen->invalid_inst_src)
43684368 return arg0_value;
43694369
43704370 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4371 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4371 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
43724372 if (arg1_value == ag->codegen->invalid_inst_src)
43734373 return arg1_value;
43744374
4375 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivExact, arg0_value, arg1_value, true);
4375 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivExact, arg0_value, arg1_value, true);
43764376 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
43774377 }
43784378 case BuiltinFnIdDivTrunc:
43794379 {
43804380 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4381 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4381 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
43824382 if (arg0_value == ag->codegen->invalid_inst_src)
43834383 return arg0_value;
43844384
43854385 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4386 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4386 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
43874387 if (arg1_value == ag->codegen->invalid_inst_src)
43884388 return arg1_value;
43894389
4390 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivTrunc, arg0_value, arg1_value, true);
4390 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivTrunc, arg0_value, arg1_value, true);
43914391 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
43924392 }
43934393 case BuiltinFnIdDivFloor:
43944394 {
43954395 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4396 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4396 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
43974397 if (arg0_value == ag->codegen->invalid_inst_src)
43984398 return arg0_value;
43994399
44004400 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4401 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4401 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
44024402 if (arg1_value == ag->codegen->invalid_inst_src)
44034403 return arg1_value;
44044404
4405 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivFloor, arg0_value, arg1_value, true);
4405 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivFloor, arg0_value, arg1_value, true);
44064406 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
44074407 }
44084408 case BuiltinFnIdRem:
44094409 {
44104410 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4411 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4411 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
44124412 if (arg0_value == ag->codegen->invalid_inst_src)
44134413 return arg0_value;
44144414
44154415 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4416 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4416 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
44174417 if (arg1_value == ag->codegen->invalid_inst_src)
44184418 return arg1_value;
44194419
4420 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemRem, arg0_value, arg1_value, true);
4420 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemRem, arg0_value, arg1_value, true);
44214421 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
44224422 }
44234423 case BuiltinFnIdMod:
44244424 {
44254425 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4426 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4426 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
44274427 if (arg0_value == ag->codegen->invalid_inst_src)
44284428 return arg0_value;
44294429
44304430 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4431 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4431 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
44324432 if (arg1_value == ag->codegen->invalid_inst_src)
44334433 return arg1_value;
44344434
4435 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemMod, arg0_value, arg1_value, true);
4435 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemMod, arg0_value, arg1_value, true);
44364436 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
44374437 }
44384438 case BuiltinFnIdSqrt:
......@@ -4451,146 +4451,146 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
44514451 case BuiltinFnIdRound:
44524452 {
44534453 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4454 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4454 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
44554455 if (arg0_value == ag->codegen->invalid_inst_src)
44564456 return arg0_value;
44574457
4458 IrInstSrc *inst = ir_build_float_op_src(ag, scope, node, arg0_value, builtin_fn->id);
4458 Stage1ZirInst *inst = ir_build_float_op_src(ag, scope, node, arg0_value, builtin_fn->id);
44594459 return ir_lval_wrap(ag, scope, inst, lval, result_loc);
44604460 }
44614461 case BuiltinFnIdTruncate:
44624462 {
44634463 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4464 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4464 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
44654465 if (arg0_value == ag->codegen->invalid_inst_src)
44664466 return arg0_value;
44674467
44684468 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4469 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4469 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
44704470 if (arg1_value == ag->codegen->invalid_inst_src)
44714471 return arg1_value;
44724472
4473 IrInstSrc *truncate = ir_build_truncate(ag, scope, node, arg0_value, arg1_value);
4473 Stage1ZirInst *truncate = ir_build_truncate(ag, scope, node, arg0_value, arg1_value);
44744474 return ir_lval_wrap(ag, scope, truncate, lval, result_loc);
44754475 }
44764476 case BuiltinFnIdIntCast:
44774477 {
44784478 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4479 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4479 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
44804480 if (arg0_value == ag->codegen->invalid_inst_src)
44814481 return arg0_value;
44824482
44834483 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4484 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4484 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
44854485 if (arg1_value == ag->codegen->invalid_inst_src)
44864486 return arg1_value;
44874487
4488 IrInstSrc *result = ir_build_int_cast(ag, scope, node, arg0_value, arg1_value);
4488 Stage1ZirInst *result = ir_build_int_cast(ag, scope, node, arg0_value, arg1_value);
44894489 return ir_lval_wrap(ag, scope, result, lval, result_loc);
44904490 }
44914491 case BuiltinFnIdFloatCast:
44924492 {
44934493 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4494 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4494 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
44954495 if (arg0_value == ag->codegen->invalid_inst_src)
44964496 return arg0_value;
44974497
44984498 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4499 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4499 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
45004500 if (arg1_value == ag->codegen->invalid_inst_src)
45014501 return arg1_value;
45024502
4503 IrInstSrc *result = ir_build_float_cast(ag, scope, node, arg0_value, arg1_value);
4503 Stage1ZirInst *result = ir_build_float_cast(ag, scope, node, arg0_value, arg1_value);
45044504 return ir_lval_wrap(ag, scope, result, lval, result_loc);
45054505 }
45064506 case BuiltinFnIdErrSetCast:
45074507 {
45084508 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4509 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4509 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
45104510 if (arg0_value == ag->codegen->invalid_inst_src)
45114511 return arg0_value;
45124512
45134513 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4514 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4514 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
45154515 if (arg1_value == ag->codegen->invalid_inst_src)
45164516 return arg1_value;
45174517
4518 IrInstSrc *result = ir_build_err_set_cast(ag, scope, node, arg0_value, arg1_value);
4518 Stage1ZirInst *result = ir_build_err_set_cast(ag, scope, node, arg0_value, arg1_value);
45194519 return ir_lval_wrap(ag, scope, result, lval, result_loc);
45204520 }
45214521 case BuiltinFnIdIntToFloat:
45224522 {
45234523 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4524 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4524 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
45254525 if (arg0_value == ag->codegen->invalid_inst_src)
45264526 return arg0_value;
45274527
45284528 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4529 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4529 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
45304530 if (arg1_value == ag->codegen->invalid_inst_src)
45314531 return arg1_value;
45324532
4533 IrInstSrc *result = ir_build_int_to_float(ag, scope, node, arg0_value, arg1_value);
4533 Stage1ZirInst *result = ir_build_int_to_float(ag, scope, node, arg0_value, arg1_value);
45344534 return ir_lval_wrap(ag, scope, result, lval, result_loc);
45354535 }
45364536 case BuiltinFnIdFloatToInt:
45374537 {
45384538 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4539 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4539 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
45404540 if (arg0_value == ag->codegen->invalid_inst_src)
45414541 return arg0_value;
45424542
45434543 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4544 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4544 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
45454545 if (arg1_value == ag->codegen->invalid_inst_src)
45464546 return arg1_value;
45474547
4548 IrInstSrc *result = ir_build_float_to_int(ag, scope, node, arg0_value, arg1_value);
4548 Stage1ZirInst *result = ir_build_float_to_int(ag, scope, node, arg0_value, arg1_value);
45494549 return ir_lval_wrap(ag, scope, result, lval, result_loc);
45504550 }
45514551 case BuiltinFnIdErrToInt:
45524552 {
45534553 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4554 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4554 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
45554555 if (arg0_value == ag->codegen->invalid_inst_src)
45564556 return arg0_value;
45574557
4558 IrInstSrc *result = ir_build_err_to_int_src(ag, scope, node, arg0_value);
4558 Stage1ZirInst *result = ir_build_err_to_int_src(ag, scope, node, arg0_value);
45594559 return ir_lval_wrap(ag, scope, result, lval, result_loc);
45604560 }
45614561 case BuiltinFnIdIntToErr:
45624562 {
45634563 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4564 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4564 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
45654565 if (arg0_value == ag->codegen->invalid_inst_src)
45664566 return arg0_value;
45674567
4568 IrInstSrc *result = ir_build_int_to_err_src(ag, scope, node, arg0_value);
4568 Stage1ZirInst *result = ir_build_int_to_err_src(ag, scope, node, arg0_value);
45694569 return ir_lval_wrap(ag, scope, result, lval, result_loc);
45704570 }
45714571 case BuiltinFnIdBoolToInt:
45724572 {
45734573 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4574 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4574 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
45754575 if (arg0_value == ag->codegen->invalid_inst_src)
45764576 return arg0_value;
45774577
4578 IrInstSrc *result = ir_build_bool_to_int(ag, scope, node, arg0_value);
4578 Stage1ZirInst *result = ir_build_bool_to_int(ag, scope, node, arg0_value);
45794579 return ir_lval_wrap(ag, scope, result, lval, result_loc);
45804580 }
45814581 case BuiltinFnIdVectorType:
45824582 {
45834583 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4584 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4584 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
45854585 if (arg0_value == ag->codegen->invalid_inst_src)
45864586 return arg0_value;
45874587
45884588 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4589 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4589 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
45904590 if (arg1_value == ag->codegen->invalid_inst_src)
45914591 return arg1_value;
45924592
4593 IrInstSrc *vector_type = ir_build_vector_type(ag, scope, node, arg0_value, arg1_value);
4593 Stage1ZirInst *vector_type = ir_build_vector_type(ag, scope, node, arg0_value, arg1_value);
45944594 return ir_lval_wrap(ag, scope, vector_type, lval, result_loc);
45954595 }
45964596 case BuiltinFnIdShuffle:
......@@ -4599,164 +4599,164 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
45994599 Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope);
46004600
46014601 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4602 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, comptime_scope);
4602 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, comptime_scope);
46034603 if (arg0_value == ag->codegen->invalid_inst_src)
46044604 return arg0_value;
46054605
46064606 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4607 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4607 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
46084608 if (arg1_value == ag->codegen->invalid_inst_src)
46094609 return arg1_value;
46104610
46114611 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
4612 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);
4612 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
46134613 if (arg2_value == ag->codegen->invalid_inst_src)
46144614 return arg2_value;
46154615
46164616 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);
4617 IrInstSrc *arg3_value = astgen_node(ag, arg3_node, comptime_scope);
4617 Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, comptime_scope);
46184618 if (arg3_value == ag->codegen->invalid_inst_src)
46194619 return arg3_value;
46204620
4621 IrInstSrc *shuffle_vector = ir_build_shuffle_vector(ag, scope, node,
4621 Stage1ZirInst *shuffle_vector = ir_build_shuffle_vector(ag, scope, node,
46224622 arg0_value, arg1_value, arg2_value, arg3_value);
46234623 return ir_lval_wrap(ag, scope, shuffle_vector, lval, result_loc);
46244624 }
46254625 case BuiltinFnIdSplat:
46264626 {
46274627 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4628 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4628 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
46294629 if (arg0_value == ag->codegen->invalid_inst_src)
46304630 return arg0_value;
46314631
46324632 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4633 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4633 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
46344634 if (arg1_value == ag->codegen->invalid_inst_src)
46354635 return arg1_value;
46364636
4637 IrInstSrc *splat = ir_build_splat_src(ag, scope, node,
4637 Stage1ZirInst *splat = ir_build_splat_src(ag, scope, node,
46384638 arg0_value, arg1_value);
46394639 return ir_lval_wrap(ag, scope, splat, lval, result_loc);
46404640 }
46414641 case BuiltinFnIdMemcpy:
46424642 {
46434643 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4644 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4644 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
46454645 if (arg0_value == ag->codegen->invalid_inst_src)
46464646 return arg0_value;
46474647
46484648 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4649 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4649 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
46504650 if (arg1_value == ag->codegen->invalid_inst_src)
46514651 return arg1_value;
46524652
46534653 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
4654 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);
4654 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
46554655 if (arg2_value == ag->codegen->invalid_inst_src)
46564656 return arg2_value;
46574657
4658 IrInstSrc *ir_memcpy = ir_build_memcpy_src(ag, scope, node, arg0_value, arg1_value, arg2_value);
4658 Stage1ZirInst *ir_memcpy = ir_build_memcpy_src(ag, scope, node, arg0_value, arg1_value, arg2_value);
46594659 return ir_lval_wrap(ag, scope, ir_memcpy, lval, result_loc);
46604660 }
46614661 case BuiltinFnIdMemset:
46624662 {
46634663 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4664 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4664 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
46654665 if (arg0_value == ag->codegen->invalid_inst_src)
46664666 return arg0_value;
46674667
46684668 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4669 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4669 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
46704670 if (arg1_value == ag->codegen->invalid_inst_src)
46714671 return arg1_value;
46724672
46734673 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
4674 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);
4674 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
46754675 if (arg2_value == ag->codegen->invalid_inst_src)
46764676 return arg2_value;
46774677
4678 IrInstSrc *ir_memset = ir_build_memset_src(ag, scope, node, arg0_value, arg1_value, arg2_value);
4678 Stage1ZirInst *ir_memset = ir_build_memset_src(ag, scope, node, arg0_value, arg1_value, arg2_value);
46794679 return ir_lval_wrap(ag, scope, ir_memset, lval, result_loc);
46804680 }
46814681 case BuiltinFnIdWasmMemorySize:
46824682 {
46834683 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4684 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4684 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
46854685 if (arg0_value == ag->codegen->invalid_inst_src)
46864686 return arg0_value;
46874687
4688 IrInstSrc *ir_wasm_memory_size = ir_build_wasm_memory_size_src(ag, scope, node, arg0_value);
4688 Stage1ZirInst *ir_wasm_memory_size = ir_build_wasm_memory_size_src(ag, scope, node, arg0_value);
46894689 return ir_lval_wrap(ag, scope, ir_wasm_memory_size, lval, result_loc);
46904690 }
46914691 case BuiltinFnIdWasmMemoryGrow:
46924692 {
46934693 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4694 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4694 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
46954695 if (arg0_value == ag->codegen->invalid_inst_src)
46964696 return arg0_value;
46974697
46984698 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4699 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4699 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
47004700 if (arg1_value == ag->codegen->invalid_inst_src)
47014701 return arg1_value;
47024702
4703 IrInstSrc *ir_wasm_memory_grow = ir_build_wasm_memory_grow_src(ag, scope, node, arg0_value, arg1_value);
4703 Stage1ZirInst *ir_wasm_memory_grow = ir_build_wasm_memory_grow_src(ag, scope, node, arg0_value, arg1_value);
47044704 return ir_lval_wrap(ag, scope, ir_wasm_memory_grow, lval, result_loc);
47054705 }
47064706 case BuiltinFnIdField:
47074707 {
47084708 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4709 IrInstSrc *arg0_value = astgen_node_extra(ag, arg0_node, scope, LValPtr, nullptr);
4709 Stage1ZirInst *arg0_value = astgen_node_extra(ag, arg0_node, scope, LValPtr, nullptr);
47104710 if (arg0_value == ag->codegen->invalid_inst_src)
47114711 return arg0_value;
47124712
47134713 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4714 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4714 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
47154715 if (arg1_value == ag->codegen->invalid_inst_src)
47164716 return arg1_value;
47174717
4718 IrInstSrc *ptr_instruction = ir_build_field_ptr_instruction(ag, scope, node,
4718 Stage1ZirInst *ptr_instruction = ir_build_field_ptr_instruction(ag, scope, node,
47194719 arg0_value, arg1_value, false);
47204720
47214721 if (lval == LValPtr || lval == LValAssign)
47224722 return ptr_instruction;
47234723
4724 IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);
4724 Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);
47254725 return ir_expr_wrap(ag, scope, load_ptr, result_loc);
47264726 }
47274727 case BuiltinFnIdHasField:
47284728 {
47294729 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4730 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4730 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
47314731 if (arg0_value == ag->codegen->invalid_inst_src)
47324732 return arg0_value;
47334733
47344734 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4735 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4735 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
47364736 if (arg1_value == ag->codegen->invalid_inst_src)
47374737 return arg1_value;
47384738
4739 IrInstSrc *type_info = ir_build_has_field(ag, scope, node, arg0_value, arg1_value);
4739 Stage1ZirInst *type_info = ir_build_has_field(ag, scope, node, arg0_value, arg1_value);
47404740 return ir_lval_wrap(ag, scope, type_info, lval, result_loc);
47414741 }
47424742 case BuiltinFnIdTypeInfo:
47434743 {
47444744 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4745 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4745 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
47464746 if (arg0_value == ag->codegen->invalid_inst_src)
47474747 return arg0_value;
47484748
4749 IrInstSrc *type_info = ir_build_type_info(ag, scope, node, arg0_value);
4749 Stage1ZirInst *type_info = ir_build_type_info(ag, scope, node, arg0_value);
47504750 return ir_lval_wrap(ag, scope, type_info, lval, result_loc);
47514751 }
47524752 case BuiltinFnIdType:
47534753 {
47544754 AstNode *arg_node = node->data.fn_call_expr.params.at(0);
4755 IrInstSrc *arg = astgen_node(ag, arg_node, scope);
4755 Stage1ZirInst *arg = astgen_node(ag, arg_node, scope);
47564756 if (arg == ag->codegen->invalid_inst_src)
47574757 return arg;
47584758
4759 IrInstSrc *type = ir_build_type(ag, scope, node, arg);
4759 Stage1ZirInst *type = ir_build_type(ag, scope, node, arg);
47604760 return ir_lval_wrap(ag, scope, type, lval, result_loc);
47614761 }
47624762 case BuiltinFnIdBreakpoint:
......@@ -4774,30 +4774,30 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
47744774 return ir_lval_wrap(ag, scope, ir_build_handle_src(ag, scope, node), lval, result_loc);
47754775 case BuiltinFnIdFrameType: {
47764776 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4777 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4777 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
47784778 if (arg0_value == ag->codegen->invalid_inst_src)
47794779 return arg0_value;
47804780
4781 IrInstSrc *frame_type = ir_build_frame_type(ag, scope, node, arg0_value);
4781 Stage1ZirInst *frame_type = ir_build_frame_type(ag, scope, node, arg0_value);
47824782 return ir_lval_wrap(ag, scope, frame_type, lval, result_loc);
47834783 }
47844784 case BuiltinFnIdFrameSize: {
47854785 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4786 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4786 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
47874787 if (arg0_value == ag->codegen->invalid_inst_src)
47884788 return arg0_value;
47894789
4790 IrInstSrc *frame_size = ir_build_frame_size_src(ag, scope, node, arg0_value);
4790 Stage1ZirInst *frame_size = ir_build_frame_size_src(ag, scope, node, arg0_value);
47914791 return ir_lval_wrap(ag, scope, frame_size, lval, result_loc);
47924792 }
47934793 case BuiltinFnIdAlignOf:
47944794 {
47954795 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4796 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4796 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
47974797 if (arg0_value == ag->codegen->invalid_inst_src)
47984798 return arg0_value;
47994799
4800 IrInstSrc *align_of = ir_build_align_of(ag, scope, node, arg0_value);
4800 Stage1ZirInst *align_of = ir_build_align_of(ag, scope, node, arg0_value);
48014801 return ir_lval_wrap(ag, scope, align_of, lval, result_loc);
48024802 }
48034803 case BuiltinFnIdAddWithOverflow:
......@@ -4813,42 +4813,42 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
48134813 case BuiltinFnIdTypeName:
48144814 {
48154815 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4816 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4816 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
48174817 if (arg0_value == ag->codegen->invalid_inst_src)
48184818 return arg0_value;
48194819
4820 IrInstSrc *type_name = ir_build_type_name(ag, scope, node, arg0_value);
4820 Stage1ZirInst *type_name = ir_build_type_name(ag, scope, node, arg0_value);
48214821 return ir_lval_wrap(ag, scope, type_name, lval, result_loc);
48224822 }
48234823 case BuiltinFnIdPanic:
48244824 {
48254825 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4826 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4826 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
48274827 if (arg0_value == ag->codegen->invalid_inst_src)
48284828 return arg0_value;
48294829
4830 IrInstSrc *panic = ir_build_panic_src(ag, scope, node, arg0_value);
4830 Stage1ZirInst *panic = ir_build_panic_src(ag, scope, node, arg0_value);
48314831 return ir_lval_wrap(ag, scope, panic, lval, result_loc);
48324832 }
48334833 case BuiltinFnIdPtrCast:
48344834 {
48354835 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4836 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4836 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
48374837 if (arg0_value == ag->codegen->invalid_inst_src)
48384838 return arg0_value;
48394839
48404840 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4841 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4841 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
48424842 if (arg1_value == ag->codegen->invalid_inst_src)
48434843 return arg1_value;
48444844
4845 IrInstSrc *ptr_cast = ir_build_ptr_cast_src(ag, scope, node, arg0_value, arg1_value, true);
4845 Stage1ZirInst *ptr_cast = ir_build_ptr_cast_src(ag, scope, node, arg0_value, arg1_value, true);
48464846 return ir_lval_wrap(ag, scope, ptr_cast, lval, result_loc);
48474847 }
48484848 case BuiltinFnIdBitCast:
48494849 {
48504850 AstNode *dest_type_node = node->data.fn_call_expr.params.at(0);
4851 IrInstSrc *dest_type = astgen_node(ag, dest_type_node, scope);
4851 Stage1ZirInst *dest_type = astgen_node(ag, dest_type_node, scope);
48524852 if (dest_type == ag->codegen->invalid_inst_src)
48534853 return dest_type;
48544854
......@@ -4862,130 +4862,130 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
48624862 ir_build_reset_result(ag, scope, node, &result_loc_bit_cast->base);
48634863
48644864 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4865 IrInstSrc *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone,
4865 Stage1ZirInst *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone,
48664866 &result_loc_bit_cast->base);
48674867 if (arg1_value == ag->codegen->invalid_inst_src)
48684868 return arg1_value;
48694869
4870 IrInstSrc *bitcast = ir_build_bit_cast_src(ag, scope, arg1_node, arg1_value, result_loc_bit_cast);
4870 Stage1ZirInst *bitcast = ir_build_bit_cast_src(ag, scope, arg1_node, arg1_value, result_loc_bit_cast);
48714871 return ir_lval_wrap(ag, scope, bitcast, lval, result_loc);
48724872 }
48734873 case BuiltinFnIdAs:
48744874 {
48754875 AstNode *dest_type_node = node->data.fn_call_expr.params.at(0);
4876 IrInstSrc *dest_type = astgen_node(ag, dest_type_node, scope);
4876 Stage1ZirInst *dest_type = astgen_node(ag, dest_type_node, scope);
48774877 if (dest_type == ag->codegen->invalid_inst_src)
48784878 return dest_type;
48794879
48804880 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, dest_type, result_loc);
48814881
48824882 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4883 IrInstSrc *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone,
4883 Stage1ZirInst *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone,
48844884 &result_loc_cast->base);
48854885 if (arg1_value == ag->codegen->invalid_inst_src)
48864886 return arg1_value;
48874887
4888 IrInstSrc *result = ir_build_implicit_cast(ag, scope, node, arg1_value, result_loc_cast);
4888 Stage1ZirInst *result = ir_build_implicit_cast(ag, scope, node, arg1_value, result_loc_cast);
48894889 return ir_lval_wrap(ag, scope, result, lval, result_loc);
48904890 }
48914891 case BuiltinFnIdIntToPtr:
48924892 {
48934893 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4894 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4894 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
48954895 if (arg0_value == ag->codegen->invalid_inst_src)
48964896 return arg0_value;
48974897
48984898 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4899 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4899 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
49004900 if (arg1_value == ag->codegen->invalid_inst_src)
49014901 return arg1_value;
49024902
4903 IrInstSrc *int_to_ptr = ir_build_int_to_ptr_src(ag, scope, node, arg0_value, arg1_value);
4903 Stage1ZirInst *int_to_ptr = ir_build_int_to_ptr_src(ag, scope, node, arg0_value, arg1_value);
49044904 return ir_lval_wrap(ag, scope, int_to_ptr, lval, result_loc);
49054905 }
49064906 case BuiltinFnIdPtrToInt:
49074907 {
49084908 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4909 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4909 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
49104910 if (arg0_value == ag->codegen->invalid_inst_src)
49114911 return arg0_value;
49124912
4913 IrInstSrc *ptr_to_int = ir_build_ptr_to_int_src(ag, scope, node, arg0_value);
4913 Stage1ZirInst *ptr_to_int = ir_build_ptr_to_int_src(ag, scope, node, arg0_value);
49144914 return ir_lval_wrap(ag, scope, ptr_to_int, lval, result_loc);
49154915 }
49164916 case BuiltinFnIdTagName:
49174917 {
49184918 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4919 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4919 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
49204920 if (arg0_value == ag->codegen->invalid_inst_src)
49214921 return arg0_value;
49224922
4923 IrInstSrc *tag_name = ir_build_tag_name_src(ag, scope, node, arg0_value);
4923 Stage1ZirInst *tag_name = ir_build_tag_name_src(ag, scope, node, arg0_value);
49244924 return ir_lval_wrap(ag, scope, tag_name, lval, result_loc);
49254925 }
49264926 case BuiltinFnIdFieldParentPtr:
49274927 {
49284928 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4929 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4929 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
49304930 if (arg0_value == ag->codegen->invalid_inst_src)
49314931 return arg0_value;
49324932
49334933 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4934 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4934 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
49354935 if (arg1_value == ag->codegen->invalid_inst_src)
49364936 return arg1_value;
49374937
49384938 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
4939 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);
4939 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
49404940 if (arg2_value == ag->codegen->invalid_inst_src)
49414941 return arg2_value;
49424942
4943 IrInstSrc *field_parent_ptr = ir_build_field_parent_ptr_src(ag, scope, node,
4943 Stage1ZirInst *field_parent_ptr = ir_build_field_parent_ptr_src(ag, scope, node,
49444944 arg0_value, arg1_value, arg2_value);
49454945 return ir_lval_wrap(ag, scope, field_parent_ptr, lval, result_loc);
49464946 }
49474947 case BuiltinFnIdOffsetOf:
49484948 {
49494949 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4950 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4950 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
49514951 if (arg0_value == ag->codegen->invalid_inst_src)
49524952 return arg0_value;
49534953
49544954 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4955 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4955 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
49564956 if (arg1_value == ag->codegen->invalid_inst_src)
49574957 return arg1_value;
49584958
4959 IrInstSrc *offset_of = ir_build_offset_of(ag, scope, node, arg0_value, arg1_value);
4959 Stage1ZirInst *offset_of = ir_build_offset_of(ag, scope, node, arg0_value, arg1_value);
49604960 return ir_lval_wrap(ag, scope, offset_of, lval, result_loc);
49614961 }
49624962 case BuiltinFnIdBitOffsetOf:
49634963 {
49644964 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
4965 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
4965 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
49664966 if (arg0_value == ag->codegen->invalid_inst_src)
49674967 return arg0_value;
49684968
49694969 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
4970 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
4970 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
49714971 if (arg1_value == ag->codegen->invalid_inst_src)
49724972 return arg1_value;
49734973
4974 IrInstSrc *offset_of = ir_build_bit_offset_of(ag, scope, node, arg0_value, arg1_value);
4974 Stage1ZirInst *offset_of = ir_build_bit_offset_of(ag, scope, node, arg0_value, arg1_value);
49754975 return ir_lval_wrap(ag, scope, offset_of, lval, result_loc);
49764976 }
49774977 case BuiltinFnIdCall: {
49784978 // Cast the options parameter to the options type
49794979 ZigType *options_type = get_builtin_type(ag->codegen, "CallOptions");
4980 IrInstSrc *options_type_inst = ir_build_const_type(ag, scope, node, options_type);
4980 Stage1ZirInst *options_type_inst = ir_build_const_type(ag, scope, node, options_type);
49814981 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc());
49824982
49834983 AstNode *options_node = node->data.fn_call_expr.params.at(0);
4984 IrInstSrc *options_inner = astgen_node_extra(ag, options_node, scope,
4984 Stage1ZirInst *options_inner = astgen_node_extra(ag, options_node, scope,
49854985 LValNone, &result_loc_cast->base);
49864986 if (options_inner == ag->codegen->invalid_inst_src)
49874987 return options_inner;
4988 IrInstSrc *options = ir_build_implicit_cast(ag, scope, options_node, options_inner, result_loc_cast);
4988 Stage1ZirInst *options = ir_build_implicit_cast(ag, scope, options_node, options_inner, result_loc_cast);
49894989
49904990 AstNode *fn_ref_node = node->data.fn_call_expr.params.at(1);
49914991 AstNode *args_node = node->data.fn_call_expr.params.at(2);
......@@ -5004,15 +5004,15 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
50045004 return ag->codegen->invalid_inst_src;
50055005 }
50065006 } else {
5007 IrInstSrc *fn_ref = astgen_node(ag, fn_ref_node, scope);
5007 Stage1ZirInst *fn_ref = astgen_node(ag, fn_ref_node, scope);
50085008 if (fn_ref == ag->codegen->invalid_inst_src)
50095009 return fn_ref;
50105010
5011 IrInstSrc *args = astgen_node(ag, args_node, scope);
5011 Stage1ZirInst *args = astgen_node(ag, args_node, scope);
50125012 if (args == ag->codegen->invalid_inst_src)
50135013 return args;
50145014
5015 IrInstSrc *call = ir_build_call_extra(ag, scope, node, options, fn_ref, args, result_loc);
5015 Stage1ZirInst *call = ir_build_call_extra(ag, scope, node, options, fn_ref, args, result_loc);
50165016 return ir_lval_wrap(ag, scope, call, lval, result_loc);
50175017 }
50185018 }
......@@ -5021,227 +5021,227 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
50215021 case BuiltinFnIdShlExact:
50225022 {
50235023 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5024 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5024 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
50255025 if (arg0_value == ag->codegen->invalid_inst_src)
50265026 return arg0_value;
50275027
50285028 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5029 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
5029 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
50305030 if (arg1_value == ag->codegen->invalid_inst_src)
50315031 return arg1_value;
50325032
5033 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftLeftExact, arg0_value, arg1_value, true);
5033 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftLeftExact, arg0_value, arg1_value, true);
50345034 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
50355035 }
50365036 case BuiltinFnIdShrExact:
50375037 {
50385038 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5039 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5039 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
50405040 if (arg0_value == ag->codegen->invalid_inst_src)
50415041 return arg0_value;
50425042
50435043 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5044 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
5044 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
50455045 if (arg1_value == ag->codegen->invalid_inst_src)
50465046 return arg1_value;
50475047
5048 IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftRightExact, arg0_value, arg1_value, true);
5048 Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftRightExact, arg0_value, arg1_value, true);
50495049 return ir_lval_wrap(ag, scope, bin_op, lval, result_loc);
50505050 }
50515051 case BuiltinFnIdSetEvalBranchQuota:
50525052 {
50535053 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5054 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5054 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
50555055 if (arg0_value == ag->codegen->invalid_inst_src)
50565056 return arg0_value;
50575057
5058 IrInstSrc *set_eval_branch_quota = ir_build_set_eval_branch_quota(ag, scope, node, arg0_value);
5058 Stage1ZirInst *set_eval_branch_quota = ir_build_set_eval_branch_quota(ag, scope, node, arg0_value);
50595059 return ir_lval_wrap(ag, scope, set_eval_branch_quota, lval, result_loc);
50605060 }
50615061 case BuiltinFnIdAlignCast:
50625062 {
50635063 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5064 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5064 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
50655065 if (arg0_value == ag->codegen->invalid_inst_src)
50665066 return arg0_value;
50675067
50685068 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5069 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
5069 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
50705070 if (arg1_value == ag->codegen->invalid_inst_src)
50715071 return arg1_value;
50725072
5073 IrInstSrc *align_cast = ir_build_align_cast_src(ag, scope, node, arg0_value, arg1_value);
5073 Stage1ZirInst *align_cast = ir_build_align_cast_src(ag, scope, node, arg0_value, arg1_value);
50745074 return ir_lval_wrap(ag, scope, align_cast, lval, result_loc);
50755075 }
50765076 case BuiltinFnIdThis:
50775077 {
5078 IrInstSrc *this_inst = astgen_this(ag, scope, node);
5078 Stage1ZirInst *this_inst = astgen_this(ag, scope, node);
50795079 return ir_lval_wrap(ag, scope, this_inst, lval, result_loc);
50805080 }
50815081 case BuiltinFnIdSetAlignStack:
50825082 {
50835083 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5084 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5084 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
50855085 if (arg0_value == ag->codegen->invalid_inst_src)
50865086 return arg0_value;
50875087
5088 IrInstSrc *set_align_stack = ir_build_set_align_stack(ag, scope, node, arg0_value);
5088 Stage1ZirInst *set_align_stack = ir_build_set_align_stack(ag, scope, node, arg0_value);
50895089 return ir_lval_wrap(ag, scope, set_align_stack, lval, result_loc);
50905090 }
50915091 case BuiltinFnIdExport:
50925092 {
50935093 // Cast the options parameter to the options type
50945094 ZigType *options_type = get_builtin_type(ag->codegen, "ExportOptions");
5095 IrInstSrc *options_type_inst = ir_build_const_type(ag, scope, node, options_type);
5095 Stage1ZirInst *options_type_inst = ir_build_const_type(ag, scope, node, options_type);
50965096 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc());
50975097
50985098 AstNode *target_node = node->data.fn_call_expr.params.at(0);
5099 IrInstSrc *target_value = astgen_node(ag, target_node, scope);
5099 Stage1ZirInst *target_value = astgen_node(ag, target_node, scope);
51005100 if (target_value == ag->codegen->invalid_inst_src)
51015101 return target_value;
51025102
51035103 AstNode *options_node = node->data.fn_call_expr.params.at(1);
5104 IrInstSrc *options_value = astgen_node_extra(ag, options_node,
5104 Stage1ZirInst *options_value = astgen_node_extra(ag, options_node,
51055105 scope, LValNone, &result_loc_cast->base);
51065106 if (options_value == ag->codegen->invalid_inst_src)
51075107 return options_value;
51085108
5109 IrInstSrc *casted_options_value = ir_build_implicit_cast(
5109 Stage1ZirInst *casted_options_value = ir_build_implicit_cast(
51105110 ag, scope, options_node, options_value, result_loc_cast);
51115111
5112 IrInstSrc *ir_export = ir_build_export(ag, scope, node, target_value, casted_options_value);
5112 Stage1ZirInst *ir_export = ir_build_export(ag, scope, node, target_value, casted_options_value);
51135113 return ir_lval_wrap(ag, scope, ir_export, lval, result_loc);
51145114 }
51155115 case BuiltinFnIdExtern:
51165116 {
51175117 // Cast the options parameter to the options type
51185118 ZigType *options_type = get_builtin_type(ag->codegen, "ExternOptions");
5119 IrInstSrc *options_type_inst = ir_build_const_type(ag, scope, node, options_type);
5119 Stage1ZirInst *options_type_inst = ir_build_const_type(ag, scope, node, options_type);
51205120 ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc());
51215121
51225122 AstNode *type_node = node->data.fn_call_expr.params.at(0);
5123 IrInstSrc *type_value = astgen_node(ag, type_node, scope);
5123 Stage1ZirInst *type_value = astgen_node(ag, type_node, scope);
51245124 if (type_value == ag->codegen->invalid_inst_src)
51255125 return type_value;
51265126
51275127 AstNode *options_node = node->data.fn_call_expr.params.at(1);
5128 IrInstSrc *options_value = astgen_node_extra(ag, options_node,
5128 Stage1ZirInst *options_value = astgen_node_extra(ag, options_node,
51295129 scope, LValNone, &result_loc_cast->base);
51305130 if (options_value == ag->codegen->invalid_inst_src)
51315131 return options_value;
51325132
5133 IrInstSrc *casted_options_value = ir_build_implicit_cast(
5133 Stage1ZirInst *casted_options_value = ir_build_implicit_cast(
51345134 ag, scope, options_node, options_value, result_loc_cast);
51355135
5136 IrInstSrc *ir_extern = ir_build_extern(ag, scope, node, type_value, casted_options_value);
5136 Stage1ZirInst *ir_extern = ir_build_extern(ag, scope, node, type_value, casted_options_value);
51375137 return ir_lval_wrap(ag, scope, ir_extern, lval, result_loc);
51385138 }
51395139 case BuiltinFnIdErrorReturnTrace:
51405140 {
5141 IrInstSrc *error_return_trace = ir_build_error_return_trace_src(ag, scope, node,
5141 Stage1ZirInst *error_return_trace = ir_build_error_return_trace_src(ag, scope, node,
51425142 IrInstErrorReturnTraceNull);
51435143 return ir_lval_wrap(ag, scope, error_return_trace, lval, result_loc);
51445144 }
51455145 case BuiltinFnIdAtomicRmw:
51465146 {
51475147 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5148 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5148 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
51495149 if (arg0_value == ag->codegen->invalid_inst_src)
51505150 return arg0_value;
51515151
51525152 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5153 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
5153 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
51545154 if (arg1_value == ag->codegen->invalid_inst_src)
51555155 return arg1_value;
51565156
51575157 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
5158 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);
5158 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
51595159 if (arg2_value == ag->codegen->invalid_inst_src)
51605160 return arg2_value;
51615161
51625162 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);
5163 IrInstSrc *arg3_value = astgen_node(ag, arg3_node, scope);
5163 Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, scope);
51645164 if (arg3_value == ag->codegen->invalid_inst_src)
51655165 return arg3_value;
51665166
51675167 AstNode *arg4_node = node->data.fn_call_expr.params.at(4);
5168 IrInstSrc *arg4_value = astgen_node(ag, arg4_node, scope);
5168 Stage1ZirInst *arg4_value = astgen_node(ag, arg4_node, scope);
51695169 if (arg4_value == ag->codegen->invalid_inst_src)
51705170 return arg4_value;
51715171
5172 IrInstSrc *inst = ir_build_atomic_rmw_src(ag, scope, node,
5172 Stage1ZirInst *inst = ir_build_atomic_rmw_src(ag, scope, node,
51735173 arg0_value, arg1_value, arg2_value, arg3_value, arg4_value);
51745174 return ir_lval_wrap(ag, scope, inst, lval, result_loc);
51755175 }
51765176 case BuiltinFnIdAtomicLoad:
51775177 {
51785178 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5179 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5179 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
51805180 if (arg0_value == ag->codegen->invalid_inst_src)
51815181 return arg0_value;
51825182
51835183 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5184 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
5184 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
51855185 if (arg1_value == ag->codegen->invalid_inst_src)
51865186 return arg1_value;
51875187
51885188 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
5189 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);
5189 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
51905190 if (arg2_value == ag->codegen->invalid_inst_src)
51915191 return arg2_value;
51925192
5193 IrInstSrc *inst = ir_build_atomic_load_src(ag, scope, node, arg0_value, arg1_value, arg2_value);
5193 Stage1ZirInst *inst = ir_build_atomic_load_src(ag, scope, node, arg0_value, arg1_value, arg2_value);
51945194 return ir_lval_wrap(ag, scope, inst, lval, result_loc);
51955195 }
51965196 case BuiltinFnIdAtomicStore:
51975197 {
51985198 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5199 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5199 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
52005200 if (arg0_value == ag->codegen->invalid_inst_src)
52015201 return arg0_value;
52025202
52035203 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5204 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
5204 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
52055205 if (arg1_value == ag->codegen->invalid_inst_src)
52065206 return arg1_value;
52075207
52085208 AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
5209 IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope);
5209 Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
52105210 if (arg2_value == ag->codegen->invalid_inst_src)
52115211 return arg2_value;
52125212
52135213 AstNode *arg3_node = node->data.fn_call_expr.params.at(3);
5214 IrInstSrc *arg3_value = astgen_node(ag, arg3_node, scope);
5214 Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, scope);
52155215 if (arg3_value == ag->codegen->invalid_inst_src)
52165216 return arg3_value;
52175217
5218 IrInstSrc *inst = ir_build_atomic_store_src(ag, scope, node, arg0_value, arg1_value,
5218 Stage1ZirInst *inst = ir_build_atomic_store_src(ag, scope, node, arg0_value, arg1_value,
52195219 arg2_value, arg3_value);
52205220 return ir_lval_wrap(ag, scope, inst, lval, result_loc);
52215221 }
52225222 case BuiltinFnIdIntToEnum:
52235223 {
52245224 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5225 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5225 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
52265226 if (arg0_value == ag->codegen->invalid_inst_src)
52275227 return arg0_value;
52285228
52295229 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5230 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
5230 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
52315231 if (arg1_value == ag->codegen->invalid_inst_src)
52325232 return arg1_value;
52335233
5234 IrInstSrc *result = ir_build_int_to_enum_src(ag, scope, node, arg0_value, arg1_value);
5234 Stage1ZirInst *result = ir_build_int_to_enum_src(ag, scope, node, arg0_value, arg1_value);
52355235 return ir_lval_wrap(ag, scope, result, lval, result_loc);
52365236 }
52375237 case BuiltinFnIdEnumToInt:
52385238 {
52395239 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5240 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5240 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
52415241 if (arg0_value == ag->codegen->invalid_inst_src)
52425242 return arg0_value;
52435243
5244 IrInstSrc *result = ir_build_enum_to_int(ag, scope, node, arg0_value);
5244 Stage1ZirInst *result = ir_build_enum_to_int(ag, scope, node, arg0_value);
52455245 return ir_lval_wrap(ag, scope, result, lval, result_loc);
52465246 }
52475247 case BuiltinFnIdCtz:
......@@ -5251,16 +5251,16 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
52515251 case BuiltinFnIdBitReverse:
52525252 {
52535253 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5254 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5254 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
52555255 if (arg0_value == ag->codegen->invalid_inst_src)
52565256 return arg0_value;
52575257
52585258 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5259 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
5259 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
52605260 if (arg1_value == ag->codegen->invalid_inst_src)
52615261 return arg1_value;
52625262
5263 IrInstSrc *result;
5263 Stage1ZirInst *result;
52645264 switch (builtin_fn->id) {
52655265 case BuiltinFnIdCtz:
52665266 result = ir_build_ctz(ag, scope, node, arg0_value, arg1_value);
......@@ -5285,27 +5285,27 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
52855285 case BuiltinFnIdHasDecl:
52865286 {
52875287 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
5288 IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope);
5288 Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope);
52895289 if (arg0_value == ag->codegen->invalid_inst_src)
52905290 return arg0_value;
52915291
52925292 AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
5293 IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope);
5293 Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
52945294 if (arg1_value == ag->codegen->invalid_inst_src)
52955295 return arg1_value;
52965296
5297 IrInstSrc *has_decl = ir_build_has_decl(ag, scope, node, arg0_value, arg1_value);
5297 Stage1ZirInst *has_decl = ir_build_has_decl(ag, scope, node, arg0_value, arg1_value);
52985298 return ir_lval_wrap(ag, scope, has_decl, lval, result_loc);
52995299 }
53005300 case BuiltinFnIdUnionInit:
53015301 {
53025302 AstNode *union_type_node = node->data.fn_call_expr.params.at(0);
5303 IrInstSrc *union_type_inst = astgen_node(ag, union_type_node, scope);
5303 Stage1ZirInst *union_type_inst = astgen_node(ag, union_type_node, scope);
53045304 if (union_type_inst == ag->codegen->invalid_inst_src)
53055305 return union_type_inst;
53065306
53075307 AstNode *name_node = node->data.fn_call_expr.params.at(1);
5308 IrInstSrc *name_inst = astgen_node(ag, name_node, scope);
5308 Stage1ZirInst *name_inst = astgen_node(ag, name_node, scope);
53095309 if (name_inst == ag->codegen->invalid_inst_src)
53105310 return name_inst;
53115311
......@@ -5316,7 +5316,7 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode
53165316 }
53175317 case BuiltinFnIdSrc:
53185318 {
5319 IrInstSrc *src_inst = ir_build_src(ag, scope, node);
5319 Stage1ZirInst *src_inst = ir_build_src(ag, scope, node);
53205320 return ir_lval_wrap(ag, scope, src_inst, lval, result_loc);
53215321 }
53225322 }
......@@ -5335,7 +5335,7 @@ static ScopeNoSuspend *get_scope_nosuspend(Scope *scope) {
53355335 return nullptr;
53365336}
53375337
5338static IrInstSrc *astgen_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
5338static Stage1ZirInst *astgen_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
53395339 ResultLoc *result_loc)
53405340{
53415341 assert(node->type == NodeTypeFnCallExpr);
......@@ -5354,16 +5354,16 @@ static IrInstSrc *astgen_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node,
53545354 nullptr, node->data.fn_call_expr.params.items, node->data.fn_call_expr.params.length, lval, result_loc);
53555355}
53565356
5357static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
5357static Stage1ZirInst *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
53585358 ResultLoc *result_loc)
53595359{
53605360 assert(node->type == NodeTypeIfBoolExpr);
53615361
5362 IrInstSrc *condition = astgen_node(ag, node->data.if_bool_expr.condition, scope);
5362 Stage1ZirInst *condition = astgen_node(ag, node->data.if_bool_expr.condition, scope);
53635363 if (condition == ag->codegen->invalid_inst_src)
53645364 return ag->codegen->invalid_inst_src;
53655365
5366 IrInstSrc *is_comptime;
5366 Stage1ZirInst *is_comptime;
53675367 if (ir_should_inline(ag->exec, scope)) {
53685368 is_comptime = ir_build_const_bool(ag, scope, node, true);
53695369 } else {
......@@ -5377,7 +5377,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
53775377 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "Else");
53785378 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "EndIf");
53795379
5380 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, condition,
5380 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, scope, node, condition,
53815381 then_block, else_block, is_comptime);
53825382 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block,
53835383 result_loc, is_comptime);
......@@ -5385,7 +5385,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
53855385 ir_set_cursor_at_end_and_append_block(ag, then_block);
53865386
53875387 Scope *subexpr_scope = create_runtime_scope(ag->codegen, node, scope, is_comptime);
5388 IrInstSrc *then_expr_result = astgen_node_extra(ag, then_node, subexpr_scope, lval,
5388 Stage1ZirInst *then_expr_result = astgen_node_extra(ag, then_node, subexpr_scope, lval,
53895389 &peer_parent->peers.at(0)->base);
53905390 if (then_expr_result == ag->codegen->invalid_inst_src)
53915391 return ag->codegen->invalid_inst_src;
......@@ -5394,7 +5394,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
53945394 ir_build_br(ag, scope, node, endif_block, is_comptime);
53955395
53965396 ir_set_cursor_at_end_and_append_block(ag, else_block);
5397 IrInstSrc *else_expr_result;
5397 Stage1ZirInst *else_expr_result;
53985398 if (else_node) {
53995399 else_expr_result = astgen_node_extra(ag, else_node, subexpr_scope, lval, &peer_parent->peers.at(1)->base);
54005400 if (else_expr_result == ag->codegen->invalid_inst_src)
......@@ -5408,39 +5408,39 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
54085408 ir_build_br(ag, scope, node, endif_block, is_comptime);
54095409
54105410 ir_set_cursor_at_end_and_append_block(ag, endif_block);
5411 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
5411 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
54125412 incoming_values[0] = then_expr_result;
54135413 incoming_values[1] = else_expr_result;
54145414 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
54155415 incoming_blocks[0] = after_then_block;
54165416 incoming_blocks[1] = after_else_block;
54175417
5418 IrInstSrc *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);
5418 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);
54195419 return ir_expr_wrap(ag, scope, phi, result_loc);
54205420}
54215421
5422static IrInstSrc *astgen_prefix_op_id_lval(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id, LVal lval) {
5422static Stage1ZirInst *astgen_prefix_op_id_lval(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id, LVal lval) {
54235423 assert(node->type == NodeTypePrefixOpExpr);
54245424 AstNode *expr_node = node->data.prefix_op_expr.primary_expr;
54255425
5426 IrInstSrc *value = astgen_node_extra(ag, expr_node, scope, lval, nullptr);
5426 Stage1ZirInst *value = astgen_node_extra(ag, expr_node, scope, lval, nullptr);
54275427 if (value == ag->codegen->invalid_inst_src)
54285428 return value;
54295429
54305430 return ir_build_un_op(ag, scope, node, op_id, value);
54315431}
54325432
5433static IrInstSrc *astgen_prefix_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id) {
5433static Stage1ZirInst *astgen_prefix_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id) {
54345434 return astgen_prefix_op_id_lval(ag, scope, node, op_id, LValNone);
54355435}
54365436
5437static IrInstSrc *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *inst, ResultLoc *result_loc) {
5437static Stage1ZirInst *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *inst, ResultLoc *result_loc) {
54385438 if (inst == ag->codegen->invalid_inst_src) return inst;
54395439 ir_build_end_expr(ag, scope, inst->source_node, inst, result_loc);
54405440 return inst;
54415441}
54425442
5443static IrInstSrc *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *value, LVal lval,
5443static Stage1ZirInst *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *value, LVal lval,
54445444 ResultLoc *result_loc)
54455445{
54465446 // This logic must be kept in sync with
......@@ -5448,7 +5448,7 @@ static IrInstSrc *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *value,
54485448 if (value == ag->codegen->invalid_inst_src ||
54495449 instr_is_unreachable(value) ||
54505450 value->source_node->type == NodeTypeDefer ||
5451 value->id == IrInstSrcIdDeclVar)
5451 value->id == Stage1ZirInstIdDeclVar)
54525452 {
54535453 return value;
54545454 }
......@@ -5500,7 +5500,7 @@ static Error token_number_literal_u32(Stage1AstGen *ag, AstNode *source_node,
55005500
55015501}
55025502
5503static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
5503static Stage1ZirInst *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
55045504 Error err;
55055505 assert(node->type == NodeTypePointerType);
55065506
......@@ -5515,7 +5515,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n
55155515 AstNode *expr_node = node->data.pointer_type.op_expr;
55165516 AstNode *align_expr = node->data.pointer_type.align_expr;
55175517
5518 IrInstSrc *sentinel;
5518 Stage1ZirInst *sentinel;
55195519 if (sentinel_expr != nullptr) {
55205520 sentinel = astgen_node(ag, sentinel_expr, scope);
55215521 if (sentinel == ag->codegen->invalid_inst_src)
......@@ -5524,7 +5524,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n
55245524 sentinel = nullptr;
55255525 }
55265526
5527 IrInstSrc *align_value;
5527 Stage1ZirInst *align_value;
55285528 if (align_expr != nullptr) {
55295529 align_value = astgen_node(ag, align_expr, scope);
55305530 if (align_value == ag->codegen->invalid_inst_src)
......@@ -5533,7 +5533,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n
55335533 align_value = nullptr;
55345534 }
55355535
5536 IrInstSrc *child_type = astgen_node(ag, expr_node, scope);
5536 Stage1ZirInst *child_type = astgen_node(ag, expr_node, scope);
55375537 if (child_type == ag->codegen->invalid_inst_src)
55385538 return child_type;
55395539
......@@ -5565,36 +5565,36 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n
55655565 ptr_len, sentinel, align_value, bit_offset_start, host_int_bytes, is_allow_zero);
55665566}
55675567
5568static IrInstSrc *astgen_catch_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
5568static Stage1ZirInst *astgen_catch_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
55695569 AstNode *expr_node, LVal lval, ResultLoc *result_loc)
55705570{
5571 IrInstSrc *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
5571 Stage1ZirInst *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
55725572 if (err_union_ptr == ag->codegen->invalid_inst_src)
55735573 return ag->codegen->invalid_inst_src;
55745574
5575 IrInstSrc *payload_ptr = ir_build_unwrap_err_payload_src(ag, scope, source_node, err_union_ptr, true, false);
5575 Stage1ZirInst *payload_ptr = ir_build_unwrap_err_payload_src(ag, scope, source_node, err_union_ptr, true, false);
55765576 if (payload_ptr == ag->codegen->invalid_inst_src)
55775577 return ag->codegen->invalid_inst_src;
55785578
55795579 if (lval == LValPtr)
55805580 return payload_ptr;
55815581
5582 IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, source_node, payload_ptr);
5582 Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, source_node, payload_ptr);
55835583 return ir_expr_wrap(ag, scope, load_ptr, result_loc);
55845584}
55855585
5586static IrInstSrc *astgen_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *node) {
5586static Stage1ZirInst *astgen_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *node) {
55875587 assert(node->type == NodeTypePrefixOpExpr);
55885588 AstNode *expr_node = node->data.prefix_op_expr.primary_expr;
55895589
5590 IrInstSrc *value = astgen_node(ag, expr_node, scope);
5590 Stage1ZirInst *value = astgen_node(ag, expr_node, scope);
55915591 if (value == ag->codegen->invalid_inst_src)
55925592 return ag->codegen->invalid_inst_src;
55935593
55945594 return ir_build_bool_not(ag, scope, node, value);
55955595}
55965596
5597static IrInstSrc *astgen_prefix_op_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
5597static Stage1ZirInst *astgen_prefix_op_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
55985598 ResultLoc *result_loc)
55995599{
56005600 assert(node->type == NodeTypePrefixOpExpr);
......@@ -5622,12 +5622,12 @@ static IrInstSrc *astgen_prefix_op_expr(Stage1AstGen *ag, Scope *scope, AstNode
56225622 zig_unreachable();
56235623}
56245624
5625static IrInstSrc *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
5626 IrInstSrc *union_type, IrInstSrc *field_name, AstNode *expr_node,
5625static Stage1ZirInst *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
5626 Stage1ZirInst *union_type, Stage1ZirInst *field_name, AstNode *expr_node,
56275627 LVal lval, ResultLoc *parent_result_loc)
56285628{
5629 IrInstSrc *container_ptr = ir_build_resolve_result(ag, scope, source_node, parent_result_loc, union_type);
5630 IrInstSrc *field_ptr = ir_build_field_ptr_instruction(ag, scope, source_node, container_ptr,
5629 Stage1ZirInst *container_ptr = ir_build_resolve_result(ag, scope, source_node, parent_result_loc, union_type);
5630 Stage1ZirInst *field_ptr = ir_build_field_ptr_instruction(ag, scope, source_node, container_ptr,
56315631 field_name, true);
56325632
56335633 ResultLocInstruction *result_loc_inst = heap::c_allocator.create<ResultLocInstruction>();
......@@ -5636,18 +5636,18 @@ static IrInstSrc *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode
56365636 ir_ref_instruction(field_ptr, ag->current_basic_block);
56375637 ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base);
56385638
5639 IrInstSrc *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,
5639 Stage1ZirInst *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,
56405640 &result_loc_inst->base);
56415641 if (expr_value == ag->codegen->invalid_inst_src)
56425642 return expr_value;
56435643
5644 IrInstSrc *init_union = ir_build_union_init_named_field(ag, scope, source_node, union_type,
5644 Stage1ZirInst *init_union = ir_build_union_init_named_field(ag, scope, source_node, union_type,
56455645 field_name, field_ptr, container_ptr);
56465646
56475647 return ir_lval_wrap(ag, scope, init_union, lval, parent_result_loc);
56485648}
56495649
5650static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
5650static Stage1ZirInst *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
56515651 ResultLoc *parent_result_loc)
56525652{
56535653 assert(node->type == NodeTypeContainerInitExpr);
......@@ -5659,14 +5659,14 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
56595659 ResultLoc *child_result_loc;
56605660 AstNode *init_array_type_source_node;
56615661 if (container_init_expr->type != nullptr) {
5662 IrInstSrc *container_type;
5662 Stage1ZirInst *container_type;
56635663 if (container_init_expr->type->type == NodeTypeInferredArrayType) {
56645664 if (kind == ContainerInitKindStruct) {
56655665 add_node_error(ag->codegen, container_init_expr->type,
56665666 buf_sprintf("initializing array with struct syntax"));
56675667 return ag->codegen->invalid_inst_src;
56685668 }
5669 IrInstSrc *sentinel;
5669 Stage1ZirInst *sentinel;
56705670 if (container_init_expr->type->data.inferred_array_type.sentinel != nullptr) {
56715671 sentinel = astgen_node(ag, container_init_expr->type->data.inferred_array_type.sentinel, scope);
56725672 if (sentinel == ag->codegen->invalid_inst_src)
......@@ -5675,12 +5675,12 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
56755675 sentinel = nullptr;
56765676 }
56775677
5678 IrInstSrc *elem_type = astgen_node(ag,
5678 Stage1ZirInst *elem_type = astgen_node(ag,
56795679 container_init_expr->type->data.inferred_array_type.child_type, scope);
56805680 if (elem_type == ag->codegen->invalid_inst_src)
56815681 return elem_type;
56825682 size_t item_count = container_init_expr->entries.length;
5683 IrInstSrc *item_count_inst = ir_build_const_usize(ag, scope, node, item_count);
5683 Stage1ZirInst *item_count_inst = ir_build_const_usize(ag, scope, node, item_count);
56845684 container_type = ir_build_array_type(ag, scope, node, item_count_inst, sentinel, elem_type);
56855685 } else {
56865686 container_type = astgen_node(ag, container_init_expr->type, scope);
......@@ -5702,11 +5702,11 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
57025702
57035703 switch (kind) {
57045704 case ContainerInitKindStruct: {
5705 IrInstSrc *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc,
5705 Stage1ZirInst *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc,
57065706 nullptr);
57075707
57085708 size_t field_count = container_init_expr->entries.length;
5709 IrInstSrcContainerInitFieldsField *fields = heap::c_allocator.allocate<IrInstSrcContainerInitFieldsField>(field_count);
5709 Stage1ZirInstContainerInitFieldsField *fields = heap::c_allocator.allocate<Stage1ZirInstContainerInitFieldsField>(field_count);
57105710 for (size_t i = 0; i < field_count; i += 1) {
57115711 AstNode *entry_node = container_init_expr->entries.at(i);
57125712 assert(entry_node->type == NodeTypeStructValueField);
......@@ -5714,7 +5714,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
57145714 Buf *name = entry_node->data.struct_val_field.name;
57155715 AstNode *expr_node = entry_node->data.struct_val_field.expr;
57165716
5717 IrInstSrc *field_ptr = ir_build_field_ptr(ag, scope, entry_node, container_ptr, name, true);
5717 Stage1ZirInst *field_ptr = ir_build_field_ptr(ag, scope, entry_node, container_ptr, name, true);
57185718 ResultLocInstruction *result_loc_inst = heap::c_allocator.create<ResultLocInstruction>();
57195719 result_loc_inst->base.id = ResultLocIdInstruction;
57205720 result_loc_inst->base.source_instruction = field_ptr;
......@@ -5722,7 +5722,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
57225722 ir_ref_instruction(field_ptr, ag->current_basic_block);
57235723 ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base);
57245724
5725 IrInstSrc *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,
5725 Stage1ZirInst *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,
57265726 &result_loc_inst->base);
57275727 if (expr_value == ag->codegen->invalid_inst_src)
57285728 return expr_value;
......@@ -5731,7 +5731,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
57315731 fields[i].source_node = entry_node;
57325732 fields[i].result_loc = field_ptr;
57335733 }
5734 IrInstSrc *result = ir_build_container_init_fields(ag, scope, node, field_count,
5734 Stage1ZirInst *result = ir_build_container_init_fields(ag, scope, node, field_count,
57355735 fields, container_ptr);
57365736
57375737 if (result_loc_cast != nullptr) {
......@@ -5742,15 +5742,15 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
57425742 case ContainerInitKindArray: {
57435743 size_t item_count = container_init_expr->entries.length;
57445744
5745 IrInstSrc *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc,
5745 Stage1ZirInst *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc,
57465746 nullptr);
57475747
5748 IrInstSrc **result_locs = heap::c_allocator.allocate<IrInstSrc *>(item_count);
5748 Stage1ZirInst **result_locs = heap::c_allocator.allocate<Stage1ZirInst *>(item_count);
57495749 for (size_t i = 0; i < item_count; i += 1) {
57505750 AstNode *expr_node = container_init_expr->entries.at(i);
57515751
5752 IrInstSrc *elem_index = ir_build_const_usize(ag, scope, expr_node, i);
5753 IrInstSrc *elem_ptr = ir_build_elem_ptr(ag, scope, expr_node, container_ptr,
5752 Stage1ZirInst *elem_index = ir_build_const_usize(ag, scope, expr_node, i);
5753 Stage1ZirInst *elem_ptr = ir_build_elem_ptr(ag, scope, expr_node, container_ptr,
57545754 elem_index, false, PtrLenSingle, init_array_type_source_node);
57555755 ResultLocInstruction *result_loc_inst = heap::c_allocator.create<ResultLocInstruction>();
57565756 result_loc_inst->base.id = ResultLocIdInstruction;
......@@ -5759,14 +5759,14 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
57595759 ir_ref_instruction(elem_ptr, ag->current_basic_block);
57605760 ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base);
57615761
5762 IrInstSrc *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,
5762 Stage1ZirInst *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone,
57635763 &result_loc_inst->base);
57645764 if (expr_value == ag->codegen->invalid_inst_src)
57655765 return expr_value;
57665766
57675767 result_locs[i] = elem_ptr;
57685768 }
5769 IrInstSrc *result = ir_build_container_init_list(ag, scope, node, item_count,
5769 Stage1ZirInst *result = ir_build_container_init_list(ag, scope, node, item_count,
57705770 result_locs, container_ptr, init_array_type_source_node);
57715771 if (result_loc_cast != nullptr) {
57725772 result = ir_build_implicit_cast(ag, scope, node, result, result_loc_cast);
......@@ -5777,7 +5777,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast
57775777 zig_unreachable();
57785778}
57795779
5780static ResultLocVar *ir_build_var_result_loc(Stage1AstGen *ag, IrInstSrc *alloca, ZigVar *var) {
5780static ResultLocVar *ir_build_var_result_loc(Stage1AstGen *ag, Stage1ZirInst *alloca, ZigVar *var) {
57815781 ResultLocVar *result_loc_var = heap::c_allocator.create<ResultLocVar>();
57825782 result_loc_var->base.id = ResultLocIdVar;
57835783 result_loc_var->base.source_instruction = alloca;
......@@ -5789,7 +5789,7 @@ static ResultLocVar *ir_build_var_result_loc(Stage1AstGen *ag, IrInstSrc *alloca
57895789 return result_loc_var;
57905790}
57915791
5792static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, IrInstSrc *dest_type,
5792static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, Stage1ZirInst *dest_type,
57935793 ResultLoc *parent_result_loc)
57945794{
57955795 ResultLocCast *result_loc_cast = heap::c_allocator.create<ResultLocCast>();
......@@ -5805,15 +5805,15 @@ static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, IrInstSrc *dest
58055805}
58065806
58075807static void build_decl_var_and_init(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var,
5808 IrInstSrc *init, const char *name_hint, IrInstSrc *is_comptime)
5808 Stage1ZirInst *init, const char *name_hint, Stage1ZirInst *is_comptime)
58095809{
5810 IrInstSrc *alloca = ir_build_alloca_src(ag, scope, source_node, nullptr, name_hint, is_comptime);
5810 Stage1ZirInst *alloca = ir_build_alloca_src(ag, scope, source_node, nullptr, name_hint, is_comptime);
58115811 ResultLocVar *var_result_loc = ir_build_var_result_loc(ag, alloca, var);
58125812 ir_build_end_expr(ag, scope, source_node, init, &var_result_loc->base);
58135813 ir_build_var_decl_src(ag, scope, source_node, var, nullptr, alloca);
58145814}
58155815
5816static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) {
5816static Stage1ZirInst *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) {
58175817 assert(node->type == NodeTypeVariableDeclaration);
58185818
58195819 AstNodeVariableDeclaration *variable_declaration = &node->data.variable_declaration;
......@@ -5826,7 +5826,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
58265826 // Used for the type expr and the align expr
58275827 Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope);
58285828
5829 IrInstSrc *type_instruction;
5829 Stage1ZirInst *type_instruction;
58305830 if (variable_declaration->type != nullptr) {
58315831 type_instruction = astgen_node(ag, variable_declaration->type, comptime_scope);
58325832 if (type_instruction == ag->codegen->invalid_inst_src)
......@@ -5840,10 +5840,10 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
58405840 bool is_extern = variable_declaration->is_extern;
58415841
58425842 bool is_comptime_scalar = ir_should_inline(ag->exec, scope) || variable_declaration->is_comptime;
5843 IrInstSrc *is_comptime = ir_build_const_bool(ag, scope, node, is_comptime_scalar);
5843 Stage1ZirInst *is_comptime = ir_build_const_bool(ag, scope, node, is_comptime_scalar);
58445844 ZigVar *var = ir_create_var(ag, node, scope, variable_declaration->symbol,
58455845 is_const, is_const, is_shadowable, is_comptime);
5846 // we detect IrInstSrcDeclVar in gen_block to make sure the next node
5846 // we detect Stage1ZirInstDeclVar in gen_block to make sure the next node
58475847 // is inside var->child_scope
58485848
58495849 if (!is_extern && !variable_declaration->expr) {
......@@ -5852,7 +5852,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
58525852 return ag->codegen->invalid_inst_src;
58535853 }
58545854
5855 IrInstSrc *align_value = nullptr;
5855 Stage1ZirInst *align_value = nullptr;
58565856 if (variable_declaration->align_expr != nullptr) {
58575857 align_value = astgen_node(ag, variable_declaration->align_expr, comptime_scope);
58585858 if (align_value == ag->codegen->invalid_inst_src)
......@@ -5867,7 +5867,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
58675867 // Parser should ensure that this never happens
58685868 assert(variable_declaration->threadlocal_tok == 0);
58695869
5870 IrInstSrc *alloca = ir_build_alloca_src(ag, scope, node, align_value,
5870 Stage1ZirInst *alloca = ir_build_alloca_src(ag, scope, node, align_value,
58715871 buf_ptr(variable_declaration->symbol), is_comptime);
58725872
58735873 // Create a result location for the initialization expression.
......@@ -5889,7 +5889,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
58895889 // so that the struct or enum from the init expression inherits the name.
58905890 Buf *old_exec_name = ag->exec->name;
58915891 ag->exec->name = variable_declaration->symbol;
5892 IrInstSrc *init_value = astgen_node_extra(ag, variable_declaration->expr, init_scope,
5892 Stage1ZirInst *init_value = astgen_node_extra(ag, variable_declaration->expr, init_scope,
58935893 LValNone, init_result_loc);
58945894 ag->exec->name = old_exec_name;
58955895
......@@ -5897,7 +5897,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
58975897 return ag->codegen->invalid_inst_src;
58985898
58995899 if (result_loc_cast != nullptr) {
5900 IrInstSrc *implicit_cast = ir_build_implicit_cast(ag, scope, init_value->source_node,
5900 Stage1ZirInst *implicit_cast = ir_build_implicit_cast(ag, scope, init_value->source_node,
59015901 init_value, result_loc_cast);
59025902 ir_build_end_expr(ag, scope, node, implicit_cast, &result_loc_var->base);
59035903 }
......@@ -5905,7 +5905,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node)
59055905 return ir_build_var_decl_src(ag, scope, node, var, align_value, alloca);
59065906}
59075907
5908static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
5908static Stage1ZirInst *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
59095909 ResultLoc *result_loc)
59105910{
59115911 assert(node->type == NodeTypeWhileExpr);
......@@ -5921,7 +5921,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
59215921 Stage1ZirBasicBlock *else_block = else_node ?
59225922 ir_create_basic_block(ag, scope, "WhileElse") : end_block;
59235923
5924 IrInstSrc *is_comptime = ir_build_const_bool(ag, scope, node,
5924 Stage1ZirInst *is_comptime = ir_build_const_bool(ag, scope, node,
59255925 ir_should_inline(ag->exec, scope) || node->data.while_expr.is_inline);
59265926 ir_build_br(ag, scope, node, cond_block, is_comptime);
59275927
......@@ -5943,15 +5943,15 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
59435943 payload_scope = subexpr_scope;
59445944 }
59455945 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, payload_scope);
5946 IrInstSrc *err_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope,
5946 Stage1ZirInst *err_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope,
59475947 LValPtr, nullptr);
59485948 if (err_val_ptr == ag->codegen->invalid_inst_src)
59495949 return err_val_ptr;
5950 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node->data.while_expr.condition, err_val_ptr,
5950 Stage1ZirInst *is_err = ir_build_test_err_src(ag, scope, node->data.while_expr.condition, err_val_ptr,
59515951 true, false);
59525952 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
5953 IrInstSrc *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);
5954 IrInstSrc *cond_br_inst;
5953 Stage1ZirInst *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);
5954 Stage1ZirInst *cond_br_inst;
59555955 if (!instr_is_unreachable(is_err)) {
59565956 cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, is_err,
59575957 else_block, body_block, is_comptime);
......@@ -5965,14 +5965,14 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
59655965
59665966 ir_set_cursor_at_end_and_append_block(ag, body_block);
59675967 if (var_symbol) {
5968 IrInstSrc *payload_ptr = ir_build_unwrap_err_payload_src(ag, &spill_scope->base, symbol_node,
5968 Stage1ZirInst *payload_ptr = ir_build_unwrap_err_payload_src(ag, &spill_scope->base, symbol_node,
59695969 err_val_ptr, false, false);
5970 IrInstSrc *var_value = node->data.while_expr.var_is_ptr ?
5970 Stage1ZirInst *var_value = node->data.while_expr.var_is_ptr ?
59715971 payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, symbol_node, payload_ptr);
59725972 build_decl_var_and_init(ag, payload_scope, symbol_node, payload_var, var_value, buf_ptr(var_symbol), is_comptime);
59735973 }
59745974
5975 ZigList<IrInstSrc *> incoming_values = {0};
5975 ZigList<Stage1ZirInst *> incoming_values = {0};
59765976 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
59775977
59785978 if (is_duplicate_label(ag->codegen, payload_scope, node, node->data.while_expr.name))
......@@ -5991,7 +5991,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
59915991 // Note the body block of the loop is not the place that lval and result_loc are used -
59925992 // it's actually in break statements, handled similarly to return statements.
59935993 // That is why we set those values in loop_scope above and not in this astgen_node call.
5994 IrInstSrc *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);
5994 Stage1ZirInst *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);
59955995 if (body_result == ag->codegen->invalid_inst_src)
59965996 return body_result;
59975997
......@@ -6006,7 +6006,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
60066006
60076007 if (continue_expr_node) {
60086008 ir_set_cursor_at_end_and_append_block(ag, continue_block);
6009 IrInstSrc *expr_result = astgen_node(ag, continue_expr_node, payload_scope);
6009 Stage1ZirInst *expr_result = astgen_node(ag, continue_expr_node, payload_scope);
60106010 if (expr_result == ag->codegen->invalid_inst_src)
60116011 return expr_result;
60126012 if (!instr_is_unreachable(expr_result)) {
......@@ -6023,8 +6023,8 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
60236023 ZigVar *err_var = ir_create_var(ag, err_symbol_node, scope, err_symbol,
60246024 true, false, false, is_comptime);
60256025 Scope *err_scope = err_var->child_scope;
6026 IrInstSrc *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, err_symbol_node, err_val_ptr);
6027 IrInstSrc *err_value = ir_build_load_ptr(ag, err_scope, err_symbol_node, err_ptr);
6026 Stage1ZirInst *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, err_symbol_node, err_val_ptr);
6027 Stage1ZirInst *err_value = ir_build_load_ptr(ag, err_scope, err_symbol_node, err_ptr);
60286028 build_decl_var_and_init(ag, err_scope, err_symbol_node, err_var, err_value, buf_ptr(err_symbol), is_comptime);
60296029
60306030 if (peer_parent->peers.length != 0) {
......@@ -6032,7 +6032,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
60326032 }
60336033 ResultLocPeer *peer_result = create_peer_result(peer_parent);
60346034 peer_parent->peers.append(peer_result);
6035 IrInstSrc *else_result = astgen_node_extra(ag, else_node, err_scope, lval, &peer_result->base);
6035 Stage1ZirInst *else_result = astgen_node_extra(ag, else_node, err_scope, lval, &peer_result->base);
60366036 if (else_result == ag->codegen->invalid_inst_src)
60376037 return else_result;
60386038 if (!instr_is_unreachable(else_result))
......@@ -6050,7 +6050,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
60506050 peer_parent->peers.last()->next_bb = end_block;
60516051 }
60526052
6053 IrInstSrc *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,
6053 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,
60546054 incoming_blocks.items, incoming_values.items, peer_parent);
60556055 return ir_expr_wrap(ag, scope, phi, result_loc);
60566056 } else if (var_symbol != nullptr) {
......@@ -6063,15 +6063,15 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
60636063 true, false, false, is_comptime);
60646064 Scope *child_scope = payload_var->child_scope;
60656065 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, child_scope);
6066 IrInstSrc *maybe_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope,
6066 Stage1ZirInst *maybe_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope,
60676067 LValPtr, nullptr);
60686068 if (maybe_val_ptr == ag->codegen->invalid_inst_src)
60696069 return maybe_val_ptr;
6070 IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node->data.while_expr.condition, maybe_val_ptr);
6071 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node->data.while_expr.condition, maybe_val);
6070 Stage1ZirInst *maybe_val = ir_build_load_ptr(ag, scope, node->data.while_expr.condition, maybe_val_ptr);
6071 Stage1ZirInst *is_non_null = ir_build_test_non_null_src(ag, scope, node->data.while_expr.condition, maybe_val);
60726072 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
6073 IrInstSrc *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);
6074 IrInstSrc *cond_br_inst;
6073 Stage1ZirInst *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);
6074 Stage1ZirInst *cond_br_inst;
60756075 if (!instr_is_unreachable(is_non_null)) {
60766076 cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, is_non_null,
60776077 body_block, else_block, is_comptime);
......@@ -6084,12 +6084,12 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
60846084 is_comptime);
60856085
60866086 ir_set_cursor_at_end_and_append_block(ag, body_block);
6087 IrInstSrc *payload_ptr = ir_build_optional_unwrap_ptr(ag, &spill_scope->base, symbol_node, maybe_val_ptr, false);
6088 IrInstSrc *var_value = node->data.while_expr.var_is_ptr ?
6087 Stage1ZirInst *payload_ptr = ir_build_optional_unwrap_ptr(ag, &spill_scope->base, symbol_node, maybe_val_ptr, false);
6088 Stage1ZirInst *var_value = node->data.while_expr.var_is_ptr ?
60896089 payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, symbol_node, payload_ptr);
60906090 build_decl_var_and_init(ag, child_scope, symbol_node, payload_var, var_value, buf_ptr(var_symbol), is_comptime);
60916091
6092 ZigList<IrInstSrc *> incoming_values = {0};
6092 ZigList<Stage1ZirInst *> incoming_values = {0};
60936093 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
60946094
60956095 if (is_duplicate_label(ag->codegen, child_scope, node, node->data.while_expr.name))
......@@ -6108,7 +6108,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
61086108 // Note the body block of the loop is not the place that lval and result_loc are used -
61096109 // it's actually in break statements, handled similarly to return statements.
61106110 // That is why we set those values in loop_scope above and not in this astgen_node call.
6111 IrInstSrc *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);
6111 Stage1ZirInst *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);
61126112 if (body_result == ag->codegen->invalid_inst_src)
61136113 return body_result;
61146114
......@@ -6123,7 +6123,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
61236123
61246124 if (continue_expr_node) {
61256125 ir_set_cursor_at_end_and_append_block(ag, continue_block);
6126 IrInstSrc *expr_result = astgen_node(ag, continue_expr_node, child_scope);
6126 Stage1ZirInst *expr_result = astgen_node(ag, continue_expr_node, child_scope);
61276127 if (expr_result == ag->codegen->invalid_inst_src)
61286128 return expr_result;
61296129 if (!instr_is_unreachable(expr_result)) {
......@@ -6132,7 +6132,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
61326132 }
61336133 }
61346134
6135 IrInstSrc *else_result = nullptr;
6135 Stage1ZirInst *else_result = nullptr;
61366136 if (else_node) {
61376137 ir_set_cursor_at_end_and_append_block(ag, else_block);
61386138
......@@ -6160,17 +6160,17 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
61606160 peer_parent->peers.last()->next_bb = end_block;
61616161 }
61626162
6163 IrInstSrc *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,
6163 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,
61646164 incoming_blocks.items, incoming_values.items, peer_parent);
61656165 return ir_expr_wrap(ag, scope, phi, result_loc);
61666166 } else {
61676167 ir_set_cursor_at_end_and_append_block(ag, cond_block);
6168 IrInstSrc *cond_val = astgen_node(ag, node->data.while_expr.condition, scope);
6168 Stage1ZirInst *cond_val = astgen_node(ag, node->data.while_expr.condition, scope);
61696169 if (cond_val == ag->codegen->invalid_inst_src)
61706170 return cond_val;
61716171 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
6172 IrInstSrc *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);
6173 IrInstSrc *cond_br_inst;
6172 Stage1ZirInst *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node);
6173 Stage1ZirInst *cond_br_inst;
61746174 if (!instr_is_unreachable(cond_val)) {
61756175 cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, cond_val,
61766176 body_block, else_block, is_comptime);
......@@ -6183,7 +6183,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
61836183 is_comptime);
61846184 ir_set_cursor_at_end_and_append_block(ag, body_block);
61856185
6186 ZigList<IrInstSrc *> incoming_values = {0};
6186 ZigList<Stage1ZirInst *> incoming_values = {0};
61876187 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
61886188
61896189 Scope *subexpr_scope = create_runtime_scope(ag->codegen, node, scope, is_comptime);
......@@ -6203,7 +6203,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
62036203 // Note the body block of the loop is not the place that lval and result_loc are used -
62046204 // it's actually in break statements, handled similarly to return statements.
62056205 // That is why we set those values in loop_scope above and not in this astgen_node call.
6206 IrInstSrc *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);
6206 Stage1ZirInst *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base);
62076207 if (body_result == ag->codegen->invalid_inst_src)
62086208 return body_result;
62096209
......@@ -6218,7 +6218,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
62186218
62196219 if (continue_expr_node) {
62206220 ir_set_cursor_at_end_and_append_block(ag, continue_block);
6221 IrInstSrc *expr_result = astgen_node(ag, continue_expr_node, subexpr_scope);
6221 Stage1ZirInst *expr_result = astgen_node(ag, continue_expr_node, subexpr_scope);
62226222 if (expr_result == ag->codegen->invalid_inst_src)
62236223 return expr_result;
62246224 if (!instr_is_unreachable(expr_result)) {
......@@ -6227,7 +6227,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
62276227 }
62286228 }
62296229
6230 IrInstSrc *else_result = nullptr;
6230 Stage1ZirInst *else_result = nullptr;
62316231 if (else_node) {
62326232 ir_set_cursor_at_end_and_append_block(ag, else_block);
62336233
......@@ -6256,13 +6256,13 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
62566256 peer_parent->peers.last()->next_bb = end_block;
62576257 }
62586258
6259 IrInstSrc *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,
6259 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, incoming_blocks.length,
62606260 incoming_blocks.items, incoming_values.items, peer_parent);
62616261 return ir_expr_wrap(ag, scope, phi, result_loc);
62626262 }
62636263}
62646264
6265static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,
6265static Stage1ZirInst *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,
62666266 ResultLoc *result_loc)
62676267{
62686268 assert(node->type == NodeTypeForExpr);
......@@ -6281,11 +6281,11 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
62816281
62826282 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, parent_scope);
62836283
6284 IrInstSrc *array_val_ptr = astgen_node_extra(ag, array_node, &spill_scope->base, LValPtr, nullptr);
6284 Stage1ZirInst *array_val_ptr = astgen_node_extra(ag, array_node, &spill_scope->base, LValPtr, nullptr);
62856285 if (array_val_ptr == ag->codegen->invalid_inst_src)
62866286 return array_val_ptr;
62876287
6288 IrInstSrc *is_comptime = ir_build_const_bool(ag, parent_scope, node,
6288 Stage1ZirInst *is_comptime = ir_build_const_bool(ag, parent_scope, node,
62896289 ir_should_inline(ag->exec, parent_scope) || node->data.for_expr.is_inline);
62906290
62916291 AstNode *index_var_source_node;
......@@ -6302,12 +6302,12 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
63026302 index_var_name = "i";
63036303 }
63046304
6305 IrInstSrc *zero = ir_build_const_usize(ag, parent_scope, node, 0);
6305 Stage1ZirInst *zero = ir_build_const_usize(ag, parent_scope, node, 0);
63066306 build_decl_var_and_init(ag, parent_scope, index_var_source_node, index_var, zero, index_var_name, is_comptime);
63076307 parent_scope = index_var->child_scope;
63086308
6309 IrInstSrc *one = ir_build_const_usize(ag, parent_scope, node, 1);
6310 IrInstSrc *index_ptr = ir_build_var_ptr(ag, parent_scope, node, index_var);
6309 Stage1ZirInst *one = ir_build_const_usize(ag, parent_scope, node, 1);
6310 Stage1ZirInst *index_ptr = ir_build_var_ptr(ag, parent_scope, node, index_var);
63116311
63126312
63136313 Stage1ZirBasicBlock *cond_block = ir_create_basic_block(ag, parent_scope, "ForCond");
......@@ -6317,36 +6317,36 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
63176317 Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, parent_scope, "ForContinue");
63186318
63196319 Buf *len_field_name = buf_create_from_str("len");
6320 IrInstSrc *len_ref = ir_build_field_ptr(ag, parent_scope, node, array_val_ptr, len_field_name, false);
6321 IrInstSrc *len_val = ir_build_load_ptr(ag, &spill_scope->base, node, len_ref);
6320 Stage1ZirInst *len_ref = ir_build_field_ptr(ag, parent_scope, node, array_val_ptr, len_field_name, false);
6321 Stage1ZirInst *len_val = ir_build_load_ptr(ag, &spill_scope->base, node, len_ref);
63226322 ir_build_br(ag, parent_scope, node, cond_block, is_comptime);
63236323
63246324 ir_set_cursor_at_end_and_append_block(ag, cond_block);
6325 IrInstSrc *index_val = ir_build_load_ptr(ag, &spill_scope->base, node, index_ptr);
6326 IrInstSrc *cond = ir_build_bin_op(ag, parent_scope, node, IrBinOpCmpLessThan, index_val, len_val, false);
6325 Stage1ZirInst *index_val = ir_build_load_ptr(ag, &spill_scope->base, node, index_ptr);
6326 Stage1ZirInst *cond = ir_build_bin_op(ag, parent_scope, node, IrBinOpCmpLessThan, index_val, len_val, false);
63276327 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
6328 IrInstSrc *void_else_value = else_node ? nullptr : ir_build_const_void(ag, parent_scope, node);
6329 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, cond,
6328 Stage1ZirInst *void_else_value = else_node ? nullptr : ir_build_const_void(ag, parent_scope, node);
6329 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, cond,
63306330 body_block, else_block, is_comptime);
63316331
63326332 ResultLocPeerParent *peer_parent = ir_build_result_peers(ag, cond_br_inst, end_block, result_loc, is_comptime);
63336333
63346334 ir_set_cursor_at_end_and_append_block(ag, body_block);
6335 IrInstSrc *elem_ptr = ir_build_elem_ptr(ag, &spill_scope->base, node, array_val_ptr, index_val,
6335 Stage1ZirInst *elem_ptr = ir_build_elem_ptr(ag, &spill_scope->base, node, array_val_ptr, index_val,
63366336 false, PtrLenSingle, nullptr);
63376337 // TODO make it an error to write to element variable or i variable.
63386338 Buf *elem_var_name = node_identifier_buf(elem_node);
63396339 ZigVar *elem_var = ir_create_var(ag, elem_node, parent_scope, elem_var_name, true, false, false, is_comptime);
63406340 Scope *child_scope = elem_var->child_scope;
63416341
6342 IrInstSrc *elem_value = node->data.for_expr.elem_is_ptr ?
6342 Stage1ZirInst *elem_value = node->data.for_expr.elem_is_ptr ?
63436343 elem_ptr : ir_build_load_ptr(ag, &spill_scope->base, elem_node, elem_ptr);
63446344 build_decl_var_and_init(ag, parent_scope, elem_node, elem_var, elem_value, buf_ptr(elem_var_name), is_comptime);
63456345
63466346 if (is_duplicate_label(ag->codegen, child_scope, node, node->data.for_expr.name))
63476347 return ag->codegen->invalid_inst_src;
63486348
6349 ZigList<IrInstSrc *> incoming_values = {0};
6349 ZigList<Stage1ZirInst *> incoming_values = {0};
63506350 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
63516351 ScopeLoop *loop_scope = create_loop_scope(ag->codegen, node, child_scope);
63526352 loop_scope->break_block = end_block;
......@@ -6361,7 +6361,7 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
63616361 // Note the body block of the loop is not the place that lval and result_loc are used -
63626362 // it's actually in break statements, handled similarly to return statements.
63636363 // That is why we set those values in loop_scope above and not in this astgen_node call.
6364 IrInstSrc *body_result = astgen_node(ag, body_node, &loop_scope->base);
6364 Stage1ZirInst *body_result = astgen_node(ag, body_node, &loop_scope->base);
63656365 if (body_result == ag->codegen->invalid_inst_src)
63666366 return ag->codegen->invalid_inst_src;
63676367
......@@ -6375,11 +6375,11 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
63756375 }
63766376
63776377 ir_set_cursor_at_end_and_append_block(ag, continue_block);
6378 IrInstSrc *new_index_val = ir_build_bin_op(ag, child_scope, node, IrBinOpAdd, index_val, one, false);
6378 Stage1ZirInst *new_index_val = ir_build_bin_op(ag, child_scope, node, IrBinOpAdd, index_val, one, false);
63796379 ir_build_store_ptr(ag, child_scope, node, index_ptr, new_index_val)->allow_write_through_const = true;
63806380 ir_build_br(ag, child_scope, node, cond_block, is_comptime);
63816381
6382 IrInstSrc *else_result = nullptr;
6382 Stage1ZirInst *else_result = nullptr;
63836383 if (else_node) {
63846384 ir_set_cursor_at_end_and_append_block(ag, else_block);
63856385
......@@ -6408,17 +6408,17 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
64086408 peer_parent->peers.last()->next_bb = end_block;
64096409 }
64106410
6411 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, incoming_blocks.length,
6411 Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, node, incoming_blocks.length,
64126412 incoming_blocks.items, incoming_values.items, peer_parent);
64136413 return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc);
64146414}
64156415
6416static IrInstSrc *astgen_bool_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6416static Stage1ZirInst *astgen_bool_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
64176417 assert(node->type == NodeTypeBoolLiteral);
64186418 return ir_build_const_bool(ag, scope, node, node->data.bool_literal.value);
64196419}
64206420
6421static IrInstSrc *astgen_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6421static Stage1ZirInst *astgen_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
64226422 assert(node->type == NodeTypeEnumLiteral);
64236423 // Currently, stage1 runs astgen for every comptime function call,
64246424 // resulting the allocation here wasting memory. As a workaround until
......@@ -6431,7 +6431,7 @@ static IrInstSrc *astgen_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *n
64316431 return ir_build_const_enum_literal(ag, scope, node, node->data.enum_literal.name);
64326432}
64336433
6434static IrInstSrc *astgen_string_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6434static Stage1ZirInst *astgen_string_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
64356435 Error err;
64366436 assert(node->type == NodeTypeStringLiteral);
64376437
......@@ -6473,7 +6473,7 @@ static IrInstSrc *astgen_string_literal(Stage1AstGen *ag, Scope *scope, AstNode
64736473 return ir_build_const_str_lit(ag, scope, node, str);
64746474}
64756475
6476static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6476static Stage1ZirInst *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
64776477 assert(node->type == NodeTypeArrayType);
64786478
64796479 AstNode *size_node = node->data.array_type.size;
......@@ -6486,7 +6486,7 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod
64866486
64876487 Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope);
64886488
6489 IrInstSrc *sentinel;
6489 Stage1ZirInst *sentinel;
64906490 if (sentinel_expr != nullptr) {
64916491 sentinel = astgen_node(ag, sentinel_expr, comptime_scope);
64926492 if (sentinel == ag->codegen->invalid_inst_src)
......@@ -6513,17 +6513,17 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod
65136513 return ag->codegen->invalid_inst_src;
65146514 }
65156515
6516 IrInstSrc *size_value = astgen_node(ag, size_node, comptime_scope);
6516 Stage1ZirInst *size_value = astgen_node(ag, size_node, comptime_scope);
65176517 if (size_value == ag->codegen->invalid_inst_src)
65186518 return size_value;
65196519
6520 IrInstSrc *child_type = astgen_node(ag, child_type_node, comptime_scope);
6520 Stage1ZirInst *child_type = astgen_node(ag, child_type_node, comptime_scope);
65216521 if (child_type == ag->codegen->invalid_inst_src)
65226522 return child_type;
65236523
65246524 return ir_build_array_type(ag, scope, node, size_value, sentinel, child_type);
65256525 } else {
6526 IrInstSrc *align_value;
6526 Stage1ZirInst *align_value;
65276527 if (align_expr != nullptr) {
65286528 align_value = astgen_node(ag, align_expr, comptime_scope);
65296529 if (align_value == ag->codegen->invalid_inst_src)
......@@ -6532,7 +6532,7 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod
65326532 align_value = nullptr;
65336533 }
65346534
6535 IrInstSrc *child_type = astgen_node(ag, child_type_node, comptime_scope);
6535 Stage1ZirInst *child_type = astgen_node(ag, child_type_node, comptime_scope);
65366536 if (child_type == ag->codegen->invalid_inst_src)
65376537 return child_type;
65386538
......@@ -6541,11 +6541,11 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod
65416541 }
65426542}
65436543
6544static IrInstSrc *astgen_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6544static Stage1ZirInst *astgen_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
65456545 assert(node->type == NodeTypeAnyFrameType);
65466546
65476547 AstNode *payload_type_node = node->data.anyframe_type.payload_type;
6548 IrInstSrc *payload_type_value = nullptr;
6548 Stage1ZirInst *payload_type_value = nullptr;
65496549
65506550 if (payload_type_node != nullptr) {
65516551 payload_type_value = astgen_node(ag, payload_type_node, scope);
......@@ -6557,16 +6557,16 @@ static IrInstSrc *astgen_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *
65576557 return ir_build_anyframe_type(ag, scope, node, payload_type_value);
65586558}
65596559
6560static IrInstSrc *astgen_undefined_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6560static Stage1ZirInst *astgen_undefined_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) {
65616561 assert(node->type == NodeTypeUndefinedLiteral);
65626562 return ir_build_const_undefined(ag, scope, node);
65636563}
65646564
6565static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node) {
6565static Stage1ZirInst *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node) {
65666566 assert(node->type == NodeTypeAsmExpr);
65676567 AstNodeAsmExpr *asm_expr = &node->data.asm_expr;
65686568
6569 IrInstSrc *asm_template = astgen_node(ag, asm_expr->asm_template, scope);
6569 Stage1ZirInst *asm_template = astgen_node(ag, asm_expr->asm_template, scope);
65706570 if (asm_template == ag->codegen->invalid_inst_src)
65716571 return ag->codegen->invalid_inst_src;
65726572
......@@ -6592,8 +6592,8 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)
65926592 nullptr, 0, is_volatile, true);
65936593 }
65946594
6595 IrInstSrc **input_list = heap::c_allocator.allocate<IrInstSrc *>(asm_expr->input_list.length);
6596 IrInstSrc **output_types = heap::c_allocator.allocate<IrInstSrc *>(asm_expr->output_list.length);
6595 Stage1ZirInst **input_list = heap::c_allocator.allocate<Stage1ZirInst *>(asm_expr->input_list.length);
6596 Stage1ZirInst **output_types = heap::c_allocator.allocate<Stage1ZirInst *>(asm_expr->output_list.length);
65976597 ZigVar **output_vars = heap::c_allocator.allocate<ZigVar *>(asm_expr->output_list.length);
65986598 size_t return_count = 0;
65996599 if (!is_volatile && asm_expr->output_list.length == 0) {
......@@ -6606,7 +6606,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)
66066606 if (asm_output->return_type) {
66076607 return_count += 1;
66086608
6609 IrInstSrc *return_type = astgen_node(ag, asm_output->return_type, scope);
6609 Stage1ZirInst *return_type = astgen_node(ag, asm_output->return_type, scope);
66106610 if (return_type == ag->codegen->invalid_inst_src)
66116611 return ag->codegen->invalid_inst_src;
66126612 if (return_count > 1) {
......@@ -6640,7 +6640,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)
66406640 }
66416641 for (size_t i = 0; i < asm_expr->input_list.length; i += 1) {
66426642 AsmInput *asm_input = asm_expr->input_list.at(i);
6643 IrInstSrc *input_value = astgen_node(ag, asm_input->expr, scope);
6643 Stage1ZirInst *input_value = astgen_node(ag, asm_input->expr, scope);
66446644 if (input_value == ag->codegen->invalid_inst_src)
66456645 return ag->codegen->invalid_inst_src;
66466646
......@@ -6651,7 +6651,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node)
66516651 output_vars, return_count, is_volatile, false);
66526652}
66536653
6654static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
6654static Stage1ZirInst *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
66556655 ResultLoc *result_loc)
66566656{
66576657 assert(node->type == NodeTypeIfOptional);
......@@ -6665,24 +6665,24 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
66656665 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, expr_node, scope);
66666666 spill_scope->spill_harder = true;
66676667
6668 IrInstSrc *maybe_val_ptr = astgen_node_extra(ag, expr_node, &spill_scope->base, LValPtr, nullptr);
6668 Stage1ZirInst *maybe_val_ptr = astgen_node_extra(ag, expr_node, &spill_scope->base, LValPtr, nullptr);
66696669 if (maybe_val_ptr == ag->codegen->invalid_inst_src)
66706670 return maybe_val_ptr;
66716671
6672 IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node, maybe_val_ptr);
6673 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node, maybe_val);
6672 Stage1ZirInst *maybe_val = ir_build_load_ptr(ag, scope, node, maybe_val_ptr);
6673 Stage1ZirInst *is_non_null = ir_build_test_non_null_src(ag, scope, node, maybe_val);
66746674
66756675 Stage1ZirBasicBlock *then_block = ir_create_basic_block(ag, scope, "OptionalThen");
66766676 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "OptionalElse");
66776677 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "OptionalEndIf");
66786678
6679 IrInstSrc *is_comptime;
6679 Stage1ZirInst *is_comptime;
66806680 if (ir_should_inline(ag->exec, scope)) {
66816681 is_comptime = ir_build_const_bool(ag, scope, node, true);
66826682 } else {
66836683 is_comptime = ir_build_test_comptime(ag, scope, node, is_non_null);
66846684 }
6685 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, is_non_null,
6685 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, scope, node, is_non_null,
66866686 then_block, else_block, is_comptime);
66876687
66886688 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block,
......@@ -6698,15 +6698,15 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
66986698 ZigVar *var = ir_create_var(ag, node, subexpr_scope,
66996699 var_symbol, is_const, is_const, is_shadowable, is_comptime);
67006700
6701 IrInstSrc *payload_ptr = ir_build_optional_unwrap_ptr(ag, subexpr_scope, node, maybe_val_ptr, false);
6702 IrInstSrc *var_value = var_is_ptr ?
6701 Stage1ZirInst *payload_ptr = ir_build_optional_unwrap_ptr(ag, subexpr_scope, node, maybe_val_ptr, false);
6702 Stage1ZirInst *var_value = var_is_ptr ?
67036703 payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, node, payload_ptr);
67046704 build_decl_var_and_init(ag, subexpr_scope, node, var, var_value, buf_ptr(var_symbol), is_comptime);
67056705 var_scope = var->child_scope;
67066706 } else {
67076707 var_scope = subexpr_scope;
67086708 }
6709 IrInstSrc *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval,
6709 Stage1ZirInst *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval,
67106710 &peer_parent->peers.at(0)->base);
67116711 if (then_expr_result == ag->codegen->invalid_inst_src)
67126712 return then_expr_result;
......@@ -6715,7 +6715,7 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
67156715 ir_build_br(ag, scope, node, endif_block, is_comptime);
67166716
67176717 ir_set_cursor_at_end_and_append_block(ag, else_block);
6718 IrInstSrc *else_expr_result;
6718 Stage1ZirInst *else_expr_result;
67196719 if (else_node) {
67206720 else_expr_result = astgen_node_extra(ag, else_node, subexpr_scope, lval, &peer_parent->peers.at(1)->base);
67216721 if (else_expr_result == ag->codegen->invalid_inst_src)
......@@ -6729,18 +6729,18 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
67296729 ir_build_br(ag, scope, node, endif_block, is_comptime);
67306730
67316731 ir_set_cursor_at_end_and_append_block(ag, endif_block);
6732 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
6732 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
67336733 incoming_values[0] = then_expr_result;
67346734 incoming_values[1] = else_expr_result;
67356735 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
67366736 incoming_blocks[0] = after_then_block;
67376737 incoming_blocks[1] = after_else_block;
67386738
6739 IrInstSrc *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);
6739 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);
67406740 return ir_expr_wrap(ag, scope, phi, result_loc);
67416741}
67426742
6743static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
6743static Stage1ZirInst *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
67446744 ResultLoc *result_loc)
67456745{
67466746 assert(node->type == NodeTypeIfErrorExpr);
......@@ -6753,20 +6753,20 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
67536753 Buf *var_symbol = node->data.if_err_expr.var_symbol;
67546754 Buf *err_symbol = node->data.if_err_expr.err_symbol;
67556755
6756 IrInstSrc *err_val_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr);
6756 Stage1ZirInst *err_val_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr);
67576757 if (err_val_ptr == ag->codegen->invalid_inst_src)
67586758 return err_val_ptr;
67596759
6760 IrInstSrc *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr);
6761 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, err_val_ptr, true, false);
6760 Stage1ZirInst *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr);
6761 Stage1ZirInst *is_err = ir_build_test_err_src(ag, scope, node, err_val_ptr, true, false);
67626762
67636763 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "TryOk");
67646764 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "TryElse");
67656765 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "TryEnd");
67666766
67676767 bool force_comptime = ir_should_inline(ag->exec, scope);
6768 IrInstSrc *is_comptime = force_comptime ? ir_build_const_bool(ag, scope, node, true) : ir_build_test_comptime(ag, scope, node, is_err);
6769 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, is_err, else_block, ok_block, is_comptime);
6768 Stage1ZirInst *is_comptime = force_comptime ? ir_build_const_bool(ag, scope, node, true) : ir_build_test_comptime(ag, scope, node, is_err);
6769 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, scope, node, is_err, else_block, ok_block, is_comptime);
67706770
67716771 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block,
67726772 result_loc, is_comptime);
......@@ -6777,19 +6777,19 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
67776777 Scope *var_scope;
67786778 if (var_symbol) {
67796779 bool is_shadowable = false;
6780 IrInstSrc *var_is_comptime = force_comptime ? ir_build_const_bool(ag, subexpr_scope, node, true) : ir_build_test_comptime(ag, subexpr_scope, node, err_val);
6780 Stage1ZirInst *var_is_comptime = force_comptime ? ir_build_const_bool(ag, subexpr_scope, node, true) : ir_build_test_comptime(ag, subexpr_scope, node, err_val);
67816781 ZigVar *var = ir_create_var(ag, node, subexpr_scope,
67826782 var_symbol, var_is_const, var_is_const, is_shadowable, var_is_comptime);
67836783
6784 IrInstSrc *payload_ptr = ir_build_unwrap_err_payload_src(ag, subexpr_scope, node, err_val_ptr, false, false);
6785 IrInstSrc *var_value = var_is_ptr ?
6784 Stage1ZirInst *payload_ptr = ir_build_unwrap_err_payload_src(ag, subexpr_scope, node, err_val_ptr, false, false);
6785 Stage1ZirInst *var_value = var_is_ptr ?
67866786 payload_ptr : ir_build_load_ptr(ag, subexpr_scope, node, payload_ptr);
67876787 build_decl_var_and_init(ag, subexpr_scope, node, var, var_value, buf_ptr(var_symbol), var_is_comptime);
67886788 var_scope = var->child_scope;
67896789 } else {
67906790 var_scope = subexpr_scope;
67916791 }
6792 IrInstSrc *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval,
6792 Stage1ZirInst *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval,
67936793 &peer_parent->peers.at(0)->base);
67946794 if (then_expr_result == ag->codegen->invalid_inst_src)
67956795 return then_expr_result;
......@@ -6799,7 +6799,7 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
67996799
68006800 ir_set_cursor_at_end_and_append_block(ag, else_block);
68016801
6802 IrInstSrc *else_expr_result;
6802 Stage1ZirInst *else_expr_result;
68036803 if (else_node) {
68046804 Scope *err_var_scope;
68056805 if (err_symbol) {
......@@ -6808,8 +6808,8 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
68086808 ZigVar *var = ir_create_var(ag, node, subexpr_scope,
68096809 err_symbol, is_const, is_const, is_shadowable, is_comptime);
68106810
6811 IrInstSrc *err_ptr = ir_build_unwrap_err_code_src(ag, subexpr_scope, node, err_val_ptr);
6812 IrInstSrc *err_value = ir_build_load_ptr(ag, subexpr_scope, node, err_ptr);
6811 Stage1ZirInst *err_ptr = ir_build_unwrap_err_code_src(ag, subexpr_scope, node, err_val_ptr);
6812 Stage1ZirInst *err_value = ir_build_load_ptr(ag, subexpr_scope, node, err_ptr);
68136813 build_decl_var_and_init(ag, subexpr_scope, node, var, err_value, buf_ptr(err_symbol), is_comptime);
68146814 err_var_scope = var->child_scope;
68156815 } else {
......@@ -6827,22 +6827,22 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
68276827 ir_build_br(ag, scope, node, endif_block, is_comptime);
68286828
68296829 ir_set_cursor_at_end_and_append_block(ag, endif_block);
6830 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
6830 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
68316831 incoming_values[0] = then_expr_result;
68326832 incoming_values[1] = else_expr_result;
68336833 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
68346834 incoming_blocks[0] = after_then_block;
68356835 incoming_blocks[1] = after_else_block;
68366836
6837 IrInstSrc *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);
6837 Stage1ZirInst *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent);
68386838 return ir_expr_wrap(ag, scope, phi, result_loc);
68396839}
68406840
68416841static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *switch_node, AstNode *prong_node,
6842 Stage1ZirBasicBlock *end_block, IrInstSrc *is_comptime, IrInstSrc *var_is_comptime,
6843 IrInstSrc *target_value_ptr, IrInstSrc **prong_values, size_t prong_values_len,
6844 ZigList<Stage1ZirBasicBlock *> *incoming_blocks, ZigList<IrInstSrc *> *incoming_values,
6845 IrInstSrcSwitchElseVar **out_switch_else_var, LVal lval, ResultLoc *result_loc)
6842 Stage1ZirBasicBlock *end_block, Stage1ZirInst *is_comptime, Stage1ZirInst *var_is_comptime,
6843 Stage1ZirInst *target_value_ptr, Stage1ZirInst **prong_values, size_t prong_values_len,
6844 ZigList<Stage1ZirBasicBlock *> *incoming_blocks, ZigList<Stage1ZirInst *> *incoming_values,
6845 Stage1ZirInstSwitchElseVar **out_switch_else_var, LVal lval, ResultLoc *result_loc)
68466846{
68476847 assert(switch_node->type == NodeTypeSwitchExpr);
68486848 assert(prong_node->type == NodeTypeSwitchProng);
......@@ -6860,16 +6860,16 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw
68606860 ZigVar *var = ir_create_var(ag, var_symbol_node, scope,
68616861 var_name, is_const, is_const, is_shadowable, var_is_comptime);
68626862 child_scope = var->child_scope;
6863 IrInstSrc *var_value;
6863 Stage1ZirInst *var_value;
68646864 if (out_switch_else_var != nullptr) {
6865 IrInstSrcSwitchElseVar *switch_else_var = ir_build_switch_else_var(ag, scope, var_symbol_node,
6865 Stage1ZirInstSwitchElseVar *switch_else_var = ir_build_switch_else_var(ag, scope, var_symbol_node,
68666866 target_value_ptr);
68676867 *out_switch_else_var = switch_else_var;
6868 IrInstSrc *payload_ptr = &switch_else_var->base;
6868 Stage1ZirInst *payload_ptr = &switch_else_var->base;
68696869 var_value = var_is_ptr ?
68706870 payload_ptr : ir_build_load_ptr(ag, scope, var_symbol_node, payload_ptr);
68716871 } else if (prong_values != nullptr) {
6872 IrInstSrc *payload_ptr = ir_build_switch_var(ag, scope, var_symbol_node, target_value_ptr,
6872 Stage1ZirInst *payload_ptr = ir_build_switch_var(ag, scope, var_symbol_node, target_value_ptr,
68736873 prong_values, prong_values_len);
68746874 var_value = var_is_ptr ?
68756875 payload_ptr : ir_build_load_ptr(ag, scope, var_symbol_node, payload_ptr);
......@@ -6882,7 +6882,7 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw
68826882 child_scope = scope;
68836883 }
68846884
6885 IrInstSrc *expr_result = astgen_node_extra(ag, expr_node, child_scope, lval, result_loc);
6885 Stage1ZirInst *expr_result = astgen_node_extra(ag, expr_node, child_scope, lval, result_loc);
68866886 if (expr_result == ag->codegen->invalid_inst_src)
68876887 return false;
68886888 if (!instr_is_unreachable(expr_result))
......@@ -6892,25 +6892,25 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw
68926892 return true;
68936893}
68946894
6895static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
6895static Stage1ZirInst *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
68966896 ResultLoc *result_loc)
68976897{
68986898 assert(node->type == NodeTypeSwitchExpr);
68996899
69006900 AstNode *target_node = node->data.switch_expr.expr;
6901 IrInstSrc *target_value_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr);
6901 Stage1ZirInst *target_value_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr);
69026902 if (target_value_ptr == ag->codegen->invalid_inst_src)
69036903 return target_value_ptr;
6904 IrInstSrc *target_value = ir_build_switch_target(ag, scope, node, target_value_ptr);
6904 Stage1ZirInst *target_value = ir_build_switch_target(ag, scope, node, target_value_ptr);
69056905
69066906 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "SwitchElse");
69076907 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, scope, "SwitchEnd");
69086908
69096909 size_t prong_count = node->data.switch_expr.prongs.length;
6910 ZigList<IrInstSrcSwitchBrCase> cases = {0};
6910 ZigList<Stage1ZirInstSwitchBrCase> cases = {0};
69116911
6912 IrInstSrc *is_comptime;
6913 IrInstSrc *var_is_comptime;
6912 Stage1ZirInst *is_comptime;
6913 Stage1ZirInst *var_is_comptime;
69146914 if (ir_should_inline(ag->exec, scope)) {
69156915 is_comptime = ir_build_const_bool(ag, scope, node, true);
69166916 var_is_comptime = is_comptime;
......@@ -6919,11 +6919,11 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
69196919 var_is_comptime = ir_build_test_comptime(ag, scope, node, target_value_ptr);
69206920 }
69216921
6922 ZigList<IrInstSrc *> incoming_values = {0};
6922 ZigList<Stage1ZirInst *> incoming_values = {0};
69236923 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
6924 ZigList<IrInstSrcCheckSwitchProngsRange> check_ranges = {0};
6924 ZigList<Stage1ZirInstCheckSwitchProngsRange> check_ranges = {0};
69256925
6926 IrInstSrcSwitchElseVar *switch_else_var = nullptr;
6926 Stage1ZirInstSwitchElseVar *switch_else_var = nullptr;
69276927
69286928 ResultLocPeerParent *peer_parent = heap::c_allocator.create<ResultLocPeerParent>();
69296929 peer_parent->base.id = ResultLocIdPeerParent;
......@@ -6945,7 +6945,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
69456945 if (prong_node->data.switch_prong.any_items_are_range) {
69466946 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);
69476947
6948 IrInstSrc *ok_bit = nullptr;
6948 Stage1ZirInst *ok_bit = nullptr;
69496949 AstNode *last_item_node = nullptr;
69506950 for (size_t item_i = 0; item_i < prong_item_count; item_i += 1) {
69516951 AstNode *item_node = prong_node->data.switch_prong.items.at(item_i);
......@@ -6954,23 +6954,23 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
69546954 AstNode *start_node = item_node->data.switch_range.start;
69556955 AstNode *end_node = item_node->data.switch_range.end;
69566956
6957 IrInstSrc *start_value = astgen_node(ag, start_node, comptime_scope);
6957 Stage1ZirInst *start_value = astgen_node(ag, start_node, comptime_scope);
69586958 if (start_value == ag->codegen->invalid_inst_src)
69596959 return ag->codegen->invalid_inst_src;
69606960
6961 IrInstSrc *end_value = astgen_node(ag, end_node, comptime_scope);
6961 Stage1ZirInst *end_value = astgen_node(ag, end_node, comptime_scope);
69626962 if (end_value == ag->codegen->invalid_inst_src)
69636963 return ag->codegen->invalid_inst_src;
69646964
6965 IrInstSrcCheckSwitchProngsRange *check_range = check_ranges.add_one();
6965 Stage1ZirInstCheckSwitchProngsRange *check_range = check_ranges.add_one();
69666966 check_range->start = start_value;
69676967 check_range->end = end_value;
69686968
6969 IrInstSrc *lower_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpGreaterOrEq,
6969 Stage1ZirInst *lower_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpGreaterOrEq,
69706970 target_value, start_value, false);
6971 IrInstSrc *upper_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpLessOrEq,
6971 Stage1ZirInst *upper_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpLessOrEq,
69726972 target_value, end_value, false);
6973 IrInstSrc *both_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolAnd,
6973 Stage1ZirInst *both_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolAnd,
69746974 lower_range_ok, upper_range_ok, false);
69756975 if (ok_bit) {
69766976 ok_bit = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolOr, both_ok, ok_bit, false);
......@@ -6978,15 +6978,15 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
69786978 ok_bit = both_ok;
69796979 }
69806980 } else {
6981 IrInstSrc *item_value = astgen_node(ag, item_node, comptime_scope);
6981 Stage1ZirInst *item_value = astgen_node(ag, item_node, comptime_scope);
69826982 if (item_value == ag->codegen->invalid_inst_src)
69836983 return ag->codegen->invalid_inst_src;
69846984
6985 IrInstSrcCheckSwitchProngsRange *check_range = check_ranges.add_one();
6985 Stage1ZirInstCheckSwitchProngsRange *check_range = check_ranges.add_one();
69866986 check_range->start = item_value;
69876987 check_range->end = item_value;
69886988
6989 IrInstSrc *cmp_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpEq,
6989 Stage1ZirInst *cmp_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpEq,
69906990 item_value, target_value, false);
69916991 if (ok_bit) {
69926992 ok_bit = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolOr, cmp_ok, ok_bit, false);
......@@ -7001,7 +7001,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
70017001
70027002 assert(ok_bit);
70037003 assert(last_item_node);
7004 IrInstSrc *br_inst = ir_build_cond_br(ag, scope, last_item_node, ok_bit,
7004 Stage1ZirInst *br_inst = ir_build_cond_br(ag, scope, last_item_node, ok_bit,
70057005 range_block_yes, range_block_no, is_comptime);
70067006 if (peer_parent->base.source_instruction == nullptr) {
70077007 peer_parent->base.source_instruction = br_inst;
......@@ -7087,21 +7087,21 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
70877087 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);
70887088
70897089 Stage1ZirBasicBlock *prong_block = ir_create_basic_block(ag, scope, "SwitchProng");
7090 IrInstSrc **items = heap::c_allocator.allocate<IrInstSrc *>(prong_item_count);
7090 Stage1ZirInst **items = heap::c_allocator.allocate<Stage1ZirInst *>(prong_item_count);
70917091
70927092 for (size_t item_i = 0; item_i < prong_item_count; item_i += 1) {
70937093 AstNode *item_node = prong_node->data.switch_prong.items.at(item_i);
70947094 assert(item_node->type != NodeTypeSwitchRange);
70957095
7096 IrInstSrc *item_value = astgen_node(ag, item_node, comptime_scope);
7096 Stage1ZirInst *item_value = astgen_node(ag, item_node, comptime_scope);
70977097 if (item_value == ag->codegen->invalid_inst_src)
70987098 return ag->codegen->invalid_inst_src;
70997099
7100 IrInstSrcCheckSwitchProngsRange *check_range = check_ranges.add_one();
7100 Stage1ZirInstCheckSwitchProngsRange *check_range = check_ranges.add_one();
71017101 check_range->start = item_value;
71027102 check_range->end = item_value;
71037103
7104 IrInstSrcSwitchBrCase *this_case = cases.add_one();
7104 Stage1ZirInstSwitchBrCase *this_case = cases.add_one();
71057105 this_case->value = item_value;
71067106 this_case->block = prong_block;
71077107
......@@ -7125,14 +7125,14 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
71257125
71267126 }
71277127
7128 IrInstSrc *switch_prongs_void = ir_build_check_switch_prongs(ag, scope, node, target_value,
7128 Stage1ZirInst *switch_prongs_void = ir_build_check_switch_prongs(ag, scope, node, target_value,
71297129 check_ranges.items, check_ranges.length, else_prong, underscore_prong != nullptr);
71307130
7131 IrInstSrc *br_instruction;
7131 Stage1ZirInst *br_instruction;
71327132 if (cases.length == 0) {
71337133 br_instruction = ir_build_br(ag, scope, node, else_block, is_comptime);
71347134 } else {
7135 IrInstSrcSwitchBr *switch_br = ir_build_switch_br_src(ag, scope, node, target_value, else_block,
7135 Stage1ZirInstSwitchBr *switch_br = ir_build_switch_br_src(ag, scope, node, target_value, else_block,
71367136 cases.length, cases.items, is_comptime, switch_prongs_void);
71377137 if (switch_else_var != nullptr) {
71387138 switch_else_var->switch_br = switch_br;
......@@ -7160,7 +7160,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
71607160
71617161 ir_set_cursor_at_end_and_append_block(ag, end_block);
71627162 assert(incoming_blocks.length == incoming_values.length);
7163 IrInstSrc *result_instruction;
7163 Stage1ZirInst *result_instruction;
71647164 if (incoming_blocks.length == 0) {
71657165 result_instruction = ir_build_const_void(ag, scope, node);
71667166 } else {
......@@ -7170,7 +7170,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
71707170 return ir_lval_wrap(ag, scope, result_instruction, lval, result_loc);
71717171}
71727172
7173static IrInstSrc *astgen_comptime(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) {
7173static Stage1ZirInst *astgen_comptime(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) {
71747174 assert(node->type == NodeTypeCompTime);
71757175
71767176 Scope *child_scope = create_comptime_scope(ag->codegen, node, parent_scope);
......@@ -7178,7 +7178,7 @@ static IrInstSrc *astgen_comptime(Stage1AstGen *ag, Scope *parent_scope, AstNode
71787178 return astgen_node_extra(ag, node->data.comptime_expr.expr, child_scope, lval, nullptr);
71797179}
71807180
7181static IrInstSrc *astgen_nosuspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) {
7181static Stage1ZirInst *astgen_nosuspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) {
71827182 assert(node->type == NodeTypeNoSuspend);
71837183
71847184 Scope *child_scope = create_nosuspend_scope(ag->codegen, node, parent_scope);
......@@ -7186,15 +7186,15 @@ static IrInstSrc *astgen_nosuspend(Stage1AstGen *ag, Scope *parent_scope, AstNod
71867186 return astgen_node_extra(ag, node->data.nosuspend_expr.expr, child_scope, lval, nullptr);
71877187}
71887188
7189static IrInstSrc *astgen_return_from_block(Stage1AstGen *ag, Scope *break_scope, AstNode *node, ScopeBlock *block_scope) {
7190 IrInstSrc *is_comptime;
7189static Stage1ZirInst *astgen_return_from_block(Stage1AstGen *ag, Scope *break_scope, AstNode *node, ScopeBlock *block_scope) {
7190 Stage1ZirInst *is_comptime;
71917191 if (ir_should_inline(ag->exec, break_scope)) {
71927192 is_comptime = ir_build_const_bool(ag, break_scope, node, true);
71937193 } else {
71947194 is_comptime = block_scope->is_comptime;
71957195 }
71967196
7197 IrInstSrc *result_value;
7197 Stage1ZirInst *result_value;
71987198 if (node->data.break_expr.expr) {
71997199 ResultLocPeer *peer_result = create_peer_result(block_scope->peer_parent);
72007200 block_scope->peer_parent->peers.append(peer_result);
......@@ -7216,7 +7216,7 @@ static IrInstSrc *astgen_return_from_block(Stage1AstGen *ag, Scope *break_scope,
72167216 return ir_build_br(ag, break_scope, node, dest_block, is_comptime);
72177217}
72187218
7219static IrInstSrc *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *node) {
7219static Stage1ZirInst *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *node) {
72207220 assert(node->type == NodeTypeBreak);
72217221
72227222 // Search up the scope. We'll find one of these things first:
......@@ -7264,14 +7264,14 @@ static IrInstSrc *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *no
72647264 search_scope = search_scope->parent;
72657265 }
72667266
7267 IrInstSrc *is_comptime;
7267 Stage1ZirInst *is_comptime;
72687268 if (ir_should_inline(ag->exec, break_scope)) {
72697269 is_comptime = ir_build_const_bool(ag, break_scope, node, true);
72707270 } else {
72717271 is_comptime = loop_scope->is_comptime;
72727272 }
72737273
7274 IrInstSrc *result_value;
7274 Stage1ZirInst *result_value;
72757275 if (node->data.break_expr.expr) {
72767276 ResultLocPeer *peer_result = create_peer_result(loop_scope->peer_parent);
72777277 loop_scope->peer_parent->peers.append(peer_result);
......@@ -7293,7 +7293,7 @@ static IrInstSrc *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *no
72937293 return ir_build_br(ag, break_scope, node, dest_block, is_comptime);
72947294}
72957295
7296static IrInstSrc *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNode *node) {
7296static Stage1ZirInst *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNode *node) {
72977297 assert(node->type == NodeTypeContinue);
72987298
72997299 // Search up the scope. We'll find one of these things first:
......@@ -7333,7 +7333,7 @@ static IrInstSrc *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNo
73337333 search_scope = search_scope->parent;
73347334 }
73357335
7336 IrInstSrc *is_comptime;
7336 Stage1ZirInst *is_comptime;
73377337 if (ir_should_inline(ag->exec, continue_scope)) {
73387338 is_comptime = ir_build_const_bool(ag, continue_scope, node, true);
73397339 } else {
......@@ -7352,12 +7352,12 @@ static IrInstSrc *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNo
73527352 return ir_build_br(ag, continue_scope, node, dest_block, is_comptime);
73537353}
73547354
7355static IrInstSrc *astgen_error_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
7355static Stage1ZirInst *astgen_error_type(Stage1AstGen *ag, Scope *scope, AstNode *node) {
73567356 assert(node->type == NodeTypeErrorType);
73577357 return ir_build_const_type(ag, scope, node, ag->codegen->builtin_types.entry_global_error_set);
73587358}
73597359
7360static IrInstSrc *astgen_defer(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
7360static Stage1ZirInst *astgen_defer(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
73617361 assert(node->type == NodeTypeDefer);
73627362
73637363 ScopeDefer *defer_child_scope = create_defer_scope(ag->codegen, node, parent_scope);
......@@ -7369,7 +7369,7 @@ static IrInstSrc *astgen_defer(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
73697369 return ir_build_const_void(ag, parent_scope, node);
73707370}
73717371
7372static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {
7372static Stage1ZirInst *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) {
73737373 assert(node->type == NodeTypeSliceExpr);
73747374
73757375 AstNodeSliceExpr *slice_expr = &node->data.slice_expr;
......@@ -7378,15 +7378,15 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV
73787378 AstNode *end_node = slice_expr->end;
73797379 AstNode *sentinel_node = slice_expr->sentinel;
73807380
7381 IrInstSrc *ptr_value = astgen_node_extra(ag, array_node, scope, LValPtr, nullptr);
7381 Stage1ZirInst *ptr_value = astgen_node_extra(ag, array_node, scope, LValPtr, nullptr);
73827382 if (ptr_value == ag->codegen->invalid_inst_src)
73837383 return ag->codegen->invalid_inst_src;
73847384
7385 IrInstSrc *start_value = astgen_node(ag, start_node, scope);
7385 Stage1ZirInst *start_value = astgen_node(ag, start_node, scope);
73867386 if (start_value == ag->codegen->invalid_inst_src)
73877387 return ag->codegen->invalid_inst_src;
73887388
7389 IrInstSrc *end_value;
7389 Stage1ZirInst *end_value;
73907390 if (end_node) {
73917391 end_value = astgen_node(ag, end_node, scope);
73927392 if (end_value == ag->codegen->invalid_inst_src)
......@@ -7395,7 +7395,7 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV
73957395 end_value = nullptr;
73967396 }
73977397
7398 IrInstSrc *sentinel_value;
7398 Stage1ZirInst *sentinel_value;
73997399 if (sentinel_node) {
74007400 sentinel_value = astgen_node(ag, sentinel_node, scope);
74017401 if (sentinel_value == ag->codegen->invalid_inst_src)
......@@ -7404,12 +7404,12 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV
74047404 sentinel_value = nullptr;
74057405 }
74067406
7407 IrInstSrc *slice = ir_build_slice_src(ag, scope, node, ptr_value, start_value, end_value,
7407 Stage1ZirInst *slice = ir_build_slice_src(ag, scope, node, ptr_value, start_value, end_value,
74087408 sentinel_value, true, result_loc);
74097409 return ir_lval_wrap(ag, scope, slice, lval, result_loc);
74107410}
74117411
7412static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,
7412static Stage1ZirInst *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval,
74137413 ResultLoc *result_loc)
74147414{
74157415 assert(node->type == NodeTypeCatchExpr);
......@@ -7432,13 +7432,13 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
74327432 ScopeExpr *spill_scope = create_expr_scope(ag->codegen, op1_node, parent_scope);
74337433 spill_scope->spill_harder = true;
74347434
7435 IrInstSrc *err_union_ptr = astgen_node_extra(ag, op1_node, &spill_scope->base, LValPtr, nullptr);
7435 Stage1ZirInst *err_union_ptr = astgen_node_extra(ag, op1_node, &spill_scope->base, LValPtr, nullptr);
74367436 if (err_union_ptr == ag->codegen->invalid_inst_src)
74377437 return ag->codegen->invalid_inst_src;
74387438
7439 IrInstSrc *is_err = ir_build_test_err_src(ag, parent_scope, node, err_union_ptr, true, false);
7439 Stage1ZirInst *is_err = ir_build_test_err_src(ag, parent_scope, node, err_union_ptr, true, false);
74407440
7441 IrInstSrc *is_comptime;
7441 Stage1ZirInst *is_comptime;
74427442 if (ir_should_inline(ag->exec, parent_scope)) {
74437443 is_comptime = ir_build_const_bool(ag, parent_scope, node, true);
74447444 } else {
......@@ -7448,7 +7448,7 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
74487448 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrOk");
74497449 Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrError");
74507450 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrEnd");
7451 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_err, err_block, ok_block, is_comptime);
7451 Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_err, err_block, ok_block, is_comptime);
74527452
74537453 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block, result_loc,
74547454 is_comptime);
......@@ -7464,13 +7464,13 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
74647464 ZigVar *var = ir_create_var(ag, node, subexpr_scope, var_name,
74657465 is_const, is_const, is_shadowable, is_comptime);
74667466 err_scope = var->child_scope;
7467 IrInstSrc *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, node, err_union_ptr);
7468 IrInstSrc *err_value = ir_build_load_ptr(ag, err_scope, var_node, err_ptr);
7467 Stage1ZirInst *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, node, err_union_ptr);
7468 Stage1ZirInst *err_value = ir_build_load_ptr(ag, err_scope, var_node, err_ptr);
74697469 build_decl_var_and_init(ag, err_scope, var_node, var, err_value, buf_ptr(var_name), is_comptime);
74707470 } else {
74717471 err_scope = subexpr_scope;
74727472 }
7473 IrInstSrc *err_result = astgen_node_extra(ag, op2_node, err_scope, LValNone, &peer_parent->peers.at(0)->base);
7473 Stage1ZirInst *err_result = astgen_node_extra(ag, op2_node, err_scope, LValNone, &peer_parent->peers.at(0)->base);
74747474 if (err_result == ag->codegen->invalid_inst_src)
74757475 return ag->codegen->invalid_inst_src;
74767476 Stage1ZirBasicBlock *after_err_block = ag->current_basic_block;
......@@ -7478,20 +7478,20 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
74787478 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
74797479
74807480 ir_set_cursor_at_end_and_append_block(ag, ok_block);
7481 IrInstSrc *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, parent_scope, node, err_union_ptr, false, false);
7482 IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);
7481 Stage1ZirInst *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, parent_scope, node, err_union_ptr, false, false);
7482 Stage1ZirInst *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);
74837483 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);
74847484 Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block;
74857485 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
74867486
74877487 ir_set_cursor_at_end_and_append_block(ag, end_block);
7488 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
7488 Stage1ZirInst **incoming_values = heap::c_allocator.allocate<Stage1ZirInst *>(2);
74897489 incoming_values[0] = err_result;
74907490 incoming_values[1] = unwrapped_payload;
74917491 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
74927492 incoming_blocks[0] = after_err_block;
74937493 incoming_blocks[1] = after_ok_block;
7494 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);
7494 Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);
74957495 return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc);
74967496}
74977497
......@@ -7540,7 +7540,7 @@ Buf *get_anon_type_name(CodeGen *codegen, Stage1Zir *exec, const char *kind_name
75407540 }
75417541}
75427542
7543static IrInstSrc *astgen_container_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
7543static Stage1ZirInst *astgen_container_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
75447544 assert(node->type == NodeTypeContainerDecl);
75457545
75467546 ContainerKind kind = node->data.container_decl.kind;
......@@ -7569,7 +7569,7 @@ static IrInstSrc *astgen_container_decl(Stage1AstGen *ag, Scope *parent_scope, A
75697569 return ir_build_const_type(ag, parent_scope, node, container_type);
75707570}
75717571
7572static IrInstSrc *astgen_err_set_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
7572static Stage1ZirInst *astgen_err_set_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
75737573 assert(node->type == NodeTypeErrorSetDecl);
75747574
75757575 uint32_t err_count = node->data.err_set_decl.decls.length;
......@@ -7620,11 +7620,11 @@ static IrInstSrc *astgen_err_set_decl(Stage1AstGen *ag, Scope *parent_scope, Ast
76207620 return ir_build_const_type(ag, parent_scope, node, err_set_type);
76217621}
76227622
7623static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
7623static Stage1ZirInst *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
76247624 assert(node->type == NodeTypeFnProto);
76257625
76267626 size_t param_count = node->data.fn_proto.params.length;
7627 IrInstSrc **param_types = heap::c_allocator.allocate<IrInstSrc*>(param_count);
7627 Stage1ZirInst **param_types = heap::c_allocator.allocate<Stage1ZirInst*>(param_count);
76287628
76297629 bool is_var_args = false;
76307630 for (size_t i = 0; i < param_count; i += 1) {
......@@ -7635,7 +7635,7 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode
76357635 }
76367636 if (param_node->data.param_decl.anytype_token == 0) {
76377637 AstNode *type_node = param_node->data.param_decl.type;
7638 IrInstSrc *type_value = astgen_node(ag, type_node, parent_scope);
7638 Stage1ZirInst *type_value = astgen_node(ag, type_node, parent_scope);
76397639 if (type_value == ag->codegen->invalid_inst_src)
76407640 return ag->codegen->invalid_inst_src;
76417641 param_types[i] = type_value;
......@@ -7644,21 +7644,21 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode
76447644 }
76457645 }
76467646
7647 IrInstSrc *align_value = nullptr;
7647 Stage1ZirInst *align_value = nullptr;
76487648 if (node->data.fn_proto.align_expr != nullptr) {
76497649 align_value = astgen_node(ag, node->data.fn_proto.align_expr, parent_scope);
76507650 if (align_value == ag->codegen->invalid_inst_src)
76517651 return ag->codegen->invalid_inst_src;
76527652 }
76537653
7654 IrInstSrc *callconv_value = nullptr;
7654 Stage1ZirInst *callconv_value = nullptr;
76557655 if (node->data.fn_proto.callconv_expr != nullptr) {
76567656 callconv_value = astgen_node(ag, node->data.fn_proto.callconv_expr, parent_scope);
76577657 if (callconv_value == ag->codegen->invalid_inst_src)
76587658 return ag->codegen->invalid_inst_src;
76597659 }
76607660
7661 IrInstSrc *return_type;
7661 Stage1ZirInst *return_type;
76627662 if (node->data.fn_proto.return_type == nullptr) {
76637663 return_type = ir_build_const_type(ag, parent_scope, node, ag->codegen->builtin_types.entry_void);
76647664 } else {
......@@ -7670,17 +7670,17 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode
76707670 return ir_build_fn_proto(ag, parent_scope, node, param_types, align_value, callconv_value, return_type, is_var_args);
76717671}
76727672
7673static IrInstSrc *astgen_resume(Stage1AstGen *ag, Scope *scope, AstNode *node) {
7673static Stage1ZirInst *astgen_resume(Stage1AstGen *ag, Scope *scope, AstNode *node) {
76747674 assert(node->type == NodeTypeResume);
76757675
7676 IrInstSrc *target_inst = astgen_node_extra(ag, node->data.resume_expr.expr, scope, LValPtr, nullptr);
7676 Stage1ZirInst *target_inst = astgen_node_extra(ag, node->data.resume_expr.expr, scope, LValPtr, nullptr);
76777677 if (target_inst == ag->codegen->invalid_inst_src)
76787678 return ag->codegen->invalid_inst_src;
76797679
76807680 return ir_build_resume_src(ag, scope, node, target_inst);
76817681}
76827682
7683static IrInstSrc *astgen_await_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
7683static Stage1ZirInst *astgen_await_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval,
76847684 ResultLoc *result_loc)
76857685{
76867686 assert(node->type == NodeTypeAwaitExpr);
......@@ -7714,15 +7714,15 @@ static IrInstSrc *astgen_await_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
77147714 return ag->codegen->invalid_inst_src;
77157715 }
77167716
7717 IrInstSrc *target_inst = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
7717 Stage1ZirInst *target_inst = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
77187718 if (target_inst == ag->codegen->invalid_inst_src)
77197719 return ag->codegen->invalid_inst_src;
77207720
7721 IrInstSrc *await_inst = ir_build_await_src(ag, scope, node, target_inst, result_loc, is_nosuspend);
7721 Stage1ZirInst *await_inst = ir_build_await_src(ag, scope, node, target_inst, result_loc, is_nosuspend);
77227722 return ir_lval_wrap(ag, scope, await_inst, lval, result_loc);
77237723}
77247724
7725static IrInstSrc *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
7725static Stage1ZirInst *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) {
77267726 assert(node->type == NodeTypeSuspend);
77277727
77287728 if (!ag->fn) {
......@@ -7744,10 +7744,10 @@ static IrInstSrc *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode
77447744 return ag->codegen->invalid_inst_src;
77457745 }
77467746
7747 IrInstSrcSuspendBegin *begin = ir_build_suspend_begin_src(ag, parent_scope, node);
7747 Stage1ZirInstSuspendBegin *begin = ir_build_suspend_begin_src(ag, parent_scope, node);
77487748 ScopeSuspend *suspend_scope = create_suspend_scope(ag->codegen, node, parent_scope);
77497749 Scope *child_scope = &suspend_scope->base;
7750 IrInstSrc *susp_res = astgen_node(ag, node->data.suspend.block, child_scope);
7750 Stage1ZirInst *susp_res = astgen_node(ag, node->data.suspend.block, child_scope);
77517751 if (susp_res == ag->codegen->invalid_inst_src)
77527752 return ag->codegen->invalid_inst_src;
77537753 ir_build_check_statement_is_void(ag, child_scope, node->data.suspend.block, susp_res);
......@@ -7755,7 +7755,7 @@ static IrInstSrc *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode
77557755 return ir_build_suspend_finish_src(ag, parent_scope, node, begin);
77567756}
77577757
7758static IrInstSrc *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope,
7758static Stage1ZirInst *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope,
77597759 LVal lval, ResultLoc *result_loc)
77607760{
77617761 assert(scope);
......@@ -7804,13 +7804,13 @@ static IrInstSrc *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope,
78047804 return astgen_return(ag, scope, node, lval, result_loc);
78057805 case NodeTypeFieldAccessExpr:
78067806 {
7807 IrInstSrc *ptr_instruction = astgen_field_access(ag, scope, node);
7807 Stage1ZirInst *ptr_instruction = astgen_field_access(ag, scope, node);
78087808 if (ptr_instruction == ag->codegen->invalid_inst_src)
78097809 return ptr_instruction;
78107810 if (lval == LValPtr || lval == LValAssign)
78117811 return ptr_instruction;
78127812
7813 IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);
7813 Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction);
78147814 return ir_expr_wrap(ag, scope, load_ptr, result_loc);
78157815 }
78167816 case NodeTypePtrDeref: {
......@@ -7820,28 +7820,28 @@ static IrInstSrc *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope,
78207820 if (child_lval == LValAssign)
78217821 child_lval = LValPtr;
78227822
7823 IrInstSrc *value = astgen_node_extra(ag, expr_node, scope, child_lval, nullptr);
7823 Stage1ZirInst *value = astgen_node_extra(ag, expr_node, scope, child_lval, nullptr);
78247824 if (value == ag->codegen->invalid_inst_src)
78257825 return value;
78267826
78277827 // We essentially just converted any lvalue from &(x.*) to (&x).*;
78287828 // this inhibits checking that x is a pointer later, so we directly
78297829 // record whether the pointer check is needed
7830 IrInstSrc *un_op = ir_build_un_op_lval(ag, scope, node, IrUnOpDereference, value, lval, result_loc);
7830 Stage1ZirInst *un_op = ir_build_un_op_lval(ag, scope, node, IrUnOpDereference, value, lval, result_loc);
78317831 return ir_expr_wrap(ag, scope, un_op, result_loc);
78327832 }
78337833 case NodeTypeUnwrapOptional: {
78347834 AstNode *expr_node = node->data.unwrap_optional.expr;
78357835
7836 IrInstSrc *maybe_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
7836 Stage1ZirInst *maybe_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr);
78377837 if (maybe_ptr == ag->codegen->invalid_inst_src)
78387838 return ag->codegen->invalid_inst_src;
78397839
7840 IrInstSrc *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, scope, node, maybe_ptr, true );
7840 Stage1ZirInst *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, scope, node, maybe_ptr, true );
78417841 if (lval == LValPtr || lval == LValAssign)
78427842 return unwrapped_ptr;
78437843
7844 IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, unwrapped_ptr);
7844 Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, unwrapped_ptr);
78457845 return ir_expr_wrap(ag, scope, load_ptr, result_loc);
78467846 }
78477847 case NodeTypeBoolLiteral:
......@@ -7915,7 +7915,7 @@ ResultLoc *no_result_loc(void) {
79157915 return &result_loc_none->base;
79167916}
79177917
7918static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval,
7918static Stage1ZirInst *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval,
79197919 ResultLoc *result_loc)
79207920{
79217921 if (lval == LValAssign) {
......@@ -8023,7 +8023,7 @@ static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scop
80238023 } else {
80248024 child_scope = &create_expr_scope(ag->codegen, node, scope)->base;
80258025 }
8026 IrInstSrc *result = astgen_node_raw(ag, node, child_scope, lval, result_loc);
8026 Stage1ZirInst *result = astgen_node_raw(ag, node, child_scope, lval, result_loc);
80278027 if (result == ag->codegen->invalid_inst_src) {
80288028 if (ag->exec->first_err_trace_msg == nullptr) {
80298029 ag->exec->first_err_trace_msg = ag->codegen->trace_err;
......@@ -8032,7 +8032,7 @@ static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scop
80328032 return result;
80338033}
80348034
8035static IrInstSrc *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope) {
8035static Stage1ZirInst *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope) {
80368036 return astgen_node_extra(ag, node, scope, LValNone, nullptr);
80378037}
80388038
......@@ -8055,7 +8055,7 @@ bool stage1_astgen(CodeGen *codegen, AstNode *node, Scope *scope, Stage1Zir *sta
80558055 // Entry block gets a reference because we enter it to begin.
80568056 ir_ref_bb(ag->current_basic_block);
80578057
8058 IrInstSrc *result = astgen_node_extra(ag, node, scope, LValNone, nullptr);
8058 Stage1ZirInst *result = astgen_node_extra(ag, node, scope, LValNone, nullptr);
80598059
80608060 if (result == ag->codegen->invalid_inst_src)
80618061 return false;
......@@ -8113,8 +8113,8 @@ void ir_add_call_stack_errors_gen(CodeGen *codegen, Stage1Air *exec, ErrorMsg *e
81138113 ir_add_call_stack_errors_gen(codegen, exec->parent_exec, err_msg, limit - 1);
81148114}
81158115
8116void IrInstSrc::src() {
8117 IrInstSrc *inst = this;
8116void Stage1ZirInst::src() {
8117 Stage1ZirInst *inst = this;
81188118 if (inst->source_node != nullptr) {
81198119 inst->source_node->src();
81208120 } else {
src/stage1/astgen.hpp+3-3
......@@ -14,10 +14,10 @@ bool stage1_astgen(CodeGen *g, AstNode *node, Scope *scope, Stage1Zir *stage1_zi
1414 ZigFn *fn, bool in_c_import_scope);
1515bool stage1_astgen_fn(CodeGen *g, ZigFn *fn_entry);
1616
17bool ir_inst_src_has_side_effects(IrInstSrc *inst);
17bool ir_inst_src_has_side_effects(Stage1ZirInst *inst);
1818
1919ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope,
20 Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime,
20 Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime,
2121 bool skip_name_check);
2222
2323ResultLoc *no_result_loc(void);
......@@ -28,7 +28,7 @@ AstNode *ast_field_to_symbol_node(AstNode *err_set_field_node);
2828void ir_add_call_stack_errors_gen(CodeGen *codegen, Stage1Air *exec, ErrorMsg *err_msg,
2929 int limit);
3030
31void destroy_instruction_src(IrInstSrc *inst);
31void destroy_instruction_src(Stage1ZirInst *inst);
3232
3333bool ir_should_inline(Stage1Zir *exec, Scope *scope);
3434Buf *get_anon_type_name(CodeGen *codegen, Stage1Zir *exec, const char *kind_name,
src/stage1/codegen.cpp+301-301
......@@ -84,7 +84,7 @@ static void generate_error_name_table(CodeGen *g);
8484static bool value_is_all_undef(CodeGen *g, ZigValue *const_val);
8585static void gen_undef_init(CodeGen *g, ZigType *ptr_type, ZigType *value_type, LLVMValueRef ptr);
8686static LLVMValueRef build_alloca(CodeGen *g, ZigType *type_entry, const char *name, uint32_t alignment);
87static LLVMValueRef gen_await_early_return(CodeGen *g, IrInstGen *source_instr,
87static LLVMValueRef gen_await_early_return(CodeGen *g, Stage1AirInst *source_instr,
8888 LLVMValueRef target_frame_ptr, ZigType *result_type, ZigType *ptr_result_type,
8989 LLVMValueRef result_loc, bool non_async);
9090
......@@ -906,14 +906,14 @@ static LLVMValueRef get_handle_value(CodeGen *g, LLVMValueRef ptr, ZigType *type
906906 }
907907}
908908
909static void ir_assert_impl(bool ok, IrInstGen *source_instruction, const char *file, unsigned int line) {
909static void ir_assert_impl(bool ok, Stage1AirInst *source_instruction, const char *file, unsigned int line) {
910910 if (ok) return;
911911 src_assert_impl(ok, source_instruction->source_node, file, line);
912912}
913913
914914#define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__)
915915
916static bool ir_want_fast_math(CodeGen *g, IrInstGen *instruction) {
916static bool ir_want_fast_math(CodeGen *g, Stage1AirInst *instruction) {
917917 // TODO memoize
918918 Scope *scope = instruction->scope;
919919 while (scope) {
......@@ -950,7 +950,7 @@ static bool ir_want_runtime_safety_scope(CodeGen *g, Scope *scope) {
950950 g->build_mode != BuildModeSmallRelease);
951951}
952952
953static bool ir_want_runtime_safety(CodeGen *g, IrInstGen *instruction) {
953static bool ir_want_runtime_safety(CodeGen *g, Stage1AirInst *instruction) {
954954 return ir_want_runtime_safety_scope(g, instruction->scope);
955955}
956956
......@@ -1077,7 +1077,7 @@ static void gen_assertion_scope(CodeGen *g, PanicMsgId msg_id, Scope *source_sco
10771077 }
10781078}
10791079
1080static void gen_assertion(CodeGen *g, PanicMsgId msg_id, IrInstGen *source_instruction) {
1080static void gen_assertion(CodeGen *g, PanicMsgId msg_id, Stage1AirInst *source_instruction) {
10811081 return gen_assertion_scope(g, msg_id, source_instruction->scope);
10821082}
10831083
......@@ -1816,7 +1816,7 @@ static void gen_var_debug_decl(CodeGen *g, ZigVar *var) {
18161816 LLVMGetInsertBlock(g->builder));
18171817}
18181818
1819static LLVMValueRef ir_llvm_value(CodeGen *g, IrInstGen *instruction) {
1819static LLVMValueRef ir_llvm_value(CodeGen *g, Stage1AirInst *instruction) {
18201820 Error err;
18211821
18221822 bool value_has_bits;
......@@ -1827,8 +1827,8 @@ static LLVMValueRef ir_llvm_value(CodeGen *g, IrInstGen *instruction) {
18271827 return nullptr;
18281828
18291829 if (!instruction->llvm_value) {
1830 if (instruction->id == IrInstGenIdAwait) {
1831 IrInstGenAwait *await = reinterpret_cast<IrInstGenAwait*>(instruction);
1830 if (instruction->id == Stage1AirInstIdAwait) {
1831 Stage1AirInstAwait *await = reinterpret_cast<Stage1AirInstAwait*>(instruction);
18321832 if (await->result_loc != nullptr) {
18331833 return get_handle_value(g, ir_llvm_value(g, await->result_loc),
18341834 await->result_loc->value->type->data.pointer.child_type, await->result_loc->value->type);
......@@ -1921,7 +1921,7 @@ static bool iter_function_params_c_abi(CodeGen *g, ZigType *fn_type, FnWalk *fn_
19211921 case FnWalkIdCall: {
19221922 if (src_i >= fn_walk->data.call.inst->arg_count)
19231923 return false;
1924 IrInstGen *arg = fn_walk->data.call.inst->args[src_i];
1924 Stage1AirInst *arg = fn_walk->data.call.inst->args[src_i];
19251925 ty = arg->value->type;
19261926 source_node = arg->source_node;
19271927 val = ir_llvm_value(g, arg);
......@@ -2228,10 +2228,10 @@ void walk_function_params(CodeGen *g, ZigType *fn_type, FnWalk *fn_walk) {
22282228 return;
22292229 }
22302230 if (fn_walk->id == FnWalkIdCall) {
2231 IrInstGenCall *instruction = fn_walk->data.call.inst;
2231 Stage1AirInstCall *instruction = fn_walk->data.call.inst;
22322232 bool is_var_args = fn_walk->data.call.is_var_args;
22332233 for (size_t call_i = 0; call_i < instruction->arg_count; call_i += 1) {
2234 IrInstGen *param_instruction = instruction->args[call_i];
2234 Stage1AirInst *param_instruction = instruction->args[call_i];
22352235 ZigType *param_type = param_instruction->value->type;
22362236 if (is_var_args || type_has_bits(g, param_type)) {
22372237 LLVMValueRef param_value = ir_llvm_value(g, param_instruction);
......@@ -2445,7 +2445,7 @@ static LLVMValueRef get_merge_err_ret_traces_fn_val(CodeGen *g) {
24452445
24462446}
24472447static LLVMValueRef ir_render_save_err_ret_addr(CodeGen *g, Stage1Air *executable,
2448 IrInstGenSaveErrRetAddr *save_err_ret_addr_instruction)
2448 Stage1AirInstSaveErrRetAddr *save_err_ret_addr_instruction)
24492449{
24502450 assert(g->have_err_ret_tracing);
24512451
......@@ -2466,7 +2466,7 @@ static LLVMValueRef ir_render_save_err_ret_addr(CodeGen *g, Stage1Air *executabl
24662466 return nullptr;
24672467}
24682468
2469static void gen_assert_resume_id(CodeGen *g, IrInstGen *source_instr, ResumeId resume_id, PanicMsgId msg_id,
2469static void gen_assert_resume_id(CodeGen *g, Stage1AirInst *source_instr, ResumeId resume_id, PanicMsgId msg_id,
24702470 LLVMBasicBlockRef end_bb)
24712471{
24722472 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;
......@@ -2543,7 +2543,7 @@ static LLVMValueRef gen_maybe_atomic_op(CodeGen *g, LLVMAtomicRMWBinOp op, LLVMV
25432543 }
25442544}
25452545
2546static void gen_async_return(CodeGen *g, IrInstGenReturn *instruction) {
2546static void gen_async_return(CodeGen *g, Stage1AirInstReturn *instruction) {
25472547 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;
25482548
25492549 ZigType *operand_type = (instruction->operand != nullptr) ? instruction->operand->value->type : nullptr;
......@@ -2637,7 +2637,7 @@ static void gen_async_return(CodeGen *g, IrInstGenReturn *instruction) {
26372637 LLVMBuildRetVoid(g->builder);
26382638}
26392639
2640static LLVMValueRef ir_render_return(CodeGen *g, Stage1Air *executable, IrInstGenReturn *instruction) {
2640static LLVMValueRef ir_render_return(CodeGen *g, Stage1Air *executable, Stage1AirInstReturn *instruction) {
26412641 if (fn_is_async(g->cur_fn)) {
26422642 gen_async_return(g, instruction);
26432643 return nullptr;
......@@ -3063,11 +3063,11 @@ static void gen_shift_rhs_check(CodeGen *g, ZigType *lhs_type, ZigType *rhs_type
30633063}
30643064
30653065static LLVMValueRef ir_render_bin_op(CodeGen *g, Stage1Air *executable,
3066 IrInstGenBinOp *bin_op_instruction)
3066 Stage1AirInstBinOp *bin_op_instruction)
30673067{
30683068 IrBinOp op_id = bin_op_instruction->op_id;
3069 IrInstGen *op1 = bin_op_instruction->op1;
3070 IrInstGen *op2 = bin_op_instruction->op2;
3069 Stage1AirInst *op1 = bin_op_instruction->op1;
3070 Stage1AirInst *op2 = bin_op_instruction->op2;
30713071
30723072 ZigType *operand_type = op1->value->type;
30733073 ZigType *scalar_type = (operand_type->id == ZigTypeIdVector) ? operand_type->data.vector.elem_type : operand_type;
......@@ -3285,7 +3285,7 @@ static void add_error_range_check(CodeGen *g, ZigType *err_set_type, ZigType *in
32853285}
32863286
32873287static LLVMValueRef ir_render_cast(CodeGen *g, Stage1Air *executable,
3288 IrInstGenCast *cast_instruction)
3288 Stage1AirInstCast *cast_instruction)
32893289{
32903290 Error err;
32913291 ZigType *actual_type = cast_instruction->value->value->type;
......@@ -3369,7 +3369,7 @@ static LLVMValueRef ir_render_cast(CodeGen *g, Stage1Air *executable,
33693369}
33703370
33713371static LLVMValueRef ir_render_ptr_of_array_to_slice(CodeGen *g, Stage1Air *executable,
3372 IrInstGenPtrOfArrayToSlice *instruction)
3372 Stage1AirInstPtrOfArrayToSlice *instruction)
33733373{
33743374 ZigType *actual_type = instruction->operand->value->type;
33753375 ZigType *slice_type = instruction->base.value->type;
......@@ -3406,7 +3406,7 @@ static LLVMValueRef ir_render_ptr_of_array_to_slice(CodeGen *g, Stage1Air *execu
34063406}
34073407
34083408static LLVMValueRef ir_render_ptr_cast(CodeGen *g, Stage1Air *executable,
3409 IrInstGenPtrCast *instruction)
3409 Stage1AirInstPtrCast *instruction)
34103410{
34113411 ZigType *wanted_type = instruction->base.value->type;
34123412 if (!type_has_bits(g, wanted_type)) {
......@@ -3432,7 +3432,7 @@ static LLVMValueRef ir_render_ptr_cast(CodeGen *g, Stage1Air *executable,
34323432}
34333433
34343434static LLVMValueRef ir_render_bit_cast(CodeGen *g, Stage1Air *executable,
3435 IrInstGenBitCast *instruction)
3435 Stage1AirInstBitCast *instruction)
34363436{
34373437 ZigType *wanted_type = instruction->base.value->type;
34383438 ZigType *actual_type = instruction->operand->value->type;
......@@ -3460,7 +3460,7 @@ static LLVMValueRef ir_render_bit_cast(CodeGen *g, Stage1Air *executable,
34603460}
34613461
34623462static LLVMValueRef ir_render_widen_or_shorten(CodeGen *g, Stage1Air *executable,
3463 IrInstGenWidenOrShorten *instruction)
3463 Stage1AirInstWidenOrShorten *instruction)
34643464{
34653465 ZigType *actual_type = instruction->target->value->type;
34663466 // TODO instead of this logic, use the Noop instruction to change the type from
......@@ -3476,7 +3476,7 @@ static LLVMValueRef ir_render_widen_or_shorten(CodeGen *g, Stage1Air *executable
34763476 instruction->base.value->type, target_val);
34773477}
34783478
3479static LLVMValueRef ir_render_int_to_ptr(CodeGen *g, Stage1Air *executable, IrInstGenIntToPtr *instruction) {
3479static LLVMValueRef ir_render_int_to_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstIntToPtr *instruction) {
34803480 ZigType *wanted_type = instruction->base.value->type;
34813481 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);
34823482 const uint32_t align_bytes = get_ptr_align(g, wanted_type);
......@@ -3514,13 +3514,13 @@ static LLVMValueRef ir_render_int_to_ptr(CodeGen *g, Stage1Air *executable, IrIn
35143514 return LLVMBuildIntToPtr(g->builder, target_val, get_llvm_type(g, wanted_type), "");
35153515}
35163516
3517static LLVMValueRef ir_render_ptr_to_int(CodeGen *g, Stage1Air *executable, IrInstGenPtrToInt *instruction) {
3517static LLVMValueRef ir_render_ptr_to_int(CodeGen *g, Stage1Air *executable, Stage1AirInstPtrToInt *instruction) {
35183518 ZigType *wanted_type = instruction->base.value->type;
35193519 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);
35203520 return LLVMBuildPtrToInt(g->builder, target_val, get_llvm_type(g, wanted_type), "");
35213521}
35223522
3523static LLVMValueRef ir_render_int_to_enum(CodeGen *g, Stage1Air *executable, IrInstGenIntToEnum *instruction) {
3523static LLVMValueRef ir_render_int_to_enum(CodeGen *g, Stage1Air *executable, Stage1AirInstIntToEnum *instruction) {
35243524 ZigType *wanted_type = instruction->base.value->type;
35253525 assert(wanted_type->id == ZigTypeIdEnum);
35263526 ZigType *tag_int_type = wanted_type->data.enumeration.tag_int_type;
......@@ -3560,7 +3560,7 @@ static LLVMValueRef ir_render_int_to_enum(CodeGen *g, Stage1Air *executable, IrI
35603560 return tag_int_value;
35613561}
35623562
3563static LLVMValueRef ir_render_int_to_err(CodeGen *g, Stage1Air *executable, IrInstGenIntToErr *instruction) {
3563static LLVMValueRef ir_render_int_to_err(CodeGen *g, Stage1Air *executable, Stage1AirInstIntToErr *instruction) {
35643564 ZigType *wanted_type = instruction->base.value->type;
35653565 assert(wanted_type->id == ZigTypeIdErrorSet);
35663566
......@@ -3577,7 +3577,7 @@ static LLVMValueRef ir_render_int_to_err(CodeGen *g, Stage1Air *executable, IrIn
35773577 return gen_widen_or_shorten(g, false, actual_type, g->err_tag_type, target_val);
35783578}
35793579
3580static LLVMValueRef ir_render_err_to_int(CodeGen *g, Stage1Air *executable, IrInstGenErrToInt *instruction) {
3580static LLVMValueRef ir_render_err_to_int(CodeGen *g, Stage1Air *executable, Stage1AirInstErrToInt *instruction) {
35813581 ZigType *wanted_type = instruction->base.value->type;
35823582 assert(wanted_type->id == ZigTypeIdInt);
35833583 assert(!wanted_type->data.integral.is_signed);
......@@ -3604,7 +3604,7 @@ static LLVMValueRef ir_render_err_to_int(CodeGen *g, Stage1Air *executable, IrIn
36043604}
36053605
36063606static LLVMValueRef ir_render_unreachable(CodeGen *g, Stage1Air *executable,
3607 IrInstGenUnreachable *unreachable_instruction)
3607 Stage1AirInstUnreachable *unreachable_instruction)
36083608{
36093609 if (ir_want_runtime_safety(g, &unreachable_instruction->base)) {
36103610 gen_safety_crash(g, PanicMsgIdUnreachable);
......@@ -3615,7 +3615,7 @@ static LLVMValueRef ir_render_unreachable(CodeGen *g, Stage1Air *executable,
36153615}
36163616
36173617static LLVMValueRef ir_render_cond_br(CodeGen *g, Stage1Air *executable,
3618 IrInstGenCondBr *cond_br_instruction)
3618 Stage1AirInstCondBr *cond_br_instruction)
36193619{
36203620 LLVMBuildCondBr(g->builder,
36213621 ir_llvm_value(g, cond_br_instruction->condition),
......@@ -3624,19 +3624,19 @@ static LLVMValueRef ir_render_cond_br(CodeGen *g, Stage1Air *executable,
36243624 return nullptr;
36253625}
36263626
3627static LLVMValueRef ir_render_br(CodeGen *g, Stage1Air *executable, IrInstGenBr *br_instruction) {
3627static LLVMValueRef ir_render_br(CodeGen *g, Stage1Air *executable, Stage1AirInstBr *br_instruction) {
36283628 LLVMBuildBr(g->builder, br_instruction->dest_block->llvm_block);
36293629 return nullptr;
36303630}
36313631
36323632static LLVMValueRef ir_render_binary_not(CodeGen *g, Stage1Air *executable,
3633 IrInstGenBinaryNot *inst)
3633 Stage1AirInstBinaryNot *inst)
36343634{
36353635 LLVMValueRef operand = ir_llvm_value(g, inst->operand);
36363636 return LLVMBuildNot(g->builder, operand, "");
36373637}
36383638
3639static LLVMValueRef ir_gen_negation(CodeGen *g, IrInstGen *inst, IrInstGen *operand, bool wrapping) {
3639static LLVMValueRef ir_gen_negation(CodeGen *g, Stage1AirInst *inst, Stage1AirInst *operand, bool wrapping) {
36403640 LLVMValueRef llvm_operand = ir_llvm_value(g, operand);
36413641 ZigType *operand_type = operand->value->type;
36423642 ZigType *scalar_type = (operand_type->id == ZigTypeIdVector) ?
......@@ -3662,12 +3662,12 @@ static LLVMValueRef ir_gen_negation(CodeGen *g, IrInstGen *inst, IrInstGen *oper
36623662}
36633663
36643664static LLVMValueRef ir_render_negation(CodeGen *g, Stage1Air *executable,
3665 IrInstGenNegation *inst)
3665 Stage1AirInstNegation *inst)
36663666{
36673667 return ir_gen_negation(g, &inst->base, inst->operand, inst->wrapping);
36683668}
36693669
3670static LLVMValueRef ir_render_bool_not(CodeGen *g, Stage1Air *executable, IrInstGenBoolNot *instruction) {
3670static LLVMValueRef ir_render_bool_not(CodeGen *g, Stage1Air *executable, Stage1AirInstBoolNot *instruction) {
36713671 LLVMValueRef value = ir_llvm_value(g, instruction->value);
36723672 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(value));
36733673 return LLVMBuildICmp(g->builder, LLVMIntEQ, value, zero, "");
......@@ -3681,7 +3681,7 @@ static void render_decl_var(CodeGen *g, ZigVar *var) {
36813681 gen_var_debug_decl(g, var);
36823682}
36833683
3684static LLVMValueRef ir_render_decl_var(CodeGen *g, Stage1Air *executable, IrInstGenDeclVar *instruction) {
3684static LLVMValueRef ir_render_decl_var(CodeGen *g, Stage1Air *executable, Stage1AirInstDeclVar *instruction) {
36853685 instruction->var->ptr_instruction = instruction->var_ptr;
36863686 instruction->var->did_the_decl_codegen = true;
36873687 render_decl_var(g, instruction->var);
......@@ -3689,7 +3689,7 @@ static LLVMValueRef ir_render_decl_var(CodeGen *g, Stage1Air *executable, IrInst
36893689}
36903690
36913691static LLVMValueRef ir_render_load_ptr(CodeGen *g, Stage1Air *executable,
3692 IrInstGenLoadPtr *instruction)
3692 Stage1AirInstLoadPtr *instruction)
36933693{
36943694 ZigType *child_type = instruction->base.value->type;
36953695 if (!type_has_bits(g, child_type))
......@@ -3896,7 +3896,7 @@ static void gen_undef_init(CodeGen *g, ZigType *ptr_type, ZigType *value_type, L
38963896 gen_assign_raw(g, ptr, ptr_type, zero);
38973897}
38983898
3899static LLVMValueRef ir_render_store_ptr(CodeGen *g, Stage1Air *executable, IrInstGenStorePtr *instruction) {
3899static LLVMValueRef ir_render_store_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstStorePtr *instruction) {
39003900 Error err;
39013901
39023902 ZigType *ptr_type = instruction->ptr->value->type;
......@@ -3929,7 +3929,7 @@ static LLVMValueRef ir_render_store_ptr(CodeGen *g, Stage1Air *executable, IrIns
39293929}
39303930
39313931static LLVMValueRef ir_render_vector_store_elem(CodeGen *g, Stage1Air *executable,
3932 IrInstGenVectorStoreElem *instruction)
3932 Stage1AirInstVectorStoreElem *instruction)
39333933{
39343934 LLVMValueRef vector_ptr = ir_llvm_value(g, instruction->vector_ptr);
39353935 LLVMValueRef index = ir_llvm_value(g, instruction->index);
......@@ -3941,7 +3941,7 @@ static LLVMValueRef ir_render_vector_store_elem(CodeGen *g, Stage1Air *executabl
39413941 return nullptr;
39423942}
39433943
3944static LLVMValueRef ir_render_var_ptr(CodeGen *g, Stage1Air *executable, IrInstGenVarPtr *instruction) {
3944static LLVMValueRef ir_render_var_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstVarPtr *instruction) {
39453945 Error err;
39463946
39473947 ZigType *ptr_type = instruction->base.value->type;
......@@ -3969,7 +3969,7 @@ static LLVMValueRef ir_render_var_ptr(CodeGen *g, Stage1Air *executable, IrInstG
39693969}
39703970
39713971static LLVMValueRef ir_render_return_ptr(CodeGen *g, Stage1Air *executable,
3972 IrInstGenReturnPtr *instruction)
3972 Stage1AirInstReturnPtr *instruction)
39733973{
39743974 if (!type_has_bits(g, instruction->base.value->type))
39753975 return nullptr;
......@@ -3977,7 +3977,7 @@ static LLVMValueRef ir_render_return_ptr(CodeGen *g, Stage1Air *executable,
39773977 return g->cur_ret_ptr;
39783978}
39793979
3980static LLVMValueRef ir_render_elem_ptr(CodeGen *g, Stage1Air *executable, IrInstGenElemPtr *instruction) {
3980static LLVMValueRef ir_render_elem_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstElemPtr *instruction) {
39813981 LLVMValueRef array_ptr_ptr = ir_llvm_value(g, instruction->array_ptr);
39823982 ZigType *array_ptr_type = instruction->array_ptr->value->type;
39833983 assert(array_ptr_type->id == ZigTypeIdPointer);
......@@ -4152,7 +4152,7 @@ static void render_async_spills(CodeGen *g) {
41524152 ZigType *frame_type = g->cur_fn->frame_type->data.frame.locals_struct;
41534153
41544154 for (size_t alloca_i = 0; alloca_i < g->cur_fn->alloca_gen_list.length; alloca_i += 1) {
4155 IrInstGenAlloca *instruction = g->cur_fn->alloca_gen_list.at(alloca_i);
4155 Stage1AirInstAlloca *instruction = g->cur_fn->alloca_gen_list.at(alloca_i);
41564156 if (instruction->field_index == SIZE_MAX)
41574157 continue;
41584158
......@@ -4229,7 +4229,7 @@ static void gen_init_stack_trace(CodeGen *g, LLVMValueRef trace_field_ptr, LLVMV
42294229 LLVMBuildStore(g->builder, LLVMConstInt(usize_type_ref, stack_trace_ptr_count, false), addrs_len_ptr);
42304230}
42314231
4232static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, IrInstGenCall *instruction) {
4232static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, Stage1AirInstCall *instruction) {
42334233 Error err;
42344234
42354235 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;
......@@ -4579,7 +4579,7 @@ static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, IrInstGenC
45794579 return nullptr;
45804580
45814581 if (result_loc != nullptr) {
4582 if (instruction->result_loc->id == IrInstGenIdReturnPtr) {
4582 if (instruction->result_loc->id == Stage1AirInstIdReturnPtr) {
45834583 instruction->base.spill = nullptr;
45844584 return g->cur_ret_ptr;
45854585 } else {
......@@ -4650,7 +4650,7 @@ static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, IrInstGenC
46504650}
46514651
46524652static LLVMValueRef ir_render_struct_field_ptr(CodeGen *g, Stage1Air *executable,
4653 IrInstGenStructFieldPtr *instruction)
4653 Stage1AirInstStructFieldPtr *instruction)
46544654{
46554655 Error err;
46564656
......@@ -4701,7 +4701,7 @@ static LLVMValueRef ir_render_struct_field_ptr(CodeGen *g, Stage1Air *executable
47014701}
47024702
47034703static LLVMValueRef ir_render_union_field_ptr(CodeGen *g, Stage1Air *executable,
4704 IrInstGenUnionFieldPtr *instruction)
4704 Stage1AirInstUnionFieldPtr *instruction)
47054705{
47064706 if (instruction->base.value->special != ConstValSpecialRuntime)
47074707 return nullptr;
......@@ -4800,7 +4800,7 @@ static size_t find_asm_index(CodeGen *g, AstNode *node, AsmToken *tok, Buf *src_
48004800 return SIZE_MAX;
48014801}
48024802
4803static LLVMValueRef ir_render_asm_gen(CodeGen *g, Stage1Air *executable, IrInstGenAsm *instruction) {
4803static LLVMValueRef ir_render_asm_gen(CodeGen *g, Stage1Air *executable, Stage1AirInstAsm *instruction) {
48044804 AstNode *asm_node = instruction->base.source_node;
48054805 assert(asm_node->type == NodeTypeAsmExpr);
48064806 AstNodeAsmExpr *asm_expr = &asm_node->data.asm_expr;
......@@ -4885,7 +4885,7 @@ static LLVMValueRef ir_render_asm_gen(CodeGen *g, Stage1Air *executable, IrInstG
48854885 for (size_t i = 0; i < asm_expr->input_list.length; i += 1, total_index += 1, param_index += 1) {
48864886 AsmInput *asm_input = asm_expr->input_list.at(i);
48874887 buf_replace(asm_input->constraint, ',', '|');
4888 IrInstGen *ir_input = instruction->input_list[i];
4888 Stage1AirInst *ir_input = instruction->input_list[i];
48894889 buf_append_buf(&constraint_buf, asm_input->constraint);
48904890 if (total_index + 1 < total_constraint_count) {
48914891 buf_append_char(&constraint_buf, ',');
......@@ -4978,13 +4978,13 @@ static LLVMValueRef gen_non_null_bit(CodeGen *g, ZigType *maybe_type, LLVMValueR
49784978}
49794979
49804980static LLVMValueRef ir_render_test_non_null(CodeGen *g, Stage1Air *executable,
4981 IrInstGenTestNonNull *instruction)
4981 Stage1AirInstTestNonNull *instruction)
49824982{
49834983 return gen_non_null_bit(g, instruction->value->value->type, ir_llvm_value(g, instruction->value));
49844984}
49854985
49864986static LLVMValueRef ir_render_optional_unwrap_ptr(CodeGen *g, Stage1Air *executable,
4987 IrInstGenOptionalUnwrapPtr *instruction)
4987 Stage1AirInstOptionalUnwrapPtr *instruction)
49884988{
49894989 if (instruction->base.value->special != ConstValSpecialRuntime)
49904990 return nullptr;
......@@ -5090,7 +5090,7 @@ static LLVMValueRef get_int_builtin_fn(CodeGen *g, ZigType *expr_type, BuiltinFn
50905090 return fn_val;
50915091}
50925092
5093static LLVMValueRef ir_render_clz(CodeGen *g, Stage1Air *executable, IrInstGenClz *instruction) {
5093static LLVMValueRef ir_render_clz(CodeGen *g, Stage1Air *executable, Stage1AirInstClz *instruction) {
50945094 ZigType *int_type = instruction->op->value->type;
50955095 LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdClz);
50965096 LLVMValueRef operand = ir_llvm_value(g, instruction->op);
......@@ -5102,7 +5102,7 @@ static LLVMValueRef ir_render_clz(CodeGen *g, Stage1Air *executable, IrInstGenCl
51025102 return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int);
51035103}
51045104
5105static LLVMValueRef ir_render_ctz(CodeGen *g, Stage1Air *executable, IrInstGenCtz *instruction) {
5105static LLVMValueRef ir_render_ctz(CodeGen *g, Stage1Air *executable, Stage1AirInstCtz *instruction) {
51065106 ZigType *int_type = instruction->op->value->type;
51075107 LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdCtz);
51085108 LLVMValueRef operand = ir_llvm_value(g, instruction->op);
......@@ -5114,7 +5114,7 @@ static LLVMValueRef ir_render_ctz(CodeGen *g, Stage1Air *executable, IrInstGenCt
51145114 return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int);
51155115}
51165116
5117static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable, IrInstGenShuffleVector *instruction) {
5117static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable, Stage1AirInstShuffleVector *instruction) {
51185118 uint64_t len_a = instruction->a->value->type->data.vector.len;
51195119 uint64_t len_mask = instruction->mask->value->type->data.vector.len;
51205120
......@@ -5123,7 +5123,7 @@ static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable,
51235123 // when changing code, so Zig uses negative numbers to index the
51245124 // second vector. These start at -1 and go down, and are easiest to use
51255125 // with the ~ operator. Here we convert between the two formats.
5126 IrInstGen *mask = instruction->mask;
5126 Stage1AirInst *mask = instruction->mask;
51275127 LLVMValueRef *values = heap::c_allocator.allocate<LLVMValueRef>(len_mask);
51285128 for (uint64_t i = 0; i < len_mask; i++) {
51295129 if (mask->value->data.x_array.data.s_none.elements[i].special == ConstValSpecialUndef) {
......@@ -5144,7 +5144,7 @@ static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable,
51445144 llvm_mask_value, "");
51455145}
51465146
5147static LLVMValueRef ir_render_splat(CodeGen *g, Stage1Air *executable, IrInstGenSplat *instruction) {
5147static LLVMValueRef ir_render_splat(CodeGen *g, Stage1Air *executable, Stage1AirInstSplat *instruction) {
51485148 ZigType *result_type = instruction->base.value->type;
51495149 ir_assert(result_type->id == ZigTypeIdVector, &instruction->base);
51505150 uint32_t len = result_type->data.vector.len;
......@@ -5156,7 +5156,7 @@ static LLVMValueRef ir_render_splat(CodeGen *g, Stage1Air *executable, IrInstGen
51565156 return LLVMBuildShuffleVector(g->builder, op_vector, undef_vector, LLVMConstNull(mask_llvm_type), "");
51575157}
51585158
5159static LLVMValueRef ir_render_pop_count(CodeGen *g, Stage1Air *executable, IrInstGenPopCount *instruction) {
5159static LLVMValueRef ir_render_pop_count(CodeGen *g, Stage1Air *executable, Stage1AirInstPopCount *instruction) {
51605160 ZigType *int_type = instruction->op->value->type;
51615161 LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdPopCount);
51625162 LLVMValueRef operand = ir_llvm_value(g, instruction->op);
......@@ -5164,7 +5164,7 @@ static LLVMValueRef ir_render_pop_count(CodeGen *g, Stage1Air *executable, IrIns
51645164 return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int);
51655165}
51665166
5167static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, IrInstGenSwitchBr *instruction) {
5167static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, Stage1AirInstSwitchBr *instruction) {
51685168 ZigType *target_type = instruction->target_value->value->type;
51695169 LLVMBasicBlockRef else_block = instruction->else_block->llvm_block;
51705170
......@@ -5178,7 +5178,7 @@ static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, IrIns
51785178 (unsigned)instruction->case_count);
51795179
51805180 for (size_t i = 0; i < instruction->case_count; i += 1) {
5181 IrInstGenSwitchBrCase *this_case = &instruction->cases[i];
5181 Stage1AirInstSwitchBrCase *this_case = &instruction->cases[i];
51825182
51835183 LLVMValueRef case_value = ir_llvm_value(g, this_case->value);
51845184 if (target_type->id == ZigTypeIdPointer) {
......@@ -5192,7 +5192,7 @@ static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, IrIns
51925192 return nullptr;
51935193}
51945194
5195static LLVMValueRef ir_render_phi(CodeGen *g, Stage1Air *executable, IrInstGenPhi *instruction) {
5195static LLVMValueRef ir_render_phi(CodeGen *g, Stage1Air *executable, Stage1AirInstPhi *instruction) {
51965196 if (!type_has_bits(g, instruction->base.value->type))
51975197 return nullptr;
51985198
......@@ -5216,12 +5216,12 @@ static LLVMValueRef ir_render_phi(CodeGen *g, Stage1Air *executable, IrInstGenPh
52165216 return phi;
52175217}
52185218
5219static LLVMValueRef ir_render_ref(CodeGen *g, Stage1Air *executable, IrInstGenRef *instruction) {
5219static LLVMValueRef ir_render_ref(CodeGen *g, Stage1Air *executable, Stage1AirInstRef *instruction) {
52205220 if (!type_has_bits(g, instruction->base.value->type)) {
52215221 return nullptr;
52225222 }
5223 if (instruction->operand->id == IrInstGenIdCall) {
5224 IrInstGenCall *call = reinterpret_cast<IrInstGenCall *>(instruction->operand);
5223 if (instruction->operand->id == Stage1AirInstIdCall) {
5224 Stage1AirInstCall *call = reinterpret_cast<Stage1AirInstCall *>(instruction->operand);
52255225 if (call->result_loc != nullptr) {
52265226 return ir_llvm_value(g, call->result_loc);
52275227 }
......@@ -5236,7 +5236,7 @@ static LLVMValueRef ir_render_ref(CodeGen *g, Stage1Air *executable, IrInstGenRe
52365236 }
52375237}
52385238
5239static LLVMValueRef ir_render_err_name(CodeGen *g, Stage1Air *executable, IrInstGenErrName *instruction) {
5239static LLVMValueRef ir_render_err_name(CodeGen *g, Stage1Air *executable, Stage1AirInstErrName *instruction) {
52405240 assert(g->generate_error_name_table);
52415241 assert(g->errors_by_index.length > 0);
52425242
......@@ -5363,7 +5363,7 @@ static LLVMValueRef get_enum_tag_name_function(CodeGen *g, ZigType *enum_type) {
53635363}
53645364
53655365static LLVMValueRef ir_render_enum_tag_name(CodeGen *g, Stage1Air *executable,
5366 IrInstGenTagName *instruction)
5366 Stage1AirInstTagName *instruction)
53675367{
53685368 ZigType *enum_type = instruction->target->value->type;
53695369 assert(enum_type->id == ZigTypeIdEnum);
......@@ -5376,7 +5376,7 @@ static LLVMValueRef ir_render_enum_tag_name(CodeGen *g, Stage1Air *executable,
53765376}
53775377
53785378static LLVMValueRef ir_render_field_parent_ptr(CodeGen *g, Stage1Air *executable,
5379 IrInstGenFieldParentPtr *instruction)
5379 Stage1AirInstFieldParentPtr *instruction)
53805380{
53815381 ZigType *container_ptr_type = instruction->base.value->type;
53825382 assert(container_ptr_type->id == ZigTypeIdPointer);
......@@ -5402,7 +5402,7 @@ static LLVMValueRef ir_render_field_parent_ptr(CodeGen *g, Stage1Air *executable
54025402 }
54035403}
54045404
5405static LLVMValueRef ir_render_align_cast(CodeGen *g, Stage1Air *executable, IrInstGenAlignCast *instruction) {
5405static LLVMValueRef ir_render_align_cast(CodeGen *g, Stage1Air *executable, Stage1AirInstAlignCast *instruction) {
54065406 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);
54075407 assert(target_val);
54085408
......@@ -5466,7 +5466,7 @@ static LLVMValueRef ir_render_align_cast(CodeGen *g, Stage1Air *executable, IrIn
54665466}
54675467
54685468static LLVMValueRef ir_render_error_return_trace(CodeGen *g, Stage1Air *executable,
5469 IrInstGenErrorReturnTrace *instruction)
5469 Stage1AirInstErrorReturnTrace *instruction)
54705470{
54715471 bool is_llvm_alloca;
54725472 LLVMValueRef cur_err_ret_trace_val = get_cur_err_ret_trace_val(g, instruction->base.scope, &is_llvm_alloca);
......@@ -5507,7 +5507,7 @@ static enum ZigLLVM_AtomicRMWBinOp to_ZigLLVMAtomicRMWBinOp(AtomicRmwOp op, bool
55075507 zig_unreachable();
55085508}
55095509
5510static LLVMTypeRef get_atomic_abi_type(CodeGen *g, IrInstGen *instruction, bool RMWXchg) {
5510static LLVMTypeRef get_atomic_abi_type(CodeGen *g, Stage1AirInst *instruction, bool RMWXchg) {
55115511 // If the operand type of an atomic operation is not byte sized we need to
55125512 // widen it before using it and then truncate the result.
55135513 // RMW exchange of floating-point values is bitcasted to same-sized integer
......@@ -5538,7 +5538,7 @@ static LLVMTypeRef get_atomic_abi_type(CodeGen *g, IrInstGen *instruction, bool
55385538 }
55395539}
55405540
5541static LLVMValueRef ir_render_cmpxchg(CodeGen *g, Stage1Air *executable, IrInstGenCmpxchg *instruction) {
5541static LLVMValueRef ir_render_cmpxchg(CodeGen *g, Stage1Air *executable, Stage1AirInstCmpxchg *instruction) {
55425542 LLVMValueRef ptr_val = ir_llvm_value(g, instruction->ptr);
55435543 LLVMValueRef cmp_val = ir_llvm_value(g, instruction->cmp_value);
55445544 LLVMValueRef new_val = ir_llvm_value(g, instruction->new_value);
......@@ -5600,7 +5600,7 @@ static LLVMValueRef ir_render_cmpxchg(CodeGen *g, Stage1Air *executable, IrInstG
56005600 return result_loc;
56015601}
56025602
5603static LLVMValueRef ir_render_reduce(CodeGen *g, Stage1Air *executable, IrInstGenReduce *instruction) {
5603static LLVMValueRef ir_render_reduce(CodeGen *g, Stage1Air *executable, Stage1AirInstReduce *instruction) {
56045604 LLVMValueRef value = ir_llvm_value(g, instruction->value);
56055605
56065606 ZigType *value_type = instruction->value->value->type;
......@@ -5664,13 +5664,13 @@ static LLVMValueRef ir_render_reduce(CodeGen *g, Stage1Air *executable, IrInstGe
56645664 return result_val;
56655665}
56665666
5667static LLVMValueRef ir_render_fence(CodeGen *g, Stage1Air *executable, IrInstGenFence *instruction) {
5667static LLVMValueRef ir_render_fence(CodeGen *g, Stage1Air *executable, Stage1AirInstFence *instruction) {
56685668 LLVMAtomicOrdering atomic_order = to_LLVMAtomicOrdering(instruction->order);
56695669 LLVMBuildFence(g->builder, atomic_order, false, "");
56705670 return nullptr;
56715671}
56725672
5673static LLVMValueRef ir_render_truncate(CodeGen *g, Stage1Air *executable, IrInstGenTruncate *instruction) {
5673static LLVMValueRef ir_render_truncate(CodeGen *g, Stage1Air *executable, Stage1AirInstTruncate *instruction) {
56745674 LLVMValueRef target_val = ir_llvm_value(g, instruction->target);
56755675 ZigType *dest_type = instruction->base.value->type;
56765676 ZigType *src_type = instruction->target->value->type;
......@@ -5685,7 +5685,7 @@ static LLVMValueRef ir_render_truncate(CodeGen *g, Stage1Air *executable, IrInst
56855685 }
56865686}
56875687
5688static LLVMValueRef ir_render_memset(CodeGen *g, Stage1Air *executable, IrInstGenMemset *instruction) {
5688static LLVMValueRef ir_render_memset(CodeGen *g, Stage1Air *executable, Stage1AirInstMemset *instruction) {
56895689 LLVMValueRef dest_ptr = ir_llvm_value(g, instruction->dest_ptr);
56905690 LLVMValueRef len_val = ir_llvm_value(g, instruction->count);
56915691
......@@ -5715,7 +5715,7 @@ static LLVMValueRef ir_render_memset(CodeGen *g, Stage1Air *executable, IrInstGe
57155715 return nullptr;
57165716}
57175717
5718static LLVMValueRef ir_render_memcpy(CodeGen *g, Stage1Air *executable, IrInstGenMemcpy *instruction) {
5718static LLVMValueRef ir_render_memcpy(CodeGen *g, Stage1Air *executable, Stage1AirInstMemcpy *instruction) {
57195719 LLVMValueRef dest_ptr = ir_llvm_value(g, instruction->dest_ptr);
57205720 LLVMValueRef src_ptr = ir_llvm_value(g, instruction->src_ptr);
57215721 LLVMValueRef len_val = ir_llvm_value(g, instruction->count);
......@@ -5737,14 +5737,14 @@ static LLVMValueRef ir_render_memcpy(CodeGen *g, Stage1Air *executable, IrInstGe
57375737 return nullptr;
57385738}
57395739
5740static LLVMValueRef ir_render_wasm_memory_size(CodeGen *g, Stage1Air *executable, IrInstGenWasmMemorySize *instruction) {
5740static LLVMValueRef ir_render_wasm_memory_size(CodeGen *g, Stage1Air *executable, Stage1AirInstWasmMemorySize *instruction) {
57415741 // TODO adjust for wasm64
57425742 LLVMValueRef param = ir_llvm_value(g, instruction->index);
57435743 LLVMValueRef val = LLVMBuildCall(g->builder, gen_wasm_memory_size(g), &param, 1, "");
57445744 return val;
57455745}
57465746
5747static LLVMValueRef ir_render_wasm_memory_grow(CodeGen *g, Stage1Air *executable, IrInstGenWasmMemoryGrow *instruction) {
5747static LLVMValueRef ir_render_wasm_memory_grow(CodeGen *g, Stage1Air *executable, Stage1AirInstWasmMemoryGrow *instruction) {
57485748 // TODO adjust for wasm64
57495749 LLVMValueRef params[] = {
57505750 ir_llvm_value(g, instruction->index),
......@@ -5754,7 +5754,7 @@ static LLVMValueRef ir_render_wasm_memory_grow(CodeGen *g, Stage1Air *executable
57545754 return val;
57555755}
57565756
5757static LLVMValueRef ir_render_slice(CodeGen *g, Stage1Air *executable, IrInstGenSlice *instruction) {
5757static LLVMValueRef ir_render_slice(CodeGen *g, Stage1Air *executable, Stage1AirInstSlice *instruction) {
57585758 Error err;
57595759
57605760 LLVMValueRef array_ptr_ptr = ir_llvm_value(g, instruction->ptr);
......@@ -5991,13 +5991,13 @@ static LLVMValueRef get_trap_fn_val(CodeGen *g) {
59915991}
59925992
59935993
5994static LLVMValueRef ir_render_breakpoint(CodeGen *g, Stage1Air *executable, IrInstGenBreakpoint *instruction) {
5994static LLVMValueRef ir_render_breakpoint(CodeGen *g, Stage1Air *executable, Stage1AirInstBreakpoint *instruction) {
59955995 LLVMBuildCall(g->builder, get_trap_fn_val(g), nullptr, 0, "");
59965996 return nullptr;
59975997}
59985998
59995999static LLVMValueRef ir_render_return_address(CodeGen *g, Stage1Air *executable,
6000 IrInstGenReturnAddress *instruction)
6000 Stage1AirInstReturnAddress *instruction)
60016001{
60026002 if (target_is_wasm(g->zig_target) && g->zig_target->os != OsEmscripten) {
60036003 // I got this error from LLVM 10:
......@@ -6025,18 +6025,18 @@ static LLVMValueRef get_frame_address_fn_val(CodeGen *g) {
60256025}
60266026
60276027static LLVMValueRef ir_render_frame_address(CodeGen *g, Stage1Air *executable,
6028 IrInstGenFrameAddress *instruction)
6028 Stage1AirInstFrameAddress *instruction)
60296029{
60306030 LLVMValueRef zero = LLVMConstNull(g->builtin_types.entry_i32->llvm_type);
60316031 LLVMValueRef ptr_val = LLVMBuildCall(g->builder, get_frame_address_fn_val(g), &zero, 1, "");
60326032 return LLVMBuildPtrToInt(g->builder, ptr_val, g->builtin_types.entry_usize->llvm_type, "");
60336033}
60346034
6035static LLVMValueRef ir_render_handle(CodeGen *g, Stage1Air *executable, IrInstGenFrameHandle *instruction) {
6035static LLVMValueRef ir_render_handle(CodeGen *g, Stage1Air *executable, Stage1AirInstFrameHandle *instruction) {
60366036 return g->cur_frame_ptr;
60376037}
60386038
6039static LLVMValueRef render_shl_with_overflow(CodeGen *g, IrInstGenOverflowOp *instruction) {
6039static LLVMValueRef render_shl_with_overflow(CodeGen *g, Stage1AirInstOverflowOp *instruction) {
60406040 ZigType *int_type = instruction->result_ptr_type;
60416041 assert(int_type->id == ZigTypeIdInt);
60426042
......@@ -6061,7 +6061,7 @@ static LLVMValueRef render_shl_with_overflow(CodeGen *g, IrInstGenOverflowOp *in
60616061 return overflow_bit;
60626062}
60636063
6064static LLVMValueRef ir_render_overflow_op(CodeGen *g, Stage1Air *executable, IrInstGenOverflowOp *instruction) {
6064static LLVMValueRef ir_render_overflow_op(CodeGen *g, Stage1Air *executable, Stage1AirInstOverflowOp *instruction) {
60656065 AddSubMul add_sub_mul;
60666066 switch (instruction->op) {
60676067 case IrOverflowOpAdd:
......@@ -6099,7 +6099,7 @@ static LLVMValueRef ir_render_overflow_op(CodeGen *g, Stage1Air *executable, IrI
60996099 return overflow_bit;
61006100}
61016101
6102static LLVMValueRef ir_render_test_err(CodeGen *g, Stage1Air *executable, IrInstGenTestErr *instruction) {
6102static LLVMValueRef ir_render_test_err(CodeGen *g, Stage1Air *executable, Stage1AirInstTestErr *instruction) {
61036103 ZigType *err_union_type = instruction->err_union->value->type;
61046104 ZigType *payload_type = err_union_type->data.error_union.payload_type;
61056105 LLVMValueRef err_union_handle = ir_llvm_value(g, instruction->err_union);
......@@ -6117,7 +6117,7 @@ static LLVMValueRef ir_render_test_err(CodeGen *g, Stage1Air *executable, IrInst
61176117}
61186118
61196119static LLVMValueRef ir_render_unwrap_err_code(CodeGen *g, Stage1Air *executable,
6120 IrInstGenUnwrapErrCode *instruction)
6120 Stage1AirInstUnwrapErrCode *instruction)
61216121{
61226122 if (instruction->base.value->special != ConstValSpecialRuntime)
61236123 return nullptr;
......@@ -6137,7 +6137,7 @@ static LLVMValueRef ir_render_unwrap_err_code(CodeGen *g, Stage1Air *executable,
61376137}
61386138
61396139static LLVMValueRef ir_render_unwrap_err_payload(CodeGen *g, Stage1Air *executable,
6140 IrInstGenUnwrapErrPayload *instruction)
6140 Stage1AirInstUnwrapErrPayload *instruction)
61416141{
61426142 Error err;
61436143
......@@ -6205,7 +6205,7 @@ static LLVMValueRef ir_render_unwrap_err_payload(CodeGen *g, Stage1Air *executab
62056205 }
62066206}
62076207
6208static LLVMValueRef ir_render_optional_wrap(CodeGen *g, Stage1Air *executable, IrInstGenOptionalWrap *instruction) {
6208static LLVMValueRef ir_render_optional_wrap(CodeGen *g, Stage1Air *executable, Stage1AirInstOptionalWrap *instruction) {
62096209 ZigType *wanted_type = instruction->base.value->type;
62106210
62116211 assert(wanted_type->id == ZigTypeIdOptional);
......@@ -6241,7 +6241,7 @@ static LLVMValueRef ir_render_optional_wrap(CodeGen *g, Stage1Air *executable, I
62416241 return result_loc;
62426242}
62436243
6244static LLVMValueRef ir_render_err_wrap_code(CodeGen *g, Stage1Air *executable, IrInstGenErrWrapCode *instruction) {
6244static LLVMValueRef ir_render_err_wrap_code(CodeGen *g, Stage1Air *executable, Stage1AirInstErrWrapCode *instruction) {
62456245 ZigType *wanted_type = instruction->base.value->type;
62466246
62476247 assert(wanted_type->id == ZigTypeIdErrorUnion);
......@@ -6261,7 +6261,7 @@ static LLVMValueRef ir_render_err_wrap_code(CodeGen *g, Stage1Air *executable, I
62616261 return result_loc;
62626262}
62636263
6264static LLVMValueRef ir_render_err_wrap_payload(CodeGen *g, Stage1Air *executable, IrInstGenErrWrapPayload *instruction) {
6264static LLVMValueRef ir_render_err_wrap_payload(CodeGen *g, Stage1Air *executable, Stage1AirInstErrWrapPayload *instruction) {
62656265 ZigType *wanted_type = instruction->base.value->type;
62666266
62676267 assert(wanted_type->id == ZigTypeIdErrorUnion);
......@@ -6292,7 +6292,7 @@ static LLVMValueRef ir_render_err_wrap_payload(CodeGen *g, Stage1Air *executable
62926292 return result_loc;
62936293}
62946294
6295static LLVMValueRef ir_render_union_tag(CodeGen *g, Stage1Air *executable, IrInstGenUnionTag *instruction) {
6295static LLVMValueRef ir_render_union_tag(CodeGen *g, Stage1Air *executable, Stage1AirInstUnionTag *instruction) {
62966296 ZigType *union_type = instruction->value->value->type;
62976297
62986298 ZigType *tag_type = union_type->data.unionation.tag_type;
......@@ -6310,7 +6310,7 @@ static LLVMValueRef ir_render_union_tag(CodeGen *g, Stage1Air *executable, IrIns
63106310 return get_handle_value(g, tag_field_ptr, tag_type, ptr_type);
63116311}
63126312
6313static LLVMValueRef ir_render_panic(CodeGen *g, Stage1Air *executable, IrInstGenPanic *instruction) {
6313static LLVMValueRef ir_render_panic(CodeGen *g, Stage1Air *executable, Stage1AirInstPanic *instruction) {
63146314 bool is_llvm_alloca;
63156315 LLVMValueRef err_ret_trace_val = get_cur_err_ret_trace_val(g, instruction->base.scope, &is_llvm_alloca);
63166316 gen_panic(g, ir_llvm_value(g, instruction->msg), err_ret_trace_val, is_llvm_alloca);
......@@ -6318,7 +6318,7 @@ static LLVMValueRef ir_render_panic(CodeGen *g, Stage1Air *executable, IrInstGen
63186318}
63196319
63206320static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, Stage1Air *executable,
6321 IrInstGenAtomicRmw *instruction)
6321 Stage1AirInstAtomicRmw *instruction)
63226322{
63236323 bool is_signed;
63246324 ZigType *operand_type = instruction->operand->value->type;
......@@ -6370,7 +6370,7 @@ static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, Stage1Air *executable,
63706370}
63716371
63726372static LLVMValueRef ir_render_atomic_load(CodeGen *g, Stage1Air *executable,
6373 IrInstGenAtomicLoad *instruction)
6373 Stage1AirInstAtomicLoad *instruction)
63746374{
63756375 LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->ordering);
63766376 LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr);
......@@ -6391,7 +6391,7 @@ static LLVMValueRef ir_render_atomic_load(CodeGen *g, Stage1Air *executable,
63916391}
63926392
63936393static LLVMValueRef ir_render_atomic_store(CodeGen *g, Stage1Air *executable,
6394 IrInstGenAtomicStore *instruction)
6394 Stage1AirInstAtomicStore *instruction)
63956395{
63966396 LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->ordering);
63976397 LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr);
......@@ -6413,13 +6413,13 @@ static LLVMValueRef ir_render_atomic_store(CodeGen *g, Stage1Air *executable,
64136413 return nullptr;
64146414}
64156415
6416static LLVMValueRef ir_render_float_op(CodeGen *g, Stage1Air *executable, IrInstGenFloatOp *instruction) {
6416static LLVMValueRef ir_render_float_op(CodeGen *g, Stage1Air *executable, Stage1AirInstFloatOp *instruction) {
64176417 LLVMValueRef operand = ir_llvm_value(g, instruction->operand);
64186418 LLVMValueRef fn_val = get_float_fn(g, instruction->base.value->type, ZigLLVMFnIdFloatOp, instruction->fn_id);
64196419 return LLVMBuildCall(g->builder, fn_val, &operand, 1, "");
64206420}
64216421
6422static LLVMValueRef ir_render_mul_add(CodeGen *g, Stage1Air *executable, IrInstGenMulAdd *instruction) {
6422static LLVMValueRef ir_render_mul_add(CodeGen *g, Stage1Air *executable, Stage1AirInstMulAdd *instruction) {
64236423 LLVMValueRef op1 = ir_llvm_value(g, instruction->op1);
64246424 LLVMValueRef op2 = ir_llvm_value(g, instruction->op2);
64256425 LLVMValueRef op3 = ir_llvm_value(g, instruction->op3);
......@@ -6434,7 +6434,7 @@ static LLVMValueRef ir_render_mul_add(CodeGen *g, Stage1Air *executable, IrInstG
64346434 return LLVMBuildCall(g->builder, fn_val, args, 3, "");
64356435}
64366436
6437static LLVMValueRef ir_render_bswap(CodeGen *g, Stage1Air *executable, IrInstGenBswap *instruction) {
6437static LLVMValueRef ir_render_bswap(CodeGen *g, Stage1Air *executable, Stage1AirInstBswap *instruction) {
64386438 LLVMValueRef op = ir_llvm_value(g, instruction->op);
64396439 ZigType *expr_type = instruction->base.value->type;
64406440 bool is_vector = expr_type->id == ZigTypeIdVector;
......@@ -6469,7 +6469,7 @@ static LLVMValueRef ir_render_bswap(CodeGen *g, Stage1Air *executable, IrInstGen
64696469}
64706470
64716471static LLVMValueRef ir_render_extern(CodeGen *g, Stage1Air *executable,
6472 IrInstGenExtern *instruction)
6472 Stage1AirInstExtern *instruction)
64736473{
64746474 ZigType *expr_type = instruction->base.value->type;
64756475 assert(get_src_ptr_type(expr_type));
......@@ -6492,7 +6492,7 @@ static LLVMValueRef ir_render_extern(CodeGen *g, Stage1Air *executable,
64926492 return LLVMBuildBitCast(g->builder, global_value, get_llvm_type(g, expr_type), "");
64936493}
64946494
6495static LLVMValueRef ir_render_bit_reverse(CodeGen *g, Stage1Air *executable, IrInstGenBitReverse *instruction) {
6495static LLVMValueRef ir_render_bit_reverse(CodeGen *g, Stage1Air *executable, Stage1AirInstBitReverse *instruction) {
64966496 LLVMValueRef op = ir_llvm_value(g, instruction->op);
64976497 ZigType *int_type = instruction->base.value->type;
64986498 assert(int_type->id == ZigTypeIdInt);
......@@ -6501,7 +6501,7 @@ static LLVMValueRef ir_render_bit_reverse(CodeGen *g, Stage1Air *executable, IrI
65016501}
65026502
65036503static LLVMValueRef ir_render_vector_to_array(CodeGen *g, Stage1Air *executable,
6504 IrInstGenVectorToArray *instruction)
6504 Stage1AirInstVectorToArray *instruction)
65056505{
65066506 ZigType *array_type = instruction->base.value->type;
65076507 assert(array_type->id == ZigTypeIdArray);
......@@ -6535,7 +6535,7 @@ static LLVMValueRef ir_render_vector_to_array(CodeGen *g, Stage1Air *executable,
65356535}
65366536
65376537static LLVMValueRef ir_render_array_to_vector(CodeGen *g, Stage1Air *executable,
6538 IrInstGenArrayToVector *instruction)
6538 Stage1AirInstArrayToVector *instruction)
65396539{
65406540 ZigType *vector_type = instruction->base.value->type;
65416541 assert(vector_type->id == ZigTypeIdVector);
......@@ -6572,7 +6572,7 @@ static LLVMValueRef ir_render_array_to_vector(CodeGen *g, Stage1Air *executable,
65726572}
65736573
65746574static LLVMValueRef ir_render_assert_zero(CodeGen *g, Stage1Air *executable,
6575 IrInstGenAssertZero *instruction)
6575 Stage1AirInstAssertZero *instruction)
65766576{
65776577 LLVMValueRef target = ir_llvm_value(g, instruction->target);
65786578 ZigType *int_type = instruction->target->value->type;
......@@ -6583,7 +6583,7 @@ static LLVMValueRef ir_render_assert_zero(CodeGen *g, Stage1Air *executable,
65836583}
65846584
65856585static LLVMValueRef ir_render_assert_non_null(CodeGen *g, Stage1Air *executable,
6586 IrInstGenAssertNonNull *instruction)
6586 Stage1AirInstAssertNonNull *instruction)
65876587{
65886588 LLVMValueRef target = ir_llvm_value(g, instruction->target);
65896589 ZigType *target_type = instruction->target->value->type;
......@@ -6608,7 +6608,7 @@ static LLVMValueRef ir_render_assert_non_null(CodeGen *g, Stage1Air *executable,
66086608}
66096609
66106610static LLVMValueRef ir_render_suspend_begin(CodeGen *g, Stage1Air *executable,
6611 IrInstGenSuspendBegin *instruction)
6611 Stage1AirInstSuspendBegin *instruction)
66126612{
66136613 if (fn_is_async(g->cur_fn)) {
66146614 instruction->resume_bb = gen_suspend_begin(g, "SuspendResume");
......@@ -6617,7 +6617,7 @@ static LLVMValueRef ir_render_suspend_begin(CodeGen *g, Stage1Air *executable,
66176617}
66186618
66196619static LLVMValueRef ir_render_suspend_finish(CodeGen *g, Stage1Air *executable,
6620 IrInstGenSuspendFinish *instruction)
6620 Stage1AirInstSuspendFinish *instruction)
66216621{
66226622 LLVMBuildRetVoid(g->builder);
66236623
......@@ -6629,7 +6629,7 @@ static LLVMValueRef ir_render_suspend_finish(CodeGen *g, Stage1Air *executable,
66296629 return nullptr;
66306630}
66316631
6632static LLVMValueRef gen_await_early_return(CodeGen *g, IrInstGen *source_instr,
6632static LLVMValueRef gen_await_early_return(CodeGen *g, Stage1AirInst *source_instr,
66336633 LLVMValueRef target_frame_ptr, ZigType *result_type, ZigType *ptr_result_type,
66346634 LLVMValueRef result_loc, bool non_async)
66356635{
......@@ -6668,7 +6668,7 @@ static LLVMValueRef gen_await_early_return(CodeGen *g, IrInstGen *source_instr,
66686668 }
66696669}
66706670
6671static LLVMValueRef ir_render_await(CodeGen *g, Stage1Air *executable, IrInstGenAwait *instruction) {
6671static LLVMValueRef ir_render_await(CodeGen *g, Stage1Air *executable, Stage1AirInstAwait *instruction) {
66726672 LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type;
66736673 LLVMValueRef zero = LLVMConstNull(usize_type_ref);
66746674 LLVMValueRef target_frame_ptr = ir_llvm_value(g, instruction->frame);
......@@ -6755,7 +6755,7 @@ static LLVMValueRef ir_render_await(CodeGen *g, Stage1Air *executable, IrInstGen
67556755 return nullptr;
67566756}
67576757
6758static LLVMValueRef ir_render_resume(CodeGen *g, Stage1Air *executable, IrInstGenResume *instruction) {
6758static LLVMValueRef ir_render_resume(CodeGen *g, Stage1Air *executable, Stage1AirInstResume *instruction) {
67596759 LLVMValueRef frame = ir_llvm_value(g, instruction->frame);
67606760 ZigType *frame_type = instruction->frame->value->type;
67616761 assert(frame_type->id == ZigTypeIdAnyFrame);
......@@ -6765,14 +6765,14 @@ static LLVMValueRef ir_render_resume(CodeGen *g, Stage1Air *executable, IrInstGe
67656765}
67666766
67676767static LLVMValueRef ir_render_frame_size(CodeGen *g, Stage1Air *executable,
6768 IrInstGenFrameSize *instruction)
6768 Stage1AirInstFrameSize *instruction)
67696769{
67706770 LLVMValueRef fn_val = ir_llvm_value(g, instruction->fn);
67716771 return gen_frame_size(g, fn_val);
67726772}
67736773
67746774static LLVMValueRef ir_render_spill_begin(CodeGen *g, Stage1Air *executable,
6775 IrInstGenSpillBegin *instruction)
6775 Stage1AirInstSpillBegin *instruction)
67766776{
67776777 if (!fn_is_async(g->cur_fn))
67786778 return nullptr;
......@@ -6791,7 +6791,7 @@ static LLVMValueRef ir_render_spill_begin(CodeGen *g, Stage1Air *executable,
67916791 zig_unreachable();
67926792}
67936793
6794static LLVMValueRef ir_render_spill_end(CodeGen *g, Stage1Air *executable, IrInstGenSpillEnd *instruction) {
6794static LLVMValueRef ir_render_spill_end(CodeGen *g, Stage1Air *executable, Stage1AirInstSpillEnd *instruction) {
67956795 if (!fn_is_async(g->cur_fn))
67966796 return ir_llvm_value(g, instruction->begin->operand);
67976797
......@@ -6808,14 +6808,14 @@ static LLVMValueRef ir_render_spill_end(CodeGen *g, Stage1Air *executable, IrIns
68086808}
68096809
68106810static LLVMValueRef ir_render_vector_extract_elem(CodeGen *g, Stage1Air *executable,
6811 IrInstGenVectorExtractElem *instruction)
6811 Stage1AirInstVectorExtractElem *instruction)
68126812{
68136813 LLVMValueRef vector = ir_llvm_value(g, instruction->vector);
68146814 LLVMValueRef index = ir_llvm_value(g, instruction->index);
68156815 return LLVMBuildExtractElement(g->builder, vector, index, "");
68166816}
68176817
6818static void set_debug_location(CodeGen *g, IrInstGen *instruction) {
6818static void set_debug_location(CodeGen *g, Stage1AirInst *instruction) {
68196819 AstNode *source_node = instruction->source_node;
68206820 Scope *scope = instruction->scope;
68216821
......@@ -6826,187 +6826,187 @@ static void set_debug_location(CodeGen *g, IrInstGen *instruction) {
68266826 node_column_onebased(source_node), get_di_scope(g, scope));
68276827}
68286828
6829static LLVMValueRef ir_render_instruction(CodeGen *g, Stage1Air *executable, IrInstGen *instruction) {
6829static LLVMValueRef ir_render_instruction(CodeGen *g, Stage1Air *executable, Stage1AirInst *instruction) {
68306830 switch (instruction->id) {
6831 case IrInstGenIdInvalid:
6832 case IrInstGenIdConst:
6833 case IrInstGenIdAlloca:
6831 case Stage1AirInstIdInvalid:
6832 case Stage1AirInstIdConst:
6833 case Stage1AirInstIdAlloca:
68346834 zig_unreachable();
68356835
6836 case IrInstGenIdDeclVar:
6837 return ir_render_decl_var(g, executable, (IrInstGenDeclVar *)instruction);
6838 case IrInstGenIdReturn:
6839 return ir_render_return(g, executable, (IrInstGenReturn *)instruction);
6840 case IrInstGenIdBinOp:
6841 return ir_render_bin_op(g, executable, (IrInstGenBinOp *)instruction);
6842 case IrInstGenIdCast:
6843 return ir_render_cast(g, executable, (IrInstGenCast *)instruction);
6844 case IrInstGenIdUnreachable:
6845 return ir_render_unreachable(g, executable, (IrInstGenUnreachable *)instruction);
6846 case IrInstGenIdCondBr:
6847 return ir_render_cond_br(g, executable, (IrInstGenCondBr *)instruction);
6848 case IrInstGenIdBr:
6849 return ir_render_br(g, executable, (IrInstGenBr *)instruction);
6850 case IrInstGenIdBinaryNot:
6851 return ir_render_binary_not(g, executable, (IrInstGenBinaryNot *)instruction);
6852 case IrInstGenIdNegation:
6853 return ir_render_negation(g, executable, (IrInstGenNegation *)instruction);
6854 case IrInstGenIdLoadPtr:
6855 return ir_render_load_ptr(g, executable, (IrInstGenLoadPtr *)instruction);
6856 case IrInstGenIdStorePtr:
6857 return ir_render_store_ptr(g, executable, (IrInstGenStorePtr *)instruction);
6858 case IrInstGenIdVectorStoreElem:
6859 return ir_render_vector_store_elem(g, executable, (IrInstGenVectorStoreElem *)instruction);
6860 case IrInstGenIdVarPtr:
6861 return ir_render_var_ptr(g, executable, (IrInstGenVarPtr *)instruction);
6862 case IrInstGenIdReturnPtr:
6863 return ir_render_return_ptr(g, executable, (IrInstGenReturnPtr *)instruction);
6864 case IrInstGenIdElemPtr:
6865 return ir_render_elem_ptr(g, executable, (IrInstGenElemPtr *)instruction);
6866 case IrInstGenIdCall:
6867 return ir_render_call(g, executable, (IrInstGenCall *)instruction);
6868 case IrInstGenIdStructFieldPtr:
6869 return ir_render_struct_field_ptr(g, executable, (IrInstGenStructFieldPtr *)instruction);
6870 case IrInstGenIdUnionFieldPtr:
6871 return ir_render_union_field_ptr(g, executable, (IrInstGenUnionFieldPtr *)instruction);
6872 case IrInstGenIdAsm:
6873 return ir_render_asm_gen(g, executable, (IrInstGenAsm *)instruction);
6874 case IrInstGenIdTestNonNull:
6875 return ir_render_test_non_null(g, executable, (IrInstGenTestNonNull *)instruction);
6876 case IrInstGenIdOptionalUnwrapPtr:
6877 return ir_render_optional_unwrap_ptr(g, executable, (IrInstGenOptionalUnwrapPtr *)instruction);
6878 case IrInstGenIdClz:
6879 return ir_render_clz(g, executable, (IrInstGenClz *)instruction);
6880 case IrInstGenIdCtz:
6881 return ir_render_ctz(g, executable, (IrInstGenCtz *)instruction);
6882 case IrInstGenIdPopCount:
6883 return ir_render_pop_count(g, executable, (IrInstGenPopCount *)instruction);
6884 case IrInstGenIdSwitchBr:
6885 return ir_render_switch_br(g, executable, (IrInstGenSwitchBr *)instruction);
6886 case IrInstGenIdBswap:
6887 return ir_render_bswap(g, executable, (IrInstGenBswap *)instruction);
6888 case IrInstGenIdBitReverse:
6889 return ir_render_bit_reverse(g, executable, (IrInstGenBitReverse *)instruction);
6890 case IrInstGenIdPhi:
6891 return ir_render_phi(g, executable, (IrInstGenPhi *)instruction);
6892 case IrInstGenIdRef:
6893 return ir_render_ref(g, executable, (IrInstGenRef *)instruction);
6894 case IrInstGenIdErrName:
6895 return ir_render_err_name(g, executable, (IrInstGenErrName *)instruction);
6896 case IrInstGenIdCmpxchg:
6897 return ir_render_cmpxchg(g, executable, (IrInstGenCmpxchg *)instruction);
6898 case IrInstGenIdFence:
6899 return ir_render_fence(g, executable, (IrInstGenFence *)instruction);
6900 case IrInstGenIdReduce:
6901 return ir_render_reduce(g, executable, (IrInstGenReduce *)instruction);
6902 case IrInstGenIdTruncate:
6903 return ir_render_truncate(g, executable, (IrInstGenTruncate *)instruction);
6904 case IrInstGenIdBoolNot:
6905 return ir_render_bool_not(g, executable, (IrInstGenBoolNot *)instruction);
6906 case IrInstGenIdMemset:
6907 return ir_render_memset(g, executable, (IrInstGenMemset *)instruction);
6908 case IrInstGenIdMemcpy:
6909 return ir_render_memcpy(g, executable, (IrInstGenMemcpy *)instruction);
6910 case IrInstGenIdSlice:
6911 return ir_render_slice(g, executable, (IrInstGenSlice *)instruction);
6912 case IrInstGenIdBreakpoint:
6913 return ir_render_breakpoint(g, executable, (IrInstGenBreakpoint *)instruction);
6914 case IrInstGenIdReturnAddress:
6915 return ir_render_return_address(g, executable, (IrInstGenReturnAddress *)instruction);
6916 case IrInstGenIdFrameAddress:
6917 return ir_render_frame_address(g, executable, (IrInstGenFrameAddress *)instruction);
6918 case IrInstGenIdFrameHandle:
6919 return ir_render_handle(g, executable, (IrInstGenFrameHandle *)instruction);
6920 case IrInstGenIdOverflowOp:
6921 return ir_render_overflow_op(g, executable, (IrInstGenOverflowOp *)instruction);
6922 case IrInstGenIdTestErr:
6923 return ir_render_test_err(g, executable, (IrInstGenTestErr *)instruction);
6924 case IrInstGenIdUnwrapErrCode:
6925 return ir_render_unwrap_err_code(g, executable, (IrInstGenUnwrapErrCode *)instruction);
6926 case IrInstGenIdUnwrapErrPayload:
6927 return ir_render_unwrap_err_payload(g, executable, (IrInstGenUnwrapErrPayload *)instruction);
6928 case IrInstGenIdOptionalWrap:
6929 return ir_render_optional_wrap(g, executable, (IrInstGenOptionalWrap *)instruction);
6930 case IrInstGenIdErrWrapCode:
6931 return ir_render_err_wrap_code(g, executable, (IrInstGenErrWrapCode *)instruction);
6932 case IrInstGenIdErrWrapPayload:
6933 return ir_render_err_wrap_payload(g, executable, (IrInstGenErrWrapPayload *)instruction);
6934 case IrInstGenIdUnionTag:
6935 return ir_render_union_tag(g, executable, (IrInstGenUnionTag *)instruction);
6936 case IrInstGenIdPtrCast:
6937 return ir_render_ptr_cast(g, executable, (IrInstGenPtrCast *)instruction);
6938 case IrInstGenIdBitCast:
6939 return ir_render_bit_cast(g, executable, (IrInstGenBitCast *)instruction);
6940 case IrInstGenIdWidenOrShorten:
6941 return ir_render_widen_or_shorten(g, executable, (IrInstGenWidenOrShorten *)instruction);
6942 case IrInstGenIdPtrToInt:
6943 return ir_render_ptr_to_int(g, executable, (IrInstGenPtrToInt *)instruction);
6944 case IrInstGenIdIntToPtr:
6945 return ir_render_int_to_ptr(g, executable, (IrInstGenIntToPtr *)instruction);
6946 case IrInstGenIdIntToEnum:
6947 return ir_render_int_to_enum(g, executable, (IrInstGenIntToEnum *)instruction);
6948 case IrInstGenIdIntToErr:
6949 return ir_render_int_to_err(g, executable, (IrInstGenIntToErr *)instruction);
6950 case IrInstGenIdErrToInt:
6951 return ir_render_err_to_int(g, executable, (IrInstGenErrToInt *)instruction);
6952 case IrInstGenIdPanic:
6953 return ir_render_panic(g, executable, (IrInstGenPanic *)instruction);
6954 case IrInstGenIdTagName:
6955 return ir_render_enum_tag_name(g, executable, (IrInstGenTagName *)instruction);
6956 case IrInstGenIdFieldParentPtr:
6957 return ir_render_field_parent_ptr(g, executable, (IrInstGenFieldParentPtr *)instruction);
6958 case IrInstGenIdAlignCast:
6959 return ir_render_align_cast(g, executable, (IrInstGenAlignCast *)instruction);
6960 case IrInstGenIdErrorReturnTrace:
6961 return ir_render_error_return_trace(g, executable, (IrInstGenErrorReturnTrace *)instruction);
6962 case IrInstGenIdAtomicRmw:
6963 return ir_render_atomic_rmw(g, executable, (IrInstGenAtomicRmw *)instruction);
6964 case IrInstGenIdAtomicLoad:
6965 return ir_render_atomic_load(g, executable, (IrInstGenAtomicLoad *)instruction);
6966 case IrInstGenIdAtomicStore:
6967 return ir_render_atomic_store(g, executable, (IrInstGenAtomicStore *)instruction);
6968 case IrInstGenIdSaveErrRetAddr:
6969 return ir_render_save_err_ret_addr(g, executable, (IrInstGenSaveErrRetAddr *)instruction);
6970 case IrInstGenIdFloatOp:
6971 return ir_render_float_op(g, executable, (IrInstGenFloatOp *)instruction);
6972 case IrInstGenIdMulAdd:
6973 return ir_render_mul_add(g, executable, (IrInstGenMulAdd *)instruction);
6974 case IrInstGenIdArrayToVector:
6975 return ir_render_array_to_vector(g, executable, (IrInstGenArrayToVector *)instruction);
6976 case IrInstGenIdVectorToArray:
6977 return ir_render_vector_to_array(g, executable, (IrInstGenVectorToArray *)instruction);
6978 case IrInstGenIdAssertZero:
6979 return ir_render_assert_zero(g, executable, (IrInstGenAssertZero *)instruction);
6980 case IrInstGenIdAssertNonNull:
6981 return ir_render_assert_non_null(g, executable, (IrInstGenAssertNonNull *)instruction);
6982 case IrInstGenIdPtrOfArrayToSlice:
6983 return ir_render_ptr_of_array_to_slice(g, executable, (IrInstGenPtrOfArrayToSlice *)instruction);
6984 case IrInstGenIdSuspendBegin:
6985 return ir_render_suspend_begin(g, executable, (IrInstGenSuspendBegin *)instruction);
6986 case IrInstGenIdSuspendFinish:
6987 return ir_render_suspend_finish(g, executable, (IrInstGenSuspendFinish *)instruction);
6988 case IrInstGenIdResume:
6989 return ir_render_resume(g, executable, (IrInstGenResume *)instruction);
6990 case IrInstGenIdFrameSize:
6991 return ir_render_frame_size(g, executable, (IrInstGenFrameSize *)instruction);
6992 case IrInstGenIdAwait:
6993 return ir_render_await(g, executable, (IrInstGenAwait *)instruction);
6994 case IrInstGenIdSpillBegin:
6995 return ir_render_spill_begin(g, executable, (IrInstGenSpillBegin *)instruction);
6996 case IrInstGenIdSpillEnd:
6997 return ir_render_spill_end(g, executable, (IrInstGenSpillEnd *)instruction);
6998 case IrInstGenIdShuffleVector:
6999 return ir_render_shuffle_vector(g, executable, (IrInstGenShuffleVector *) instruction);
7000 case IrInstGenIdSplat:
7001 return ir_render_splat(g, executable, (IrInstGenSplat *) instruction);
7002 case IrInstGenIdVectorExtractElem:
7003 return ir_render_vector_extract_elem(g, executable, (IrInstGenVectorExtractElem *) instruction);
7004 case IrInstGenIdWasmMemorySize:
7005 return ir_render_wasm_memory_size(g, executable, (IrInstGenWasmMemorySize *) instruction);
7006 case IrInstGenIdWasmMemoryGrow:
7007 return ir_render_wasm_memory_grow(g, executable, (IrInstGenWasmMemoryGrow *) instruction);
7008 case IrInstGenIdExtern:
7009 return ir_render_extern(g, executable, (IrInstGenExtern *) instruction);
6836 case Stage1AirInstIdDeclVar:
6837 return ir_render_decl_var(g, executable, (Stage1AirInstDeclVar *)instruction);
6838 case Stage1AirInstIdReturn:
6839 return ir_render_return(g, executable, (Stage1AirInstReturn *)instruction);
6840 case Stage1AirInstIdBinOp:
6841 return ir_render_bin_op(g, executable, (Stage1AirInstBinOp *)instruction);
6842 case Stage1AirInstIdCast:
6843 return ir_render_cast(g, executable, (Stage1AirInstCast *)instruction);
6844 case Stage1AirInstIdUnreachable:
6845 return ir_render_unreachable(g, executable, (Stage1AirInstUnreachable *)instruction);
6846 case Stage1AirInstIdCondBr:
6847 return ir_render_cond_br(g, executable, (Stage1AirInstCondBr *)instruction);
6848 case Stage1AirInstIdBr:
6849 return ir_render_br(g, executable, (Stage1AirInstBr *)instruction);
6850 case Stage1AirInstIdBinaryNot:
6851 return ir_render_binary_not(g, executable, (Stage1AirInstBinaryNot *)instruction);
6852 case Stage1AirInstIdNegation:
6853 return ir_render_negation(g, executable, (Stage1AirInstNegation *)instruction);
6854 case Stage1AirInstIdLoadPtr:
6855 return ir_render_load_ptr(g, executable, (Stage1AirInstLoadPtr *)instruction);
6856 case Stage1AirInstIdStorePtr:
6857 return ir_render_store_ptr(g, executable, (Stage1AirInstStorePtr *)instruction);
6858 case Stage1AirInstIdVectorStoreElem:
6859 return ir_render_vector_store_elem(g, executable, (Stage1AirInstVectorStoreElem *)instruction);
6860 case Stage1AirInstIdVarPtr:
6861 return ir_render_var_ptr(g, executable, (Stage1AirInstVarPtr *)instruction);
6862 case Stage1AirInstIdReturnPtr:
6863 return ir_render_return_ptr(g, executable, (Stage1AirInstReturnPtr *)instruction);
6864 case Stage1AirInstIdElemPtr:
6865 return ir_render_elem_ptr(g, executable, (Stage1AirInstElemPtr *)instruction);
6866 case Stage1AirInstIdCall:
6867 return ir_render_call(g, executable, (Stage1AirInstCall *)instruction);
6868 case Stage1AirInstIdStructFieldPtr:
6869 return ir_render_struct_field_ptr(g, executable, (Stage1AirInstStructFieldPtr *)instruction);
6870 case Stage1AirInstIdUnionFieldPtr:
6871 return ir_render_union_field_ptr(g, executable, (Stage1AirInstUnionFieldPtr *)instruction);
6872 case Stage1AirInstIdAsm:
6873 return ir_render_asm_gen(g, executable, (Stage1AirInstAsm *)instruction);
6874 case Stage1AirInstIdTestNonNull:
6875 return ir_render_test_non_null(g, executable, (Stage1AirInstTestNonNull *)instruction);
6876 case Stage1AirInstIdOptionalUnwrapPtr:
6877 return ir_render_optional_unwrap_ptr(g, executable, (Stage1AirInstOptionalUnwrapPtr *)instruction);
6878 case Stage1AirInstIdClz:
6879 return ir_render_clz(g, executable, (Stage1AirInstClz *)instruction);
6880 case Stage1AirInstIdCtz:
6881 return ir_render_ctz(g, executable, (Stage1AirInstCtz *)instruction);
6882 case Stage1AirInstIdPopCount:
6883 return ir_render_pop_count(g, executable, (Stage1AirInstPopCount *)instruction);
6884 case Stage1AirInstIdSwitchBr:
6885 return ir_render_switch_br(g, executable, (Stage1AirInstSwitchBr *)instruction);
6886 case Stage1AirInstIdBswap:
6887 return ir_render_bswap(g, executable, (Stage1AirInstBswap *)instruction);
6888 case Stage1AirInstIdBitReverse:
6889 return ir_render_bit_reverse(g, executable, (Stage1AirInstBitReverse *)instruction);
6890 case Stage1AirInstIdPhi:
6891 return ir_render_phi(g, executable, (Stage1AirInstPhi *)instruction);
6892 case Stage1AirInstIdRef:
6893 return ir_render_ref(g, executable, (Stage1AirInstRef *)instruction);
6894 case Stage1AirInstIdErrName:
6895 return ir_render_err_name(g, executable, (Stage1AirInstErrName *)instruction);
6896 case Stage1AirInstIdCmpxchg:
6897 return ir_render_cmpxchg(g, executable, (Stage1AirInstCmpxchg *)instruction);
6898 case Stage1AirInstIdFence:
6899 return ir_render_fence(g, executable, (Stage1AirInstFence *)instruction);
6900 case Stage1AirInstIdReduce:
6901 return ir_render_reduce(g, executable, (Stage1AirInstReduce *)instruction);
6902 case Stage1AirInstIdTruncate:
6903 return ir_render_truncate(g, executable, (Stage1AirInstTruncate *)instruction);
6904 case Stage1AirInstIdBoolNot:
6905 return ir_render_bool_not(g, executable, (Stage1AirInstBoolNot *)instruction);
6906 case Stage1AirInstIdMemset:
6907 return ir_render_memset(g, executable, (Stage1AirInstMemset *)instruction);
6908 case Stage1AirInstIdMemcpy:
6909 return ir_render_memcpy(g, executable, (Stage1AirInstMemcpy *)instruction);
6910 case Stage1AirInstIdSlice:
6911 return ir_render_slice(g, executable, (Stage1AirInstSlice *)instruction);
6912 case Stage1AirInstIdBreakpoint:
6913 return ir_render_breakpoint(g, executable, (Stage1AirInstBreakpoint *)instruction);
6914 case Stage1AirInstIdReturnAddress:
6915 return ir_render_return_address(g, executable, (Stage1AirInstReturnAddress *)instruction);
6916 case Stage1AirInstIdFrameAddress:
6917 return ir_render_frame_address(g, executable, (Stage1AirInstFrameAddress *)instruction);
6918 case Stage1AirInstIdFrameHandle:
6919 return ir_render_handle(g, executable, (Stage1AirInstFrameHandle *)instruction);
6920 case Stage1AirInstIdOverflowOp:
6921 return ir_render_overflow_op(g, executable, (Stage1AirInstOverflowOp *)instruction);
6922 case Stage1AirInstIdTestErr:
6923 return ir_render_test_err(g, executable, (Stage1AirInstTestErr *)instruction);
6924 case Stage1AirInstIdUnwrapErrCode:
6925 return ir_render_unwrap_err_code(g, executable, (Stage1AirInstUnwrapErrCode *)instruction);
6926 case Stage1AirInstIdUnwrapErrPayload:
6927 return ir_render_unwrap_err_payload(g, executable, (Stage1AirInstUnwrapErrPayload *)instruction);
6928 case Stage1AirInstIdOptionalWrap:
6929 return ir_render_optional_wrap(g, executable, (Stage1AirInstOptionalWrap *)instruction);
6930 case Stage1AirInstIdErrWrapCode:
6931 return ir_render_err_wrap_code(g, executable, (Stage1AirInstErrWrapCode *)instruction);
6932 case Stage1AirInstIdErrWrapPayload:
6933 return ir_render_err_wrap_payload(g, executable, (Stage1AirInstErrWrapPayload *)instruction);
6934 case Stage1AirInstIdUnionTag:
6935 return ir_render_union_tag(g, executable, (Stage1AirInstUnionTag *)instruction);
6936 case Stage1AirInstIdPtrCast:
6937 return ir_render_ptr_cast(g, executable, (Stage1AirInstPtrCast *)instruction);
6938 case Stage1AirInstIdBitCast:
6939 return ir_render_bit_cast(g, executable, (Stage1AirInstBitCast *)instruction);
6940 case Stage1AirInstIdWidenOrShorten:
6941 return ir_render_widen_or_shorten(g, executable, (Stage1AirInstWidenOrShorten *)instruction);
6942 case Stage1AirInstIdPtrToInt:
6943 return ir_render_ptr_to_int(g, executable, (Stage1AirInstPtrToInt *)instruction);
6944 case Stage1AirInstIdIntToPtr:
6945 return ir_render_int_to_ptr(g, executable, (Stage1AirInstIntToPtr *)instruction);
6946 case Stage1AirInstIdIntToEnum:
6947 return ir_render_int_to_enum(g, executable, (Stage1AirInstIntToEnum *)instruction);
6948 case Stage1AirInstIdIntToErr:
6949 return ir_render_int_to_err(g, executable, (Stage1AirInstIntToErr *)instruction);
6950 case Stage1AirInstIdErrToInt:
6951 return ir_render_err_to_int(g, executable, (Stage1AirInstErrToInt *)instruction);
6952 case Stage1AirInstIdPanic:
6953 return ir_render_panic(g, executable, (Stage1AirInstPanic *)instruction);
6954 case Stage1AirInstIdTagName:
6955 return ir_render_enum_tag_name(g, executable, (Stage1AirInstTagName *)instruction);
6956 case Stage1AirInstIdFieldParentPtr:
6957 return ir_render_field_parent_ptr(g, executable, (Stage1AirInstFieldParentPtr *)instruction);
6958 case Stage1AirInstIdAlignCast:
6959 return ir_render_align_cast(g, executable, (Stage1AirInstAlignCast *)instruction);
6960 case Stage1AirInstIdErrorReturnTrace:
6961 return ir_render_error_return_trace(g, executable, (Stage1AirInstErrorReturnTrace *)instruction);
6962 case Stage1AirInstIdAtomicRmw:
6963 return ir_render_atomic_rmw(g, executable, (Stage1AirInstAtomicRmw *)instruction);
6964 case Stage1AirInstIdAtomicLoad:
6965 return ir_render_atomic_load(g, executable, (Stage1AirInstAtomicLoad *)instruction);
6966 case Stage1AirInstIdAtomicStore:
6967 return ir_render_atomic_store(g, executable, (Stage1AirInstAtomicStore *)instruction);
6968 case Stage1AirInstIdSaveErrRetAddr:
6969 return ir_render_save_err_ret_addr(g, executable, (Stage1AirInstSaveErrRetAddr *)instruction);
6970 case Stage1AirInstIdFloatOp:
6971 return ir_render_float_op(g, executable, (Stage1AirInstFloatOp *)instruction);
6972 case Stage1AirInstIdMulAdd:
6973 return ir_render_mul_add(g, executable, (Stage1AirInstMulAdd *)instruction);
6974 case Stage1AirInstIdArrayToVector:
6975 return ir_render_array_to_vector(g, executable, (Stage1AirInstArrayToVector *)instruction);
6976 case Stage1AirInstIdVectorToArray:
6977 return ir_render_vector_to_array(g, executable, (Stage1AirInstVectorToArray *)instruction);
6978 case Stage1AirInstIdAssertZero:
6979 return ir_render_assert_zero(g, executable, (Stage1AirInstAssertZero *)instruction);
6980 case Stage1AirInstIdAssertNonNull:
6981 return ir_render_assert_non_null(g, executable, (Stage1AirInstAssertNonNull *)instruction);
6982 case Stage1AirInstIdPtrOfArrayToSlice:
6983 return ir_render_ptr_of_array_to_slice(g, executable, (Stage1AirInstPtrOfArrayToSlice *)instruction);
6984 case Stage1AirInstIdSuspendBegin:
6985 return ir_render_suspend_begin(g, executable, (Stage1AirInstSuspendBegin *)instruction);
6986 case Stage1AirInstIdSuspendFinish:
6987 return ir_render_suspend_finish(g, executable, (Stage1AirInstSuspendFinish *)instruction);
6988 case Stage1AirInstIdResume:
6989 return ir_render_resume(g, executable, (Stage1AirInstResume *)instruction);
6990 case Stage1AirInstIdFrameSize:
6991 return ir_render_frame_size(g, executable, (Stage1AirInstFrameSize *)instruction);
6992 case Stage1AirInstIdAwait:
6993 return ir_render_await(g, executable, (Stage1AirInstAwait *)instruction);
6994 case Stage1AirInstIdSpillBegin:
6995 return ir_render_spill_begin(g, executable, (Stage1AirInstSpillBegin *)instruction);
6996 case Stage1AirInstIdSpillEnd:
6997 return ir_render_spill_end(g, executable, (Stage1AirInstSpillEnd *)instruction);
6998 case Stage1AirInstIdShuffleVector:
6999 return ir_render_shuffle_vector(g, executable, (Stage1AirInstShuffleVector *) instruction);
7000 case Stage1AirInstIdSplat:
7001 return ir_render_splat(g, executable, (Stage1AirInstSplat *) instruction);
7002 case Stage1AirInstIdVectorExtractElem:
7003 return ir_render_vector_extract_elem(g, executable, (Stage1AirInstVectorExtractElem *) instruction);
7004 case Stage1AirInstIdWasmMemorySize:
7005 return ir_render_wasm_memory_size(g, executable, (Stage1AirInstWasmMemorySize *) instruction);
7006 case Stage1AirInstIdWasmMemoryGrow:
7007 return ir_render_wasm_memory_grow(g, executable, (Stage1AirInstWasmMemoryGrow *) instruction);
7008 case Stage1AirInstIdExtern:
7009 return ir_render_extern(g, executable, (Stage1AirInstExtern *) instruction);
70107010 }
70117011 zig_unreachable();
70127012}
......@@ -7018,14 +7018,14 @@ static void ir_render(CodeGen *g, ZigFn *fn_entry) {
70187018 assert(executable->basic_block_list.length > 0);
70197019
70207020 for (size_t block_i = 0; block_i < executable->basic_block_list.length; block_i += 1) {
7021 IrBasicBlockGen *current_block = executable->basic_block_list.at(block_i);
7021 Stage1AirBasicBlock *current_block = executable->basic_block_list.at(block_i);
70227022 if (get_scope_typeof(current_block->scope) != nullptr) {
70237023 LLVMBuildBr(g->builder, current_block->llvm_block);
70247024 }
70257025 assert(current_block->llvm_block);
70267026 LLVMPositionBuilderAtEnd(g->builder, current_block->llvm_block);
70277027 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {
7028 IrInstGen *instruction = current_block->instruction_list.at(instr_i);
7028 Stage1AirInst *instruction = current_block->instruction_list.at(instr_i);
70297029 if (instruction->ref_count == 0 && !ir_inst_gen_has_side_effects(instruction))
70307030 continue;
70317031 if (get_scope_typeof(instruction->scope) != nullptr)
......@@ -8021,7 +8021,7 @@ static void build_all_basic_blocks(CodeGen *g, ZigFn *fn) {
80218021 g->cur_preamble_llvm_block = first_bb;
80228022 }
80238023 for (size_t block_i = 0; block_i < executable->basic_block_list.length; block_i += 1) {
8024 IrBasicBlockGen *bb = executable->basic_block_list.at(block_i);
8024 Stage1AirBasicBlock *bb = executable->basic_block_list.at(block_i);
80258025 bb->llvm_block = LLVMAppendBasicBlock(fn_val, bb->name_hint);
80268026 }
80278027 if (first_bb == nullptr) {
......@@ -8243,10 +8243,10 @@ static void do_code_gen(CodeGen *g) {
82438243 if (!is_async) {
82448244 // allocate async frames for nosuspend calls & awaits to async functions
82458245 ZigType *largest_call_frame_type = nullptr;
8246 IrInstGen *all_calls_alloca = ir_create_alloca(g, &fn_table_entry->fndef_scope->base,
8246 Stage1AirInst *all_calls_alloca = ir_create_alloca(g, &fn_table_entry->fndef_scope->base,
82478247 fn_table_entry->body_node, fn_table_entry, g->builtin_types.entry_void, "@async_call_frame");
82488248 for (size_t i = 0; i < fn_table_entry->call_list.length; i += 1) {
8249 IrInstGenCall *call = fn_table_entry->call_list.at(i);
8249 Stage1AirInstCall *call = fn_table_entry->call_list.at(i);
82508250 if (call->fn_entry == nullptr)
82518251 continue;
82528252 if (!fn_is_async(call->fn_entry))
......@@ -8268,7 +8268,7 @@ static void do_code_gen(CodeGen *g) {
82688268 }
82698269 // allocate temporary stack data
82708270 for (size_t alloca_i = 0; alloca_i < fn_table_entry->alloca_gen_list.length; alloca_i += 1) {
8271 IrInstGenAlloca *instruction = fn_table_entry->alloca_gen_list.at(alloca_i);
8271 Stage1AirInstAlloca *instruction = fn_table_entry->alloca_gen_list.at(alloca_i);
82728272 ZigType *ptr_type = instruction->base.value->type;
82738273 assert(ptr_type->id == ZigTypeIdPointer);
82748274 ZigType *child_type = ptr_type->data.pointer.child_type;
......@@ -8422,7 +8422,7 @@ static void do_code_gen(CodeGen *g) {
84228422 g->cur_async_switch_instr = switch_instr;
84238423
84248424 LLVMValueRef zero = LLVMConstNull(usize_type_ref);
8425 IrBasicBlockGen *entry_block = executable->basic_block_list.at(0);
8425 Stage1AirBasicBlock *entry_block = executable->basic_block_list.at(0);
84268426 LLVMAddCase(switch_instr, zero, entry_block->llvm_block);
84278427 g->cur_resume_block_count += 1;
84288428
......@@ -9379,7 +9379,7 @@ static void init(CodeGen *g) {
93799379 define_builtin_types(g);
93809380 define_intern_values(g);
93819381
9382 IrInstGen *sentinel_instructions = heap::c_allocator.allocate<IrInstGen>(2);
9382 Stage1AirInst *sentinel_instructions = heap::c_allocator.allocate<Stage1AirInst>(2);
93839383 g->invalid_inst_gen = &sentinel_instructions[0];
93849384 g->invalid_inst_gen->value = g->pass1_arena->create<ZigValue>();
93859385 g->invalid_inst_gen->value->type = g->builtin_types.entry_invalid;
......@@ -9388,7 +9388,7 @@ static void init(CodeGen *g) {
93889388 g->unreach_instruction->value = g->pass1_arena->create<ZigValue>();
93899389 g->unreach_instruction->value->type = g->builtin_types.entry_unreachable;
93909390
9391 g->invalid_inst_src = heap::c_allocator.create<IrInstSrc>();
9391 g->invalid_inst_src = heap::c_allocator.create<Stage1ZirInst>();
93929392
93939393 define_builtin_fns(g);
93949394 Error err;
src/stage1/ir.cpp+2246-2246
......@@ -25,10 +25,10 @@
2525struct IrBuilderGen {
2626 CodeGen *codegen;
2727 Stage1Air *exec;
28 IrBasicBlockGen *current_basic_block;
28 Stage1AirBasicBlock *current_basic_block;
2929
3030 // track for immediate post-analysis destruction
31 mem::List<IrInstGenConst *> constants;
31 mem::List<Stage1AirInstConst *> constants;
3232};
3333
3434struct IrAnalyze {
......@@ -40,17 +40,17 @@ struct IrAnalyze {
4040 size_t instruction_index;
4141 ZigType *explicit_return_type;
4242 AstNode *explicit_return_type_source_node;
43 ZigList<IrInstGen *> src_implicit_return_type_list;
43 ZigList<Stage1AirInst *> src_implicit_return_type_list;
4444 ZigList<IrSuspendPosition> resume_stack;
4545 Stage1ZirBasicBlock *const_predecessor_bb;
4646 size_t ref_count;
4747 size_t break_debug_id; // for debugging purposes
48 IrInstGen *return_ptr;
48 Stage1AirInst *return_ptr;
4949 Stage1Air *parent_exec;
5050 size_t *backward_branch_count;
5151 size_t *backward_branch_quota;
5252 ZigFn *fn;
53 IrInstSrc *suspend_source_instr;
53 Stage1ZirInst *suspend_source_instr;
5454
5555 // For the purpose of using in a debugger
5656 void dump();
......@@ -216,16 +216,16 @@ struct DbgIrBreakPoint {
216216 uint32_t line;
217217};
218218
219static IrInstGen *ir_implicit_cast(IrAnalyze *ira, IrInstGen *value, ZigType *expected_type);
220static IrInstGen *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node,
221 IrInstGen *value, ZigType *expected_type);
222static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *ptr,
219static Stage1AirInst *ir_implicit_cast(IrAnalyze *ira, Stage1AirInst *value, ZigType *expected_type);
220static Stage1AirInst *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node,
221 Stage1AirInst *value, ZigType *expected_type);
222static Stage1AirInst *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *ptr,
223223 ResultLoc *result_loc);
224static IrInstGen *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name,
225 Scope *scope, AstNode *source_node, IrInstGen *container_ptr, AstNode *container_ptr_src,
224static Stage1AirInst *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name,
225 Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, AstNode *container_ptr_src,
226226 ZigType *container_type, bool initializing);
227static IrInstGen *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var);
228static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstGen *op);
227static Stage1AirInst *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var);
228static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, Stage1AirInst *op);
229229static ZigType *adjust_ptr_align(CodeGen *g, ZigType *ptr_type, uint32_t new_align);
230230static ZigType *adjust_ptr_const(CodeGen *g, ZigType *ptr_type, bool is_const);
231231static ZigType *adjust_slice_align(CodeGen *g, ZigType *slice_type, uint32_t new_align);
......@@ -233,40 +233,40 @@ static Error buf_read_value_bytes(IrAnalyze *ira, CodeGen *codegen, AstNode *sou
233233static void buf_write_value_bytes(CodeGen *codegen, uint8_t *buf, ZigValue *val);
234234static Error ir_read_const_ptr(IrAnalyze *ira, CodeGen *codegen, AstNode *source_node,
235235 ZigValue *out_val, ZigValue *ptr_val);
236static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
237 IrInstGen *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src,
236static Stage1AirInst *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
237 Stage1AirInst *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src,
238238 bool safety_check_on, bool keep_bigger_alignment);
239static ZigValue *ir_resolve_const(IrAnalyze *ira, IrInstGen *value, UndefAllowed undef_allowed);
239static ZigValue *ir_resolve_const(IrAnalyze *ira, Stage1AirInst *value, UndefAllowed undef_allowed);
240240static Error resolve_ptr_align(IrAnalyze *ira, ZigType *ty, uint32_t *result_align);
241static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,
241static Stage1AirInst *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
242242 ZigType *ptr_type);
243static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,
243static Stage1AirInst *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
244244 ZigType *dest_type);
245static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_source_instr,
246 ResultLoc *result_loc, ZigType *value_type, IrInstGen *value, bool force_runtime, bool allow_discard);
247static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_instr,
248 ResultLoc *result_loc, ZigType *value_type, IrInstGen *value, bool force_runtime, bool allow_discard);
249static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
250 IrInstGen *base_ptr, bool safety_check_on, bool initializing);
251static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
252 IrInstGen *base_ptr, bool safety_check_on, bool initializing);
253static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,
254 IrInstGen *base_ptr, bool initializing);
255static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
256 IrInstGen *ptr, IrInstGen *uncasted_value, bool allow_write_through_const);
245static Stage1AirInst *ir_resolve_result_raw(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr,
246 ResultLoc *result_loc, ZigType *value_type, Stage1AirInst *value, bool force_runtime, bool allow_discard);
247static Stage1AirInst *ir_resolve_result(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr,
248 ResultLoc *result_loc, ZigType *value_type, Stage1AirInst *value, bool force_runtime, bool allow_discard);
249static Stage1AirInst *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
250 Stage1AirInst *base_ptr, bool safety_check_on, bool initializing);
251static Stage1AirInst *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
252 Stage1AirInst *base_ptr, bool safety_check_on, bool initializing);
253static Stage1AirInst *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,
254 Stage1AirInst *base_ptr, bool initializing);
255static Stage1AirInst *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
256 Stage1AirInst *ptr, Stage1AirInst *uncasted_value, bool allow_write_through_const);
257257static void ir_reset_result(ResultLoc *result_loc);
258static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
259 TypeStructField *field, IrInstGen *struct_ptr, ZigType *struct_type, bool initializing);
260static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,
261 Scope *scope, AstNode *source_node, IrInstGen *container_ptr, ZigType *container_type);
262static IrInstGen *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value);
263static IrInstGen *ir_error_dependency_loop(IrAnalyze *ira, AstNode *source_node);
264static IrInstGen *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty);
265static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node,
266 AstNode *field_source_node, ZigType *union_type, Buf *field_name, IrInstGen *field_result_loc,
267 IrInstGen *result_loc);
268static IrInstGen *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,
269 IrInstGen *struct_operand, TypeStructField *field);
258static Stage1AirInst *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
259 TypeStructField *field, Stage1AirInst *struct_ptr, ZigType *struct_type, bool initializing);
260static Stage1AirInst *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,
261 Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, ZigType *container_type);
262static Stage1AirInst *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value);
263static Stage1AirInst *ir_error_dependency_loop(IrAnalyze *ira, AstNode *source_node);
264static Stage1AirInst *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty);
265static Stage1AirInst *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node,
266 AstNode *field_source_node, ZigType *union_type, Buf *field_name, Stage1AirInst *field_result_loc,
267 Stage1AirInst *result_loc);
268static Stage1AirInst *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,
269 Stage1AirInst *struct_operand, TypeStructField *field);
270270static bool value_cmp_numeric_val_any(ZigValue *left, Cmp predicate, ZigValue *right);
271271static bool value_cmp_numeric_val_all(ZigValue *left, Cmp predicate, ZigValue *right);
272272static void memoize_field_init_val(CodeGen *codegen, ZigType *container_type, TypeStructField *field);
......@@ -276,195 +276,195 @@ static Error ir_resolve_lazy_recurse(AstNode *source_node, ZigValue *val);
276276static Error ir_resolve_lazy_recurse_array(AstNode *source_node, ZigValue *val, size_t len);
277277
278278
279static void ir_assert_impl(bool ok, IrInstGen *source_instruction, char const *file, unsigned int line) {
279static void ir_assert_impl(bool ok, Stage1AirInst *source_instruction, char const *file, unsigned int line) {
280280 if (ok) return;
281281 src_assert_impl(ok, source_instruction->source_node, file, line);
282282}
283283
284284#define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__)
285285
286void destroy_instruction_gen(IrInstGen *inst) {
286void destroy_instruction_gen(Stage1AirInst *inst) {
287287 switch (inst->id) {
288 case IrInstGenIdInvalid:
288 case Stage1AirInstIdInvalid:
289289 zig_unreachable();
290 case IrInstGenIdReturn:
291 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenReturn *>(inst));
292 case IrInstGenIdConst:
293 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenConst *>(inst));
294 case IrInstGenIdBinOp:
295 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBinOp *>(inst));
296 case IrInstGenIdCast:
297 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenCast *>(inst));
298 case IrInstGenIdCall:
299 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenCall *>(inst));
300 case IrInstGenIdCondBr:
301 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenCondBr *>(inst));
302 case IrInstGenIdBr:
303 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBr *>(inst));
304 case IrInstGenIdPhi:
305 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPhi *>(inst));
306 case IrInstGenIdUnreachable:
307 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenUnreachable *>(inst));
308 case IrInstGenIdElemPtr:
309 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenElemPtr *>(inst));
310 case IrInstGenIdVarPtr:
311 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenVarPtr *>(inst));
312 case IrInstGenIdReturnPtr:
313 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenReturnPtr *>(inst));
314 case IrInstGenIdLoadPtr:
315 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenLoadPtr *>(inst));
316 case IrInstGenIdStorePtr:
317 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenStorePtr *>(inst));
318 case IrInstGenIdVectorStoreElem:
319 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenVectorStoreElem *>(inst));
320 case IrInstGenIdStructFieldPtr:
321 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenStructFieldPtr *>(inst));
322 case IrInstGenIdUnionFieldPtr:
323 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenUnionFieldPtr *>(inst));
324 case IrInstGenIdAsm:
325 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAsm *>(inst));
326 case IrInstGenIdTestNonNull:
327 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenTestNonNull *>(inst));
328 case IrInstGenIdOptionalUnwrapPtr:
329 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenOptionalUnwrapPtr *>(inst));
330 case IrInstGenIdPopCount:
331 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPopCount *>(inst));
332 case IrInstGenIdClz:
333 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenClz *>(inst));
334 case IrInstGenIdCtz:
335 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenCtz *>(inst));
336 case IrInstGenIdBswap:
337 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBswap *>(inst));
338 case IrInstGenIdBitReverse:
339 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBitReverse *>(inst));
340 case IrInstGenIdSwitchBr:
341 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSwitchBr *>(inst));
342 case IrInstGenIdUnionTag:
343 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenUnionTag *>(inst));
344 case IrInstGenIdRef:
345 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenRef *>(inst));
346 case IrInstGenIdErrName:
347 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenErrName *>(inst));
348 case IrInstGenIdCmpxchg:
349 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenCmpxchg *>(inst));
350 case IrInstGenIdFence:
351 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFence *>(inst));
352 case IrInstGenIdReduce:
353 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenReduce *>(inst));
354 case IrInstGenIdTruncate:
355 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenTruncate *>(inst));
356 case IrInstGenIdShuffleVector:
357 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenShuffleVector *>(inst));
358 case IrInstGenIdSplat:
359 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSplat *>(inst));
360 case IrInstGenIdBoolNot:
361 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBoolNot *>(inst));
362 case IrInstGenIdMemset:
363 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenMemset *>(inst));
364 case IrInstGenIdMemcpy:
365 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenMemcpy *>(inst));
366 case IrInstGenIdSlice:
367 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSlice *>(inst));
368 case IrInstGenIdBreakpoint:
369 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBreakpoint *>(inst));
370 case IrInstGenIdReturnAddress:
371 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenReturnAddress *>(inst));
372 case IrInstGenIdFrameAddress:
373 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFrameAddress *>(inst));
374 case IrInstGenIdFrameHandle:
375 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFrameHandle *>(inst));
376 case IrInstGenIdFrameSize:
377 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFrameSize *>(inst));
378 case IrInstGenIdOverflowOp:
379 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenOverflowOp *>(inst));
380 case IrInstGenIdTestErr:
381 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenTestErr *>(inst));
382 case IrInstGenIdUnwrapErrCode:
383 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenUnwrapErrCode *>(inst));
384 case IrInstGenIdUnwrapErrPayload:
385 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenUnwrapErrPayload *>(inst));
386 case IrInstGenIdOptionalWrap:
387 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenOptionalWrap *>(inst));
388 case IrInstGenIdErrWrapCode:
389 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenErrWrapCode *>(inst));
390 case IrInstGenIdErrWrapPayload:
391 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenErrWrapPayload *>(inst));
392 case IrInstGenIdPtrCast:
393 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPtrCast *>(inst));
394 case IrInstGenIdBitCast:
395 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBitCast *>(inst));
396 case IrInstGenIdWidenOrShorten:
397 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenWidenOrShorten *>(inst));
398 case IrInstGenIdPtrToInt:
399 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPtrToInt *>(inst));
400 case IrInstGenIdIntToPtr:
401 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenIntToPtr *>(inst));
402 case IrInstGenIdIntToEnum:
403 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenIntToEnum *>(inst));
404 case IrInstGenIdIntToErr:
405 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenIntToErr *>(inst));
406 case IrInstGenIdErrToInt:
407 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenErrToInt *>(inst));
408 case IrInstGenIdTagName:
409 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenTagName *>(inst));
410 case IrInstGenIdPanic:
411 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPanic *>(inst));
412 case IrInstGenIdFieldParentPtr:
413 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFieldParentPtr *>(inst));
414 case IrInstGenIdAlignCast:
415 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAlignCast *>(inst));
416 case IrInstGenIdErrorReturnTrace:
417 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenErrorReturnTrace *>(inst));
418 case IrInstGenIdAtomicRmw:
419 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAtomicRmw *>(inst));
420 case IrInstGenIdSaveErrRetAddr:
421 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSaveErrRetAddr *>(inst));
422 case IrInstGenIdFloatOp:
423 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenFloatOp *>(inst));
424 case IrInstGenIdMulAdd:
425 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenMulAdd *>(inst));
426 case IrInstGenIdAtomicLoad:
427 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAtomicLoad *>(inst));
428 case IrInstGenIdAtomicStore:
429 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAtomicStore *>(inst));
430 case IrInstGenIdDeclVar:
431 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenDeclVar *>(inst));
432 case IrInstGenIdArrayToVector:
433 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenArrayToVector *>(inst));
434 case IrInstGenIdVectorToArray:
435 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenVectorToArray *>(inst));
436 case IrInstGenIdPtrOfArrayToSlice:
437 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenPtrOfArrayToSlice *>(inst));
438 case IrInstGenIdAssertZero:
439 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAssertZero *>(inst));
440 case IrInstGenIdAssertNonNull:
441 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAssertNonNull *>(inst));
442 case IrInstGenIdAlloca:
443 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAlloca *>(inst));
444 case IrInstGenIdSuspendBegin:
445 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSuspendBegin *>(inst));
446 case IrInstGenIdSuspendFinish:
447 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSuspendFinish *>(inst));
448 case IrInstGenIdResume:
449 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenResume *>(inst));
450 case IrInstGenIdAwait:
451 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenAwait *>(inst));
452 case IrInstGenIdSpillBegin:
453 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSpillBegin *>(inst));
454 case IrInstGenIdSpillEnd:
455 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenSpillEnd *>(inst));
456 case IrInstGenIdVectorExtractElem:
457 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenVectorExtractElem *>(inst));
458 case IrInstGenIdBinaryNot:
459 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenBinaryNot *>(inst));
460 case IrInstGenIdNegation:
461 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenNegation *>(inst));
462 case IrInstGenIdWasmMemorySize:
463 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenWasmMemorySize *>(inst));
464 case IrInstGenIdWasmMemoryGrow:
465 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenWasmMemoryGrow *>(inst));
466 case IrInstGenIdExtern:
467 return heap::c_allocator.destroy(reinterpret_cast<IrInstGenExtern *>(inst));
290 case Stage1AirInstIdReturn:
291 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstReturn *>(inst));
292 case Stage1AirInstIdConst:
293 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstConst *>(inst));
294 case Stage1AirInstIdBinOp:
295 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBinOp *>(inst));
296 case Stage1AirInstIdCast:
297 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstCast *>(inst));
298 case Stage1AirInstIdCall:
299 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstCall *>(inst));
300 case Stage1AirInstIdCondBr:
301 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstCondBr *>(inst));
302 case Stage1AirInstIdBr:
303 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBr *>(inst));
304 case Stage1AirInstIdPhi:
305 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPhi *>(inst));
306 case Stage1AirInstIdUnreachable:
307 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstUnreachable *>(inst));
308 case Stage1AirInstIdElemPtr:
309 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstElemPtr *>(inst));
310 case Stage1AirInstIdVarPtr:
311 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstVarPtr *>(inst));
312 case Stage1AirInstIdReturnPtr:
313 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstReturnPtr *>(inst));
314 case Stage1AirInstIdLoadPtr:
315 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstLoadPtr *>(inst));
316 case Stage1AirInstIdStorePtr:
317 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstStorePtr *>(inst));
318 case Stage1AirInstIdVectorStoreElem:
319 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstVectorStoreElem *>(inst));
320 case Stage1AirInstIdStructFieldPtr:
321 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstStructFieldPtr *>(inst));
322 case Stage1AirInstIdUnionFieldPtr:
323 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstUnionFieldPtr *>(inst));
324 case Stage1AirInstIdAsm:
325 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAsm *>(inst));
326 case Stage1AirInstIdTestNonNull:
327 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstTestNonNull *>(inst));
328 case Stage1AirInstIdOptionalUnwrapPtr:
329 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstOptionalUnwrapPtr *>(inst));
330 case Stage1AirInstIdPopCount:
331 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPopCount *>(inst));
332 case Stage1AirInstIdClz:
333 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstClz *>(inst));
334 case Stage1AirInstIdCtz:
335 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstCtz *>(inst));
336 case Stage1AirInstIdBswap:
337 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBswap *>(inst));
338 case Stage1AirInstIdBitReverse:
339 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBitReverse *>(inst));
340 case Stage1AirInstIdSwitchBr:
341 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSwitchBr *>(inst));
342 case Stage1AirInstIdUnionTag:
343 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstUnionTag *>(inst));
344 case Stage1AirInstIdRef:
345 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstRef *>(inst));
346 case Stage1AirInstIdErrName:
347 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstErrName *>(inst));
348 case Stage1AirInstIdCmpxchg:
349 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstCmpxchg *>(inst));
350 case Stage1AirInstIdFence:
351 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFence *>(inst));
352 case Stage1AirInstIdReduce:
353 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstReduce *>(inst));
354 case Stage1AirInstIdTruncate:
355 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstTruncate *>(inst));
356 case Stage1AirInstIdShuffleVector:
357 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstShuffleVector *>(inst));
358 case Stage1AirInstIdSplat:
359 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSplat *>(inst));
360 case Stage1AirInstIdBoolNot:
361 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBoolNot *>(inst));
362 case Stage1AirInstIdMemset:
363 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstMemset *>(inst));
364 case Stage1AirInstIdMemcpy:
365 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstMemcpy *>(inst));
366 case Stage1AirInstIdSlice:
367 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSlice *>(inst));
368 case Stage1AirInstIdBreakpoint:
369 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBreakpoint *>(inst));
370 case Stage1AirInstIdReturnAddress:
371 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstReturnAddress *>(inst));
372 case Stage1AirInstIdFrameAddress:
373 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFrameAddress *>(inst));
374 case Stage1AirInstIdFrameHandle:
375 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFrameHandle *>(inst));
376 case Stage1AirInstIdFrameSize:
377 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFrameSize *>(inst));
378 case Stage1AirInstIdOverflowOp:
379 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstOverflowOp *>(inst));
380 case Stage1AirInstIdTestErr:
381 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstTestErr *>(inst));
382 case Stage1AirInstIdUnwrapErrCode:
383 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstUnwrapErrCode *>(inst));
384 case Stage1AirInstIdUnwrapErrPayload:
385 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstUnwrapErrPayload *>(inst));
386 case Stage1AirInstIdOptionalWrap:
387 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstOptionalWrap *>(inst));
388 case Stage1AirInstIdErrWrapCode:
389 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstErrWrapCode *>(inst));
390 case Stage1AirInstIdErrWrapPayload:
391 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstErrWrapPayload *>(inst));
392 case Stage1AirInstIdPtrCast:
393 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPtrCast *>(inst));
394 case Stage1AirInstIdBitCast:
395 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBitCast *>(inst));
396 case Stage1AirInstIdWidenOrShorten:
397 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstWidenOrShorten *>(inst));
398 case Stage1AirInstIdPtrToInt:
399 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPtrToInt *>(inst));
400 case Stage1AirInstIdIntToPtr:
401 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstIntToPtr *>(inst));
402 case Stage1AirInstIdIntToEnum:
403 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstIntToEnum *>(inst));
404 case Stage1AirInstIdIntToErr:
405 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstIntToErr *>(inst));
406 case Stage1AirInstIdErrToInt:
407 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstErrToInt *>(inst));
408 case Stage1AirInstIdTagName:
409 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstTagName *>(inst));
410 case Stage1AirInstIdPanic:
411 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPanic *>(inst));
412 case Stage1AirInstIdFieldParentPtr:
413 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFieldParentPtr *>(inst));
414 case Stage1AirInstIdAlignCast:
415 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAlignCast *>(inst));
416 case Stage1AirInstIdErrorReturnTrace:
417 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstErrorReturnTrace *>(inst));
418 case Stage1AirInstIdAtomicRmw:
419 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAtomicRmw *>(inst));
420 case Stage1AirInstIdSaveErrRetAddr:
421 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSaveErrRetAddr *>(inst));
422 case Stage1AirInstIdFloatOp:
423 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstFloatOp *>(inst));
424 case Stage1AirInstIdMulAdd:
425 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstMulAdd *>(inst));
426 case Stage1AirInstIdAtomicLoad:
427 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAtomicLoad *>(inst));
428 case Stage1AirInstIdAtomicStore:
429 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAtomicStore *>(inst));
430 case Stage1AirInstIdDeclVar:
431 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstDeclVar *>(inst));
432 case Stage1AirInstIdArrayToVector:
433 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstArrayToVector *>(inst));
434 case Stage1AirInstIdVectorToArray:
435 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstVectorToArray *>(inst));
436 case Stage1AirInstIdPtrOfArrayToSlice:
437 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstPtrOfArrayToSlice *>(inst));
438 case Stage1AirInstIdAssertZero:
439 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAssertZero *>(inst));
440 case Stage1AirInstIdAssertNonNull:
441 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAssertNonNull *>(inst));
442 case Stage1AirInstIdAlloca:
443 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAlloca *>(inst));
444 case Stage1AirInstIdSuspendBegin:
445 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSuspendBegin *>(inst));
446 case Stage1AirInstIdSuspendFinish:
447 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSuspendFinish *>(inst));
448 case Stage1AirInstIdResume:
449 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstResume *>(inst));
450 case Stage1AirInstIdAwait:
451 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstAwait *>(inst));
452 case Stage1AirInstIdSpillBegin:
453 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSpillBegin *>(inst));
454 case Stage1AirInstIdSpillEnd:
455 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstSpillEnd *>(inst));
456 case Stage1AirInstIdVectorExtractElem:
457 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstVectorExtractElem *>(inst));
458 case Stage1AirInstIdBinaryNot:
459 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstBinaryNot *>(inst));
460 case Stage1AirInstIdNegation:
461 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstNegation *>(inst));
462 case Stage1AirInstIdWasmMemorySize:
463 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstWasmMemorySize *>(inst));
464 case Stage1AirInstIdWasmMemoryGrow:
465 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstWasmMemoryGrow *>(inst));
466 case Stage1AirInstIdExtern:
467 return heap::c_allocator.destroy(reinterpret_cast<Stage1AirInstExtern *>(inst));
468468 }
469469 zig_unreachable();
470470}
......@@ -476,7 +476,7 @@ static void ira_deref(IrAnalyze *ira) {
476476 if (ira->ref_count > 1) {
477477 ira->ref_count -= 1;
478478
479 // immediate destruction of dangling IrInstGenConst is not possible
479 // immediate destruction of dangling Stage1AirInstConst is not possible
480480 // free tracking memory because it will never be used
481481 ira->new_irb.constants.deinit(&heap::c_allocator);
482482 return;
......@@ -486,7 +486,7 @@ static void ira_deref(IrAnalyze *ira) {
486486 for (size_t bb_i = 0; bb_i < ira->zir->basic_block_list.length; bb_i += 1) {
487487 Stage1ZirBasicBlock *pass1_bb = ira->zir->basic_block_list.items[bb_i];
488488 for (size_t inst_i = 0; inst_i < pass1_bb->instruction_list.length; inst_i += 1) {
489 IrInstSrc *pass1_inst = pass1_bb->instruction_list.items[inst_i];
489 Stage1ZirInst *pass1_inst = pass1_bb->instruction_list.items[inst_i];
490490 destroy_instruction_src(pass1_inst);
491491 }
492492 heap::c_allocator.destroy(pass1_bb);
......@@ -497,7 +497,7 @@ static void ira_deref(IrAnalyze *ira) {
497497 ira->src_implicit_return_type_list.deinit();
498498 ira->resume_stack.deinit();
499499
500 // destroy dangling IrInstGenConst
500 // destroy dangling Stage1AirInstConst
501501 for (size_t i = 0; i < ira->new_irb.constants.length; i += 1) {
502502 auto constant = ira->new_irb.constants.items[i];
503503 if (constant->base.ref_count == 0 && !ir_inst_gen_has_side_effects(&constant->base))
......@@ -675,7 +675,7 @@ static bool types_have_same_zig_comptime_repr(CodeGen *codegen, ZigType *expecte
675675 zig_unreachable();
676676}
677677
678static void ir_inst_gen_append(IrBasicBlockGen *basic_block, IrInstGen *instruction) {
678static void ir_inst_gen_append(Stage1AirBasicBlock *basic_block, Stage1AirInst *instruction) {
679679 assert(basic_block);
680680 assert(instruction);
681681 basic_block->instruction_list.append(instruction);
......@@ -691,12 +691,12 @@ static bool value_is_comptime(ZigValue *const_val) {
691691 return const_val->special != ConstValSpecialRuntime;
692692}
693693
694static bool instr_is_comptime(IrInstGen *instruction) {
694static bool instr_is_comptime(Stage1AirInst *instruction) {
695695 return value_is_comptime(instruction->value);
696696}
697697
698static void ir_ref_inst_gen(IrInstGen *instruction) {
699 assert(instruction->id != IrInstGenIdInvalid);
698static void ir_ref_inst_gen(Stage1AirInst *instruction) {
699 assert(instruction->id != Stage1AirInstIdInvalid);
700700 instruction->ref_count += 1;
701701}
702702
......@@ -739,374 +739,374 @@ ZigType *ir_analyze_type_expr(IrAnalyze *ira, Scope *scope, AstNode *node) {
739739 return res_type;
740740}
741741
742static IrBasicBlockGen *ir_create_basic_block_gen(IrAnalyze *ira, Scope *scope, const char *name_hint) {
743 IrBasicBlockGen *result = heap::c_allocator.create<IrBasicBlockGen>();
742static Stage1AirBasicBlock *ir_create_basic_block_gen(IrAnalyze *ira, Scope *scope, const char *name_hint) {
743 Stage1AirBasicBlock *result = heap::c_allocator.create<Stage1AirBasicBlock>();
744744 result->scope = scope;
745745 result->name_hint = name_hint;
746746 result->debug_id = exec_next_debug_id_gen(ira->new_irb.exec);
747747 return result;
748748}
749749
750static IrBasicBlockGen *ir_build_bb_from(IrAnalyze *ira, Stage1ZirBasicBlock *other_bb) {
751 IrBasicBlockGen *new_bb = ir_create_basic_block_gen(ira, other_bb->scope, other_bb->name_hint);
750static Stage1AirBasicBlock *ir_build_bb_from(IrAnalyze *ira, Stage1ZirBasicBlock *other_bb) {
751 Stage1AirBasicBlock *new_bb = ir_create_basic_block_gen(ira, other_bb->scope, other_bb->name_hint);
752752 other_bb->child = new_bb;
753753 return new_bb;
754754}
755755
756static constexpr IrInstGenId ir_inst_id(IrInstGenDeclVar *) {
757 return IrInstGenIdDeclVar;
756static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstDeclVar *) {
757 return Stage1AirInstIdDeclVar;
758758}
759759
760static constexpr IrInstGenId ir_inst_id(IrInstGenBr *) {
761 return IrInstGenIdBr;
760static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBr *) {
761 return Stage1AirInstIdBr;
762762}
763763
764static constexpr IrInstGenId ir_inst_id(IrInstGenCondBr *) {
765 return IrInstGenIdCondBr;
764static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCondBr *) {
765 return Stage1AirInstIdCondBr;
766766}
767767
768static constexpr IrInstGenId ir_inst_id(IrInstGenSwitchBr *) {
769 return IrInstGenIdSwitchBr;
768static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSwitchBr *) {
769 return Stage1AirInstIdSwitchBr;
770770}
771771
772static constexpr IrInstGenId ir_inst_id(IrInstGenPhi *) {
773 return IrInstGenIdPhi;
772static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPhi *) {
773 return Stage1AirInstIdPhi;
774774}
775775
776static constexpr IrInstGenId ir_inst_id(IrInstGenBinaryNot *) {
777 return IrInstGenIdBinaryNot;
776static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBinaryNot *) {
777 return Stage1AirInstIdBinaryNot;
778778}
779779
780static constexpr IrInstGenId ir_inst_id(IrInstGenNegation *) {
781 return IrInstGenIdNegation;
780static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstNegation *) {
781 return Stage1AirInstIdNegation;
782782}
783783
784static constexpr IrInstGenId ir_inst_id(IrInstGenBinOp *) {
785 return IrInstGenIdBinOp;
784static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBinOp *) {
785 return Stage1AirInstIdBinOp;
786786}
787787
788static constexpr IrInstGenId ir_inst_id(IrInstGenLoadPtr *) {
789 return IrInstGenIdLoadPtr;
788static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstLoadPtr *) {
789 return Stage1AirInstIdLoadPtr;
790790}
791791
792static constexpr IrInstGenId ir_inst_id(IrInstGenStorePtr *) {
793 return IrInstGenIdStorePtr;
792static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstStorePtr *) {
793 return Stage1AirInstIdStorePtr;
794794}
795795
796static constexpr IrInstGenId ir_inst_id(IrInstGenVectorStoreElem *) {
797 return IrInstGenIdVectorStoreElem;
796static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVectorStoreElem *) {
797 return Stage1AirInstIdVectorStoreElem;
798798}
799799
800static constexpr IrInstGenId ir_inst_id(IrInstGenStructFieldPtr *) {
801 return IrInstGenIdStructFieldPtr;
800static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstStructFieldPtr *) {
801 return Stage1AirInstIdStructFieldPtr;
802802}
803803
804static constexpr IrInstGenId ir_inst_id(IrInstGenUnionFieldPtr *) {
805 return IrInstGenIdUnionFieldPtr;
804static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnionFieldPtr *) {
805 return Stage1AirInstIdUnionFieldPtr;
806806}
807807
808static constexpr IrInstGenId ir_inst_id(IrInstGenElemPtr *) {
809 return IrInstGenIdElemPtr;
808static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstElemPtr *) {
809 return Stage1AirInstIdElemPtr;
810810}
811811
812static constexpr IrInstGenId ir_inst_id(IrInstGenVarPtr *) {
813 return IrInstGenIdVarPtr;
812static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVarPtr *) {
813 return Stage1AirInstIdVarPtr;
814814}
815815
816static constexpr IrInstGenId ir_inst_id(IrInstGenReturnPtr *) {
817 return IrInstGenIdReturnPtr;
816static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReturnPtr *) {
817 return Stage1AirInstIdReturnPtr;
818818}
819819
820static constexpr IrInstGenId ir_inst_id(IrInstGenCall *) {
821 return IrInstGenIdCall;
820static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCall *) {
821 return Stage1AirInstIdCall;
822822}
823823
824static constexpr IrInstGenId ir_inst_id(IrInstGenReturn *) {
825 return IrInstGenIdReturn;
824static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReturn *) {
825 return Stage1AirInstIdReturn;
826826}
827827
828static constexpr IrInstGenId ir_inst_id(IrInstGenCast *) {
829 return IrInstGenIdCast;
828static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCast *) {
829 return Stage1AirInstIdCast;
830830}
831831
832static constexpr IrInstGenId ir_inst_id(IrInstGenUnreachable *) {
833 return IrInstGenIdUnreachable;
832static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnreachable *) {
833 return Stage1AirInstIdUnreachable;
834834}
835835
836static constexpr IrInstGenId ir_inst_id(IrInstGenAsm *) {
837 return IrInstGenIdAsm;
836static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAsm *) {
837 return Stage1AirInstIdAsm;
838838}
839839
840static constexpr IrInstGenId ir_inst_id(IrInstGenTestNonNull *) {
841 return IrInstGenIdTestNonNull;
840static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTestNonNull *) {
841 return Stage1AirInstIdTestNonNull;
842842}
843843
844static constexpr IrInstGenId ir_inst_id(IrInstGenOptionalUnwrapPtr *) {
845 return IrInstGenIdOptionalUnwrapPtr;
844static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstOptionalUnwrapPtr *) {
845 return Stage1AirInstIdOptionalUnwrapPtr;
846846}
847847
848static constexpr IrInstGenId ir_inst_id(IrInstGenOptionalWrap *) {
849 return IrInstGenIdOptionalWrap;
848static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstOptionalWrap *) {
849 return Stage1AirInstIdOptionalWrap;
850850}
851851
852static constexpr IrInstGenId ir_inst_id(IrInstGenUnionTag *) {
853 return IrInstGenIdUnionTag;
852static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnionTag *) {
853 return Stage1AirInstIdUnionTag;
854854}
855855
856static constexpr IrInstGenId ir_inst_id(IrInstGenClz *) {
857 return IrInstGenIdClz;
856static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstClz *) {
857 return Stage1AirInstIdClz;
858858}
859859
860static constexpr IrInstGenId ir_inst_id(IrInstGenCtz *) {
861 return IrInstGenIdCtz;
860static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCtz *) {
861 return Stage1AirInstIdCtz;
862862}
863863
864static constexpr IrInstGenId ir_inst_id(IrInstGenPopCount *) {
865 return IrInstGenIdPopCount;
864static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPopCount *) {
865 return Stage1AirInstIdPopCount;
866866}
867867
868static constexpr IrInstGenId ir_inst_id(IrInstGenBswap *) {
869 return IrInstGenIdBswap;
868static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBswap *) {
869 return Stage1AirInstIdBswap;
870870}
871871
872static constexpr IrInstGenId ir_inst_id(IrInstGenBitReverse *) {
873 return IrInstGenIdBitReverse;
872static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBitReverse *) {
873 return Stage1AirInstIdBitReverse;
874874}
875875
876static constexpr IrInstGenId ir_inst_id(IrInstGenRef *) {
877 return IrInstGenIdRef;
876static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstRef *) {
877 return Stage1AirInstIdRef;
878878}
879879
880static constexpr IrInstGenId ir_inst_id(IrInstGenErrName *) {
881 return IrInstGenIdErrName;
880static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrName *) {
881 return Stage1AirInstIdErrName;
882882}
883883
884static constexpr IrInstGenId ir_inst_id(IrInstGenCmpxchg *) {
885 return IrInstGenIdCmpxchg;
884static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCmpxchg *) {
885 return Stage1AirInstIdCmpxchg;
886886}
887887
888static constexpr IrInstGenId ir_inst_id(IrInstGenFence *) {
889 return IrInstGenIdFence;
888static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFence *) {
889 return Stage1AirInstIdFence;
890890}
891891
892static constexpr IrInstGenId ir_inst_id(IrInstGenReduce *) {
893 return IrInstGenIdReduce;
892static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReduce *) {
893 return Stage1AirInstIdReduce;
894894}
895895
896static constexpr IrInstGenId ir_inst_id(IrInstGenTruncate *) {
897 return IrInstGenIdTruncate;
896static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTruncate *) {
897 return Stage1AirInstIdTruncate;
898898}
899899
900static constexpr IrInstGenId ir_inst_id(IrInstGenShuffleVector *) {
901 return IrInstGenIdShuffleVector;
900static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstShuffleVector *) {
901 return Stage1AirInstIdShuffleVector;
902902}
903903
904static constexpr IrInstGenId ir_inst_id(IrInstGenSplat *) {
905 return IrInstGenIdSplat;
904static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSplat *) {
905 return Stage1AirInstIdSplat;
906906}
907907
908static constexpr IrInstGenId ir_inst_id(IrInstGenBoolNot *) {
909 return IrInstGenIdBoolNot;
908static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBoolNot *) {
909 return Stage1AirInstIdBoolNot;
910910}
911911
912static constexpr IrInstGenId ir_inst_id(IrInstGenMemset *) {
913 return IrInstGenIdMemset;
912static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstMemset *) {
913 return Stage1AirInstIdMemset;
914914}
915915
916static constexpr IrInstGenId ir_inst_id(IrInstGenMemcpy *) {
917 return IrInstGenIdMemcpy;
916static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstMemcpy *) {
917 return Stage1AirInstIdMemcpy;
918918}
919919
920static constexpr IrInstGenId ir_inst_id(IrInstGenSlice *) {
921 return IrInstGenIdSlice;
920static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSlice *) {
921 return Stage1AirInstIdSlice;
922922}
923923
924static constexpr IrInstGenId ir_inst_id(IrInstGenBreakpoint *) {
925 return IrInstGenIdBreakpoint;
924static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBreakpoint *) {
925 return Stage1AirInstIdBreakpoint;
926926}
927927
928static constexpr IrInstGenId ir_inst_id(IrInstGenReturnAddress *) {
929 return IrInstGenIdReturnAddress;
928static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReturnAddress *) {
929 return Stage1AirInstIdReturnAddress;
930930}
931931
932static constexpr IrInstGenId ir_inst_id(IrInstGenFrameAddress *) {
933 return IrInstGenIdFrameAddress;
932static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFrameAddress *) {
933 return Stage1AirInstIdFrameAddress;
934934}
935935
936static constexpr IrInstGenId ir_inst_id(IrInstGenFrameHandle *) {
937 return IrInstGenIdFrameHandle;
936static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFrameHandle *) {
937 return Stage1AirInstIdFrameHandle;
938938}
939939
940static constexpr IrInstGenId ir_inst_id(IrInstGenFrameSize *) {
941 return IrInstGenIdFrameSize;
940static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFrameSize *) {
941 return Stage1AirInstIdFrameSize;
942942}
943943
944static constexpr IrInstGenId ir_inst_id(IrInstGenOverflowOp *) {
945 return IrInstGenIdOverflowOp;
944static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstOverflowOp *) {
945 return Stage1AirInstIdOverflowOp;
946946}
947947
948static constexpr IrInstGenId ir_inst_id(IrInstGenTestErr *) {
949 return IrInstGenIdTestErr;
948static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTestErr *) {
949 return Stage1AirInstIdTestErr;
950950}
951951
952static constexpr IrInstGenId ir_inst_id(IrInstGenMulAdd *) {
953 return IrInstGenIdMulAdd;
952static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstMulAdd *) {
953 return Stage1AirInstIdMulAdd;
954954}
955955
956static constexpr IrInstGenId ir_inst_id(IrInstGenFloatOp *) {
957 return IrInstGenIdFloatOp;
956static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFloatOp *) {
957 return Stage1AirInstIdFloatOp;
958958}
959959
960static constexpr IrInstGenId ir_inst_id(IrInstGenUnwrapErrCode *) {
961 return IrInstGenIdUnwrapErrCode;
960static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnwrapErrCode *) {
961 return Stage1AirInstIdUnwrapErrCode;
962962}
963963
964static constexpr IrInstGenId ir_inst_id(IrInstGenUnwrapErrPayload *) {
965 return IrInstGenIdUnwrapErrPayload;
964static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnwrapErrPayload *) {
965 return Stage1AirInstIdUnwrapErrPayload;
966966}
967967
968static constexpr IrInstGenId ir_inst_id(IrInstGenErrWrapCode *) {
969 return IrInstGenIdErrWrapCode;
968static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrWrapCode *) {
969 return Stage1AirInstIdErrWrapCode;
970970}
971971
972static constexpr IrInstGenId ir_inst_id(IrInstGenErrWrapPayload *) {
973 return IrInstGenIdErrWrapPayload;
972static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrWrapPayload *) {
973 return Stage1AirInstIdErrWrapPayload;
974974}
975975
976static constexpr IrInstGenId ir_inst_id(IrInstGenPtrCast *) {
977 return IrInstGenIdPtrCast;
976static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPtrCast *) {
977 return Stage1AirInstIdPtrCast;
978978}
979979
980static constexpr IrInstGenId ir_inst_id(IrInstGenBitCast *) {
981 return IrInstGenIdBitCast;
980static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBitCast *) {
981 return Stage1AirInstIdBitCast;
982982}
983983
984static constexpr IrInstGenId ir_inst_id(IrInstGenWidenOrShorten *) {
985 return IrInstGenIdWidenOrShorten;
984static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstWidenOrShorten *) {
985 return Stage1AirInstIdWidenOrShorten;
986986}
987987
988static constexpr IrInstGenId ir_inst_id(IrInstGenIntToPtr *) {
989 return IrInstGenIdIntToPtr;
988static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstIntToPtr *) {
989 return Stage1AirInstIdIntToPtr;
990990}
991991
992static constexpr IrInstGenId ir_inst_id(IrInstGenPtrToInt *) {
993 return IrInstGenIdPtrToInt;
992static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPtrToInt *) {
993 return Stage1AirInstIdPtrToInt;
994994}
995995
996static constexpr IrInstGenId ir_inst_id(IrInstGenIntToEnum *) {
997 return IrInstGenIdIntToEnum;
996static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstIntToEnum *) {
997 return Stage1AirInstIdIntToEnum;
998998}
999999
1000static constexpr IrInstGenId ir_inst_id(IrInstGenIntToErr *) {
1001 return IrInstGenIdIntToErr;
1000static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstIntToErr *) {
1001 return Stage1AirInstIdIntToErr;
10021002}
10031003
1004static constexpr IrInstGenId ir_inst_id(IrInstGenErrToInt *) {
1005 return IrInstGenIdErrToInt;
1004static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrToInt *) {
1005 return Stage1AirInstIdErrToInt;
10061006}
10071007
1008static constexpr IrInstGenId ir_inst_id(IrInstGenPanic *) {
1009 return IrInstGenIdPanic;
1008static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPanic *) {
1009 return Stage1AirInstIdPanic;
10101010}
10111011
1012static constexpr IrInstGenId ir_inst_id(IrInstGenTagName *) {
1013 return IrInstGenIdTagName;
1012static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTagName *) {
1013 return Stage1AirInstIdTagName;
10141014}
10151015
1016static constexpr IrInstGenId ir_inst_id(IrInstGenFieldParentPtr *) {
1017 return IrInstGenIdFieldParentPtr;
1016static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFieldParentPtr *) {
1017 return Stage1AirInstIdFieldParentPtr;
10181018}
10191019
1020static constexpr IrInstGenId ir_inst_id(IrInstGenAlignCast *) {
1021 return IrInstGenIdAlignCast;
1020static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAlignCast *) {
1021 return Stage1AirInstIdAlignCast;
10221022}
10231023
1024static constexpr IrInstGenId ir_inst_id(IrInstGenErrorReturnTrace *) {
1025 return IrInstGenIdErrorReturnTrace;
1024static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrorReturnTrace *) {
1025 return Stage1AirInstIdErrorReturnTrace;
10261026}
10271027
1028static constexpr IrInstGenId ir_inst_id(IrInstGenAtomicRmw *) {
1029 return IrInstGenIdAtomicRmw;
1028static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAtomicRmw *) {
1029 return Stage1AirInstIdAtomicRmw;
10301030}
10311031
1032static constexpr IrInstGenId ir_inst_id(IrInstGenAtomicLoad *) {
1033 return IrInstGenIdAtomicLoad;
1032static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAtomicLoad *) {
1033 return Stage1AirInstIdAtomicLoad;
10341034}
10351035
1036static constexpr IrInstGenId ir_inst_id(IrInstGenAtomicStore *) {
1037 return IrInstGenIdAtomicStore;
1036static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAtomicStore *) {
1037 return Stage1AirInstIdAtomicStore;
10381038}
10391039
1040static constexpr IrInstGenId ir_inst_id(IrInstGenSaveErrRetAddr *) {
1041 return IrInstGenIdSaveErrRetAddr;
1040static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSaveErrRetAddr *) {
1041 return Stage1AirInstIdSaveErrRetAddr;
10421042}
10431043
1044static constexpr IrInstGenId ir_inst_id(IrInstGenVectorToArray *) {
1045 return IrInstGenIdVectorToArray;
1044static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVectorToArray *) {
1045 return Stage1AirInstIdVectorToArray;
10461046}
10471047
1048static constexpr IrInstGenId ir_inst_id(IrInstGenArrayToVector *) {
1049 return IrInstGenIdArrayToVector;
1048static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstArrayToVector *) {
1049 return Stage1AirInstIdArrayToVector;
10501050}
10511051
1052static constexpr IrInstGenId ir_inst_id(IrInstGenAssertZero *) {
1053 return IrInstGenIdAssertZero;
1052static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAssertZero *) {
1053 return Stage1AirInstIdAssertZero;
10541054}
10551055
1056static constexpr IrInstGenId ir_inst_id(IrInstGenAssertNonNull *) {
1057 return IrInstGenIdAssertNonNull;
1056static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAssertNonNull *) {
1057 return Stage1AirInstIdAssertNonNull;
10581058}
10591059
1060static constexpr IrInstGenId ir_inst_id(IrInstGenPtrOfArrayToSlice *) {
1061 return IrInstGenIdPtrOfArrayToSlice;
1060static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPtrOfArrayToSlice *) {
1061 return Stage1AirInstIdPtrOfArrayToSlice;
10621062}
10631063
1064static constexpr IrInstGenId ir_inst_id(IrInstGenSuspendBegin *) {
1065 return IrInstGenIdSuspendBegin;
1064static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSuspendBegin *) {
1065 return Stage1AirInstIdSuspendBegin;
10661066}
10671067
1068static constexpr IrInstGenId ir_inst_id(IrInstGenSuspendFinish *) {
1069 return IrInstGenIdSuspendFinish;
1068static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSuspendFinish *) {
1069 return Stage1AirInstIdSuspendFinish;
10701070}
10711071
1072static constexpr IrInstGenId ir_inst_id(IrInstGenAwait *) {
1073 return IrInstGenIdAwait;
1072static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAwait *) {
1073 return Stage1AirInstIdAwait;
10741074}
10751075
1076static constexpr IrInstGenId ir_inst_id(IrInstGenResume *) {
1077 return IrInstGenIdResume;
1076static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstResume *) {
1077 return Stage1AirInstIdResume;
10781078}
10791079
1080static constexpr IrInstGenId ir_inst_id(IrInstGenSpillBegin *) {
1081 return IrInstGenIdSpillBegin;
1080static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSpillBegin *) {
1081 return Stage1AirInstIdSpillBegin;
10821082}
10831083
1084static constexpr IrInstGenId ir_inst_id(IrInstGenSpillEnd *) {
1085 return IrInstGenIdSpillEnd;
1084static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSpillEnd *) {
1085 return Stage1AirInstIdSpillEnd;
10861086}
10871087
1088static constexpr IrInstGenId ir_inst_id(IrInstGenVectorExtractElem *) {
1089 return IrInstGenIdVectorExtractElem;
1088static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVectorExtractElem *) {
1089 return Stage1AirInstIdVectorExtractElem;
10901090}
10911091
1092static constexpr IrInstGenId ir_inst_id(IrInstGenAlloca *) {
1093 return IrInstGenIdAlloca;
1092static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAlloca *) {
1093 return Stage1AirInstIdAlloca;
10941094}
10951095
1096static constexpr IrInstGenId ir_inst_id(IrInstGenConst *) {
1097 return IrInstGenIdConst;
1096static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstConst *) {
1097 return Stage1AirInstIdConst;
10981098}
10991099
1100static constexpr IrInstGenId ir_inst_id(IrInstGenWasmMemorySize *) {
1101 return IrInstGenIdWasmMemorySize;
1100static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstWasmMemorySize *) {
1101 return Stage1AirInstIdWasmMemorySize;
11021102}
11031103
1104static constexpr IrInstGenId ir_inst_id(IrInstGenWasmMemoryGrow *) {
1105 return IrInstGenIdWasmMemoryGrow;
1104static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstWasmMemoryGrow *) {
1105 return Stage1AirInstIdWasmMemoryGrow;
11061106}
11071107
1108static constexpr IrInstGenId ir_inst_id(IrInstGenExtern *) {
1109 return IrInstGenIdExtern;
1108static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstExtern *) {
1109 return Stage1AirInstIdExtern;
11101110}
11111111
11121112template<typename T>
......@@ -1155,11 +1155,11 @@ static T *ir_build_inst_void(IrBuilderGen *irb, Scope *scope, AstNode *source_no
11551155 return special_instruction;
11561156}
11571157
1158IrInstGen *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn,
1158Stage1AirInst *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn,
11591159 ZigType *var_type, const char *name_hint)
11601160{
1161 IrInstGenAlloca *alloca_gen = heap::c_allocator.create<IrInstGenAlloca>();
1162 alloca_gen->base.id = IrInstGenIdAlloca;
1161 Stage1AirInstAlloca *alloca_gen = heap::c_allocator.create<Stage1AirInstAlloca>();
1162 alloca_gen->base.id = Stage1AirInstIdAlloca;
11631163 alloca_gen->base.source_node = source_node;
11641164 alloca_gen->base.scope = scope;
11651165 alloca_gen->base.value = g->pass1_arena->create<ZigValue>();
......@@ -1170,10 +1170,10 @@ IrInstGen *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigF
11701170 return &alloca_gen->base;
11711171}
11721172
1173static IrInstGen *ir_build_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1174 ZigType *dest_type, IrInstGen *value, CastOp cast_op)
1173static Stage1AirInst *ir_build_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1174 ZigType *dest_type, Stage1AirInst *value, CastOp cast_op)
11751175{
1176 IrInstGenCast *inst = ir_build_inst_gen<IrInstGenCast>(&ira->new_irb, scope, source_node);
1176 Stage1AirInstCast *inst = ir_build_inst_gen<Stage1AirInstCast>(&ira->new_irb, scope, source_node);
11771177 inst->base.value->type = dest_type;
11781178 inst->value = value;
11791179 inst->cast_op = cast_op;
......@@ -1183,10 +1183,10 @@ static IrInstGen *ir_build_cast(IrAnalyze *ira, Scope *scope, AstNode *source_no
11831183 return &inst->base;
11841184}
11851185
1186static IrInstGen *ir_build_cond_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *condition,
1187 IrBasicBlockGen *then_block, IrBasicBlockGen *else_block)
1186static Stage1AirInst *ir_build_cond_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *condition,
1187 Stage1AirBasicBlock *then_block, Stage1AirBasicBlock *else_block)
11881188{
1189 IrInstGenCondBr *inst = ir_build_inst_noreturn<IrInstGenCondBr>(&ira->new_irb, scope, source_node);
1189 Stage1AirInstCondBr *inst = ir_build_inst_noreturn<Stage1AirInstCondBr>(&ira->new_irb, scope, source_node);
11901190 inst->condition = condition;
11911191 inst->then_block = then_block;
11921192 inst->else_block = else_block;
......@@ -1196,8 +1196,8 @@ static IrInstGen *ir_build_cond_br_gen(IrAnalyze *ira, Scope *scope, AstNode *so
11961196 return &inst->base;
11971197}
11981198
1199static IrInstGen *ir_build_return_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand) {
1200 IrInstGenReturn *inst = ir_build_inst_noreturn<IrInstGenReturn>(&ira->new_irb, scope, source_node);
1199static Stage1AirInst *ir_build_return_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand) {
1200 Stage1AirInstReturn *inst = ir_build_inst_noreturn<Stage1AirInstReturn>(&ira->new_irb, scope, source_node);
12011201 inst->operand = operand;
12021202
12031203 if (operand != nullptr) ir_ref_inst_gen(operand);
......@@ -1205,10 +1205,10 @@ static IrInstGen *ir_build_return_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
12051205 return &inst->base;
12061206}
12071207
1208static IrInstGen *ir_build_bin_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *res_type,
1209 IrBinOp op_id, IrInstGen *op1, IrInstGen *op2, bool safety_check_on)
1208static Stage1AirInst *ir_build_bin_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *res_type,
1209 IrBinOp op_id, Stage1AirInst *op1, Stage1AirInst *op2, bool safety_check_on)
12101210{
1211 IrInstGenBinOp *inst = ir_build_inst_gen<IrInstGenBinOp>(&ira->new_irb,
1211 Stage1AirInstBinOp *inst = ir_build_inst_gen<Stage1AirInstBinOp>(&ira->new_irb,
12121212 scope, source_node);
12131213 inst->base.value->type = res_type;
12141214 inst->op_id = op_id;
......@@ -1223,8 +1223,8 @@ static IrInstGen *ir_build_bin_op_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
12231223}
12241224
12251225
1226static IrInstGen *ir_build_var_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) {
1227 IrInstGenVarPtr *instruction = ir_build_inst_gen<IrInstGenVarPtr>(&ira->new_irb, scope, source_node);
1226static Stage1AirInst *ir_build_var_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) {
1227 Stage1AirInstVarPtr *instruction = ir_build_inst_gen<Stage1AirInstVarPtr>(&ira->new_irb, scope, source_node);
12281228 instruction->var = var;
12291229
12301230 var->ref_count += 1;
......@@ -1232,16 +1232,16 @@ static IrInstGen *ir_build_var_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *so
12321232 return &instruction->base;
12331233}
12341234
1235static IrInstGen *ir_build_return_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
1236 IrInstGenReturnPtr *instruction = ir_build_inst_gen<IrInstGenReturnPtr>(&ira->new_irb, scope, source_node);
1235static Stage1AirInst *ir_build_return_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
1236 Stage1AirInstReturnPtr *instruction = ir_build_inst_gen<Stage1AirInstReturnPtr>(&ira->new_irb, scope, source_node);
12371237 instruction->base.value->type = ty;
12381238 return &instruction->base;
12391239}
12401240
1241static IrInstGen *ir_build_elem_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1242 IrInstGen *array_ptr, IrInstGen *elem_index, bool safety_check_on, ZigType *return_type)
1241static Stage1AirInst *ir_build_elem_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1242 Stage1AirInst *array_ptr, Stage1AirInst *elem_index, bool safety_check_on, ZigType *return_type)
12431243{
1244 IrInstGenElemPtr *instruction = ir_build_inst_gen<IrInstGenElemPtr>(&ira->new_irb, scope, source_node);
1244 Stage1AirInstElemPtr *instruction = ir_build_inst_gen<Stage1AirInstElemPtr>(&ira->new_irb, scope, source_node);
12451245 instruction->base.value->type = return_type;
12461246 instruction->array_ptr = array_ptr;
12471247 instruction->elem_index = elem_index;
......@@ -1253,10 +1253,10 @@ static IrInstGen *ir_build_elem_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *s
12531253 return &instruction->base;
12541254}
12551255
1256static IrInstGen *ir_build_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1257 IrInstGen *struct_ptr, TypeStructField *field, ZigType *ptr_type)
1256static Stage1AirInst *ir_build_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1257 Stage1AirInst *struct_ptr, TypeStructField *field, ZigType *ptr_type)
12581258{
1259 IrInstGenStructFieldPtr *inst = ir_build_inst_gen<IrInstGenStructFieldPtr>(&ira->new_irb, scope, source_node);
1259 Stage1AirInstStructFieldPtr *inst = ir_build_inst_gen<Stage1AirInstStructFieldPtr>(&ira->new_irb, scope, source_node);
12601260 inst->base.value->type = ptr_type;
12611261 inst->struct_ptr = struct_ptr;
12621262 inst->field = field;
......@@ -1266,10 +1266,10 @@ static IrInstGen *ir_build_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNod
12661266 return &inst->base;
12671267}
12681268
1269static IrInstGen *ir_build_union_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1270 IrInstGen *union_ptr, TypeUnionField *field, bool safety_check_on, bool initializing, ZigType *ptr_type)
1269static Stage1AirInst *ir_build_union_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1270 Stage1AirInst *union_ptr, TypeUnionField *field, bool safety_check_on, bool initializing, ZigType *ptr_type)
12711271{
1272 IrInstGenUnionFieldPtr *inst = ir_build_inst_gen<IrInstGenUnionFieldPtr>(&ira->new_irb,
1272 Stage1AirInstUnionFieldPtr *inst = ir_build_inst_gen<Stage1AirInstUnionFieldPtr>(&ira->new_irb,
12731273 scope, source_node);
12741274 inst->base.value->type = ptr_type;
12751275 inst->initializing = initializing;
......@@ -1282,12 +1282,12 @@ static IrInstGen *ir_build_union_field_ptr(IrAnalyze *ira, Scope *scope, AstNode
12821282 return &inst->base;
12831283}
12841284
1285static IrInstGenCall *ir_build_call_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1286 ZigFn *fn_entry, IrInstGen *fn_ref, size_t arg_count, IrInstGen **args,
1287 CallModifier modifier, IrInstGen *new_stack, bool is_async_call_builtin,
1288 IrInstGen *result_loc, ZigType *return_type)
1285static Stage1AirInstCall *ir_build_call_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1286 ZigFn *fn_entry, Stage1AirInst *fn_ref, size_t arg_count, Stage1AirInst **args,
1287 CallModifier modifier, Stage1AirInst *new_stack, bool is_async_call_builtin,
1288 Stage1AirInst *result_loc, ZigType *return_type)
12891289{
1290 IrInstGenCall *call_instruction = ir_build_inst_gen<IrInstGenCall>(&ira->new_irb,
1290 Stage1AirInstCall *call_instruction = ir_build_inst_gen<Stage1AirInstCall>(&ira->new_irb,
12911291 scope, source_node);
12921292 call_instruction->base.value->type = return_type;
12931293 call_instruction->fn_entry = fn_entry;
......@@ -1308,13 +1308,13 @@ static IrInstGenCall *ir_build_call_gen(IrAnalyze *ira, Scope *scope, AstNode *s
13081308 return call_instruction;
13091309}
13101310
1311static IrInstGen *ir_build_phi_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, size_t incoming_count,
1312 IrBasicBlockGen **incoming_blocks, IrInstGen **incoming_values, ZigType *result_type)
1311static Stage1AirInst *ir_build_phi_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, size_t incoming_count,
1312 Stage1AirBasicBlock **incoming_blocks, Stage1AirInst **incoming_values, ZigType *result_type)
13131313{
13141314 assert(incoming_count != 0);
13151315 assert(incoming_count != SIZE_MAX);
13161316
1317 IrInstGenPhi *phi_instruction = ir_build_inst_gen<IrInstGenPhi>(&ira->new_irb,
1317 Stage1AirInstPhi *phi_instruction = ir_build_inst_gen<Stage1AirInstPhi>(&ira->new_irb,
13181318 scope, source_node);
13191319 phi_instruction->base.value->type = result_type;
13201320 phi_instruction->incoming_count = incoming_count;
......@@ -1328,15 +1328,15 @@ static IrInstGen *ir_build_phi_gen(IrAnalyze *ira, Scope *scope, AstNode *source
13281328 return &phi_instruction->base;
13291329}
13301330
1331static IrInstGen *ir_build_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrBasicBlockGen *dest_block) {
1332 IrInstGenBr *inst = ir_build_inst_noreturn<IrInstGenBr>(&ira->new_irb, scope, source_node);
1331static Stage1AirInst *ir_build_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirBasicBlock *dest_block) {
1332 Stage1AirInstBr *inst = ir_build_inst_noreturn<Stage1AirInstBr>(&ira->new_irb, scope, source_node);
13331333 inst->dest_block = dest_block;
13341334
13351335 return &inst->base;
13361336}
13371337
1338static IrInstGen *ir_build_negation(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand, ZigType *expr_type, bool wrapping) {
1339 IrInstGenNegation *instruction = ir_build_inst_gen<IrInstGenNegation>(&ira->new_irb,
1338static Stage1AirInst *ir_build_negation(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand, ZigType *expr_type, bool wrapping) {
1339 Stage1AirInstNegation *instruction = ir_build_inst_gen<Stage1AirInstNegation>(&ira->new_irb,
13401340 scope, source_node);
13411341 instruction->base.value->type = expr_type;
13421342 instruction->operand = operand;
......@@ -1347,10 +1347,10 @@ static IrInstGen *ir_build_negation(IrAnalyze *ira, Scope *scope, AstNode *sourc
13471347 return &instruction->base;
13481348}
13491349
1350static IrInstGen *ir_build_binary_not(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand,
1350static Stage1AirInst *ir_build_binary_not(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand,
13511351 ZigType *expr_type)
13521352{
1353 IrInstGenBinaryNot *instruction = ir_build_inst_gen<IrInstGenBinaryNot>(&ira->new_irb,
1353 Stage1AirInstBinaryNot *instruction = ir_build_inst_gen<Stage1AirInstBinaryNot>(&ira->new_irb,
13541354 scope, source_node);
13551355 instruction->base.value->type = expr_type;
13561356 instruction->operand = operand;
......@@ -1360,13 +1360,13 @@ static IrInstGen *ir_build_binary_not(IrAnalyze *ira, Scope *scope, AstNode *sou
13601360 return &instruction->base;
13611361}
13621362
1363static IrInstGen *ir_build_unreachable_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1364 IrInstGenUnreachable *inst = ir_build_inst_noreturn<IrInstGenUnreachable>(&ira->new_irb, scope, source_node);
1363static Stage1AirInst *ir_build_unreachable_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1364 Stage1AirInstUnreachable *inst = ir_build_inst_noreturn<Stage1AirInstUnreachable>(&ira->new_irb, scope, source_node);
13651365 return &inst->base;
13661366}
13671367
1368static IrInstGen *ir_build_store_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *ptr, IrInstGen *value) {
1369 IrInstGenStorePtr *instruction = ir_build_inst_void<IrInstGenStorePtr>(&ira->new_irb,
1368static Stage1AirInst *ir_build_store_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *ptr, Stage1AirInst *value) {
1369 Stage1AirInstStorePtr *instruction = ir_build_inst_void<Stage1AirInstStorePtr>(&ira->new_irb,
13701370 scope, source_node);
13711371 instruction->ptr = ptr;
13721372 instruction->value = value;
......@@ -1377,10 +1377,10 @@ static IrInstGen *ir_build_store_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *
13771377 return &instruction->base;
13781378}
13791379
1380static IrInstGen *ir_build_vector_store_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1381 IrInstGen *vector_ptr, IrInstGen *index, IrInstGen *value)
1380static Stage1AirInst *ir_build_vector_store_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1381 Stage1AirInst *vector_ptr, Stage1AirInst *index, Stage1AirInst *value)
13821382{
1383 IrInstGenVectorStoreElem *inst = ir_build_inst_void<IrInstGenVectorStoreElem>(
1383 Stage1AirInstVectorStoreElem *inst = ir_build_inst_void<Stage1AirInstVectorStoreElem>(
13841384 &ira->new_irb, scope, source_node);
13851385 inst->vector_ptr = vector_ptr;
13861386 inst->index = index;
......@@ -1393,10 +1393,10 @@ static IrInstGen *ir_build_vector_store_elem(IrAnalyze *ira, Scope *scope, AstNo
13931393 return &inst->base;
13941394}
13951395
1396static IrInstGen *ir_build_var_decl_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1397 ZigVar *var, IrInstGen *var_ptr)
1396static Stage1AirInst *ir_build_var_decl_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1397 ZigVar *var, Stage1AirInst *var_ptr)
13981398{
1399 IrInstGenDeclVar *inst = ir_build_inst_gen<IrInstGenDeclVar>(&ira->new_irb,
1399 Stage1AirInstDeclVar *inst = ir_build_inst_gen<Stage1AirInstDeclVar>(&ira->new_irb,
14001400 scope, source_node);
14011401 inst->base.value->special = ConstValSpecialStatic;
14021402 inst->base.value->type = ira->codegen->builtin_types.entry_void;
......@@ -1408,10 +1408,10 @@ static IrInstGen *ir_build_var_decl_gen(IrAnalyze *ira, Scope *scope, AstNode *s
14081408 return &inst->base;
14091409}
14101410
1411static IrInstGen *ir_build_extern_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Buf *name,
1411static Stage1AirInst *ir_build_extern_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Buf *name,
14121412 GlobalLinkageId linkage, bool is_thread_local, ZigType *expr_type)
14131413{
1414 IrInstGenExtern *instruction = ir_build_inst_gen<IrInstGenExtern>(&ira->new_irb,
1414 Stage1AirInstExtern *instruction = ir_build_inst_gen<Stage1AirInstExtern>(&ira->new_irb,
14151415 scope, source_node);
14161416 instruction->base.value->type = expr_type;
14171417 instruction->name = name;
......@@ -1421,10 +1421,10 @@ static IrInstGen *ir_build_extern_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
14211421 return &instruction->base;
14221422}
14231423
1424static IrInstGen *ir_build_load_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1425 IrInstGen *ptr, ZigType *ty, IrInstGen *result_loc)
1424static Stage1AirInst *ir_build_load_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1425 Stage1AirInst *ptr, ZigType *ty, Stage1AirInst *result_loc)
14261426{
1427 IrInstGenLoadPtr *instruction = ir_build_inst_gen<IrInstGenLoadPtr>(
1427 Stage1AirInstLoadPtr *instruction = ir_build_inst_gen<Stage1AirInstLoadPtr>(
14281428 &ira->new_irb, scope, source_node);
14291429 instruction->base.value->type = ty;
14301430 instruction->ptr = ptr;
......@@ -1436,12 +1436,12 @@ static IrInstGen *ir_build_load_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *s
14361436 return &instruction->base;
14371437}
14381438
1439static IrInstGen *ir_build_asm_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1439static Stage1AirInst *ir_build_asm_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
14401440 Buf *asm_template, AsmToken *token_list, size_t token_list_len,
1441 IrInstGen **input_list, IrInstGen **output_types, ZigVar **output_vars, size_t return_count,
1441 Stage1AirInst **input_list, Stage1AirInst **output_types, ZigVar **output_vars, size_t return_count,
14421442 bool has_side_effects, ZigType *return_type)
14431443{
1444 IrInstGenAsm *instruction = ir_build_inst_gen<IrInstGenAsm>(&ira->new_irb, scope, source_node);
1444 Stage1AirInstAsm *instruction = ir_build_inst_gen<Stage1AirInstAsm>(&ira->new_irb, scope, source_node);
14451445 instruction->base.value->type = return_type;
14461446 instruction->asm_template = asm_template;
14471447 instruction->token_list = token_list;
......@@ -1454,20 +1454,20 @@ static IrInstGen *ir_build_asm_gen(IrAnalyze *ira, Scope *scope, AstNode *source
14541454
14551455 assert(source_node->type == NodeTypeAsmExpr);
14561456 for (size_t i = 0; i < source_node->data.asm_expr.output_list.length; i += 1) {
1457 IrInstGen *output_type = output_types[i];
1457 Stage1AirInst *output_type = output_types[i];
14581458 if (output_type) ir_ref_inst_gen(output_type);
14591459 }
14601460
14611461 for (size_t i = 0; i < source_node->data.asm_expr.input_list.length; i += 1) {
1462 IrInstGen *input_value = input_list[i];
1462 Stage1AirInst *input_value = input_list[i];
14631463 ir_ref_inst_gen(input_value);
14641464 }
14651465
14661466 return &instruction->base;
14671467}
14681468
1469static IrInstGen *ir_build_test_non_null_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) {
1470 IrInstGenTestNonNull *inst = ir_build_inst_gen<IrInstGenTestNonNull>(&ira->new_irb,
1469static Stage1AirInst *ir_build_test_non_null_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) {
1470 Stage1AirInstTestNonNull *inst = ir_build_inst_gen<Stage1AirInstTestNonNull>(&ira->new_irb,
14711471 scope, source_node);
14721472 inst->base.value->type = ira->codegen->builtin_types.entry_bool;
14731473 inst->value = value;
......@@ -1477,10 +1477,10 @@ static IrInstGen *ir_build_test_non_null_gen(IrAnalyze *ira, Scope *scope, AstNo
14771477 return &inst->base;
14781478}
14791479
1480static IrInstGen *ir_build_optional_unwrap_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1481 IrInstGen *base_ptr, bool safety_check_on, bool initializing, ZigType *result_type)
1480static Stage1AirInst *ir_build_optional_unwrap_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1481 Stage1AirInst *base_ptr, bool safety_check_on, bool initializing, ZigType *result_type)
14821482{
1483 IrInstGenOptionalUnwrapPtr *inst = ir_build_inst_gen<IrInstGenOptionalUnwrapPtr>(&ira->new_irb,
1483 Stage1AirInstOptionalUnwrapPtr *inst = ir_build_inst_gen<Stage1AirInstOptionalUnwrapPtr>(&ira->new_irb,
14841484 scope, source_node);
14851485 inst->base.value->type = result_type;
14861486 inst->base_ptr = base_ptr;
......@@ -1492,10 +1492,10 @@ static IrInstGen *ir_build_optional_unwrap_ptr_gen(IrAnalyze *ira, Scope *scope,
14921492 return &inst->base;
14931493}
14941494
1495static IrInstGen *ir_build_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_ty,
1496 IrInstGen *operand, IrInstGen *result_loc)
1495static Stage1AirInst *ir_build_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_ty,
1496 Stage1AirInst *operand, Stage1AirInst *result_loc)
14971497{
1498 IrInstGenOptionalWrap *instruction = ir_build_inst_gen<IrInstGenOptionalWrap>(
1498 Stage1AirInstOptionalWrap *instruction = ir_build_inst_gen<Stage1AirInstOptionalWrap>(
14991499 &ira->new_irb, scope, source_node);
15001500 instruction->base.value->type = result_ty;
15011501 instruction->operand = operand;
......@@ -1507,10 +1507,10 @@ static IrInstGen *ir_build_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *
15071507 return &instruction->base;
15081508}
15091509
1510static IrInstGen *ir_build_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1511 ZigType *result_type, IrInstGen *operand, IrInstGen *result_loc)
1510static Stage1AirInst *ir_build_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1511 ZigType *result_type, Stage1AirInst *operand, Stage1AirInst *result_loc)
15121512{
1513 IrInstGenErrWrapPayload *instruction = ir_build_inst_gen<IrInstGenErrWrapPayload>(
1513 Stage1AirInstErrWrapPayload *instruction = ir_build_inst_gen<Stage1AirInstErrWrapPayload>(
15141514 &ira->new_irb, scope, source_node);
15151515 instruction->base.value->type = result_type;
15161516 instruction->operand = operand;
......@@ -1522,10 +1522,10 @@ static IrInstGen *ir_build_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNod
15221522 return &instruction->base;
15231523}
15241524
1525static IrInstGen *ir_build_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1526 ZigType *result_type, IrInstGen *operand, IrInstGen *result_loc)
1525static Stage1AirInst *ir_build_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1526 ZigType *result_type, Stage1AirInst *operand, Stage1AirInst *result_loc)
15271527{
1528 IrInstGenErrWrapCode *instruction = ir_build_inst_gen<IrInstGenErrWrapCode>(
1528 Stage1AirInstErrWrapCode *instruction = ir_build_inst_gen<Stage1AirInstErrWrapCode>(
15291529 &ira->new_irb, scope, source_node);
15301530 instruction->base.value->type = result_type;
15311531 instruction->operand = operand;
......@@ -1537,8 +1537,8 @@ static IrInstGen *ir_build_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *
15371537 return &instruction->base;
15381538}
15391539
1540static IrInstGen *ir_build_clz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, IrInstGen *op) {
1541 IrInstGenClz *instruction = ir_build_inst_gen<IrInstGenClz>(&ira->new_irb,
1540static Stage1AirInst *ir_build_clz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, Stage1AirInst *op) {
1541 Stage1AirInstClz *instruction = ir_build_inst_gen<Stage1AirInstClz>(&ira->new_irb,
15421542 scope, source_node);
15431543 instruction->base.value->type = result_type;
15441544 instruction->op = op;
......@@ -1548,8 +1548,8 @@ static IrInstGen *ir_build_clz_gen(IrAnalyze *ira, Scope *scope, AstNode *source
15481548 return &instruction->base;
15491549}
15501550
1551static IrInstGen *ir_build_ctz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, IrInstGen *op) {
1552 IrInstGenCtz *instruction = ir_build_inst_gen<IrInstGenCtz>(&ira->new_irb,
1551static Stage1AirInst *ir_build_ctz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, Stage1AirInst *op) {
1552 Stage1AirInstCtz *instruction = ir_build_inst_gen<Stage1AirInstCtz>(&ira->new_irb,
15531553 scope, source_node);
15541554 instruction->base.value->type = result_type;
15551555 instruction->op = op;
......@@ -1559,10 +1559,10 @@ static IrInstGen *ir_build_ctz_gen(IrAnalyze *ira, Scope *scope, AstNode *source
15591559 return &instruction->base;
15601560}
15611561
1562static IrInstGen *ir_build_pop_count_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1563 IrInstGen *op)
1562static Stage1AirInst *ir_build_pop_count_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1563 Stage1AirInst *op)
15641564{
1565 IrInstGenPopCount *instruction = ir_build_inst_gen<IrInstGenPopCount>(&ira->new_irb,
1565 Stage1AirInstPopCount *instruction = ir_build_inst_gen<Stage1AirInstPopCount>(&ira->new_irb,
15661566 scope, source_node);
15671567 instruction->base.value->type = result_type;
15681568 instruction->op = op;
......@@ -1572,10 +1572,10 @@ static IrInstGen *ir_build_pop_count_gen(IrAnalyze *ira, Scope *scope, AstNode *
15721572 return &instruction->base;
15731573}
15741574
1575static IrInstGen *ir_build_bswap_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *op_type,
1576 IrInstGen *op)
1575static Stage1AirInst *ir_build_bswap_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *op_type,
1576 Stage1AirInst *op)
15771577{
1578 IrInstGenBswap *instruction = ir_build_inst_gen<IrInstGenBswap>(&ira->new_irb,
1578 Stage1AirInstBswap *instruction = ir_build_inst_gen<Stage1AirInstBswap>(&ira->new_irb,
15791579 scope, source_node);
15801580 instruction->base.value->type = op_type;
15811581 instruction->op = op;
......@@ -1585,10 +1585,10 @@ static IrInstGen *ir_build_bswap_gen(IrAnalyze *ira, Scope *scope, AstNode *sour
15851585 return &instruction->base;
15861586}
15871587
1588static IrInstGen *ir_build_bit_reverse_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *int_type,
1589 IrInstGen *op)
1588static Stage1AirInst *ir_build_bit_reverse_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *int_type,
1589 Stage1AirInst *op)
15901590{
1591 IrInstGenBitReverse *instruction = ir_build_inst_gen<IrInstGenBitReverse>(&ira->new_irb,
1591 Stage1AirInstBitReverse *instruction = ir_build_inst_gen<Stage1AirInstBitReverse>(&ira->new_irb,
15921592 scope, source_node);
15931593 instruction->base.value->type = int_type;
15941594 instruction->op = op;
......@@ -1598,10 +1598,10 @@ static IrInstGen *ir_build_bit_reverse_gen(IrAnalyze *ira, Scope *scope, AstNode
15981598 return &instruction->base;
15991599}
16001600
1601static IrInstGenSwitchBr *ir_build_switch_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1602 IrInstGen *target_value, IrBasicBlockGen *else_block, size_t case_count, IrInstGenSwitchBrCase *cases)
1601static Stage1AirInstSwitchBr *ir_build_switch_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1602 Stage1AirInst *target_value, Stage1AirBasicBlock *else_block, size_t case_count, Stage1AirInstSwitchBrCase *cases)
16031603{
1604 IrInstGenSwitchBr *instruction = ir_build_inst_noreturn<IrInstGenSwitchBr>(&ira->new_irb,
1604 Stage1AirInstSwitchBr *instruction = ir_build_inst_noreturn<Stage1AirInstSwitchBr>(&ira->new_irb,
16051605 scope, source_node);
16061606 instruction->target_value = target_value;
16071607 instruction->else_block = else_block;
......@@ -1617,10 +1617,10 @@ static IrInstGenSwitchBr *ir_build_switch_br_gen(IrAnalyze *ira, Scope *scope, A
16171617 return instruction;
16181618}
16191619
1620static IrInstGen *ir_build_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,
1620static Stage1AirInst *ir_build_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
16211621 ZigType *tag_type)
16221622{
1623 IrInstGenUnionTag *instruction = ir_build_inst_gen<IrInstGenUnionTag>(&ira->new_irb,
1623 Stage1AirInstUnionTag *instruction = ir_build_inst_gen<Stage1AirInstUnionTag>(&ira->new_irb,
16241624 scope, source_node);
16251625 instruction->value = value;
16261626 instruction->base.value->type = tag_type;
......@@ -1630,10 +1630,10 @@ static IrInstGen *ir_build_union_tag(IrAnalyze *ira, Scope *scope, AstNode *sour
16301630 return &instruction->base;
16311631}
16321632
1633static IrInstGen *ir_build_ref_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1634 IrInstGen *operand, IrInstGen *result_loc)
1633static Stage1AirInst *ir_build_ref_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1634 Stage1AirInst *operand, Stage1AirInst *result_loc)
16351635{
1636 IrInstGenRef *instruction = ir_build_inst_gen<IrInstGenRef>(&ira->new_irb,
1636 Stage1AirInstRef *instruction = ir_build_inst_gen<Stage1AirInstRef>(&ira->new_irb,
16371637 scope, source_node);
16381638 instruction->base.value->type = result_type;
16391639 instruction->operand = operand;
......@@ -1645,10 +1645,10 @@ static IrInstGen *ir_build_ref_gen(IrAnalyze *ira, Scope *scope, AstNode *source
16451645 return &instruction->base;
16461646}
16471647
1648static IrInstGen *ir_build_err_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,
1648static Stage1AirInst *ir_build_err_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
16491649 ZigType *str_type)
16501650{
1651 IrInstGenErrName *instruction = ir_build_inst_gen<IrInstGenErrName>(&ira->new_irb,
1651 Stage1AirInstErrName *instruction = ir_build_inst_gen<Stage1AirInstErrName>(&ira->new_irb,
16521652 scope, source_node);
16531653 instruction->base.value->type = str_type;
16541654 instruction->value = value;
......@@ -1658,11 +1658,11 @@ static IrInstGen *ir_build_err_name_gen(IrAnalyze *ira, Scope *scope, AstNode *s
16581658 return &instruction->base;
16591659}
16601660
1661static IrInstGen *ir_build_cmpxchg_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1662 IrInstGen *ptr, IrInstGen *cmp_value, IrInstGen *new_value,
1663 AtomicOrder success_order, AtomicOrder failure_order, bool is_weak, IrInstGen *result_loc)
1661static Stage1AirInst *ir_build_cmpxchg_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1662 Stage1AirInst *ptr, Stage1AirInst *cmp_value, Stage1AirInst *new_value,
1663 AtomicOrder success_order, AtomicOrder failure_order, bool is_weak, Stage1AirInst *result_loc)
16641664{
1665 IrInstGenCmpxchg *instruction = ir_build_inst_gen<IrInstGenCmpxchg>(&ira->new_irb,
1665 Stage1AirInstCmpxchg *instruction = ir_build_inst_gen<Stage1AirInstCmpxchg>(&ira->new_irb,
16661666 scope, source_node);
16671667 instruction->base.value->type = result_type;
16681668 instruction->ptr = ptr;
......@@ -1681,16 +1681,16 @@ static IrInstGen *ir_build_cmpxchg_gen(IrAnalyze *ira, Scope *scope, AstNode *so
16811681 return &instruction->base;
16821682}
16831683
1684static IrInstGen *ir_build_fence_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, AtomicOrder order) {
1685 IrInstGenFence *instruction = ir_build_inst_void<IrInstGenFence>(&ira->new_irb,
1684static Stage1AirInst *ir_build_fence_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, AtomicOrder order) {
1685 Stage1AirInstFence *instruction = ir_build_inst_void<Stage1AirInstFence>(&ira->new_irb,
16861686 scope, source_node);
16871687 instruction->order = order;
16881688
16891689 return &instruction->base;
16901690}
16911691
1692static IrInstGen *ir_build_reduce_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ReduceOp op, IrInstGen *value, ZigType *result_type) {
1693 IrInstGenReduce *instruction = ir_build_inst_gen<IrInstGenReduce>(&ira->new_irb,
1692static Stage1AirInst *ir_build_reduce_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ReduceOp op, Stage1AirInst *value, ZigType *result_type) {
1693 Stage1AirInstReduce *instruction = ir_build_inst_gen<Stage1AirInstReduce>(&ira->new_irb,
16941694 scope, source_node);
16951695 instruction->base.value->type = result_type;
16961696 instruction->op = op;
......@@ -1701,38 +1701,38 @@ static IrInstGen *ir_build_reduce_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
17011701 return &instruction->base;
17021702}
17031703
1704static void ir_set_cursor_at_end_gen(IrBuilderGen *irb, IrBasicBlockGen *basic_block) {
1704static void ir_set_cursor_at_end_gen(IrBuilderGen *irb, Stage1AirBasicBlock *basic_block) {
17051705 assert(basic_block);
17061706 irb->current_basic_block = basic_block;
17071707}
17081708
1709static void ir_append_basic_block_gen(IrBuilderGen *irb, IrBasicBlockGen *bb) {
1709static void ir_append_basic_block_gen(IrBuilderGen *irb, Stage1AirBasicBlock *bb) {
17101710 assert(!bb->already_appended);
17111711 bb->already_appended = true;
17121712 irb->exec->basic_block_list.append(bb);
17131713}
17141714
1715static void ir_set_cursor_at_end_and_append_block_gen(IrBuilderGen *irb, IrBasicBlockGen *basic_block) {
1715static void ir_set_cursor_at_end_and_append_block_gen(IrBuilderGen *irb, Stage1AirBasicBlock *basic_block) {
17161716 ir_append_basic_block_gen(irb, basic_block);
17171717 ir_set_cursor_at_end_gen(irb, basic_block);
17181718}
17191719
1720static IrInstGen *ir_build_suspend_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1721 IrInstGenSuspendBegin *inst = ir_build_inst_void<IrInstGenSuspendBegin>(&ira->new_irb,
1720static Stage1AirInst *ir_build_suspend_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1721 Stage1AirInstSuspendBegin *inst = ir_build_inst_void<Stage1AirInstSuspendBegin>(&ira->new_irb,
17221722 scope, source_node);
17231723 return &inst->base;
17241724}
17251725
1726static IrInstGen *ir_build_save_err_ret_addr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1727 IrInstGenSaveErrRetAddr *inst = ir_build_inst_void<IrInstGenSaveErrRetAddr>(&ira->new_irb,
1726static Stage1AirInst *ir_build_save_err_ret_addr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1727 Stage1AirInstSaveErrRetAddr *inst = ir_build_inst_void<Stage1AirInstSaveErrRetAddr>(&ira->new_irb,
17281728 scope, source_node);
17291729 return &inst->base;
17301730}
17311731
1732static IrInstGen *ir_build_truncate_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *dest_type,
1733 IrInstGen *target)
1732static Stage1AirInst *ir_build_truncate_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *dest_type,
1733 Stage1AirInst *target)
17341734{
1735 IrInstGenTruncate *instruction = ir_build_inst_gen<IrInstGenTruncate>(&ira->new_irb,
1735 Stage1AirInstTruncate *instruction = ir_build_inst_gen<Stage1AirInstTruncate>(&ira->new_irb,
17361736 scope, source_node);
17371737 instruction->base.value->type = dest_type;
17381738 instruction->target = target;
......@@ -1742,10 +1742,10 @@ static IrInstGen *ir_build_truncate_gen(IrAnalyze *ira, Scope *scope, AstNode *s
17421742 return &instruction->base;
17431743}
17441744
1745static IrInstGen *ir_build_shuffle_vector_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1746 ZigType *result_type, IrInstGen *a, IrInstGen *b, IrInstGen *mask)
1745static Stage1AirInst *ir_build_shuffle_vector_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1746 ZigType *result_type, Stage1AirInst *a, Stage1AirInst *b, Stage1AirInst *mask)
17471747{
1748 IrInstGenShuffleVector *inst = ir_build_inst_gen<IrInstGenShuffleVector>(&ira->new_irb, scope, source_node);
1748 Stage1AirInstShuffleVector *inst = ir_build_inst_gen<Stage1AirInstShuffleVector>(&ira->new_irb, scope, source_node);
17491749 inst->base.value->type = result_type;
17501750 inst->a = a;
17511751 inst->b = b;
......@@ -1758,10 +1758,10 @@ static IrInstGen *ir_build_shuffle_vector_gen(IrAnalyze *ira, Scope *scope, AstN
17581758 return &inst->base;
17591759}
17601760
1761static IrInstGen *ir_build_splat_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1762 IrInstGen *scalar)
1761static Stage1AirInst *ir_build_splat_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type,
1762 Stage1AirInst *scalar)
17631763{
1764 IrInstGenSplat *instruction = ir_build_inst_gen<IrInstGenSplat>(
1764 Stage1AirInstSplat *instruction = ir_build_inst_gen<Stage1AirInstSplat>(
17651765 &ira->new_irb, scope, source_node);
17661766 instruction->base.value->type = result_type;
17671767 instruction->scalar = scalar;
......@@ -1771,8 +1771,8 @@ static IrInstGen *ir_build_splat_gen(IrAnalyze *ira, Scope *scope, AstNode *sour
17711771 return &instruction->base;
17721772}
17731773
1774static IrInstGen *ir_build_bool_not_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) {
1775 IrInstGenBoolNot *instruction = ir_build_inst_gen<IrInstGenBoolNot>(&ira->new_irb,
1774static Stage1AirInst *ir_build_bool_not_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) {
1775 Stage1AirInstBoolNot *instruction = ir_build_inst_gen<Stage1AirInstBoolNot>(&ira->new_irb,
17761776 scope, source_node);
17771777 instruction->base.value->type = ira->codegen->builtin_types.entry_bool;
17781778 instruction->value = value;
......@@ -1782,10 +1782,10 @@ static IrInstGen *ir_build_bool_not_gen(IrAnalyze *ira, Scope *scope, AstNode *s
17821782 return &instruction->base;
17831783}
17841784
1785static IrInstGen *ir_build_memset_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1786 IrInstGen *dest_ptr, IrInstGen *byte, IrInstGen *count)
1785static Stage1AirInst *ir_build_memset_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1786 Stage1AirInst *dest_ptr, Stage1AirInst *byte, Stage1AirInst *count)
17871787{
1788 IrInstGenMemset *instruction = ir_build_inst_void<IrInstGenMemset>(&ira->new_irb,
1788 Stage1AirInstMemset *instruction = ir_build_inst_void<Stage1AirInstMemset>(&ira->new_irb,
17891789 scope, source_node);
17901790 instruction->dest_ptr = dest_ptr;
17911791 instruction->byte = byte;
......@@ -1798,10 +1798,10 @@ static IrInstGen *ir_build_memset_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
17981798 return &instruction->base;
17991799}
18001800
1801static IrInstGen *ir_build_memcpy_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1802 IrInstGen *dest_ptr, IrInstGen *src_ptr, IrInstGen *count)
1801static Stage1AirInst *ir_build_memcpy_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1802 Stage1AirInst *dest_ptr, Stage1AirInst *src_ptr, Stage1AirInst *count)
18031803{
1804 IrInstGenMemcpy *instruction = ir_build_inst_void<IrInstGenMemcpy>(&ira->new_irb,
1804 Stage1AirInstMemcpy *instruction = ir_build_inst_void<Stage1AirInstMemcpy>(&ira->new_irb,
18051805 scope, source_node);
18061806 instruction->dest_ptr = dest_ptr;
18071807 instruction->src_ptr = src_ptr;
......@@ -1814,11 +1814,11 @@ static IrInstGen *ir_build_memcpy_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
18141814 return &instruction->base;
18151815}
18161816
1817static IrInstGen *ir_build_slice_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *slice_type,
1818 IrInstGen *ptr, IrInstGen *start, IrInstGen *end, bool safety_check_on, IrInstGen *result_loc,
1817static Stage1AirInst *ir_build_slice_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *slice_type,
1818 Stage1AirInst *ptr, Stage1AirInst *start, Stage1AirInst *end, bool safety_check_on, Stage1AirInst *result_loc,
18191819 ZigValue *sentinel)
18201820{
1821 IrInstGenSlice *instruction = ir_build_inst_gen<IrInstGenSlice>(
1821 Stage1AirInstSlice *instruction = ir_build_inst_gen<Stage1AirInstSlice>(
18221822 &ira->new_irb, scope, source_node);
18231823 instruction->base.value->type = slice_type;
18241824 instruction->ptr = ptr;
......@@ -1836,33 +1836,33 @@ static IrInstGen *ir_build_slice_gen(IrAnalyze *ira, Scope *scope, AstNode *sour
18361836 return &instruction->base;
18371837}
18381838
1839static IrInstGen *ir_build_breakpoint_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1840 IrInstGenBreakpoint *instruction = ir_build_inst_void<IrInstGenBreakpoint>(&ira->new_irb,
1839static Stage1AirInst *ir_build_breakpoint_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1840 Stage1AirInstBreakpoint *instruction = ir_build_inst_void<Stage1AirInstBreakpoint>(&ira->new_irb,
18411841 scope, source_node);
18421842 return &instruction->base;
18431843}
18441844
1845static IrInstGen *ir_build_return_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1846 IrInstGenReturnAddress *inst = ir_build_inst_gen<IrInstGenReturnAddress>(&ira->new_irb, scope, source_node);
1845static Stage1AirInst *ir_build_return_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1846 Stage1AirInstReturnAddress *inst = ir_build_inst_gen<Stage1AirInstReturnAddress>(&ira->new_irb, scope, source_node);
18471847 inst->base.value->type = ira->codegen->builtin_types.entry_usize;
18481848 return &inst->base;
18491849}
18501850
1851static IrInstGen *ir_build_frame_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1852 IrInstGenFrameAddress *inst = ir_build_inst_gen<IrInstGenFrameAddress>(&ira->new_irb, scope, source_node);
1851static Stage1AirInst *ir_build_frame_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
1852 Stage1AirInstFrameAddress *inst = ir_build_inst_gen<Stage1AirInstFrameAddress>(&ira->new_irb, scope, source_node);
18531853 inst->base.value->type = ira->codegen->builtin_types.entry_usize;
18541854 return &inst->base;
18551855}
18561856
1857static IrInstGen *ir_build_handle_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
1858 IrInstGenFrameHandle *inst = ir_build_inst_gen<IrInstGenFrameHandle>(&ira->new_irb, scope, source_node);
1857static Stage1AirInst *ir_build_handle_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
1858 Stage1AirInstFrameHandle *inst = ir_build_inst_gen<Stage1AirInstFrameHandle>(&ira->new_irb, scope, source_node);
18591859 inst->base.value->type = ty;
18601860 return &inst->base;
18611861}
18621862
1863static IrInstGen *ir_build_frame_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *fn)
1863static Stage1AirInst *ir_build_frame_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *fn)
18641864{
1865 IrInstGenFrameSize *inst = ir_build_inst_gen<IrInstGenFrameSize>(&ira->new_irb, scope, source_node);
1865 Stage1AirInstFrameSize *inst = ir_build_inst_gen<Stage1AirInstFrameSize>(&ira->new_irb, scope, source_node);
18661866 inst->base.value->type = ira->codegen->builtin_types.entry_usize;
18671867 inst->fn = fn;
18681868
......@@ -1871,11 +1871,11 @@ static IrInstGen *ir_build_frame_size_gen(IrAnalyze *ira, Scope *scope, AstNode
18711871 return &inst->base;
18721872}
18731873
1874static IrInstGen *ir_build_overflow_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1875 IrOverflowOp op, IrInstGen *op1, IrInstGen *op2, IrInstGen *result_ptr,
1874static Stage1AirInst *ir_build_overflow_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1875 IrOverflowOp op, Stage1AirInst *op1, Stage1AirInst *op2, Stage1AirInst *result_ptr,
18761876 ZigType *result_ptr_type)
18771877{
1878 IrInstGenOverflowOp *instruction = ir_build_inst_gen<IrInstGenOverflowOp>(&ira->new_irb,
1878 Stage1AirInstOverflowOp *instruction = ir_build_inst_gen<Stage1AirInstOverflowOp>(&ira->new_irb,
18791879 scope, source_node);
18801880 instruction->base.value->type = ira->codegen->builtin_types.entry_bool;
18811881 instruction->op = op;
......@@ -1891,10 +1891,10 @@ static IrInstGen *ir_build_overflow_op_gen(IrAnalyze *ira, Scope *scope, AstNode
18911891 return &instruction->base;
18921892}
18931893
1894static IrInstGen *ir_build_float_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand,
1894static Stage1AirInst *ir_build_float_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand,
18951895 BuiltinFnId fn_id, ZigType *operand_type)
18961896{
1897 IrInstGenFloatOp *instruction = ir_build_inst_gen<IrInstGenFloatOp>(&ira->new_irb,
1897 Stage1AirInstFloatOp *instruction = ir_build_inst_gen<Stage1AirInstFloatOp>(&ira->new_irb,
18981898 scope, source_node);
18991899 instruction->base.value->type = operand_type;
19001900 instruction->operand = operand;
......@@ -1905,10 +1905,10 @@ static IrInstGen *ir_build_float_op_gen(IrAnalyze *ira, Scope *scope, AstNode *s
19051905 return &instruction->base;
19061906}
19071907
1908static IrInstGen *ir_build_mul_add_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *op1, IrInstGen *op2,
1909 IrInstGen *op3, ZigType *expr_type)
1908static Stage1AirInst *ir_build_mul_add_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *op1, Stage1AirInst *op2,
1909 Stage1AirInst *op3, ZigType *expr_type)
19101910{
1911 IrInstGenMulAdd *instruction = ir_build_inst_gen<IrInstGenMulAdd>(&ira->new_irb,
1911 Stage1AirInstMulAdd *instruction = ir_build_inst_gen<Stage1AirInstMulAdd>(&ira->new_irb,
19121912 scope, source_node);
19131913 instruction->base.value->type = expr_type;
19141914 instruction->op1 = op1;
......@@ -1922,8 +1922,8 @@ static IrInstGen *ir_build_mul_add_gen(IrAnalyze *ira, Scope *scope, AstNode *so
19221922 return &instruction->base;
19231923}
19241924
1925static IrInstGen *ir_build_test_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *err_union) {
1926 IrInstGenTestErr *instruction = ir_build_inst_gen<IrInstGenTestErr>(
1925static Stage1AirInst *ir_build_test_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *err_union) {
1926 Stage1AirInstTestErr *instruction = ir_build_inst_gen<Stage1AirInstTestErr>(
19271927 &ira->new_irb, scope, source_node);
19281928 instruction->base.value->type = ira->codegen->builtin_types.entry_bool;
19291929 instruction->err_union = err_union;
......@@ -1933,10 +1933,10 @@ static IrInstGen *ir_build_test_err_gen(IrAnalyze *ira, Scope *scope, AstNode *s
19331933 return &instruction->base;
19341934}
19351935
1936static IrInstGen *ir_build_unwrap_err_code_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1937 IrInstGen *err_union_ptr, ZigType *result_type)
1936static Stage1AirInst *ir_build_unwrap_err_code_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1937 Stage1AirInst *err_union_ptr, ZigType *result_type)
19381938{
1939 IrInstGenUnwrapErrCode *inst = ir_build_inst_gen<IrInstGenUnwrapErrCode>(&ira->new_irb, scope, source_node);
1939 Stage1AirInstUnwrapErrCode *inst = ir_build_inst_gen<Stage1AirInstUnwrapErrCode>(&ira->new_irb, scope, source_node);
19401940 inst->base.value->type = result_type;
19411941 inst->err_union_ptr = err_union_ptr;
19421942
......@@ -1945,10 +1945,10 @@ static IrInstGen *ir_build_unwrap_err_code_gen(IrAnalyze *ira, Scope *scope, Ast
19451945 return &inst->base;
19461946}
19471947
1948static IrInstGen *ir_build_unwrap_err_payload_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1949 IrInstGen *value, bool safety_check_on, bool initializing, ZigType *result_type)
1948static Stage1AirInst *ir_build_unwrap_err_payload_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1949 Stage1AirInst *value, bool safety_check_on, bool initializing, ZigType *result_type)
19501950{
1951 IrInstGenUnwrapErrPayload *inst = ir_build_inst_gen<IrInstGenUnwrapErrPayload>(&ira->new_irb, scope, source_node);
1951 Stage1AirInstUnwrapErrPayload *inst = ir_build_inst_gen<Stage1AirInstUnwrapErrPayload>(&ira->new_irb, scope, source_node);
19521952 inst->base.value->type = result_type;
19531953 inst->value = value;
19541954 inst->safety_check_on = safety_check_on;
......@@ -1959,10 +1959,10 @@ static IrInstGen *ir_build_unwrap_err_payload_gen(IrAnalyze *ira, Scope *scope,
19591959 return &inst->base;
19601960}
19611961
1962static IrInstGen *ir_build_ptr_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1963 ZigType *ptr_type, IrInstGen *ptr, bool safety_check_on)
1962static Stage1AirInst *ir_build_ptr_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1963 ZigType *ptr_type, Stage1AirInst *ptr, bool safety_check_on)
19641964{
1965 IrInstGenPtrCast *instruction = ir_build_inst_gen<IrInstGenPtrCast>(
1965 Stage1AirInstPtrCast *instruction = ir_build_inst_gen<Stage1AirInstPtrCast>(
19661966 &ira->new_irb, scope, source_node);
19671967 instruction->base.value->type = ptr_type;
19681968 instruction->ptr = ptr;
......@@ -1973,10 +1973,10 @@ static IrInstGen *ir_build_ptr_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *s
19731973 return &instruction->base;
19741974}
19751975
1976static IrInstGen *ir_build_bit_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1977 IrInstGen *operand, ZigType *ty)
1976static Stage1AirInst *ir_build_bit_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
1977 Stage1AirInst *operand, ZigType *ty)
19781978{
1979 IrInstGenBitCast *instruction = ir_build_inst_gen<IrInstGenBitCast>(
1979 Stage1AirInstBitCast *instruction = ir_build_inst_gen<Stage1AirInstBitCast>(
19801980 &ira->new_irb, scope, source_node);
19811981 instruction->base.value->type = ty;
19821982 instruction->operand = operand;
......@@ -1986,10 +1986,10 @@ static IrInstGen *ir_build_bit_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *s
19861986 return &instruction->base;
19871987}
19881988
1989static IrInstGen *ir_build_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,
1989static Stage1AirInst *ir_build_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
19901990 ZigType *result_type)
19911991{
1992 IrInstGenWidenOrShorten *inst = ir_build_inst_gen<IrInstGenWidenOrShorten>(&ira->new_irb, scope, source_node);
1992 Stage1AirInstWidenOrShorten *inst = ir_build_inst_gen<Stage1AirInstWidenOrShorten>(&ira->new_irb, scope, source_node);
19931993 inst->base.value->type = result_type;
19941994 inst->target = target;
19951995
......@@ -1998,10 +1998,10 @@ static IrInstGen *ir_build_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNod
19981998 return &inst->base;
19991999}
20002000
2001static IrInstGen *ir_build_int_to_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2002 IrInstGen *target, ZigType *ptr_type)
2001static Stage1AirInst *ir_build_int_to_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2002 Stage1AirInst *target, ZigType *ptr_type)
20032003{
2004 IrInstGenIntToPtr *instruction = ir_build_inst_gen<IrInstGenIntToPtr>(&ira->new_irb, scope, source_node);
2004 Stage1AirInstIntToPtr *instruction = ir_build_inst_gen<Stage1AirInstIntToPtr>(&ira->new_irb, scope, source_node);
20052005 instruction->base.value->type = ptr_type;
20062006 instruction->target = target;
20072007
......@@ -2010,8 +2010,8 @@ static IrInstGen *ir_build_int_to_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode
20102010 return &instruction->base;
20112011}
20122012
2013static IrInstGen *ir_build_ptr_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target) {
2014 IrInstGenPtrToInt *inst = ir_build_inst_gen<IrInstGenPtrToInt>(&ira->new_irb, scope, source_node);
2013static Stage1AirInst *ir_build_ptr_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target) {
2014 Stage1AirInstPtrToInt *inst = ir_build_inst_gen<Stage1AirInstPtrToInt>(&ira->new_irb, scope, source_node);
20152015 inst->base.value->type = ira->codegen->builtin_types.entry_usize;
20162016 inst->target = target;
20172017
......@@ -2020,10 +2020,10 @@ static IrInstGen *ir_build_ptr_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode
20202020 return &inst->base;
20212021}
20222022
2023static IrInstGen *ir_build_int_to_enum_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2024 ZigType *dest_type, IrInstGen *target)
2023static Stage1AirInst *ir_build_int_to_enum_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2024 ZigType *dest_type, Stage1AirInst *target)
20252025{
2026 IrInstGenIntToEnum *instruction = ir_build_inst_gen<IrInstGenIntToEnum>(&ira->new_irb, scope, source_node);
2026 Stage1AirInstIntToEnum *instruction = ir_build_inst_gen<Stage1AirInstIntToEnum>(&ira->new_irb, scope, source_node);
20272027 instruction->base.value->type = dest_type;
20282028 instruction->target = target;
20292029
......@@ -2032,10 +2032,10 @@ static IrInstGen *ir_build_int_to_enum_gen(IrAnalyze *ira, Scope *scope, AstNode
20322032 return &instruction->base;
20332033}
20342034
2035static IrInstGen *ir_build_int_to_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,
2035static Stage1AirInst *ir_build_int_to_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
20362036 ZigType *wanted_type)
20372037{
2038 IrInstGenIntToErr *instruction = ir_build_inst_gen<IrInstGenIntToErr>(&ira->new_irb, scope, source_node);
2038 Stage1AirInstIntToErr *instruction = ir_build_inst_gen<Stage1AirInstIntToErr>(&ira->new_irb, scope, source_node);
20392039 instruction->base.value->type = wanted_type;
20402040 instruction->target = target;
20412041
......@@ -2044,10 +2044,10 @@ static IrInstGen *ir_build_int_to_err_gen(IrAnalyze *ira, Scope *scope, AstNode
20442044 return &instruction->base;
20452045}
20462046
2047static IrInstGen *ir_build_err_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,
2047static Stage1AirInst *ir_build_err_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
20482048 ZigType *wanted_type)
20492049{
2050 IrInstGenErrToInt *instruction = ir_build_inst_gen<IrInstGenErrToInt>(&ira->new_irb, scope, source_node);
2050 Stage1AirInstErrToInt *instruction = ir_build_inst_gen<Stage1AirInstErrToInt>(&ira->new_irb, scope, source_node);
20512051 instruction->base.value->type = wanted_type;
20522052 instruction->target = target;
20532053
......@@ -2056,8 +2056,8 @@ static IrInstGen *ir_build_err_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode
20562056 return &instruction->base;
20572057}
20582058
2059static IrInstGen *ir_build_panic_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *msg) {
2060 IrInstGenPanic *instruction = ir_build_inst_noreturn<IrInstGenPanic>(&ira->new_irb,
2059static Stage1AirInst *ir_build_panic_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *msg) {
2060 Stage1AirInstPanic *instruction = ir_build_inst_noreturn<Stage1AirInstPanic>(&ira->new_irb,
20612061 scope, source_node);
20622062 instruction->msg = msg;
20632063
......@@ -2066,10 +2066,10 @@ static IrInstGen *ir_build_panic_gen(IrAnalyze *ira, Scope *scope, AstNode *sour
20662066 return &instruction->base;
20672067}
20682068
2069static IrInstGen *ir_build_tag_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,
2069static Stage1AirInst *ir_build_tag_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
20702070 ZigType *result_type)
20712071{
2072 IrInstGenTagName *instruction = ir_build_inst_gen<IrInstGenTagName>(&ira->new_irb,
2072 Stage1AirInstTagName *instruction = ir_build_inst_gen<Stage1AirInstTagName>(&ira->new_irb,
20732073 scope, source_node);
20742074 instruction->base.value->type = result_type;
20752075 instruction->target = target;
......@@ -2079,10 +2079,10 @@ static IrInstGen *ir_build_tag_name_gen(IrAnalyze *ira, Scope *scope, AstNode *s
20792079 return &instruction->base;
20802080}
20812081
2082static IrInstGen *ir_build_field_parent_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2083 IrInstGen *field_ptr, TypeStructField *field, ZigType *result_type)
2082static Stage1AirInst *ir_build_field_parent_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2083 Stage1AirInst *field_ptr, TypeStructField *field, ZigType *result_type)
20842084{
2085 IrInstGenFieldParentPtr *inst = ir_build_inst_gen<IrInstGenFieldParentPtr>(&ira->new_irb,
2085 Stage1AirInstFieldParentPtr *inst = ir_build_inst_gen<Stage1AirInstFieldParentPtr>(&ira->new_irb,
20862086 scope, source_node);
20872087 inst->base.value->type = result_type;
20882088 inst->field_ptr = field_ptr;
......@@ -2093,10 +2093,10 @@ static IrInstGen *ir_build_field_parent_ptr_gen(IrAnalyze *ira, Scope *scope, As
20932093 return &inst->base;
20942094}
20952095
2096static IrInstGen *ir_build_align_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,
2096static Stage1AirInst *ir_build_align_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
20972097 ZigType *result_type)
20982098{
2099 IrInstGenAlignCast *instruction = ir_build_inst_gen<IrInstGenAlignCast>(&ira->new_irb, scope, source_node);
2099 Stage1AirInstAlignCast *instruction = ir_build_inst_gen<Stage1AirInstAlignCast>(&ira->new_irb, scope, source_node);
21002100 instruction->base.value->type = result_type;
21012101 instruction->target = target;
21022102
......@@ -2105,20 +2105,20 @@ static IrInstGen *ir_build_align_cast_gen(IrAnalyze *ira, Scope *scope, AstNode
21052105 return &instruction->base;
21062106}
21072107
2108static IrInstGen *ir_build_error_return_trace_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2108static Stage1AirInst *ir_build_error_return_trace_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
21092109 IrInstErrorReturnTraceOptional optional, ZigType *result_type)
21102110{
2111 IrInstGenErrorReturnTrace *inst = ir_build_inst_gen<IrInstGenErrorReturnTrace>(&ira->new_irb, scope, source_node);
2111 Stage1AirInstErrorReturnTrace *inst = ir_build_inst_gen<Stage1AirInstErrorReturnTrace>(&ira->new_irb, scope, source_node);
21122112 inst->base.value->type = result_type;
21132113 inst->optional = optional;
21142114
21152115 return &inst->base;
21162116}
21172117
2118static IrInstGen *ir_build_atomic_rmw_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2119 IrInstGen *ptr, IrInstGen *operand, AtomicRmwOp op, AtomicOrder ordering, ZigType *operand_type)
2118static Stage1AirInst *ir_build_atomic_rmw_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2119 Stage1AirInst *ptr, Stage1AirInst *operand, AtomicRmwOp op, AtomicOrder ordering, ZigType *operand_type)
21202120{
2121 IrInstGenAtomicRmw *instruction = ir_build_inst_gen<IrInstGenAtomicRmw>(&ira->new_irb, scope, source_node);
2121 Stage1AirInstAtomicRmw *instruction = ir_build_inst_gen<Stage1AirInstAtomicRmw>(&ira->new_irb, scope, source_node);
21222122 instruction->base.value->type = operand_type;
21232123 instruction->ptr = ptr;
21242124 instruction->op = op;
......@@ -2131,10 +2131,10 @@ static IrInstGen *ir_build_atomic_rmw_gen(IrAnalyze *ira, Scope *scope, AstNode
21312131 return &instruction->base;
21322132}
21332133
2134static IrInstGen *ir_build_atomic_load_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2135 IrInstGen *ptr, AtomicOrder ordering, ZigType *operand_type)
2134static Stage1AirInst *ir_build_atomic_load_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2135 Stage1AirInst *ptr, AtomicOrder ordering, ZigType *operand_type)
21362136{
2137 IrInstGenAtomicLoad *instruction = ir_build_inst_gen<IrInstGenAtomicLoad>(&ira->new_irb,
2137 Stage1AirInstAtomicLoad *instruction = ir_build_inst_gen<Stage1AirInstAtomicLoad>(&ira->new_irb,
21382138 scope, source_node);
21392139 instruction->base.value->type = operand_type;
21402140 instruction->ptr = ptr;
......@@ -2145,10 +2145,10 @@ static IrInstGen *ir_build_atomic_load_gen(IrAnalyze *ira, Scope *scope, AstNode
21452145 return &instruction->base;
21462146}
21472147
2148static IrInstGen *ir_build_atomic_store_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2149 IrInstGen *ptr, IrInstGen *value, AtomicOrder ordering)
2148static Stage1AirInst *ir_build_atomic_store_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2149 Stage1AirInst *ptr, Stage1AirInst *value, AtomicOrder ordering)
21502150{
2151 IrInstGenAtomicStore *instruction = ir_build_inst_void<IrInstGenAtomicStore>(&ira->new_irb,
2151 Stage1AirInstAtomicStore *instruction = ir_build_inst_void<Stage1AirInstAtomicStore>(&ira->new_irb,
21522152 scope, source_node);
21532153 instruction->ptr = ptr;
21542154 instruction->value = value;
......@@ -2161,10 +2161,10 @@ static IrInstGen *ir_build_atomic_store_gen(IrAnalyze *ira, Scope *scope, AstNod
21612161}
21622162
21632163
2164static IrInstGen *ir_build_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2165 ZigType *result_type, IrInstGen *vector, IrInstGen *result_loc)
2164static Stage1AirInst *ir_build_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2165 ZigType *result_type, Stage1AirInst *vector, Stage1AirInst *result_loc)
21662166{
2167 IrInstGenVectorToArray *instruction = ir_build_inst_gen<IrInstGenVectorToArray>(&ira->new_irb,
2167 Stage1AirInstVectorToArray *instruction = ir_build_inst_gen<Stage1AirInstVectorToArray>(&ira->new_irb,
21682168 scope, source_node);
21692169 instruction->base.value->type = result_type;
21702170 instruction->vector = vector;
......@@ -2176,10 +2176,10 @@ static IrInstGen *ir_build_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode
21762176 return &instruction->base;
21772177}
21782178
2179static IrInstGen *ir_build_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2180 ZigType *result_type, IrInstGen *operand, IrInstGen *result_loc)
2179static Stage1AirInst *ir_build_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2180 ZigType *result_type, Stage1AirInst *operand, Stage1AirInst *result_loc)
21812181{
2182 IrInstGenPtrOfArrayToSlice *instruction = ir_build_inst_gen<IrInstGenPtrOfArrayToSlice>(&ira->new_irb,
2182 Stage1AirInstPtrOfArrayToSlice *instruction = ir_build_inst_gen<Stage1AirInstPtrOfArrayToSlice>(&ira->new_irb,
21832183 scope, source_node);
21842184 instruction->base.value->type = result_type;
21852185 instruction->operand = operand;
......@@ -2191,10 +2191,10 @@ static IrInstGen *ir_build_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, A
21912191 return &instruction->base;
21922192}
21932193
2194static IrInstGen *ir_build_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2195 IrInstGen *array, ZigType *result_type)
2194static Stage1AirInst *ir_build_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2195 Stage1AirInst *array, ZigType *result_type)
21962196{
2197 IrInstGenArrayToVector *instruction = ir_build_inst_gen<IrInstGenArrayToVector>(&ira->new_irb,
2197 Stage1AirInstArrayToVector *instruction = ir_build_inst_gen<Stage1AirInstArrayToVector>(&ira->new_irb,
21982198 scope, source_node);
21992199 instruction->base.value->type = result_type;
22002200 instruction->array = array;
......@@ -2204,10 +2204,10 @@ static IrInstGen *ir_build_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode
22042204 return &instruction->base;
22052205}
22062206
2207static IrInstGen *ir_build_assert_zero(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2208 IrInstGen *target)
2207static Stage1AirInst *ir_build_assert_zero(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2208 Stage1AirInst *target)
22092209{
2210 IrInstGenAssertZero *instruction = ir_build_inst_gen<IrInstGenAssertZero>(&ira->new_irb,
2210 Stage1AirInstAssertZero *instruction = ir_build_inst_gen<Stage1AirInstAssertZero>(&ira->new_irb,
22112211 scope, source_node);
22122212 instruction->base.value->type = ira->codegen->builtin_types.entry_void;
22132213 instruction->target = target;
......@@ -2217,10 +2217,10 @@ static IrInstGen *ir_build_assert_zero(IrAnalyze *ira, Scope *scope, AstNode *so
22172217 return &instruction->base;
22182218}
22192219
2220static IrInstGen *ir_build_assert_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2221 IrInstGen *target)
2220static Stage1AirInst *ir_build_assert_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2221 Stage1AirInst *target)
22222222{
2223 IrInstGenAssertNonNull *instruction = ir_build_inst_gen<IrInstGenAssertNonNull>(&ira->new_irb,
2223 Stage1AirInstAssertNonNull *instruction = ir_build_inst_gen<Stage1AirInstAssertNonNull>(&ira->new_irb,
22242224 scope, source_node);
22252225 instruction->base.value->type = ira->codegen->builtin_types.entry_void;
22262226 instruction->target = target;
......@@ -2230,10 +2230,10 @@ static IrInstGen *ir_build_assert_non_null(IrAnalyze *ira, Scope *scope, AstNode
22302230 return &instruction->base;
22312231}
22322232
2233static IrInstGenAlloca *ir_build_alloca_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2233static Stage1AirInstAlloca *ir_build_alloca_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
22342234 uint32_t align, const char *name_hint)
22352235{
2236 IrInstGenAlloca *instruction = ir_create_inst_gen<IrInstGenAlloca>(&ira->new_irb,
2236 Stage1AirInstAlloca *instruction = ir_create_inst_gen<Stage1AirInstAlloca>(&ira->new_irb,
22372237 scope, source_node);
22382238 instruction->align = align;
22392239 instruction->name_hint = name_hint;
......@@ -2241,8 +2241,8 @@ static IrInstGenAlloca *ir_build_alloca_gen(IrAnalyze *ira, Scope *scope, AstNod
22412241 return instruction;
22422242}
22432243
2244static IrInstGen *ir_build_suspend_finish_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGenSuspendBegin *begin) {
2245 IrInstGenSuspendFinish *inst = ir_build_inst_void<IrInstGenSuspendFinish>(&ira->new_irb,
2244static Stage1AirInst *ir_build_suspend_finish_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInstSuspendBegin *begin) {
2245 Stage1AirInstSuspendFinish *inst = ir_build_inst_void<Stage1AirInstSuspendFinish>(&ira->new_irb,
22462246 scope, source_node);
22472247 inst->begin = begin;
22482248
......@@ -2251,10 +2251,10 @@ static IrInstGen *ir_build_suspend_finish_gen(IrAnalyze *ira, Scope *scope, AstN
22512251 return &inst->base;
22522252}
22532253
2254static IrInstGenAwait *ir_build_await_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2255 IrInstGen *frame, ZigType *result_type, IrInstGen *result_loc, bool is_nosuspend)
2254static Stage1AirInstAwait *ir_build_await_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2255 Stage1AirInst *frame, ZigType *result_type, Stage1AirInst *result_loc, bool is_nosuspend)
22562256{
2257 IrInstGenAwait *instruction = ir_build_inst_gen<IrInstGenAwait>(&ira->new_irb,
2257 Stage1AirInstAwait *instruction = ir_build_inst_gen<Stage1AirInstAwait>(&ira->new_irb,
22582258 scope, source_node);
22592259 instruction->base.value->type = result_type;
22602260 instruction->frame = frame;
......@@ -2267,8 +2267,8 @@ static IrInstGenAwait *ir_build_await_gen(IrAnalyze *ira, Scope *scope, AstNode
22672267 return instruction;
22682268}
22692269
2270static IrInstGen *ir_build_resume_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *frame) {
2271 IrInstGenResume *instruction = ir_build_inst_void<IrInstGenResume>(&ira->new_irb,
2270static Stage1AirInst *ir_build_resume_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *frame) {
2271 Stage1AirInstResume *instruction = ir_build_inst_void<Stage1AirInstResume>(&ira->new_irb,
22722272 scope, source_node);
22732273 instruction->frame = frame;
22742274
......@@ -2277,10 +2277,10 @@ static IrInstGen *ir_build_resume_gen(IrAnalyze *ira, Scope *scope, AstNode *sou
22772277 return &instruction->base;
22782278}
22792279
2280static IrInstGen *ir_build_spill_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand,
2280static Stage1AirInst *ir_build_spill_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand,
22812281 SpillId spill_id)
22822282{
2283 IrInstGenSpillBegin *instruction = ir_build_inst_void<IrInstGenSpillBegin>(&ira->new_irb,
2283 Stage1AirInstSpillBegin *instruction = ir_build_inst_void<Stage1AirInstSpillBegin>(&ira->new_irb,
22842284 scope, source_node);
22852285 instruction->operand = operand;
22862286 instruction->spill_id = spill_id;
......@@ -2290,10 +2290,10 @@ static IrInstGen *ir_build_spill_begin_gen(IrAnalyze *ira, Scope *scope, AstNode
22902290 return &instruction->base;
22912291}
22922292
2293static IrInstGen *ir_build_spill_end_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGenSpillBegin *begin,
2293static Stage1AirInst *ir_build_spill_end_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInstSpillBegin *begin,
22942294 ZigType *result_type)
22952295{
2296 IrInstGenSpillEnd *instruction = ir_build_inst_gen<IrInstGenSpillEnd>(&ira->new_irb,
2296 Stage1AirInstSpillEnd *instruction = ir_build_inst_gen<Stage1AirInstSpillEnd>(&ira->new_irb,
22972297 scope, source_node);
22982298 instruction->base.value->type = result_type;
22992299 instruction->begin = begin;
......@@ -2303,10 +2303,10 @@ static IrInstGen *ir_build_spill_end_gen(IrAnalyze *ira, Scope *scope, AstNode *
23032303 return &instruction->base;
23042304}
23052305
2306static IrInstGen *ir_build_vector_extract_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2307 IrInstGen *vector, IrInstGen *index)
2306static Stage1AirInst *ir_build_vector_extract_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node,
2307 Stage1AirInst *vector, Stage1AirInst *index)
23082308{
2309 IrInstGenVectorExtractElem *instruction = ir_build_inst_gen<IrInstGenVectorExtractElem>(
2309 Stage1AirInstVectorExtractElem *instruction = ir_build_inst_gen<Stage1AirInstVectorExtractElem>(
23102310 &ira->new_irb, scope, source_node);
23112311 instruction->base.value->type = vector->value->type->data.vector.elem_type;
23122312 instruction->vector = vector;
......@@ -2318,8 +2318,8 @@ static IrInstGen *ir_build_vector_extract_elem(IrAnalyze *ira, Scope *scope, Ast
23182318 return &instruction->base;
23192319}
23202320
2321static IrInstGen *ir_build_wasm_memory_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *index) {
2322 IrInstGenWasmMemorySize *instruction = ir_build_inst_gen<IrInstGenWasmMemorySize>(&ira->new_irb,
2321static Stage1AirInst *ir_build_wasm_memory_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *index) {
2322 Stage1AirInstWasmMemorySize *instruction = ir_build_inst_gen<Stage1AirInstWasmMemorySize>(&ira->new_irb,
23232323 scope, source_node);
23242324 instruction->base.value->type = ira->codegen->builtin_types.entry_u32;
23252325 instruction->index = index;
......@@ -2329,8 +2329,8 @@ static IrInstGen *ir_build_wasm_memory_size_gen(IrAnalyze *ira, Scope *scope, As
23292329 return &instruction->base;
23302330}
23312331
2332static IrInstGen *ir_build_wasm_memory_grow_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *index, IrInstGen *delta) {
2333 IrInstGenWasmMemoryGrow *instruction = ir_build_inst_gen<IrInstGenWasmMemoryGrow>(&ira->new_irb,
2332static Stage1AirInst *ir_build_wasm_memory_grow_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *index, Stage1AirInst *delta) {
2333 Stage1AirInstWasmMemoryGrow *instruction = ir_build_inst_gen<Stage1AirInstWasmMemoryGrow>(&ira->new_irb,
23342334 scope, source_node);
23352335 instruction->base.value->type = ira->codegen->builtin_types.entry_i32;
23362336 instruction->index = index;
......@@ -2555,7 +2555,7 @@ static ErrorMsg *opt_ir_add_error_node(IrAnalyze *ira, CodeGen *codegen, AstNode
25552555 return add_node_error(codegen, source_node, msg);
25562556}
25572557
2558static ErrorMsg *ir_add_error(IrAnalyze *ira, IrInstGen *source_instruction, Buf *msg) {
2558static ErrorMsg *ir_add_error(IrAnalyze *ira, Stage1AirInst *source_instruction, Buf *msg) {
25592559 return ir_add_error_node(ira, source_instruction->source_node, msg);
25602560}
25612561
......@@ -2605,17 +2605,17 @@ ZigValue *const_ptr_pointee(IrAnalyze *ira, CodeGen *codegen, ZigValue *const_va
26052605}
26062606
26072607static Error ir_exec_scan_for_side_effects(CodeGen *codegen, Stage1Air *exec) {
2608 IrBasicBlockGen *bb = exec->basic_block_list.at(0);
2608 Stage1AirBasicBlock *bb = exec->basic_block_list.at(0);
26092609 for (size_t i = 0; i < bb->instruction_list.length; i += 1) {
2610 IrInstGen *instruction = bb->instruction_list.at(i);
2611 if (instruction->id == IrInstGenIdReturn) {
2610 Stage1AirInst *instruction = bb->instruction_list.at(i);
2611 if (instruction->id == Stage1AirInstIdReturn) {
26122612 return ErrorNone;
26132613 } else if (ir_inst_gen_has_side_effects(instruction)) {
26142614 if (instr_is_comptime(instruction)) {
26152615 switch (instruction->id) {
2616 case IrInstGenIdUnwrapErrPayload:
2617 case IrInstGenIdOptionalUnwrapPtr:
2618 case IrInstGenIdUnionFieldPtr:
2616 case Stage1AirInstIdUnwrapErrPayload:
2617 case Stage1AirInstIdOptionalUnwrapPtr:
2618 case Stage1AirInstIdUnionFieldPtr:
26192619 continue;
26202620 default:
26212621 break;
......@@ -2633,7 +2633,7 @@ static Error ir_exec_scan_for_side_effects(CodeGen *codegen, Stage1Air *exec) {
26332633 zig_unreachable();
26342634}
26352635
2636static bool ir_emit_global_runtime_side_effect(IrAnalyze *ira, IrInstSrc* source_instruction) {
2636static bool ir_emit_global_runtime_side_effect(IrAnalyze *ira, Stage1ZirInst* source_instruction) {
26372637 if (ir_should_inline(ira->zir, source_instruction->scope)) {
26382638 ir_add_error_node(ira, source_instruction->source_node, buf_sprintf("unable to evaluate constant expression"));
26392639 return false;
......@@ -3423,7 +3423,7 @@ static void value_to_bigfloat(BigFloat *out, ZigValue *val) {
34233423 }
34243424}
34253425
3426static bool ir_num_lit_fits_in_other_type(IrAnalyze *ira, IrInstGen *instruction, ZigType *other_type,
3426static bool ir_num_lit_fits_in_other_type(IrAnalyze *ira, Stage1AirInst *instruction, ZigType *other_type,
34273427 bool explicit_cast)
34283428{
34293429 if (type_is_invalid(other_type)) {
......@@ -4185,11 +4185,11 @@ static void update_errors_helper(CodeGen *g, ErrorTableEntry ***errors, size_t *
41854185}
41864186
41874187static ZigType *ir_resolve_peer_types(IrAnalyze *ira, AstNode *source_node, ZigType *expected_type,
4188 IrInstGen **instructions, size_t instruction_count)
4188 Stage1AirInst **instructions, size_t instruction_count)
41894189{
41904190 Error err;
41914191 assert(instruction_count >= 1);
4192 IrInstGen *prev_inst;
4192 Stage1AirInst *prev_inst;
41934193 size_t i = 0;
41944194 for (;;) {
41954195 prev_inst = instructions[i];
......@@ -4231,7 +4231,7 @@ static ZigType *ir_resolve_peer_types(IrAnalyze *ira, AstNode *source_node, ZigT
42314231 bool make_the_slice_const = false;
42324232 bool make_the_pointer_const = false;
42334233 for (; i < instruction_count; i += 1) {
4234 IrInstGen *cur_inst = instructions[i];
4234 Stage1AirInst *cur_inst = instructions[i];
42354235 ZigType *cur_type = cur_inst->value->type;
42364236 ZigType *prev_type = prev_inst->value->type;
42374237
......@@ -5085,36 +5085,36 @@ static bool eval_const_expr_implicit_cast(IrAnalyze *ira, Scope *scope, AstNode
50855085 return true;
50865086}
50875087
5088static IrInstGen *ir_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
5089 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,
5088static Stage1AirInst *ir_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
5089 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
50905090 scope, source_node);
5091 IrInstGen *new_instruction = &const_instruction->base;
5091 Stage1AirInst *new_instruction = &const_instruction->base;
50925092 new_instruction->value->type = ty;
50935093 new_instruction->value->special = ConstValSpecialStatic;
50945094 ira->new_irb.constants.append(&heap::c_allocator, const_instruction);
50955095 return new_instruction;
50965096}
50975097
5098static IrInstGen *ir_const_noval(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
5099 IrInstGenConst *const_instruction = ir_create_inst_noval<IrInstGenConst>(&ira->new_irb,
5098static Stage1AirInst *ir_const_noval(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
5099 Stage1AirInstConst *const_instruction = ir_create_inst_noval<Stage1AirInstConst>(&ira->new_irb,
51005100 scope, source_node);
51015101 ira->new_irb.constants.append(&heap::c_allocator, const_instruction);
51025102 return &const_instruction->base;
51035103}
51045104
5105// This function initializes the new IrInstGen with the provided ZigValue,
5105// This function initializes the new Stage1AirInst with the provided ZigValue,
51065106// rather than creating a new one.
5107static IrInstGen *ir_const_move(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigValue *val) {
5108 IrInstGen *result = ir_const_noval(ira, scope, source_node);
5107static Stage1AirInst *ir_const_move(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigValue *val) {
5108 Stage1AirInst *result = ir_const_noval(ira, scope, source_node);
51095109 result->value = val;
51105110 return result;
51115111}
51125112
5113static IrInstGen *ir_resolve_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,
5113static Stage1AirInst *ir_resolve_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
51145114 ZigType *wanted_type, CastOp cast_op)
51155115{
51165116 if (instr_is_comptime(value) || !type_has_bits(ira->codegen, wanted_type)) {
5117 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
5117 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
51185118 ZigValue *val = ir_resolve_const(ira, value, UndefBad);
51195119 if (val == nullptr)
51205120 return ira->codegen->invalid_inst_gen;
......@@ -5131,8 +5131,8 @@ static IrInstGen *ir_resolve_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
51315131 }
51325132}
51335133
5134static IrInstGen *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira,
5135 Scope *scope, AstNode *source_node, IrInstGen *value, ZigType *wanted_type)
5134static Stage1AirInst *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira,
5135 Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *wanted_type)
51365136{
51375137 src_assert(value->value->type->id == ZigTypeIdPointer, source_node);
51385138
......@@ -5157,7 +5157,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira,
51575157 if (pointee == nullptr)
51585158 return ira->codegen->invalid_inst_gen;
51595159 if (pointee->special != ConstValSpecialRuntime) {
5160 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
5160 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
51615161 result->value->data.x_ptr.special = ConstPtrSpecialBaseArray;
51625162 result->value->data.x_ptr.mut = val->data.x_ptr.mut;
51635163 result->value->data.x_ptr.data.base_array.array_val = pointee;
......@@ -5170,8 +5170,8 @@ static IrInstGen *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira,
51705170 wanted_type, value, CastOpBitCast);
51715171}
51725172
5173static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5174 IrInstGen *array_ptr, ZigType *wanted_type, ResultLoc *result_loc)
5173static Stage1AirInst *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5174 Stage1AirInst *array_ptr, ZigType *wanted_type, ResultLoc *result_loc)
51755175{
51765176 Error err;
51775177
......@@ -5190,7 +5190,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
51905190 // undef_array->special = ConstValSpecialUndef;
51915191 // undef_array->type = array_type;
51925192
5193 // IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
5193 // Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
51945194 // init_const_slice(ira->codegen, result->value, undef_array, 0, 0, false, nullptr);
51955195 // result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = ConstPtrMutComptimeConst;
51965196 // result->value->type = wanted_type;
......@@ -5217,7 +5217,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
52175217 undef_array->special = ConstValSpecialUndef;
52185218 undef_array->type = array_type;
52195219
5220 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
5220 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
52215221 init_const_slice(ira->codegen, result->value, undef_array, 0, 0, false, nullptr);
52225222 result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = ConstPtrMutComptimeConst;
52235223 result->value->type = wanted_type;
......@@ -5228,7 +5228,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
52285228 if (array_ptr_val->data.x_ptr.special == ConstPtrSpecialSubArray) {
52295229 ZigValue *array_val = array_ptr_val->data.x_ptr.data.base_array.array_val;
52305230 if (array_val->special != ConstValSpecialRuntime) {
5231 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
5231 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
52325232 init_const_slice(ira->codegen, result->value, array_val,
52335233 array_ptr_val->data.x_ptr.data.base_array.elem_index,
52345234 array_type->data.array.len, wanted_const, nullptr);
......@@ -5243,7 +5243,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
52435243 if (pointee->special != ConstValSpecialRuntime) {
52445244 assert(array_ptr_val->type->id == ZigTypeIdPointer);
52455245
5246 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
5246 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
52475247 init_const_slice(ira->codegen, result->value, pointee, 0, array_type->data.array.len, wanted_const, nullptr);
52485248 result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = array_ptr_val->data.x_ptr.mut;
52495249 result->value->type = wanted_type;
......@@ -5253,7 +5253,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
52535253 }
52545254
52555255 if (result_loc == nullptr) result_loc = no_result_loc();
5256 IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr,
5256 Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr,
52575257 result_loc, wanted_type, nullptr, true, true);
52585258 if (type_is_invalid(result_loc_inst->value->type) ||
52595259 result_loc_inst->value->type->id == ZigTypeIdUnreachable)
......@@ -5263,7 +5263,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope,
52635263 return ir_build_ptr_of_array_to_slice(ira, scope, source_node, wanted_type, array_ptr, result_loc_inst);
52645264}
52655265
5266static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, IrInstSrc *ref_old_instruction) {
5266static Stage1AirBasicBlock *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirInst *ref_old_instruction) {
52675267 assert(old_bb);
52685268
52695269 if (old_bb->child) {
......@@ -5272,15 +5272,15 @@ static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_b
52725272 }
52735273 }
52745274
5275 IrBasicBlockGen *new_bb = ir_build_bb_from(ira, old_bb);
5275 Stage1AirBasicBlock *new_bb = ir_build_bb_from(ira, old_bb);
52765276 new_bb->ref_instruction = ref_old_instruction;
52775277
52785278 return new_bb;
52795279}
52805280
5281static IrBasicBlockGen *ir_get_new_bb_runtime(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, IrInstSrc *ref_old_instruction) {
5281static Stage1AirBasicBlock *ir_get_new_bb_runtime(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirInst *ref_old_instruction) {
52825282 assert(ref_old_instruction != nullptr);
5283 IrBasicBlockGen *new_bb = ir_get_new_bb(ira, old_bb, ref_old_instruction);
5283 Stage1AirBasicBlock *new_bb = ir_get_new_bb(ira, old_bb, ref_old_instruction);
52845284 if (new_bb->must_be_comptime_source_node != nullptr) {
52855285 ErrorMsg *msg = ir_add_error_node(ira, ref_old_instruction->source_node,
52865286 buf_sprintf("control flow attempts to use compile-time variable at runtime"));
......@@ -5301,7 +5301,7 @@ static void ir_start_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirBa
53015301 ira->old_bb_index = old_bb->index;
53025302}
53035303
5304static IrInstGen *ira_suspend(IrAnalyze *ira, IrInstSrc *old_instruction, Stage1ZirBasicBlock *next_bb,
5304static Stage1AirInst *ira_suspend(IrAnalyze *ira, Stage1ZirInst *old_instruction, Stage1ZirBasicBlock *next_bb,
53055305 IrSuspendPosition *suspend_pos)
53065306{
53075307 if (ira->codegen->verbose_ir) {
......@@ -5331,7 +5331,7 @@ static IrInstGen *ira_suspend(IrAnalyze *ira, IrInstSrc *old_instruction, Stage1
53315331 return ira->codegen->unreach_instruction;
53325332}
53335333
5334static IrInstGen *ira_resume(IrAnalyze *ira) {
5334static Stage1AirInst *ira_resume(IrAnalyze *ira) {
53355335 IrSuspendPosition pos = ira->resume_stack.pop();
53365336 if (ira->codegen->verbose_ir) {
53375337 fprintf(stderr, "resume (%zu,%zu) ", pos.basic_block_index, pos.instruction_index);
......@@ -5414,7 +5414,7 @@ static void ir_finish_bb(IrAnalyze *ira) {
54145414 ir_start_next_bb(ira);
54155415}
54165416
5417static IrInstGen *ir_unreach_error(IrAnalyze *ira) {
5417static Stage1AirInst *ir_unreach_error(IrAnalyze *ira) {
54185418 ira->old_bb_index = SIZE_MAX;
54195419 if (ira->new_irb.exec->first_err_trace_msg == nullptr) {
54205420 ira->new_irb.exec->first_err_trace_msg = ira->codegen->trace_err;
......@@ -5441,7 +5441,7 @@ static bool ir_emit_backward_branch(IrAnalyze *ira, AstNode* source_node) {
54415441 return true;
54425442}
54435443
5444static IrInstGen *ir_inline_bb(IrAnalyze *ira, AstNode* source_node, Stage1ZirBasicBlock *old_bb) {
5444static Stage1AirInst *ir_inline_bb(IrAnalyze *ira, AstNode* source_node, Stage1ZirBasicBlock *old_bb) {
54455445 if (old_bb->debug_id <= ira->zir_current_basic_block->debug_id) {
54465446 if (!ir_emit_backward_branch(ira, source_node))
54475447 return ir_unreach_error(ira);
......@@ -5452,14 +5452,14 @@ static IrInstGen *ir_inline_bb(IrAnalyze *ira, AstNode* source_node, Stage1ZirBa
54525452 return ira->codegen->unreach_instruction;
54535453}
54545454
5455static IrInstGen *ir_finish_anal(IrAnalyze *ira, IrInstGen *instruction) {
5455static Stage1AirInst *ir_finish_anal(IrAnalyze *ira, Stage1AirInst *instruction) {
54565456 if (instruction->value->type->id == ZigTypeIdUnreachable)
54575457 ir_finish_bb(ira);
54585458 return instruction;
54595459}
54605460
5461static IrInstGen *ir_const_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry) {
5462 IrInstGen *result = ir_const(ira, scope, source_node, fn_entry->type_entry);
5461static Stage1AirInst *ir_const_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry) {
5462 Stage1AirInst *result = ir_const(ira, scope, source_node, fn_entry->type_entry);
54635463 result->value->special = ConstValSpecialStatic;
54645464 result->value->data.x_ptr.data.fn.fn_entry = fn_entry;
54655465 result->value->data.x_ptr.mut = ConstPtrMutComptimeConst;
......@@ -5467,62 +5467,62 @@ static IrInstGen *ir_const_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node
54675467 return result;
54685468}
54695469
5470static IrInstGen *ir_const_bound_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5471 ZigFn *fn_entry, IrInstGen *first_arg, AstNode *first_arg_src)
5470static Stage1AirInst *ir_const_bound_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5471 ZigFn *fn_entry, Stage1AirInst *first_arg, AstNode *first_arg_src)
54725472{
54735473 // This is unfortunately required to avoid improperly freeing first_arg_src
54745474 ira_ref(ira);
54755475
5476 IrInstGen *result = ir_const(ira, scope, source_node, get_bound_fn_type(ira->codegen, fn_entry));
5476 Stage1AirInst *result = ir_const(ira, scope, source_node, get_bound_fn_type(ira->codegen, fn_entry));
54775477 result->value->data.x_bound_fn.fn = fn_entry;
54785478 result->value->data.x_bound_fn.first_arg = first_arg;
54795479 result->value->data.x_bound_fn.first_arg_src = first_arg_src;
54805480 return result;
54815481}
54825482
5483static IrInstGen *ir_const_type(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
5484 IrInstGen *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_type);
5483static Stage1AirInst *ir_const_type(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
5484 Stage1AirInst *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_type);
54855485 result->value->data.x_type = ty;
54865486 return result;
54875487}
54885488
5489static IrInstGen *ir_const_bool(IrAnalyze *ira, Scope *scope, AstNode *source_node, bool value) {
5490 IrInstGen *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_bool);
5489static Stage1AirInst *ir_const_bool(IrAnalyze *ira, Scope *scope, AstNode *source_node, bool value) {
5490 Stage1AirInst *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_bool);
54915491 result->value->data.x_bool = value;
54925492 return result;
54935493}
54945494
5495static IrInstGen *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
5496 IrInstGen *result = ir_const(ira, scope, source_node, ty);
5495static Stage1AirInst *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) {
5496 Stage1AirInst *result = ir_const(ira, scope, source_node, ty);
54975497 result->value->special = ConstValSpecialUndef;
54985498 return result;
54995499}
55005500
5501static IrInstGen *ir_const_unreachable(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
5502 IrInstGen *result = ir_const_noval(ira, scope, source_node);
5501static Stage1AirInst *ir_const_unreachable(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
5502 Stage1AirInst *result = ir_const_noval(ira, scope, source_node);
55035503 result->value = ira->codegen->intern.for_unreachable();
55045504 return result;
55055505}
55065506
5507static IrInstGen *ir_const_void(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
5508 IrInstGen *result = ir_const_noval(ira, scope, source_node);
5507static Stage1AirInst *ir_const_void(IrAnalyze *ira, Scope *scope, AstNode *source_node) {
5508 Stage1AirInst *result = ir_const_noval(ira, scope, source_node);
55095509 result->value = ira->codegen->intern.for_void();
55105510 return result;
55115511}
55125512
5513static IrInstGen *ir_const_unsigned(IrAnalyze *ira, Scope *scope, AstNode *source_node, uint64_t value) {
5514 IrInstGen *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_num_lit_int);
5513static Stage1AirInst *ir_const_unsigned(IrAnalyze *ira, Scope *scope, AstNode *source_node, uint64_t value) {
5514 Stage1AirInst *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_num_lit_int);
55155515 bigint_init_unsigned(&result->value->data.x_bigint, value);
55165516 return result;
55175517}
55185518
5519static IrInstGen *ir_get_const_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5519static Stage1AirInst *ir_get_const_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
55205520 ZigValue *pointee, ZigType *pointee_type,
55215521 ConstPtrMut ptr_mut, bool ptr_is_const, bool ptr_is_volatile, uint32_t ptr_align)
55225522{
55235523 ZigType *ptr_type = get_pointer_to_type_extra(ira->codegen, pointee_type,
55245524 ptr_is_const, ptr_is_volatile, PtrLenSingle, ptr_align, 0, 0, false);
5525 IrInstGen *const_instr = ir_const(ira, scope, source_node, ptr_type);
5525 Stage1AirInst *const_instr = ir_const(ira, scope, source_node, ptr_type);
55265526 ZigValue *const_val = const_instr->value;
55275527 const_val->data.x_ptr.special = ConstPtrSpecialRef;
55285528 const_val->data.x_ptr.mut = ptr_mut;
......@@ -5564,7 +5564,7 @@ static Error ir_resolve_const_val(CodeGen *codegen, Stage1Air *exec, AstNode *so
55645564 }
55655565}
55665566
5567static ZigValue *ir_resolve_const(IrAnalyze *ira, IrInstGen *value, UndefAllowed undef_allowed) {
5567static ZigValue *ir_resolve_const(IrAnalyze *ira, Stage1AirInst *value, UndefAllowed undef_allowed) {
55685568 Error err;
55695569 if ((err = ir_resolve_const_val(ira->codegen, ira->new_irb.exec, value->source_node,
55705570 value->value, undef_allowed)))
......@@ -5640,7 +5640,7 @@ Error ir_eval_const_value(CodeGen *codegen, Scope *scope, AstNode *node,
56405640 return ErrorNone;
56415641}
56425642
5643static ErrorTableEntry *ir_resolve_error(IrAnalyze *ira, IrInstGen *err_value) {
5643static ErrorTableEntry *ir_resolve_error(IrAnalyze *ira, Stage1AirInst *err_value) {
56445644 if (type_is_invalid(err_value->value->type))
56455645 return nullptr;
56465646
......@@ -5669,7 +5669,7 @@ static ZigType *ir_resolve_const_type(CodeGen *codegen, Stage1Air *exec, AstNode
56695669 return val->data.x_type;
56705670}
56715671
5672static ZigValue *ir_resolve_type_lazy(IrAnalyze *ira, IrInstGen *type_value) {
5672static ZigValue *ir_resolve_type_lazy(IrAnalyze *ira, Stage1AirInst *type_value) {
56735673 if (type_is_invalid(type_value->value->type))
56745674 return nullptr;
56755675
......@@ -5689,7 +5689,7 @@ static ZigValue *ir_resolve_type_lazy(IrAnalyze *ira, IrInstGen *type_value) {
56895689 return type_value->value;
56905690}
56915691
5692static ZigType *ir_resolve_type(IrAnalyze *ira, IrInstGen *type_value) {
5692static ZigType *ir_resolve_type(IrAnalyze *ira, Stage1AirInst *type_value) {
56935693 ZigValue *val = ir_resolve_type_lazy(ira, type_value);
56945694 if (val == nullptr)
56955695 return ira->codegen->builtin_types.entry_invalid;
......@@ -5711,7 +5711,7 @@ static Error ir_validate_vector_elem_type(IrAnalyze *ira, AstNode *source_node,
57115711 return ErrorNone;
57125712}
57135713
5714static ZigType *ir_resolve_vector_elem_type(IrAnalyze *ira, IrInstGen *elem_type_value) {
5714static ZigType *ir_resolve_vector_elem_type(IrAnalyze *ira, Stage1AirInst *elem_type_value) {
57155715 Error err;
57165716 ZigType *elem_type = ir_resolve_type(ira, elem_type_value);
57175717 if (type_is_invalid(elem_type))
......@@ -5721,7 +5721,7 @@ static ZigType *ir_resolve_vector_elem_type(IrAnalyze *ira, IrInstGen *elem_type
57215721 return elem_type;
57225722}
57235723
5724static ZigType *ir_resolve_int_type(IrAnalyze *ira, IrInstGen *type_value) {
5724static ZigType *ir_resolve_int_type(IrAnalyze *ira, Stage1AirInst *type_value) {
57255725 ZigType *ty = ir_resolve_type(ira, type_value);
57265726 if (type_is_invalid(ty))
57275727 return ira->codegen->builtin_types.entry_invalid;
......@@ -5742,7 +5742,7 @@ static ZigType *ir_resolve_int_type(IrAnalyze *ira, IrInstGen *type_value) {
57425742 return ty;
57435743}
57445744
5745static ZigType *ir_resolve_error_set_type(IrAnalyze *ira, AstNode *op_source, IrInstGen *type_value) {
5745static ZigType *ir_resolve_error_set_type(IrAnalyze *ira, AstNode *op_source, Stage1AirInst *type_value) {
57465746 if (type_is_invalid(type_value->value->type))
57475747 return ira->codegen->builtin_types.entry_invalid;
57485748
......@@ -5770,7 +5770,7 @@ static ZigType *ir_resolve_error_set_type(IrAnalyze *ira, AstNode *op_source, Ir
57705770 return result_type;
57715771}
57725772
5773static ZigFn *ir_resolve_fn(IrAnalyze *ira, IrInstGen *fn_value) {
5773static ZigFn *ir_resolve_fn(IrAnalyze *ira, Stage1AirInst *fn_value) {
57745774 if (type_is_invalid(fn_value->value->type))
57755775 return nullptr;
57765776
......@@ -5791,14 +5791,14 @@ static ZigFn *ir_resolve_fn(IrAnalyze *ira, IrInstGen *fn_value) {
57915791 return const_val->data.x_ptr.data.fn.fn_entry;
57925792}
57935793
5794static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5795 IrInstGen *value, ZigType *wanted_type, ResultLoc *result_loc)
5794static Stage1AirInst *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5795 Stage1AirInst *value, ZigType *wanted_type, ResultLoc *result_loc)
57965796{
57975797 assert(wanted_type->id == ZigTypeIdOptional);
57985798
57995799 if (instr_is_comptime(value)) {
58005800 ZigType *payload_type = wanted_type->data.maybe.child_type;
5801 IrInstGen *casted_payload = ir_implicit_cast(ira, value, payload_type);
5801 Stage1AirInst *casted_payload = ir_implicit_cast(ira, value, payload_type);
58025802 if (type_is_invalid(casted_payload->value->type))
58035803 return ira->codegen->invalid_inst_gen;
58045804
......@@ -5806,7 +5806,7 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode
58065806 if (!val)
58075807 return ira->codegen->invalid_inst_gen;
58085808
5809 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,
5809 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
58105810 scope, source_node);
58115811 const_instruction->base.value->special = ConstValSpecialStatic;
58125812 if (types_have_same_zig_comptime_repr(ira->codegen, wanted_type, payload_type)) {
......@@ -5821,7 +5821,7 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode
58215821 if (result_loc == nullptr && handle_is_ptr(ira->codegen, wanted_type)) {
58225822 result_loc = no_result_loc();
58235823 }
5824 IrInstGen *result_loc_inst = nullptr;
5824 Stage1AirInst *result_loc_inst = nullptr;
58255825 if (result_loc != nullptr) {
58265826 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true);
58275827 if (type_is_invalid(result_loc_inst->value->type) ||
......@@ -5830,20 +5830,20 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode
58305830 return result_loc_inst;
58315831 }
58325832 }
5833 IrInstGen *result = ir_build_optional_wrap(ira, scope, source_node, wanted_type, value, result_loc_inst);
5833 Stage1AirInst *result = ir_build_optional_wrap(ira, scope, source_node, wanted_type, value, result_loc_inst);
58345834 result->value->data.rh_maybe = RuntimeHintOptionalNonNull;
58355835 return result;
58365836}
58375837
5838static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5839 IrInstGen *value, ZigType *wanted_type, ResultLoc *result_loc)
5838static Stage1AirInst *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5839 Stage1AirInst *value, ZigType *wanted_type, ResultLoc *result_loc)
58405840{
58415841 assert(wanted_type->id == ZigTypeIdErrorUnion);
58425842
58435843 ZigType *payload_type = wanted_type->data.error_union.payload_type;
58445844 ZigType *err_set_type = wanted_type->data.error_union.err_set_type;
58455845 if (instr_is_comptime(value)) {
5846 IrInstGen *casted_payload = ir_implicit_cast(ira, value, payload_type);
5846 Stage1AirInst *casted_payload = ir_implicit_cast(ira, value, payload_type);
58475847 if (type_is_invalid(casted_payload->value->type))
58485848 return ira->codegen->invalid_inst_gen;
58495849
......@@ -5856,7 +5856,7 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN
58565856 err_set_val->special = ConstValSpecialStatic;
58575857 err_set_val->data.x_err_set = nullptr;
58585858
5859 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,
5859 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
58605860 scope, source_node);
58615861 const_instruction->base.value->type = wanted_type;
58625862 const_instruction->base.value->special = ConstValSpecialStatic;
......@@ -5865,7 +5865,7 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN
58655865 return &const_instruction->base;
58665866 }
58675867
5868 IrInstGen *result_loc_inst;
5868 Stage1AirInst *result_loc_inst;
58695869 if (handle_is_ptr(ira->codegen, wanted_type)) {
58705870 if (result_loc == nullptr) result_loc = no_result_loc();
58715871 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true);
......@@ -5877,12 +5877,12 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN
58775877 result_loc_inst = nullptr;
58785878 }
58795879
5880 IrInstGen *result = ir_build_err_wrap_payload(ira, scope, source_node, wanted_type, value, result_loc_inst);
5880 Stage1AirInst *result = ir_build_err_wrap_payload(ira, scope, source_node, wanted_type, value, result_loc_inst);
58815881 result->value->data.rh_error_union = RuntimeHintErrorUnionNonError;
58825882 return result;
58835883}
58845884
5885static IrInstGen *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,
5885static Stage1AirInst *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
58865886 ZigType *wanted_type)
58875887{
58885888 assert(value->value->type->id == ZigTypeIdErrorSet);
......@@ -5912,7 +5912,7 @@ static IrInstGen *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode
59125912 }
59135913 }
59145914
5915 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,
5915 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
59165916 scope, source_node);
59175917 const_instruction->base.value->type = wanted_type;
59185918 const_instruction->base.value->special = ConstValSpecialStatic;
......@@ -5923,8 +5923,8 @@ static IrInstGen *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode
59235923 return ir_build_cast(ira, scope, source_node, wanted_type, value, CastOpErrSet);
59245924}
59255925
5926static IrInstGen *ir_analyze_frame_ptr_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5927 IrInstGen *frame_ptr, ZigType *wanted_type)
5926static Stage1AirInst *ir_analyze_frame_ptr_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5927 Stage1AirInst *frame_ptr, ZigType *wanted_type)
59285928{
59295929 if (instr_is_comptime(frame_ptr)) {
59305930 ZigValue *ptr_val = ir_resolve_const(ira, frame_ptr, UndefBad);
......@@ -5940,8 +5940,8 @@ static IrInstGen *ir_analyze_frame_ptr_to_anyframe(IrAnalyze *ira, Scope *scope,
59405940 return ir_build_cast(ira, scope, source_node, wanted_type, frame_ptr, CastOpBitCast);
59415941}
59425942
5943static IrInstGen *ir_analyze_anyframe_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5944 IrInstGen *value, ZigType *wanted_type)
5943static Stage1AirInst *ir_analyze_anyframe_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node,
5944 Stage1AirInst *value, ZigType *wanted_type)
59455945{
59465946 if (instr_is_comptime(value)) {
59475947 zig_panic("TODO comptime anyframe->T to anyframe");
......@@ -5951,12 +5951,12 @@ static IrInstGen *ir_analyze_anyframe_to_anyframe(IrAnalyze *ira, Scope *scope,
59515951}
59525952
59535953
5954static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,
5954static Stage1AirInst *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
59555955 ZigType *wanted_type, ResultLoc *result_loc)
59565956{
59575957 assert(wanted_type->id == ZigTypeIdErrorUnion);
59585958
5959 IrInstGen *casted_value = ir_implicit_cast(ira, value, wanted_type->data.error_union.err_set_type);
5959 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, wanted_type->data.error_union.err_set_type);
59605960
59615961 if (instr_is_comptime(casted_value)) {
59625962 ZigValue *val = ir_resolve_const(ira, casted_value, UndefBad);
......@@ -5968,7 +5968,7 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode
59685968 err_set_val->type = wanted_type->data.error_union.err_set_type;
59695969 err_set_val->data.x_err_set = val->data.x_err_set;
59705970
5971 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,
5971 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
59725972 scope, source_node);
59735973 const_instruction->base.value->type = wanted_type;
59745974 const_instruction->base.value->special = ConstValSpecialStatic;
......@@ -5977,7 +5977,7 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode
59775977 return &const_instruction->base;
59785978 }
59795979
5980 IrInstGen *result_loc_inst;
5980 Stage1AirInst *result_loc_inst;
59815981 if (handle_is_ptr(ira->codegen, wanted_type)) {
59825982 if (result_loc == nullptr) result_loc = no_result_loc();
59835983 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true);
......@@ -5991,19 +5991,19 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode
59915991 }
59925992
59935993
5994 IrInstGen *result = ir_build_err_wrap_code(ira, scope, source_node, wanted_type, value, result_loc_inst);
5994 Stage1AirInst *result = ir_build_err_wrap_code(ira, scope, source_node, wanted_type, value, result_loc_inst);
59955995 result->value->data.rh_error_union = RuntimeHintErrorUnionError;
59965996 return result;
59975997}
59985998
5999static IrInstGen *ir_analyze_null_to_maybe(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, ZigType *wanted_type) {
5999static Stage1AirInst *ir_analyze_null_to_maybe(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *wanted_type) {
60006000 assert(wanted_type->id == ZigTypeIdOptional);
60016001 assert(instr_is_comptime(value));
60026002
60036003 ZigValue *val = ir_resolve_const(ira, value, UndefBad);
60046004 assert(val != nullptr);
60056005
6006 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6006 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
60076007 result->value->special = ConstValSpecialStatic;
60086008
60096009 if (get_src_ptr_type(wanted_type) != nullptr) {
......@@ -6016,8 +6016,8 @@ static IrInstGen *ir_analyze_null_to_maybe(IrAnalyze *ira, Scope *scope, AstNode
60166016 return result;
60176017}
60186018
6019static IrInstGen *ir_analyze_null_to_c_pointer(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6020 IrInstGen *value, ZigType *wanted_type)
6019static Stage1AirInst *ir_analyze_null_to_c_pointer(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6020 Stage1AirInst *value, ZigType *wanted_type)
60216021{
60226022 assert(wanted_type->id == ZigTypeIdPointer);
60236023 assert(wanted_type->data.pointer.ptr_len == PtrLenC);
......@@ -6026,13 +6026,13 @@ static IrInstGen *ir_analyze_null_to_c_pointer(IrAnalyze *ira, Scope *scope, Ast
60266026 ZigValue *val = ir_resolve_const(ira, value, UndefBad);
60276027 assert(val != nullptr);
60286028
6029 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6029 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
60306030 result->value->data.x_ptr.special = ConstPtrSpecialNull;
60316031 result->value->data.x_ptr.mut = ConstPtrMutComptimeConst;
60326032 return result;
60336033}
60346034
6035static IrInstGen *ir_get_ref2(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,
6035static Stage1AirInst *ir_get_ref2(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
60366036 ZigType *elem_type, bool is_const, bool is_volatile)
60376037{
60386038 Error err;
......@@ -6054,19 +6054,19 @@ static IrInstGen *ir_get_ref2(IrAnalyze *ira, Scope *scope, AstNode *source_node
60546054 if ((err = type_resolve(ira->codegen, ptr_type, ResolveStatusZeroBitsKnown)))
60556055 return ira->codegen->invalid_inst_gen;
60566056
6057 IrInstGen *result_loc;
6057 Stage1AirInst *result_loc;
60586058 if (type_has_bits(ira->codegen, ptr_type) && !handle_is_ptr(ira->codegen, elem_type)) {
60596059 result_loc = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), elem_type, nullptr, true, true);
60606060 } else {
60616061 result_loc = nullptr;
60626062 }
60636063
6064 IrInstGen *new_instruction = ir_build_ref_gen(ira, scope, source_node, ptr_type, value, result_loc);
6064 Stage1AirInst *new_instruction = ir_build_ref_gen(ira, scope, source_node, ptr_type, value, result_loc);
60656065 new_instruction->value->data.rh_ptr = RuntimeHintPtrStack;
60666066 return new_instruction;
60676067}
60686068
6069static IrInstGen *ir_get_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,
6069static Stage1AirInst *ir_get_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
60706070 bool is_const, bool is_volatile)
60716071{
60726072 return ir_get_ref2(ira, scope, source_node, value, value->value->type, is_const, is_volatile);
......@@ -6103,10 +6103,10 @@ static bool can_fold_enum_type(ZigType *ty) {
61036103 (tag_int_type->id == ZigTypeIdInt && tag_int_type->data.integral.bit_count == 0);
61046104}
61056105
6106static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target) {
6106static Stage1AirInst *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target) {
61076107 Error err;
61086108
6109 IrInstGen *enum_target;
6109 Stage1AirInst *enum_target;
61106110 ZigType *enum_type;
61116111 if (target->value->type->id == ZigTypeIdUnion) {
61126112 enum_type = ir_resolve_union_tag_type(ira, target->source_node, target->value->type);
......@@ -6132,7 +6132,7 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *
61326132
61336133 // If there is only one possible tag, then we know at comptime what it is.
61346134 if (can_fold_enum_type(enum_type)) {
6135 IrInstGen *result = ir_const(ira, scope, source_node, tag_type);
6135 Stage1AirInst *result = ir_const(ira, scope, source_node, tag_type);
61366136 init_const_bigint(result->value, tag_type,
61376137 &enum_type->data.enumeration.fields[0].value);
61386138 return result;
......@@ -6142,7 +6142,7 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *
61426142 ZigValue *val = ir_resolve_const(ira, enum_target, UndefBad);
61436143 if (!val)
61446144 return ira->codegen->invalid_inst_gen;
6145 IrInstGen *result = ir_const(ira, scope, source_node, tag_type);
6145 Stage1AirInst *result = ir_const(ira, scope, source_node, tag_type);
61466146 init_const_bigint(result->value, tag_type, &val->data.x_enum_tag);
61476147 return result;
61486148 }
......@@ -6150,8 +6150,8 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *
61506150 return ir_build_widen_or_shorten(ira, scope, source_node, enum_target, tag_type);
61516151}
61526152
6153static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6154 IrInstGen *target, ZigType *wanted_type)
6153static Stage1AirInst *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6154 Stage1AirInst *target, ZigType *wanted_type)
61556155{
61566156 assert(target->value->type->id == ZigTypeIdUnion);
61576157 assert(wanted_type->id == ZigTypeIdEnum);
......@@ -6161,7 +6161,7 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode
61616161 ZigValue *val = ir_resolve_const(ira, target, UndefBad);
61626162 if (!val)
61636163 return ira->codegen->invalid_inst_gen;
6164 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6164 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
61656165 result->value->special = ConstValSpecialStatic;
61666166 result->value->type = wanted_type;
61676167 bigint_init_bigint(&result->value->data.x_enum_tag, &val->data.x_union.tag);
......@@ -6170,7 +6170,7 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode
61706170
61716171 // If there is only 1 possible tag, then we know at comptime what it is.
61726172 if (can_fold_enum_type(wanted_type)) {
6173 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6173 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
61746174 result->value->special = ConstValSpecialStatic;
61756175 result->value->type = wanted_type;
61766176 TypeEnumField *enum_field = target->value->type->data.unionation.fields[0].enum_field;
......@@ -6181,16 +6181,16 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode
61816181 return ir_build_union_tag(ira, scope, source_node, target, wanted_type);
61826182}
61836183
6184static IrInstGen *ir_analyze_undefined_to_anything(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6185 IrInstGen *target, ZigType *wanted_type)
6184static Stage1AirInst *ir_analyze_undefined_to_anything(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6185 Stage1AirInst *target, ZigType *wanted_type)
61866186{
6187 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6187 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
61886188 result->value->special = ConstValSpecialUndef;
61896189 return result;
61906190}
61916191
6192static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6193 IrInstGen *uncasted_target, ZigType *wanted_type)
6192static Stage1AirInst *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6193 Stage1AirInst *uncasted_target, ZigType *wanted_type)
61946194{
61956195 Error err;
61966196 assert(wanted_type->id == ZigTypeIdUnion);
......@@ -6198,7 +6198,7 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode
61986198 if ((err = type_resolve(ira->codegen, wanted_type, ResolveStatusZeroBitsKnown)))
61996199 return ira->codegen->invalid_inst_gen;
62006200
6201 IrInstGen *target = ir_implicit_cast(ira, uncasted_target, wanted_type->data.unionation.tag_type);
6201 Stage1AirInst *target = ir_implicit_cast(ira, uncasted_target, wanted_type->data.unionation.tag_type);
62026202 if (type_is_invalid(target->value->type))
62036203 return ira->codegen->invalid_inst_gen;
62046204
......@@ -6240,7 +6240,7 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode
62406240 break;
62416241 }
62426242
6243 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6243 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
62446244 result->value->special = ConstValSpecialStatic;
62456245 result->value->type = wanted_type;
62466246 bigint_init_bigint(&result->value->data.x_union.tag, &val->data.x_enum_tag);
......@@ -6287,8 +6287,8 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode
62876287
62886288static bool value_numeric_fits_in_type(ZigValue *value, ZigType *type_entry);
62896289
6290static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6291 IrInstGen *target, ZigType *wanted_type)
6290static Stage1AirInst *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6291 Stage1AirInst *target, ZigType *wanted_type)
62926292{
62936293 ZigType *wanted_scalar_type = (target->value->type->id == ZigTypeIdVector) ?
62946294 wanted_type->data.vector.elem_type : wanted_type;
......@@ -6314,7 +6314,7 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN
63146314 }
63156315 }
63166316
6317 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6317 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
63186318 result->value->type = wanted_type;
63196319
63206320 if (wanted_type->id == ZigTypeIdVector) {
......@@ -6351,7 +6351,7 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN
63516351 assert(wanted_type->id == ZigTypeIdInt);
63526352 assert(type_has_bits(ira->codegen, target->value->type));
63536353 ir_build_assert_zero(ira, scope, source_node, target);
6354 IrInstGen *result = ir_const_unsigned(ira, scope, source_node, 0);
6354 Stage1AirInst *result = ir_const_unsigned(ira, scope, source_node, 0);
63556355 result->value->type = wanted_type;
63566356 return result;
63576357 }
......@@ -6359,8 +6359,8 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN
63596359 return ir_build_widen_or_shorten(ira, scope, source_node, target, wanted_type);
63606360}
63616361
6362static IrInstGen *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6363 IrInstGen *target, ZigType *wanted_type)
6362static Stage1AirInst *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6363 Stage1AirInst *target, ZigType *wanted_type)
63646364{
63656365 Error err;
63666366 assert(wanted_type->id == ZigTypeIdEnum);
......@@ -6397,7 +6397,7 @@ static IrInstGen *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *
63976397 return ira->codegen->invalid_inst_gen;
63986398 }
63996399
6400 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6400 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
64016401 bigint_init_bigint(&result->value->data.x_enum_tag, &val->data.x_bigint);
64026402 return result;
64036403 }
......@@ -6405,14 +6405,14 @@ static IrInstGen *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *
64056405 return ir_build_int_to_enum_gen(ira, scope, source_node, wanted_type, target);
64066406}
64076407
6408static IrInstGen *ir_analyze_number_to_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6409 IrInstGen *target, ZigType *wanted_type)
6408static Stage1AirInst *ir_analyze_number_to_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6409 Stage1AirInst *target, ZigType *wanted_type)
64106410{
64116411 ZigValue *val = ir_resolve_const(ira, target, UndefBad);
64126412 if (!val)
64136413 return ira->codegen->invalid_inst_gen;
64146414
6415 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6415 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
64166416 if (wanted_type->id == ZigTypeIdComptimeFloat) {
64176417 float_init_float(result->value, val);
64186418 } else if (wanted_type->id == ZigTypeIdComptimeInt) {
......@@ -6423,7 +6423,7 @@ static IrInstGen *ir_analyze_number_to_literal(IrAnalyze *ira, Scope *scope, Ast
64236423 return result;
64246424}
64256425
6426static IrInstGen *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,
6426static Stage1AirInst *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
64276427 ZigType *wanted_type)
64286428{
64296429 assert(target->value->type->id == ZigTypeIdInt);
......@@ -6435,7 +6435,7 @@ static IrInstGen *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *s
64356435 if (!val)
64366436 return ira->codegen->invalid_inst_gen;
64376437
6438 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6438 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
64396439
64406440 if (!resolve_inferred_error_set(ira->codegen, wanted_type, source_node)) {
64416441 return ira->codegen->invalid_inst_gen;
......@@ -6485,7 +6485,7 @@ static IrInstGen *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *s
64856485 return ir_build_int_to_err_gen(ira, scope, source_node, target, wanted_type);
64866486}
64876487
6488static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,
6488static Stage1AirInst *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
64896489 ZigType *wanted_type)
64906490{
64916491 assert(wanted_type->id == ZigTypeIdInt);
......@@ -6497,7 +6497,7 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s
64976497 if (!val)
64986498 return ira->codegen->invalid_inst_gen;
64996499
6500 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6500 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
65016501
65026502 ErrorTableEntry *err;
65036503 if (err_type->id == ZigTypeIdErrorUnion) {
......@@ -6536,11 +6536,11 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s
65366536 return ira->codegen->invalid_inst_gen;
65376537 }
65386538 if (err_set_type->data.error_set.err_count == 0) {
6539 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6539 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
65406540 bigint_init_unsigned(&result->value->data.x_bigint, 0);
65416541 return result;
65426542 } else if (err_set_type->data.error_set.err_count == 1) {
6543 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
6543 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
65446544 ErrorTableEntry *err = err_set_type->data.error_set.errors[0];
65456545 bigint_init_unsigned(&result->value->data.x_bigint, err->value);
65466546 return result;
......@@ -6558,7 +6558,7 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s
65586558 return ir_build_err_to_int_gen(ira, scope, source_node, target, wanted_type);
65596559}
65606560
6561static IrInstGen *ir_analyze_ptr_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,
6561static Stage1AirInst *ir_analyze_ptr_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
65626562 ZigType *wanted_type)
65636563{
65646564 assert(wanted_type->id == ZigTypeIdPointer);
......@@ -6589,7 +6589,7 @@ static IrInstGen *ir_analyze_ptr_to_array(IrAnalyze *ira, Scope *scope, AstNode
65896589 array_val->parent.id = ConstParentIdScalar;
65906590 array_val->parent.data.p_scalar.scalar_val = pointee;
65916591
6592 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,
6592 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
65936593 scope, source_node);
65946594 const_instruction->base.value->type = wanted_type;
65956595 const_instruction->base.value->special = ConstValSpecialStatic;
......@@ -6798,12 +6798,12 @@ static void report_recursive_error(IrAnalyze *ira, AstNode *source_node, ConstCa
67986798 }
67996799}
68006800
6801static IrInstGen *ir_analyze_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6802 IrInstGen *array, ZigType *vector_type)
6801static Stage1AirInst *ir_analyze_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6802 Stage1AirInst *array, ZigType *vector_type)
68036803{
68046804 if (instr_is_comptime(array)) {
68056805 // arrays and vectors have the same ZigValue representation
6806 IrInstGen *result = ir_const(ira, scope, source_node, vector_type);
6806 Stage1AirInst *result = ir_const(ira, scope, source_node, vector_type);
68076807 copy_const_val(ira->codegen, result->value, array->value);
68086808 result->value->type = vector_type;
68096809 return result;
......@@ -6811,12 +6811,12 @@ static IrInstGen *ir_analyze_array_to_vector(IrAnalyze *ira, Scope *scope, AstNo
68116811 return ir_build_array_to_vector(ira, scope, source_node, array, vector_type);
68126812}
68136813
6814static IrInstGen *ir_analyze_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6815 IrInstGen *vector, ZigType *array_type, ResultLoc *result_loc)
6814static Stage1AirInst *ir_analyze_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6815 Stage1AirInst *vector, ZigType *array_type, ResultLoc *result_loc)
68166816{
68176817 if (instr_is_comptime(vector)) {
68186818 // arrays and vectors have the same ZigValue representation
6819 IrInstGen *result = ir_const(ira, scope, source_node, array_type);
6819 Stage1AirInst *result = ir_const(ira, scope, source_node, array_type);
68206820 copy_const_val(ira->codegen, result->value, vector->value);
68216821 result->value->type = array_type;
68226822 return result;
......@@ -6824,17 +6824,17 @@ static IrInstGen *ir_analyze_vector_to_array(IrAnalyze *ira, Scope *scope, AstNo
68246824 if (result_loc == nullptr) {
68256825 result_loc = no_result_loc();
68266826 }
6827 IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, array_type, nullptr, true, true);
6827 Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, array_type, nullptr, true, true);
68286828 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {
68296829 return result_loc_inst;
68306830 }
68316831 return ir_build_vector_to_array(ira, scope, source_node, array_type, vector, result_loc_inst);
68326832}
68336833
6834static IrInstGen *ir_analyze_int_to_c_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6835 IrInstGen *integer, ZigType *dest_type)
6834static Stage1AirInst *ir_analyze_int_to_c_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6835 Stage1AirInst *integer, ZigType *dest_type)
68366836{
6837 IrInstGen *unsigned_integer;
6837 Stage1AirInst *unsigned_integer;
68386838 if (instr_is_comptime(integer)) {
68396839 unsigned_integer = integer;
68406840 } else {
......@@ -6875,7 +6875,7 @@ static bool is_pointery_and_elem_is_not_pointery(ZigType *ty) {
68756875 return false;
68766876}
68776877
6878static IrInstGen *ir_analyze_enum_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,
6878static Stage1AirInst *ir_analyze_enum_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
68796879 ZigType *enum_type)
68806880{
68816881 assert(enum_type->id == ZigTypeIdEnum);
......@@ -6892,14 +6892,14 @@ static IrInstGen *ir_analyze_enum_literal(IrAnalyze *ira, Scope *scope, AstNode
68926892 buf_sprintf("'%s' declared here", buf_ptr(&enum_type->name)));
68936893 return ira->codegen->invalid_inst_gen;
68946894 }
6895 IrInstGen *result = ir_const(ira, scope, source_node, enum_type);
6895 Stage1AirInst *result = ir_const(ira, scope, source_node, enum_type);
68966896 bigint_init_bigint(&result->value->data.x_enum_tag, &field->value);
68976897
68986898 return result;
68996899}
69006900
6901static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6902 IrInstGen *struct_ptr, ZigType *actual_type, ZigType *wanted_type)
6901static Stage1AirInst *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6902 Stage1AirInst *struct_ptr, ZigType *actual_type, ZigType *wanted_type)
69036903{
69046904 Error err;
69056905
......@@ -6918,20 +6918,20 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop
69186918
69196919 // Determine if the struct_operand will be comptime.
69206920 ZigValue *elem_values = heap::c_allocator.allocate<ZigValue>(array_len);
6921 IrInstGen **casted_fields = heap::c_allocator.allocate<IrInstGen *>(array_len);
6922 IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type);
6921 Stage1AirInst **casted_fields = heap::c_allocator.allocate<Stage1AirInst *>(array_len);
6922 Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type);
69236923
69246924 for (size_t i = 0; i < array_len; i += 1) {
69256925 TypeStructField *src_field = actual_type->data.structure.fields[i];
69266926
6927 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr,
6927 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr,
69286928 actual_type, false);
69296929 if (type_is_invalid(field_ptr->value->type))
69306930 return ira->codegen->invalid_inst_gen;
6931 IrInstGen *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);
6931 Stage1AirInst *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);
69326932 if (type_is_invalid(field_value->value->type))
69336933 return ira->codegen->invalid_inst_gen;
6934 IrInstGen *casted_value = ir_implicit_cast(ira, field_value, elem_type);
6934 Stage1AirInst *casted_value = ir_implicit_cast(ira, field_value, elem_type);
69356935 if (type_is_invalid(casted_value->value->type))
69366936 return ira->codegen->invalid_inst_gen;
69376937
......@@ -6954,13 +6954,13 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop
69546954 }
69556955
69566956 if (is_comptime) {
6957 IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type);
6957 Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type);
69586958 const_result->value->data.x_array.special = ConstArraySpecialNone;
69596959 const_result->value->data.x_array.data.s_none.elements = elem_values;
69606960 return const_result;
69616961 }
69626962
6963 IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
6963 Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
69646964 wanted_type, nullptr, true, true);
69656965 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {
69666966 return ira->codegen->invalid_inst_gen;
......@@ -6968,12 +6968,12 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop
69686968
69696969 ZigType *elem_type_ptr = get_pointer_to_type(ira->codegen, elem_type, false);
69706970 for (size_t i = 0; i < array_len; i += 1) {
6971 IrInstGen *index_val = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_usize);
6971 Stage1AirInst *index_val = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_usize);
69726972 bigint_init_unsigned(&index_val->value->data.x_bigint, i);
69736973
6974 IrInstGen *elem_ptr = ir_build_elem_ptr_gen(ira, scope, source_node,
6974 Stage1AirInst *elem_ptr = ir_build_elem_ptr_gen(ira, scope, source_node,
69756975 result_loc_inst, index_val, false, elem_type_ptr);
6976 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, elem_ptr, casted_fields[i], true);
6976 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, elem_ptr, casted_fields[i], true);
69776977 if (type_is_invalid(store_ptr_inst->value->type))
69786978 return ira->codegen->invalid_inst_gen;
69796979 }
......@@ -6984,8 +6984,8 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop
69846984 return result_loc_inst;
69856985}
69866986
6987static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6988 IrInstGen *struct_ptr, ZigType *actual_type, ZigType *wanted_type)
6987static Stage1AirInst *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *scope, AstNode *source_node,
6988 Stage1AirInst *struct_ptr, ZigType *actual_type, ZigType *wanted_type)
69896989{
69906990 Error err;
69916991
......@@ -7008,8 +7008,8 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco
70087008 // Also emit compile errors for missing fields and duplicate fields.
70097009 AstNode **field_assign_nodes = heap::c_allocator.allocate<AstNode *>(actual_field_count);
70107010 ZigValue **field_values = heap::c_allocator.allocate<ZigValue *>(actual_field_count);
7011 IrInstGen **casted_fields = heap::c_allocator.allocate<IrInstGen *>(actual_field_count);
7012 IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type);
7011 Stage1AirInst **casted_fields = heap::c_allocator.allocate<Stage1AirInst *>(actual_field_count);
7012 Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type);
70137013
70147014 for (size_t i = 0; i < instr_field_count; i += 1) {
70157015 TypeStructField *src_field = actual_type->data.structure.fields[i];
......@@ -7046,14 +7046,14 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco
70467046 }
70477047 field_assign_nodes[dst_field->src_index] = src_field->decl_node;
70487048
7049 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr,
7049 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr,
70507050 actual_type, false);
70517051 if (type_is_invalid(field_ptr->value->type))
70527052 return ira->codegen->invalid_inst_gen;
7053 IrInstGen *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);
7053 Stage1AirInst *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);
70547054 if (type_is_invalid(field_value->value->type))
70557055 return ira->codegen->invalid_inst_gen;
7056 IrInstGen *casted_value = ir_implicit_cast(ira, field_value, dst_field->type_entry);
7056 Stage1AirInst *casted_value = ir_implicit_cast(ira, field_value, dst_field->type_entry);
70577057 if (type_is_invalid(casted_value->value->type))
70587058 return ira->codegen->invalid_inst_gen;
70597059
......@@ -7103,12 +7103,12 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco
71037103
71047104 if (is_comptime) {
71057105 heap::c_allocator.deallocate(field_assign_nodes, actual_field_count);
7106 IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type);
7106 Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type);
71077107 const_result->value->data.x_struct.fields = field_values;
71087108 return const_result;
71097109 }
71107110
7111 IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
7111 Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
71127112 wanted_type, nullptr, true, true);
71137113 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {
71147114 return ira->codegen->invalid_inst_gen;
......@@ -7119,10 +7119,10 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco
71197119 if (field->is_comptime)
71207120 continue;
71217121
7122 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc_inst, wanted_type, true);
7122 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc_inst, wanted_type, true);
71237123 if (type_is_invalid(field_ptr->value->type))
71247124 return ira->codegen->invalid_inst_gen;
7125 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, field_ptr, casted_fields[i], true);
7125 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, field_ptr, casted_fields[i], true);
71267126 if (type_is_invalid(store_ptr_inst->value->type))
71277127 return ira->codegen->invalid_inst_gen;
71287128 }
......@@ -7134,8 +7134,8 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco
71347134 return result_loc_inst;
71357135}
71367136
7137static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7138 IrInstGen *struct_ptr, ZigType *struct_type, ZigType *union_type)
7137static Stage1AirInst *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7138 Stage1AirInst *struct_ptr, ZigType *struct_type, ZigType *union_type)
71397139{
71407140 Error err;
71417141
......@@ -7160,15 +7160,15 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop
71607160 if (payload_type == nullptr)
71617161 return ira->codegen->invalid_inst_gen;
71627162
7163 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, only_field, struct_ptr,
7163 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, only_field, struct_ptr,
71647164 struct_type, false);
71657165 if (type_is_invalid(field_ptr->value->type))
71667166 return ira->codegen->invalid_inst_gen;
7167 IrInstGen *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);
7167 Stage1AirInst *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr);
71687168 if (type_is_invalid(field_value->value->type))
71697169 return ira->codegen->invalid_inst_gen;
71707170
7171 IrInstGen *casted_value = ir_implicit_cast(ira, field_value, payload_type);
7171 Stage1AirInst *casted_value = ir_implicit_cast(ira, field_value, payload_type);
71727172 if (type_is_invalid(casted_value->value->type))
71737173 return ira->codegen->invalid_inst_gen;
71747174
......@@ -7177,7 +7177,7 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop
71777177 if (val == nullptr)
71787178 return ira->codegen->invalid_inst_gen;
71797179
7180 IrInstGen *result = ir_const(ira, scope, source_node, union_type);
7180 Stage1AirInst *result = ir_const(ira, scope, source_node, union_type);
71817181 bigint_init_bigint(&result->value->data.x_union.tag, &union_field->enum_field->value);
71827182 result->value->data.x_union.payload = val;
71837183
......@@ -7187,18 +7187,18 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop
71877187 return result;
71887188 }
71897189
7190 IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
7190 Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
71917191 union_type, nullptr, true, true);
71927192 if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) {
71937193 return ira->codegen->invalid_inst_gen;
71947194 }
71957195
7196 IrInstGen *payload_ptr = ir_analyze_container_field_ptr(ira, only_field->name,
7196 Stage1AirInst *payload_ptr = ir_analyze_container_field_ptr(ira, only_field->name,
71977197 scope, source_node, result_loc_inst, source_node, union_type, true);
71987198 if (type_is_invalid(payload_ptr->value->type))
71997199 return ira->codegen->invalid_inst_gen;
72007200
7201 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, payload_ptr, casted_value, false);
7201 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, payload_ptr, casted_value, false);
72027202 if (type_is_invalid(store_ptr_inst->value->type))
72037203 return ira->codegen->invalid_inst_gen;
72047204
......@@ -7243,30 +7243,30 @@ static Error ir_cast_ptr_align(IrAnalyze *ira, Scope *scope, AstNode *source_nod
72437243 return ErrorNone;
72447244}
72457245
7246static IrInstGen *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7247 IrInstGen *struct_operand, TypeStructField *field)
7246static Stage1AirInst *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7247 Stage1AirInst *struct_operand, TypeStructField *field)
72487248{
7249 IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, struct_operand, true, false);
7249 Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, struct_operand, true, false);
72507250 if (type_is_invalid(struct_ptr->value->type))
72517251 return ira->codegen->invalid_inst_gen;
7252 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, struct_ptr,
7252 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, struct_ptr,
72537253 struct_operand->value->type, false);
72547254 if (type_is_invalid(field_ptr->value->type))
72557255 return ira->codegen->invalid_inst_gen;
72567256 return ir_get_deref(ira, scope, source_node, field_ptr, nullptr);
72577257}
72587258
7259static IrInstGen *ir_analyze_optional_value_payload_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7260 IrInstGen *optional_operand, bool safety_check_on)
7259static Stage1AirInst *ir_analyze_optional_value_payload_value(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7260 Stage1AirInst *optional_operand, bool safety_check_on)
72617261{
7262 IrInstGen *opt_ptr = ir_get_ref(ira, scope, source_node, optional_operand, true, false);
7263 IrInstGen *payload_ptr = ir_analyze_unwrap_optional_payload(ira, scope, source_node, opt_ptr,
7262 Stage1AirInst *opt_ptr = ir_get_ref(ira, scope, source_node, optional_operand, true, false);
7263 Stage1AirInst *payload_ptr = ir_analyze_unwrap_optional_payload(ira, scope, source_node, opt_ptr,
72647264 safety_check_on, false);
72657265 return ir_get_deref(ira, scope, source_node, payload_ptr, nullptr);
72667266}
72677267
7268static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7269 ZigType *wanted_type, IrInstGen *value)
7268static Stage1AirInst *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7269 ZigType *wanted_type, Stage1AirInst *value)
72707270{
72717271 Error err;
72727272 ZigType *actual_type = value->value->type;
......@@ -7336,7 +7336,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
73367336 actual_type->data.pointer.child_type->data.array.child_type, source_node,
73377337 !wanted_child_type->data.pointer.is_const).id == ConstCastResultIdOk)
73387338 {
7339 IrInstGen *cast1 = ir_resolve_ptr_of_array_to_unknown_len_ptr(ira, scope, source_node, value,
7339 Stage1AirInst *cast1 = ir_resolve_ptr_of_array_to_unknown_len_ptr(ira, scope, source_node, value,
73407340 wanted_child_type);
73417341 if (type_is_invalid(cast1->value->type))
73427342 return ira->codegen->invalid_inst_gen;
......@@ -7373,11 +7373,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
73737373 actual_type->id == ZigTypeIdComptimeInt ||
73747374 actual_type->id == ZigTypeIdComptimeFloat)
73757375 {
7376 IrInstGen *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.error_union.payload_type, value);
7376 Stage1AirInst *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.error_union.payload_type, value);
73777377 if (type_is_invalid(cast1->value->type))
73787378 return ira->codegen->invalid_inst_gen;
73797379
7380 IrInstGen *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);
7380 Stage1AirInst *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);
73817381 if (type_is_invalid(cast2->value->type))
73827382 return ira->codegen->invalid_inst_gen;
73837383
......@@ -7394,13 +7394,13 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
73947394 wanted_type->id == ZigTypeIdFloat || wanted_type->id == ZigTypeIdComptimeFloat))
73957395 {
73967396 if (value->value->special == ConstValSpecialUndef) {
7397 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
7397 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
73987398 result->value->special = ConstValSpecialUndef;
73997399 return result;
74007400 }
74017401 if (ir_num_lit_fits_in_other_type(ira, value, wanted_type, true)) {
74027402 if (wanted_type->id == ZigTypeIdComptimeInt || wanted_type->id == ZigTypeIdInt) {
7403 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
7403 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
74047404 if (actual_type->id == ZigTypeIdComptimeInt || actual_type->id == ZigTypeIdInt) {
74057405 copy_const_val(ira->codegen, result->value, value->value);
74067406 result->value->type = wanted_type;
......@@ -7409,7 +7409,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
74097409 }
74107410 return result;
74117411 } else if (wanted_type->id == ZigTypeIdComptimeFloat || wanted_type->id == ZigTypeIdFloat) {
7412 IrInstGen *result = ir_const(ira, scope, source_node, wanted_type);
7412 Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type);
74137413 if (actual_type->id == ZigTypeIdComptimeInt || actual_type->id == ZigTypeIdInt) {
74147414 BigFloat bf;
74157415 bigfloat_init_bigint(&bf, &value->value->data.x_bigint);
......@@ -7457,11 +7457,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
74577457 actual_type->data.pointer.ptr_len == PtrLenSingle &&
74587458 actual_type->data.pointer.child_type->id == ZigTypeIdArray)
74597459 {
7460 IrInstGen *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.maybe.child_type, value);
7460 Stage1AirInst *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.maybe.child_type, value);
74617461 if (type_is_invalid(cast1->value->type))
74627462 return ira->codegen->invalid_inst_gen;
74637463
7464 IrInstGen *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);
7464 Stage1AirInst *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);
74657465 if (type_is_invalid(cast2->value->type))
74667466 return ira->codegen->invalid_inst_gen;
74677467
......@@ -7543,11 +7543,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
75437543 }
75447544 if (ok_align) {
75457545 if (wanted_type->id == ZigTypeIdErrorUnion) {
7546 IrInstGen *cast1 = ir_analyze_cast(ira, scope, source_node, slice_type, value);
7546 Stage1AirInst *cast1 = ir_analyze_cast(ira, scope, source_node, slice_type, value);
75477547 if (type_is_invalid(cast1->value->type))
75487548 return ira->codegen->invalid_inst_gen;
75497549
7550 IrInstGen *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);
7550 Stage1AirInst *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);
75517551 if (type_is_invalid(cast2->value->type))
75527552 return ira->codegen->invalid_inst_gen;
75537553
......@@ -7623,7 +7623,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
76237623 }
76247624 }
76257625 if (ok) {
7626 IrInstGen *cast1 = ir_analyze_frame_ptr_to_anyframe(ira, scope, source_node, value, anyframe_type);
7626 Stage1AirInst *cast1 = ir_analyze_frame_ptr_to_anyframe(ira, scope, source_node, value, anyframe_type);
76277627 if (anyframe_type == wanted_type)
76287628 return cast1;
76297629 return ir_analyze_cast(ira, scope, source_node, wanted_type, cast1);
......@@ -7678,7 +7678,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
76787678 if (actual_type->id == ZigTypeIdEnumLiteral &&
76797679 (wanted_type->id == ZigTypeIdOptional && wanted_type->data.maybe.child_type->id == ZigTypeIdEnum))
76807680 {
7681 IrInstGen *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.maybe.child_type);
7681 Stage1AirInst *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.maybe.child_type);
76827682 if (type_is_invalid(result->value->type))
76837683 return result;
76847684
......@@ -7689,7 +7689,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
76897689 if (actual_type->id == ZigTypeIdEnumLiteral &&
76907690 (wanted_type->id == ZigTypeIdErrorUnion && wanted_type->data.error_union.payload_type->id == ZigTypeIdEnum))
76917691 {
7692 IrInstGen *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.error_union.payload_type);
7692 Stage1AirInst *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.error_union.payload_type);
76937693 if (type_is_invalid(result->value->type))
76947694 return result;
76957695
......@@ -7751,7 +7751,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
77517751 slice_ptr_type->data.pointer.sentinel))))
77527752 {
77537753 TypeStructField *ptr_field = actual_type->data.structure.fields[slice_ptr_index];
7754 IrInstGen *slice_ptr = ir_analyze_struct_value_field_value(ira, scope, source_node, value, ptr_field);
7754 Stage1AirInst *slice_ptr = ir_analyze_struct_value_field_value(ira, scope, source_node, value, ptr_field);
77557755 return ir_implicit_cast2(ira, scope, source_node, slice_ptr, wanted_type);
77567756 }
77577757 }
......@@ -7835,31 +7835,31 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
78357835 if (wanted_type->id == ZigTypeIdArray && (is_array_init || field_count == 0) &&
78367836 wanted_type->data.array.len == field_count)
78377837 {
7838 IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);
7838 Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);
78397839 if (type_is_invalid(struct_ptr->value->type))
78407840 return ira->codegen->invalid_inst_gen;
78417841
7842 IrInstGen *ptr = ir_analyze_struct_literal_to_array(ira, scope, source_node, struct_ptr, actual_type, wanted_type);
7842 Stage1AirInst *ptr = ir_analyze_struct_literal_to_array(ira, scope, source_node, struct_ptr, actual_type, wanted_type);
78437843 if (ptr->value->type->id != ZigTypeIdPointer)
78447844 return ptr;
78457845 return ir_get_deref(ira, scope, source_node, ptr, nullptr);
78467846 } else if (wanted_type->id == ZigTypeIdStruct && !is_slice(wanted_type) &&
78477847 (!is_array_init || field_count == 0))
78487848 {
7849 IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);
7849 Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);
78507850 if (type_is_invalid(struct_ptr->value->type))
78517851 return ira->codegen->invalid_inst_gen;
78527852
7853 IrInstGen *ptr = ir_analyze_struct_literal_to_struct(ira, scope, source_node, struct_ptr, actual_type, wanted_type);
7853 Stage1AirInst *ptr = ir_analyze_struct_literal_to_struct(ira, scope, source_node, struct_ptr, actual_type, wanted_type);
78547854 if (ptr->value->type->id != ZigTypeIdPointer)
78557855 return ptr;
78567856 return ir_get_deref(ira, scope, source_node, ptr, nullptr);
78577857 } else if (wanted_type->id == ZigTypeIdUnion && !is_array_init && field_count == 1) {
7858 IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);
7858 Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false);
78597859 if (type_is_invalid(struct_ptr->value->type))
78607860 return ira->codegen->invalid_inst_gen;
78617861
7862 IrInstGen *ptr = ir_analyze_struct_literal_to_union(ira, scope, source_node, struct_ptr, actual_type, wanted_type);
7862 Stage1AirInst *ptr = ir_analyze_struct_literal_to_union(ira, scope, source_node, struct_ptr, actual_type, wanted_type);
78637863 if (ptr->value->type->id != ZigTypeIdPointer)
78647864 return ptr;
78657865 return ir_get_deref(ira, scope, source_node, ptr, nullptr);
......@@ -7881,19 +7881,19 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
78817881 if (wanted_child->id == ZigTypeIdArray && (is_array_init || field_count == 0) &&
78827882 wanted_child->data.array.len == field_count && (const_ok || field_count == 0))
78837883 {
7884 IrInstGen *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, wanted_child);
7884 Stage1AirInst *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, wanted_child);
78857885 if (res->value->type->id == ZigTypeIdPointer)
78867886 return res;
78877887 return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile);
78887888 } else if (wanted_child->id == ZigTypeIdStruct && !is_slice(wanted_type) &&
78897889 (!is_array_init || field_count == 0) && const_ok)
78907890 {
7891 IrInstGen *res = ir_analyze_struct_literal_to_struct(ira, scope, source_node, value, anon_type, wanted_child);
7891 Stage1AirInst *res = ir_analyze_struct_literal_to_struct(ira, scope, source_node, value, anon_type, wanted_child);
78927892 if (res->value->type->id == ZigTypeIdPointer)
78937893 return res;
78947894 return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile);
78957895 } else if (wanted_child->id == ZigTypeIdUnion && !is_array_init && field_count == 1 && const_ok) {
7896 IrInstGen *res = ir_analyze_struct_literal_to_union(ira, scope, source_node, value, anon_type, wanted_child);
7896 Stage1AirInst *res = ir_analyze_struct_literal_to_union(ira, scope, source_node, value, anon_type, wanted_child);
78977897 if (res->value->type->id == ZigTypeIdPointer)
78987898 return res;
78997899 return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile);
......@@ -7905,7 +7905,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
79057905 {
79067906 ZigType *slice_child_type = slice_type->data.pointer.child_type;
79077907 ZigType *slice_array_type = get_array_type(ira->codegen, slice_child_type, field_count, nullptr);
7908 IrInstGen *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, slice_array_type);
7908 Stage1AirInst *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, slice_array_type);
79097909 if (type_is_invalid(res->value->type))
79107910 return ira->codegen->invalid_inst_gen;
79117911 if (res->value->type->id != ZigTypeIdPointer)
......@@ -7923,7 +7923,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
79237923
79247924 // T to ?U, where T implicitly casts to U
79257925 if (wanted_type->id == ZigTypeIdOptional && actual_type->id != ZigTypeIdOptional) {
7926 IrInstGen *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.maybe.child_type);
7926 Stage1AirInst *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.maybe.child_type);
79277927 if (type_is_invalid(cast1->value->type))
79287928 return ira->codegen->invalid_inst_gen;
79297929 return ir_implicit_cast2(ira, scope, source_node, cast1, wanted_type);
......@@ -7933,7 +7933,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
79337933 if (wanted_type->id == ZigTypeIdErrorUnion && actual_type->id != ZigTypeIdErrorUnion &&
79347934 actual_type->id != ZigTypeIdErrorSet)
79357935 {
7936 IrInstGen *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.error_union.payload_type);
7936 Stage1AirInst *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.error_union.payload_type);
79377937 if (type_is_invalid(cast1->value->type))
79387938 return ira->codegen->invalid_inst_gen;
79397939 return ir_implicit_cast2(ira, scope, source_node, cast1, wanted_type);
......@@ -7947,8 +7947,8 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_
79477947 return ira->codegen->invalid_inst_gen;
79487948}
79497949
7950static IrInstGen *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7951 IrInstGen *value, ZigType *expected_type)
7950static Stage1AirInst *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node,
7951 Stage1AirInst *value, ZigType *expected_type)
79527952{
79537953 assert(value);
79547954 assert(!expected_type || !type_is_invalid(expected_type));
......@@ -7964,11 +7964,11 @@ static IrInstGen *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *sourc
79647964 return ir_analyze_cast(ira, scope, source_node, expected_type, value);
79657965}
79667966
7967static IrInstGen *ir_implicit_cast(IrAnalyze *ira, IrInstGen *value, ZigType *expected_type) {
7967static Stage1AirInst *ir_implicit_cast(IrAnalyze *ira, Stage1AirInst *value, ZigType *expected_type) {
79687968 return ir_implicit_cast2(ira, value->scope, value->source_node, value, expected_type);
79697969}
79707970
7971static ZigType *get_ptr_elem_type(CodeGen *g, IrInstGen *ptr) {
7971static ZigType *get_ptr_elem_type(CodeGen *g, Stage1AirInst *ptr) {
79727972 ir_assert(ptr->value->type->id == ZigTypeIdPointer, ptr);
79737973 ZigType *elem_type = ptr->value->type->data.pointer.child_type;
79747974 if (elem_type != g->builtin_types.entry_anytype)
......@@ -7982,7 +7982,7 @@ static ZigType *get_ptr_elem_type(CodeGen *g, IrInstGen *ptr) {
79827982 return pointee->type;
79837983}
79847984
7985static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *ptr,
7985static Stage1AirInst *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *ptr,
79867986 ResultLoc *result_loc)
79877987{
79887988 Error err;
......@@ -8027,7 +8027,7 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod
80278027 child_type = pointee->type;
80288028 }
80298029 if (pointee->special != ConstValSpecialRuntime) {
8030 IrInstGen *result = ir_const(ira, scope, source_node, child_type);
8030 Stage1AirInst *result = ir_const(ira, scope, source_node, child_type);
80318031
80328032 if ((err = ir_read_const_ptr(ira, ira->codegen, source_node, result->value,
80338033 ptr->value)))
......@@ -8041,25 +8041,25 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod
80418041 }
80428042
80438043 // if the instruction is a const ref instruction we can skip it
8044 if (ptr->id == IrInstGenIdRef) {
8045 IrInstGenRef *ref_inst = reinterpret_cast<IrInstGenRef *>(ptr);
8044 if (ptr->id == Stage1AirInstIdRef) {
8045 Stage1AirInstRef *ref_inst = reinterpret_cast<Stage1AirInstRef *>(ptr);
80468046 return ref_inst->operand;
80478047 }
80488048
80498049 // If the instruction is a element pointer instruction to a vector, we emit
80508050 // vector element extract instruction rather than load pointer. If the
80518051 // pointer type has non-VECTOR_INDEX_RUNTIME value, it would have been
8052 // possible to implement this in the codegen for IrInstGenLoadPtr.
8052 // possible to implement this in the codegen for Stage1AirInstLoadPtr.
80538053 // However if it has VECTOR_INDEX_RUNTIME then we must emit a compile error
80548054 // if the vector index cannot be determined right here, right now, because
80558055 // the type information does not contain enough information to actually
80568056 // perform a dereference.
80578057 if (ptr_type->data.pointer.vector_index == VECTOR_INDEX_RUNTIME) {
8058 if (ptr->id == IrInstGenIdElemPtr) {
8059 IrInstGenElemPtr *elem_ptr = (IrInstGenElemPtr *)ptr;
8060 IrInstGen *vector_loaded = ir_get_deref(ira, elem_ptr->array_ptr->scope,
8058 if (ptr->id == Stage1AirInstIdElemPtr) {
8059 Stage1AirInstElemPtr *elem_ptr = (Stage1AirInstElemPtr *)ptr;
8060 Stage1AirInst *vector_loaded = ir_get_deref(ira, elem_ptr->array_ptr->scope,
80618061 elem_ptr->array_ptr->source_node, elem_ptr->array_ptr, nullptr);
8062 IrInstGen *elem_index = elem_ptr->elem_index;
8062 Stage1AirInst *elem_index = elem_ptr->elem_index;
80638063 return ir_build_vector_extract_elem(ira, scope, source_node, vector_loaded, elem_index);
80648064 }
80658065 ir_add_error(ira, ptr,
......@@ -8067,7 +8067,7 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod
80678067 return ira->codegen->invalid_inst_gen;
80688068 }
80698069
8070 IrInstGen *result_loc_inst;
8070 Stage1AirInst *result_loc_inst;
80718071 if (ptr_type->data.pointer.host_int_bytes != 0 && handle_is_ptr(ira->codegen, child_type)) {
80728072 if (result_loc == nullptr) result_loc = no_result_loc();
80738073 result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, child_type, nullptr, true, true);
......@@ -8104,7 +8104,7 @@ static bool ir_resolve_const_align(CodeGen *codegen, Stage1Air *exec, AstNode *s
81048104 return true;
81058105}
81068106
8107static bool ir_resolve_align(IrAnalyze *ira, IrInstGen *value, ZigType *elem_type, uint32_t *out) {
8107static bool ir_resolve_align(IrAnalyze *ira, Stage1AirInst *value, ZigType *elem_type, uint32_t *out) {
81088108 if (type_is_invalid(value->value->type))
81098109 return false;
81108110
......@@ -8125,7 +8125,7 @@ static bool ir_resolve_align(IrAnalyze *ira, IrInstGen *value, ZigType *elem_typ
81258125 }
81268126 }
81278127
8128 IrInstGen *casted_value = ir_implicit_cast(ira, value, get_align_amt_type(ira->codegen));
8128 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, get_align_amt_type(ira->codegen));
81298129 if (type_is_invalid(casted_value->value->type))
81308130 return false;
81318131
......@@ -8133,11 +8133,11 @@ static bool ir_resolve_align(IrAnalyze *ira, IrInstGen *value, ZigType *elem_typ
81338133 casted_value->value, out);
81348134}
81358135
8136static bool ir_resolve_unsigned(IrAnalyze *ira, IrInstGen *value, ZigType *int_type, uint64_t *out) {
8136static bool ir_resolve_unsigned(IrAnalyze *ira, Stage1AirInst *value, ZigType *int_type, uint64_t *out) {
81378137 if (type_is_invalid(value->value->type))
81388138 return false;
81398139
8140 IrInstGen *casted_value = ir_implicit_cast(ira, value, int_type);
8140 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, int_type);
81418141 if (type_is_invalid(casted_value->value->type))
81428142 return false;
81438143
......@@ -8149,15 +8149,15 @@ static bool ir_resolve_unsigned(IrAnalyze *ira, IrInstGen *value, ZigType *int_t
81498149 return true;
81508150}
81518151
8152static bool ir_resolve_usize(IrAnalyze *ira, IrInstGen *value, uint64_t *out) {
8152static bool ir_resolve_usize(IrAnalyze *ira, Stage1AirInst *value, uint64_t *out) {
81538153 return ir_resolve_unsigned(ira, value, ira->codegen->builtin_types.entry_usize, out);
81548154}
81558155
8156static bool ir_resolve_bool(IrAnalyze *ira, IrInstGen *value, bool *out) {
8156static bool ir_resolve_bool(IrAnalyze *ira, Stage1AirInst *value, bool *out) {
81578157 if (type_is_invalid(value->value->type))
81588158 return false;
81598159
8160 IrInstGen *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_bool);
8160 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_bool);
81618161 if (type_is_invalid(casted_value->value->type))
81628162 return false;
81638163
......@@ -8169,7 +8169,7 @@ static bool ir_resolve_bool(IrAnalyze *ira, IrInstGen *value, bool *out) {
81698169 return true;
81708170}
81718171
8172static bool ir_resolve_comptime(IrAnalyze *ira, IrInstGen *value, bool *out) {
8172static bool ir_resolve_comptime(IrAnalyze *ira, Stage1AirInst *value, bool *out) {
81738173 if (!value) {
81748174 *out = false;
81758175 return true;
......@@ -8177,13 +8177,13 @@ static bool ir_resolve_comptime(IrAnalyze *ira, IrInstGen *value, bool *out) {
81778177 return ir_resolve_bool(ira, value, out);
81788178}
81798179
8180static bool ir_resolve_reduce_op(IrAnalyze *ira, IrInstGen *value, ReduceOp *out) {
8180static bool ir_resolve_reduce_op(IrAnalyze *ira, Stage1AirInst *value, ReduceOp *out) {
81818181 if (type_is_invalid(value->value->type))
81828182 return false;
81838183
81848184 ZigType *reduce_op_type = get_builtin_type(ira->codegen, "ReduceOp");
81858185
8186 IrInstGen *casted_value = ir_implicit_cast(ira, value, reduce_op_type);
8186 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, reduce_op_type);
81878187 if (type_is_invalid(casted_value->value->type))
81888188 return false;
81898189
......@@ -8195,13 +8195,13 @@ static bool ir_resolve_reduce_op(IrAnalyze *ira, IrInstGen *value, ReduceOp *out
81958195 return true;
81968196}
81978197
8198static bool ir_resolve_atomic_order(IrAnalyze *ira, IrInstGen *value, AtomicOrder *out) {
8198static bool ir_resolve_atomic_order(IrAnalyze *ira, Stage1AirInst *value, AtomicOrder *out) {
81998199 if (type_is_invalid(value->value->type))
82008200 return false;
82018201
82028202 ZigType *atomic_order_type = get_builtin_type(ira->codegen, "AtomicOrder");
82038203
8204 IrInstGen *casted_value = ir_implicit_cast(ira, value, atomic_order_type);
8204 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, atomic_order_type);
82058205 if (type_is_invalid(casted_value->value->type))
82068206 return false;
82078207
......@@ -8213,13 +8213,13 @@ static bool ir_resolve_atomic_order(IrAnalyze *ira, IrInstGen *value, AtomicOrde
82138213 return true;
82148214}
82158215
8216static bool ir_resolve_atomic_rmw_op(IrAnalyze *ira, IrInstGen *value, AtomicRmwOp *out) {
8216static bool ir_resolve_atomic_rmw_op(IrAnalyze *ira, Stage1AirInst *value, AtomicRmwOp *out) {
82178217 if (type_is_invalid(value->value->type))
82188218 return false;
82198219
82208220 ZigType *atomic_rmw_op_type = get_builtin_type(ira->codegen, "AtomicRmwOp");
82218221
8222 IrInstGen *casted_value = ir_implicit_cast(ira, value, atomic_rmw_op_type);
8222 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, atomic_rmw_op_type);
82238223 if (type_is_invalid(casted_value->value->type))
82248224 return false;
82258225
......@@ -8231,13 +8231,13 @@ static bool ir_resolve_atomic_rmw_op(IrAnalyze *ira, IrInstGen *value, AtomicRmw
82318231 return true;
82328232}
82338233
8234static bool ir_resolve_global_linkage(IrAnalyze *ira, IrInstGen *value, GlobalLinkageId *out) {
8234static bool ir_resolve_global_linkage(IrAnalyze *ira, Stage1AirInst *value, GlobalLinkageId *out) {
82358235 if (type_is_invalid(value->value->type))
82368236 return false;
82378237
82388238 ZigType *global_linkage_type = get_builtin_type(ira->codegen, "GlobalLinkage");
82398239
8240 IrInstGen *casted_value = ir_implicit_cast(ira, value, global_linkage_type);
8240 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, global_linkage_type);
82418241 if (type_is_invalid(casted_value->value->type))
82428242 return false;
82438243
......@@ -8249,13 +8249,13 @@ static bool ir_resolve_global_linkage(IrAnalyze *ira, IrInstGen *value, GlobalLi
82498249 return true;
82508250}
82518251
8252static bool ir_resolve_float_mode(IrAnalyze *ira, IrInstGen *value, FloatMode *out) {
8252static bool ir_resolve_float_mode(IrAnalyze *ira, Stage1AirInst *value, FloatMode *out) {
82538253 if (type_is_invalid(value->value->type))
82548254 return false;
82558255
82568256 ZigType *float_mode_type = get_builtin_type(ira->codegen, "FloatMode");
82578257
8258 IrInstGen *casted_value = ir_implicit_cast(ira, value, float_mode_type);
8258 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, float_mode_type);
82598259 if (type_is_invalid(casted_value->value->type))
82608260 return false;
82618261
......@@ -8267,14 +8267,14 @@ static bool ir_resolve_float_mode(IrAnalyze *ira, IrInstGen *value, FloatMode *o
82678267 return true;
82688268}
82698269
8270static Buf *ir_resolve_str(IrAnalyze *ira, IrInstGen *value) {
8270static Buf *ir_resolve_str(IrAnalyze *ira, Stage1AirInst *value) {
82718271 if (type_is_invalid(value->value->type))
82728272 return nullptr;
82738273
82748274 ZigType *ptr_type = get_pointer_to_type_extra(ira->codegen, ira->codegen->builtin_types.entry_u8,
82758275 true, false, PtrLenUnknown, 0, 0, 0, false);
82768276 ZigType *str_type = get_slice_type(ira->codegen, ptr_type);
8277 IrInstGen *casted_value = ir_implicit_cast(ira, value, str_type);
8277 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, str_type);
82788278 if (type_is_invalid(casted_value->value->type))
82798279 return nullptr;
82808280
......@@ -8309,10 +8309,10 @@ static Buf *ir_resolve_str(IrAnalyze *ira, IrInstGen *value) {
83098309 return result;
83108310}
83118311
8312static IrInstGen *ir_analyze_instruction_add_implicit_return_type(IrAnalyze *ira,
8313 IrInstSrcAddImplicitReturnType *instruction)
8312static Stage1AirInst *ir_analyze_instruction_add_implicit_return_type(IrAnalyze *ira,
8313 Stage1ZirInstAddImplicitReturnType *instruction)
83148314{
8315 IrInstGen *value = instruction->value->child;
8315 Stage1AirInst *value = instruction->value->child;
83168316 if (type_is_invalid(value->value->type))
83178317 return ir_unreach_error(ira);
83188318
......@@ -8323,18 +8323,18 @@ static IrInstGen *ir_analyze_instruction_add_implicit_return_type(IrAnalyze *ira
83238323 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
83248324}
83258325
8326static IrInstGen *ir_analyze_instruction_return(IrAnalyze *ira, IrInstSrcReturn *instruction) {
8326static Stage1AirInst *ir_analyze_instruction_return(IrAnalyze *ira, Stage1ZirInstReturn *instruction) {
83278327 if (instruction->operand == nullptr) {
83288328 // result location mechanism took care of it.
8329 IrInstGen *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr);
8329 Stage1AirInst *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr);
83308330 return ir_finish_anal(ira, result);
83318331 }
83328332
8333 IrInstGen *operand = instruction->operand->child;
8333 Stage1AirInst *operand = instruction->operand->child;
83348334 if (type_is_invalid(operand->value->type))
83358335 return ir_unreach_error(ira);
83368336
8337 IrInstGen *casted_operand = ir_implicit_cast(ira, operand, ira->explicit_return_type);
8337 Stage1AirInst *casted_operand = ir_implicit_cast(ira, operand, ira->explicit_return_type);
83388338 if (type_is_invalid(casted_operand->value->type)) {
83398339 AstNode *source_node = ira->explicit_return_type_source_node;
83408340 if (source_node != nullptr) {
......@@ -8349,7 +8349,7 @@ static IrInstGen *ir_analyze_instruction_return(IrAnalyze *ira, IrInstSrcReturn
83498349 handle_is_ptr(ira->codegen, ira->explicit_return_type))
83508350 {
83518351 // result location mechanism took care of it.
8352 IrInstGen *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr);
8352 Stage1AirInst *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr);
83538353 return ir_finish_anal(ira, result);
83548354 }
83558355
......@@ -8362,30 +8362,30 @@ static IrInstGen *ir_analyze_instruction_return(IrAnalyze *ira, IrInstSrcReturn
83628362 return ir_unreach_error(ira);
83638363 }
83648364
8365 IrInstGen *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, casted_operand);
8365 Stage1AirInst *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, casted_operand);
83668366 return ir_finish_anal(ira, result);
83678367}
83688368
8369static IrInstGen *ir_analyze_instruction_const(IrAnalyze *ira, IrInstSrcConst *instruction) {
8369static Stage1AirInst *ir_analyze_instruction_const(IrAnalyze *ira, Stage1ZirInstConst *instruction) {
83708370 return ir_const_move(ira, instruction->base.scope, instruction->base.source_node, instruction->value);
83718371}
83728372
8373static IrInstGen *ir_analyze_bin_op_bool(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) {
8374 IrInstGen *op1 = bin_op_instruction->op1->child;
8373static Stage1AirInst *ir_analyze_bin_op_bool(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) {
8374 Stage1AirInst *op1 = bin_op_instruction->op1->child;
83758375 if (type_is_invalid(op1->value->type))
83768376 return ira->codegen->invalid_inst_gen;
83778377
8378 IrInstGen *op2 = bin_op_instruction->op2->child;
8378 Stage1AirInst *op2 = bin_op_instruction->op2->child;
83798379 if (type_is_invalid(op2->value->type))
83808380 return ira->codegen->invalid_inst_gen;
83818381
83828382 ZigType *bool_type = ira->codegen->builtin_types.entry_bool;
83838383
8384 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, bool_type);
8384 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, bool_type);
83858385 if (type_is_invalid(casted_op1->value->type))
83868386 return ira->codegen->invalid_inst_gen;
83878387
8388 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, bool_type);
8388 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, bool_type);
83898389 if (type_is_invalid(casted_op2->value->type))
83908390 return ira->codegen->invalid_inst_gen;
83918391
......@@ -8465,7 +8465,7 @@ static void set_optional_payload(ZigValue *opt_val, ZigValue *payload) {
84658465 }
84668466}
84678467
8468static IrInstGen *ir_evaluate_bin_op_cmp(IrAnalyze *ira, ZigType *resolved_type,
8468static Stage1AirInst *ir_evaluate_bin_op_cmp(IrAnalyze *ira, ZigType *resolved_type,
84698469 ZigValue *op1_val, ZigValue *op2_val, Scope *scope, AstNode *source_node, IrBinOp op_id,
84708470 bool one_possible_value)
84718471{
......@@ -8508,7 +8508,7 @@ static IrInstGen *ir_evaluate_bin_op_cmp(IrAnalyze *ira, ZigType *resolved_type,
85088508 zig_unreachable();
85098509}
85108510
8511static IrInstGen *ir_try_evaluate_bin_op_cmp_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *op1, IrInstGen *op2,
8511static Stage1AirInst *ir_try_evaluate_bin_op_cmp_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *op1, Stage1AirInst *op2,
85128512 ZigType *resolved_type, IrBinOp op_id)
85138513{
85148514 assert(op1->value->type == resolved_type && op2->value->type == resolved_type);
......@@ -8533,14 +8533,14 @@ static IrInstGen *ir_try_evaluate_bin_op_cmp_const(IrAnalyze *ira, Scope *scope,
85338533 return ira->codegen->invalid_inst_gen;
85348534 if (resolved_type->id != ZigTypeIdVector)
85358535 return ir_evaluate_bin_op_cmp(ira, resolved_type, op1_val, op2_val, scope, source_node, op_id, one_possible_value);
8536 IrInstGen *result = ir_const(ira, scope, source_node,
8536 Stage1AirInst *result = ir_const(ira, scope, source_node,
85378537 get_vector_type(ira->codegen, resolved_type->data.vector.len, ira->codegen->builtin_types.entry_bool));
85388538 result->value->data.x_array.data.s_none.elements =
85398539 ira->codegen->pass1_arena->allocate<ZigValue>(resolved_type->data.vector.len);
85408540
85418541 expand_undef_array(ira->codegen, result->value);
85428542 for (size_t i = 0;i < resolved_type->data.vector.len;i++) {
8543 IrInstGen *cur_res = ir_evaluate_bin_op_cmp(ira, resolved_type->data.vector.elem_type,
8543 Stage1AirInst *cur_res = ir_evaluate_bin_op_cmp(ira, resolved_type->data.vector.elem_type,
85448544 &op1_val->data.x_array.data.s_none.elements[i],
85458545 &op2_val->data.x_array.data.s_none.elements[i],
85468546 scope, source_node, op_id, one_possible_value);
......@@ -8708,14 +8708,14 @@ never_mind_just_calculate_it_normally:
87088708 return nullptr;
87098709 }
87108710 if (op1_val->type->id == ZigTypeIdComptimeFloat) {
8711 IrInstGen *tmp = ir_const_noval(ira, scope, source_node);
8711 Stage1AirInst *tmp = ir_const_noval(ira, scope, source_node);
87128712 tmp->value = op1_val;
8713 IrInstGen *casted = ir_implicit_cast(ira, tmp, op2_val->type);
8713 Stage1AirInst *casted = ir_implicit_cast(ira, tmp, op2_val->type);
87148714 op1_val = casted->value;
87158715 } else if (op2_val->type->id == ZigTypeIdComptimeFloat) {
8716 IrInstGen *tmp = ir_const_noval(ira, scope, source_node);
8716 Stage1AirInst *tmp = ir_const_noval(ira, scope, source_node);
87178717 tmp->value = op2_val;
8718 IrInstGen *casted = ir_implicit_cast(ira, tmp, op1_val->type);
8718 Stage1AirInst *casted = ir_implicit_cast(ira, tmp, op1_val->type);
87198719 op2_val = casted->value;
87208720 }
87218721 Cmp cmp_result = float_cmp(op1_val, op2_val);
......@@ -8768,8 +8768,8 @@ never_mind_just_calculate_it_normally:
87688768 return nullptr;
87698769}
87708770
8771static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, AstNode *source_node,
8772 IrInstGen *op1, IrInstGen *op2, IrBinOp op_id)
8771static Stage1AirInst *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, AstNode *source_node,
8772 Stage1AirInst *op1, Stage1AirInst *op2, IrBinOp op_id)
87738773{
87748774 Error err;
87758775
......@@ -8833,7 +8833,7 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As
88338833 if (((opv_op1 || instr_is_comptime(op1)) && (opv_op2 || instr_is_comptime(op2))) ||
88348834 (have_op1_cmp_zero && have_op2_cmp_zero))
88358835 {
8836 IrInstGen *result_instruction = ir_const(ira, scope, source_node, result_type);
8836 Stage1AirInst *result_instruction = ir_const(ira, scope, source_node, result_type);
88378837 ZigValue *out_val = result_instruction->value;
88388838 if (result_type->id == ZigTypeIdVector) {
88398839 size_t len = result_type->data.vector.len;
......@@ -8954,8 +8954,8 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As
89548954 }
89558955 ZigType *dest_type = (result_type->id == ZigTypeIdVector) ?
89568956 get_vector_type(ira->codegen, result_type->data.vector.len, dest_scalar_type) : dest_scalar_type;
8957 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, dest_type);
8958 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, dest_type);
8957 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, dest_type);
8958 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, dest_type);
89598959 if (type_is_invalid(casted_op1->value->type) || type_is_invalid(casted_op2->value->type))
89608960 return ira->codegen->invalid_inst_gen;
89618961 return ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id, casted_op1, casted_op2, true);
......@@ -9071,10 +9071,10 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As
90719071 ZigType *dest_type = (result_type->id == ZigTypeIdVector) ?
90729072 get_vector_type(ira->codegen, result_type->data.vector.len, dest_scalar_type) : dest_scalar_type;
90739073
9074 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, dest_type);
9074 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, dest_type);
90759075 if (type_is_invalid(casted_op1->value->type))
90769076 return ira->codegen->invalid_inst_gen;
9077 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, dest_type);
9077 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, dest_type);
90789078 if (type_is_invalid(casted_op2->value->type))
90799079 return ira->codegen->invalid_inst_gen;
90809080 return ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id, casted_op1, casted_op2, true);
......@@ -9128,8 +9128,8 @@ static bool type_is_self_comparable(ZigType *ty, bool is_equality_cmp) {
91289128 zig_unreachable();
91299129}
91309130
9131static IrInstGen *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type,
9132 IrInstGen *optional, IrInstGen *non_optional, IrBinOp op_id)
9131static Stage1AirInst *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type,
9132 Stage1AirInst *optional, Stage1AirInst *non_optional, IrBinOp op_id)
91339133{
91349134 assert(optional->value->type->id == ZigTypeIdOptional);
91359135 assert(optional->value->type->data.maybe.child_type == non_optional->value->type);
......@@ -9148,12 +9148,12 @@ static IrInstGen *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira
91489148 }
91499149
91509150 if (!optional_value_is_null(optional_val)) {
9151 IrInstGen *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false);
9151 Stage1AirInst *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false);
91529152 if (type_is_invalid(optional_unwrapped->value->type)) {
91539153 return ira->codegen->invalid_inst_gen;
91549154 }
91559155
9156 IrInstGen *ret = ir_try_evaluate_bin_op_cmp_const(ira, scope, source_node, optional_unwrapped, non_optional, child_type, op_id);
9156 Stage1AirInst *ret = ir_try_evaluate_bin_op_cmp_const(ira, scope, source_node, optional_unwrapped, non_optional, child_type, op_id);
91579157 assert(ret != nullptr);
91589158 return ret;
91599159 }
......@@ -9163,8 +9163,8 @@ static IrInstGen *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira
91639163 }
91649164}
91659165
9166static IrInstGen *ir_evaluate_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type,
9167 IrInstGen *optional, IrInstGen *non_optional, IrBinOp op_id)
9166static Stage1AirInst *ir_evaluate_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type,
9167 Stage1AirInst *optional, Stage1AirInst *non_optional, IrBinOp op_id)
91689168{
91699169 assert(optional->value->type->id == ZigTypeIdOptional);
91709170 assert(optional->value->type->data.maybe.child_type == non_optional->value->type);
......@@ -9174,47 +9174,47 @@ static IrInstGen *ir_evaluate_cmp_optional_non_optional(IrAnalyze *ira, Scope *s
91749174 ZigType *result_type = ira->codegen->builtin_types.entry_bool;
91759175 ir_append_basic_block_gen(&ira->new_irb, ira->new_irb.current_basic_block);
91769176
9177 IrBasicBlockGen *null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNull");
9178 IrBasicBlockGen *non_null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNotNull");
9179 IrBasicBlockGen *end_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalEnd");
9177 Stage1AirBasicBlock *null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNull");
9178 Stage1AirBasicBlock *non_null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNotNull");
9179 Stage1AirBasicBlock *end_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalEnd");
91809180
9181 IrInstGen *is_non_null = ir_build_test_non_null_gen(ira, scope, source_node, optional);
9181 Stage1AirInst *is_non_null = ir_build_test_non_null_gen(ira, scope, source_node, optional);
91829182 ir_build_cond_br_gen(ira, scope, source_node, is_non_null, non_null_block, null_block);
91839183
91849184 ir_set_cursor_at_end_and_append_block_gen(&ira->new_irb, non_null_block);
9185 IrInstGen *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false);
9185 Stage1AirInst *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false);
91869186 if (type_is_invalid(optional_unwrapped->value->type)) {
91879187 return ira->codegen->invalid_inst_gen;
91889188 }
9189 IrInstGen *non_null_cmp_result = ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id,
9189 Stage1AirInst *non_null_cmp_result = ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id,
91909190 optional_unwrapped, non_optional, false); // safety check unnecessary for comparison operators
91919191 ir_build_br_gen(ira, scope, source_node, end_block);
91929192
91939193
91949194 ir_set_cursor_at_end_and_append_block_gen(&ira->new_irb, null_block);
9195 IrInstGen *null_result = ir_const_bool(ira, scope, source_node, (op_id != IrBinOpCmpEq));
9195 Stage1AirInst *null_result = ir_const_bool(ira, scope, source_node, (op_id != IrBinOpCmpEq));
91969196 ir_build_br_gen(ira, scope, source_node, end_block);
91979197
91989198 ir_set_cursor_at_end_gen(&ira->new_irb, end_block);
91999199 int incoming_count = 2;
9200 IrBasicBlockGen **incoming_blocks = heap::c_allocator.allocate_nonzero<IrBasicBlockGen *>(incoming_count);
9200 Stage1AirBasicBlock **incoming_blocks = heap::c_allocator.allocate_nonzero<Stage1AirBasicBlock *>(incoming_count);
92019201 incoming_blocks[0] = null_block;
92029202 incoming_blocks[1] = non_null_block;
9203 IrInstGen **incoming_values = heap::c_allocator.allocate_nonzero<IrInstGen *>(incoming_count);
9203 Stage1AirInst **incoming_values = heap::c_allocator.allocate_nonzero<Stage1AirInst *>(incoming_count);
92049204 incoming_values[0] = null_result;
92059205 incoming_values[1] = non_null_cmp_result;
92069206
92079207 return ir_build_phi_gen(ira, scope, source_node, incoming_count, incoming_blocks, incoming_values, result_type);
92089208}
92099209
9210static IrInstGen *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node,
9211 IrInstGen *op1, IrInstGen *op2, IrInstGen *optional, IrBinOp op_id)
9210static Stage1AirInst *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node,
9211 Stage1AirInst *op1, Stage1AirInst *op2, Stage1AirInst *optional, IrBinOp op_id)
92129212{
92139213 assert(op_id == IrBinOpCmpEq || op_id == IrBinOpCmpNotEq);
92149214 assert(optional->value->type->id == ZigTypeIdOptional);
92159215 assert(get_src_ptr_type(optional->value->type) == nullptr);
92169216
9217 IrInstGen *non_optional;
9217 Stage1AirInst *non_optional;
92189218 if (op1 == optional) {
92199219 non_optional = op2;
92209220 } else if (op2 == optional) {
......@@ -9253,7 +9253,7 @@ static IrInstGen *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *sc
92539253 return ira->codegen->invalid_inst_gen;
92549254 }
92559255
9256 if (IrInstGen *const_result = ir_try_evaluate_cmp_optional_non_optional_const(ira, scope, source_node, child_type,
9256 if (Stage1AirInst *const_result = ir_try_evaluate_cmp_optional_non_optional_const(ira, scope, source_node, child_type,
92579257 optional, non_optional, op_id))
92589258 {
92599259 return const_result;
......@@ -9262,12 +9262,12 @@ static IrInstGen *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *sc
92629262 return ir_evaluate_cmp_optional_non_optional(ira, scope, source_node, child_type, optional, non_optional, op_id);
92639263}
92649264
9265static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) {
9266 IrInstGen *op1 = bin_op_instruction->op1->child;
9265static Stage1AirInst *ir_analyze_bin_op_cmp(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) {
9266 Stage1AirInst *op1 = bin_op_instruction->op1->child;
92679267 if (type_is_invalid(op1->value->type))
92689268 return ira->codegen->invalid_inst_gen;
92699269
9270 IrInstGen *op2 = bin_op_instruction->op2->child;
9270 Stage1AirInst *op2 = bin_op_instruction->op2->child;
92719271 if (type_is_invalid(op2->value->type))
92729272 return ira->codegen->invalid_inst_gen;
92739273
......@@ -9282,7 +9282,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
92829282 ((op1->value->type->id == ZigTypeIdNull && op2->value->type->id == ZigTypeIdOptional) ||
92839283 (op2->value->type->id == ZigTypeIdNull && op1->value->type->id == ZigTypeIdOptional)))
92849284 {
9285 IrInstGen *maybe_op;
9285 Stage1AirInst *maybe_op;
92869286 if (op1->value->type->id == ZigTypeIdNull) {
92879287 maybe_op = op2;
92889288 } else if (op2->value->type->id == ZigTypeIdNull) {
......@@ -9300,7 +9300,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
93009300 bin_op_instruction->base.source_node, bool_result);
93019301 }
93029302
9303 IrInstGen *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope,
9303 Stage1AirInst *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope,
93049304 bin_op_instruction->base.source_node, maybe_op);
93059305
93069306 if (op_id == IrBinOpCmpEq) {
......@@ -9315,7 +9315,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
93159315 (op2->value->type->id == ZigTypeIdNull && op1->value->type->id == ZigTypeIdPointer &&
93169316 op1->value->type->data.pointer.ptr_len == PtrLenC)))
93179317 {
9318 IrInstGen *c_ptr_op;
9318 Stage1AirInst *c_ptr_op;
93199319 if (op1->value->type->id == ZigTypeIdNull) {
93209320 c_ptr_op = op2;
93219321 } else if (op2->value->type->id == ZigTypeIdNull) {
......@@ -9335,7 +9335,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
93359335 bool bool_result = (op_id == IrBinOpCmpEq) ? is_null : !is_null;
93369336 return ir_const_bool(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, bool_result);
93379337 }
9338 IrInstGen *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, c_ptr_op);
9338 Stage1AirInst *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, c_ptr_op);
93399339
93409340 if (op_id == IrBinOpCmpEq) {
93419341 return ir_build_bool_not_gen(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, is_non_null);
......@@ -9360,8 +9360,8 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
93609360 (op2->value->type->id == ZigTypeIdEnumLiteral && op1->value->type->id == ZigTypeIdUnion)))
93619361 {
93629362 // Support equality comparison between a union's tag value and a enum literal
9363 IrInstGen *union_val = op1->value->type->id == ZigTypeIdUnion ? op1 : op2;
9364 IrInstGen *enum_val = op1->value->type->id == ZigTypeIdUnion ? op2 : op1;
9363 Stage1AirInst *union_val = op1->value->type->id == ZigTypeIdUnion ? op1 : op2;
9364 Stage1AirInst *enum_val = op1->value->type->id == ZigTypeIdUnion ? op2 : op1;
93659365
93669366 if (!is_tagged_union(union_val->value->type)) {
93679367 ErrorMsg *msg = ir_add_error_node(ira, source_node,
......@@ -9375,11 +9375,11 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
93759375 ZigType *tag_type = union_val->value->type->data.unionation.tag_type;
93769376 assert(tag_type != nullptr);
93779377
9378 IrInstGen *casted_union = ir_implicit_cast(ira, union_val, tag_type);
9378 Stage1AirInst *casted_union = ir_implicit_cast(ira, union_val, tag_type);
93799379 if (type_is_invalid(casted_union->value->type))
93809380 return ira->codegen->invalid_inst_gen;
93819381
9382 IrInstGen *casted_val = ir_implicit_cast(ira, enum_val, tag_type);
9382 Stage1AirInst *casted_val = ir_implicit_cast(ira, enum_val, tag_type);
93839383 if (type_is_invalid(casted_val->value->type))
93849384 return ira->codegen->invalid_inst_gen;
93859385
......@@ -9486,7 +9486,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
94869486 return ir_analyze_bin_op_cmp_numeric(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, op1, op2, op_id);
94879487 }
94889488
9489 IrInstGen *instructions[] = {op1, op2};
9489 Stage1AirInst *instructions[] = {op1, op2};
94909490 ZigType *resolved_type = ir_resolve_peer_types(ira, source_node, nullptr, instructions, 2);
94919491 if (type_is_invalid(resolved_type))
94929492 return ira->codegen->invalid_inst_gen;
......@@ -9499,15 +9499,15 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i
94999499 return ira->codegen->invalid_inst_gen;
95009500 }
95019501
9502 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, resolved_type);
9502 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, resolved_type);
95039503 if (type_is_invalid(casted_op1->value->type))
95049504 return ira->codegen->invalid_inst_gen;
95059505
9506 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, resolved_type);
9506 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, resolved_type);
95079507 if (type_is_invalid(casted_op2->value->type))
95089508 return ira->codegen->invalid_inst_gen;
95099509
9510 IrInstGen *resolve_const_result = ir_try_evaluate_bin_op_cmp_const(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, casted_op1,
9510 Stage1AirInst *resolve_const_result = ir_try_evaluate_bin_op_cmp_const(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, casted_op1,
95119511 casted_op2, resolved_type, op_id);
95129512 if (resolve_const_result != nullptr) {
95139513 return resolve_const_result;
......@@ -9700,10 +9700,10 @@ static ErrorMsg *ir_eval_math_op_scalar(IrAnalyze *ira, Scope *scope, AstNode *s
97009700}
97019701
97029702// This works on operands that have already been checked to be comptime known.
9703static IrInstGen *ir_analyze_math_op(IrAnalyze *ira, Scope *scope, AstNode *source_node,
9703static Stage1AirInst *ir_analyze_math_op(IrAnalyze *ira, Scope *scope, AstNode *source_node,
97049704 ZigType *type_entry, ZigValue *op1_val, IrBinOp op_id, ZigValue *op2_val)
97059705{
9706 IrInstGen *result_instruction = ir_const(ira, scope, source_node, type_entry);
9706 Stage1AirInst *result_instruction = ir_const(ira, scope, source_node, type_entry);
97079707 ZigValue *out_val = result_instruction->value;
97089708 if (type_entry->id == ZigTypeIdVector) {
97099709 expand_undef_array(ira->codegen, op1_val);
......@@ -9736,12 +9736,12 @@ static IrInstGen *ir_analyze_math_op(IrAnalyze *ira, Scope *scope, AstNode *sour
97369736 return ir_implicit_cast(ira, result_instruction, type_entry);
97379737}
97389738
9739static IrInstGen *ir_analyze_bit_shift(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) {
9740 IrInstGen *op1 = bin_op_instruction->op1->child;
9739static Stage1AirInst *ir_analyze_bit_shift(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) {
9740 Stage1AirInst *op1 = bin_op_instruction->op1->child;
97419741 if (type_is_invalid(op1->value->type))
97429742 return ira->codegen->invalid_inst_gen;
97439743
9744 IrInstGen *op2 = bin_op_instruction->op2->child;
9744 Stage1AirInst *op2 = bin_op_instruction->op2->child;
97459745 if (type_is_invalid(op2->value->type))
97469746 return ira->codegen->invalid_inst_gen;
97479747
......@@ -9781,7 +9781,7 @@ static IrInstGen *ir_analyze_bit_shift(IrAnalyze *ira, IrInstSrcBinOp *bin_op_in
97819781 return ira->codegen->invalid_inst_gen;
97829782 }
97839783
9784 IrInstGen *casted_op2;
9784 Stage1AirInst *casted_op2;
97859785 IrBinOp op_id = bin_op_instruction->op_id;
97869786 if (op1_scalar_type->id == ZigTypeIdComptimeInt) {
97879787 // comptime_int has no finite bit width
......@@ -10005,14 +10005,14 @@ static bool value_cmp_numeric_val_all(ZigValue *left, Cmp predicate, ZigValue *r
1000510005 return value_cmp_numeric_val(left, predicate, right, false);
1000610006}
1000710007
10008static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruction) {
10008static Stage1AirInst *ir_analyze_bin_op_math(IrAnalyze *ira, Stage1ZirInstBinOp *instruction) {
1000910009 Error err;
1001010010
10011 IrInstGen *op1 = instruction->op1->child;
10011 Stage1AirInst *op1 = instruction->op1->child;
1001210012 if (type_is_invalid(op1->value->type))
1001310013 return ira->codegen->invalid_inst_gen;
1001410014
10015 IrInstGen *op2 = instruction->op2->child;
10015 Stage1AirInst *op2 = instruction->op2->child;
1001610016 if (type_is_invalid(op2->value->type))
1001710017 return ira->codegen->invalid_inst_gen;
1001810018
......@@ -10020,7 +10020,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
1002010020
1002110021 // look for pointer math
1002210022 if (is_pointer_arithmetic_allowed(op1->value->type, op_id)) {
10023 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, ira->codegen->builtin_types.entry_usize);
10023 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, ira->codegen->builtin_types.entry_usize);
1002410024 if (type_is_invalid(casted_op2->value->type))
1002510025 return ira->codegen->invalid_inst_gen;
1002610026
......@@ -10095,7 +10095,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
1009510095 } else {
1009610096 zig_unreachable();
1009710097 }
10098 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
10098 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
1009910099 result->value->data.x_ptr.special = ConstPtrSpecialHardCodedAddr;
1010010100 result->value->data.x_ptr.mut = ConstPtrMutRuntimeVar;
1010110101 result->value->data.x_ptr.data.hard_coded_addr.addr = new_addr;
......@@ -10105,7 +10105,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
1010510105 return ir_build_bin_op_gen(ira, instruction->base.scope, instruction->base.source_node, result_type, op_id, op1, casted_op2, true);
1010610106 }
1010710107
10108 IrInstGen *instructions[] = {op1, op2};
10108 Stage1AirInst *instructions[] = {op1, op2};
1010910109 ZigType *resolved_type = ir_resolve_peer_types(ira, instruction->base.source_node, nullptr, instructions, 2);
1011010110 if (type_is_invalid(resolved_type))
1011110111 return ira->codegen->invalid_inst_gen;
......@@ -10125,11 +10125,11 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
1012510125 return ira->codegen->invalid_inst_gen;
1012610126 }
1012710127
10128 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, resolved_type);
10128 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, resolved_type);
1012910129 if (type_is_invalid(casted_op1->value->type))
1013010130 return ira->codegen->invalid_inst_gen;
1013110131
10132 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, resolved_type);
10132 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, resolved_type);
1013310133 if (type_is_invalid(casted_op2->value->type))
1013410134 return ira->codegen->invalid_inst_gen;
1013510135
......@@ -10170,17 +10170,17 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
1017010170 // division function ambiguity problem.
1017110171 ok = true;
1017210172 } else {
10173 IrInstGen *trunc_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
10173 Stage1AirInst *trunc_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
1017410174 op1_val, IrBinOpDivTrunc, op2_val);
1017510175 if (type_is_invalid(trunc_val->value->type))
1017610176 return ira->codegen->invalid_inst_gen;
1017710177
10178 IrInstGen *floor_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
10178 Stage1AirInst *floor_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
1017910179 op1_val, IrBinOpDivFloor, op2_val);
1018010180 if (type_is_invalid(floor_val->value->type))
1018110181 return ira->codegen->invalid_inst_gen;
1018210182
10183 IrInstGen *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node,
10183 Stage1AirInst *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node,
1018410184 trunc_val, floor_val, IrBinOpCmpEq);
1018510185 if (type_is_invalid(cmp_val->value->type))
1018610186 return ira->codegen->invalid_inst_gen;
......@@ -10209,17 +10209,17 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
1020910209 // division function ambiguity problem.
1021010210 ok = true;
1021110211 } else {
10212 IrInstGen *rem_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
10212 Stage1AirInst *rem_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
1021310213 op1_val, IrBinOpRemRem, op2_val);
1021410214 if (type_is_invalid(rem_val->value->type))
1021510215 return ira->codegen->invalid_inst_gen;
1021610216
10217 IrInstGen *mod_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
10217 Stage1AirInst *mod_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type,
1021810218 op1_val, IrBinOpRemMod, op2_val);
1021910219 if (type_is_invalid(mod_val->value->type))
1022010220 return ira->codegen->invalid_inst_gen;
1022110221
10222 IrInstGen *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node,
10222 Stage1AirInst *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node,
1022310223 rem_val, mod_val, IrBinOpCmpEq);
1022410224 if (type_is_invalid(cmp_val->value->type))
1022510225 return ira->codegen->invalid_inst_gen;
......@@ -10273,8 +10273,8 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc
1027310273 op_id, casted_op1, casted_op2, instruction->safety_check_on);
1027410274}
1027510275
10276static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *source_node,
10277 IrInstGen *op1, IrInstGen *op2)
10276static Stage1AirInst *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *source_node,
10277 Stage1AirInst *op1, Stage1AirInst *op2)
1027810278{
1027910279 Error err;
1028010280 ZigType *op1_type = op1->value->type;
......@@ -10296,7 +10296,7 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so
1029610296 new_type->data.structure.fields = realloc_type_struct_fields(new_type->data.structure.fields,
1029710297 0, new_field_count);
1029810298
10299 IrInstGen *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
10299 Stage1AirInst *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
1030010300 new_type, nullptr, false, true);
1030110301
1030210302 for (uint32_t i = 0; i < new_field_count; i += 1) {
......@@ -10318,10 +10318,10 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so
1031810318 if ((err = type_resolve(ira->codegen, new_type, ResolveStatusZeroBitsKnown)))
1031910319 return ira->codegen->invalid_inst_gen;
1032010320
10321 ZigList<IrInstGen *> const_ptrs = {};
10321 ZigList<Stage1AirInst *> const_ptrs = {};
1032210322 for (uint32_t i = 0; i < new_field_count; i += 1) {
1032310323 TypeStructField *dst_field = new_type->data.structure.fields[i];
10324 IrInstGen *src_struct_op;
10324 Stage1AirInst *src_struct_op;
1032510325 TypeStructField *src_field;
1032610326 if (i < op1_field_count) {
1032710327 src_field = op1_type->data.structure.fields[i];
......@@ -10330,18 +10330,18 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so
1033010330 src_field = op2_type->data.structure.fields[i - op1_field_count];
1033110331 src_struct_op = op2;
1033210332 }
10333 IrInstGen *field_value = ir_analyze_struct_value_field_value(ira, scope, source_node,
10333 Stage1AirInst *field_value = ir_analyze_struct_value_field_value(ira, scope, source_node,
1033410334 src_struct_op, src_field);
1033510335 if (type_is_invalid(field_value->value->type))
1033610336 return ira->codegen->invalid_inst_gen;
10337 IrInstGen *dest_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, dst_field,
10337 Stage1AirInst *dest_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, dst_field,
1033810338 new_struct_ptr, new_type, true);
1033910339 if (type_is_invalid(dest_ptr->value->type))
1034010340 return ira->codegen->invalid_inst_gen;
1034110341 if (instr_is_comptime(field_value)) {
1034210342 const_ptrs.append(dest_ptr);
1034310343 }
10344 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, dest_ptr, field_value,
10344 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, dest_ptr, field_value,
1034510345 true);
1034610346 if (type_is_invalid(store_ptr_inst->value->type))
1034710347 return ira->codegen->invalid_inst_gen;
......@@ -10349,13 +10349,13 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so
1034910349 if (const_ptrs.length != new_field_count) {
1035010350 new_struct_ptr->value->special = ConstValSpecialRuntime;
1035110351 for (size_t i = 0; i < const_ptrs.length; i += 1) {
10352 IrInstGen *elem_result_loc = const_ptrs.at(i);
10352 Stage1AirInst *elem_result_loc = const_ptrs.at(i);
1035310353 assert(elem_result_loc->value->special == ConstValSpecialStatic);
1035410354 if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) {
1035510355 // This field will be generated comptime; no need to do this.
1035610356 continue;
1035710357 }
10358 IrInstGen *deref = ir_get_deref(ira, elem_result_loc->scope,
10358 Stage1AirInst *deref = ir_get_deref(ira, elem_result_loc->scope,
1035910359 elem_result_loc->source_node, elem_result_loc, nullptr);
1036010360 if (!type_requires_comptime(ira->codegen, elem_result_loc->value->type->data.pointer.child_type)) {
1036110361 elem_result_loc->value->special = ConstValSpecialRuntime;
......@@ -10369,13 +10369,13 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so
1036910369 return ir_get_deref(ira, scope, source_node, new_struct_ptr, nullptr);
1037010370}
1037110371
10372static IrInstGen *ir_analyze_array_cat(IrAnalyze *ira, IrInstSrcBinOp *instruction) {
10373 IrInstGen *op1 = instruction->op1->child;
10372static Stage1AirInst *ir_analyze_array_cat(IrAnalyze *ira, Stage1ZirInstBinOp *instruction) {
10373 Stage1AirInst *op1 = instruction->op1->child;
1037410374 ZigType *op1_type = op1->value->type;
1037510375 if (type_is_invalid(op1_type))
1037610376 return ira->codegen->invalid_inst_gen;
1037710377
10378 IrInstGen *op2 = instruction->op2->child;
10378 Stage1AirInst *op2 = instruction->op2->child;
1037910379 ZigType *op2_type = op2->value->type;
1038010380 if (type_is_invalid(op2_type))
1038110381 return ira->codegen->invalid_inst_gen;
......@@ -10510,7 +10510,7 @@ static IrInstGen *ir_analyze_array_cat(IrAnalyze *ira, IrInstSrcBinOp *instructi
1051010510 }
1051110511
1051210512 // The type of result is populated in the following if blocks
10513 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
10513 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
1051410514 ZigValue *out_val = result->value;
1051510515
1051610516 ZigValue *out_array_val;
......@@ -10598,8 +10598,8 @@ static IrInstGen *ir_analyze_array_cat(IrAnalyze *ira, IrInstSrcBinOp *instructi
1059810598 return result;
1059910599}
1060010600
10601static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *source_node,
10602 IrInstGen *op1, IrInstGen *op2)
10601static Stage1AirInst *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *source_node,
10602 Stage1AirInst *op1, Stage1AirInst *op2)
1060310603{
1060410604 Error err;
1060510605 ZigType *op1_type = op1->value->type;
......@@ -10626,7 +10626,7 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s
1062610626 new_type->data.structure.fields = realloc_type_struct_fields(
1062710627 new_type->data.structure.fields, 0, new_field_count);
1062810628
10629 IrInstGen *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
10629 Stage1AirInst *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(),
1063010630 new_type, nullptr, false, true);
1063110631
1063210632 for (uint64_t i = 0; i < new_field_count; i += 1) {
......@@ -10645,17 +10645,17 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s
1064510645 if ((err = type_resolve(ira->codegen, new_type, ResolveStatusZeroBitsKnown)))
1064610646 return ira->codegen->invalid_inst_gen;
1064710647
10648 ZigList<IrInstGen *> const_ptrs = {};
10648 ZigList<Stage1AirInst *> const_ptrs = {};
1064910649 for (uint64_t i = 0; i < new_field_count; i += 1) {
1065010650 TypeStructField *src_field = op1_type->data.structure.fields[i % op1_field_count];
1065110651 TypeStructField *dst_field = new_type->data.structure.fields[i];
1065210652
10653 IrInstGen *field_value = ir_analyze_struct_value_field_value(
10653 Stage1AirInst *field_value = ir_analyze_struct_value_field_value(
1065410654 ira, scope, source_node, op1, src_field);
1065510655 if (type_is_invalid(field_value->value->type))
1065610656 return ira->codegen->invalid_inst_gen;
1065710657
10658 IrInstGen *dest_ptr = ir_analyze_struct_field_ptr(
10658 Stage1AirInst *dest_ptr = ir_analyze_struct_field_ptr(
1065910659 ira, scope, source_node, dst_field, new_struct_ptr, new_type, true);
1066010660 if (type_is_invalid(dest_ptr->value->type))
1066110661 return ira->codegen->invalid_inst_gen;
......@@ -10664,7 +10664,7 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s
1066410664 const_ptrs.append(dest_ptr);
1066510665 }
1066610666
10667 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(
10667 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(
1066810668 ira, scope, source_node, dest_ptr, field_value, true);
1066910669 if (type_is_invalid(store_ptr_inst->value->type))
1067010670 return ira->codegen->invalid_inst_gen;
......@@ -10673,18 +10673,18 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s
1067310673 if (const_ptrs.length != new_field_count) {
1067410674 new_struct_ptr->value->special = ConstValSpecialRuntime;
1067510675 for (size_t i = 0; i < const_ptrs.length; i += 1) {
10676 IrInstGen *elem_result_loc = const_ptrs.at(i);
10676 Stage1AirInst *elem_result_loc = const_ptrs.at(i);
1067710677 assert(elem_result_loc->value->special == ConstValSpecialStatic);
1067810678 if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) {
1067910679 // This field will be generated comptime; no need to do this.
1068010680 continue;
1068110681 }
10682 IrInstGen *deref = ir_get_deref(ira, elem_result_loc->scope,
10682 Stage1AirInst *deref = ir_get_deref(ira, elem_result_loc->scope,
1068310683 elem_result_loc->source_node, elem_result_loc, nullptr);
1068410684 if (!type_requires_comptime(ira->codegen, elem_result_loc->value->type->data.pointer.child_type)) {
1068510685 elem_result_loc->value->special = ConstValSpecialRuntime;
1068610686 }
10687 IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, elem_result_loc->scope,
10687 Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, elem_result_loc->scope,
1068810688 elem_result_loc->source_node, elem_result_loc, deref, true);
1068910689 if (type_is_invalid(store_ptr_inst->value->type))
1069010690 return ira->codegen->invalid_inst_gen;
......@@ -10696,12 +10696,12 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s
1069610696 return ir_get_deref(ira, scope, source_node, new_struct_ptr, nullptr);
1069710697}
1069810698
10699static IrInstGen *ir_analyze_array_mult(IrAnalyze *ira, IrInstSrcBinOp *instruction) {
10700 IrInstGen *op1 = instruction->op1->child;
10699static Stage1AirInst *ir_analyze_array_mult(IrAnalyze *ira, Stage1ZirInstBinOp *instruction) {
10700 Stage1AirInst *op1 = instruction->op1->child;
1070110701 if (type_is_invalid(op1->value->type))
1070210702 return ira->codegen->invalid_inst_gen;
1070310703
10704 IrInstGen *op2 = instruction->op2->child;
10704 Stage1AirInst *op2 = instruction->op2->child;
1070510705 if (type_is_invalid(op2->value->type))
1070610706 return ira->codegen->invalid_inst_gen;
1070710707
......@@ -10718,7 +10718,7 @@ static IrInstGen *ir_analyze_array_mult(IrAnalyze *ira, IrInstSrcBinOp *instruct
1071810718 op1->value->type->data.pointer.child_type->id == ZigTypeIdArray)
1071910719 {
1072010720 array_type = op1->value->type->data.pointer.child_type;
10721 IrInstGen *array_inst = ir_get_deref(ira, op1->scope, op1->source_node, op1, nullptr);
10721 Stage1AirInst *array_inst = ir_get_deref(ira, op1->scope, op1->source_node, op1, nullptr);
1072210722 if (type_is_invalid(array_inst->value->type))
1072310723 return ira->codegen->invalid_inst_gen;
1072410724 array_val = ir_resolve_const(ira, array_inst, UndefOk);
......@@ -10748,7 +10748,7 @@ static IrInstGen *ir_analyze_array_mult(IrAnalyze *ira, IrInstSrcBinOp *instruct
1074810748 ZigType *result_array_type = get_array_type(ira->codegen, child_type, new_array_len,
1074910749 array_type->data.array.sentinel);
1075010750
10751 IrInstGen *array_result;
10751 Stage1AirInst *array_result;
1075210752 if (array_val->special == ConstValSpecialUndef || array_val->data.x_array.special == ConstArraySpecialUndef) {
1075310753 array_result = ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, result_array_type);
1075410754 } else {
......@@ -10799,8 +10799,8 @@ skip_computation:
1079910799 }
1080010800}
1080110801
10802static IrInstGen *ir_analyze_instruction_merge_err_sets(IrAnalyze *ira,
10803 IrInstSrcMergeErrSets *instruction)
10802static Stage1AirInst *ir_analyze_instruction_merge_err_sets(IrAnalyze *ira,
10803 Stage1ZirInstMergeErrSets *instruction)
1080410804{
1080510805 ZigType *op1_type = ir_resolve_error_set_type(ira, instruction->base.source_node, instruction->op1->child);
1080610806 if (type_is_invalid(op1_type))
......@@ -10838,7 +10838,7 @@ static IrInstGen *ir_analyze_instruction_merge_err_sets(IrAnalyze *ira,
1083810838}
1083910839
1084010840
10841static IrInstGen *ir_analyze_instruction_bin_op(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) {
10841static Stage1AirInst *ir_analyze_instruction_bin_op(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) {
1084210842 IrBinOp op_id = bin_op_instruction->op_id;
1084310843 switch (op_id) {
1084410844 case IrBinOpInvalid:
......@@ -10883,12 +10883,12 @@ static IrInstGen *ir_analyze_instruction_bin_op(IrAnalyze *ira, IrInstSrcBinOp *
1088310883 zig_unreachable();
1088410884}
1088510885
10886static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclVar *decl_var_instruction) {
10886static Stage1AirInst *ir_analyze_instruction_decl_var(IrAnalyze *ira, Stage1ZirInstDeclVar *decl_var_instruction) {
1088710887 Error err;
1088810888 ZigVar *var = decl_var_instruction->var;
1088910889
1089010890 ZigType *explicit_type = nullptr;
10891 IrInstGen *var_type = nullptr;
10891 Stage1AirInst *var_type = nullptr;
1089210892 if (decl_var_instruction->var_type != nullptr) {
1089310893 var_type = decl_var_instruction->var_type->child;
1089410894 ZigType *proposed_type = ir_resolve_type(ira, var_type);
......@@ -10905,7 +10905,7 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV
1090510905
1090610906 bool var_class_requires_const = false;
1090710907
10908 IrInstGen *var_ptr = decl_var_instruction->ptr->child;
10908 Stage1AirInst *var_ptr = decl_var_instruction->ptr->child;
1090910909 // if this is null, a compiler error happened and did not initialize the variable.
1091010910 // if there are no compile errors there may be a missing ir_expr_wrap in pass1 IR generation.
1091110911 if (var_ptr == nullptr || type_is_invalid(var_ptr->value->type)) {
......@@ -11022,7 +11022,7 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV
1102211022 // we need a runtime ptr but we have a comptime val.
1102311023 // since it's a comptime val there are no instructions for it.
1102411024 // we memcpy the init value here
11025 IrInstGen *deref = ir_get_deref(ira, var_ptr->scope, var_ptr->source_node, var_ptr, nullptr);
11025 Stage1AirInst *deref = ir_get_deref(ira, var_ptr->scope, var_ptr->source_node, var_ptr, nullptr);
1102611026 if (type_is_invalid(deref->value->type)) {
1102711027 var->var_type = ira->codegen->builtin_types.entry_invalid;
1102811028 return ira->codegen->invalid_inst_gen;
......@@ -11051,12 +11051,12 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV
1105111051 return ir_build_var_decl_gen(ira, decl_var_instruction->base.scope, decl_var_instruction->base.source_node, var, var_ptr);
1105211052}
1105311053
11054static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport *instruction) {
11055 IrInstGen *target = instruction->target->child;
11054static Stage1AirInst *ir_analyze_instruction_export(IrAnalyze *ira, Stage1ZirInstExport *instruction) {
11055 Stage1AirInst *target = instruction->target->child;
1105611056 if (type_is_invalid(target->value->type))
1105711057 return ira->codegen->invalid_inst_gen;
1105811058
11059 IrInstGen *options = instruction->options->child;
11059 Stage1AirInst *options = instruction->options->child;
1106011060 if (type_is_invalid(options->value->type))
1106111061 return ira->codegen->invalid_inst_gen;
1106211062
......@@ -11065,29 +11065,29 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport
1106511065
1106611066 TypeStructField *name_field = find_struct_type_field(options_type, buf_create_from_str("name"));
1106711067 src_assert(name_field != nullptr, instruction->base.source_node);
11068 IrInstGen *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field);
11068 Stage1AirInst *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field);
1106911069 if (type_is_invalid(name_inst->value->type))
1107011070 return ira->codegen->invalid_inst_gen;
1107111071
1107211072 TypeStructField *linkage_field = find_struct_type_field(options_type, buf_create_from_str("linkage"));
1107311073 src_assert(linkage_field != nullptr, instruction->base.source_node);
11074 IrInstGen *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field);
11074 Stage1AirInst *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field);
1107511075 if (type_is_invalid(linkage_inst->value->type))
1107611076 return ira->codegen->invalid_inst_gen;
1107711077
1107811078 TypeStructField *section_field = find_struct_type_field(options_type, buf_create_from_str("section"));
1107911079 src_assert(section_field != nullptr, instruction->base.source_node);
11080 IrInstGen *section_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, section_field);
11080 Stage1AirInst *section_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, section_field);
1108111081 if (type_is_invalid(section_inst->value->type))
1108211082 return ira->codegen->invalid_inst_gen;
1108311083
1108411084 // The `section` field is optional, we have to unwrap it first
11085 IrInstGen *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, section_inst);
11085 Stage1AirInst *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, section_inst);
1108611086 bool is_non_null;
1108711087 if (!ir_resolve_bool(ira, non_null_check, &is_non_null))
1108811088 return ira->codegen->invalid_inst_gen;
1108911089
11090 IrInstGen *section_str_inst = nullptr;
11090 Stage1AirInst *section_str_inst = nullptr;
1109111091 if (is_non_null) {
1109211092 section_str_inst = ir_analyze_optional_value_payload_value(ira, instruction->base.scope, instruction->base.source_node, section_inst, false);
1109311093 if (type_is_invalid(section_str_inst->value->type))
......@@ -11307,10 +11307,10 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport
1130711307 }
1130811308
1130911309 // TODO audit the various ways to use @export
11310 if (want_var_export && target->id == IrInstGenIdLoadPtr) {
11311 IrInstGenLoadPtr *load_ptr = reinterpret_cast<IrInstGenLoadPtr *>(target);
11312 if (load_ptr->ptr->id == IrInstGenIdVarPtr) {
11313 IrInstGenVarPtr *var_ptr = reinterpret_cast<IrInstGenVarPtr *>(load_ptr->ptr);
11310 if (want_var_export && target->id == Stage1AirInstIdLoadPtr) {
11311 Stage1AirInstLoadPtr *load_ptr = reinterpret_cast<Stage1AirInstLoadPtr *>(target);
11312 if (load_ptr->ptr->id == Stage1AirInstIdVarPtr) {
11313 Stage1AirInstVarPtr *var_ptr = reinterpret_cast<Stage1AirInstVarPtr *>(load_ptr->ptr);
1131411314 ZigVar *var = var_ptr->var;
1131511315 add_var_export(ira->codegen, var, buf_ptr(symbol_name), global_linkage_id);
1131611316 var->section_name = section_name;
......@@ -11322,12 +11322,12 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport
1132211322
1132311323static void add_link_lib_symbol(IrAnalyze *ira, Buf *lib_name, Buf *symbol_name, AstNode *source_node);
1132411324
11325static IrInstGen *ir_analyze_instruction_extern(IrAnalyze *ira, IrInstSrcExtern *instruction) {
11326 IrInstGen *type_inst = instruction->type->child;
11325static Stage1AirInst *ir_analyze_instruction_extern(IrAnalyze *ira, Stage1ZirInstExtern *instruction) {
11326 Stage1AirInst *type_inst = instruction->type->child;
1132711327 if (type_is_invalid(type_inst->value->type))
1132811328 return ira->codegen->invalid_inst_gen;
1132911329
11330 IrInstGen *options = instruction->options->child;
11330 Stage1AirInst *options = instruction->options->child;
1133111331 if (type_is_invalid(options->value->type))
1133211332 return ira->codegen->invalid_inst_gen;
1133311333
......@@ -11336,35 +11336,35 @@ static IrInstGen *ir_analyze_instruction_extern(IrAnalyze *ira, IrInstSrcExtern
1133611336
1133711337 TypeStructField *name_field = find_struct_type_field(options_type, buf_create_from_str("name"));
1133811338 src_assert(name_field != nullptr, instruction->base.source_node);
11339 IrInstGen *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field);
11339 Stage1AirInst *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field);
1134011340 if (type_is_invalid(name_inst->value->type))
1134111341 return ira->codegen->invalid_inst_gen;
1134211342
1134311343 TypeStructField *linkage_field = find_struct_type_field(options_type, buf_create_from_str("linkage"));
1134411344 src_assert(linkage_field != nullptr, instruction->base.source_node);
11345 IrInstGen *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field);
11345 Stage1AirInst *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field);
1134611346 if (type_is_invalid(linkage_inst->value->type))
1134711347 return ira->codegen->invalid_inst_gen;
1134811348
1134911349 TypeStructField *is_thread_local_field = find_struct_type_field(options_type, buf_create_from_str("is_thread_local"));
1135011350 src_assert(is_thread_local_field != nullptr, instruction->base.source_node);
11351 IrInstGen *is_thread_local_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, is_thread_local_field);
11351 Stage1AirInst *is_thread_local_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, is_thread_local_field);
1135211352 if (type_is_invalid(is_thread_local_inst->value->type))
1135311353 return ira->codegen->invalid_inst_gen;
1135411354
1135511355 TypeStructField *library_name_field = find_struct_type_field(options_type, buf_create_from_str("library_name"));
1135611356 src_assert(library_name_field != nullptr, instruction->base.source_node);
11357 IrInstGen *library_name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, library_name_field);
11357 Stage1AirInst *library_name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, library_name_field);
1135811358 if (type_is_invalid(library_name_inst->value->type))
1135911359 return ira->codegen->invalid_inst_gen;
1136011360
1136111361 // The `library_name` field is optional, we have to unwrap it first
11362 IrInstGen *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, library_name_inst);
11362 Stage1AirInst *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, library_name_inst);
1136311363 bool is_non_null;
1136411364 if (!ir_resolve_bool(ira, non_null_check, &is_non_null))
1136511365 return ira->codegen->invalid_inst_gen;
1136611366
11367 IrInstGen *library_name_val_inst = nullptr;
11367 Stage1AirInst *library_name_val_inst = nullptr;
1136811368 if (is_non_null) {
1136911369 library_name_val_inst = ir_analyze_optional_value_payload_value(ira, instruction->base.scope, instruction->base.source_node, library_name_inst, false);
1137011370 if (type_is_invalid(library_name_val_inst->value->type))
......@@ -11445,14 +11445,14 @@ static bool ira_has_err_ret_trace(IrAnalyze *ira) {
1144511445 return fn != nullptr && fn->calls_or_awaits_errorable_fn && ira->codegen->have_err_ret_tracing;
1144611446}
1144711447
11448static IrInstGen *ir_analyze_instruction_error_return_trace(IrAnalyze *ira,
11449 IrInstSrcErrorReturnTrace *instruction)
11448static Stage1AirInst *ir_analyze_instruction_error_return_trace(IrAnalyze *ira,
11449 Stage1ZirInstErrorReturnTrace *instruction)
1145011450{
1145111451 ZigType *ptr_to_stack_trace_type = get_pointer_to_type(ira->codegen, get_stack_trace_type(ira->codegen), false);
1145211452 if (instruction->optional == IrInstErrorReturnTraceNull) {
1145311453 ZigType *optional_type = get_optional_type(ira->codegen, ptr_to_stack_trace_type);
1145411454 if (!ira_has_err_ret_trace(ira)) {
11455 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, optional_type);
11455 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, optional_type);
1145611456 ZigValue *out_val = result->value;
1145711457 assert(get_src_ptr_type(optional_type) != nullptr);
1145811458 out_val->data.x_ptr.special = ConstPtrSpecialHardCodedAddr;
......@@ -11468,8 +11468,8 @@ static IrInstGen *ir_analyze_instruction_error_return_trace(IrAnalyze *ira,
1146811468 }
1146911469}
1147011470
11471static IrInstGen *ir_analyze_instruction_error_union(IrAnalyze *ira, IrInstSrcErrorUnion *instruction) {
11472 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
11471static Stage1AirInst *ir_analyze_instruction_error_union(IrAnalyze *ira, Stage1ZirInstErrorUnion *instruction) {
11472 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
1147311473 result->value->special = ConstValSpecialLazy;
1147411474
1147511475 LazyValueErrUnionType *lazy_err_union_type = heap::c_allocator.create<LazyValueErrUnionType>();
......@@ -11488,7 +11488,7 @@ static IrInstGen *ir_analyze_instruction_error_union(IrAnalyze *ira, IrInstSrcEr
1148811488 return result;
1148911489}
1149011490
11491static IrInstGen *ir_analyze_alloca(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *var_type,
11491static Stage1AirInst *ir_analyze_alloca(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *var_type,
1149211492 uint32_t align, const char *name_hint, bool force_comptime)
1149311493{
1149411494 Error err;
......@@ -11497,7 +11497,7 @@ static IrInstGen *ir_analyze_alloca(IrAnalyze *ira, Scope *scope, AstNode *sourc
1149711497 pointee->special = ConstValSpecialUndef;
1149811498 pointee->llvm_align = align;
1149911499
11500 IrInstGenAlloca *result = ir_build_alloca_gen(ira, scope, source_node, align, name_hint);
11500 Stage1AirInstAlloca *result = ir_build_alloca_gen(ira, scope, source_node, align, name_hint);
1150111501 result->base.value->special = ConstValSpecialStatic;
1150211502 result->base.value->data.x_ptr.special = ConstPtrSpecialRef;
1150311503 result->base.value->data.x_ptr.mut = force_comptime ? ConstPtrMutComptimeVar : ConstPtrMutInfer;
......@@ -11572,7 +11572,7 @@ static bool type_can_bit_cast(ZigType *t) {
1157211572 }
1157311573}
1157411574
11575static void set_up_result_loc_for_inferred_comptime(IrAnalyze *ira, IrInstGen *ptr) {
11575static void set_up_result_loc_for_inferred_comptime(IrAnalyze *ira, Stage1AirInst *ptr) {
1157611576 ZigValue *undef_child = ira->codegen->pass1_arena->create<ZigValue>();
1157711577 undef_child->type = ptr->value->type->data.pointer.child_type;
1157811578 undef_child->special = ConstValSpecialUndef;
......@@ -11611,12 +11611,12 @@ static Error ir_result_has_type(IrAnalyze *ira, ResultLoc *result_loc, bool *out
1161111611 zig_unreachable();
1161211612}
1161311613
11614static IrInstGen *ir_resolve_no_result_loc(IrAnalyze *ira, IrInstSrc *suspend_source_instr,
11614static Stage1AirInst *ir_resolve_no_result_loc(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr,
1161511615 ResultLoc *result_loc, ZigType *value_type)
1161611616{
1161711617 if (type_is_invalid(value_type))
1161811618 return ira->codegen->invalid_inst_gen;
11619 IrInstGenAlloca *alloca_gen = ir_build_alloca_gen(ira, suspend_source_instr->scope,
11619 Stage1AirInstAlloca *alloca_gen = ir_build_alloca_gen(ira, suspend_source_instr->scope,
1162011620 suspend_source_instr->source_node, 0, "");
1162111621 alloca_gen->base.value->type = get_pointer_to_type_extra(ira->codegen, value_type, false, false,
1162211622 PtrLenSingle, 0, 0, 0, false);
......@@ -11632,9 +11632,9 @@ static IrInstGen *ir_resolve_no_result_loc(IrAnalyze *ira, IrInstSrc *suspend_so
1163211632
1163311633static bool result_loc_is_discard(ResultLoc *result_loc_pass1) {
1163411634 if (result_loc_pass1->id == ResultLocIdInstruction &&
11635 result_loc_pass1->source_instruction->id == IrInstSrcIdConst)
11635 result_loc_pass1->source_instruction->id == Stage1ZirInstIdConst)
1163611636 {
11637 IrInstSrcConst *const_inst = reinterpret_cast<IrInstSrcConst *>(result_loc_pass1->source_instruction);
11637 Stage1ZirInstConst *const_inst = reinterpret_cast<Stage1ZirInstConst *>(result_loc_pass1->source_instruction);
1163811638 if (value_is_comptime(const_inst->value) &&
1163911639 const_inst->value->type->id == ZigTypeIdPointer &&
1164011640 const_inst->value->data.x_ptr.special == ConstPtrSpecialDiscard)
......@@ -11646,8 +11646,8 @@ static bool result_loc_is_discard(ResultLoc *result_loc_pass1) {
1164611646}
1164711647
1164811648// when calling this function, at the callsite must check for result type noreturn and propagate it up
11649static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_source_instr,
11650 ResultLoc *result_loc, ZigType *value_type, IrInstGen *value, bool force_runtime,
11649static Stage1AirInst *ir_resolve_result_raw(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr,
11650 ResultLoc *result_loc, ZigType *value_type, Stage1AirInst *value, bool force_runtime,
1165111651 bool allow_discard)
1165211652{
1165311653 Error err;
......@@ -11672,8 +11672,8 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
1167211672 }
1167311673 case ResultLocIdVar: {
1167411674 ResultLocVar *result_loc_var = reinterpret_cast<ResultLocVar *>(result_loc);
11675 assert(result_loc->source_instruction->id == IrInstSrcIdAlloca);
11676 IrInstSrcAlloca *alloca_src = reinterpret_cast<IrInstSrcAlloca *>(result_loc->source_instruction);
11675 assert(result_loc->source_instruction->id == Stage1ZirInstIdAlloca);
11676 Stage1ZirInstAlloca *alloca_src = reinterpret_cast<Stage1ZirInstAlloca *>(result_loc->source_instruction);
1167711677
1167811678 ZigVar *var = result_loc_var->var;
1167911679 if (var->var_type != nullptr && !ir_get_var_is_comptime(var)) {
......@@ -11702,7 +11702,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
1170211702 if (alloca_src->align != nullptr && !ir_resolve_align(ira, alloca_src->align->child, nullptr, &align)) {
1170311703 return ira->codegen->invalid_inst_gen;
1170411704 }
11705 IrInstGen *alloca_gen = ir_analyze_alloca(ira,
11705 Stage1AirInst *alloca_gen = ir_analyze_alloca(ira,
1170611706 result_loc->source_instruction->scope,
1170711707 result_loc->source_instruction->source_node, value_type,
1170811708 align, alloca_src->name_hint, force_comptime);
......@@ -11739,7 +11739,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
1173911739 ResultLocPeerParent *peer_parent = result_peer->parent;
1174011740
1174111741 if (peer_parent->peers.length == 1) {
11742 IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,
11742 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,
1174311743 value_type, value, force_runtime, true);
1174411744 result_peer->suspend_pos.basic_block_index = SIZE_MAX;
1174511745 result_peer->suspend_pos.instruction_index = SIZE_MAX;
......@@ -11766,7 +11766,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
1176611766 return ira->codegen->invalid_inst_gen;
1176711767 if (peer_parent_has_type) {
1176811768 peer_parent->skipped = true;
11769 IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,
11769 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,
1177011770 value_type, value, force_runtime || !is_condition_comptime, true);
1177111771 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||
1177211772 parent_result_loc->value->type->id == ZigTypeIdUnreachable)
......@@ -11783,7 +11783,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
1178311783 if (peer_parent->end_bb->suspend_instruction_ref == nullptr) {
1178411784 peer_parent->end_bb->suspend_instruction_ref = suspend_source_instr;
1178511785 }
11786 IrInstGen *unreach_inst = ira_suspend(ira, suspend_source_instr, result_peer->next_bb,
11786 Stage1AirInst *unreach_inst = ira_suspend(ira, suspend_source_instr, result_peer->next_bb,
1178711787 &result_peer->suspend_pos);
1178811788 if (result_peer->next_bb == nullptr) {
1178911789 ir_start_next_bb(ira);
......@@ -11791,7 +11791,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
1179111791 return unreach_inst;
1179211792 }
1179311793
11794 IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,
11794 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent,
1179511795 peer_parent->resolved_type, nullptr, force_runtime, true);
1179611796 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||
1179711797 parent_result_loc->value->type->id == ZigTypeIdUnreachable)
......@@ -11814,7 +11814,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
1181411814 return ir_resolve_no_result_loc(ira, suspend_source_instr, result_loc, value_type);
1181511815 }
1181611816
11817 IrInstGen *casted_value;
11817 Stage1AirInst *casted_value;
1181811818 if (value != nullptr) {
1181911819 casted_value = ir_implicit_cast2(ira, suspend_source_instr->scope,
1182011820 suspend_source_instr->source_node, value, dest_type);
......@@ -11825,7 +11825,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
1182511825 casted_value = nullptr;
1182611826 }
1182711827
11828 IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_cast->parent,
11828 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_cast->parent,
1182911829 dest_type, casted_value, force_runtime, true);
1183011830 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||
1183111831 parent_result_loc->value->type->id == ZigTypeIdUnreachable)
......@@ -11922,7 +11922,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
1192211922 return ira->codegen->invalid_inst_gen;
1192311923 }
1192411924
11925 IrInstGen *bitcasted_value;
11925 Stage1AirInst *bitcasted_value;
1192611926 if (value != nullptr) {
1192711927 bitcasted_value = ir_analyze_bit_cast(ira, result_loc->source_instruction->scope,
1192811928 result_loc->source_instruction->source_node, value, dest_type);
......@@ -11936,7 +11936,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
1193611936 }
1193711937
1193811938 bool parent_was_written = result_bit_cast->parent->written;
11939 IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_bit_cast->parent,
11939 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_bit_cast->parent,
1194011940 dest_type, bitcasted_value, force_runtime, true);
1194111941 if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) ||
1194211942 parent_result_loc->value->type->id == ZigTypeIdUnreachable)
......@@ -11987,15 +11987,15 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc
1198711987 zig_unreachable();
1198811988}
1198911989
11990static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_instr,
11991 ResultLoc *result_loc_pass1, ZigType *value_type, IrInstGen *value, bool force_runtime,
11990static Stage1AirInst *ir_resolve_result(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr,
11991 ResultLoc *result_loc_pass1, ZigType *value_type, Stage1AirInst *value, bool force_runtime,
1199211992 bool allow_discard)
1199311993{
1199411994 if (!allow_discard && result_loc_is_discard(result_loc_pass1)) {
1199511995 result_loc_pass1 = no_result_loc();
1199611996 }
1199711997 bool was_written = result_loc_pass1->written;
11998 IrInstGen *result_loc = ir_resolve_result_raw(ira, suspend_source_instr, result_loc_pass1, value_type,
11998 Stage1AirInst *result_loc = ir_resolve_result_raw(ira, suspend_source_instr, result_loc_pass1, value_type,
1199911999 value, force_runtime, allow_discard);
1200012000 if (result_loc == nullptr || result_loc->value->type->id == ZigTypeIdUnreachable ||
1200112001 type_is_invalid(result_loc->value->type))
......@@ -12012,7 +12012,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in
1201212012 InferredStructField *isf = result_loc->value->type->data.pointer.inferred_struct_field;
1201312013 if (isf != nullptr) {
1201412014 TypeStructField *field;
12015 IrInstGen *casted_ptr;
12015 Stage1AirInst *casted_ptr;
1201612016 if (isf->already_resolved) {
1201712017 field = find_struct_type_field(isf->inferred_struct_type, isf->field_name);
1201812018 casted_ptr = result_loc;
......@@ -12102,7 +12102,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in
1210212102 return ir_analyze_unwrap_err_code(ira, suspend_source_instr->scope,
1210312103 suspend_source_instr->source_node, result_loc, true);
1210412104 } else {
12105 IrInstGen *unwrapped_err_ptr = ir_analyze_unwrap_error_payload(ira,
12105 Stage1AirInst *unwrapped_err_ptr = ir_analyze_unwrap_error_payload(ira,
1210612106 suspend_source_instr->scope, suspend_source_instr->source_node,
1210712107 result_loc, false, true);
1210812108 ZigType *actual_payload_type = actual_elem_type->data.error_union.payload_type;
......@@ -12119,7 +12119,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in
1211912119 return result_loc;
1212012120}
1212112121
12122static IrInstGen *ir_analyze_instruction_resolve_result(IrAnalyze *ira, IrInstSrcResolveResult *instruction) {
12122static Stage1AirInst *ir_analyze_instruction_resolve_result(IrAnalyze *ira, Stage1ZirInstResolveResult *instruction) {
1212312123 ZigType *implicit_elem_type;
1212412124 if (instruction->ty == nullptr) {
1212512125 if (instruction->result_loc->id == ResultLocIdCast) {
......@@ -12158,7 +12158,7 @@ static IrInstGen *ir_analyze_instruction_resolve_result(IrAnalyze *ira, IrInstSr
1215812158 if (type_is_invalid(implicit_elem_type))
1215912159 return ira->codegen->invalid_inst_gen;
1216012160 }
12161 IrInstGen *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
12161 Stage1AirInst *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
1216212162 implicit_elem_type, nullptr, false, true);
1216312163 if (result_loc != nullptr)
1216412164 return result_loc;
......@@ -12178,9 +12178,9 @@ static IrInstGen *ir_analyze_instruction_resolve_result(IrAnalyze *ira, IrInstSr
1217812178 return result_loc;
1217912179 }
1218012180
12181 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, implicit_elem_type);
12181 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, implicit_elem_type);
1218212182 result->value->special = ConstValSpecialUndef;
12183 IrInstGen *ptr = ir_get_ref(ira, instruction->base.scope, instruction->base.source_node, result, false, false);
12183 Stage1AirInst *ptr = ir_get_ref(ira, instruction->base.scope, instruction->base.source_node, result, false, false);
1218412184 ptr->value->data.x_ptr.mut = ConstPtrMutComptimeVar;
1218512185 return ptr;
1218612186}
......@@ -12204,7 +12204,7 @@ static void ir_reset_result(ResultLoc *result_loc) {
1220412204 break;
1220512205 }
1220612206 case ResultLocIdVar: {
12207 IrInstSrcAlloca *alloca_src = reinterpret_cast<IrInstSrcAlloca *>(result_loc->source_instruction);
12207 Stage1ZirInstAlloca *alloca_src = reinterpret_cast<Stage1ZirInstAlloca *>(result_loc->source_instruction);
1220812208 alloca_src->base.child = nullptr;
1220912209 break;
1221012210 }
......@@ -12220,14 +12220,14 @@ static void ir_reset_result(ResultLoc *result_loc) {
1222012220 }
1222112221}
1222212222
12223static IrInstGen *ir_analyze_instruction_reset_result(IrAnalyze *ira, IrInstSrcResetResult *instruction) {
12223static Stage1AirInst *ir_analyze_instruction_reset_result(IrAnalyze *ira, Stage1ZirInstResetResult *instruction) {
1222412224 ir_reset_result(instruction->result_loc);
1222512225 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
1222612226}
1222712227
12228static IrInstGen *get_async_call_result_loc(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12229 ZigType *fn_ret_type, bool is_async_call_builtin, IrInstGen **args_ptr, size_t args_len,
12230 IrInstGen *ret_ptr_uncasted)
12228static Stage1AirInst *get_async_call_result_loc(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12229 ZigType *fn_ret_type, bool is_async_call_builtin, Stage1AirInst **args_ptr, size_t args_len,
12230 Stage1AirInst *ret_ptr_uncasted)
1223112231{
1223212232 src_assert(is_async_call_builtin, source_node);
1223312233 if (type_is_invalid(ret_ptr_uncasted->value->type))
......@@ -12239,9 +12239,9 @@ static IrInstGen *get_async_call_result_loc(IrAnalyze *ira, Scope *scope, AstNod
1223912239 return ir_implicit_cast(ira, ret_ptr_uncasted, get_pointer_to_type(ira->codegen, fn_ret_type, false));
1224012240}
1224112241
12242static IrInstGen *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry,
12243 ZigType *fn_type, IrInstGen *fn_ref, IrInstGen **casted_args, size_t arg_count,
12244 IrInstGen *casted_new_stack, bool is_async_call_builtin, IrInstGen *ret_ptr_uncasted,
12242static Stage1AirInst *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry,
12243 ZigType *fn_type, Stage1AirInst *fn_ref, Stage1AirInst **casted_args, size_t arg_count,
12244 Stage1AirInst *casted_new_stack, bool is_async_call_builtin, Stage1AirInst *ret_ptr_uncasted,
1224512245 ResultLoc *call_result_loc)
1224612246{
1224712247 if (fn_entry == nullptr) {
......@@ -12257,20 +12257,20 @@ static IrInstGen *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *s
1225712257 }
1225812258 if (casted_new_stack != nullptr) {
1225912259 ZigType *fn_ret_type = fn_type->data.fn.fn_type_id.return_type;
12260 IrInstGen *ret_ptr = get_async_call_result_loc(ira, scope, source_node, fn_ret_type, is_async_call_builtin,
12260 Stage1AirInst *ret_ptr = get_async_call_result_loc(ira, scope, source_node, fn_ret_type, is_async_call_builtin,
1226112261 casted_args, arg_count, ret_ptr_uncasted);
1226212262 if (ret_ptr != nullptr && type_is_invalid(ret_ptr->value->type))
1226312263 return ira->codegen->invalid_inst_gen;
1226412264
1226512265 ZigType *anyframe_type = get_any_frame_type(ira->codegen, fn_ret_type);
1226612266
12267 IrInstGenCall *call_gen = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref,
12267 Stage1AirInstCall *call_gen = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref,
1226812268 arg_count, casted_args, CallModifierAsync, casted_new_stack,
1226912269 is_async_call_builtin, ret_ptr, anyframe_type);
1227012270 return &call_gen->base;
1227112271 } else {
1227212272 ZigType *frame_type = get_fn_frame_type(ira->codegen, fn_entry);
12273 IrInstGen *result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc,
12273 Stage1AirInst *result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc,
1227412274 frame_type, nullptr, true, false);
1227512275 if (type_is_invalid(result_loc->value->type) || result_loc->value->type->id == ZigTypeIdUnreachable) {
1227612276 return result_loc;
......@@ -12285,12 +12285,12 @@ static IrInstGen *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *s
1228512285 }
1228612286}
1228712287static bool ir_analyze_fn_call_inline_arg(IrAnalyze *ira, AstNode *fn_proto_node,
12288 IrInstGen *arg, Scope **exec_scope, size_t *next_proto_i)
12288 Stage1AirInst *arg, Scope **exec_scope, size_t *next_proto_i)
1228912289{
1229012290 AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(*next_proto_i);
1229112291 assert(param_decl_node->type == NodeTypeParamDecl);
1229212292
12293 IrInstGen *casted_arg;
12293 Stage1AirInst *casted_arg;
1229412294 if (param_decl_node->data.param_decl.anytype_token == 0) {
1229512295 AstNode *param_type_node = param_decl_node->data.param_decl.type;
1229612296 ZigType *param_type = ir_analyze_type_expr(ira, *exec_scope, param_type_node);
......@@ -12318,15 +12318,15 @@ static bool ir_analyze_fn_call_inline_arg(IrAnalyze *ira, AstNode *fn_proto_node
1231812318}
1231912319
1232012320static bool ir_analyze_fn_call_generic_arg(IrAnalyze *ira, AstNode *fn_proto_node,
12321 IrInstGen *arg, AstNode *arg_src, Scope **child_scope, size_t *next_proto_i,
12322 GenericFnTypeId *generic_id, FnTypeId *fn_type_id, IrInstGen **casted_args,
12321 Stage1AirInst *arg, AstNode *arg_src, Scope **child_scope, size_t *next_proto_i,
12322 GenericFnTypeId *generic_id, FnTypeId *fn_type_id, Stage1AirInst **casted_args,
1232312323 ZigFn *impl_fn)
1232412324{
1232512325 AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(*next_proto_i);
1232612326 assert(param_decl_node->type == NodeTypeParamDecl);
1232712327 bool is_var_args = param_decl_node->data.param_decl.is_var_args;
1232812328 bool arg_part_of_generic_id = false;
12329 IrInstGen *casted_arg;
12329 Stage1AirInst *casted_arg;
1233012330
1233112331 ZigType *param_info_type = nullptr;
1233212332 if (is_var_args) {
......@@ -12414,7 +12414,7 @@ static bool ir_analyze_fn_call_generic_arg(IrAnalyze *ira, AstNode *fn_proto_nod
1241412414 return true;
1241512415}
1241612416
12417static IrInstGen *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) {
12417static Stage1AirInst *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) {
1241812418 while (var->next_var != nullptr) {
1241912419 var = var->next_var;
1242012420 }
......@@ -12433,7 +12433,7 @@ static IrInstGen *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_n
1243312433 bool comptime_var_mem = ir_get_var_is_comptime(var);
1243412434 bool linkage_makes_it_runtime = var->decl_node->data.variable_declaration.is_extern;
1243512435
12436 IrInstGen *result = ir_build_var_ptr_gen(ira, scope, source_node, var);
12436 Stage1AirInst *result = ir_build_var_ptr_gen(ira, scope, source_node, var);
1243712437 result->value->type = var_ptr_type;
1243812438
1243912439 if (!linkage_makes_it_runtime && !var->is_thread_local && value_is_comptime(var->const_value)) {
......@@ -12482,8 +12482,8 @@ static void mark_comptime_value_escape(IrAnalyze *ira, Scope *scope, AstNode *so
1248212482 }
1248312483}
1248412484
12485static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12486 IrInstGen *ptr, IrInstGen *uncasted_value, bool allow_write_through_const)
12485static Stage1AirInst *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12486 Stage1AirInst *ptr, Stage1AirInst *uncasted_value, bool allow_write_through_const)
1248712487{
1248812488 assert(ptr->value->type->id == ZigTypeIdPointer);
1248912489
......@@ -12503,7 +12503,7 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so
1250312503 }
1250412504
1250512505 ZigType *child_type = ptr->value->type->data.pointer.child_type;
12506 IrInstGen *value = ir_implicit_cast(ira, uncasted_value, child_type);
12506 Stage1AirInst *value = ir_implicit_cast(ira, uncasted_value, child_type);
1250712507 if (type_is_invalid(value->value->type))
1250812508 return ira->codegen->invalid_inst_gen;
1250912509
......@@ -12583,14 +12583,14 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so
1258312583 }
1258412584
1258512585 // If this is a store to a pointer with a runtime-known vector index,
12586 // we have to figure out the IrInstGen which represents the index and
12587 // emit a IrInstGenVectorStoreElem, or emit a compile error
12586 // we have to figure out the Stage1AirInst which represents the index and
12587 // emit a Stage1AirInstVectorStoreElem, or emit a compile error
1258812588 // explaining why it is impossible for this store to work. Which is that
1258912589 // the pointer address is of the vector; without the element index being known
1259012590 // we cannot properly perform the insertion.
1259112591 if (ptr->value->type->data.pointer.vector_index == VECTOR_INDEX_RUNTIME) {
12592 if (ptr->id == IrInstGenIdElemPtr) {
12593 IrInstGenElemPtr *elem_ptr = (IrInstGenElemPtr *)ptr;
12592 if (ptr->id == Stage1AirInstIdElemPtr) {
12593 Stage1AirInstElemPtr *elem_ptr = (Stage1AirInstElemPtr *)ptr;
1259412594 return ir_build_vector_store_elem(ira, scope, source_node, elem_ptr->array_ptr,
1259512595 elem_ptr->elem_index, value);
1259612596 }
......@@ -12603,8 +12603,8 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so
1260312603 return ir_build_store_ptr_gen(ira, scope, source_node, ptr, value);
1260412604}
1260512605
12606static IrInstGen *analyze_casted_new_stack(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12607 IrInstGen *new_stack, AstNode *new_stack_src, bool is_async_call_builtin, ZigFn *fn_entry)
12606static Stage1AirInst *analyze_casted_new_stack(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12607 Stage1AirInst *new_stack, AstNode *new_stack_src, bool is_async_call_builtin, ZigFn *fn_entry)
1260812608{
1260912609 if (new_stack == nullptr)
1261012610 return nullptr;
......@@ -12637,11 +12637,11 @@ static IrInstGen *analyze_casted_new_stack(IrAnalyze *ira, Scope *scope, AstNode
1263712637 }
1263812638}
1263912639
12640static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12641 ZigFn *fn_entry, ZigType *fn_type, IrInstGen *fn_ref,
12642 IrInstGen *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier,
12643 IrInstGen *new_stack, AstNode *new_stack_src, bool is_async_call_builtin,
12644 IrInstGen **args_ptr, size_t args_len, IrInstGen *ret_ptr, ResultLoc *call_result_loc)
12640static Stage1AirInst *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *source_node,
12641 ZigFn *fn_entry, ZigType *fn_type, Stage1AirInst *fn_ref,
12642 Stage1AirInst *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier,
12643 Stage1AirInst *new_stack, AstNode *new_stack_src, bool is_async_call_builtin,
12644 Stage1AirInst **args_ptr, size_t args_len, Stage1AirInst *ret_ptr, ResultLoc *call_result_loc)
1264512645{
1264612646 Error err;
1264712647 FnTypeId *fn_type_id = &fn_type->data.fn.fn_type_id;
......@@ -12729,7 +12729,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1272912729 first_arg_known_bare = param_type->id != ZigTypeIdPointer;
1273012730 }
1273112731
12732 IrInstGen *first_arg;
12732 Stage1AirInst *first_arg;
1273312733 if (!first_arg_known_bare) {
1273412734 first_arg = first_arg_ptr;
1273512735 } else {
......@@ -12743,7 +12743,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1274312743 }
1274412744
1274512745 for (size_t call_i = 0; call_i < args_len; call_i += 1) {
12746 IrInstGen *old_arg = args_ptr[call_i];
12746 Stage1AirInst *old_arg = args_ptr[call_i];
1274712747
1274812748 if (!ir_analyze_fn_call_inline_arg(ira, fn_proto_node, old_arg, &exec_scope, &next_proto_i))
1274912749 return ira->codegen->invalid_inst_gen;
......@@ -12841,7 +12841,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1284112841 }
1284212842 }
1284312843
12844 IrInstGen *new_instruction = ir_const_move(ira, scope, source_node, result);
12844 Stage1AirInst *new_instruction = ir_const_move(ira, scope, source_node, result);
1284512845 return ir_finish_anal(ira, new_instruction);
1284612846 }
1284712847
......@@ -12854,7 +12854,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1285412854
1285512855 size_t new_fn_arg_count = first_arg_1_or_0 + args_len;
1285612856
12857 IrInstGen **casted_args = heap::c_allocator.allocate<IrInstGen *>(new_fn_arg_count);
12857 Stage1AirInst **casted_args = heap::c_allocator.allocate<Stage1AirInst *>(new_fn_arg_count);
1285812858
1285912859 // Fork a scope of the function with known values for the parameters.
1286012860 Scope *parent_scope = fn_entry->fndef_scope->base.parent;
......@@ -12887,7 +12887,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1288712887 first_arg_known_bare = param_type->id != ZigTypeIdPointer;
1288812888 }
1288912889
12890 IrInstGen *first_arg;
12890 Stage1AirInst *first_arg;
1289112891 if (!first_arg_known_bare) {
1289212892 first_arg = first_arg_ptr;
1289312893 } else {
......@@ -12907,7 +12907,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1290712907 ZigFn *parent_fn_entry = ira->fn;
1290812908 assert(parent_fn_entry);
1290912909 for (size_t call_i = 0; call_i < args_len; call_i += 1) {
12910 IrInstGen *arg = args_ptr[call_i];
12910 Stage1AirInst *arg = args_ptr[call_i];
1291112911
1291212912 AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(next_proto_i);
1291312913 assert(param_decl_node->type == NodeTypeParamDecl);
......@@ -12932,7 +12932,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1293212932 {
1293312933 return ira->codegen->invalid_inst_gen;
1293412934 }
12935 IrInstGenConst *const_instruction = ir_create_inst_noval<IrInstGenConst>(&ira->new_irb,
12935 Stage1AirInstConst *const_instruction = ir_create_inst_noval<Stage1AirInstConst>(&ira->new_irb,
1293612936 impl_fn->child_scope, fn_proto_node->data.fn_proto.align_expr);
1293712937 const_instruction->base.value = align_result;
1293812938
......@@ -13015,20 +13015,20 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1301513015 parent_fn_entry->calls_or_awaits_errorable_fn = true;
1301613016 }
1301713017
13018 IrInstGen *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack,
13018 Stage1AirInst *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack,
1301913019 new_stack_src, is_async_call_builtin, impl_fn);
1302013020 if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type))
1302113021 return ira->codegen->invalid_inst_gen;
1302213022
1302313023 size_t impl_param_count = impl_fn_type_id->param_count;
1302413024 if (modifier == CallModifierAsync) {
13025 IrInstGen *result = ir_analyze_async_call(ira, scope, source_node, impl_fn, impl_fn->type_entry,
13025 Stage1AirInst *result = ir_analyze_async_call(ira, scope, source_node, impl_fn, impl_fn->type_entry,
1302613026 nullptr, casted_args, impl_param_count, casted_new_stack, is_async_call_builtin, ret_ptr,
1302713027 call_result_loc);
1302813028 return ir_finish_anal(ira, result);
1302913029 }
1303013030
13031 IrInstGen *result_loc;
13031 Stage1AirInst *result_loc;
1303213032 if (handle_is_ptr(ira->codegen, impl_fn_type_id->return_type)) {
1303313033 result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc,
1303413034 impl_fn_type_id->return_type, nullptr, true, false);
......@@ -13041,9 +13041,9 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1304113041 return ira->codegen->invalid_inst_gen;
1304213042 }
1304313043
13044 IrInstGen *dummy_value = ir_const(ira, scope, source_node, impl_fn_type_id->return_type);
13044 Stage1AirInst *dummy_value = ir_const(ira, scope, source_node, impl_fn_type_id->return_type);
1304513045 dummy_value->value->special = ConstValSpecialRuntime;
13046 IrInstGen *dummy_result = ir_implicit_cast2(ira, scope, source_node,
13046 Stage1AirInst *dummy_result = ir_implicit_cast2(ira, scope, source_node,
1304713047 dummy_value, result_loc->value->type->data.pointer.child_type);
1304813048 if (type_is_invalid(dummy_result->value->type))
1304913049 return ira->codegen->invalid_inst_gen;
......@@ -13073,7 +13073,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1307313073 parent_fn_entry->inferred_async_fn = impl_fn;
1307413074 }
1307513075
13076 IrInstGenCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node,
13076 Stage1AirInstCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node,
1307713077 impl_fn, nullptr, impl_param_count, casted_args, modifier, casted_new_stack,
1307813078 is_async_call_builtin, result_loc, impl_fn_type_id->return_type);
1307913079
......@@ -13092,7 +13092,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1309213092 }
1309313093
1309413094
13095 IrInstGen **casted_args = heap::c_allocator.allocate<IrInstGen *>(call_param_count);
13095 Stage1AirInst **casted_args = heap::c_allocator.allocate<Stage1AirInst *>(call_param_count);
1309613096 size_t next_arg_index = 0;
1309713097 if (first_arg_ptr) {
1309813098 assert(first_arg_ptr->value->type->id == ZigTypeIdPointer);
......@@ -13101,7 +13101,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1310113101 if (type_is_invalid(param_type))
1310213102 return ira->codegen->invalid_inst_gen;
1310313103
13104 IrInstGen *first_arg;
13104 Stage1AirInst *first_arg;
1310513105 if (param_type->id == ZigTypeIdPointer) {
1310613106 first_arg = first_arg_ptr;
1310713107 } else {
......@@ -13111,7 +13111,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1311113111 return ira->codegen->invalid_inst_gen;
1311213112 }
1311313113
13114 IrInstGen *casted_arg = ir_implicit_cast2(ira, first_arg->scope, first_arg_ptr_src, first_arg, param_type);
13114 Stage1AirInst *casted_arg = ir_implicit_cast2(ira, first_arg->scope, first_arg_ptr_src, first_arg, param_type);
1311513115 if (type_is_invalid(casted_arg->value->type))
1311613116 return ira->codegen->invalid_inst_gen;
1311713117
......@@ -13119,11 +13119,11 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1311913119 next_arg_index += 1;
1312013120 }
1312113121 for (size_t call_i = 0; call_i < args_len; call_i += 1) {
13122 IrInstGen *old_arg = args_ptr[call_i];
13122 Stage1AirInst *old_arg = args_ptr[call_i];
1312313123 if (type_is_invalid(old_arg->value->type))
1312413124 return ira->codegen->invalid_inst_gen;
1312513125
13126 IrInstGen *casted_arg;
13126 Stage1AirInst *casted_arg;
1312713127 if (next_arg_index < src_param_count) {
1312813128 ZigType *param_type = fn_type_id->param_info[next_arg_index].type;
1312913129 if (type_is_invalid(param_type))
......@@ -13151,13 +13151,13 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1315113151 return ira->codegen->invalid_inst_gen;
1315213152 }
1315313153
13154 IrInstGen *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack, new_stack_src,
13154 Stage1AirInst *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack, new_stack_src,
1315513155 is_async_call_builtin, fn_entry);
1315613156 if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type))
1315713157 return ira->codegen->invalid_inst_gen;
1315813158
1315913159 if (modifier == CallModifierAsync) {
13160 IrInstGen *result = ir_analyze_async_call(ira, scope, source_node, fn_entry, fn_type, fn_ref,
13160 Stage1AirInst *result = ir_analyze_async_call(ira, scope, source_node, fn_entry, fn_type, fn_ref,
1316113161 casted_args, call_param_count, casted_new_stack, is_async_call_builtin, ret_ptr, call_result_loc);
1316213162 return ir_finish_anal(ira, result);
1316313163 }
......@@ -13170,7 +13170,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1317013170 parent_fn_entry->inferred_async_fn = fn_entry;
1317113171 }
1317213172
13173 IrInstGen *result_loc;
13173 Stage1AirInst *result_loc;
1317413174 if (handle_is_ptr(ira->codegen, return_type)) {
1317513175 result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc,
1317613176 return_type, nullptr, true, false);
......@@ -13185,9 +13185,9 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1318513185
1318613186 ZigType *expected_return_type = result_loc->value->type->data.pointer.child_type;
1318713187
13188 IrInstGen *dummy_value = ir_const(ira, scope, source_node, return_type);
13188 Stage1AirInst *dummy_value = ir_const(ira, scope, source_node, return_type);
1318913189 dummy_value->value->special = ConstValSpecialRuntime;
13190 IrInstGen *dummy_result = ir_implicit_cast2(ira, scope, source_node,
13190 Stage1AirInst *dummy_result = ir_implicit_cast2(ira, scope, source_node,
1319113191 dummy_value, expected_return_type);
1319213192 if (type_is_invalid(dummy_result->value->type)) {
1319313193 if ((return_type->id == ZigTypeIdErrorUnion || return_type->id == ZigTypeIdErrorSet) &&
......@@ -13220,7 +13220,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1322013220 result_loc = nullptr;
1322113221 }
1322213222
13223 IrInstGenCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref,
13223 Stage1AirInstCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref,
1322413224 call_param_count, casted_args, modifier, casted_new_stack,
1322513225 is_async_call_builtin, result_loc, return_type);
1322613226 if (get_scope_typeof(scope) == nullptr) {
......@@ -13229,11 +13229,11 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour
1322913229 return ir_finish_anal(ira, &new_call_instruction->base);
1323013230}
1323113231
13232static IrInstGen *ir_analyze_fn_call_src(IrAnalyze *ira, IrInstSrcCall *call_instruction,
13233 ZigFn *fn_entry, ZigType *fn_type, IrInstGen *fn_ref,
13234 IrInstGen *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier)
13232static Stage1AirInst *ir_analyze_fn_call_src(IrAnalyze *ira, Stage1ZirInstCall *call_instruction,
13233 ZigFn *fn_entry, ZigType *fn_type, Stage1AirInst *fn_ref,
13234 Stage1AirInst *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier)
1323513235{
13236 IrInstGen *new_stack = nullptr;
13236 Stage1AirInst *new_stack = nullptr;
1323713237 AstNode *new_stack_src = nullptr;
1323813238 if (call_instruction->new_stack) {
1323913239 new_stack = call_instruction->new_stack->child;
......@@ -13241,19 +13241,19 @@ static IrInstGen *ir_analyze_fn_call_src(IrAnalyze *ira, IrInstSrcCall *call_ins
1324113241 return ira->codegen->invalid_inst_gen;
1324213242 new_stack_src = call_instruction->new_stack->source_node;
1324313243 }
13244 IrInstGen **args_ptr = heap::c_allocator.allocate<IrInstGen *>(call_instruction->arg_count);
13244 Stage1AirInst **args_ptr = heap::c_allocator.allocate<Stage1AirInst *>(call_instruction->arg_count);
1324513245 for (size_t i = 0; i < call_instruction->arg_count; i += 1) {
1324613246 args_ptr[i] = call_instruction->args[i]->child;
1324713247 if (type_is_invalid(args_ptr[i]->value->type))
1324813248 return ira->codegen->invalid_inst_gen;
1324913249 }
13250 IrInstGen *ret_ptr = nullptr;
13250 Stage1AirInst *ret_ptr = nullptr;
1325113251 if (call_instruction->ret_ptr != nullptr) {
1325213252 ret_ptr = call_instruction->ret_ptr->child;
1325313253 if (type_is_invalid(ret_ptr->value->type))
1325413254 return ira->codegen->invalid_inst_gen;
1325513255 }
13256 IrInstGen *result = ir_analyze_fn_call(ira, call_instruction->base.scope,
13256 Stage1AirInst *result = ir_analyze_fn_call(ira, call_instruction->base.scope,
1325713257 call_instruction->base.source_node, fn_entry, fn_type, fn_ref,
1325813258 first_arg_ptr, first_arg_ptr_src, modifier, new_stack, new_stack_src,
1325913259 call_instruction->is_async_call_builtin, args_ptr, call_instruction->arg_count, ret_ptr,
......@@ -13262,21 +13262,21 @@ static IrInstGen *ir_analyze_fn_call_src(IrAnalyze *ira, IrInstSrcCall *call_ins
1326213262 return result;
1326313263}
1326413264
13265static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node,
13266 IrInstSrc *pass1_options, IrInstSrc *pass1_fn_ref, IrInstGen **args_ptr, size_t args_len,
13265static Stage1AirInst *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node,
13266 Stage1ZirInst *pass1_options, Stage1ZirInst *pass1_fn_ref, Stage1AirInst **args_ptr, size_t args_len,
1326713267 ResultLoc *result_loc)
1326813268{
13269 IrInstGen *options = pass1_options->child;
13269 Stage1AirInst *options = pass1_options->child;
1327013270 if (type_is_invalid(options->value->type))
1327113271 return ira->codegen->invalid_inst_gen;
1327213272
13273 IrInstGen *fn_ref = pass1_fn_ref->child;
13273 Stage1AirInst *fn_ref = pass1_fn_ref->child;
1327413274 if (type_is_invalid(fn_ref->value->type))
1327513275 return ira->codegen->invalid_inst_gen;
1327613276
1327713277 TypeStructField *modifier_field = find_struct_type_field(options->value->type, buf_create_from_str("modifier"));
1327813278 src_assert(modifier_field != nullptr, source_node);
13279 IrInstGen *modifier_inst = ir_analyze_struct_value_field_value(ira, scope, source_node, options, modifier_field);
13279 Stage1AirInst *modifier_inst = ir_analyze_struct_value_field_value(ira, scope, source_node, options, modifier_field);
1328013280 ZigValue *modifier_val = ir_resolve_const(ira, modifier_inst, UndefBad);
1328113281 if (modifier_val == nullptr)
1328213282 return ira->codegen->invalid_inst_gen;
......@@ -13307,7 +13307,7 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s
1330713307 }
1330813308 }
1330913309
13310 IrInstGen *first_arg_ptr = nullptr;
13310 Stage1AirInst *first_arg_ptr = nullptr;
1331113311 AstNode *first_arg_ptr_src = nullptr;
1331213312 ZigFn *fn = nullptr;
1331313313 if (instr_is_comptime(fn_ref)) {
......@@ -13342,16 +13342,16 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s
1334213342
1334313343 TypeStructField *stack_field = find_struct_type_field(options->value->type, buf_create_from_str("stack"));
1334413344 src_assert(stack_field != nullptr, source_node);
13345 IrInstGen *opt_stack = ir_analyze_struct_value_field_value(ira, scope, source_node, options, stack_field);
13345 Stage1AirInst *opt_stack = ir_analyze_struct_value_field_value(ira, scope, source_node, options, stack_field);
1334613346 if (type_is_invalid(opt_stack->value->type))
1334713347 return ira->codegen->invalid_inst_gen;
1334813348
13349 IrInstGen *stack_is_non_null_inst = ir_analyze_test_non_null(ira, scope, source_node, opt_stack);
13349 Stage1AirInst *stack_is_non_null_inst = ir_analyze_test_non_null(ira, scope, source_node, opt_stack);
1335013350 bool stack_is_non_null;
1335113351 if (!ir_resolve_bool(ira, stack_is_non_null_inst, &stack_is_non_null))
1335213352 return ira->codegen->invalid_inst_gen;
1335313353
13354 IrInstGen *stack = nullptr;
13354 Stage1AirInst *stack = nullptr;
1335513355 AstNode *stack_src = nullptr;
1335613356 if (stack_is_non_null) {
1335713357 stack = ir_analyze_optional_value_payload_value(ira, scope, source_node, opt_stack, false);
......@@ -13364,10 +13364,10 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s
1336413364 modifier, stack, stack_src, false, args_ptr, args_len, nullptr, result_loc);
1336513365}
1336613366
13367static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node, CallModifier modifier,
13368 IrInstSrc *pass1_fn_ref, IrInstSrc *ret_ptr, IrInstSrc *new_stack, IrInstGen **args_ptr, size_t args_len, ResultLoc *result_loc)
13367static Stage1AirInst *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node, CallModifier modifier,
13368 Stage1ZirInst *pass1_fn_ref, Stage1ZirInst *ret_ptr, Stage1ZirInst *new_stack, Stage1AirInst **args_ptr, size_t args_len, ResultLoc *result_loc)
1336913369{
13370 IrInstGen *fn_ref = pass1_fn_ref->child;
13370 Stage1AirInst *fn_ref = pass1_fn_ref->child;
1337113371 if (type_is_invalid(fn_ref->value->type))
1337213372 return ira->codegen->invalid_inst_gen;
1337313373
......@@ -13376,7 +13376,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN
1337613376 return ira->codegen->invalid_inst_gen;
1337713377 }
1337813378
13379 IrInstGen *first_arg_ptr = nullptr;
13379 Stage1AirInst *first_arg_ptr = nullptr;
1338013380 AstNode *first_arg_ptr_src = nullptr;
1338113381 ZigFn *fn = nullptr;
1338213382 if (instr_is_comptime(fn_ref)) {
......@@ -13392,7 +13392,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN
1339213392 }
1339313393 }
1339413394
13395 IrInstGen *ret_ptr_uncasted = nullptr;
13395 Stage1AirInst *ret_ptr_uncasted = nullptr;
1339613396 if (ret_ptr != nullptr) {
1339713397 ret_ptr_uncasted = ret_ptr->child;
1339813398 if (type_is_invalid(ret_ptr_uncasted->value->type))
......@@ -13400,7 +13400,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN
1340013400 }
1340113401
1340213402 ZigType *fn_type = (fn != nullptr) ? fn->type_entry : fn_ref->value->type;
13403 IrInstGen *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node,
13403 Stage1AirInst *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node,
1340413404 new_stack->child, new_stack->source_node, true, fn);
1340513405 if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type))
1340613406 return ira->codegen->invalid_inst_gen;
......@@ -13410,7 +13410,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN
1341013410 args_len, ret_ptr_uncasted, result_loc);
1341113411}
1341213412
13413static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *args, IrInstGen ***args_ptr, size_t *args_len) {
13413static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *args, Stage1AirInst ***args_ptr, size_t *args_len) {
1341413414 ZigType *args_type = args->value->type;
1341513415 if (type_is_invalid(args_type))
1341613416 return false;
......@@ -13423,7 +13423,7 @@ static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *so
1342313423
1342413424 if (is_tuple(args_type)) {
1342513425 *args_len = args_type->data.structure.src_field_count;
13426 *args_ptr = heap::c_allocator.allocate<IrInstGen *>(*args_len);
13426 *args_ptr = heap::c_allocator.allocate<Stage1AirInst *>(*args_len);
1342713427 for (size_t i = 0; i < *args_len; i += 1) {
1342813428 TypeStructField *arg_field = args_type->data.structure.fields[i];
1342913429 (*args_ptr)[i] = ir_analyze_struct_value_field_value(ira, scope, source_node, args, arg_field);
......@@ -13437,50 +13437,50 @@ static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *so
1343713437 return true;
1343813438}
1343913439
13440static IrInstGen *ir_analyze_instruction_call_extra(IrAnalyze *ira, IrInstSrcCallExtra *instruction) {
13441 IrInstGen *args = instruction->args->child;
13442 IrInstGen **args_ptr = nullptr;
13440static Stage1AirInst *ir_analyze_instruction_call_extra(IrAnalyze *ira, Stage1ZirInstCallExtra *instruction) {
13441 Stage1AirInst *args = instruction->args->child;
13442 Stage1AirInst **args_ptr = nullptr;
1344313443 size_t args_len = 0;
1344413444 if (!ir_extract_tuple_call_args(ira, instruction->base.scope, instruction->base.source_node, args, &args_ptr, &args_len)) {
1344513445 return ira->codegen->invalid_inst_gen;
1344613446 }
1344713447
13448 IrInstGen *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options,
13448 Stage1AirInst *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options,
1344913449 instruction->fn_ref, args_ptr, args_len, instruction->result_loc);
1345013450 heap::c_allocator.deallocate(args_ptr, args_len);
1345113451 return result;
1345213452}
1345313453
13454static IrInstGen *ir_analyze_instruction_async_call_extra(IrAnalyze *ira, IrInstSrcAsyncCallExtra *instruction) {
13455 IrInstGen *args = instruction->args->child;
13456 IrInstGen **args_ptr = nullptr;
13454static Stage1AirInst *ir_analyze_instruction_async_call_extra(IrAnalyze *ira, Stage1ZirInstAsyncCallExtra *instruction) {
13455 Stage1AirInst *args = instruction->args->child;
13456 Stage1AirInst **args_ptr = nullptr;
1345713457 size_t args_len = 0;
1345813458 if (!ir_extract_tuple_call_args(ira, instruction->base.scope, instruction->base.source_node, args, &args_ptr, &args_len)) {
1345913459 return ira->codegen->invalid_inst_gen;
1346013460 }
1346113461
13462 IrInstGen *result = ir_analyze_async_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->modifier,
13462 Stage1AirInst *result = ir_analyze_async_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->modifier,
1346313463 instruction->fn_ref, instruction->ret_ptr, instruction->new_stack, args_ptr, args_len, instruction->result_loc);
1346413464 heap::c_allocator.deallocate(args_ptr, args_len);
1346513465 return result;
1346613466}
1346713467
13468static IrInstGen *ir_analyze_instruction_call_args(IrAnalyze *ira, IrInstSrcCallArgs *instruction) {
13469 IrInstGen **args_ptr = heap::c_allocator.allocate<IrInstGen *>(instruction->args_len);
13468static Stage1AirInst *ir_analyze_instruction_call_args(IrAnalyze *ira, Stage1ZirInstCallArgs *instruction) {
13469 Stage1AirInst **args_ptr = heap::c_allocator.allocate<Stage1AirInst *>(instruction->args_len);
1347013470 for (size_t i = 0; i < instruction->args_len; i += 1) {
1347113471 args_ptr[i] = instruction->args_ptr[i]->child;
1347213472 if (type_is_invalid(args_ptr[i]->value->type))
1347313473 return ira->codegen->invalid_inst_gen;
1347413474 }
1347513475
13476 IrInstGen *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options,
13476 Stage1AirInst *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options,
1347713477 instruction->fn_ref, args_ptr, instruction->args_len, instruction->result_loc);
1347813478 heap::c_allocator.deallocate(args_ptr, instruction->args_len);
1347913479 return result;
1348013480}
1348113481
13482static IrInstGen *ir_analyze_instruction_call(IrAnalyze *ira, IrInstSrcCall *call_instruction) {
13483 IrInstGen *fn_ref = call_instruction->fn_ref->child;
13482static Stage1AirInst *ir_analyze_instruction_call(IrAnalyze *ira, Stage1ZirInstCall *call_instruction) {
13483 Stage1AirInst *fn_ref = call_instruction->fn_ref->child;
1348413484 if (type_is_invalid(fn_ref->value->type))
1348513485 return ira->codegen->invalid_inst_gen;
1348613486
......@@ -13507,7 +13507,7 @@ static IrInstGen *ir_analyze_instruction_call(IrAnalyze *ira, IrInstSrcCall *cal
1350713507 } else if (fn_ref->value->type->id == ZigTypeIdBoundFn) {
1350813508 assert(fn_ref->value->special == ConstValSpecialStatic);
1350913509 ZigFn *fn_table_entry = fn_ref->value->data.x_bound_fn.fn;
13510 IrInstGen *first_arg_ptr = fn_ref->value->data.x_bound_fn.first_arg;
13510 Stage1AirInst *first_arg_ptr = fn_ref->value->data.x_bound_fn.first_arg;
1351113511 AstNode *first_arg_ptr_src = fn_ref->value->data.x_bound_fn.first_arg_src;
1351213512 CallModifier modifier = is_comptime ? CallModifierCompileTime : call_instruction->modifier;
1351313513 return ir_analyze_fn_call_src(ira, call_instruction, fn_table_entry, fn_table_entry->type_entry,
......@@ -13641,8 +13641,8 @@ static Error ir_read_const_ptr(IrAnalyze *ira, CodeGen *codegen, AstNode *source
1364113641 zig_unreachable();
1364213642}
1364313643
13644static IrInstGen *ir_analyze_optional_type(IrAnalyze *ira, IrInstSrcUnOp *instruction) {
13645 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
13644static Stage1AirInst *ir_analyze_optional_type(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) {
13645 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
1364613646 result->value->special = ConstValSpecialLazy;
1364713647
1364813648 LazyValueOptType *lazy_opt_type = heap::c_allocator.create<LazyValueOptType>();
......@@ -13692,8 +13692,8 @@ static ErrorMsg *ir_eval_negation_scalar(IrAnalyze *ira, Scope *scope, AstNode *
1369213692 return nullptr;
1369313693}
1369413694
13695static IrInstGen *ir_analyze_negation(IrAnalyze *ira, IrInstSrcUnOp *instruction) {
13696 IrInstGen *value = instruction->value->child;
13695static Stage1AirInst *ir_analyze_negation(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) {
13696 Stage1AirInst *value = instruction->value->child;
1369713697 ZigType *expr_type = value->value->type;
1369813698 if (type_is_invalid(expr_type))
1369913699 return ira->codegen->invalid_inst_gen;
......@@ -13723,7 +13723,7 @@ static IrInstGen *ir_analyze_negation(IrAnalyze *ira, IrInstSrcUnOp *instruction
1372313723 if (!operand_val)
1372413724 return ira->codegen->invalid_inst_gen;
1372513725
13726 IrInstGen *result_instruction = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);
13726 Stage1AirInst *result_instruction = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);
1372713727 ZigValue *out_val = result_instruction->value;
1372813728 if (expr_type->id == ZigTypeIdVector) {
1372913729 expand_undef_array(ira->codegen, operand_val);
......@@ -13758,8 +13758,8 @@ static IrInstGen *ir_analyze_negation(IrAnalyze *ira, IrInstSrcUnOp *instruction
1375813758 return ir_build_negation(ira, instruction->base.scope, instruction->base.source_node, value, expr_type, is_wrap_op);
1375913759}
1376013760
13761static IrInstGen *ir_analyze_bin_not(IrAnalyze *ira, IrInstSrcUnOp *instruction) {
13762 IrInstGen *value = instruction->value->child;
13761static Stage1AirInst *ir_analyze_bin_not(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) {
13762 Stage1AirInst *value = instruction->value->child;
1376313763 ZigType *expr_type = value->value->type;
1376413764 if (type_is_invalid(expr_type))
1376513765 return ira->codegen->invalid_inst_gen;
......@@ -13778,7 +13778,7 @@ static IrInstGen *ir_analyze_bin_not(IrAnalyze *ira, IrInstSrcUnOp *instruction)
1377813778 if (expr_val == nullptr)
1377913779 return ira->codegen->invalid_inst_gen;
1378013780
13781 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);
13781 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);
1378213782
1378313783 if (expr_type->id == ZigTypeIdVector) {
1378413784 expand_undef_array(ira->codegen, expr_val);
......@@ -13805,7 +13805,7 @@ static IrInstGen *ir_analyze_bin_not(IrAnalyze *ira, IrInstSrcUnOp *instruction)
1380513805 return ir_build_binary_not(ira, instruction->base.scope, instruction->base.source_node, value, expr_type);
1380613806}
1380713807
13808static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *instruction) {
13808static Stage1AirInst *ir_analyze_instruction_un_op(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) {
1380913809 IrUnOp op_id = instruction->op_id;
1381013810 switch (op_id) {
1381113811 case IrUnOpInvalid:
......@@ -13816,7 +13816,7 @@ static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *in
1381613816 case IrUnOpNegationWrap:
1381713817 return ir_analyze_negation(ira, instruction);
1381813818 case IrUnOpDereference: {
13819 IrInstGen *ptr = instruction->value->child;
13819 Stage1AirInst *ptr = instruction->value->child;
1382013820 if (type_is_invalid(ptr->value->type))
1382113821 return ira->codegen->invalid_inst_gen;
1382213822 ZigType *ptr_type = ptr->value->type;
......@@ -13827,7 +13827,7 @@ static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *in
1382713827 return ira->codegen->invalid_inst_gen;
1382813828 }
1382913829
13830 IrInstGen *result = ir_get_deref(ira, instruction->base.scope,
13830 Stage1AirInst *result = ir_get_deref(ira, instruction->base.scope,
1383113831 instruction->base.source_node, ptr, instruction->result_loc);
1383213832 if (type_is_invalid(result->value->type))
1383313833 return ira->codegen->invalid_inst_gen;
......@@ -13860,7 +13860,7 @@ static void ir_push_resume_block(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb) {
1386013860 }
1386113861}
1386213862
13863static IrInstGen *ir_analyze_instruction_br(IrAnalyze *ira, IrInstSrcBr *br_instruction) {
13863static Stage1AirInst *ir_analyze_instruction_br(IrAnalyze *ira, Stage1ZirInstBr *br_instruction) {
1386413864 Stage1ZirBasicBlock *old_dest_block = br_instruction->dest_block;
1386513865
1386613866 bool is_comptime;
......@@ -13870,18 +13870,18 @@ static IrInstGen *ir_analyze_instruction_br(IrAnalyze *ira, IrInstSrcBr *br_inst
1387013870 if (is_comptime || (old_dest_block->ref_count == 1 && old_dest_block->suspend_instruction_ref == nullptr))
1387113871 return ir_inline_bb(ira, br_instruction->base.source_node, old_dest_block);
1387213872
13873 IrBasicBlockGen *new_bb = ir_get_new_bb_runtime(ira, old_dest_block, &br_instruction->base);
13873 Stage1AirBasicBlock *new_bb = ir_get_new_bb_runtime(ira, old_dest_block, &br_instruction->base);
1387413874 if (new_bb == nullptr)
1387513875 return ir_unreach_error(ira);
1387613876
1387713877 ir_push_resume_block(ira, old_dest_block);
1387813878
13879 IrInstGen *result = ir_build_br_gen(ira, br_instruction->base.scope, br_instruction->base.source_node, new_bb);
13879 Stage1AirInst *result = ir_build_br_gen(ira, br_instruction->base.scope, br_instruction->base.source_node, new_bb);
1388013880 return ir_finish_anal(ira, result);
1388113881}
1388213882
13883static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr *cond_br_instruction) {
13884 IrInstGen *condition = cond_br_instruction->condition->child;
13883static Stage1AirInst *ir_analyze_instruction_cond_br(IrAnalyze *ira, Stage1ZirInstCondBr *cond_br_instruction) {
13884 Stage1AirInst *condition = cond_br_instruction->condition->child;
1388513885 if (type_is_invalid(condition->value->type))
1388613886 return ir_unreach_error(ira);
1388713887
......@@ -13890,7 +13890,7 @@ static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr
1389013890 return ir_unreach_error(ira);
1389113891
1389213892 ZigType *bool_type = ira->codegen->builtin_types.entry_bool;
13893 IrInstGen *casted_condition = ir_implicit_cast(ira, condition, bool_type);
13893 Stage1AirInst *casted_condition = ir_implicit_cast(ira, condition, bool_type);
1389413894 if (type_is_invalid(casted_condition->value->type))
1389513895 return ir_unreach_error(ira);
1389613896
......@@ -13905,37 +13905,37 @@ static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr
1390513905 if (is_comptime || (old_dest_block->ref_count == 1 && old_dest_block->suspend_instruction_ref == nullptr))
1390613906 return ir_inline_bb(ira, cond_br_instruction->base.source_node, old_dest_block);
1390713907
13908 IrBasicBlockGen *new_dest_block = ir_get_new_bb_runtime(ira, old_dest_block, &cond_br_instruction->base);
13908 Stage1AirBasicBlock *new_dest_block = ir_get_new_bb_runtime(ira, old_dest_block, &cond_br_instruction->base);
1390913909 if (new_dest_block == nullptr)
1391013910 return ir_unreach_error(ira);
1391113911
1391213912 ir_push_resume_block(ira, old_dest_block);
1391313913
13914 IrInstGen *result = ir_build_br_gen(ira, cond_br_instruction->base.scope,
13914 Stage1AirInst *result = ir_build_br_gen(ira, cond_br_instruction->base.scope,
1391513915 cond_br_instruction->base.source_node, new_dest_block);
1391613916 return ir_finish_anal(ira, result);
1391713917 }
1391813918
1391913919 assert(cond_br_instruction->then_block != cond_br_instruction->else_block);
13920 IrBasicBlockGen *new_then_block = ir_get_new_bb_runtime(ira, cond_br_instruction->then_block, &cond_br_instruction->base);
13920 Stage1AirBasicBlock *new_then_block = ir_get_new_bb_runtime(ira, cond_br_instruction->then_block, &cond_br_instruction->base);
1392113921 if (new_then_block == nullptr)
1392213922 return ir_unreach_error(ira);
1392313923
13924 IrBasicBlockGen *new_else_block = ir_get_new_bb_runtime(ira, cond_br_instruction->else_block, &cond_br_instruction->base);
13924 Stage1AirBasicBlock *new_else_block = ir_get_new_bb_runtime(ira, cond_br_instruction->else_block, &cond_br_instruction->base);
1392513925 if (new_else_block == nullptr)
1392613926 return ir_unreach_error(ira);
1392713927
1392813928 ir_push_resume_block(ira, cond_br_instruction->else_block);
1392913929 ir_push_resume_block(ira, cond_br_instruction->then_block);
1393013930
13931 IrInstGen *result = ir_build_cond_br_gen(ira, cond_br_instruction->base.scope,
13931 Stage1AirInst *result = ir_build_cond_br_gen(ira, cond_br_instruction->base.scope,
1393213932 cond_br_instruction->base.source_node, casted_condition, new_then_block,
1393313933 new_else_block);
1393413934 return ir_finish_anal(ira, result);
1393513935}
1393613936
13937static IrInstGen *ir_analyze_instruction_unreachable(IrAnalyze *ira,
13938 IrInstSrcUnreachable *unreachable_instruction)
13937static Stage1AirInst *ir_analyze_instruction_unreachable(IrAnalyze *ira,
13938 Stage1ZirInstUnreachable *unreachable_instruction)
1393913939{
1394013940 if (ir_should_inline(ira->zir, unreachable_instruction->base.scope)) {
1394113941 ir_add_error_node(ira, unreachable_instruction->base.source_node,
......@@ -13943,12 +13943,12 @@ static IrInstGen *ir_analyze_instruction_unreachable(IrAnalyze *ira,
1394313943 return ir_unreach_error(ira);
1394413944 }
1394513945
13946 IrInstGen *result = ir_build_unreachable_gen(ira, unreachable_instruction->base.scope,
13946 Stage1AirInst *result = ir_build_unreachable_gen(ira, unreachable_instruction->base.scope,
1394713947 unreachable_instruction->base.source_node);
1394813948 return ir_finish_anal(ira, result);
1394913949}
1395013950
13951static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_instruction) {
13951static Stage1AirInst *ir_analyze_instruction_phi(IrAnalyze *ira, Stage1ZirInstPhi *phi_instruction) {
1395213952 Error err;
1395313953
1395413954 if (ira->const_predecessor_bb) {
......@@ -13956,13 +13956,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1395613956 Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i];
1395713957 if (predecessor != ira->const_predecessor_bb)
1395813958 continue;
13959 IrInstGen *value = phi_instruction->incoming_values[i]->child;
13959 Stage1AirInst *value = phi_instruction->incoming_values[i]->child;
1396013960 assert(value->value->type);
1396113961 if (type_is_invalid(value->value->type))
1396213962 return ira->codegen->invalid_inst_gen;
1396313963
1396413964 if (value->value->special != ConstValSpecialRuntime) {
13965 IrInstGen *result = ir_const(ira, phi_instruction->base.scope,
13965 Stage1AirInst *result = ir_const(ira, phi_instruction->base.scope,
1396613966 phi_instruction->base.source_node, nullptr);
1396713967 copy_const_val(ira->codegen, result->value, value->value);
1396813968 return result;
......@@ -13978,11 +13978,11 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1397813978 peer_parent->peers.length >= 2)
1397913979 {
1398013980 if (peer_parent->resolved_type == nullptr) {
13981 IrInstGen **instructions = heap::c_allocator.allocate<IrInstGen *>(peer_parent->peers.length);
13981 Stage1AirInst **instructions = heap::c_allocator.allocate<Stage1AirInst *>(peer_parent->peers.length);
1398213982 for (size_t i = 0; i < peer_parent->peers.length; i += 1) {
1398313983 ResultLocPeer *this_peer = peer_parent->peers.at(i);
1398413984
13985 IrInstGen *gen_instruction = this_peer->base.gen_instruction;
13985 Stage1AirInst *gen_instruction = this_peer->base.gen_instruction;
1398613986 if (gen_instruction == nullptr) {
1398713987 // unreachable instructions will cause implicit_elem_type to be null
1398813988 if (this_peer->base.implicit_elem_type == nullptr) {
......@@ -14010,7 +14010,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1401014010 phi_instruction->base.source_node);
1401114011
1401214012 // In case resolving the parent activates a suspend, do it now
14013 IrInstGen *parent_result_loc = ir_resolve_result(ira, &phi_instruction->base, peer_parent->parent,
14013 Stage1AirInst *parent_result_loc = ir_resolve_result(ira, &phi_instruction->base, peer_parent->parent,
1401414014 peer_parent->resolved_type, nullptr, false, true);
1401514015 if (parent_result_loc != nullptr &&
1401614016 (type_is_invalid(parent_result_loc->value->type) || parent_result_loc->value->type->id == ZigTypeIdUnreachable))
......@@ -14019,13 +14019,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1401914019 }
1402014020 // If the above code generated any instructions in the current basic block, we need
1402114021 // to move them to the peer parent predecessor.
14022 ZigList<IrInstGen *> instrs_to_move = {};
14022 ZigList<Stage1AirInst *> instrs_to_move = {};
1402314023 while (ira->new_irb.current_basic_block->instruction_list.length != 0) {
1402414024 instrs_to_move.append(ira->new_irb.current_basic_block->instruction_list.pop());
1402514025 }
1402614026 if (instrs_to_move.length != 0) {
14027 IrBasicBlockGen *predecessor = peer_parent->base.source_instruction->child->owner_bb;
14028 IrInstGen *branch_instruction = predecessor->instruction_list.pop();
14027 Stage1AirBasicBlock *predecessor = peer_parent->base.source_instruction->child->owner_bb;
14028 Stage1AirInst *branch_instruction = predecessor->instruction_list.pop();
1402914029 src_assert(branch_instruction->value->type->id == ZigTypeIdUnreachable,
1403014030 phi_instruction->base.source_node);
1403114031 while (instrs_to_move.length != 0) {
......@@ -14053,8 +14053,8 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1405314053 return ira_resume(ira);
1405414054 }
1405514055
14056 ZigList<IrBasicBlockGen*> new_incoming_blocks = {0};
14057 ZigList<IrInstGen*> new_incoming_values = {0};
14056 ZigList<Stage1AirBasicBlock*> new_incoming_blocks = {0};
14057 ZigList<Stage1AirInst*> new_incoming_values = {0};
1405814058
1405914059 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
1406014060 Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i];
......@@ -14062,9 +14062,9 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1406214062 continue;
1406314063
1406414064
14065 IrInstSrc *old_value = phi_instruction->incoming_values[i];
14065 Stage1ZirInst *old_value = phi_instruction->incoming_values[i];
1406614066 assert(old_value);
14067 IrInstGen *new_value = old_value->child;
14067 Stage1AirInst *new_value = old_value->child;
1406814068 if (!new_value || new_value->value->type->id == ZigTypeIdUnreachable || predecessor->child == nullptr)
1406914069 continue;
1407014070
......@@ -14078,13 +14078,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1407814078 }
1407914079
1408014080 if (new_incoming_blocks.length == 0) {
14081 IrInstGen *result = ir_build_unreachable_gen(ira, phi_instruction->base.scope,
14081 Stage1AirInst *result = ir_build_unreachable_gen(ira, phi_instruction->base.scope,
1408214082 phi_instruction->base.source_node);
1408314083 return ir_finish_anal(ira, result);
1408414084 }
1408514085
1408614086 if (new_incoming_blocks.length == 1) {
14087 IrInstGen *incoming_value = new_incoming_values.at(0);
14087 Stage1AirInst *incoming_value = new_incoming_values.at(0);
1408814088 new_incoming_blocks.deinit();
1408914089 new_incoming_values.deinit();
1409014090 return incoming_value;
......@@ -14145,14 +14145,14 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1414514145 // cast all values to the resolved type. however we can't put cast instructions in front of the phi instruction.
1414614146 // so we go back and insert the casts as the last instruction in the corresponding predecessor blocks, and
1414714147 // then make sure the branch instruction is preserved.
14148 IrBasicBlockGen *cur_bb = ira->new_irb.current_basic_block;
14148 Stage1AirBasicBlock *cur_bb = ira->new_irb.current_basic_block;
1414914149 for (size_t i = 0; i < new_incoming_values.length; i += 1) {
14150 IrInstGen *new_value = new_incoming_values.at(i);
14151 IrBasicBlockGen *predecessor = new_incoming_blocks.at(i);
14150 Stage1AirInst *new_value = new_incoming_values.at(i);
14151 Stage1AirBasicBlock *predecessor = new_incoming_blocks.at(i);
1415214152 src_assert(predecessor->instruction_list.length != 0, phi_instruction->base.source_node);
14153 IrInstGen *branch_instruction = predecessor->instruction_list.pop();
14153 Stage1AirInst *branch_instruction = predecessor->instruction_list.pop();
1415414154 ir_set_cursor_at_end_gen(&ira->new_irb, predecessor);
14155 IrInstGen *casted_value = ir_implicit_cast(ira, new_value, resolved_type);
14155 Stage1AirInst *casted_value = ir_implicit_cast(ira, new_value, resolved_type);
1415614156 if (type_is_invalid(casted_value->value->type)) {
1415714157 return ira->codegen->invalid_inst_gen;
1415814158 }
......@@ -14167,7 +14167,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1416714167 }
1416814168 ir_set_cursor_at_end_gen(&ira->new_irb, cur_bb);
1416914169
14170 IrInstGen *result = ir_build_phi_gen(ira, phi_instruction->base.scope,
14170 Stage1AirInst *result = ir_build_phi_gen(ira, phi_instruction->base.scope,
1417114171 phi_instruction->base.source_node, new_incoming_blocks.length,
1417214172 new_incoming_blocks.items, new_incoming_values.items, resolved_type);
1417314173
......@@ -14179,9 +14179,9 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1417914179 return result;
1418014180}
1418114181
14182static IrInstGen *ir_analyze_instruction_var_ptr(IrAnalyze *ira, IrInstSrcVarPtr *instruction) {
14182static Stage1AirInst *ir_analyze_instruction_var_ptr(IrAnalyze *ira, Stage1ZirInstVarPtr *instruction) {
1418314183 ZigVar *var = instruction->var;
14184 IrInstGen *result = ir_get_var_ptr(ira, instruction->base.scope, instruction->base.source_node, var);
14184 Stage1AirInst *result = ir_get_var_ptr(ira, instruction->base.scope, instruction->base.source_node, var);
1418514185 if (instruction->crossed_fndef_scope != nullptr && !instr_is_comptime(result)) {
1418614186 ErrorMsg *msg = ir_add_error_node(ira, instruction->base.source_node,
1418714187 buf_sprintf("'%s' not accessible from inner function", var->name));
......@@ -14309,13 +14309,13 @@ static Error compute_elem_align(IrAnalyze *ira, ZigType *elem_type, uint32_t bas
1430914309 return ErrorNone;
1431014310}
1431114311
14312static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemPtr *elem_ptr_instruction) {
14312static Stage1AirInst *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, Stage1ZirInstElemPtr *elem_ptr_instruction) {
1431314313 Error err;
14314 IrInstGen *array_ptr = elem_ptr_instruction->array_ptr->child;
14314 Stage1AirInst *array_ptr = elem_ptr_instruction->array_ptr->child;
1431514315 if (type_is_invalid(array_ptr->value->type))
1431614316 return ira->codegen->invalid_inst_gen;
1431714317
14318 IrInstGen *elem_index = elem_ptr_instruction->elem_index->child;
14318 Stage1AirInst *elem_index = elem_ptr_instruction->elem_index->child;
1431914319 if (type_is_invalid(elem_index->value->type))
1432014320 return ira->codegen->invalid_inst_gen;
1432114321
......@@ -14337,7 +14337,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
1433714337 array_type->data.pointer.ptr_len == PtrLenSingle &&
1433814338 array_type->data.pointer.child_type->id == ZigTypeIdArray)
1433914339 {
14340 IrInstGen *ptr_value = ir_get_deref(ira, elem_ptr_instruction->base.scope,
14340 Stage1AirInst *ptr_value = ir_get_deref(ira, elem_ptr_instruction->base.scope,
1434114341 elem_ptr_instruction->base.source_node, array_ptr, nullptr);
1434214342 if (type_is_invalid(ptr_value->value->type))
1434314343 return ira->codegen->invalid_inst_gen;
......@@ -14392,7 +14392,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
1439214392 array_type->data.structure.resolve_status == ResolveStatusBeingInferred)
1439314393 {
1439414394 ZigType *usize = ira->codegen->builtin_types.entry_usize;
14395 IrInstGen *casted_elem_index = ir_implicit_cast(ira, elem_index, usize);
14395 Stage1AirInst *casted_elem_index = ir_implicit_cast(ira, elem_index, usize);
1439614396 if (type_is_invalid(casted_elem_index->value->type))
1439714397 return ira->codegen->invalid_inst_gen;
1439814398 src_assert(instr_is_comptime(casted_elem_index), elem_ptr_instruction->base.source_node);
......@@ -14421,7 +14421,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
1442114421 }
1442214422
1442314423 ZigType *usize = ira->codegen->builtin_types.entry_usize;
14424 IrInstGen *casted_elem_index = ir_implicit_cast(ira, elem_index, usize);
14424 Stage1AirInst *casted_elem_index = ir_implicit_cast(ira, elem_index, usize);
1442514425 if (type_is_invalid(casted_elem_index->value->type))
1442614426 return ira->codegen->invalid_inst_gen;
1442714427
......@@ -14553,7 +14553,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
1455314553 return ira->codegen->invalid_inst_gen;
1455414554 }
1455514555 if (array_type->id == ZigTypeIdPointer) {
14556 IrInstGen *result = ir_const(ira, elem_ptr_instruction->base.scope, elem_ptr_instruction->base.source_node, return_type);
14556 Stage1AirInst *result = ir_const(ira, elem_ptr_instruction->base.scope, elem_ptr_instruction->base.source_node, return_type);
1455714557 ZigValue *out_val = result->value;
1455814558 out_val->data.x_ptr.mut = array_ptr_val->data.x_ptr.mut;
1455914559 size_t new_index;
......@@ -14639,7 +14639,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
1463914639 return_type);
1464014640 }
1464114641 ZigValue *len_field = array_ptr_val->data.x_struct.fields[slice_len_index];
14642 IrInstGen *result = ir_const(ira, elem_ptr_instruction->base.scope,
14642 Stage1AirInst *result = ir_const(ira, elem_ptr_instruction->base.scope,
1464314643 elem_ptr_instruction->base.source_node, return_type);
1464414644 ZigValue *out_val = result->value;
1464514645 ZigType *slice_ptr_type = array_type->data.structure.fields[slice_ptr_index]->type_entry;
......@@ -14699,7 +14699,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
1469914699 } else if (array_type->id == ZigTypeIdArray || array_type->id == ZigTypeIdVector) {
1470014700 expand_undef_array(ira->codegen, array_ptr_val);
1470114701
14702 IrInstGen *result;
14702 Stage1AirInst *result;
1470314703 if (orig_array_ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
1470414704 result = ir_build_elem_ptr_gen(ira, elem_ptr_instruction->base.scope,
1470514705 elem_ptr_instruction->base.source_node, array_ptr, casted_elem_index,
......@@ -14766,9 +14766,9 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP
1476614766 elem_ptr_instruction->base.source_node, array_ptr, casted_elem_index, safety_check_on, return_type);
1476714767}
1476814768
14769static IrInstGen *ir_analyze_container_member_access_inner(IrAnalyze *ira,
14769static Stage1AirInst *ir_analyze_container_member_access_inner(IrAnalyze *ira,
1477014770 ZigType *bare_struct_type, Buf *field_name, Scope *scope, AstNode *source_node,
14771 IrInstGen *container_ptr, AstNode *container_ptr_src, ZigType *container_type)
14771 Stage1AirInst *container_ptr, AstNode *container_ptr_src, ZigType *container_type)
1477214772{
1477314773 if (!is_slice(bare_struct_type)) {
1477414774 ScopeDecls *container_scope = get_container_scope(bare_struct_type);
......@@ -14798,7 +14798,7 @@ static IrInstGen *ir_analyze_container_member_access_inner(IrAnalyze *ira,
1479814798 if (type_is_invalid(fn_entry->type_entry))
1479914799 return ira->codegen->invalid_inst_gen;
1480014800
14801 IrInstGen *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn_entry, container_ptr,
14801 Stage1AirInst *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn_entry, container_ptr,
1480214802 container_ptr_src);
1480314803 return ir_get_ref(ira, scope, source_node, bound_fn_value, true, false);
1480414804 } else if (tld->id == TldIdVar) {
......@@ -14818,7 +14818,7 @@ static IrInstGen *ir_analyze_container_member_access_inner(IrAnalyze *ira,
1481814818 if (var->const_value->type->id == ZigTypeIdFn) {
1481914819 src_assert(var->const_value->data.x_ptr.special == ConstPtrSpecialFunction, source_node);
1482014820 ZigFn *fn = var->const_value->data.x_ptr.data.fn.fn_entry;
14821 IrInstGen *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn, container_ptr,
14821 Stage1AirInst *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn, container_ptr,
1482214822 container_ptr_src);
1482314823 return ir_get_ref(ira, scope, source_node, bound_fn_value, true, false);
1482414824 }
......@@ -14857,15 +14857,15 @@ static void memoize_field_init_val(CodeGen *codegen, ZigType *container_type, Ty
1485714857 field->type_entry, nullptr, UndefOk);
1485814858}
1485914859
14860static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
14861 TypeStructField *field, IrInstGen *struct_ptr, ZigType *struct_type, bool initializing)
14860static Stage1AirInst *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node,
14861 TypeStructField *field, Stage1AirInst *struct_ptr, ZigType *struct_type, bool initializing)
1486214862{
1486314863 Error err;
1486414864 ZigType *field_type = resolve_struct_field_type(ira->codegen, field);
1486514865 if (field_type == nullptr)
1486614866 return ira->codegen->invalid_inst_gen;
1486714867 if (field->is_comptime) {
14868 IrInstGen *elem = ir_const(ira, scope, source_node, field_type);
14868 Stage1AirInst *elem = ir_const(ira, scope, source_node, field_type);
1486914869 memoize_field_init_val(ira->codegen, struct_type, field);
1487014870 if(field->init_val != nullptr && type_is_invalid(field->init_val->type)){
1487114871 return ira->codegen->invalid_inst_gen;
......@@ -14877,7 +14877,7 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN
1487714877 case OnePossibleValueInvalid:
1487814878 return ira->codegen->invalid_inst_gen;
1487914879 case OnePossibleValueYes: {
14880 IrInstGen *elem = ir_const_move(ira, scope, source_node,
14880 Stage1AirInst *elem = ir_const_move(ira, scope, source_node,
1488114881 get_the_one_possible_value(ira->codegen, field_type));
1488214882 return ir_get_ref(ira, scope, source_node, elem,
1488314883 struct_ptr->value->type->data.pointer.is_const,
......@@ -14941,7 +14941,7 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN
1494114941 field_val->parent.data.p_struct.field_index = i;
1494214942 }
1494314943 }
14944 IrInstGen *result;
14944 Stage1AirInst *result;
1494514945 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
1494614946 result = ir_build_struct_field_ptr(ira, scope, source_node, struct_ptr, field, ptr_type);
1494714947 result->value->special = ConstValSpecialStatic;
......@@ -14959,8 +14959,8 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN
1495914959 return ir_build_struct_field_ptr(ira, scope, source_node, struct_ptr, field, ptr_type);
1496014960}
1496114961
14962static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,
14963 Scope *scope, AstNode *source_node, IrInstGen *container_ptr, ZigType *container_type)
14962static Stage1AirInst *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,
14963 Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, ZigType *container_type)
1496414964{
1496514965 // The type of the field is not available until a store using this pointer happens.
1496614966 // So, here we create a special pointer type which has the inferred struct type and
......@@ -14985,7 +14985,7 @@ static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,
1498514985 if (ptr_val == nullptr)
1498614986 return ira->codegen->invalid_inst_gen;
1498714987
14988 IrInstGen *result;
14988 Stage1AirInst *result;
1498914989 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
1499014990 result = ir_build_cast(ira, scope, source_node, container_ptr_type, container_ptr, CastOpNoop);
1499114991 } else {
......@@ -14999,8 +14999,8 @@ static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name,
1499914999 return ir_build_cast(ira, scope, source_node, field_ptr_type, container_ptr, CastOpNoop);
1500015000}
1500115001
15002static IrInstGen *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name,
15003 Scope *scope, AstNode *source_node, IrInstGen *container_ptr, AstNode *container_ptr_src,
15002static Stage1AirInst *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name,
15003 Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, AstNode *container_ptr_src,
1500415004 ZigType *container_type, bool initializing)
1500515005{
1500615006 Error err;
......@@ -15108,7 +15108,7 @@ static IrInstGen *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name
1510815108 ZigValue *payload_val = union_val->data.x_union.payload;
1510915109 assert(payload_val);
1511015110
15111 IrInstGen *result;
15111 Stage1AirInst *result;
1511215112 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
1511315113 result = ir_build_union_field_ptr(ira, scope, source_node, container_ptr, field, true,
1511415114 initializing, ptr_type);
......@@ -15139,12 +15139,12 @@ static void add_link_lib_symbol(IrAnalyze *ira, Buf *lib_name, Buf *symbol_name,
1513915139 }
1514015140}
1514115141
15142static IrInstGen *ir_error_dependency_loop(IrAnalyze *ira, AstNode* source_node) {
15142static Stage1AirInst *ir_error_dependency_loop(IrAnalyze *ira, AstNode* source_node) {
1514315143 ir_add_error_node(ira, source_node, buf_sprintf("dependency loop detected"));
1514415144 return ira->codegen->invalid_inst_gen;
1514515145}
1514615146
15147static IrInstGen *ir_analyze_decl_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Tld *tld) {
15147static Stage1AirInst *ir_analyze_decl_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Tld *tld) {
1514815148 resolve_top_level_decl(ira->codegen, tld, source_node, true);
1514915149 if (tld->resolution == TldResolutionInvalid) {
1515015150 return ira->codegen->invalid_inst_gen;
......@@ -15181,7 +15181,7 @@ static IrInstGen *ir_analyze_decl_ref(IrAnalyze *ira, Scope *scope, AstNode *sou
1518115181 add_link_lib_symbol(ira, tld_fn->extern_lib_name, &fn_entry->symbol_name, source_node);
1518215182 }
1518315183
15184 IrInstGen *fn_inst = ir_const_fn(ira, scope, source_node, fn_entry);
15184 Stage1AirInst *fn_inst = ir_const_fn(ira, scope, source_node, fn_entry);
1518515185 return ir_get_ref(ira, scope, source_node, fn_inst, true, false);
1518615186 }
1518715187 }
......@@ -15199,9 +15199,9 @@ static ErrorTableEntry *find_err_table_entry(ZigType *err_set_type, Buf *field_n
1519915199 return nullptr;
1520015200}
1520115201
15202static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFieldPtr *field_ptr_instruction) {
15202static Stage1AirInst *ir_analyze_instruction_field_ptr(IrAnalyze *ira, Stage1ZirInstFieldPtr *field_ptr_instruction) {
1520315203 Error err;
15204 IrInstGen *container_ptr = field_ptr_instruction->container_ptr->child;
15204 Stage1AirInst *container_ptr = field_ptr_instruction->container_ptr->child;
1520515205 if (type_is_invalid(container_ptr->value->type))
1520615206 return ira->codegen->invalid_inst_gen;
1520715207
......@@ -15209,7 +15209,7 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel
1520915209
1521015210 Buf *field_name = field_ptr_instruction->field_name_buffer;
1521115211 if (!field_name) {
15212 IrInstGen *field_name_expr = field_ptr_instruction->field_name_expr->child;
15212 Stage1AirInst *field_name_expr = field_ptr_instruction->field_name_expr->child;
1521315213 field_name = ir_resolve_str(ira, field_name_expr);
1521415214 if (!field_name)
1521515215 return ira->codegen->invalid_inst_gen;
......@@ -15221,22 +15221,22 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel
1522115221 if (type_is_invalid(container_type)) {
1522215222 return ira->codegen->invalid_inst_gen;
1522315223 } else if (is_tuple(container_type) && !field_ptr_instruction->initializing && buf_eql_str(field_name, "len")) {
15224 IrInstGen *len_inst = ir_const_unsigned(ira, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node,
15224 Stage1AirInst *len_inst = ir_const_unsigned(ira, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node,
1522515225 container_type->data.structure.src_field_count);
1522615226 return ir_get_ref(ira, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node, len_inst, true, false);
1522715227 } else if (is_slice(container_type) || is_container_ref(container_type)) {
1522815228 assert(container_ptr->value->type->id == ZigTypeIdPointer);
1522915229 if (container_type->id == ZigTypeIdPointer) {
1523015230 ZigType *bare_type = container_ref_type(container_type);
15231 IrInstGen *container_child = ir_get_deref(ira, field_ptr_instruction->base.scope,
15231 Stage1AirInst *container_child = ir_get_deref(ira, field_ptr_instruction->base.scope,
1523215232 field_ptr_instruction->base.source_node, container_ptr, nullptr);
15233 IrInstGen *result = ir_analyze_container_field_ptr(ira, field_name,
15233 Stage1AirInst *result = ir_analyze_container_field_ptr(ira, field_name,
1523415234 field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node,
1523515235 container_child, field_ptr_instruction->container_ptr->source_node, bare_type,
1523615236 field_ptr_instruction->initializing);
1523715237 return result;
1523815238 } else {
15239 IrInstGen *result = ir_analyze_container_field_ptr(ira, field_name,
15239 Stage1AirInst *result = ir_analyze_container_field_ptr(ira, field_name,
1524015240 field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node,
1524115241 container_ptr, field_ptr_instruction->container_ptr->source_node,
1524215242 container_type, field_ptr_instruction->initializing);
......@@ -15390,26 +15390,26 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel
1539015390 }
1539115391}
1539215392
15393static IrInstGen *ir_analyze_instruction_store_ptr(IrAnalyze *ira, IrInstSrcStorePtr *instruction) {
15394 IrInstGen *ptr = instruction->ptr->child;
15393static Stage1AirInst *ir_analyze_instruction_store_ptr(IrAnalyze *ira, Stage1ZirInstStorePtr *instruction) {
15394 Stage1AirInst *ptr = instruction->ptr->child;
1539515395 if (type_is_invalid(ptr->value->type))
1539615396 return ira->codegen->invalid_inst_gen;
1539715397
15398 IrInstGen *value = instruction->value->child;
15398 Stage1AirInst *value = instruction->value->child;
1539915399 if (type_is_invalid(value->value->type))
1540015400 return ira->codegen->invalid_inst_gen;
1540115401
1540215402 return ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, ptr, value, instruction->allow_write_through_const);
1540315403}
1540415404
15405static IrInstGen *ir_analyze_instruction_load_ptr(IrAnalyze *ira, IrInstSrcLoadPtr *instruction) {
15406 IrInstGen *ptr = instruction->ptr->child;
15405static Stage1AirInst *ir_analyze_instruction_load_ptr(IrAnalyze *ira, Stage1ZirInstLoadPtr *instruction) {
15406 Stage1AirInst *ptr = instruction->ptr->child;
1540715407 if (type_is_invalid(ptr->value->type))
1540815408 return ira->codegen->invalid_inst_gen;
1540915409 return ir_get_deref(ira, instruction->base.scope, instruction->base.source_node, ptr, nullptr);
1541015410}
1541115411
15412static IrInstGen *ir_analyze_instruction_typeof(IrAnalyze *ira, IrInstSrcTypeOf *typeof_instruction) {
15412static Stage1AirInst *ir_analyze_instruction_typeof(IrAnalyze *ira, Stage1ZirInstTypeOf *typeof_instruction) {
1541315413 ZigType *type_entry;
1541415414
1541515415 const size_t value_count = typeof_instruction->value_count;
......@@ -15418,9 +15418,9 @@ static IrInstGen *ir_analyze_instruction_typeof(IrAnalyze *ira, IrInstSrcTypeOf
1541815418 if (value_count < 2) {
1541915419 type_entry = typeof_instruction->value.scalar->child->value->type;
1542015420 } else {
15421 IrInstGen **args = heap::c_allocator.allocate<IrInstGen*>(value_count);
15421 Stage1AirInst **args = heap::c_allocator.allocate<Stage1AirInst*>(value_count);
1542215422 for (size_t i = 0; i < value_count; i += 1) {
15423 IrInstGen *value = typeof_instruction->value.list[i]->child;
15423 Stage1AirInst *value = typeof_instruction->value.list[i]->child;
1542415424 if (type_is_invalid(value->value->type))
1542515425 return ira->codegen->invalid_inst_gen;
1542615426 args[i] = value;
......@@ -15438,13 +15438,13 @@ static IrInstGen *ir_analyze_instruction_typeof(IrAnalyze *ira, IrInstSrcTypeOf
1543815438 return ir_const_type(ira, typeof_instruction->base.scope, typeof_instruction->base.source_node, type_entry);
1543915439}
1544015440
15441static IrInstGen *ir_analyze_instruction_set_cold(IrAnalyze *ira, IrInstSrcSetCold *instruction) {
15441static Stage1AirInst *ir_analyze_instruction_set_cold(IrAnalyze *ira, Stage1ZirInstSetCold *instruction) {
1544215442 if (ira->new_irb.exec->is_inline) {
1544315443 // ignore setCold when running functions at compile time
1544415444 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
1544515445 }
1544615446
15447 IrInstGen *is_cold_value = instruction->is_cold->child;
15447 Stage1AirInst *is_cold_value = instruction->is_cold->child;
1544815448 bool want_cold;
1544915449 if (!ir_resolve_bool(ira, is_cold_value, &want_cold))
1545015450 return ira->codegen->invalid_inst_gen;
......@@ -15467,8 +15467,8 @@ static IrInstGen *ir_analyze_instruction_set_cold(IrAnalyze *ira, IrInstSrcSetCo
1546715467 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
1546815468}
1546915469
15470static IrInstGen *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira,
15471 IrInstSrcSetRuntimeSafety *set_runtime_safety_instruction)
15470static Stage1AirInst *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira,
15471 Stage1ZirInstSetRuntimeSafety *set_runtime_safety_instruction)
1547215472{
1547315473 if (ira->new_irb.exec->is_inline) {
1547415474 // ignore setRuntimeSafety when running functions at compile time
......@@ -15505,7 +15505,7 @@ static IrInstGen *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira,
1550515505 }
1550615506 assert(scope != nullptr);
1550715507
15508 IrInstGen *safety_on_value = set_runtime_safety_instruction->safety_on->child;
15508 Stage1AirInst *safety_on_value = set_runtime_safety_instruction->safety_on->child;
1550915509 bool want_runtime_safety;
1551015510 if (!ir_resolve_bool(ira, safety_on_value, &want_runtime_safety))
1551115511 return ira->codegen->invalid_inst_gen;
......@@ -15524,8 +15524,8 @@ static IrInstGen *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira,
1552415524 set_runtime_safety_instruction->base.source_node);
1552515525}
1552615526
15527static IrInstGen *ir_analyze_instruction_set_float_mode(IrAnalyze *ira,
15528 IrInstSrcSetFloatMode *instruction)
15527static Stage1AirInst *ir_analyze_instruction_set_float_mode(IrAnalyze *ira,
15528 Stage1ZirInstSetFloatMode *instruction)
1552915529{
1553015530 if (ira->new_irb.exec->is_inline) {
1553115531 // ignore setFloatMode when running functions at compile time
......@@ -15561,7 +15561,7 @@ static IrInstGen *ir_analyze_instruction_set_float_mode(IrAnalyze *ira,
1556115561 }
1556215562 assert(scope != nullptr);
1556315563
15564 IrInstGen *float_mode_value = instruction->mode_value->child;
15564 Stage1AirInst *float_mode_value = instruction->mode_value->child;
1556515565 FloatMode float_mode_scalar;
1556615566 if (!ir_resolve_float_mode(ira, float_mode_value, &float_mode_scalar))
1556715567 return ira->codegen->invalid_inst_gen;
......@@ -15579,7 +15579,7 @@ static IrInstGen *ir_analyze_instruction_set_float_mode(IrAnalyze *ira,
1557915579 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
1558015580}
1558115581
15582static IrInstGen *ir_analyze_instruction_any_frame_type(IrAnalyze *ira, IrInstSrcAnyFrameType *instruction) {
15582static Stage1AirInst *ir_analyze_instruction_any_frame_type(IrAnalyze *ira, Stage1ZirInstAnyFrameType *instruction) {
1558315583 ZigType *payload_type = nullptr;
1558415584 if (instruction->payload_type != nullptr) {
1558515585 payload_type = ir_resolve_type(ira, instruction->payload_type->child);
......@@ -15591,8 +15591,8 @@ static IrInstGen *ir_analyze_instruction_any_frame_type(IrAnalyze *ira, IrInstSr
1559115591 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, any_frame_type);
1559215592}
1559315593
15594static IrInstGen *ir_analyze_instruction_slice_type(IrAnalyze *ira, IrInstSrcSliceType *slice_type_instruction) {
15595 IrInstGen *result = ir_const(ira, slice_type_instruction->base.scope,
15594static Stage1AirInst *ir_analyze_instruction_slice_type(IrAnalyze *ira, Stage1ZirInstSliceType *slice_type_instruction) {
15595 Stage1AirInst *result = ir_const(ira, slice_type_instruction->base.scope,
1559615596 slice_type_instruction->base.source_node, ira->codegen->builtin_types.entry_type);
1559715597 result->value->special = ConstValSpecialLazy;
1559815598
......@@ -15643,7 +15643,7 @@ static size_t find_asm_index(CodeGen *g, AstNode *node, AsmToken *tok, Buf *src_
1564315643 return SIZE_MAX;
1564415644}
1564515645
15646static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_instruction) {
15646static Stage1AirInst *ir_analyze_instruction_asm(IrAnalyze *ira, Stage1ZirInstAsm *asm_instruction) {
1564715647 Error err;
1564815648
1564915649 assert(asm_instruction->base.source_node->type == NodeTypeAsmExpr);
......@@ -15688,8 +15688,8 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i
1568815688
1568915689 // TODO validate the output types and variable types
1569015690
15691 IrInstGen **input_list = heap::c_allocator.allocate<IrInstGen *>(asm_expr->input_list.length);
15692 IrInstGen **output_types = heap::c_allocator.allocate<IrInstGen *>(asm_expr->output_list.length);
15691 Stage1AirInst **input_list = heap::c_allocator.allocate<Stage1AirInst *>(asm_expr->input_list.length);
15692 Stage1AirInst **output_types = heap::c_allocator.allocate<Stage1AirInst *>(asm_expr->output_list.length);
1569315693
1569415694 ZigType *return_type = ira->codegen->builtin_types.entry_void;
1569515695 for (size_t i = 0; i < asm_expr->output_list.length; i += 1) {
......@@ -15703,7 +15703,7 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i
1570315703 }
1570415704
1570515705 for (size_t i = 0; i < asm_expr->input_list.length; i += 1) {
15706 IrInstGen *const input_value = asm_instruction->input_list[i]->child;
15706 Stage1AirInst *const input_value = asm_instruction->input_list[i]->child;
1570715707 if (type_is_invalid(input_value->value->type))
1570815708 return ira->codegen->invalid_inst_gen;
1570915709
......@@ -15724,8 +15724,8 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i
1572415724 asm_instruction->has_side_effects, return_type);
1572515725}
1572615726
15727static IrInstGen *ir_analyze_instruction_array_type(IrAnalyze *ira, IrInstSrcArrayType *array_type_instruction) {
15728 IrInstGen *result = ir_const(ira, array_type_instruction->base.scope,
15727static Stage1AirInst *ir_analyze_instruction_array_type(IrAnalyze *ira, Stage1ZirInstArrayType *array_type_instruction) {
15728 Stage1AirInst *result = ir_const(ira, array_type_instruction->base.scope,
1572915729 array_type_instruction->base.source_node, ira->codegen->builtin_types.entry_type);
1573015730 result->value->special = ConstValSpecialLazy;
1573115731
......@@ -15750,8 +15750,8 @@ static IrInstGen *ir_analyze_instruction_array_type(IrAnalyze *ira, IrInstSrcArr
1575015750 return result;
1575115751}
1575215752
15753static IrInstGen *ir_analyze_instruction_size_of(IrAnalyze *ira, IrInstSrcSizeOf *instruction) {
15754 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int);
15753static Stage1AirInst *ir_analyze_instruction_size_of(IrAnalyze *ira, Stage1ZirInstSizeOf *instruction) {
15754 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int);
1575515755 result->value->special = ConstValSpecialLazy;
1575615756
1575715757 LazyValueSizeOf *lazy_size_of = heap::c_allocator.create<LazyValueSizeOf>();
......@@ -15767,7 +15767,7 @@ static IrInstGen *ir_analyze_instruction_size_of(IrAnalyze *ira, IrInstSrcSizeOf
1576715767 return result;
1576815768}
1576915769
15770static IrInstGen *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) {
15770static Stage1AirInst *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) {
1577115771 ZigType *type_entry = value->value->type;
1577215772
1577315773 if (type_entry->id == ZigTypeIdPointer && type_entry->data.pointer.allow_zero) {
......@@ -15803,16 +15803,16 @@ static IrInstGen *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode
1580315803 }
1580415804}
1580515805
15806static IrInstGen *ir_analyze_instruction_test_non_null(IrAnalyze *ira, IrInstSrcTestNonNull *instruction) {
15807 IrInstGen *value = instruction->value->child;
15806static Stage1AirInst *ir_analyze_instruction_test_non_null(IrAnalyze *ira, Stage1ZirInstTestNonNull *instruction) {
15807 Stage1AirInst *value = instruction->value->child;
1580815808 if (type_is_invalid(value->value->type))
1580915809 return ira->codegen->invalid_inst_gen;
1581015810
1581115811 return ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, value);
1581215812}
1581315813
15814static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
15815 IrInstGen *base_ptr, bool safety_check_on, bool initializing)
15814static Stage1AirInst *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
15815 Stage1AirInst *base_ptr, bool safety_check_on, bool initializing)
1581615816{
1581715817 Error err;
1581815818
......@@ -15841,7 +15841,7 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop
1584115841 }
1584215842 if (!safety_check_on)
1584315843 return base_ptr;
15844 IrInstGen *c_ptr_val = ir_get_deref(ira, scope, source_node, base_ptr, nullptr);
15844 Stage1AirInst *c_ptr_val = ir_get_deref(ira, scope, source_node, base_ptr, nullptr);
1584515845 ir_build_assert_non_null(ira, scope, source_node, c_ptr_val);
1584615846 return base_ptr;
1584715847 }
......@@ -15900,7 +15900,7 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop
1590015900 }
1590115901 }
1590215902
15903 IrInstGen *result;
15903 Stage1AirInst *result;
1590415904 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
1590515905 result = ir_build_optional_unwrap_ptr_gen(ira, scope, source_node, base_ptr, false,
1590615906 initializing, result_type);
......@@ -15935,10 +15935,10 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop
1593515935 initializing, result_type);
1593615936}
1593715937
15938static IrInstGen *ir_analyze_instruction_optional_unwrap_ptr(IrAnalyze *ira,
15939 IrInstSrcOptionalUnwrapPtr *instruction)
15938static Stage1AirInst *ir_analyze_instruction_optional_unwrap_ptr(IrAnalyze *ira,
15939 Stage1ZirInstOptionalUnwrapPtr *instruction)
1594015940{
15941 IrInstGen *base_ptr = instruction->base_ptr->child;
15941 Stage1AirInst *base_ptr = instruction->base_ptr->child;
1594215942 if (type_is_invalid(base_ptr->value->type))
1594315943 return ira->codegen->invalid_inst_gen;
1594415944
......@@ -15946,12 +15946,12 @@ static IrInstGen *ir_analyze_instruction_optional_unwrap_ptr(IrAnalyze *ira,
1594615946 instruction->safety_check_on, false);
1594715947}
1594815948
15949static IrInstGen *ir_analyze_instruction_ctz(IrAnalyze *ira, IrInstSrcCtz *instruction) {
15949static Stage1AirInst *ir_analyze_instruction_ctz(IrAnalyze *ira, Stage1ZirInstCtz *instruction) {
1595015950 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
1595115951 if (type_is_invalid(int_type))
1595215952 return ira->codegen->invalid_inst_gen;
1595315953
15954 IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type);
15954 Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type);
1595515955 if (type_is_invalid(op->value->type))
1595615956 return ira->codegen->invalid_inst_gen;
1595715957
......@@ -15972,12 +15972,12 @@ static IrInstGen *ir_analyze_instruction_ctz(IrAnalyze *ira, IrInstSrcCtz *instr
1597215972 return ir_build_ctz_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op);
1597315973}
1597415974
15975static IrInstGen *ir_analyze_instruction_clz(IrAnalyze *ira, IrInstSrcClz *instruction) {
15975static Stage1AirInst *ir_analyze_instruction_clz(IrAnalyze *ira, Stage1ZirInstClz *instruction) {
1597615976 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
1597715977 if (type_is_invalid(int_type))
1597815978 return ira->codegen->invalid_inst_gen;
1597915979
15980 IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type);
15980 Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type);
1598115981 if (type_is_invalid(op->value->type))
1598215982 return ira->codegen->invalid_inst_gen;
1598315983
......@@ -15998,12 +15998,12 @@ static IrInstGen *ir_analyze_instruction_clz(IrAnalyze *ira, IrInstSrcClz *instr
1599815998 return ir_build_clz_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op);
1599915999}
1600016000
16001static IrInstGen *ir_analyze_instruction_pop_count(IrAnalyze *ira, IrInstSrcPopCount *instruction) {
16001static Stage1AirInst *ir_analyze_instruction_pop_count(IrAnalyze *ira, Stage1ZirInstPopCount *instruction) {
1600216002 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
1600316003 if (type_is_invalid(int_type))
1600416004 return ira->codegen->invalid_inst_gen;
1600516005
16006 IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type);
16006 Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type);
1600716007 if (type_is_invalid(op->value->type))
1600816008 return ira->codegen->invalid_inst_gen;
1600916009
......@@ -16029,7 +16029,7 @@ static IrInstGen *ir_analyze_instruction_pop_count(IrAnalyze *ira, IrInstSrcPopC
1602916029 return ir_build_pop_count_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op);
1603016030}
1603116031
16032static IrInstGen *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) {
16032static Stage1AirInst *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) {
1603316033 if (type_is_invalid(value->value->type))
1603416034 return ira->codegen->invalid_inst_gen;
1603516035
......@@ -16055,7 +16055,7 @@ static IrInstGen *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *so
1605516055 if (!val)
1605616056 return ira->codegen->invalid_inst_gen;
1605716057
16058 IrInstGenConst *const_instruction = ir_create_inst_gen<IrInstGenConst>(&ira->new_irb,
16058 Stage1AirInstConst *const_instruction = ir_create_inst_gen<Stage1AirInstConst>(&ira->new_irb,
1605916059 scope, source_node);
1606016060 const_instruction->base.value->type = tag_type;
1606116061 const_instruction->base.value->special = ConstValSpecialStatic;
......@@ -16066,10 +16066,10 @@ static IrInstGen *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *so
1606616066 return ir_build_union_tag(ira, scope, source_node, value, tag_type);
1606716067}
1606816068
16069static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,
16070 IrInstSrcSwitchBr *switch_br_instruction)
16069static Stage1AirInst *ir_analyze_instruction_switch_br(IrAnalyze *ira,
16070 Stage1ZirInstSwitchBr *switch_br_instruction)
1607116071{
16072 IrInstGen *target_value = switch_br_instruction->target_value->child;
16072 Stage1AirInst *target_value = switch_br_instruction->target_value->child;
1607316073 if (type_is_invalid(target_value->value->type))
1607416074 return ir_unreach_error(ira);
1607516075
......@@ -16093,12 +16093,12 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,
1609316093
1609416094 Stage1ZirBasicBlock *old_dest_block = switch_br_instruction->else_block;
1609516095 for (size_t i = 0; i < case_count; i += 1) {
16096 IrInstSrcSwitchBrCase *old_case = &switch_br_instruction->cases[i];
16097 IrInstGen *case_value = old_case->value->child;
16096 Stage1ZirInstSwitchBrCase *old_case = &switch_br_instruction->cases[i];
16097 Stage1AirInst *case_value = old_case->value->child;
1609816098 if (type_is_invalid(case_value->value->type))
1609916099 return ir_unreach_error(ira);
1610016100
16101 IrInstGen *casted_case_value = ir_implicit_cast(ira, case_value, target_value->value->type);
16101 Stage1AirInst *casted_case_value = ir_implicit_cast(ira, case_value, target_value->value->type);
1610216102 if (type_is_invalid(casted_case_value->value->type))
1610316103 return ir_unreach_error(ira);
1610416104
......@@ -16115,17 +16115,17 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,
1611516115 if (is_comptime || old_dest_block->ref_count == 1) {
1611616116 return ir_inline_bb(ira, switch_br_instruction->base.source_node, old_dest_block);
1611716117 } else {
16118 IrBasicBlockGen *new_dest_block = ir_get_new_bb(ira, old_dest_block, &switch_br_instruction->base);
16119 IrInstGen *result = ir_build_br_gen(ira, switch_br_instruction->base.scope,
16118 Stage1AirBasicBlock *new_dest_block = ir_get_new_bb(ira, old_dest_block, &switch_br_instruction->base);
16119 Stage1AirInst *result = ir_build_br_gen(ira, switch_br_instruction->base.scope,
1612016120 switch_br_instruction->base.source_node, new_dest_block);
1612116121 return ir_finish_anal(ira, result);
1612216122 }
1612316123 }
1612416124
16125 IrInstGenSwitchBrCase *cases = heap::c_allocator.allocate<IrInstGenSwitchBrCase>(case_count);
16125 Stage1AirInstSwitchBrCase *cases = heap::c_allocator.allocate<Stage1AirInstSwitchBrCase>(case_count);
1612616126 for (size_t i = 0; i < case_count; i += 1) {
16127 IrInstSrcSwitchBrCase *old_case = &switch_br_instruction->cases[i];
16128 IrInstGenSwitchBrCase *new_case = &cases[i];
16127 Stage1ZirInstSwitchBrCase *old_case = &switch_br_instruction->cases[i];
16128 Stage1AirInstSwitchBrCase *new_case = &cases[i];
1612916129 new_case->block = ir_get_new_bb(ira, old_case->block, &switch_br_instruction->base);
1613016130 new_case->value = ira->codegen->invalid_inst_gen;
1613116131
......@@ -16135,12 +16135,12 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,
1613516135 // it back after the loop.
1613616136 new_case->block->ref_instruction = nullptr;
1613716137
16138 IrInstSrc *old_value = old_case->value;
16139 IrInstGen *new_value = old_value->child;
16138 Stage1ZirInst *old_value = old_case->value;
16139 Stage1AirInst *new_value = old_value->child;
1614016140 if (type_is_invalid(new_value->value->type))
1614116141 continue;
1614216142
16143 IrInstGen *casted_new_value = ir_implicit_cast(ira, new_value, target_value->value->type);
16143 Stage1AirInst *casted_new_value = ir_implicit_cast(ira, new_value, target_value->value->type);
1614416144 if (type_is_invalid(casted_new_value->value->type))
1614516145 continue;
1614616146
......@@ -16151,23 +16151,23 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,
1615116151 }
1615216152
1615316153 for (size_t i = 0; i < case_count; i += 1) {
16154 IrInstGenSwitchBrCase *new_case = &cases[i];
16154 Stage1AirInstSwitchBrCase *new_case = &cases[i];
1615516155 if (type_is_invalid(new_case->value->value->type))
1615616156 return ir_unreach_error(ira);
1615716157 new_case->block->ref_instruction = &switch_br_instruction->base;
1615816158 }
1615916159
16160 IrBasicBlockGen *new_else_block = ir_get_new_bb(ira, switch_br_instruction->else_block, &switch_br_instruction->base);
16161 IrInstGenSwitchBr *switch_br = ir_build_switch_br_gen(ira, switch_br_instruction->base.scope,
16160 Stage1AirBasicBlock *new_else_block = ir_get_new_bb(ira, switch_br_instruction->else_block, &switch_br_instruction->base);
16161 Stage1AirInstSwitchBr *switch_br = ir_build_switch_br_gen(ira, switch_br_instruction->base.scope,
1616216162 switch_br_instruction->base.source_node, target_value, new_else_block, case_count, cases);
1616316163 return ir_finish_anal(ira, &switch_br->base);
1616416164}
1616516165
16166static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,
16167 IrInstSrcSwitchTarget *switch_target_instruction)
16166static Stage1AirInst *ir_analyze_instruction_switch_target(IrAnalyze *ira,
16167 Stage1ZirInstSwitchTarget *switch_target_instruction)
1616816168{
1616916169 Error err;
16170 IrInstGen *target_value_ptr = switch_target_instruction->target_value_ptr->child;
16170 Stage1AirInst *target_value_ptr = switch_target_instruction->target_value_ptr->child;
1617116171 if (type_is_invalid(target_value_ptr->value->type))
1617216172 return ira->codegen->invalid_inst_gen;
1617316173
......@@ -16207,14 +16207,14 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,
1620716207 case ZigTypeIdFn:
1620816208 case ZigTypeIdErrorSet: {
1620916209 if (pointee_val) {
16210 IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope,
16210 Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope,
1621116211 switch_target_instruction->base.source_node, nullptr);
1621216212 copy_const_val(ira->codegen, result->value, pointee_val);
1621316213 result->value->type = target_type;
1621416214 return result;
1621516215 }
1621616216
16217 IrInstGen *result = ir_get_deref(ira, switch_target_instruction->base.scope,
16217 Stage1AirInst *result = ir_get_deref(ira, switch_target_instruction->base.scope,
1621816218 switch_target_instruction->base.source_node, target_value_ptr, nullptr);
1621916219 result->value->type = target_type;
1622016220 return result;
......@@ -16234,19 +16234,19 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,
1623416234 assert(tag_type != nullptr);
1623516235 assert(tag_type->id == ZigTypeIdEnum);
1623616236 if (pointee_val) {
16237 IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type);
16237 Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type);
1623816238 bigint_init_bigint(&result->value->data.x_enum_tag, &pointee_val->data.x_union.tag);
1623916239 return result;
1624016240 }
1624116241
1624216242 if (can_fold_enum_type(tag_type)) {
16243 IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type);
16243 Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type);
1624416244 TypeEnumField *only_field = &tag_type->data.enumeration.fields[0];
1624516245 bigint_init_bigint(&result->value->data.x_enum_tag, &only_field->value);
1624616246 return result;
1624716247 }
1624816248
16249 IrInstGen *union_value = ir_get_deref(ira, switch_target_instruction->base.scope,
16249 Stage1AirInst *union_value = ir_get_deref(ira, switch_target_instruction->base.scope,
1625016250 switch_target_instruction->base.source_node, target_value_ptr, nullptr);
1625116251 union_value->value->type = target_type;
1625216252
......@@ -16258,18 +16258,18 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,
1625816258
1625916259 if (can_fold_enum_type(target_type)) {
1626016260 TypeEnumField *only_field = &target_type->data.enumeration.fields[0];
16261 IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type);
16261 Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type);
1626216262 bigint_init_bigint(&result->value->data.x_enum_tag, &only_field->value);
1626316263 return result;
1626416264 }
1626516265
1626616266 if (pointee_val) {
16267 IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type);
16267 Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type);
1626816268 bigint_init_bigint(&result->value->data.x_enum_tag, &pointee_val->data.x_enum_tag);
1626916269 return result;
1627016270 }
1627116271
16272 IrInstGen *enum_value = ir_get_deref(ira, switch_target_instruction->base.scope,
16272 Stage1AirInst *enum_value = ir_get_deref(ira, switch_target_instruction->base.scope,
1627316273 switch_target_instruction->base.source_node, target_value_ptr, nullptr);
1627416274 enum_value->value->type = target_type;
1627516275 return enum_value;
......@@ -16293,8 +16293,8 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira,
1629316293 zig_unreachable();
1629416294}
1629516295
16296static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwitchVar *instruction) {
16297 IrInstGen *target_value_ptr = instruction->target_value_ptr->child;
16296static Stage1AirInst *ir_analyze_instruction_switch_var(IrAnalyze *ira, Stage1ZirInstSwitchVar *instruction) {
16297 Stage1AirInst *target_value_ptr = instruction->target_value_ptr->child;
1629816298 if (type_is_invalid(target_value_ptr->value->type))
1629916299 return ira->codegen->invalid_inst_gen;
1630016300
......@@ -16307,11 +16307,11 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi
1630716307 assert(enum_type->id == ZigTypeIdEnum);
1630816308 assert(instruction->prongs_len > 0);
1630916309
16310 IrInstGen *first_prong_value = instruction->prongs_ptr[0]->child;
16310 Stage1AirInst *first_prong_value = instruction->prongs_ptr[0]->child;
1631116311 if (type_is_invalid(first_prong_value->value->type))
1631216312 return ira->codegen->invalid_inst_gen;
1631316313
16314 IrInstGen *first_casted_prong_value = ir_implicit_cast(ira, first_prong_value, enum_type);
16314 Stage1AirInst *first_casted_prong_value = ir_implicit_cast(ira, first_prong_value, enum_type);
1631516315 if (type_is_invalid(first_casted_prong_value->value->type))
1631616316 return ira->codegen->invalid_inst_gen;
1631716317
......@@ -16323,11 +16323,11 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi
1632316323
1632416324 ErrorMsg *invalid_payload_msg = nullptr;
1632516325 for (size_t prong_i = 1; prong_i < instruction->prongs_len; prong_i += 1) {
16326 IrInstGen *this_prong_inst = instruction->prongs_ptr[prong_i]->child;
16326 Stage1AirInst *this_prong_inst = instruction->prongs_ptr[prong_i]->child;
1632716327 if (type_is_invalid(this_prong_inst->value->type))
1632816328 return ira->codegen->invalid_inst_gen;
1632916329
16330 IrInstGen *this_casted_prong_value = ir_implicit_cast(ira, this_prong_inst, enum_type);
16330 Stage1AirInst *this_casted_prong_value = ir_implicit_cast(ira, this_prong_inst, enum_type);
1633116331 if (type_is_invalid(this_casted_prong_value->value->type))
1633216332 return ira->codegen->invalid_inst_gen;
1633316333
......@@ -16362,7 +16362,7 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi
1636216362 if (pointee_val == nullptr)
1636316363 return ira->codegen->invalid_inst_gen;
1636416364
16365 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node,
16365 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node,
1636616366 get_pointer_to_type(ira->codegen, first_field->type_entry,
1636716367 target_val_ptr->type->data.pointer.is_const));
1636816368 ZigValue *out_val = result->value;
......@@ -16416,10 +16416,10 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi
1641616416 }
1641716417}
1641816418
16419static IrInstGen *ir_analyze_instruction_switch_else_var(IrAnalyze *ira,
16420 IrInstSrcSwitchElseVar *instruction)
16419static Stage1AirInst *ir_analyze_instruction_switch_else_var(IrAnalyze *ira,
16420 Stage1ZirInstSwitchElseVar *instruction)
1642116421{
16422 IrInstGen *target_value_ptr = instruction->target_value_ptr->child;
16422 Stage1AirInst *target_value_ptr = instruction->target_value_ptr->child;
1642316423 if (type_is_invalid(target_value_ptr->value->type))
1642416424 return ira->codegen->invalid_inst_gen;
1642516425
......@@ -16441,8 +16441,8 @@ static IrInstGen *ir_analyze_instruction_switch_else_var(IrAnalyze *ira,
1644116441 // We may not have any case in the switch if this is a lone else
1644216442 const size_t switch_cases = instruction->switch_br ? instruction->switch_br->case_count : 0;
1644316443 for (size_t case_i = 0; case_i < switch_cases; case_i += 1) {
16444 IrInstSrcSwitchBrCase *br_case = &instruction->switch_br->cases[case_i];
16445 IrInstGen *case_expr = br_case->value->child;
16444 Stage1ZirInstSwitchBrCase *br_case = &instruction->switch_br->cases[case_i];
16445 Stage1AirInst *case_expr = br_case->value->child;
1644616446 if (case_expr->value->type->id == ZigTypeIdErrorSet) {
1644716447 ErrorTableEntry *err = ir_resolve_error(ira, case_expr);
1644816448 if (err == nullptr)
......@@ -16498,10 +16498,10 @@ static IrInstGen *ir_analyze_instruction_switch_else_var(IrAnalyze *ira,
1649816498 return target_value_ptr;
1649916499}
1650016500
16501static IrInstGen *ir_analyze_instruction_import(IrAnalyze *ira, IrInstSrcImport *import_instruction) {
16501static Stage1AirInst *ir_analyze_instruction_import(IrAnalyze *ira, Stage1ZirInstImport *import_instruction) {
1650216502 Error err;
1650316503
16504 IrInstGen *name_value = import_instruction->name->child;
16504 Stage1AirInst *name_value = import_instruction->name->child;
1650516505 Buf *import_target_str = ir_resolve_str(ira, name_value);
1650616506 if (!import_target_str)
1650716507 return ira->codegen->invalid_inst_gen;
......@@ -16534,8 +16534,8 @@ static IrInstGen *ir_analyze_instruction_import(IrAnalyze *ira, IrInstSrcImport
1653416534 return ir_const_type(ira, import_instruction->base.scope, import_instruction->base.source_node, target_import);
1653516535}
1653616536
16537static IrInstGen *ir_analyze_instruction_ref(IrAnalyze *ira, IrInstSrcRef *ref_instruction) {
16538 IrInstGen *value = ref_instruction->value->child;
16537static Stage1AirInst *ir_analyze_instruction_ref(IrAnalyze *ira, Stage1ZirInstRef *ref_instruction) {
16538 Stage1AirInst *value = ref_instruction->value->child;
1653916539 if (type_is_invalid(value->value->type))
1654016540 return ira->codegen->invalid_inst_gen;
1654116541
......@@ -16550,9 +16550,9 @@ static IrInstGen *ir_analyze_instruction_ref(IrAnalyze *ira, IrInstSrcRef *ref_i
1655016550 return ir_get_ref(ira, ref_instruction->base.scope, ref_instruction->base.source_node, value, is_const, is_volatile);
1655116551}
1655216552
16553static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node,
16554 AstNode *field_source_node, ZigType *union_type, Buf *field_name, IrInstGen *field_result_loc,
16555 IrInstGen *result_loc)
16553static Stage1AirInst *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node,
16554 AstNode *field_source_node, ZigType *union_type, Buf *field_name, Stage1AirInst *field_result_loc,
16555 Stage1AirInst *result_loc)
1655616556{
1655716557 Error err;
1655816558 assert(union_type->id == ZigTypeIdUnion);
......@@ -16584,7 +16584,7 @@ static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *s
1658416584 bool is_comptime = ir_should_inline(ira->zir, scope)
1658516585 || type_requires_comptime(ira->codegen, union_type) == ReqCompTimeYes;
1658616586
16587 IrInstGen *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr);
16587 Stage1AirInst *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr);
1658816588 if (is_comptime && !instr_is_comptime(result)) {
1658916589 ir_add_error(ira, field_result_loc,
1659016590 buf_sprintf("unable to evaluate constant expression"));
......@@ -16593,9 +16593,9 @@ static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *s
1659316593 return result;
1659416594}
1659516595
16596static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, AstNode *source_node,
16597 ZigType *container_type, size_t instr_field_count, IrInstSrcContainerInitFieldsField *fields,
16598 IrInstGen *result_loc)
16596static Stage1AirInst *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, AstNode *source_node,
16597 ZigType *container_type, size_t instr_field_count, Stage1ZirInstContainerInitFieldsField *fields,
16598 Stage1AirInst *result_loc)
1659916599{
1660016600 Error err;
1660116601 if (container_type->id == ZigTypeIdUnion) {
......@@ -16604,8 +16604,8 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
1660416604 buf_sprintf("union initialization expects exactly one field"));
1660516605 return ira->codegen->invalid_inst_gen;
1660616606 }
16607 IrInstSrcContainerInitFieldsField *field = &fields[0];
16608 IrInstGen *field_result_loc = field->result_loc->child;
16607 Stage1ZirInstContainerInitFieldsField *field = &fields[0];
16608 Stage1AirInst *field_result_loc = field->result_loc->child;
1660916609 if (type_is_invalid(field_result_loc->value->type))
1661016610 return ira->codegen->invalid_inst_gen;
1661116611
......@@ -16629,10 +16629,10 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
1662916629
1663016630 size_t actual_field_count = container_type->data.structure.src_field_count;
1663116631
16632 IrInstGen *first_non_const_instruction = nullptr;
16632 Stage1AirInst *first_non_const_instruction = nullptr;
1663316633
1663416634 AstNode **field_assign_nodes = heap::c_allocator.allocate<AstNode *>(actual_field_count);
16635 ZigList<IrInstGen *> const_ptrs = {};
16635 ZigList<Stage1AirInst *> const_ptrs = {};
1663616636
1663716637 bool is_comptime = ir_should_inline(ira->zir, scope)
1663816638 || type_requires_comptime(ira->codegen, container_type) == ReqCompTimeYes;
......@@ -16650,9 +16650,9 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
1665016650 // comptime-known values.
1665116651
1665216652 for (size_t i = 0; i < instr_field_count; i += 1) {
16653 IrInstSrcContainerInitFieldsField *field = &fields[i];
16653 Stage1ZirInstContainerInitFieldsField *field = &fields[i];
1665416654
16655 IrInstGen *field_result_loc = field->result_loc->child;
16655 Stage1AirInst *field_result_loc = field->result_loc->child;
1665616656 if (type_is_invalid(field_result_loc->value->type))
1665716657 return ira->codegen->invalid_inst_gen;
1665816658
......@@ -16701,10 +16701,10 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
1670116701 if (type_is_invalid(field->init_val->type))
1670216702 return ira->codegen->invalid_inst_gen;
1670316703
16704 IrInstGen *runtime_inst = ir_const(ira, scope, source_node, field->init_val->type);
16704 Stage1AirInst *runtime_inst = ir_const(ira, scope, source_node, field->init_val->type);
1670516705 copy_const_val(ira->codegen, runtime_inst->value, field->init_val);
1670616706
16707 IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc,
16707 Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc,
1670816708 container_type, true);
1670916709 ir_analyze_store_ptr(ira, scope, source_node, field_ptr, runtime_inst, false);
1671016710 if (instr_is_comptime(field_ptr) && field_ptr->value->data.x_ptr.mut != ConstPtrMutRuntimeVar) {
......@@ -16721,8 +16721,8 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
1672116721 if (const_ptrs.length != actual_field_count) {
1672216722 result_loc->value->special = ConstValSpecialRuntime;
1672316723 for (size_t i = 0; i < const_ptrs.length; i += 1) {
16724 IrInstGen *field_result_loc = const_ptrs.at(i);
16725 IrInstGen *deref = ir_get_deref(ira, field_result_loc->scope,
16724 Stage1AirInst *field_result_loc = const_ptrs.at(i);
16725 Stage1AirInst *deref = ir_get_deref(ira, field_result_loc->scope,
1672616726 field_result_loc->source_node, field_result_loc, nullptr);
1672716727 field_result_loc->value->special = ConstValSpecialRuntime;
1672816728 ir_analyze_store_ptr(ira, field_result_loc->scope, field_result_loc->source_node,
......@@ -16732,7 +16732,7 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
1673216732 }
1673316733
1673416734 const_ptrs.deinit();
16735 IrInstGen *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr);
16735 Stage1AirInst *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr);
1673616736
1673716737 if (is_comptime && !instr_is_comptime(result)) {
1673816738 ir_add_error_node(ira, first_non_const_instruction->source_node,
......@@ -16743,11 +16743,11 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope,
1674316743 return result;
1674416744}
1674516745
16746static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
16747 IrInstSrcContainerInitList *instruction)
16746static Stage1AirInst *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
16747 Stage1ZirInstContainerInitList *instruction)
1674816748{
1674916749 src_assert(instruction->result_loc != nullptr, instruction->base.source_node);
16750 IrInstGen *result_loc = instruction->result_loc->child;
16750 Stage1AirInst *result_loc = instruction->result_loc->child;
1675116751 if (type_is_invalid(result_loc->value->type))
1675216752 return result_loc;
1675316753
......@@ -16778,7 +16778,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
1677816778
1677916779 if (container_type->id == ZigTypeIdStruct && elem_count == 0) {
1678016780 src_assert(instruction->result_loc != nullptr, instruction->base.source_node);
16781 IrInstGen *result_loc = instruction->result_loc->child;
16781 Stage1AirInst *result_loc = instruction->result_loc->child;
1678216782 if (type_is_invalid(result_loc->value->type))
1678316783 return result_loc;
1678416784 return ir_analyze_container_init_fields(ira, instruction->base.scope, instruction->base.source_node, container_type, 0, nullptr, result_loc);
......@@ -16830,7 +16830,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
1683016830 break;
1683116831 }
1683216832
16833 IrInstGen *first_non_const_instruction = nullptr;
16833 Stage1AirInst *first_non_const_instruction = nullptr;
1683416834
1683516835 // The Result Location Mechanism has already emitted runtime instructions to
1683616836 // initialize runtime elements and has omitted instructions for the comptime
......@@ -16839,10 +16839,10 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
1683916839 // array initialization can be a comptime value, overwrite ConstPtrMutInfer with
1684016840 // ConstPtrMutComptimeConst. Otherwise, emit instructions to runtime-initialize the
1684116841 // elements that have comptime-known values.
16842 ZigList<IrInstGen *> const_ptrs = {};
16842 ZigList<Stage1AirInst *> const_ptrs = {};
1684316843
1684416844 for (size_t i = 0; i < elem_count; i += 1) {
16845 IrInstGen *elem_result_loc = instruction->elem_result_loc_list[i]->child;
16845 Stage1AirInst *elem_result_loc = instruction->elem_result_loc_list[i]->child;
1684616846 if (type_is_invalid(elem_result_loc->value->type))
1684716847 return ira->codegen->invalid_inst_gen;
1684816848
......@@ -16861,13 +16861,13 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
1686116861 if (const_ptrs.length != elem_count) {
1686216862 result_loc->value->special = ConstValSpecialRuntime;
1686316863 for (size_t i = 0; i < const_ptrs.length; i += 1) {
16864 IrInstGen *elem_result_loc = const_ptrs.at(i);
16864 Stage1AirInst *elem_result_loc = const_ptrs.at(i);
1686516865 assert(elem_result_loc->value->special == ConstValSpecialStatic);
1686616866 if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) {
1686716867 // This field will be generated comptime; no need to do this.
1686816868 continue;
1686916869 }
16870 IrInstGen *deref = ir_get_deref(ira, elem_result_loc->scope,
16870 Stage1AirInst *deref = ir_get_deref(ira, elem_result_loc->scope,
1687116871 elem_result_loc->source_node, elem_result_loc, nullptr);
1687216872 elem_result_loc->value->special = ConstValSpecialRuntime;
1687316873 ir_analyze_store_ptr(ira, elem_result_loc->scope, elem_result_loc->source_node,
......@@ -16878,7 +16878,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
1687816878
1687916879 const_ptrs.deinit();
1688016880
16881 IrInstGen *result = ir_get_deref(ira, instruction->base.scope, instruction->base.source_node,
16881 Stage1AirInst *result = ir_get_deref(ira, instruction->base.scope, instruction->base.source_node,
1688216882 result_loc, nullptr);
1688316883 // If the result is a tuple, we are allowed to return a struct that uses ConstValSpecialRuntime fields at comptime.
1688416884 if (instr_is_comptime(result) || is_tuple(container_type))
......@@ -16902,11 +16902,11 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira,
1690216902 return result;
1690316903}
1690416904
16905static IrInstGen *ir_analyze_instruction_container_init_fields(IrAnalyze *ira,
16906 IrInstSrcContainerInitFields *instruction)
16905static Stage1AirInst *ir_analyze_instruction_container_init_fields(IrAnalyze *ira,
16906 Stage1ZirInstContainerInitFields *instruction)
1690716907{
1690816908 src_assert(instruction->result_loc != nullptr, instruction->base.source_node);
16909 IrInstGen *result_loc = instruction->result_loc->child;
16909 Stage1AirInst *result_loc = instruction->result_loc->child;
1691016910 if (type_is_invalid(result_loc->value->type))
1691116911 return result_loc;
1691216912
......@@ -16922,8 +16922,8 @@ static IrInstGen *ir_analyze_instruction_container_init_fields(IrAnalyze *ira,
1692216922 instruction->field_count, instruction->fields, result_loc);
1692316923}
1692416924
16925static IrInstGen *ir_analyze_instruction_compile_err(IrAnalyze *ira, IrInstSrcCompileErr *instruction) {
16926 IrInstGen *msg_value = instruction->msg->child;
16925static Stage1AirInst *ir_analyze_instruction_compile_err(IrAnalyze *ira, Stage1ZirInstCompileErr *instruction) {
16926 Stage1AirInst *msg_value = instruction->msg->child;
1692716927 Buf *msg_buf = ir_resolve_str(ira, msg_value);
1692816928 if (!msg_buf)
1692916929 return ira->codegen->invalid_inst_gen;
......@@ -16933,11 +16933,11 @@ static IrInstGen *ir_analyze_instruction_compile_err(IrAnalyze *ira, IrInstSrcCo
1693316933 return ira->codegen->invalid_inst_gen;
1693416934}
1693516935
16936static IrInstGen *ir_analyze_instruction_compile_log(IrAnalyze *ira, IrInstSrcCompileLog *instruction) {
16936static Stage1AirInst *ir_analyze_instruction_compile_log(IrAnalyze *ira, Stage1ZirInstCompileLog *instruction) {
1693716937 Buf buf = BUF_INIT;
1693816938 fprintf(stderr, "| ");
1693916939 for (size_t i = 0; i < instruction->msg_count; i += 1) {
16940 IrInstGen *msg = instruction->msg_list[i]->child;
16940 Stage1AirInst *msg = instruction->msg_list[i]->child;
1694116941 if (type_is_invalid(msg->value->type))
1694216942 return ira->codegen->invalid_inst_gen;
1694316943 buf_resize(&buf, 0);
......@@ -16963,12 +16963,12 @@ static IrInstGen *ir_analyze_instruction_compile_log(IrAnalyze *ira, IrInstSrcCo
1696316963 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
1696416964}
1696516965
16966static IrInstGen *ir_analyze_instruction_err_name(IrAnalyze *ira, IrInstSrcErrName *instruction) {
16967 IrInstGen *value = instruction->value->child;
16966static Stage1AirInst *ir_analyze_instruction_err_name(IrAnalyze *ira, Stage1ZirInstErrName *instruction) {
16967 Stage1AirInst *value = instruction->value->child;
1696816968 if (type_is_invalid(value->value->type))
1696916969 return ira->codegen->invalid_inst_gen;
1697016970
16971 IrInstGen *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_global_error_set);
16971 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_global_error_set);
1697216972 if (type_is_invalid(casted_value->value->type))
1697316973 return ira->codegen->invalid_inst_gen;
1697416974
......@@ -16982,7 +16982,7 @@ static IrInstGen *ir_analyze_instruction_err_name(IrAnalyze *ira, IrInstSrcErrNa
1698216982 ira->codegen, &err->name,
1698316983 ira->codegen->intern.for_zero_byte());
1698416984 }
16985 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
16985 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
1698616986 result->value = err->cached_error_name_val;
1698716987 return result;
1698816988 }
......@@ -16996,16 +16996,16 @@ static IrInstGen *ir_analyze_instruction_err_name(IrAnalyze *ira, IrInstSrcErrNa
1699616996 return ir_build_err_name_gen(ira, instruction->base.scope, instruction->base.source_node, value, str_type);
1699716997}
1699816998
16999static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrcTagName *instruction) {
16999static Stage1AirInst *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, Stage1ZirInstTagName *instruction) {
1700017000 Error err;
17001 IrInstGen *target = instruction->target->child;
17001 Stage1AirInst *target = instruction->target->child;
1700217002 if (type_is_invalid(target->value->type))
1700317003 return ira->codegen->invalid_inst_gen;
1700417004
1700517005 ZigType *target_type = target->value->type;
1700617006
1700717007 if (target_type->id == ZigTypeIdEnumLiteral) {
17008 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
17008 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
1700917009 Buf *field_name = target->value->data.x_enum_literal;
1701017010 result->value = create_sentineled_str_lit(
1701117011 ira->codegen, field_name,
......@@ -17028,7 +17028,7 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc
1702817028
1702917029 if (can_fold_enum_type(target_type)) {
1703017030 TypeEnumField *only_field = &target_type->data.enumeration.fields[0];
17031 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
17031 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
1703217032 result->value = create_sentineled_str_lit(
1703317033 ira->codegen, only_field->name,
1703417034 ira->codegen->intern.for_zero_byte());
......@@ -17047,7 +17047,7 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc
1704717047 buf_sprintf("no tag by value %s", buf_ptr(int_buf)));
1704817048 return ira->codegen->invalid_inst_gen;
1704917049 }
17050 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
17050 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
1705117051 result->value = create_sentineled_str_lit(
1705217052 ira->codegen, field->name,
1705317053 ira->codegen->intern.for_zero_byte());
......@@ -17062,21 +17062,21 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc
1706217062 return ir_build_tag_name_gen(ira, instruction->base.scope, instruction->base.source_node, target, result_type);
1706317063}
1706417064
17065static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,
17066 IrInstSrcFieldParentPtr *instruction)
17065static Stage1AirInst *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,
17066 Stage1ZirInstFieldParentPtr *instruction)
1706717067{
1706817068 Error err;
17069 IrInstGen *type_value = instruction->type_value->child;
17069 Stage1AirInst *type_value = instruction->type_value->child;
1707017070 ZigType *container_type = ir_resolve_type(ira, type_value);
1707117071 if (type_is_invalid(container_type))
1707217072 return ira->codegen->invalid_inst_gen;
1707317073
17074 IrInstGen *field_name_value = instruction->field_name->child;
17074 Stage1AirInst *field_name_value = instruction->field_name->child;
1707517075 Buf *field_name = ir_resolve_str(ira, field_name_value);
1707617076 if (!field_name)
1707717077 return ira->codegen->invalid_inst_gen;
1707817078
17079 IrInstGen *field_ptr = instruction->field_ptr->child;
17079 Stage1AirInst *field_ptr = instruction->field_ptr->child;
1708017080 if (type_is_invalid(field_ptr->value->type))
1708117081 return ira->codegen->invalid_inst_gen;
1708217082
......@@ -17112,7 +17112,7 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,
1711217112 field_ptr->value->type->data.pointer.is_volatile,
1711317113 PtrLenSingle,
1711417114 field_ptr_align, 0, 0, false);
17115 IrInstGen *casted_field_ptr = ir_implicit_cast(ira, field_ptr, field_ptr_type);
17115 Stage1AirInst *casted_field_ptr = ir_implicit_cast(ira, field_ptr, field_ptr_type);
1711617116 if (type_is_invalid(casted_field_ptr->value->type))
1711717117 return ira->codegen->invalid_inst_gen;
1711817118
......@@ -17141,7 +17141,7 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,
1714117141 return ira->codegen->invalid_inst_gen;
1714217142 }
1714317143
17144 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
17144 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
1714517145 ZigValue *out_val = result->value;
1714617146 out_val->data.x_ptr.special = ConstPtrSpecialRef;
1714717147 out_val->data.x_ptr.data.ref.pointee = field_ptr_val->data.x_ptr.data.base_struct.struct_val;
......@@ -17153,8 +17153,8 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira,
1715317153}
1715417154
1715517155static TypeStructField *validate_host_int_byte_offset(IrAnalyze *ira,
17156 IrInstGen *type_value,
17157 IrInstGen *field_name_value,
17156 Stage1AirInst *type_value,
17157 Stage1AirInst *field_name_value,
1715817158 size_t *byte_offset)
1715917159{
1716017160 ZigType *container_type = ir_resolve_type(ira, type_value);
......@@ -17194,12 +17194,12 @@ static TypeStructField *validate_host_int_byte_offset(IrAnalyze *ira,
1719417194 return field;
1719517195}
1719617196
17197static IrInstGen *ir_analyze_instruction_offset_of(IrAnalyze *ira, IrInstSrcOffsetOf *instruction) {
17198 IrInstGen *type_value = instruction->type_value->child;
17197static Stage1AirInst *ir_analyze_instruction_offset_of(IrAnalyze *ira, Stage1ZirInstOffsetOf *instruction) {
17198 Stage1AirInst *type_value = instruction->type_value->child;
1719917199 if (type_is_invalid(type_value->value->type))
1720017200 return ira->codegen->invalid_inst_gen;
1720117201
17202 IrInstGen *field_name_value = instruction->field_name->child;
17202 Stage1AirInst *field_name_value = instruction->field_name->child;
1720317203 size_t host_int_byte_offset = 0;
1720417204 TypeStructField *field = nullptr;
1720517205 if (!(field = validate_host_int_byte_offset(ira, type_value, field_name_value, &host_int_byte_offset)))
......@@ -17209,11 +17209,11 @@ static IrInstGen *ir_analyze_instruction_offset_of(IrAnalyze *ira, IrInstSrcOffs
1720917209 return ir_const_unsigned(ira, instruction->base.scope, instruction->base.source_node, byte_offset);
1721017210}
1721117211
17212static IrInstGen *ir_analyze_instruction_bit_offset_of(IrAnalyze *ira, IrInstSrcBitOffsetOf *instruction) {
17213 IrInstGen *type_value = instruction->type_value->child;
17212static Stage1AirInst *ir_analyze_instruction_bit_offset_of(IrAnalyze *ira, Stage1ZirInstBitOffsetOf *instruction) {
17213 Stage1AirInst *type_value = instruction->type_value->child;
1721417214 if (type_is_invalid(type_value->value->type))
1721517215 return ira->codegen->invalid_inst_gen;
17216 IrInstGen *field_name_value = instruction->field_name->child;
17216 Stage1AirInst *field_name_value = instruction->field_name->child;
1721717217 size_t host_int_byte_offset = 0;
1721817218 TypeStructField *field = nullptr;
1721917219 if (!(field = validate_host_int_byte_offset(ira, type_value, field_name_value, &host_int_byte_offset)))
......@@ -18275,9 +18275,9 @@ static Error ir_make_type_info_value(IrAnalyze *ira, Scope *scope, AstNode *sour
1827518275 return ErrorNone;
1827618276}
1827718277
18278static IrInstGen *ir_analyze_instruction_type_info(IrAnalyze *ira, IrInstSrcTypeInfo *instruction) {
18278static Stage1AirInst *ir_analyze_instruction_type_info(IrAnalyze *ira, Stage1ZirInstTypeInfo *instruction) {
1827918279 Error err;
18280 IrInstGen *type_value = instruction->type_value->child;
18280 Stage1AirInst *type_value = instruction->type_value->child;
1828118281 ZigType *type_entry = ir_resolve_type(ira, type_value);
1828218282 if (type_is_invalid(type_entry))
1828318283 return ira->codegen->invalid_inst_gen;
......@@ -18288,7 +18288,7 @@ static IrInstGen *ir_analyze_instruction_type_info(IrAnalyze *ira, IrInstSrcType
1828818288 if ((err = ir_make_type_info_value(ira, instruction->base.scope, instruction->base.source_node, type_entry, &payload)))
1828918289 return ira->codegen->invalid_inst_gen;
1829018290
18291 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
18291 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
1829218292 ZigValue *out_val = result->value;
1829318293 bigint_init_unsigned(&out_val->data.x_union.tag, type_id_index(type_entry));
1829418294 out_val->data.x_union.payload = payload;
......@@ -18321,8 +18321,8 @@ static Error get_const_field_sentinel(IrAnalyze *ira, Scope *scope, AstNode *sou
1832118321 if (field_val == nullptr)
1832218322 return ErrorSemanticAnalyzeFail;
1832318323
18324 IrInstGen *field_inst = ir_const_move(ira, scope, source_node, field_val);
18325 IrInstGen *casted_field_inst = ir_implicit_cast(ira, field_inst,
18324 Stage1AirInst *field_inst = ir_const_move(ira, scope, source_node, field_val);
18325 Stage1AirInst *casted_field_inst = ir_implicit_cast(ira, field_inst,
1832618326 get_optional_type(ira->codegen, elem_type));
1832718327 if (type_is_invalid(casted_field_inst->value->type))
1832818328 return ErrorSemanticAnalyzeFail;
......@@ -19065,12 +19065,12 @@ static ZigType *type_info_to_type(IrAnalyze *ira, Scope *scope, AstNode *source_
1906519065 zig_unreachable();
1906619066}
1906719067
19068static IrInstGen *ir_analyze_instruction_type(IrAnalyze *ira, IrInstSrcType *instruction) {
19069 IrInstGen *uncasted_type_info = instruction->type_info->child;
19068static Stage1AirInst *ir_analyze_instruction_type(IrAnalyze *ira, Stage1ZirInstType *instruction) {
19069 Stage1AirInst *uncasted_type_info = instruction->type_info->child;
1907019070 if (type_is_invalid(uncasted_type_info->value->type))
1907119071 return ira->codegen->invalid_inst_gen;
1907219072
19073 IrInstGen *type_info = ir_implicit_cast(ira, uncasted_type_info, ir_type_info_get_type(ira, nullptr, nullptr));
19073 Stage1AirInst *type_info = ir_implicit_cast(ira, uncasted_type_info, ir_type_info_get_type(ira, nullptr, nullptr));
1907419074 if (type_is_invalid(type_info->value->type))
1907519075 return ira->codegen->invalid_inst_gen;
1907619076
......@@ -19085,8 +19085,8 @@ static IrInstGen *ir_analyze_instruction_type(IrAnalyze *ira, IrInstSrcType *ins
1908519085 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, type);
1908619086}
1908719087
19088static IrInstGen *ir_analyze_instruction_set_eval_branch_quota(IrAnalyze *ira,
19089 IrInstSrcSetEvalBranchQuota *instruction)
19088static Stage1AirInst *ir_analyze_instruction_set_eval_branch_quota(IrAnalyze *ira,
19089 Stage1ZirInstSetEvalBranchQuota *instruction)
1909019090{
1909119091 uint64_t new_quota;
1909219092 if (!ir_resolve_unsigned(ira, instruction->new_quota->child, ira->codegen->builtin_types.entry_u32, &new_quota))
......@@ -19099,8 +19099,8 @@ static IrInstGen *ir_analyze_instruction_set_eval_branch_quota(IrAnalyze *ira,
1909919099 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
1910019100}
1910119101
19102static IrInstGen *ir_analyze_instruction_type_name(IrAnalyze *ira, IrInstSrcTypeName *instruction) {
19103 IrInstGen *type_value = instruction->type_value->child;
19102static Stage1AirInst *ir_analyze_instruction_type_name(IrAnalyze *ira, Stage1ZirInstTypeName *instruction) {
19103 Stage1AirInst *type_value = instruction->type_value->child;
1910419104 ZigType *type_entry = ir_resolve_type(ira, type_value);
1910519105 if (type_is_invalid(type_entry))
1910619106 return ira->codegen->invalid_inst_gen;
......@@ -19108,12 +19108,12 @@ static IrInstGen *ir_analyze_instruction_type_name(IrAnalyze *ira, IrInstSrcType
1910819108 if (!type_entry->cached_const_name_val) {
1910919109 type_entry->cached_const_name_val = create_const_str_lit(ira->codegen, type_bare_name(type_entry));
1911019110 }
19111 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
19111 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
1911219112 copy_const_val(ira->codegen, result->value, type_entry->cached_const_name_val);
1911319113 return result;
1911419114}
1911519115
19116static IrInstGen *ir_analyze_instruction_c_import(IrAnalyze *ira, IrInstSrcCImport *instruction) {
19116static Stage1AirInst *ir_analyze_instruction_c_import(IrAnalyze *ira, Stage1ZirInstCImport *instruction) {
1911719117 Error err;
1911819118 AstNode *node = instruction->base.source_node;
1911919119 assert(node->type == NodeTypeFnCallExpr);
......@@ -19195,8 +19195,8 @@ static IrInstGen *ir_analyze_instruction_c_import(IrAnalyze *ira, IrInstSrcCImpo
1919519195 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, child_import);
1919619196}
1919719197
19198static IrInstGen *ir_analyze_instruction_c_include(IrAnalyze *ira, IrInstSrcCInclude *instruction) {
19199 IrInstGen *name_value = instruction->name->child;
19198static Stage1AirInst *ir_analyze_instruction_c_include(IrAnalyze *ira, Stage1ZirInstCInclude *instruction) {
19199 Stage1AirInst *name_value = instruction->name->child;
1920019200 if (type_is_invalid(name_value->value->type))
1920119201 return ira->codegen->invalid_inst_gen;
1920219202
......@@ -19213,8 +19213,8 @@ static IrInstGen *ir_analyze_instruction_c_include(IrAnalyze *ira, IrInstSrcCInc
1921319213 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
1921419214}
1921519215
19216static IrInstGen *ir_analyze_instruction_c_define(IrAnalyze *ira, IrInstSrcCDefine *instruction) {
19217 IrInstGen *name = instruction->name->child;
19216static Stage1AirInst *ir_analyze_instruction_c_define(IrAnalyze *ira, Stage1ZirInstCDefine *instruction) {
19217 Stage1AirInst *name = instruction->name->child;
1921819218 if (type_is_invalid(name->value->type))
1921919219 return ira->codegen->invalid_inst_gen;
1922019220
......@@ -19222,7 +19222,7 @@ static IrInstGen *ir_analyze_instruction_c_define(IrAnalyze *ira, IrInstSrcCDefi
1922219222 if (!define_name)
1922319223 return ira->codegen->invalid_inst_gen;
1922419224
19225 IrInstGen *value = instruction->value->child;
19225 Stage1AirInst *value = instruction->value->child;
1922619226 if (type_is_invalid(value->value->type))
1922719227 return ira->codegen->invalid_inst_gen;
1922819228
......@@ -19244,8 +19244,8 @@ static IrInstGen *ir_analyze_instruction_c_define(IrAnalyze *ira, IrInstSrcCDefi
1924419244 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
1924519245}
1924619246
19247static IrInstGen *ir_analyze_instruction_c_undef(IrAnalyze *ira, IrInstSrcCUndef *instruction) {
19248 IrInstGen *name = instruction->name->child;
19247static Stage1AirInst *ir_analyze_instruction_c_undef(IrAnalyze *ira, Stage1ZirInstCUndef *instruction) {
19248 Stage1AirInst *name = instruction->name->child;
1924919249 if (type_is_invalid(name->value->type))
1925019250 return ira->codegen->invalid_inst_gen;
1925119251
......@@ -19262,8 +19262,8 @@ static IrInstGen *ir_analyze_instruction_c_undef(IrAnalyze *ira, IrInstSrcCUndef
1926219262 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
1926319263}
1926419264
19265static IrInstGen *ir_analyze_instruction_embed_file(IrAnalyze *ira, IrInstSrcEmbedFile *instruction) {
19266 IrInstGen *name = instruction->name->child;
19265static Stage1AirInst *ir_analyze_instruction_embed_file(IrAnalyze *ira, Stage1ZirInstEmbedFile *instruction) {
19266 Stage1AirInst *name = instruction->name->child;
1926719267 if (type_is_invalid(name->value->type))
1926819268 return ira->codegen->invalid_inst_gen;
1926919269
......@@ -19298,12 +19298,12 @@ static IrInstGen *ir_analyze_instruction_embed_file(IrAnalyze *ira, IrInstSrcEmb
1929819298 }
1929919299 }
1930019300
19301 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
19301 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr);
1930219302 init_const_str_lit(ira->codegen, result->value, file_contents, true);
1930319303 return result;
1930419304}
1930519305
19306static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxchg *instruction) {
19306static Stage1AirInst *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, Stage1ZirInstCmpxchg *instruction) {
1930719307 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->type_value->child);
1930819308 if (type_is_invalid(operand_type))
1930919309 return ira->codegen->invalid_inst_gen;
......@@ -19314,26 +19314,26 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
1931419314 return ira->codegen->invalid_inst_gen;
1931519315 }
1931619316
19317 IrInstGen *ptr = instruction->ptr->child;
19317 Stage1AirInst *ptr = instruction->ptr->child;
1931819318 if (type_is_invalid(ptr->value->type))
1931919319 return ira->codegen->invalid_inst_gen;
1932019320
1932119321 // TODO let this be volatile
1932219322 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false);
19323 IrInstGen *casted_ptr = ir_implicit_cast2(ira, instruction->ptr->scope,
19323 Stage1AirInst *casted_ptr = ir_implicit_cast2(ira, instruction->ptr->scope,
1932419324 instruction->ptr->source_node, ptr, ptr_type);
1932519325 if (type_is_invalid(casted_ptr->value->type))
1932619326 return ira->codegen->invalid_inst_gen;
1932719327
19328 IrInstGen *cmp_value = instruction->cmp_value->child;
19328 Stage1AirInst *cmp_value = instruction->cmp_value->child;
1932919329 if (type_is_invalid(cmp_value->value->type))
1933019330 return ira->codegen->invalid_inst_gen;
1933119331
19332 IrInstGen *new_value = instruction->new_value->child;
19332 Stage1AirInst *new_value = instruction->new_value->child;
1933319333 if (type_is_invalid(new_value->value->type))
1933419334 return ira->codegen->invalid_inst_gen;
1933519335
19336 IrInstGen *success_order_value = instruction->success_order_value->child;
19336 Stage1AirInst *success_order_value = instruction->success_order_value->child;
1933719337 if (type_is_invalid(success_order_value->value->type))
1933819338 return ira->codegen->invalid_inst_gen;
1933919339
......@@ -19341,7 +19341,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
1934119341 if (!ir_resolve_atomic_order(ira, success_order_value, &success_order))
1934219342 return ira->codegen->invalid_inst_gen;
1934319343
19344 IrInstGen *failure_order_value = instruction->failure_order_value->child;
19344 Stage1AirInst *failure_order_value = instruction->failure_order_value->child;
1934519345 if (type_is_invalid(failure_order_value->value->type))
1934619346 return ira->codegen->invalid_inst_gen;
1934719347
......@@ -19349,12 +19349,12 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
1934919349 if (!ir_resolve_atomic_order(ira, failure_order_value, &failure_order))
1935019350 return ira->codegen->invalid_inst_gen;
1935119351
19352 IrInstGen *casted_cmp_value = ir_implicit_cast2(ira, instruction->cmp_value->scope,
19352 Stage1AirInst *casted_cmp_value = ir_implicit_cast2(ira, instruction->cmp_value->scope,
1935319353 instruction->cmp_value->source_node, cmp_value, operand_type);
1935419354 if (type_is_invalid(casted_cmp_value->value->type))
1935519355 return ira->codegen->invalid_inst_gen;
1935619356
19357 IrInstGen *casted_new_value = ir_implicit_cast2(ira, instruction->new_value->scope,
19357 Stage1AirInst *casted_new_value = ir_implicit_cast2(ira, instruction->new_value->scope,
1935819358 instruction->new_value->source_node, new_value, operand_type);
1935919359 if (type_is_invalid(casted_new_value->value->type))
1936019360 return ira->codegen->invalid_inst_gen;
......@@ -19387,7 +19387,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
1938719387 case OnePossibleValueInvalid:
1938819388 return ira->codegen->invalid_inst_gen;
1938919389 case OnePossibleValueYes: {
19390 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
19390 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
1939119391 set_optional_value_to_null(result->value);
1939219392 return result;
1939319393 }
......@@ -19414,7 +19414,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
1941419414 return ira->codegen->invalid_inst_gen;
1941519415
1941619416 bool eql = const_values_equal(ira->codegen, stored_val, expected_val);
19417 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
19417 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type);
1941819418 if (eql) {
1941919419 copy_const_val(ira->codegen, stored_val, new_val);
1942019420 set_optional_value_to_null(result->value);
......@@ -19424,7 +19424,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
1942419424 return result;
1942519425 }
1942619426
19427 IrInstGen *result_loc;
19427 Stage1AirInst *result_loc;
1942819428 if (handle_is_ptr(ira->codegen, result_type)) {
1942919429 result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
1943019430 result_type, nullptr, true, true);
......@@ -19568,12 +19568,12 @@ static ErrorMsg *ir_eval_reduce(IrAnalyze *ira, Scope *scope, AstNode *source_no
1956819568 return nullptr;
1956919569}
1957019570
19571static IrInstGen *ir_analyze_instruction_reduce(IrAnalyze *ira, IrInstSrcReduce *instruction) {
19572 IrInstGen *op_inst = instruction->op->child;
19571static Stage1AirInst *ir_analyze_instruction_reduce(IrAnalyze *ira, Stage1ZirInstReduce *instruction) {
19572 Stage1AirInst *op_inst = instruction->op->child;
1957319573 if (type_is_invalid(op_inst->value->type))
1957419574 return ira->codegen->invalid_inst_gen;
1957519575
19576 IrInstGen *value_inst = instruction->value->child;
19576 Stage1AirInst *value_inst = instruction->value->child;
1957719577 if (type_is_invalid(value_inst->value->type))
1957819578 return ira->codegen->invalid_inst_gen;
1957919579
......@@ -19624,7 +19624,7 @@ static IrInstGen *ir_analyze_instruction_reduce(IrAnalyze *ira, IrInstSrcReduce
1962419624 }
1962519625
1962619626 if (instr_is_comptime(value_inst)) {
19627 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, elem_type);
19627 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, elem_type);
1962819628 if (ir_eval_reduce(ira, instruction->base.scope, instruction->base.source_node, op, value_inst->value, result->value))
1962919629 return ira->codegen->invalid_inst_gen;
1963019630 return result;
......@@ -19633,8 +19633,8 @@ static IrInstGen *ir_analyze_instruction_reduce(IrAnalyze *ira, IrInstSrcReduce
1963319633 return ir_build_reduce_gen(ira, instruction->base.scope, instruction->base.source_node, op, value_inst, elem_type);
1963419634}
1963519635
19636static IrInstGen *ir_analyze_instruction_fence(IrAnalyze *ira, IrInstSrcFence *instruction) {
19637 IrInstGen *order_inst = instruction->order->child;
19636static Stage1AirInst *ir_analyze_instruction_fence(IrAnalyze *ira, Stage1ZirInstFence *instruction) {
19637 Stage1AirInst *order_inst = instruction->order->child;
1963819638 if (type_is_invalid(order_inst->value->type))
1963919639 return ira->codegen->invalid_inst_gen;
1964019640
......@@ -19651,8 +19651,8 @@ static IrInstGen *ir_analyze_instruction_fence(IrAnalyze *ira, IrInstSrcFence *i
1965119651 return ir_build_fence_gen(ira, instruction->base.scope, instruction->base.source_node, order);
1965219652}
1965319653
19654static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTruncate *instruction) {
19655 IrInstGen *dest_type_value = instruction->dest_type->child;
19654static Stage1AirInst *ir_analyze_instruction_truncate(IrAnalyze *ira, Stage1ZirInstTruncate *instruction) {
19655 Stage1AirInst *dest_type_value = instruction->dest_type->child;
1965619656 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);
1965719657 if (type_is_invalid(dest_type))
1965819658 return ira->codegen->invalid_inst_gen;
......@@ -19664,7 +19664,7 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc
1966419664 return ira->codegen->invalid_inst_gen;
1966519665 }
1966619666
19667 IrInstGen *target = instruction->target->child;
19667 Stage1AirInst *target = instruction->target->child;
1966819668 ZigType *src_type = target->value->type;
1966919669 if (type_is_invalid(src_type))
1967019670 return ira->codegen->invalid_inst_gen;
......@@ -19697,14 +19697,14 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc
1969719697 if (val == nullptr)
1969819698 return ira->codegen->invalid_inst_gen;
1969919699
19700 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type);
19700 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type);
1970119701 bigint_truncate(&result->value->data.x_bigint, &val->data.x_bigint,
1970219702 dest_type->data.integral.bit_count, dest_type->data.integral.is_signed);
1970319703 return result;
1970419704 }
1970519705
1970619706 if (src_type->data.integral.bit_count == 0 || dest_type->data.integral.bit_count == 0) {
19707 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type);
19707 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type);
1970819708 bigint_init_unsigned(&result->value->data.x_bigint, 0);
1970919709 return result;
1971019710 }
......@@ -19712,7 +19712,7 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc
1971219712 return ir_build_truncate_gen(ira, instruction->base.scope, instruction->base.source_node, dest_type, target);
1971319713}
1971419714
19715static IrInstGen *ir_analyze_instruction_int_cast(IrAnalyze *ira, IrInstSrcIntCast *instruction) {
19715static Stage1AirInst *ir_analyze_instruction_int_cast(IrAnalyze *ira, Stage1ZirInstIntCast *instruction) {
1971619716 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);
1971719717 if (type_is_invalid(dest_type))
1971819718 return ira->codegen->invalid_inst_gen;
......@@ -19726,7 +19726,7 @@ static IrInstGen *ir_analyze_instruction_int_cast(IrAnalyze *ira, IrInstSrcIntCa
1972619726 return ira->codegen->invalid_inst_gen;
1972719727 }
1972819728
19729 IrInstGen *target = instruction->target->child;
19729 Stage1AirInst *target = instruction->target->child;
1973019730 if (type_is_invalid(target->value->type))
1973119731 return ira->codegen->invalid_inst_gen;
1973219732
......@@ -19750,7 +19750,7 @@ static IrInstGen *ir_analyze_instruction_int_cast(IrAnalyze *ira, IrInstSrcIntCa
1975019750 return ir_analyze_widen_or_shorten(ira, instruction->base.scope, instruction->base.source_node, target, dest_type);
1975119751}
1975219752
19753static IrInstGen *ir_analyze_instruction_float_cast(IrAnalyze *ira, IrInstSrcFloatCast *instruction) {
19753static Stage1AirInst *ir_analyze_instruction_float_cast(IrAnalyze *ira, Stage1ZirInstFloatCast *instruction) {
1975419754 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);
1975519755 if (type_is_invalid(dest_type))
1975619756 return ira->codegen->invalid_inst_gen;
......@@ -19761,7 +19761,7 @@ static IrInstGen *ir_analyze_instruction_float_cast(IrAnalyze *ira, IrInstSrcFlo
1976119761 return ira->codegen->invalid_inst_gen;
1976219762 }
1976319763
19764 IrInstGen *target = instruction->target->child;
19764 Stage1AirInst *target = instruction->target->child;
1976519765 if (type_is_invalid(target->value->type))
1976619766 return ira->codegen->invalid_inst_gen;
1976719767
......@@ -19800,7 +19800,7 @@ static IrInstGen *ir_analyze_instruction_float_cast(IrAnalyze *ira, IrInstSrcFlo
1980019800 return ir_analyze_widen_or_shorten(ira, instruction->base.scope, instruction->base.source_node, target, dest_type);
1980119801}
1980219802
19803static IrInstGen *ir_analyze_instruction_err_set_cast(IrAnalyze *ira, IrInstSrcErrSetCast *instruction) {
19803static Stage1AirInst *ir_analyze_instruction_err_set_cast(IrAnalyze *ira, Stage1ZirInstErrSetCast *instruction) {
1980419804 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);
1980519805 if (type_is_invalid(dest_type))
1980619806 return ira->codegen->invalid_inst_gen;
......@@ -19811,7 +19811,7 @@ static IrInstGen *ir_analyze_instruction_err_set_cast(IrAnalyze *ira, IrInstSrcE
1981119811 return ira->codegen->invalid_inst_gen;
1981219812 }
1981319813
19814 IrInstGen *target = instruction->target->child;
19814 Stage1AirInst *target = instruction->target->child;
1981519815 if (type_is_invalid(target->value->type))
1981619816 return ira->codegen->invalid_inst_gen;
1981719817
......@@ -19849,7 +19849,7 @@ static Error resolve_ptr_align(IrAnalyze *ira, ZigType *ty, uint32_t *result_ali
1984919849 return ErrorNone;
1985019850}
1985119851
19852static IrInstGen *ir_analyze_instruction_int_to_float(IrAnalyze *ira, IrInstSrcIntToFloat *instruction) {
19852static Stage1AirInst *ir_analyze_instruction_int_to_float(IrAnalyze *ira, Stage1ZirInstIntToFloat *instruction) {
1985319853 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);
1985419854 if (type_is_invalid(dest_type))
1985519855 return ira->codegen->invalid_inst_gen;
......@@ -19860,7 +19860,7 @@ static IrInstGen *ir_analyze_instruction_int_to_float(IrAnalyze *ira, IrInstSrcI
1986019860 return ira->codegen->invalid_inst_gen;
1986119861 }
1986219862
19863 IrInstGen *target = instruction->target->child;
19863 Stage1AirInst *target = instruction->target->child;
1986419864 if (type_is_invalid(target->value->type))
1986519865 return ira->codegen->invalid_inst_gen;
1986619866
......@@ -19873,7 +19873,7 @@ static IrInstGen *ir_analyze_instruction_int_to_float(IrAnalyze *ira, IrInstSrcI
1987319873 return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, dest_type, CastOpIntToFloat);
1987419874}
1987519875
19876static IrInstGen *ir_analyze_instruction_float_to_int(IrAnalyze *ira, IrInstSrcFloatToInt *instruction) {
19876static Stage1AirInst *ir_analyze_instruction_float_to_int(IrAnalyze *ira, Stage1ZirInstFloatToInt *instruction) {
1987719877 ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child);
1987819878 if (type_is_invalid(dest_type))
1987919879 return ira->codegen->invalid_inst_gen;
......@@ -19884,7 +19884,7 @@ static IrInstGen *ir_analyze_instruction_float_to_int(IrAnalyze *ira, IrInstSrcF
1988419884 return ira->codegen->invalid_inst_gen;
1988519885 }
1988619886
19887 IrInstGen *target = instruction->target->child;
19887 Stage1AirInst *target = instruction->target->child;
1988819888 if (type_is_invalid(target->value->type))
1988919889 return ira->codegen->invalid_inst_gen;
1989019890
......@@ -19901,12 +19901,12 @@ static IrInstGen *ir_analyze_instruction_float_to_int(IrAnalyze *ira, IrInstSrcF
1990119901 return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, dest_type, CastOpFloatToInt);
1990219902}
1990319903
19904static IrInstGen *ir_analyze_instruction_err_to_int(IrAnalyze *ira, IrInstSrcErrToInt *instruction) {
19905 IrInstGen *target = instruction->target->child;
19904static Stage1AirInst *ir_analyze_instruction_err_to_int(IrAnalyze *ira, Stage1ZirInstErrToInt *instruction) {
19905 Stage1AirInst *target = instruction->target->child;
1990619906 if (type_is_invalid(target->value->type))
1990719907 return ira->codegen->invalid_inst_gen;
1990819908
19909 IrInstGen *casted_target;
19909 Stage1AirInst *casted_target;
1991019910 if (target->value->type->id == ZigTypeIdErrorSet) {
1991119911 casted_target = target;
1991219912 } else {
......@@ -19918,20 +19918,20 @@ static IrInstGen *ir_analyze_instruction_err_to_int(IrAnalyze *ira, IrInstSrcErr
1991819918 return ir_analyze_err_to_int(ira, instruction->base.scope, instruction->base.source_node, casted_target, ira->codegen->err_tag_type);
1991919919}
1992019920
19921static IrInstGen *ir_analyze_instruction_int_to_err(IrAnalyze *ira, IrInstSrcIntToErr *instruction) {
19922 IrInstGen *target = instruction->target->child;
19921static Stage1AirInst *ir_analyze_instruction_int_to_err(IrAnalyze *ira, Stage1ZirInstIntToErr *instruction) {
19922 Stage1AirInst *target = instruction->target->child;
1992319923 if (type_is_invalid(target->value->type))
1992419924 return ira->codegen->invalid_inst_gen;
1992519925
19926 IrInstGen *casted_target = ir_implicit_cast(ira, target, ira->codegen->err_tag_type);
19926 Stage1AirInst *casted_target = ir_implicit_cast(ira, target, ira->codegen->err_tag_type);
1992719927 if (type_is_invalid(casted_target->value->type))
1992819928 return ira->codegen->invalid_inst_gen;
1992919929
1993019930 return ir_analyze_int_to_err(ira, instruction->base.scope, instruction->base.source_node, casted_target, ira->codegen->builtin_types.entry_global_error_set);
1993119931}
1993219932
19933static IrInstGen *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, IrInstSrcBoolToInt *instruction) {
19934 IrInstGen *target = instruction->target->child;
19933static Stage1AirInst *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, Stage1ZirInstBoolToInt *instruction) {
19934 Stage1AirInst *target = instruction->target->child;
1993519935 if (type_is_invalid(target->value->type))
1993619936 return ira->codegen->invalid_inst_gen;
1993719937
......@@ -19953,7 +19953,7 @@ static IrInstGen *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, IrInstSrcBo
1995319953 return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, u1_type, CastOpBoolToInt);
1995419954}
1995519955
19956static IrInstGen *ir_analyze_instruction_vector_type(IrAnalyze *ira, IrInstSrcVectorType *instruction) {
19956static Stage1AirInst *ir_analyze_instruction_vector_type(IrAnalyze *ira, Stage1ZirInstVectorType *instruction) {
1995719957 uint64_t len;
1995819958 if (!ir_resolve_unsigned(ira, instruction->len->child, ira->codegen->builtin_types.entry_u32, &len))
1995919959 return ira->codegen->invalid_inst_gen;
......@@ -19967,8 +19967,8 @@ static IrInstGen *ir_analyze_instruction_vector_type(IrAnalyze *ira, IrInstSrcVe
1996719967 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, vector_type);
1996819968}
1996919969
19970static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,
19971 ZigType *scalar_type, IrInstGen *a, IrInstGen *b, IrInstGen *mask)
19970static Stage1AirInst *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node,
19971 ZigType *scalar_type, Stage1AirInst *a, Stage1AirInst *b, Stage1AirInst *mask)
1997219972{
1997319973 Error err;
1997419974 src_assert(source_node && scalar_type && a && b && mask, source_node);
......@@ -20056,7 +20056,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod
2005620056 continue;
2005720057 int32_t v_i32 = bigint_as_signed(&mask_elem_val->data.x_bigint);
2005820058 uint32_t v;
20059 IrInstGen *chosen_operand;
20059 Stage1AirInst *chosen_operand;
2006020060 if (v_i32 >= 0) {
2006120061 v = (uint32_t)v_i32;
2006220062 chosen_operand = a;
......@@ -20091,7 +20091,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod
2009120091 expand_undef_array(ira->codegen, a_val);
2009220092 expand_undef_array(ira->codegen, b_val);
2009320093
20094 IrInstGen *result = ir_const(ira, scope, source_node, result_type);
20094 Stage1AirInst *result = ir_const(ira, scope, source_node, result_type);
2009520095 result->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate<ZigValue>(len_mask);
2009620096 for (uint32_t i = 0; i < mask_val->type->data.vector.len; i += 1) {
2009720097 ZigValue *mask_elem_val = &mask_val->data.x_array.data.s_none.elements[i];
......@@ -20123,7 +20123,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod
2012320123 uint32_t len_min = min(len_a, len_b);
2012420124 uint32_t len_max = max(len_a, len_b);
2012520125
20126 IrInstGen *expand_mask = ir_const(ira, mask->scope, mask->source_node,
20126 Stage1AirInst *expand_mask = ir_const(ira, mask->scope, mask->source_node,
2012720127 get_vector_type(ira->codegen, len_max, ira->codegen->builtin_types.entry_i32));
2012820128 expand_mask->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate<ZigValue>(len_max);
2012920129 uint32_t i = 0;
......@@ -20132,7 +20132,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod
2013220132 for (; i < len_max; i += 1)
2013320133 bigint_init_signed(&expand_mask->value->data.x_array.data.s_none.elements[i].data.x_bigint, -1);
2013420134
20135 IrInstGen *undef = ir_const_undef(ira, scope, source_node,
20135 Stage1AirInst *undef = ir_const_undef(ira, scope, source_node,
2013620136 get_vector_type(ira->codegen, len_min, scalar_type));
2013720137
2013820138 if (len_b < len_a) {
......@@ -20146,34 +20146,34 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod
2014620146 result_type, a, b, mask);
2014720147}
2014820148
20149static IrInstGen *ir_analyze_instruction_shuffle_vector(IrAnalyze *ira, IrInstSrcShuffleVector *instruction) {
20149static Stage1AirInst *ir_analyze_instruction_shuffle_vector(IrAnalyze *ira, Stage1ZirInstShuffleVector *instruction) {
2015020150 ZigType *scalar_type = ir_resolve_vector_elem_type(ira, instruction->scalar_type->child);
2015120151 if (type_is_invalid(scalar_type))
2015220152 return ira->codegen->invalid_inst_gen;
2015320153
20154 IrInstGen *a = instruction->a->child;
20154 Stage1AirInst *a = instruction->a->child;
2015520155 if (type_is_invalid(a->value->type))
2015620156 return ira->codegen->invalid_inst_gen;
2015720157
20158 IrInstGen *b = instruction->b->child;
20158 Stage1AirInst *b = instruction->b->child;
2015920159 if (type_is_invalid(b->value->type))
2016020160 return ira->codegen->invalid_inst_gen;
2016120161
20162 IrInstGen *mask = instruction->mask->child;
20162 Stage1AirInst *mask = instruction->mask->child;
2016320163 if (type_is_invalid(mask->value->type))
2016420164 return ira->codegen->invalid_inst_gen;
2016520165
2016620166 return ir_analyze_shuffle_vector(ira, instruction->base.scope, instruction->base.source_node, scalar_type, a, b, mask);
2016720167}
2016820168
20169static IrInstGen *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstSrcSplat *instruction) {
20169static Stage1AirInst *ir_analyze_instruction_splat(IrAnalyze *ira, Stage1ZirInstSplat *instruction) {
2017020170 Error err;
2017120171
20172 IrInstGen *len = instruction->len->child;
20172 Stage1AirInst *len = instruction->len->child;
2017320173 if (type_is_invalid(len->value->type))
2017420174 return ira->codegen->invalid_inst_gen;
2017520175
20176 IrInstGen *scalar = instruction->scalar->child;
20176 Stage1AirInst *scalar = instruction->scalar->child;
2017720177 if (type_is_invalid(scalar->value->type))
2017820178 return ira->codegen->invalid_inst_gen;
2017920179
......@@ -20194,7 +20194,7 @@ static IrInstGen *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstSrcSplat *i
2019420194 if (scalar_val->special == ConstValSpecialUndef)
2019520195 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, return_type);
2019620196
20197 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);
20197 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);
2019820198 result->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate<ZigValue>(len_int);
2019920199 for (uint32_t i = 0; i < len_int; i += 1) {
2020020200 copy_const_val(ira->codegen, &result->value->data.x_array.data.s_none.elements[i], scalar_val);
......@@ -20205,14 +20205,14 @@ static IrInstGen *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstSrcSplat *i
2020520205 return ir_build_splat_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, scalar);
2020620206}
2020720207
20208static IrInstGen *ir_analyze_instruction_bool_not(IrAnalyze *ira, IrInstSrcBoolNot *instruction) {
20209 IrInstGen *value = instruction->value->child;
20208static Stage1AirInst *ir_analyze_instruction_bool_not(IrAnalyze *ira, Stage1ZirInstBoolNot *instruction) {
20209 Stage1AirInst *value = instruction->value->child;
2021020210 if (type_is_invalid(value->value->type))
2021120211 return ira->codegen->invalid_inst_gen;
2021220212
2021320213 ZigType *bool_type = ira->codegen->builtin_types.entry_bool;
2021420214
20215 IrInstGen *casted_value = ir_implicit_cast(ira, value, bool_type);
20215 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, bool_type);
2021620216 if (type_is_invalid(casted_value->value->type))
2021720217 return ira->codegen->invalid_inst_gen;
2021820218
......@@ -20227,18 +20227,18 @@ static IrInstGen *ir_analyze_instruction_bool_not(IrAnalyze *ira, IrInstSrcBoolN
2022720227 return ir_build_bool_not_gen(ira, instruction->base.scope, instruction->base.source_node, casted_value);
2022820228}
2022920229
20230static IrInstGen *ir_analyze_instruction_memset(IrAnalyze *ira, IrInstSrcMemset *instruction) {
20230static Stage1AirInst *ir_analyze_instruction_memset(IrAnalyze *ira, Stage1ZirInstMemset *instruction) {
2023120231 Error err;
2023220232
20233 IrInstGen *dest_ptr = instruction->dest_ptr->child;
20233 Stage1AirInst *dest_ptr = instruction->dest_ptr->child;
2023420234 if (type_is_invalid(dest_ptr->value->type))
2023520235 return ira->codegen->invalid_inst_gen;
2023620236
20237 IrInstGen *byte_value = instruction->byte->child;
20237 Stage1AirInst *byte_value = instruction->byte->child;
2023820238 if (type_is_invalid(byte_value->value->type))
2023920239 return ira->codegen->invalid_inst_gen;
2024020240
20241 IrInstGen *count_value = instruction->count->child;
20241 Stage1AirInst *count_value = instruction->count->child;
2024220242 if (type_is_invalid(count_value->value->type))
2024320243 return ira->codegen->invalid_inst_gen;
2024420244
......@@ -20258,15 +20258,15 @@ static IrInstGen *ir_analyze_instruction_memset(IrAnalyze *ira, IrInstSrcMemset
2025820258 ZigType *u8_ptr = get_pointer_to_type_extra(ira->codegen, u8, false, dest_is_volatile,
2025920259 PtrLenUnknown, dest_align, 0, 0, false);
2026020260
20261 IrInstGen *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr);
20261 Stage1AirInst *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr);
2026220262 if (type_is_invalid(casted_dest_ptr->value->type))
2026320263 return ira->codegen->invalid_inst_gen;
2026420264
20265 IrInstGen *casted_byte = ir_implicit_cast(ira, byte_value, u8);
20265 Stage1AirInst *casted_byte = ir_implicit_cast(ira, byte_value, u8);
2026620266 if (type_is_invalid(casted_byte->value->type))
2026720267 return ira->codegen->invalid_inst_gen;
2026820268
20269 IrInstGen *casted_count = ir_implicit_cast(ira, count_value, usize);
20269 Stage1AirInst *casted_count = ir_implicit_cast(ira, count_value, usize);
2027020270 if (type_is_invalid(casted_count->value->type))
2027120271 return ira->codegen->invalid_inst_gen;
2027220272
......@@ -20346,18 +20346,18 @@ static IrInstGen *ir_analyze_instruction_memset(IrAnalyze *ira, IrInstSrcMemset
2034620346 return ir_build_memset_gen(ira, instruction->base.scope, instruction->base.source_node, casted_dest_ptr, casted_byte, casted_count);
2034720347}
2034820348
20349static IrInstGen *ir_analyze_instruction_memcpy(IrAnalyze *ira, IrInstSrcMemcpy *instruction) {
20349static Stage1AirInst *ir_analyze_instruction_memcpy(IrAnalyze *ira, Stage1ZirInstMemcpy *instruction) {
2035020350 Error err;
2035120351
20352 IrInstGen *dest_ptr = instruction->dest_ptr->child;
20352 Stage1AirInst *dest_ptr = instruction->dest_ptr->child;
2035320353 if (type_is_invalid(dest_ptr->value->type))
2035420354 return ira->codegen->invalid_inst_gen;
2035520355
20356 IrInstGen *src_ptr = instruction->src_ptr->child;
20356 Stage1AirInst *src_ptr = instruction->src_ptr->child;
2035720357 if (type_is_invalid(src_ptr->value->type))
2035820358 return ira->codegen->invalid_inst_gen;
2035920359
20360 IrInstGen *count_value = instruction->count->child;
20360 Stage1AirInst *count_value = instruction->count->child;
2036120361 if (type_is_invalid(count_value->value->type))
2036220362 return ira->codegen->invalid_inst_gen;
2036320363
......@@ -20391,15 +20391,15 @@ static IrInstGen *ir_analyze_instruction_memcpy(IrAnalyze *ira, IrInstSrcMemcpy
2039120391 ZigType *u8_ptr_const = get_pointer_to_type_extra(ira->codegen, u8, true, src_is_volatile,
2039220392 PtrLenUnknown, src_align, 0, 0, false);
2039320393
20394 IrInstGen *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr_mut);
20394 Stage1AirInst *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr_mut);
2039520395 if (type_is_invalid(casted_dest_ptr->value->type))
2039620396 return ira->codegen->invalid_inst_gen;
2039720397
20398 IrInstGen *casted_src_ptr = ir_implicit_cast(ira, src_ptr, u8_ptr_const);
20398 Stage1AirInst *casted_src_ptr = ir_implicit_cast(ira, src_ptr, u8_ptr_const);
2039920399 if (type_is_invalid(casted_src_ptr->value->type))
2040020400 return ira->codegen->invalid_inst_gen;
2040120401
20402 IrInstGen *casted_count = ir_implicit_cast(ira, count_value, usize);
20402 Stage1AirInst *casted_count = ir_implicit_cast(ira, count_value, usize);
2040320403 if (type_is_invalid(casted_count->value->type))
2040420404 return ira->codegen->invalid_inst_gen;
2040520405
......@@ -20534,10 +20534,10 @@ static ZigType *get_result_loc_type(IrAnalyze *ira, ResultLoc *result_loc) {
2053420534 return nullptr;
2053520535}
2053620536
20537static IrInstGen *ir_analyze_instruction_slice(IrAnalyze *ira, IrInstSrcSlice *instruction) {
20537static Stage1AirInst *ir_analyze_instruction_slice(IrAnalyze *ira, Stage1ZirInstSlice *instruction) {
2053820538 Error err;
2053920539
20540 IrInstGen *ptr_ptr = instruction->ptr->child;
20540 Stage1AirInst *ptr_ptr = instruction->ptr->child;
2054120541 if (type_is_invalid(ptr_ptr->value->type))
2054220542 return ira->codegen->invalid_inst_gen;
2054320543
......@@ -20545,16 +20545,16 @@ static IrInstGen *ir_analyze_instruction_slice(IrAnalyze *ira, IrInstSrcSlice *i
2054520545 assert(ptr_ptr_type->id == ZigTypeIdPointer);
2054620546 ZigType *array_type = ptr_ptr_type->data.pointer.child_type;
2054720547
20548 IrInstGen *start = instruction->start->child;
20548 Stage1AirInst *start = instruction->start->child;
2054920549 if (type_is_invalid(start->value->type))
2055020550 return ira->codegen->invalid_inst_gen;
2055120551
2055220552 ZigType *usize = ira->codegen->builtin_types.entry_usize;
20553 IrInstGen *casted_start = ir_implicit_cast(ira, start, usize);
20553 Stage1AirInst *casted_start = ir_implicit_cast(ira, start, usize);
2055420554 if (type_is_invalid(casted_start->value->type))
2055520555 return ira->codegen->invalid_inst_gen;
2055620556
20557 IrInstGen *end;
20557 Stage1AirInst *end;
2055820558 if (instruction->end) {
2055920559 end = instruction->end->child;
2056020560 if (type_is_invalid(end->value->type))
......@@ -20626,10 +20626,10 @@ static IrInstGen *ir_analyze_instruction_slice(IrAnalyze *ira, IrInstSrcSlice *i
2062620626
2062720627 ZigValue *sentinel_val = nullptr;
2062820628 if (instruction->sentinel) {
20629 IrInstGen *uncasted_sentinel = instruction->sentinel->child;
20629 Stage1AirInst *uncasted_sentinel = instruction->sentinel->child;
2063020630 if (type_is_invalid(uncasted_sentinel->value->type))
2063120631 return ira->codegen->invalid_inst_gen;
20632 IrInstGen *sentinel = ir_implicit_cast(ira, uncasted_sentinel, elem_type);
20632 Stage1AirInst *sentinel = ir_implicit_cast(ira, uncasted_sentinel, elem_type);
2063320633 if (type_is_invalid(sentinel->value->type))
2063420634 return ira->codegen->invalid_inst_gen;
2063520635 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);
......@@ -20990,7 +20990,7 @@ done_with_return_type:
2099020990 }
2099120991 exit_check_sentinel:
2099220992
20993 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);
20993 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);
2099420994
2099520995 ZigValue *ptr_val;
2099620996 if (return_type->id == ZigTypeIdPointer) {
......@@ -21061,7 +21061,7 @@ done_with_return_type:
2106121061 }
2106221062
2106321063 if (generate_non_null_assert) {
21064 IrInstGen *ptr_val = ir_get_deref(ira, instruction->base.scope,
21064 Stage1AirInst *ptr_val = ir_get_deref(ira, instruction->base.scope,
2106521065 instruction->base.source_node, ptr_ptr, nullptr);
2106621066
2106721067 if (type_is_invalid(ptr_val->value->type))
......@@ -21070,7 +21070,7 @@ done_with_return_type:
2107021070 ir_build_assert_non_null(ira, instruction->base.scope, instruction->base.source_node, ptr_val);
2107121071 }
2107221072
21073 IrInstGen *result_loc = nullptr;
21073 Stage1AirInst *result_loc = nullptr;
2107421074
2107521075 if (return_type->id != ZigTypeIdPointer) {
2107621076 result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
......@@ -21086,9 +21086,9 @@ done_with_return_type:
2108621086 return ira->codegen->invalid_inst_gen;
2108721087 }
2108821088
21089 IrInstGen *dummy_value = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);
21089 Stage1AirInst *dummy_value = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type);
2109021090 dummy_value->value->special = ConstValSpecialRuntime;
21091 IrInstGen *dummy_result = ir_implicit_cast2(ira,
21091 Stage1AirInst *dummy_result = ir_implicit_cast2(ira,
2109221092 instruction->base.scope, instruction->base.source_node,
2109321093 dummy_value, result_loc->value->type->data.pointer.child_type);
2109421094 if (type_is_invalid(dummy_result->value->type))
......@@ -21100,7 +21100,7 @@ done_with_return_type:
2110021100 casted_start, end, instruction->safety_check_on, result_loc, sentinel_val);
2110121101}
2110221102
21103static IrInstGen *ir_analyze_instruction_has_field(IrAnalyze *ira, IrInstSrcHasField *instruction) {
21103static Stage1AirInst *ir_analyze_instruction_has_field(IrAnalyze *ira, Stage1ZirInstHasField *instruction) {
2110421104 Error err;
2110521105 ZigType *container_type = ir_resolve_type(ira, instruction->container_type->child);
2110621106 if (type_is_invalid(container_type))
......@@ -21128,7 +21128,7 @@ static IrInstGen *ir_analyze_instruction_has_field(IrAnalyze *ira, IrInstSrcHasF
2112821128 return ir_const_bool(ira, instruction->base.scope, instruction->base.source_node, result);
2112921129}
2113021130
21131static IrInstGen *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, IrInstSrcWasmMemorySize *instruction) {
21131static Stage1AirInst *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, Stage1ZirInstWasmMemorySize *instruction) {
2113221132 // TODO generate compile error for target_arch different than 32bit
2113321133 if (!target_is_wasm(ira->codegen->zig_target)) {
2113421134 ir_add_error_node(ira, instruction->base.source_node,
......@@ -21136,20 +21136,20 @@ static IrInstGen *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, IrInst
2113621136 return ira->codegen->invalid_inst_gen;
2113721137 }
2113821138
21139 IrInstGen *index = instruction->index->child;
21139 Stage1AirInst *index = instruction->index->child;
2114021140 if (type_is_invalid(index->value->type))
2114121141 return ira->codegen->invalid_inst_gen;
2114221142
2114321143 ZigType *u32 = ira->codegen->builtin_types.entry_u32;
2114421144
21145 IrInstGen *casted_index = ir_implicit_cast(ira, index, u32);
21145 Stage1AirInst *casted_index = ir_implicit_cast(ira, index, u32);
2114621146 if (type_is_invalid(casted_index->value->type))
2114721147 return ira->codegen->invalid_inst_gen;
2114821148
2114921149 return ir_build_wasm_memory_size_gen(ira, instruction->base.scope, instruction->base.source_node, casted_index);
2115021150}
2115121151
21152static IrInstGen *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, IrInstSrcWasmMemoryGrow *instruction) {
21152static Stage1AirInst *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, Stage1ZirInstWasmMemoryGrow *instruction) {
2115321153 // TODO generate compile error for target_arch different than 32bit
2115421154 if (!target_is_wasm(ira->codegen->zig_target)) {
2115521155 ir_add_error_node(ira, instruction->base.source_node,
......@@ -21157,40 +21157,40 @@ static IrInstGen *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, IrInst
2115721157 return ira->codegen->invalid_inst_gen;
2115821158 }
2115921159
21160 IrInstGen *index = instruction->index->child;
21160 Stage1AirInst *index = instruction->index->child;
2116121161 if (type_is_invalid(index->value->type))
2116221162 return ira->codegen->invalid_inst_gen;
2116321163
2116421164 ZigType *u32 = ira->codegen->builtin_types.entry_u32;
2116521165
21166 IrInstGen *casted_index = ir_implicit_cast(ira, index, u32);
21166 Stage1AirInst *casted_index = ir_implicit_cast(ira, index, u32);
2116721167 if (type_is_invalid(casted_index->value->type))
2116821168 return ira->codegen->invalid_inst_gen;
2116921169
21170 IrInstGen *delta = instruction->delta->child;
21170 Stage1AirInst *delta = instruction->delta->child;
2117121171 if (type_is_invalid(delta->value->type))
2117221172 return ira->codegen->invalid_inst_gen;
2117321173
21174 IrInstGen *casted_delta = ir_implicit_cast(ira, delta, u32);
21174 Stage1AirInst *casted_delta = ir_implicit_cast(ira, delta, u32);
2117521175 if (type_is_invalid(casted_delta->value->type))
2117621176 return ira->codegen->invalid_inst_gen;
2117721177
2117821178 return ir_build_wasm_memory_grow_gen(ira, instruction->base.scope, instruction->base.source_node, casted_index, casted_delta);
2117921179}
2118021180
21181static IrInstGen *ir_analyze_instruction_breakpoint(IrAnalyze *ira, IrInstSrcBreakpoint *instruction) {
21181static Stage1AirInst *ir_analyze_instruction_breakpoint(IrAnalyze *ira, Stage1ZirInstBreakpoint *instruction) {
2118221182 return ir_build_breakpoint_gen(ira, instruction->base.scope, instruction->base.source_node);
2118321183}
2118421184
21185static IrInstGen *ir_analyze_instruction_return_address(IrAnalyze *ira, IrInstSrcReturnAddress *instruction) {
21185static Stage1AirInst *ir_analyze_instruction_return_address(IrAnalyze *ira, Stage1ZirInstReturnAddress *instruction) {
2118621186 return ir_build_return_address_gen(ira, instruction->base.scope, instruction->base.source_node);
2118721187}
2118821188
21189static IrInstGen *ir_analyze_instruction_frame_address(IrAnalyze *ira, IrInstSrcFrameAddress *instruction) {
21189static Stage1AirInst *ir_analyze_instruction_frame_address(IrAnalyze *ira, Stage1ZirInstFrameAddress *instruction) {
2119021190 return ir_build_frame_address_gen(ira, instruction->base.scope, instruction->base.source_node);
2119121191}
2119221192
21193static IrInstGen *ir_analyze_instruction_frame_handle(IrAnalyze *ira, IrInstSrcFrameHandle *instruction) {
21193static Stage1AirInst *ir_analyze_instruction_frame_handle(IrAnalyze *ira, Stage1ZirInstFrameHandle *instruction) {
2119421194 ZigFn *fn = ira->fn;
2119521195 src_assert(fn != nullptr, instruction->base.source_node);
2119621196
......@@ -21204,7 +21204,7 @@ static IrInstGen *ir_analyze_instruction_frame_handle(IrAnalyze *ira, IrInstSrcF
2120421204 return ir_build_handle_gen(ira, instruction->base.scope, instruction->base.source_node, ptr_frame_type);
2120521205}
2120621206
21207static IrInstGen *ir_analyze_instruction_frame_type(IrAnalyze *ira, IrInstSrcFrameType *instruction) {
21207static Stage1AirInst *ir_analyze_instruction_frame_type(IrAnalyze *ira, Stage1ZirInstFrameType *instruction) {
2120821208 ZigFn *fn = ir_resolve_fn(ira, instruction->fn->child);
2120921209 if (fn == nullptr)
2121021210 return ira->codegen->invalid_inst_gen;
......@@ -21219,8 +21219,8 @@ static IrInstGen *ir_analyze_instruction_frame_type(IrAnalyze *ira, IrInstSrcFra
2121921219 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, ty);
2122021220}
2122121221
21222static IrInstGen *ir_analyze_instruction_frame_size(IrAnalyze *ira, IrInstSrcFrameSize *instruction) {
21223 IrInstGen *fn = instruction->fn->child;
21222static Stage1AirInst *ir_analyze_instruction_frame_size(IrAnalyze *ira, Stage1ZirInstFrameSize *instruction) {
21223 Stage1AirInst *fn = instruction->fn->child;
2122421224 if (type_is_invalid(fn->value->type))
2122521225 return ira->codegen->invalid_inst_gen;
2122621226
......@@ -21235,13 +21235,13 @@ static IrInstGen *ir_analyze_instruction_frame_size(IrAnalyze *ira, IrInstSrcFra
2123521235 return ir_build_frame_size_gen(ira, instruction->base.scope, instruction->base.source_node, fn);
2123621236}
2123721237
21238static IrInstGen *ir_analyze_instruction_align_of(IrAnalyze *ira, IrInstSrcAlignOf *instruction) {
21238static Stage1AirInst *ir_analyze_instruction_align_of(IrAnalyze *ira, Stage1ZirInstAlignOf *instruction) {
2123921239 // Here we create a lazy value in order to avoid resolving the alignment of the type
2124021240 // immediately. This avoids false positive dependency loops such as:
2124121241 // const Node = struct {
2124221242 // field: []align(@alignOf(Node)) Node,
2124321243 // };
21244 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int);
21244 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int);
2124521245 result->value->special = ConstValSpecialLazy;
2124621246
2124721247 LazyValueAlignOf *lazy_align_of = heap::c_allocator.create<LazyValueAlignOf>();
......@@ -21256,10 +21256,10 @@ static IrInstGen *ir_analyze_instruction_align_of(IrAnalyze *ira, IrInstSrcAlign
2125621256 return result;
2125721257}
2125821258
21259static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOverflowOp *instruction) {
21259static Stage1AirInst *ir_analyze_instruction_overflow_op(IrAnalyze *ira, Stage1ZirInstOverflowOp *instruction) {
2126021260 Error err;
2126121261
21262 IrInstGen *type_value = instruction->type_value->child;
21262 Stage1AirInst *type_value = instruction->type_value->child;
2126321263 if (type_is_invalid(type_value->value->type))
2126421264 return ira->codegen->invalid_inst_gen;
2126521265
......@@ -21273,19 +21273,19 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv
2127321273 return ira->codegen->invalid_inst_gen;
2127421274 }
2127521275
21276 IrInstGen *op1 = instruction->op1->child;
21276 Stage1AirInst *op1 = instruction->op1->child;
2127721277 if (type_is_invalid(op1->value->type))
2127821278 return ira->codegen->invalid_inst_gen;
2127921279
21280 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, dest_type);
21280 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, dest_type);
2128121281 if (type_is_invalid(casted_op1->value->type))
2128221282 return ira->codegen->invalid_inst_gen;
2128321283
21284 IrInstGen *op2 = instruction->op2->child;
21284 Stage1AirInst *op2 = instruction->op2->child;
2128521285 if (type_is_invalid(op2->value->type))
2128621286 return ira->codegen->invalid_inst_gen;
2128721287
21288 IrInstGen *casted_op2;
21288 Stage1AirInst *casted_op2;
2128921289 if (instruction->op == IrOverflowOpShl) {
2129021290 ZigType *shift_amt_type = get_smallest_unsigned_int_type(ira->codegen,
2129121291 dest_type->data.integral.bit_count - 1);
......@@ -21296,7 +21296,7 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv
2129621296 if (type_is_invalid(casted_op2->value->type))
2129721297 return ira->codegen->invalid_inst_gen;
2129821298
21299 IrInstGen *result_ptr = instruction->result_ptr->child;
21299 Stage1AirInst *result_ptr = instruction->result_ptr->child;
2130021300 if (type_is_invalid(result_ptr->value->type))
2130121301 return ira->codegen->invalid_inst_gen;
2130221302
......@@ -21313,7 +21313,7 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv
2131321313 expected_ptr_type = get_pointer_to_type(ira->codegen, dest_type, false);
2131421314 }
2131521315
21316 IrInstGen *casted_result_ptr = ir_implicit_cast(ira, result_ptr, expected_ptr_type);
21316 Stage1AirInst *casted_result_ptr = ir_implicit_cast(ira, result_ptr, expected_ptr_type);
2131721317 if (type_is_invalid(casted_result_ptr->value->type))
2131821318 return ira->codegen->invalid_inst_gen;
2131921319
......@@ -21403,8 +21403,8 @@ static void ir_eval_mul_add(IrAnalyze *ira, ZigType *float_type,
2140321403 }
2140421404}
2140521405
21406static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd *instruction) {
21407 IrInstGen *type_value = instruction->type_value->child;
21406static Stage1AirInst *ir_analyze_instruction_mul_add(IrAnalyze *ira, Stage1ZirInstMulAdd *instruction) {
21407 Stage1AirInst *type_value = instruction->type_value->child;
2140821408 if (type_is_invalid(type_value->value->type))
2140921409 return ira->codegen->invalid_inst_gen;
2141021410
......@@ -21420,27 +21420,27 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd
2142021420 return ira->codegen->invalid_inst_gen;
2142121421 }
2142221422
21423 IrInstGen *op1 = instruction->op1->child;
21423 Stage1AirInst *op1 = instruction->op1->child;
2142421424 if (type_is_invalid(op1->value->type))
2142521425 return ira->codegen->invalid_inst_gen;
2142621426
21427 IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, expr_type);
21427 Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, expr_type);
2142821428 if (type_is_invalid(casted_op1->value->type))
2142921429 return ira->codegen->invalid_inst_gen;
2143021430
21431 IrInstGen *op2 = instruction->op2->child;
21431 Stage1AirInst *op2 = instruction->op2->child;
2143221432 if (type_is_invalid(op2->value->type))
2143321433 return ira->codegen->invalid_inst_gen;
2143421434
21435 IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, expr_type);
21435 Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, expr_type);
2143621436 if (type_is_invalid(casted_op2->value->type))
2143721437 return ira->codegen->invalid_inst_gen;
2143821438
21439 IrInstGen *op3 = instruction->op3->child;
21439 Stage1AirInst *op3 = instruction->op3->child;
2144021440 if (type_is_invalid(op3->value->type))
2144121441 return ira->codegen->invalid_inst_gen;
2144221442
21443 IrInstGen *casted_op3 = ir_implicit_cast(ira, op3, expr_type);
21443 Stage1AirInst *casted_op3 = ir_implicit_cast(ira, op3, expr_type);
2144421444 if (type_is_invalid(casted_op3->value->type))
2144521445 return ira->codegen->invalid_inst_gen;
2144621446
......@@ -21457,7 +21457,7 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd
2145721457 if (!op3_const)
2145821458 return ira->codegen->invalid_inst_gen;
2145921459
21460 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);
21460 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type);
2146121461 ZigValue *out_val = result->value;
2146221462
2146321463 if (expr_type->id == ZigTypeIdVector) {
......@@ -21491,12 +21491,12 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd
2149121491 return ir_build_mul_add_gen(ira, instruction->base.scope, instruction->base.source_node, casted_op1, casted_op2, casted_op3, expr_type);
2149221492}
2149321493
21494static IrInstGen *ir_analyze_instruction_test_err(IrAnalyze *ira, IrInstSrcTestErr *instruction) {
21495 IrInstGen *base_ptr = instruction->base_ptr->child;
21494static Stage1AirInst *ir_analyze_instruction_test_err(IrAnalyze *ira, Stage1ZirInstTestErr *instruction) {
21495 Stage1AirInst *base_ptr = instruction->base_ptr->child;
2149621496 if (type_is_invalid(base_ptr->value->type))
2149721497 return ira->codegen->invalid_inst_gen;
2149821498
21499 IrInstGen *value;
21499 Stage1AirInst *value;
2150021500 if (instruction->base_ptr_is_payload) {
2150121501 value = base_ptr;
2150221502 } else {
......@@ -21540,8 +21540,8 @@ static IrInstGen *ir_analyze_instruction_test_err(IrAnalyze *ira, IrInstSrcTestE
2154021540 }
2154121541}
2154221542
21543static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,
21544 IrInstGen *base_ptr, bool initializing)
21543static Stage1AirInst *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node,
21544 Stage1AirInst *base_ptr, bool initializing)
2154521545{
2154621546 ZigType *ptr_type = base_ptr->value->type;
2154721547
......@@ -21595,7 +21595,7 @@ static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNo
2159521595 }
2159621596 src_assert(err_union_val->special != ConstValSpecialRuntime, source_node);
2159721597
21598 IrInstGen *result;
21598 Stage1AirInst *result;
2159921599 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
2160021600 result = ir_build_unwrap_err_code_gen(ira, scope,
2160121601 source_node, base_ptr, result_type);
......@@ -21614,15 +21614,15 @@ static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNo
2161421614 return ir_build_unwrap_err_code_gen(ira, scope, source_node, base_ptr, result_type);
2161521615}
2161621616
21617static IrInstGen *ir_analyze_instruction_unwrap_err_code(IrAnalyze *ira, IrInstSrcUnwrapErrCode *instruction) {
21618 IrInstGen *base_ptr = instruction->err_union_ptr->child;
21617static Stage1AirInst *ir_analyze_instruction_unwrap_err_code(IrAnalyze *ira, Stage1ZirInstUnwrapErrCode *instruction) {
21618 Stage1AirInst *base_ptr = instruction->err_union_ptr->child;
2161921619 if (type_is_invalid(base_ptr->value->type))
2162021620 return ira->codegen->invalid_inst_gen;
2162121621 return ir_analyze_unwrap_err_code(ira, instruction->base.scope, instruction->base.source_node, base_ptr, false);
2162221622}
2162321623
21624static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
21625 IrInstGen *base_ptr, bool safety_check_on, bool initializing)
21624static Stage1AirInst *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node,
21625 Stage1AirInst *base_ptr, bool safety_check_on, bool initializing)
2162621626{
2162721627 ZigType *ptr_type = base_ptr->value->type;
2162821628
......@@ -21680,7 +21680,7 @@ static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope,
2168021680 return ira->codegen->invalid_inst_gen;
2168121681 }
2168221682
21683 IrInstGen *result;
21683 Stage1AirInst *result;
2168421684 if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) {
2168521685 result = ir_build_unwrap_err_payload_gen(ira, scope,
2168621686 source_node, base_ptr, safety_check_on, initializing, result_type);
......@@ -21700,22 +21700,22 @@ static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope,
2170021700 base_ptr, safety_check_on, initializing, result_type);
2170121701}
2170221702
21703static IrInstGen *ir_analyze_instruction_unwrap_err_payload(IrAnalyze *ira,
21704 IrInstSrcUnwrapErrPayload *instruction)
21703static Stage1AirInst *ir_analyze_instruction_unwrap_err_payload(IrAnalyze *ira,
21704 Stage1ZirInstUnwrapErrPayload *instruction)
2170521705{
2170621706 assert(instruction->value->child);
21707 IrInstGen *value = instruction->value->child;
21707 Stage1AirInst *value = instruction->value->child;
2170821708 if (type_is_invalid(value->value->type))
2170921709 return ira->codegen->invalid_inst_gen;
2171021710
2171121711 return ir_analyze_unwrap_error_payload(ira, instruction->base.scope, instruction->base.source_node, value, instruction->safety_check_on, false);
2171221712}
2171321713
21714static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnProto *instruction) {
21714static Stage1AirInst *ir_analyze_instruction_fn_proto(IrAnalyze *ira, Stage1ZirInstFnProto *instruction) {
2171521715 AstNode *proto_node = instruction->base.source_node;
2171621716 assert(proto_node->type == NodeTypeFnProto);
2171721717
21718 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
21718 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
2171921719 result->value->special = ConstValSpecialLazy;
2172021720
2172121721 LazyValueFnType *lazy_fn_type = heap::c_allocator.create<LazyValueFnType>();
......@@ -21733,7 +21733,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro
2173321733 if (instruction->callconv_value != nullptr) {
2173421734 ZigType *cc_enum_type = get_builtin_type(ira->codegen, "CallingConvention");
2173521735
21736 IrInstGen *casted_value = ir_implicit_cast(ira, instruction->callconv_value->child, cc_enum_type);
21736 Stage1AirInst *casted_value = ir_implicit_cast(ira, instruction->callconv_value->child, cc_enum_type);
2173721737 if (type_is_invalid(casted_value->value->type))
2173821738 return ira->codegen->invalid_inst_gen;
2173921739
......@@ -21746,7 +21746,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro
2174621746
2174721747 size_t param_count = proto_node->data.fn_proto.params.length;
2174821748 lazy_fn_type->proto_node = proto_node;
21749 lazy_fn_type->param_types = heap::c_allocator.allocate<IrInstGen *>(param_count);
21749 lazy_fn_type->param_types = heap::c_allocator.allocate<Stage1AirInst *>(param_count);
2175021750
2175121751 for (size_t param_index = 0; param_index < param_count; param_index += 1) {
2175221752 AstNode *param_node = proto_node->data.fn_proto.params.at(param_index);
......@@ -21770,7 +21770,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro
2177021770 return result;
2177121771 }
2177221772
21773 IrInstGen *param_type_value = instruction->param_types[param_index]->child;
21773 Stage1AirInst *param_type_value = instruction->param_types[param_index]->child;
2177421774 if (type_is_invalid(param_type_value->value->type))
2177521775 return ira->codegen->invalid_inst_gen;
2177621776 if (ir_resolve_const(ira, param_type_value, LazyOk) == nullptr)
......@@ -21791,23 +21791,23 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro
2179121791 return result;
2179221792}
2179321793
21794static IrInstGen *ir_analyze_instruction_test_comptime(IrAnalyze *ira, IrInstSrcTestComptime *instruction) {
21795 IrInstGen *value = instruction->value->child;
21794static Stage1AirInst *ir_analyze_instruction_test_comptime(IrAnalyze *ira, Stage1ZirInstTestComptime *instruction) {
21795 Stage1AirInst *value = instruction->value->child;
2179621796 if (type_is_invalid(value->value->type))
2179721797 return ira->codegen->invalid_inst_gen;
2179821798
2179921799 return ir_const_bool(ira, instruction->base.scope, instruction->base.source_node, instr_is_comptime(value));
2180021800}
2180121801
21802static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
21803 IrInstSrcCheckSwitchProngs *instruction, bool have_underscore_prong)
21802static Stage1AirInst *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
21803 Stage1ZirInstCheckSwitchProngs *instruction, bool have_underscore_prong)
2180421804{
21805 IrInstGen *target_value = instruction->target_value->child;
21805 Stage1AirInst *target_value = instruction->target_value->child;
2180621806 ZigType *switch_type = target_value->value->type;
2180721807 if (type_is_invalid(switch_type))
2180821808 return ira->codegen->invalid_inst_gen;
2180921809
21810 ZigValue *original_value = ((IrInstSrcSwitchTarget *)(instruction->target_value))->target_value_ptr->child->value;
21810 ZigValue *original_value = ((Stage1ZirInstSwitchTarget *)(instruction->target_value))->target_value_ptr->child->value;
2181121811 bool target_is_originally_union = original_value->type->id == ZigTypeIdPointer &&
2181221812 original_value->type->data.pointer.child_type->id == ZigTypeIdUnion;
2181321813
......@@ -21816,19 +21816,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
2181621816 field_prev_uses.init(switch_type->data.enumeration.src_field_count);
2181721817
2181821818 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {
21819 IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i];
21819 Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i];
2182021820
21821 IrInstGen *start_value_uncasted = range->start->child;
21821 Stage1AirInst *start_value_uncasted = range->start->child;
2182221822 if (type_is_invalid(start_value_uncasted->value->type))
2182321823 return ira->codegen->invalid_inst_gen;
21824 IrInstGen *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type);
21824 Stage1AirInst *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type);
2182521825 if (type_is_invalid(start_value->value->type))
2182621826 return ira->codegen->invalid_inst_gen;
2182721827
21828 IrInstGen *end_value_uncasted = range->end->child;
21828 Stage1AirInst *end_value_uncasted = range->end->child;
2182921829 if (type_is_invalid(end_value_uncasted->value->type))
2183021830 return ira->codegen->invalid_inst_gen;
21831 IrInstGen *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type);
21831 Stage1AirInst *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type);
2183221832 if (type_is_invalid(end_value->value->type))
2183321833 return ira->codegen->invalid_inst_gen;
2183421834
......@@ -21914,19 +21914,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
2191421914 AstNode **field_prev_uses = heap::c_allocator.allocate<AstNode *>(field_prev_uses_count);
2191521915
2191621916 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {
21917 IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i];
21917 Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i];
2191821918
21919 IrInstGen *start_value_uncasted = range->start->child;
21919 Stage1AirInst *start_value_uncasted = range->start->child;
2192021920 if (type_is_invalid(start_value_uncasted->value->type))
2192121921 return ira->codegen->invalid_inst_gen;
21922 IrInstGen *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type);
21922 Stage1AirInst *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type);
2192321923 if (type_is_invalid(start_value->value->type))
2192421924 return ira->codegen->invalid_inst_gen;
2192521925
21926 IrInstGen *end_value_uncasted = range->end->child;
21926 Stage1AirInst *end_value_uncasted = range->end->child;
2192721927 if (type_is_invalid(end_value_uncasted->value->type))
2192821928 return ira->codegen->invalid_inst_gen;
21929 IrInstGen *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type);
21929 Stage1AirInst *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type);
2193021930 if (type_is_invalid(end_value->value->type))
2193121931 return ira->codegen->invalid_inst_gen;
2193221932
......@@ -21972,19 +21972,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
2197221972 } else if (switch_type->id == ZigTypeIdInt) {
2197321973 RangeSet rs = {0};
2197421974 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {
21975 IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i];
21975 Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i];
2197621976
21977 IrInstGen *start_value = range->start->child;
21977 Stage1AirInst *start_value = range->start->child;
2197821978 if (type_is_invalid(start_value->value->type))
2197921979 return ira->codegen->invalid_inst_gen;
21980 IrInstGen *casted_start_value = ir_implicit_cast(ira, start_value, switch_type);
21980 Stage1AirInst *casted_start_value = ir_implicit_cast(ira, start_value, switch_type);
2198121981 if (type_is_invalid(casted_start_value->value->type))
2198221982 return ira->codegen->invalid_inst_gen;
2198321983
21984 IrInstGen *end_value = range->end->child;
21984 Stage1AirInst *end_value = range->end->child;
2198521985 if (type_is_invalid(end_value->value->type))
2198621986 return ira->codegen->invalid_inst_gen;
21987 IrInstGen *casted_end_value = ir_implicit_cast(ira, end_value, switch_type);
21987 Stage1AirInst *casted_end_value = ir_implicit_cast(ira, end_value, switch_type);
2198821988 if (type_is_invalid(casted_end_value->value->type))
2198921989 return ira->codegen->invalid_inst_gen;
2199021990
......@@ -22030,11 +22030,11 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
2203022030 int seenTrue = 0;
2203122031 int seenFalse = 0;
2203222032 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {
22033 IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i];
22033 Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i];
2203422034
22035 IrInstGen *value = range->start->child;
22035 Stage1AirInst *value = range->start->child;
2203622036
22037 IrInstGen *casted_value = ir_implicit_cast(ira, value, switch_type);
22037 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, switch_type);
2203822038 if (type_is_invalid(casted_value->value->type))
2203922039 return ira->codegen->invalid_inst_gen;
2204022040
......@@ -22070,15 +22070,15 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
2207022070 buf_sprintf("else prong required when switching on type '%s'", buf_ptr(&switch_type->name)));
2207122071 return ira->codegen->invalid_inst_gen;
2207222072 } else if(switch_type->id == ZigTypeIdMetaType) {
22073 HashMap<const ZigType*, IrInstGen*, type_ptr_hash, type_ptr_eql> prevs;
22073 HashMap<const ZigType*, Stage1AirInst*, type_ptr_hash, type_ptr_eql> prevs;
2207422074 // HashMap doubles capacity when reaching 60% capacity,
2207522075 // because we know the size at init we can avoid reallocation by doubling it here
2207622076 prevs.init(instruction->range_count * 2);
2207722077 for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) {
22078 IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i];
22078 Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i];
2207922079
22080 IrInstGen *value = range->start->child;
22081 IrInstGen *casted_value = ir_implicit_cast(ira, value, switch_type);
22080 Stage1AirInst *value = range->start->child;
22081 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, switch_type);
2208222082 if (type_is_invalid(casted_value->value->type)) {
2208322083 prevs.deinit();
2208422084 return ira->codegen->invalid_inst_gen;
......@@ -22103,10 +22103,10 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira,
2210322103 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
2210422104}
2210522105
22106static IrInstGen *ir_analyze_instruction_check_statement_is_void(IrAnalyze *ira,
22107 IrInstSrcCheckStatementIsVoid *instruction)
22106static Stage1AirInst *ir_analyze_instruction_check_statement_is_void(IrAnalyze *ira,
22107 Stage1ZirInstCheckStatementIsVoid *instruction)
2210822108{
22109 IrInstGen *statement_value = instruction->statement_value->child;
22109 Stage1AirInst *statement_value = instruction->statement_value->child;
2211022110 ZigType *statement_type = statement_value->value->type;
2211122111 if (type_is_invalid(statement_type))
2211222112 return ira->codegen->invalid_inst_gen;
......@@ -22122,8 +22122,8 @@ static IrInstGen *ir_analyze_instruction_check_statement_is_void(IrAnalyze *ira,
2212222122 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
2212322123}
2212422124
22125static IrInstGen *ir_analyze_instruction_panic(IrAnalyze *ira, IrInstSrcPanic *instruction) {
22126 IrInstGen *msg = instruction->msg->child;
22125static Stage1AirInst *ir_analyze_instruction_panic(IrAnalyze *ira, Stage1ZirInstPanic *instruction) {
22126 Stage1AirInst *msg = instruction->msg->child;
2212722127 if (type_is_invalid(msg->value->type))
2212822128 return ir_unreach_error(ira);
2212922129
......@@ -22135,15 +22135,15 @@ static IrInstGen *ir_analyze_instruction_panic(IrAnalyze *ira, IrInstSrcPanic *i
2213522135 ZigType *u8_ptr_type = get_pointer_to_type_extra(ira->codegen, ira->codegen->builtin_types.entry_u8,
2213622136 true, false, PtrLenUnknown, 0, 0, 0, false);
2213722137 ZigType *str_type = get_slice_type(ira->codegen, u8_ptr_type);
22138 IrInstGen *casted_msg = ir_implicit_cast(ira, msg, str_type);
22138 Stage1AirInst *casted_msg = ir_implicit_cast(ira, msg, str_type);
2213922139 if (type_is_invalid(casted_msg->value->type))
2214022140 return ir_unreach_error(ira);
2214122141
22142 IrInstGen *new_instruction = ir_build_panic_gen(ira, instruction->base.scope, instruction->base.source_node, casted_msg);
22142 Stage1AirInst *new_instruction = ir_build_panic_gen(ira, instruction->base.scope, instruction->base.source_node, casted_msg);
2214322143 return ir_finish_anal(ira, new_instruction);
2214422144}
2214522145
22146static IrInstGen *ir_align_cast(IrAnalyze *ira, IrInstGen *target, uint32_t align_bytes, bool safety_check_on) {
22146static Stage1AirInst *ir_align_cast(IrAnalyze *ira, Stage1AirInst *target, uint32_t align_bytes, bool safety_check_on) {
2214722147 Error err;
2214822148
2214922149 ZigType *target_type = target->value->type;
......@@ -22224,7 +22224,7 @@ static IrInstGen *ir_align_cast(IrAnalyze *ira, IrInstGen *target, uint32_t alig
2222422224 return ira->codegen->invalid_inst_gen;
2222522225 }
2222622226
22227 IrInstGen *result = ir_const(ira, target->scope, target->source_node, result_type);
22227 Stage1AirInst *result = ir_const(ira, target->scope, target->source_node, result_type);
2222822228 copy_const_val(ira->codegen, result->value, val);
2222922229 result->value->type = result_type;
2223022230 return result;
......@@ -22237,8 +22237,8 @@ static IrInstGen *ir_align_cast(IrAnalyze *ira, IrInstGen *target, uint32_t alig
2223722237 }
2223822238}
2223922239
22240static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
22241 IrInstGen *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src,
22240static Stage1AirInst *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node,
22241 Stage1AirInst *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src,
2224222242 bool safety_check_on, bool keep_bigger_alignment)
2224322243{
2224422244 Error err;
......@@ -22312,8 +22312,8 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
2231222312 // For slices, follow the `ptr` field.
2231322313 if (is_slice(src_type)) {
2231422314 TypeStructField *ptr_field = src_type->data.structure.fields[slice_ptr_index];
22315 IrInstGen *ptr_ref = ir_get_ref(ira, scope, source_node, ptr, true, false);
22316 IrInstGen *ptr_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, ptr_field, ptr_ref, src_type, false);
22315 Stage1AirInst *ptr_ref = ir_get_ref(ira, scope, source_node, ptr, true, false);
22316 Stage1AirInst *ptr_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, ptr_field, ptr_ref, src_type, false);
2231722317 ptr = ir_get_deref(ira, scope, source_node, ptr_ptr, nullptr);
2231822318 }
2231922319
......@@ -22335,7 +22335,7 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
2233522335 }
2233622336 }
2233722337
22338 IrInstGen *result;
22338 Stage1AirInst *result;
2233922339 if (val->data.x_ptr.mut == ConstPtrMutInfer) {
2234022340 result = ir_build_ptr_cast_gen(ira, scope, source_node, dest_type, ptr, safety_check_on);
2234122341 } else {
......@@ -22380,10 +22380,10 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
2238022380 return ira->codegen->invalid_inst_gen;
2238122381 }
2238222382
22383 IrInstGen *casted_ptr = ir_build_ptr_cast_gen(ira, scope, source_node, dest_type, ptr, safety_check_on);
22383 Stage1AirInst *casted_ptr = ir_build_ptr_cast_gen(ira, scope, source_node, dest_type, ptr, safety_check_on);
2238422384
2238522385 // Keep the bigger alignment, it can only help- unless the target is zero bits.
22386 IrInstGen *result;
22386 Stage1AirInst *result;
2238722387 if (keep_bigger_alignment && src_align_bytes > dest_align_bytes && type_has_bits(ira->codegen, dest_type)) {
2238822388 result = ir_align_cast(ira, casted_ptr, src_align_bytes, false);
2238922389 if (type_is_invalid(result->value->type))
......@@ -22394,13 +22394,13 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
2239422394 return result;
2239522395}
2239622396
22397static IrInstGen *ir_analyze_instruction_ptr_cast(IrAnalyze *ira, IrInstSrcPtrCast *instruction) {
22398 IrInstGen *dest_type_value = instruction->dest_type->child;
22397static Stage1AirInst *ir_analyze_instruction_ptr_cast(IrAnalyze *ira, Stage1ZirInstPtrCast *instruction) {
22398 Stage1AirInst *dest_type_value = instruction->dest_type->child;
2239922399 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);
2240022400 if (type_is_invalid(dest_type))
2240122401 return ira->codegen->invalid_inst_gen;
2240222402
22403 IrInstGen *ptr = instruction->ptr->child;
22403 Stage1AirInst *ptr = instruction->ptr->child;
2240422404 ZigType *src_type = ptr->value->type;
2240522405 if (type_is_invalid(src_type))
2240622406 return ira->codegen->invalid_inst_gen;
......@@ -22762,7 +22762,7 @@ static Error buf_read_value_bytes(IrAnalyze *ira, CodeGen *codegen, AstNode *sou
2276222762 zig_unreachable();
2276322763}
2276422764
22765static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value,
22765static Stage1AirInst *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value,
2276622766 ZigType *dest_type)
2276722767{
2276822768 Error err;
......@@ -22813,7 +22813,7 @@ static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
2281322813 if (!val)
2281422814 return ira->codegen->invalid_inst_gen;
2281522815
22816 IrInstGen *result = ir_const(ira, scope, source_node, dest_type);
22816 Stage1AirInst *result = ir_const(ira, scope, source_node, dest_type);
2281722817 uint8_t *buf = heap::c_allocator.allocate_nonzero<uint8_t>(src_size_bytes);
2281822818 buf_write_value_bytes(ira->codegen, buf, val);
2281922819 if ((err = buf_read_value_bytes(ira, ira->codegen, source_node, buf, result->value)))
......@@ -22830,7 +22830,7 @@ static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *sou
2283022830 return ir_build_bit_cast_gen(ira, scope, source_node, value, dest_type);
2283122831}
2283222832
22833static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target,
22833static Stage1AirInst *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target,
2283422834 ZigType *ptr_type)
2283522835{
2283622836 Error err;
......@@ -22838,7 +22838,7 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s
2283822838 src_assert(get_src_ptr_type(ptr_type) != nullptr, source_node);
2283922839 src_assert(type_has_bits(ira->codegen, ptr_type), source_node);
2284022840
22841 IrInstGen *casted_int = ir_implicit_cast(ira, target, ira->codegen->builtin_types.entry_usize);
22841 Stage1AirInst *casted_int = ir_implicit_cast(ira, target, ira->codegen->builtin_types.entry_usize);
2284222842 if (type_is_invalid(casted_int->value->type))
2284322843 return ira->codegen->invalid_inst_gen;
2284422844
......@@ -22865,7 +22865,7 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s
2286522865 return ira->codegen->invalid_inst_gen;
2286622866 }
2286722867
22868 IrInstGen *result = ir_const(ira, scope, source_node, ptr_type);
22868 Stage1AirInst *result = ir_const(ira, scope, source_node, ptr_type);
2286922869 if (ptr_type->id == ZigTypeIdOptional && addr == 0) {
2287022870 result->value->data.x_ptr.special = ConstPtrSpecialNull;
2287122871 result->value->data.x_ptr.mut = ConstPtrMutComptimeConst;
......@@ -22881,9 +22881,9 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s
2288122881 return ir_build_int_to_ptr_gen(ira, scope, source_node, casted_int, ptr_type);
2288222882}
2288322883
22884static IrInstGen *ir_analyze_instruction_int_to_ptr(IrAnalyze *ira, IrInstSrcIntToPtr *instruction) {
22884static Stage1AirInst *ir_analyze_instruction_int_to_ptr(IrAnalyze *ira, Stage1ZirInstIntToPtr *instruction) {
2288522885 Error err;
22886 IrInstGen *dest_type_value = instruction->dest_type->child;
22886 Stage1AirInst *dest_type_value = instruction->dest_type->child;
2288722887 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);
2288822888 if (type_is_invalid(dest_type))
2288922889 return ira->codegen->invalid_inst_gen;
......@@ -22904,15 +22904,15 @@ static IrInstGen *ir_analyze_instruction_int_to_ptr(IrAnalyze *ira, IrInstSrcInt
2290422904 return ira->codegen->invalid_inst_gen;
2290522905 }
2290622906
22907 IrInstGen *target = instruction->target->child;
22907 Stage1AirInst *target = instruction->target->child;
2290822908 if (type_is_invalid(target->value->type))
2290922909 return ira->codegen->invalid_inst_gen;
2291022910
2291122911 return ir_analyze_int_to_ptr(ira, instruction->base.scope, instruction->base.source_node, target, dest_type);
2291222912}
2291322913
22914static IrInstGen *ir_analyze_instruction_decl_ref(IrAnalyze *ira, IrInstSrcDeclRef *instruction) {
22915 IrInstGen *ref_instruction = ir_analyze_decl_ref(ira, instruction->base.scope, instruction->base.source_node, instruction->tld);
22914static Stage1AirInst *ir_analyze_instruction_decl_ref(IrAnalyze *ira, Stage1ZirInstDeclRef *instruction) {
22915 Stage1AirInst *ref_instruction = ir_analyze_decl_ref(ira, instruction->base.scope, instruction->base.source_node, instruction->tld);
2291622916 if (type_is_invalid(ref_instruction->value->type)) {
2291722917 return ira->codegen->invalid_inst_gen;
2291822918 }
......@@ -22924,9 +22924,9 @@ static IrInstGen *ir_analyze_instruction_decl_ref(IrAnalyze *ira, IrInstSrcDeclR
2292422924 }
2292522925}
2292622926
22927static IrInstGen *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, IrInstSrcPtrToInt *instruction) {
22927static Stage1AirInst *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, Stage1ZirInstPtrToInt *instruction) {
2292822928 Error err;
22929 IrInstGen *target = instruction->target->child;
22929 Stage1AirInst *target = instruction->target->child;
2293022930 if (type_is_invalid(target->value->type))
2293122931 return ira->codegen->invalid_inst_gen;
2293222932
......@@ -22957,12 +22957,12 @@ static IrInstGen *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, IrInstSrcPtr
2295722957 // Since we've already run this type trough get_src_ptr_type it is
2295822958 // safe to access the x_ptr fields
2295922959 if (val->data.x_ptr.special == ConstPtrSpecialHardCodedAddr) {
22960 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize);
22960 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize);
2296122961 bigint_init_unsigned(&result->value->data.x_bigint, val->data.x_ptr.data.hard_coded_addr.addr);
2296222962 result->value->type = usize;
2296322963 return result;
2296422964 } else if (val->data.x_ptr.special == ConstPtrSpecialNull) {
22965 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize);
22965 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize);
2296622966 bigint_init_unsigned(&result->value->data.x_bigint, 0);
2296722967 result->value->type = usize;
2296822968 return result;
......@@ -22972,10 +22972,10 @@ static IrInstGen *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, IrInstSrcPtr
2297222972 return ir_build_ptr_to_int_gen(ira, instruction->base.scope, instruction->base.source_node, target);
2297322973}
2297422974
22975static IrInstGen *ir_analyze_instruction_ptr_type_simple(IrAnalyze *ira,
22976 IrInstSrcPtrTypeSimple *instruction, bool is_const)
22975static Stage1AirInst *ir_analyze_instruction_ptr_type_simple(IrAnalyze *ira,
22976 Stage1ZirInstPtrTypeSimple *instruction, bool is_const)
2297722977{
22978 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
22978 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
2297922979 result->value->special = ConstValSpecialLazy;
2298022980
2298122981 LazyValuePtrTypeSimple *lazy_ptr_type = heap::c_allocator.create<LazyValuePtrTypeSimple>();
......@@ -22990,8 +22990,8 @@ static IrInstGen *ir_analyze_instruction_ptr_type_simple(IrAnalyze *ira,
2299022990 return result;
2299122991}
2299222992
22993static IrInstGen *ir_analyze_instruction_ptr_type(IrAnalyze *ira, IrInstSrcPtrType *instruction) {
22994 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
22993static Stage1AirInst *ir_analyze_instruction_ptr_type(IrAnalyze *ira, Stage1ZirInstPtrType *instruction) {
22994 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type);
2299522995 result->value->special = ConstValSpecialLazy;
2299622996
2299722997 LazyValuePtrType *lazy_ptr_type = heap::c_allocator.create<LazyValuePtrType>();
......@@ -23031,8 +23031,8 @@ static IrInstGen *ir_analyze_instruction_ptr_type(IrAnalyze *ira, IrInstSrcPtrTy
2303123031 return result;
2303223032}
2303323033
23034static IrInstGen *ir_analyze_instruction_align_cast(IrAnalyze *ira, IrInstSrcAlignCast *instruction) {
23035 IrInstGen *target = instruction->target->child;
23034static Stage1AirInst *ir_analyze_instruction_align_cast(IrAnalyze *ira, Stage1ZirInstAlignCast *instruction) {
23035 Stage1AirInst *target = instruction->target->child;
2303623036 if (type_is_invalid(target->value->type))
2303723037 return ira->codegen->invalid_inst_gen;
2303823038
......@@ -23045,20 +23045,20 @@ static IrInstGen *ir_analyze_instruction_align_cast(IrAnalyze *ira, IrInstSrcAli
2304523045 }
2304623046
2304723047 uint32_t align_bytes;
23048 IrInstGen *align_bytes_inst = instruction->align_bytes->child;
23048 Stage1AirInst *align_bytes_inst = instruction->align_bytes->child;
2304923049 if (!ir_resolve_align(ira, align_bytes_inst, elem_type, &align_bytes))
2305023050 return ira->codegen->invalid_inst_gen;
2305123051
23052 IrInstGen *result = ir_align_cast(ira, target, align_bytes, true);
23052 Stage1AirInst *result = ir_align_cast(ira, target, align_bytes, true);
2305323053 if (type_is_invalid(result->value->type))
2305423054 return ira->codegen->invalid_inst_gen;
2305523055
2305623056 return result;
2305723057}
2305823058
23059static IrInstGen *ir_analyze_instruction_set_align_stack(IrAnalyze *ira, IrInstSrcSetAlignStack *instruction) {
23059static Stage1AirInst *ir_analyze_instruction_set_align_stack(IrAnalyze *ira, Stage1ZirInstSetAlignStack *instruction) {
2306023060 uint32_t align_bytes;
23061 IrInstGen *align_bytes_inst = instruction->align_bytes->child;
23061 Stage1AirInst *align_bytes_inst = instruction->align_bytes->child;
2306223062 if (!ir_resolve_align(ira, align_bytes_inst, nullptr, &align_bytes))
2306323063 return ira->codegen->invalid_inst_gen;
2306423064
......@@ -23095,15 +23095,15 @@ static IrInstGen *ir_analyze_instruction_set_align_stack(IrAnalyze *ira, IrInstS
2309523095 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
2309623096}
2309723097
23098static IrInstGen *ir_analyze_instruction_arg_type(IrAnalyze *ira, IrInstSrcArgType *instruction,
23098static Stage1AirInst *ir_analyze_instruction_arg_type(IrAnalyze *ira, Stage1ZirInstArgType *instruction,
2309923099 bool allow_var)
2310023100{
23101 IrInstGen *fn_type_inst = instruction->fn_type->child;
23101 Stage1AirInst *fn_type_inst = instruction->fn_type->child;
2310223102 ZigType *fn_type = ir_resolve_type(ira, fn_type_inst);
2310323103 if (type_is_invalid(fn_type))
2310423104 return ira->codegen->invalid_inst_gen;
2310523105
23106 IrInstGen *arg_index_inst = instruction->arg_index->child;
23106 Stage1AirInst *arg_index_inst = instruction->arg_index->child;
2310723107 uint64_t arg_index;
2310823108 if (!ir_resolve_usize(ira, arg_index_inst, &arg_index))
2310923109 return ira->codegen->invalid_inst_gen;
......@@ -23146,7 +23146,7 @@ static IrInstGen *ir_analyze_instruction_arg_type(IrAnalyze *ira, IrInstSrcArgTy
2314623146 return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, result_type);
2314723147}
2314823148
23149static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstGen *op) {
23149static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, Stage1AirInst *op) {
2315023150 ZigType *operand_type = ir_resolve_type(ira, op);
2315123151 if (type_is_invalid(operand_type))
2315223152 return ira->codegen->builtin_types.entry_invalid;
......@@ -23193,18 +23193,18 @@ static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstGen *op) {
2319323193 return operand_type;
2319423194}
2319523195
23196static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAtomicRmw *instruction) {
23196static Stage1AirInst *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, Stage1ZirInstAtomicRmw *instruction) {
2319723197 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child);
2319823198 if (type_is_invalid(operand_type))
2319923199 return ira->codegen->invalid_inst_gen;
2320023200
23201 IrInstGen *ptr_inst = instruction->ptr->child;
23201 Stage1AirInst *ptr_inst = instruction->ptr->child;
2320223202 if (type_is_invalid(ptr_inst->value->type))
2320323203 return ira->codegen->invalid_inst_gen;
2320423204
2320523205 // TODO let this be volatile
2320623206 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false);
23207 IrInstGen *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);
23207 Stage1AirInst *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);
2320823208 if (type_is_invalid(casted_ptr->value->type))
2320923209 return ira->codegen->invalid_inst_gen;
2321023210
......@@ -23227,11 +23227,11 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
2322723227 return ira->codegen->invalid_inst_gen;
2322823228 }
2322923229
23230 IrInstGen *operand = instruction->operand->child;
23230 Stage1AirInst *operand = instruction->operand->child;
2323123231 if (type_is_invalid(operand->value->type))
2323223232 return ira->codegen->invalid_inst_gen;
2323323233
23234 IrInstGen *casted_operand = ir_implicit_cast(ira, operand, operand_type);
23234 Stage1AirInst *casted_operand = ir_implicit_cast(ira, operand, operand_type);
2323523235 if (type_is_invalid(casted_operand->value->type))
2323623236 return ira->codegen->invalid_inst_gen;
2323723237
......@@ -23269,7 +23269,7 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
2326923269 if (op2_val == nullptr)
2327023270 return ira->codegen->invalid_inst_gen;
2327123271
23272 IrInstGen *result = ir_const(ira, scope, source_node, operand_type);
23272 Stage1AirInst *result = ir_const(ira, scope, source_node, operand_type);
2327323273 copy_const_val(ira->codegen, result->value, op1_val);
2327423274 if (op == AtomicRmwOp_xchg) {
2327523275 copy_const_val(ira->codegen, op1_val, op2_val);
......@@ -23292,7 +23292,7 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
2329223292 // store op2 if op2 > op1
2329323293 bin_op = IrBinOpCmpLessThan;
2329423294
23295 IrInstGen *dummy_value = ir_const(ira, scope, source_node, operand_type);
23295 Stage1AirInst *dummy_value = ir_const(ira, scope, source_node, operand_type);
2329623296 msg = ir_eval_bin_op_cmp_scalar(ira, scope, source_node, op1_val, bin_op, op2_val, dummy_value->value);
2329723297 if (msg != nullptr) {
2329823298 return ira->codegen->invalid_inst_gen;
......@@ -23345,17 +23345,17 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
2334523345 ordering, operand_type);
2334623346}
2334723347
23348static IrInstGen *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstSrcAtomicLoad *instruction) {
23348static Stage1AirInst *ir_analyze_instruction_atomic_load(IrAnalyze *ira, Stage1ZirInstAtomicLoad *instruction) {
2334923349 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child);
2335023350 if (type_is_invalid(operand_type))
2335123351 return ira->codegen->invalid_inst_gen;
2335223352
23353 IrInstGen *ptr_inst = instruction->ptr->child;
23353 Stage1AirInst *ptr_inst = instruction->ptr->child;
2335423354 if (type_is_invalid(ptr_inst->value->type))
2335523355 return ira->codegen->invalid_inst_gen;
2335623356
2335723357 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, true);
23358 IrInstGen *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);
23358 Stage1AirInst *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);
2335923359 if (type_is_invalid(casted_ptr->value->type))
2336023360 return ira->codegen->invalid_inst_gen;
2336123361
......@@ -23371,7 +23371,7 @@ static IrInstGen *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstSrcAt
2337123371 }
2337223372
2337323373 if (instr_is_comptime(casted_ptr)) {
23374 IrInstGen *result = ir_get_deref(ira, instruction->base.scope,
23374 Stage1AirInst *result = ir_get_deref(ira, instruction->base.scope,
2337523375 instruction->base.source_node, casted_ptr, nullptr);
2337623376 src_assert(result->value->type != nullptr, instruction->base.source_node);
2337723377 return result;
......@@ -23380,25 +23380,25 @@ static IrInstGen *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstSrcAt
2338023380 return ir_build_atomic_load_gen(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, ordering, operand_type);
2338123381}
2338223382
23383static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcAtomicStore *instruction) {
23383static Stage1AirInst *ir_analyze_instruction_atomic_store(IrAnalyze *ira, Stage1ZirInstAtomicStore *instruction) {
2338423384 ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child);
2338523385 if (type_is_invalid(operand_type))
2338623386 return ira->codegen->invalid_inst_gen;
2338723387
23388 IrInstGen *ptr_inst = instruction->ptr->child;
23388 Stage1AirInst *ptr_inst = instruction->ptr->child;
2338923389 if (type_is_invalid(ptr_inst->value->type))
2339023390 return ira->codegen->invalid_inst_gen;
2339123391
2339223392 ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false);
23393 IrInstGen *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);
23393 Stage1AirInst *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type);
2339423394 if (type_is_invalid(casted_ptr->value->type))
2339523395 return ira->codegen->invalid_inst_gen;
2339623396
23397 IrInstGen *value = instruction->value->child;
23397 Stage1AirInst *value = instruction->value->child;
2339823398 if (type_is_invalid(value->value->type))
2339923399 return ira->codegen->invalid_inst_gen;
2340023400
23401 IrInstGen *casted_value = ir_implicit_cast(ira, value, operand_type);
23401 Stage1AirInst *casted_value = ir_implicit_cast(ira, value, operand_type);
2340223402 if (type_is_invalid(casted_value->value->type))
2340323403 return ira->codegen->invalid_inst_gen;
2340423404
......@@ -23425,7 +23425,7 @@ static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcA
2342523425 }
2342623426
2342723427 if (instr_is_comptime(casted_value) && instr_is_comptime(casted_ptr)) {
23428 IrInstGen *result = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, value, false);
23428 Stage1AirInst *result = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, value, false);
2342923429 result->value->type = ira->codegen->builtin_types.entry_void;
2343023430 return result;
2343123431 }
......@@ -23433,7 +23433,7 @@ static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcA
2343323433 return ir_build_atomic_store_gen(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, casted_value, ordering);
2343423434}
2343523435
23436static IrInstGen *ir_analyze_instruction_save_err_ret_addr(IrAnalyze *ira, IrInstSrcSaveErrRetAddr *instruction) {
23436static Stage1AirInst *ir_analyze_instruction_save_err_ret_addr(IrAnalyze *ira, Stage1ZirInstSaveErrRetAddr *instruction) {
2343723437 return ir_build_save_err_ret_addr_gen(ira, instruction->base.scope, instruction->base.source_node);
2343823438}
2343923439
......@@ -23660,8 +23660,8 @@ static ErrorMsg *ir_eval_float_op(IrAnalyze *ira, Scope *scope, AstNode *source_
2366023660 return nullptr;
2366123661}
2366223662
23663static IrInstGen *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstSrcFloatOp *instruction) {
23664 IrInstGen *operand = instruction->operand->child;
23663static Stage1AirInst *ir_analyze_instruction_float_op(IrAnalyze *ira, Stage1ZirInstFloatOp *instruction) {
23664 Stage1AirInst *operand = instruction->operand->child;
2366523665 ZigType *operand_type = operand->value->type;
2366623666 if (type_is_invalid(operand_type))
2366723667 return ira->codegen->invalid_inst_gen;
......@@ -23683,7 +23683,7 @@ static IrInstGen *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstSrcFloat
2368323683 if (operand_val->special == ConstValSpecialUndef)
2368423684 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, operand_type);
2368523685
23686 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, operand_type);
23686 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, operand_type);
2368723687 ZigValue *out_val = result->value;
2368823688
2368923689 if (operand_type->id == ZigTypeIdVector) {
......@@ -23722,14 +23722,14 @@ static IrInstGen *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstSrcFloat
2372223722 return ir_build_float_op_gen(ira, instruction->base.scope, instruction->base.source_node, operand, instruction->fn_id, operand_type);
2372323723}
2372423724
23725static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *instruction) {
23725static Stage1AirInst *ir_analyze_instruction_bswap(IrAnalyze *ira, Stage1ZirInstBswap *instruction) {
2372623726 Error err;
2372723727
2372823728 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
2372923729 if (type_is_invalid(int_type))
2373023730 return ira->codegen->invalid_inst_gen;
2373123731
23732 IrInstGen *uncasted_op = instruction->op->child;
23732 Stage1AirInst *uncasted_op = instruction->op->child;
2373323733 if (type_is_invalid(uncasted_op->value->type))
2373423734 return ira->codegen->invalid_inst_gen;
2373523735
......@@ -23751,7 +23751,7 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i
2375123751 bool is_vector = (vector_len != UINT32_MAX);
2375223752 ZigType *op_type = is_vector ? get_vector_type(ira->codegen, vector_len, int_type) : int_type;
2375323753
23754 IrInstGen *op = ir_implicit_cast(ira, uncasted_op, op_type);
23754 Stage1AirInst *op = ir_implicit_cast(ira, uncasted_op, op_type);
2375523755 if (type_is_invalid(op->value->type))
2375623756 return ira->codegen->invalid_inst_gen;
2375723757
......@@ -23772,7 +23772,7 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i
2377223772 if (val->special == ConstValSpecialUndef)
2377323773 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, op_type);
2377423774
23775 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, op_type);
23775 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, op_type);
2377623776 const size_t buf_size = int_type->data.integral.bit_count / 8;
2377723777 uint8_t *buf = heap::c_allocator.allocate_nonzero<uint8_t>(buf_size);
2377823778 if (is_vector) {
......@@ -23808,17 +23808,17 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i
2380823808 return ir_build_bswap_gen(ira, instruction->base.scope, instruction->base.source_node, op_type, op);
2380923809}
2381023810
23811static IrInstGen *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, IrInstSrcBitReverse *instruction) {
23811static Stage1AirInst *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, Stage1ZirInstBitReverse *instruction) {
2381223812 ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
2381323813 if (type_is_invalid(int_type))
2381423814 return ira->codegen->invalid_inst_gen;
2381523815
23816 IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type);
23816 Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type);
2381723817 if (type_is_invalid(op->value->type))
2381823818 return ira->codegen->invalid_inst_gen;
2381923819
2382023820 if (int_type->data.integral.bit_count == 0) {
23821 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type);
23821 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type);
2382223822 bigint_init_unsigned(&result->value->data.x_bigint, 0);
2382323823 return result;
2382423824 }
......@@ -23830,7 +23830,7 @@ static IrInstGen *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, IrInstSrcBi
2383023830 if (val->special == ConstValSpecialUndef)
2383123831 return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, int_type);
2383223832
23833 IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type);
23833 Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type);
2383423834 size_t num_bits = int_type->data.integral.bit_count;
2383523835 size_t buf_size = (num_bits + 7) / 8;
2383623836 uint8_t *comptime_buf = heap::c_allocator.allocate_nonzero<uint8_t>(buf_size);
......@@ -23863,17 +23863,17 @@ static IrInstGen *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, IrInstSrcBi
2386323863}
2386423864
2386523865
23866static IrInstGen *ir_analyze_instruction_enum_to_int(IrAnalyze *ira, IrInstSrcEnumToInt *instruction) {
23867 IrInstGen *target = instruction->target->child;
23866static Stage1AirInst *ir_analyze_instruction_enum_to_int(IrAnalyze *ira, Stage1ZirInstEnumToInt *instruction) {
23867 Stage1AirInst *target = instruction->target->child;
2386823868 if (type_is_invalid(target->value->type))
2386923869 return ira->codegen->invalid_inst_gen;
2387023870
2387123871 return ir_analyze_enum_to_int(ira, instruction->base.scope, instruction->base.source_node, target);
2387223872}
2387323873
23874static IrInstGen *ir_analyze_instruction_int_to_enum(IrAnalyze *ira, IrInstSrcIntToEnum *instruction) {
23874static Stage1AirInst *ir_analyze_instruction_int_to_enum(IrAnalyze *ira, Stage1ZirInstIntToEnum *instruction) {
2387523875 Error err;
23876 IrInstGen *dest_type_value = instruction->dest_type->child;
23876 Stage1AirInst *dest_type_value = instruction->dest_type->child;
2387723877 ZigType *dest_type = ir_resolve_type(ira, dest_type_value);
2387823878 if (type_is_invalid(dest_type))
2387923879 return ira->codegen->invalid_inst_gen;
......@@ -23889,24 +23889,24 @@ static IrInstGen *ir_analyze_instruction_int_to_enum(IrAnalyze *ira, IrInstSrcIn
2388923889
2389023890 ZigType *tag_type = dest_type->data.enumeration.tag_int_type;
2389123891
23892 IrInstGen *target = instruction->target->child;
23892 Stage1AirInst *target = instruction->target->child;
2389323893 if (type_is_invalid(target->value->type))
2389423894 return ira->codegen->invalid_inst_gen;
2389523895
23896 IrInstGen *casted_target = ir_implicit_cast(ira, target, tag_type);
23896 Stage1AirInst *casted_target = ir_implicit_cast(ira, target, tag_type);
2389723897 if (type_is_invalid(casted_target->value->type))
2389823898 return ira->codegen->invalid_inst_gen;
2389923899
2390023900 return ir_analyze_int_to_enum(ira, instruction->base.scope, instruction->base.source_node, casted_target, dest_type);
2390123901}
2390223902
23903static IrInstGen *ir_analyze_instruction_check_runtime_scope(IrAnalyze *ira, IrInstSrcCheckRuntimeScope *instruction) {
23904 IrInstGen *block_comptime_inst = instruction->scope_is_comptime->child;
23903static Stage1AirInst *ir_analyze_instruction_check_runtime_scope(IrAnalyze *ira, Stage1ZirInstCheckRuntimeScope *instruction) {
23904 Stage1AirInst *block_comptime_inst = instruction->scope_is_comptime->child;
2390523905 bool scope_is_comptime;
2390623906 if (!ir_resolve_bool(ira, block_comptime_inst, &scope_is_comptime))
2390723907 return ira->codegen->invalid_inst_gen;
2390823908
23909 IrInstGen *is_comptime_inst = instruction->is_comptime->child;
23909 Stage1AirInst *is_comptime_inst = instruction->is_comptime->child;
2391023910 bool is_comptime;
2391123911 if (!ir_resolve_bool(ira, is_comptime_inst, &is_comptime))
2391223912 return ira->codegen->invalid_inst_gen;
......@@ -23922,7 +23922,7 @@ static IrInstGen *ir_analyze_instruction_check_runtime_scope(IrAnalyze *ira, IrI
2392223922 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
2392323923}
2392423924
23925static IrInstGen *ir_analyze_instruction_has_decl(IrAnalyze *ira, IrInstSrcHasDecl *instruction) {
23925static Stage1AirInst *ir_analyze_instruction_has_decl(IrAnalyze *ira, Stage1ZirInstHasDecl *instruction) {
2392623926 ZigType *container_type = ir_resolve_type(ira, instruction->container->child);
2392723927 if (type_is_invalid(container_type))
2392823928 return ira->codegen->invalid_inst_gen;
......@@ -23965,7 +23965,7 @@ static void populate_invalid_variable_in_scope(CodeGen *g, Scope *scope, AstNode
2396523965 scope_decls->decl_table.put(var_name, &tld_var->base);
2396623966}
2396723967
23968static IrInstGen *ir_analyze_instruction_undeclared_ident(IrAnalyze *ira, IrInstSrcUndeclaredIdent *instruction) {
23968static Stage1AirInst *ir_analyze_instruction_undeclared_ident(IrAnalyze *ira, Stage1ZirInstUndeclaredIdent *instruction) {
2396923969 // put a variable of same name with invalid type in global scope
2397023970 // so that future references to this same name will find a variable with an invalid type
2397123971 populate_invalid_variable_in_scope(ira->codegen, instruction->base.scope,
......@@ -23975,13 +23975,13 @@ static IrInstGen *ir_analyze_instruction_undeclared_ident(IrAnalyze *ira, IrInst
2397523975 return ira->codegen->invalid_inst_gen;
2397623976}
2397723977
23978static IrInstGen *ir_analyze_instruction_end_expr(IrAnalyze *ira, IrInstSrcEndExpr *instruction) {
23979 IrInstGen *value = instruction->value->child;
23978static Stage1AirInst *ir_analyze_instruction_end_expr(IrAnalyze *ira, Stage1ZirInstEndExpr *instruction) {
23979 Stage1AirInst *value = instruction->value->child;
2398023980 if (type_is_invalid(value->value->type))
2398123981 return ira->codegen->invalid_inst_gen;
2398223982
2398323983 bool was_written = instruction->result_loc->written;
23984 IrInstGen *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
23984 Stage1AirInst *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
2398523985 value->value->type, value, false, true);
2398623986 if (result_loc != nullptr) {
2398723987 if (type_is_invalid(result_loc->value->type))
......@@ -23990,7 +23990,7 @@ static IrInstGen *ir_analyze_instruction_end_expr(IrAnalyze *ira, IrInstSrcEndEx
2399023990 return result_loc;
2399123991
2399223992 if (!was_written || instruction->result_loc->id == ResultLocIdPeer) {
23993 IrInstGen *store_ptr = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, result_loc, value,
23993 Stage1AirInst *store_ptr = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, result_loc, value,
2399423994 instruction->result_loc->allow_write_through_const);
2399523995 if (type_is_invalid(store_ptr->value->type)) {
2399623996 if (instruction->result_loc->id == ResultLocIdReturn &&
......@@ -24018,8 +24018,8 @@ static IrInstGen *ir_analyze_instruction_end_expr(IrAnalyze *ira, IrInstSrcEndEx
2401824018 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
2401924019}
2402024020
24021static IrInstGen *ir_analyze_instruction_implicit_cast(IrAnalyze *ira, IrInstSrcImplicitCast *instruction) {
24022 IrInstGen *operand = instruction->operand->child;
24021static Stage1AirInst *ir_analyze_instruction_implicit_cast(IrAnalyze *ira, Stage1ZirInstImplicitCast *instruction) {
24022 Stage1AirInst *operand = instruction->operand->child;
2402324023 if (type_is_invalid(operand->value->type))
2402424024 return operand;
2402524025
......@@ -24030,12 +24030,12 @@ static IrInstGen *ir_analyze_instruction_implicit_cast(IrAnalyze *ira, IrInstSrc
2403024030 operand, dest_type);
2403124031}
2403224032
24033static IrInstGen *ir_analyze_instruction_bit_cast_src(IrAnalyze *ira, IrInstSrcBitCast *instruction) {
24034 IrInstGen *operand = instruction->operand->child;
24033static Stage1AirInst *ir_analyze_instruction_bit_cast_src(IrAnalyze *ira, Stage1ZirInstBitCast *instruction) {
24034 Stage1AirInst *operand = instruction->operand->child;
2403524035 if (type_is_invalid(operand->value->type))
2403624036 return operand;
2403724037
24038 IrInstGen *result_loc = ir_resolve_result(ira, &instruction->base,
24038 Stage1AirInst *result_loc = ir_resolve_result(ira, &instruction->base,
2403924039 &instruction->result_loc_bit_cast->base, operand->value->type, operand, false, true);
2404024040 if (result_loc != nullptr &&
2404124041 (type_is_invalid(result_loc->value->type) || result_loc->value->type->id == ZigTypeIdUnreachable))
......@@ -24050,8 +24050,8 @@ static IrInstGen *ir_analyze_instruction_bit_cast_src(IrAnalyze *ira, IrInstSrcB
2405024050 return ir_analyze_bit_cast(ira, instruction->base.scope, instruction->base.source_node, operand, dest_type);
2405124051}
2405224052
24053static IrInstGen *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira,
24054 IrInstSrcUnionInitNamedField *instruction)
24053static Stage1AirInst *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira,
24054 Stage1ZirInstUnionInitNamedField *instruction)
2405524055{
2405624056 ZigType *union_type = ir_resolve_type(ira, instruction->union_type->child);
2405724057 if (type_is_invalid(union_type))
......@@ -24067,11 +24067,11 @@ static IrInstGen *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira,
2406724067 if (field_name == nullptr)
2406824068 return ira->codegen->invalid_inst_gen;
2406924069
24070 IrInstGen *field_result_loc = instruction->field_result_loc->child;
24070 Stage1AirInst *field_result_loc = instruction->field_result_loc->child;
2407124071 if (type_is_invalid(field_result_loc->value->type))
2407224072 return ira->codegen->invalid_inst_gen;
2407324073
24074 IrInstGen *result_loc = instruction->result_loc->child;
24074 Stage1AirInst *result_loc = instruction->result_loc->child;
2407524075 if (type_is_invalid(result_loc->value->type))
2407624076 return ira->codegen->invalid_inst_gen;
2407724077
......@@ -24079,16 +24079,16 @@ static IrInstGen *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira,
2407924079 union_type, field_name, field_result_loc, result_loc);
2408024080}
2408124081
24082static IrInstGen *ir_analyze_instruction_suspend_begin(IrAnalyze *ira, IrInstSrcSuspendBegin *instruction) {
24082static Stage1AirInst *ir_analyze_instruction_suspend_begin(IrAnalyze *ira, Stage1ZirInstSuspendBegin *instruction) {
2408324083 return ir_build_suspend_begin_gen(ira, instruction->base.scope, instruction->base.source_node);
2408424084}
2408524085
24086static IrInstGen *ir_analyze_instruction_suspend_finish(IrAnalyze *ira, IrInstSrcSuspendFinish *instruction) {
24087 IrInstGen *begin_base = instruction->begin->base.child;
24086static Stage1AirInst *ir_analyze_instruction_suspend_finish(IrAnalyze *ira, Stage1ZirInstSuspendFinish *instruction) {
24087 Stage1AirInst *begin_base = instruction->begin->base.child;
2408824088 if (type_is_invalid(begin_base->value->type))
2408924089 return ira->codegen->invalid_inst_gen;
24090 src_assert(begin_base->id == IrInstGenIdSuspendBegin, instruction->base.source_node);
24091 IrInstGenSuspendBegin *begin = reinterpret_cast<IrInstGenSuspendBegin *>(begin_base);
24090 src_assert(begin_base->id == Stage1AirInstIdSuspendBegin, instruction->base.source_node);
24091 Stage1AirInstSuspendBegin *begin = reinterpret_cast<Stage1AirInstSuspendBegin *>(begin_base);
2409224092
2409324093 ZigFn *fn_entry = ira->fn;
2409424094 src_assert(fn_entry != nullptr, instruction->base.source_node);
......@@ -24100,8 +24100,8 @@ static IrInstGen *ir_analyze_instruction_suspend_finish(IrAnalyze *ira, IrInstSr
2410024100 return ir_build_suspend_finish_gen(ira, instruction->base.scope, instruction->base.source_node, begin);
2410124101}
2410224102
24103static IrInstGen *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope, AstNode *source_node,
24104 IrInstGen *frame_ptr, ZigFn **target_fn)
24103static Stage1AirInst *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope, AstNode *source_node,
24104 Stage1AirInst *frame_ptr, ZigFn **target_fn)
2410524105{
2410624106 if (type_is_invalid(frame_ptr->value->type))
2410724107 return ira->codegen->invalid_inst_gen;
......@@ -24109,7 +24109,7 @@ static IrInstGen *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope,
2410924109 *target_fn = nullptr;
2411024110
2411124111 ZigType *result_type;
24112 IrInstGen *frame;
24112 Stage1AirInst *frame;
2411324113 if (frame_ptr->value->type->id == ZigTypeIdPointer &&
2411424114 frame_ptr->value->type->data.pointer.ptr_len == PtrLenSingle &&
2411524115 frame_ptr->value->type->data.pointer.child_type->id == ZigTypeIdFnFrame)
......@@ -24139,19 +24139,19 @@ static IrInstGen *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope,
2413924139 }
2414024140
2414124141 ZigType *any_frame_type = get_any_frame_type(ira->codegen, result_type);
24142 IrInstGen *casted_frame = ir_implicit_cast(ira, frame, any_frame_type);
24142 Stage1AirInst *casted_frame = ir_implicit_cast(ira, frame, any_frame_type);
2414324143 if (type_is_invalid(casted_frame->value->type))
2414424144 return ira->codegen->invalid_inst_gen;
2414524145
2414624146 return casted_frame;
2414724147}
2414824148
24149static IrInstGen *ir_analyze_instruction_await(IrAnalyze *ira, IrInstSrcAwait *instruction) {
24150 IrInstGen *operand = instruction->frame->child;
24149static Stage1AirInst *ir_analyze_instruction_await(IrAnalyze *ira, Stage1ZirInstAwait *instruction) {
24150 Stage1AirInst *operand = instruction->frame->child;
2415124151 if (type_is_invalid(operand->value->type))
2415224152 return ira->codegen->invalid_inst_gen;
2415324153 ZigFn *target_fn;
24154 IrInstGen *frame = analyze_frame_ptr_to_anyframe_T(ira, instruction->base.scope, instruction->base.source_node, operand, &target_fn);
24154 Stage1AirInst *frame = analyze_frame_ptr_to_anyframe_T(ira, instruction->base.scope, instruction->base.source_node, operand, &target_fn);
2415524155 if (type_is_invalid(frame->value->type))
2415624156 return ira->codegen->invalid_inst_gen;
2415724157
......@@ -24171,7 +24171,7 @@ static IrInstGen *ir_analyze_instruction_await(IrAnalyze *ira, IrInstSrcAwait *i
2417124171 fn_entry->calls_or_awaits_errorable_fn = true;
2417224172 }
2417324173
24174 IrInstGen *result_loc;
24174 Stage1AirInst *result_loc;
2417524175 if (type_has_bits(ira->codegen, result_type)) {
2417624176 result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc,
2417724177 result_type, nullptr, true, true);
......@@ -24184,19 +24184,19 @@ static IrInstGen *ir_analyze_instruction_await(IrAnalyze *ira, IrInstSrcAwait *i
2418424184 result_loc = nullptr;
2418524185 }
2418624186
24187 IrInstGenAwait *result = ir_build_await_gen(ira, instruction->base.scope, instruction->base.source_node, frame, result_type, result_loc,
24187 Stage1AirInstAwait *result = ir_build_await_gen(ira, instruction->base.scope, instruction->base.source_node, frame, result_type, result_loc,
2418824188 instruction->is_nosuspend);
2418924189 result->target_fn = target_fn;
2419024190 fn_entry->await_list.append(result);
2419124191 return ir_finish_anal(ira, &result->base);
2419224192}
2419324193
24194static IrInstGen *ir_analyze_instruction_resume(IrAnalyze *ira, IrInstSrcResume *instruction) {
24195 IrInstGen *frame_ptr = instruction->frame->child;
24194static Stage1AirInst *ir_analyze_instruction_resume(IrAnalyze *ira, Stage1ZirInstResume *instruction) {
24195 Stage1AirInst *frame_ptr = instruction->frame->child;
2419624196 if (type_is_invalid(frame_ptr->value->type))
2419724197 return ira->codegen->invalid_inst_gen;
2419824198
24199 IrInstGen *frame;
24199 Stage1AirInst *frame;
2420024200 if (frame_ptr->value->type->id == ZigTypeIdPointer &&
2420124201 frame_ptr->value->type->data.pointer.ptr_len == PtrLenSingle &&
2420224202 frame_ptr->value->type->data.pointer.child_type->id == ZigTypeIdFnFrame)
......@@ -24208,7 +24208,7 @@ static IrInstGen *ir_analyze_instruction_resume(IrAnalyze *ira, IrInstSrcResume
2420824208 }
2420924209
2421024210 ZigType *any_frame_type = get_any_frame_type(ira->codegen, nullptr);
24211 IrInstGen *casted_frame = ir_implicit_cast2(ira, instruction->frame->scope,
24211 Stage1AirInst *casted_frame = ir_implicit_cast2(ira, instruction->frame->scope,
2421224212 instruction->frame->source_node, frame, any_frame_type);
2421324213 if (type_is_invalid(casted_frame->value->type))
2421424214 return ira->codegen->invalid_inst_gen;
......@@ -24216,11 +24216,11 @@ static IrInstGen *ir_analyze_instruction_resume(IrAnalyze *ira, IrInstSrcResume
2421624216 return ir_build_resume_gen(ira, instruction->base.scope, instruction->base.source_node, casted_frame);
2421724217}
2421824218
24219static IrInstGen *ir_analyze_instruction_spill_begin(IrAnalyze *ira, IrInstSrcSpillBegin *instruction) {
24219static Stage1AirInst *ir_analyze_instruction_spill_begin(IrAnalyze *ira, Stage1ZirInstSpillBegin *instruction) {
2422024220 if (ir_should_inline(ira->zir, instruction->base.scope))
2422124221 return ir_const_void(ira, instruction->base.scope, instruction->base.source_node);
2422224222
24223 IrInstGen *operand = instruction->operand->child;
24223 Stage1AirInst *operand = instruction->operand->child;
2422424224 if (type_is_invalid(operand->value->type))
2422524225 return ira->codegen->invalid_inst_gen;
2422624226
......@@ -24238,8 +24238,8 @@ static IrInstGen *ir_analyze_instruction_spill_begin(IrAnalyze *ira, IrInstSrcSp
2423824238 return ir_build_spill_begin_gen(ira, instruction->base.scope, instruction->base.source_node, operand, instruction->spill_id);
2423924239}
2424024240
24241static IrInstGen *ir_analyze_instruction_spill_end(IrAnalyze *ira, IrInstSrcSpillEnd *instruction) {
24242 IrInstGen *operand = instruction->begin->operand->child;
24241static Stage1AirInst *ir_analyze_instruction_spill_end(IrAnalyze *ira, Stage1ZirInstSpillEnd *instruction) {
24242 Stage1AirInst *operand = instruction->begin->operand->child;
2424324243 if (type_is_invalid(operand->value->type))
2424424244 return ira->codegen->invalid_inst_gen;
2424524245
......@@ -24250,13 +24250,13 @@ static IrInstGen *ir_analyze_instruction_spill_end(IrAnalyze *ira, IrInstSrcSpil
2425024250 return operand;
2425124251 }
2425224252
24253 src_assert(instruction->begin->base.child->id == IrInstGenIdSpillBegin, instruction->base.source_node);
24254 IrInstGenSpillBegin *begin = reinterpret_cast<IrInstGenSpillBegin *>(instruction->begin->base.child);
24253 src_assert(instruction->begin->base.child->id == Stage1AirInstIdSpillBegin, instruction->base.source_node);
24254 Stage1AirInstSpillBegin *begin = reinterpret_cast<Stage1AirInstSpillBegin *>(instruction->begin->base.child);
2425524255
2425624256 return ir_build_spill_end_gen(ira, instruction->base.scope, instruction->base.source_node, begin, operand->value->type);
2425724257}
2425824258
24259static IrInstGen *ir_analyze_instruction_src(IrAnalyze *ira, IrInstSrcSrc *instruction) {
24259static Stage1AirInst *ir_analyze_instruction_src(IrAnalyze *ira, Stage1ZirInstSrc *instruction) {
2426024260 ZigFn *fn_entry = scope_fn_entry(instruction->base.scope);
2426124261 if (fn_entry == nullptr) {
2426224262 ir_add_error_node(ira, instruction->base.source_node, buf_sprintf("@src outside function"));
......@@ -24318,289 +24318,289 @@ static IrInstGen *ir_analyze_instruction_src(IrAnalyze *ira, IrInstSrcSrc *instr
2431824318 return ir_const_move(ira, instruction->base.scope, instruction->base.source_node, result);
2431924319}
2432024320
24321static IrInstGen *ir_analyze_instruction_base(IrAnalyze *ira, IrInstSrc *instruction) {
24321static Stage1AirInst *ir_analyze_instruction_base(IrAnalyze *ira, Stage1ZirInst *instruction) {
2432224322 switch (instruction->id) {
24323 case IrInstSrcIdInvalid:
24323 case Stage1ZirInstIdInvalid:
2432424324 zig_unreachable();
2432524325
24326 case IrInstSrcIdReturn:
24327 return ir_analyze_instruction_return(ira, (IrInstSrcReturn *)instruction);
24328 case IrInstSrcIdConst:
24329 return ir_analyze_instruction_const(ira, (IrInstSrcConst *)instruction);
24330 case IrInstSrcIdUnOp:
24331 return ir_analyze_instruction_un_op(ira, (IrInstSrcUnOp *)instruction);
24332 case IrInstSrcIdBinOp:
24333 return ir_analyze_instruction_bin_op(ira, (IrInstSrcBinOp *)instruction);
24334 case IrInstSrcIdMergeErrSets:
24335 return ir_analyze_instruction_merge_err_sets(ira, (IrInstSrcMergeErrSets *)instruction);
24336 case IrInstSrcIdDeclVar:
24337 return ir_analyze_instruction_decl_var(ira, (IrInstSrcDeclVar *)instruction);
24338 case IrInstSrcIdLoadPtr:
24339 return ir_analyze_instruction_load_ptr(ira, (IrInstSrcLoadPtr *)instruction);
24340 case IrInstSrcIdStorePtr:
24341 return ir_analyze_instruction_store_ptr(ira, (IrInstSrcStorePtr *)instruction);
24342 case IrInstSrcIdElemPtr:
24343 return ir_analyze_instruction_elem_ptr(ira, (IrInstSrcElemPtr *)instruction);
24344 case IrInstSrcIdVarPtr:
24345 return ir_analyze_instruction_var_ptr(ira, (IrInstSrcVarPtr *)instruction);
24346 case IrInstSrcIdFieldPtr:
24347 return ir_analyze_instruction_field_ptr(ira, (IrInstSrcFieldPtr *)instruction);
24348 case IrInstSrcIdCall:
24349 return ir_analyze_instruction_call(ira, (IrInstSrcCall *)instruction);
24350 case IrInstSrcIdCallArgs:
24351 return ir_analyze_instruction_call_args(ira, (IrInstSrcCallArgs *)instruction);
24352 case IrInstSrcIdCallExtra:
24353 return ir_analyze_instruction_call_extra(ira, (IrInstSrcCallExtra *)instruction);
24354 case IrInstSrcIdAsyncCallExtra:
24355 return ir_analyze_instruction_async_call_extra(ira, (IrInstSrcAsyncCallExtra *)instruction);
24356 case IrInstSrcIdBr:
24357 return ir_analyze_instruction_br(ira, (IrInstSrcBr *)instruction);
24358 case IrInstSrcIdCondBr:
24359 return ir_analyze_instruction_cond_br(ira, (IrInstSrcCondBr *)instruction);
24360 case IrInstSrcIdUnreachable:
24361 return ir_analyze_instruction_unreachable(ira, (IrInstSrcUnreachable *)instruction);
24362 case IrInstSrcIdPhi:
24363 return ir_analyze_instruction_phi(ira, (IrInstSrcPhi *)instruction);
24364 case IrInstSrcIdTypeOf:
24365 return ir_analyze_instruction_typeof(ira, (IrInstSrcTypeOf *)instruction);
24366 case IrInstSrcIdSetCold:
24367 return ir_analyze_instruction_set_cold(ira, (IrInstSrcSetCold *)instruction);
24368 case IrInstSrcIdSetRuntimeSafety:
24369 return ir_analyze_instruction_set_runtime_safety(ira, (IrInstSrcSetRuntimeSafety *)instruction);
24370 case IrInstSrcIdSetFloatMode:
24371 return ir_analyze_instruction_set_float_mode(ira, (IrInstSrcSetFloatMode *)instruction);
24372 case IrInstSrcIdAnyFrameType:
24373 return ir_analyze_instruction_any_frame_type(ira, (IrInstSrcAnyFrameType *)instruction);
24374 case IrInstSrcIdSliceType:
24375 return ir_analyze_instruction_slice_type(ira, (IrInstSrcSliceType *)instruction);
24376 case IrInstSrcIdAsm:
24377 return ir_analyze_instruction_asm(ira, (IrInstSrcAsm *)instruction);
24378 case IrInstSrcIdArrayType:
24379 return ir_analyze_instruction_array_type(ira, (IrInstSrcArrayType *)instruction);
24380 case IrInstSrcIdSizeOf:
24381 return ir_analyze_instruction_size_of(ira, (IrInstSrcSizeOf *)instruction);
24382 case IrInstSrcIdTestNonNull:
24383 return ir_analyze_instruction_test_non_null(ira, (IrInstSrcTestNonNull *)instruction);
24384 case IrInstSrcIdOptionalUnwrapPtr:
24385 return ir_analyze_instruction_optional_unwrap_ptr(ira, (IrInstSrcOptionalUnwrapPtr *)instruction);
24386 case IrInstSrcIdClz:
24387 return ir_analyze_instruction_clz(ira, (IrInstSrcClz *)instruction);
24388 case IrInstSrcIdCtz:
24389 return ir_analyze_instruction_ctz(ira, (IrInstSrcCtz *)instruction);
24390 case IrInstSrcIdPopCount:
24391 return ir_analyze_instruction_pop_count(ira, (IrInstSrcPopCount *)instruction);
24392 case IrInstSrcIdBswap:
24393 return ir_analyze_instruction_bswap(ira, (IrInstSrcBswap *)instruction);
24394 case IrInstSrcIdBitReverse:
24395 return ir_analyze_instruction_bit_reverse(ira, (IrInstSrcBitReverse *)instruction);
24396 case IrInstSrcIdSwitchBr:
24397 return ir_analyze_instruction_switch_br(ira, (IrInstSrcSwitchBr *)instruction);
24398 case IrInstSrcIdSwitchTarget:
24399 return ir_analyze_instruction_switch_target(ira, (IrInstSrcSwitchTarget *)instruction);
24400 case IrInstSrcIdSwitchVar:
24401 return ir_analyze_instruction_switch_var(ira, (IrInstSrcSwitchVar *)instruction);
24402 case IrInstSrcIdSwitchElseVar:
24403 return ir_analyze_instruction_switch_else_var(ira, (IrInstSrcSwitchElseVar *)instruction);
24404 case IrInstSrcIdImport:
24405 return ir_analyze_instruction_import(ira, (IrInstSrcImport *)instruction);
24406 case IrInstSrcIdRef:
24407 return ir_analyze_instruction_ref(ira, (IrInstSrcRef *)instruction);
24408 case IrInstSrcIdContainerInitList:
24409 return ir_analyze_instruction_container_init_list(ira, (IrInstSrcContainerInitList *)instruction);
24410 case IrInstSrcIdContainerInitFields:
24411 return ir_analyze_instruction_container_init_fields(ira, (IrInstSrcContainerInitFields *)instruction);
24412 case IrInstSrcIdCompileErr:
24413 return ir_analyze_instruction_compile_err(ira, (IrInstSrcCompileErr *)instruction);
24414 case IrInstSrcIdCompileLog:
24415 return ir_analyze_instruction_compile_log(ira, (IrInstSrcCompileLog *)instruction);
24416 case IrInstSrcIdErrName:
24417 return ir_analyze_instruction_err_name(ira, (IrInstSrcErrName *)instruction);
24418 case IrInstSrcIdTypeName:
24419 return ir_analyze_instruction_type_name(ira, (IrInstSrcTypeName *)instruction);
24420 case IrInstSrcIdCImport:
24421 return ir_analyze_instruction_c_import(ira, (IrInstSrcCImport *)instruction);
24422 case IrInstSrcIdCInclude:
24423 return ir_analyze_instruction_c_include(ira, (IrInstSrcCInclude *)instruction);
24424 case IrInstSrcIdCDefine:
24425 return ir_analyze_instruction_c_define(ira, (IrInstSrcCDefine *)instruction);
24426 case IrInstSrcIdCUndef:
24427 return ir_analyze_instruction_c_undef(ira, (IrInstSrcCUndef *)instruction);
24428 case IrInstSrcIdEmbedFile:
24429 return ir_analyze_instruction_embed_file(ira, (IrInstSrcEmbedFile *)instruction);
24430 case IrInstSrcIdCmpxchg:
24431 return ir_analyze_instruction_cmpxchg(ira, (IrInstSrcCmpxchg *)instruction);
24432 case IrInstSrcIdFence:
24433 return ir_analyze_instruction_fence(ira, (IrInstSrcFence *)instruction);
24434 case IrInstSrcIdReduce:
24435 return ir_analyze_instruction_reduce(ira, (IrInstSrcReduce *)instruction);
24436 case IrInstSrcIdTruncate:
24437 return ir_analyze_instruction_truncate(ira, (IrInstSrcTruncate *)instruction);
24438 case IrInstSrcIdIntCast:
24439 return ir_analyze_instruction_int_cast(ira, (IrInstSrcIntCast *)instruction);
24440 case IrInstSrcIdFloatCast:
24441 return ir_analyze_instruction_float_cast(ira, (IrInstSrcFloatCast *)instruction);
24442 case IrInstSrcIdErrSetCast:
24443 return ir_analyze_instruction_err_set_cast(ira, (IrInstSrcErrSetCast *)instruction);
24444 case IrInstSrcIdIntToFloat:
24445 return ir_analyze_instruction_int_to_float(ira, (IrInstSrcIntToFloat *)instruction);
24446 case IrInstSrcIdFloatToInt:
24447 return ir_analyze_instruction_float_to_int(ira, (IrInstSrcFloatToInt *)instruction);
24448 case IrInstSrcIdBoolToInt:
24449 return ir_analyze_instruction_bool_to_int(ira, (IrInstSrcBoolToInt *)instruction);
24450 case IrInstSrcIdVectorType:
24451 return ir_analyze_instruction_vector_type(ira, (IrInstSrcVectorType *)instruction);
24452 case IrInstSrcIdShuffleVector:
24453 return ir_analyze_instruction_shuffle_vector(ira, (IrInstSrcShuffleVector *)instruction);
24454 case IrInstSrcIdSplat:
24455 return ir_analyze_instruction_splat(ira, (IrInstSrcSplat *)instruction);
24456 case IrInstSrcIdBoolNot:
24457 return ir_analyze_instruction_bool_not(ira, (IrInstSrcBoolNot *)instruction);
24458 case IrInstSrcIdMemset:
24459 return ir_analyze_instruction_memset(ira, (IrInstSrcMemset *)instruction);
24460 case IrInstSrcIdMemcpy:
24461 return ir_analyze_instruction_memcpy(ira, (IrInstSrcMemcpy *)instruction);
24462 case IrInstSrcIdSlice:
24463 return ir_analyze_instruction_slice(ira, (IrInstSrcSlice *)instruction);
24464 case IrInstSrcIdBreakpoint:
24465 return ir_analyze_instruction_breakpoint(ira, (IrInstSrcBreakpoint *)instruction);
24466 case IrInstSrcIdReturnAddress:
24467 return ir_analyze_instruction_return_address(ira, (IrInstSrcReturnAddress *)instruction);
24468 case IrInstSrcIdFrameAddress:
24469 return ir_analyze_instruction_frame_address(ira, (IrInstSrcFrameAddress *)instruction);
24470 case IrInstSrcIdFrameHandle:
24471 return ir_analyze_instruction_frame_handle(ira, (IrInstSrcFrameHandle *)instruction);
24472 case IrInstSrcIdFrameType:
24473 return ir_analyze_instruction_frame_type(ira, (IrInstSrcFrameType *)instruction);
24474 case IrInstSrcIdFrameSize:
24475 return ir_analyze_instruction_frame_size(ira, (IrInstSrcFrameSize *)instruction);
24476 case IrInstSrcIdAlignOf:
24477 return ir_analyze_instruction_align_of(ira, (IrInstSrcAlignOf *)instruction);
24478 case IrInstSrcIdOverflowOp:
24479 return ir_analyze_instruction_overflow_op(ira, (IrInstSrcOverflowOp *)instruction);
24480 case IrInstSrcIdTestErr:
24481 return ir_analyze_instruction_test_err(ira, (IrInstSrcTestErr *)instruction);
24482 case IrInstSrcIdUnwrapErrCode:
24483 return ir_analyze_instruction_unwrap_err_code(ira, (IrInstSrcUnwrapErrCode *)instruction);
24484 case IrInstSrcIdUnwrapErrPayload:
24485 return ir_analyze_instruction_unwrap_err_payload(ira, (IrInstSrcUnwrapErrPayload *)instruction);
24486 case IrInstSrcIdFnProto:
24487 return ir_analyze_instruction_fn_proto(ira, (IrInstSrcFnProto *)instruction);
24488 case IrInstSrcIdTestComptime:
24489 return ir_analyze_instruction_test_comptime(ira, (IrInstSrcTestComptime *)instruction);
24490 case IrInstSrcIdCheckSwitchProngsUnderNo:
24491 return ir_analyze_instruction_check_switch_prongs(ira, (IrInstSrcCheckSwitchProngs *)instruction, false);
24492 case IrInstSrcIdCheckSwitchProngsUnderYes:
24493 return ir_analyze_instruction_check_switch_prongs(ira, (IrInstSrcCheckSwitchProngs *)instruction, true);
24494 case IrInstSrcIdCheckStatementIsVoid:
24495 return ir_analyze_instruction_check_statement_is_void(ira, (IrInstSrcCheckStatementIsVoid *)instruction);
24496 case IrInstSrcIdDeclRef:
24497 return ir_analyze_instruction_decl_ref(ira, (IrInstSrcDeclRef *)instruction);
24498 case IrInstSrcIdPanic:
24499 return ir_analyze_instruction_panic(ira, (IrInstSrcPanic *)instruction);
24500 case IrInstSrcIdPtrCast:
24501 return ir_analyze_instruction_ptr_cast(ira, (IrInstSrcPtrCast *)instruction);
24502 case IrInstSrcIdIntToPtr:
24503 return ir_analyze_instruction_int_to_ptr(ira, (IrInstSrcIntToPtr *)instruction);
24504 case IrInstSrcIdPtrToInt:
24505 return ir_analyze_instruction_ptr_to_int(ira, (IrInstSrcPtrToInt *)instruction);
24506 case IrInstSrcIdTagName:
24507 return ir_analyze_instruction_enum_tag_name(ira, (IrInstSrcTagName *)instruction);
24508 case IrInstSrcIdFieldParentPtr:
24509 return ir_analyze_instruction_field_parent_ptr(ira, (IrInstSrcFieldParentPtr *)instruction);
24510 case IrInstSrcIdOffsetOf:
24511 return ir_analyze_instruction_offset_of(ira, (IrInstSrcOffsetOf *)instruction);
24512 case IrInstSrcIdBitOffsetOf:
24513 return ir_analyze_instruction_bit_offset_of(ira, (IrInstSrcBitOffsetOf *)instruction);
24514 case IrInstSrcIdTypeInfo:
24515 return ir_analyze_instruction_type_info(ira, (IrInstSrcTypeInfo *) instruction);
24516 case IrInstSrcIdType:
24517 return ir_analyze_instruction_type(ira, (IrInstSrcType *)instruction);
24518 case IrInstSrcIdHasField:
24519 return ir_analyze_instruction_has_field(ira, (IrInstSrcHasField *) instruction);
24520 case IrInstSrcIdSetEvalBranchQuota:
24521 return ir_analyze_instruction_set_eval_branch_quota(ira, (IrInstSrcSetEvalBranchQuota *)instruction);
24522 case IrInstSrcIdPtrType:
24523 return ir_analyze_instruction_ptr_type(ira, (IrInstSrcPtrType *)instruction);
24524 case IrInstSrcIdPtrTypeSimple:
24525 return ir_analyze_instruction_ptr_type_simple(ira, (IrInstSrcPtrTypeSimple *)instruction, false);
24526 case IrInstSrcIdPtrTypeSimpleConst:
24527 return ir_analyze_instruction_ptr_type_simple(ira, (IrInstSrcPtrTypeSimple *)instruction, true);
24528 case IrInstSrcIdAlignCast:
24529 return ir_analyze_instruction_align_cast(ira, (IrInstSrcAlignCast *)instruction);
24530 case IrInstSrcIdImplicitCast:
24531 return ir_analyze_instruction_implicit_cast(ira, (IrInstSrcImplicitCast *)instruction);
24532 case IrInstSrcIdResolveResult:
24533 return ir_analyze_instruction_resolve_result(ira, (IrInstSrcResolveResult *)instruction);
24534 case IrInstSrcIdResetResult:
24535 return ir_analyze_instruction_reset_result(ira, (IrInstSrcResetResult *)instruction);
24536 case IrInstSrcIdSetAlignStack:
24537 return ir_analyze_instruction_set_align_stack(ira, (IrInstSrcSetAlignStack *)instruction);
24538 case IrInstSrcIdArgTypeAllowVarFalse:
24539 return ir_analyze_instruction_arg_type(ira, (IrInstSrcArgType *)instruction, false);
24540 case IrInstSrcIdArgTypeAllowVarTrue:
24541 return ir_analyze_instruction_arg_type(ira, (IrInstSrcArgType *)instruction, true);
24542 case IrInstSrcIdExport:
24543 return ir_analyze_instruction_export(ira, (IrInstSrcExport *)instruction);
24544 case IrInstSrcIdExtern:
24545 return ir_analyze_instruction_extern(ira, (IrInstSrcExtern *)instruction);
24546 case IrInstSrcIdErrorReturnTrace:
24547 return ir_analyze_instruction_error_return_trace(ira, (IrInstSrcErrorReturnTrace *)instruction);
24548 case IrInstSrcIdErrorUnion:
24549 return ir_analyze_instruction_error_union(ira, (IrInstSrcErrorUnion *)instruction);
24550 case IrInstSrcIdAtomicRmw:
24551 return ir_analyze_instruction_atomic_rmw(ira, (IrInstSrcAtomicRmw *)instruction);
24552 case IrInstSrcIdAtomicLoad:
24553 return ir_analyze_instruction_atomic_load(ira, (IrInstSrcAtomicLoad *)instruction);
24554 case IrInstSrcIdAtomicStore:
24555 return ir_analyze_instruction_atomic_store(ira, (IrInstSrcAtomicStore *)instruction);
24556 case IrInstSrcIdSaveErrRetAddr:
24557 return ir_analyze_instruction_save_err_ret_addr(ira, (IrInstSrcSaveErrRetAddr *)instruction);
24558 case IrInstSrcIdAddImplicitReturnType:
24559 return ir_analyze_instruction_add_implicit_return_type(ira, (IrInstSrcAddImplicitReturnType *)instruction);
24560 case IrInstSrcIdFloatOp:
24561 return ir_analyze_instruction_float_op(ira, (IrInstSrcFloatOp *)instruction);
24562 case IrInstSrcIdMulAdd:
24563 return ir_analyze_instruction_mul_add(ira, (IrInstSrcMulAdd *)instruction);
24564 case IrInstSrcIdIntToErr:
24565 return ir_analyze_instruction_int_to_err(ira, (IrInstSrcIntToErr *)instruction);
24566 case IrInstSrcIdErrToInt:
24567 return ir_analyze_instruction_err_to_int(ira, (IrInstSrcErrToInt *)instruction);
24568 case IrInstSrcIdIntToEnum:
24569 return ir_analyze_instruction_int_to_enum(ira, (IrInstSrcIntToEnum *)instruction);
24570 case IrInstSrcIdEnumToInt:
24571 return ir_analyze_instruction_enum_to_int(ira, (IrInstSrcEnumToInt *)instruction);
24572 case IrInstSrcIdCheckRuntimeScope:
24573 return ir_analyze_instruction_check_runtime_scope(ira, (IrInstSrcCheckRuntimeScope *)instruction);
24574 case IrInstSrcIdHasDecl:
24575 return ir_analyze_instruction_has_decl(ira, (IrInstSrcHasDecl *)instruction);
24576 case IrInstSrcIdUndeclaredIdent:
24577 return ir_analyze_instruction_undeclared_ident(ira, (IrInstSrcUndeclaredIdent *)instruction);
24578 case IrInstSrcIdAlloca:
24326 case Stage1ZirInstIdReturn:
24327 return ir_analyze_instruction_return(ira, (Stage1ZirInstReturn *)instruction);
24328 case Stage1ZirInstIdConst:
24329 return ir_analyze_instruction_const(ira, (Stage1ZirInstConst *)instruction);
24330 case Stage1ZirInstIdUnOp:
24331 return ir_analyze_instruction_un_op(ira, (Stage1ZirInstUnOp *)instruction);
24332 case Stage1ZirInstIdBinOp:
24333 return ir_analyze_instruction_bin_op(ira, (Stage1ZirInstBinOp *)instruction);
24334 case Stage1ZirInstIdMergeErrSets:
24335 return ir_analyze_instruction_merge_err_sets(ira, (Stage1ZirInstMergeErrSets *)instruction);
24336 case Stage1ZirInstIdDeclVar:
24337 return ir_analyze_instruction_decl_var(ira, (Stage1ZirInstDeclVar *)instruction);
24338 case Stage1ZirInstIdLoadPtr:
24339 return ir_analyze_instruction_load_ptr(ira, (Stage1ZirInstLoadPtr *)instruction);
24340 case Stage1ZirInstIdStorePtr:
24341 return ir_analyze_instruction_store_ptr(ira, (Stage1ZirInstStorePtr *)instruction);
24342 case Stage1ZirInstIdElemPtr:
24343 return ir_analyze_instruction_elem_ptr(ira, (Stage1ZirInstElemPtr *)instruction);
24344 case Stage1ZirInstIdVarPtr:
24345 return ir_analyze_instruction_var_ptr(ira, (Stage1ZirInstVarPtr *)instruction);
24346 case Stage1ZirInstIdFieldPtr:
24347 return ir_analyze_instruction_field_ptr(ira, (Stage1ZirInstFieldPtr *)instruction);
24348 case Stage1ZirInstIdCall:
24349 return ir_analyze_instruction_call(ira, (Stage1ZirInstCall *)instruction);
24350 case Stage1ZirInstIdCallArgs:
24351 return ir_analyze_instruction_call_args(ira, (Stage1ZirInstCallArgs *)instruction);
24352 case Stage1ZirInstIdCallExtra:
24353 return ir_analyze_instruction_call_extra(ira, (Stage1ZirInstCallExtra *)instruction);
24354 case Stage1ZirInstIdAsyncCallExtra:
24355 return ir_analyze_instruction_async_call_extra(ira, (Stage1ZirInstAsyncCallExtra *)instruction);
24356 case Stage1ZirInstIdBr:
24357 return ir_analyze_instruction_br(ira, (Stage1ZirInstBr *)instruction);
24358 case Stage1ZirInstIdCondBr:
24359 return ir_analyze_instruction_cond_br(ira, (Stage1ZirInstCondBr *)instruction);
24360 case Stage1ZirInstIdUnreachable:
24361 return ir_analyze_instruction_unreachable(ira, (Stage1ZirInstUnreachable *)instruction);
24362 case Stage1ZirInstIdPhi:
24363 return ir_analyze_instruction_phi(ira, (Stage1ZirInstPhi *)instruction);
24364 case Stage1ZirInstIdTypeOf:
24365 return ir_analyze_instruction_typeof(ira, (Stage1ZirInstTypeOf *)instruction);
24366 case Stage1ZirInstIdSetCold:
24367 return ir_analyze_instruction_set_cold(ira, (Stage1ZirInstSetCold *)instruction);
24368 case Stage1ZirInstIdSetRuntimeSafety:
24369 return ir_analyze_instruction_set_runtime_safety(ira, (Stage1ZirInstSetRuntimeSafety *)instruction);
24370 case Stage1ZirInstIdSetFloatMode:
24371 return ir_analyze_instruction_set_float_mode(ira, (Stage1ZirInstSetFloatMode *)instruction);
24372 case Stage1ZirInstIdAnyFrameType:
24373 return ir_analyze_instruction_any_frame_type(ira, (Stage1ZirInstAnyFrameType *)instruction);
24374 case Stage1ZirInstIdSliceType:
24375 return ir_analyze_instruction_slice_type(ira, (Stage1ZirInstSliceType *)instruction);
24376 case Stage1ZirInstIdAsm:
24377 return ir_analyze_instruction_asm(ira, (Stage1ZirInstAsm *)instruction);
24378 case Stage1ZirInstIdArrayType:
24379 return ir_analyze_instruction_array_type(ira, (Stage1ZirInstArrayType *)instruction);
24380 case Stage1ZirInstIdSizeOf:
24381 return ir_analyze_instruction_size_of(ira, (Stage1ZirInstSizeOf *)instruction);
24382 case Stage1ZirInstIdTestNonNull:
24383 return ir_analyze_instruction_test_non_null(ira, (Stage1ZirInstTestNonNull *)instruction);
24384 case Stage1ZirInstIdOptionalUnwrapPtr:
24385 return ir_analyze_instruction_optional_unwrap_ptr(ira, (Stage1ZirInstOptionalUnwrapPtr *)instruction);
24386 case Stage1ZirInstIdClz:
24387 return ir_analyze_instruction_clz(ira, (Stage1ZirInstClz *)instruction);
24388 case Stage1ZirInstIdCtz:
24389 return ir_analyze_instruction_ctz(ira, (Stage1ZirInstCtz *)instruction);
24390 case Stage1ZirInstIdPopCount:
24391 return ir_analyze_instruction_pop_count(ira, (Stage1ZirInstPopCount *)instruction);
24392 case Stage1ZirInstIdBswap:
24393 return ir_analyze_instruction_bswap(ira, (Stage1ZirInstBswap *)instruction);
24394 case Stage1ZirInstIdBitReverse:
24395 return ir_analyze_instruction_bit_reverse(ira, (Stage1ZirInstBitReverse *)instruction);
24396 case Stage1ZirInstIdSwitchBr:
24397 return ir_analyze_instruction_switch_br(ira, (Stage1ZirInstSwitchBr *)instruction);
24398 case Stage1ZirInstIdSwitchTarget:
24399 return ir_analyze_instruction_switch_target(ira, (Stage1ZirInstSwitchTarget *)instruction);
24400 case Stage1ZirInstIdSwitchVar:
24401 return ir_analyze_instruction_switch_var(ira, (Stage1ZirInstSwitchVar *)instruction);
24402 case Stage1ZirInstIdSwitchElseVar:
24403 return ir_analyze_instruction_switch_else_var(ira, (Stage1ZirInstSwitchElseVar *)instruction);
24404 case Stage1ZirInstIdImport:
24405 return ir_analyze_instruction_import(ira, (Stage1ZirInstImport *)instruction);
24406 case Stage1ZirInstIdRef:
24407 return ir_analyze_instruction_ref(ira, (Stage1ZirInstRef *)instruction);
24408 case Stage1ZirInstIdContainerInitList:
24409 return ir_analyze_instruction_container_init_list(ira, (Stage1ZirInstContainerInitList *)instruction);
24410 case Stage1ZirInstIdContainerInitFields:
24411 return ir_analyze_instruction_container_init_fields(ira, (Stage1ZirInstContainerInitFields *)instruction);
24412 case Stage1ZirInstIdCompileErr:
24413 return ir_analyze_instruction_compile_err(ira, (Stage1ZirInstCompileErr *)instruction);
24414 case Stage1ZirInstIdCompileLog:
24415 return ir_analyze_instruction_compile_log(ira, (Stage1ZirInstCompileLog *)instruction);
24416 case Stage1ZirInstIdErrName:
24417 return ir_analyze_instruction_err_name(ira, (Stage1ZirInstErrName *)instruction);
24418 case Stage1ZirInstIdTypeName:
24419 return ir_analyze_instruction_type_name(ira, (Stage1ZirInstTypeName *)instruction);
24420 case Stage1ZirInstIdCImport:
24421 return ir_analyze_instruction_c_import(ira, (Stage1ZirInstCImport *)instruction);
24422 case Stage1ZirInstIdCInclude:
24423 return ir_analyze_instruction_c_include(ira, (Stage1ZirInstCInclude *)instruction);
24424 case Stage1ZirInstIdCDefine:
24425 return ir_analyze_instruction_c_define(ira, (Stage1ZirInstCDefine *)instruction);
24426 case Stage1ZirInstIdCUndef:
24427 return ir_analyze_instruction_c_undef(ira, (Stage1ZirInstCUndef *)instruction);
24428 case Stage1ZirInstIdEmbedFile:
24429 return ir_analyze_instruction_embed_file(ira, (Stage1ZirInstEmbedFile *)instruction);
24430 case Stage1ZirInstIdCmpxchg:
24431 return ir_analyze_instruction_cmpxchg(ira, (Stage1ZirInstCmpxchg *)instruction);
24432 case Stage1ZirInstIdFence:
24433 return ir_analyze_instruction_fence(ira, (Stage1ZirInstFence *)instruction);
24434 case Stage1ZirInstIdReduce:
24435 return ir_analyze_instruction_reduce(ira, (Stage1ZirInstReduce *)instruction);
24436 case Stage1ZirInstIdTruncate:
24437 return ir_analyze_instruction_truncate(ira, (Stage1ZirInstTruncate *)instruction);
24438 case Stage1ZirInstIdIntCast:
24439 return ir_analyze_instruction_int_cast(ira, (Stage1ZirInstIntCast *)instruction);
24440 case Stage1ZirInstIdFloatCast:
24441 return ir_analyze_instruction_float_cast(ira, (Stage1ZirInstFloatCast *)instruction);
24442 case Stage1ZirInstIdErrSetCast:
24443 return ir_analyze_instruction_err_set_cast(ira, (Stage1ZirInstErrSetCast *)instruction);
24444 case Stage1ZirInstIdIntToFloat:
24445 return ir_analyze_instruction_int_to_float(ira, (Stage1ZirInstIntToFloat *)instruction);
24446 case Stage1ZirInstIdFloatToInt:
24447 return ir_analyze_instruction_float_to_int(ira, (Stage1ZirInstFloatToInt *)instruction);
24448 case Stage1ZirInstIdBoolToInt:
24449 return ir_analyze_instruction_bool_to_int(ira, (Stage1ZirInstBoolToInt *)instruction);
24450 case Stage1ZirInstIdVectorType:
24451 return ir_analyze_instruction_vector_type(ira, (Stage1ZirInstVectorType *)instruction);
24452 case Stage1ZirInstIdShuffleVector:
24453 return ir_analyze_instruction_shuffle_vector(ira, (Stage1ZirInstShuffleVector *)instruction);
24454 case Stage1ZirInstIdSplat:
24455 return ir_analyze_instruction_splat(ira, (Stage1ZirInstSplat *)instruction);
24456 case Stage1ZirInstIdBoolNot:
24457 return ir_analyze_instruction_bool_not(ira, (Stage1ZirInstBoolNot *)instruction);
24458 case Stage1ZirInstIdMemset:
24459 return ir_analyze_instruction_memset(ira, (Stage1ZirInstMemset *)instruction);
24460 case Stage1ZirInstIdMemcpy:
24461 return ir_analyze_instruction_memcpy(ira, (Stage1ZirInstMemcpy *)instruction);
24462 case Stage1ZirInstIdSlice:
24463 return ir_analyze_instruction_slice(ira, (Stage1ZirInstSlice *)instruction);
24464 case Stage1ZirInstIdBreakpoint:
24465 return ir_analyze_instruction_breakpoint(ira, (Stage1ZirInstBreakpoint *)instruction);
24466 case Stage1ZirInstIdReturnAddress:
24467 return ir_analyze_instruction_return_address(ira, (Stage1ZirInstReturnAddress *)instruction);
24468 case Stage1ZirInstIdFrameAddress:
24469 return ir_analyze_instruction_frame_address(ira, (Stage1ZirInstFrameAddress *)instruction);
24470 case Stage1ZirInstIdFrameHandle:
24471 return ir_analyze_instruction_frame_handle(ira, (Stage1ZirInstFrameHandle *)instruction);
24472 case Stage1ZirInstIdFrameType:
24473 return ir_analyze_instruction_frame_type(ira, (Stage1ZirInstFrameType *)instruction);
24474 case Stage1ZirInstIdFrameSize:
24475 return ir_analyze_instruction_frame_size(ira, (Stage1ZirInstFrameSize *)instruction);
24476 case Stage1ZirInstIdAlignOf:
24477 return ir_analyze_instruction_align_of(ira, (Stage1ZirInstAlignOf *)instruction);
24478 case Stage1ZirInstIdOverflowOp:
24479 return ir_analyze_instruction_overflow_op(ira, (Stage1ZirInstOverflowOp *)instruction);
24480 case Stage1ZirInstIdTestErr:
24481 return ir_analyze_instruction_test_err(ira, (Stage1ZirInstTestErr *)instruction);
24482 case Stage1ZirInstIdUnwrapErrCode:
24483 return ir_analyze_instruction_unwrap_err_code(ira, (Stage1ZirInstUnwrapErrCode *)instruction);
24484 case Stage1ZirInstIdUnwrapErrPayload:
24485 return ir_analyze_instruction_unwrap_err_payload(ira, (Stage1ZirInstUnwrapErrPayload *)instruction);
24486 case Stage1ZirInstIdFnProto:
24487 return ir_analyze_instruction_fn_proto(ira, (Stage1ZirInstFnProto *)instruction);
24488 case Stage1ZirInstIdTestComptime:
24489 return ir_analyze_instruction_test_comptime(ira, (Stage1ZirInstTestComptime *)instruction);
24490 case Stage1ZirInstIdCheckSwitchProngsUnderNo:
24491 return ir_analyze_instruction_check_switch_prongs(ira, (Stage1ZirInstCheckSwitchProngs *)instruction, false);
24492 case Stage1ZirInstIdCheckSwitchProngsUnderYes:
24493 return ir_analyze_instruction_check_switch_prongs(ira, (Stage1ZirInstCheckSwitchProngs *)instruction, true);
24494 case Stage1ZirInstIdCheckStatementIsVoid:
24495 return ir_analyze_instruction_check_statement_is_void(ira, (Stage1ZirInstCheckStatementIsVoid *)instruction);
24496 case Stage1ZirInstIdDeclRef:
24497 return ir_analyze_instruction_decl_ref(ira, (Stage1ZirInstDeclRef *)instruction);
24498 case Stage1ZirInstIdPanic:
24499 return ir_analyze_instruction_panic(ira, (Stage1ZirInstPanic *)instruction);
24500 case Stage1ZirInstIdPtrCast:
24501 return ir_analyze_instruction_ptr_cast(ira, (Stage1ZirInstPtrCast *)instruction);
24502 case Stage1ZirInstIdIntToPtr:
24503 return ir_analyze_instruction_int_to_ptr(ira, (Stage1ZirInstIntToPtr *)instruction);
24504 case Stage1ZirInstIdPtrToInt:
24505 return ir_analyze_instruction_ptr_to_int(ira, (Stage1ZirInstPtrToInt *)instruction);
24506 case Stage1ZirInstIdTagName:
24507 return ir_analyze_instruction_enum_tag_name(ira, (Stage1ZirInstTagName *)instruction);
24508 case Stage1ZirInstIdFieldParentPtr:
24509 return ir_analyze_instruction_field_parent_ptr(ira, (Stage1ZirInstFieldParentPtr *)instruction);
24510 case Stage1ZirInstIdOffsetOf:
24511 return ir_analyze_instruction_offset_of(ira, (Stage1ZirInstOffsetOf *)instruction);
24512 case Stage1ZirInstIdBitOffsetOf:
24513 return ir_analyze_instruction_bit_offset_of(ira, (Stage1ZirInstBitOffsetOf *)instruction);
24514 case Stage1ZirInstIdTypeInfo:
24515 return ir_analyze_instruction_type_info(ira, (Stage1ZirInstTypeInfo *) instruction);
24516 case Stage1ZirInstIdType:
24517 return ir_analyze_instruction_type(ira, (Stage1ZirInstType *)instruction);
24518 case Stage1ZirInstIdHasField:
24519 return ir_analyze_instruction_has_field(ira, (Stage1ZirInstHasField *) instruction);
24520 case Stage1ZirInstIdSetEvalBranchQuota:
24521 return ir_analyze_instruction_set_eval_branch_quota(ira, (Stage1ZirInstSetEvalBranchQuota *)instruction);
24522 case Stage1ZirInstIdPtrType:
24523 return ir_analyze_instruction_ptr_type(ira, (Stage1ZirInstPtrType *)instruction);
24524 case Stage1ZirInstIdPtrTypeSimple:
24525 return ir_analyze_instruction_ptr_type_simple(ira, (Stage1ZirInstPtrTypeSimple *)instruction, false);
24526 case Stage1ZirInstIdPtrTypeSimpleConst:
24527 return ir_analyze_instruction_ptr_type_simple(ira, (Stage1ZirInstPtrTypeSimple *)instruction, true);
24528 case Stage1ZirInstIdAlignCast:
24529 return ir_analyze_instruction_align_cast(ira, (Stage1ZirInstAlignCast *)instruction);
24530 case Stage1ZirInstIdImplicitCast:
24531 return ir_analyze_instruction_implicit_cast(ira, (Stage1ZirInstImplicitCast *)instruction);
24532 case Stage1ZirInstIdResolveResult:
24533 return ir_analyze_instruction_resolve_result(ira, (Stage1ZirInstResolveResult *)instruction);
24534 case Stage1ZirInstIdResetResult:
24535 return ir_analyze_instruction_reset_result(ira, (Stage1ZirInstResetResult *)instruction);
24536 case Stage1ZirInstIdSetAlignStack:
24537 return ir_analyze_instruction_set_align_stack(ira, (Stage1ZirInstSetAlignStack *)instruction);
24538 case Stage1ZirInstIdArgTypeAllowVarFalse:
24539 return ir_analyze_instruction_arg_type(ira, (Stage1ZirInstArgType *)instruction, false);
24540 case Stage1ZirInstIdArgTypeAllowVarTrue:
24541 return ir_analyze_instruction_arg_type(ira, (Stage1ZirInstArgType *)instruction, true);
24542 case Stage1ZirInstIdExport:
24543 return ir_analyze_instruction_export(ira, (Stage1ZirInstExport *)instruction);
24544 case Stage1ZirInstIdExtern:
24545 return ir_analyze_instruction_extern(ira, (Stage1ZirInstExtern *)instruction);
24546 case Stage1ZirInstIdErrorReturnTrace:
24547 return ir_analyze_instruction_error_return_trace(ira, (Stage1ZirInstErrorReturnTrace *)instruction);
24548 case Stage1ZirInstIdErrorUnion:
24549 return ir_analyze_instruction_error_union(ira, (Stage1ZirInstErrorUnion *)instruction);
24550 case Stage1ZirInstIdAtomicRmw:
24551 return ir_analyze_instruction_atomic_rmw(ira, (Stage1ZirInstAtomicRmw *)instruction);
24552 case Stage1ZirInstIdAtomicLoad:
24553 return ir_analyze_instruction_atomic_load(ira, (Stage1ZirInstAtomicLoad *)instruction);
24554 case Stage1ZirInstIdAtomicStore:
24555 return ir_analyze_instruction_atomic_store(ira, (Stage1ZirInstAtomicStore *)instruction);
24556 case Stage1ZirInstIdSaveErrRetAddr:
24557 return ir_analyze_instruction_save_err_ret_addr(ira, (Stage1ZirInstSaveErrRetAddr *)instruction);
24558 case Stage1ZirInstIdAddImplicitReturnType:
24559 return ir_analyze_instruction_add_implicit_return_type(ira, (Stage1ZirInstAddImplicitReturnType *)instruction);
24560 case Stage1ZirInstIdFloatOp:
24561 return ir_analyze_instruction_float_op(ira, (Stage1ZirInstFloatOp *)instruction);
24562 case Stage1ZirInstIdMulAdd:
24563 return ir_analyze_instruction_mul_add(ira, (Stage1ZirInstMulAdd *)instruction);
24564 case Stage1ZirInstIdIntToErr:
24565 return ir_analyze_instruction_int_to_err(ira, (Stage1ZirInstIntToErr *)instruction);
24566 case Stage1ZirInstIdErrToInt:
24567 return ir_analyze_instruction_err_to_int(ira, (Stage1ZirInstErrToInt *)instruction);
24568 case Stage1ZirInstIdIntToEnum:
24569 return ir_analyze_instruction_int_to_enum(ira, (Stage1ZirInstIntToEnum *)instruction);
24570 case Stage1ZirInstIdEnumToInt:
24571 return ir_analyze_instruction_enum_to_int(ira, (Stage1ZirInstEnumToInt *)instruction);
24572 case Stage1ZirInstIdCheckRuntimeScope:
24573 return ir_analyze_instruction_check_runtime_scope(ira, (Stage1ZirInstCheckRuntimeScope *)instruction);
24574 case Stage1ZirInstIdHasDecl:
24575 return ir_analyze_instruction_has_decl(ira, (Stage1ZirInstHasDecl *)instruction);
24576 case Stage1ZirInstIdUndeclaredIdent:
24577 return ir_analyze_instruction_undeclared_ident(ira, (Stage1ZirInstUndeclaredIdent *)instruction);
24578 case Stage1ZirInstIdAlloca:
2457924579 return nullptr;
24580 case IrInstSrcIdEndExpr:
24581 return ir_analyze_instruction_end_expr(ira, (IrInstSrcEndExpr *)instruction);
24582 case IrInstSrcIdBitCast:
24583 return ir_analyze_instruction_bit_cast_src(ira, (IrInstSrcBitCast *)instruction);
24584 case IrInstSrcIdUnionInitNamedField:
24585 return ir_analyze_instruction_union_init_named_field(ira, (IrInstSrcUnionInitNamedField *)instruction);
24586 case IrInstSrcIdSuspendBegin:
24587 return ir_analyze_instruction_suspend_begin(ira, (IrInstSrcSuspendBegin *)instruction);
24588 case IrInstSrcIdSuspendFinish:
24589 return ir_analyze_instruction_suspend_finish(ira, (IrInstSrcSuspendFinish *)instruction);
24590 case IrInstSrcIdResume:
24591 return ir_analyze_instruction_resume(ira, (IrInstSrcResume *)instruction);
24592 case IrInstSrcIdAwait:
24593 return ir_analyze_instruction_await(ira, (IrInstSrcAwait *)instruction);
24594 case IrInstSrcIdSpillBegin:
24595 return ir_analyze_instruction_spill_begin(ira, (IrInstSrcSpillBegin *)instruction);
24596 case IrInstSrcIdSpillEnd:
24597 return ir_analyze_instruction_spill_end(ira, (IrInstSrcSpillEnd *)instruction);
24598 case IrInstSrcIdWasmMemorySize:
24599 return ir_analyze_instruction_wasm_memory_size(ira, (IrInstSrcWasmMemorySize *)instruction);
24600 case IrInstSrcIdWasmMemoryGrow:
24601 return ir_analyze_instruction_wasm_memory_grow(ira, (IrInstSrcWasmMemoryGrow *)instruction);
24602 case IrInstSrcIdSrc:
24603 return ir_analyze_instruction_src(ira, (IrInstSrcSrc *)instruction);
24580 case Stage1ZirInstIdEndExpr:
24581 return ir_analyze_instruction_end_expr(ira, (Stage1ZirInstEndExpr *)instruction);
24582 case Stage1ZirInstIdBitCast:
24583 return ir_analyze_instruction_bit_cast_src(ira, (Stage1ZirInstBitCast *)instruction);
24584 case Stage1ZirInstIdUnionInitNamedField:
24585 return ir_analyze_instruction_union_init_named_field(ira, (Stage1ZirInstUnionInitNamedField *)instruction);
24586 case Stage1ZirInstIdSuspendBegin:
24587 return ir_analyze_instruction_suspend_begin(ira, (Stage1ZirInstSuspendBegin *)instruction);
24588 case Stage1ZirInstIdSuspendFinish:
24589 return ir_analyze_instruction_suspend_finish(ira, (Stage1ZirInstSuspendFinish *)instruction);
24590 case Stage1ZirInstIdResume:
24591 return ir_analyze_instruction_resume(ira, (Stage1ZirInstResume *)instruction);
24592 case Stage1ZirInstIdAwait:
24593 return ir_analyze_instruction_await(ira, (Stage1ZirInstAwait *)instruction);
24594 case Stage1ZirInstIdSpillBegin:
24595 return ir_analyze_instruction_spill_begin(ira, (Stage1ZirInstSpillBegin *)instruction);
24596 case Stage1ZirInstIdSpillEnd:
24597 return ir_analyze_instruction_spill_end(ira, (Stage1ZirInstSpillEnd *)instruction);
24598 case Stage1ZirInstIdWasmMemorySize:
24599 return ir_analyze_instruction_wasm_memory_size(ira, (Stage1ZirInstWasmMemorySize *)instruction);
24600 case Stage1ZirInstIdWasmMemoryGrow:
24601 return ir_analyze_instruction_wasm_memory_grow(ira, (Stage1ZirInstWasmMemoryGrow *)instruction);
24602 case Stage1ZirInstIdSrc:
24603 return ir_analyze_instruction_src(ira, (Stage1ZirInstSrc *)instruction);
2460424604 }
2460524605 zig_unreachable();
2460624606}
......@@ -24630,7 +24630,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
2463024630 ira->new_irb.exec = stage1_air;
2463124631
2463224632 Stage1ZirBasicBlock *old_entry_bb = ira->zir->basic_block_list.at(0);
24633 IrBasicBlockGen *new_entry_bb = ir_get_new_bb(ira, old_entry_bb, nullptr);
24633 Stage1AirBasicBlock *new_entry_bb = ir_get_new_bb(ira, old_entry_bb, nullptr);
2463424634 ira->new_irb.current_basic_block = new_entry_bb;
2463524635 ira->old_bb_index = 0;
2463624636
......@@ -24638,7 +24638,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
2463824638
2463924639 if (result_ptr != nullptr) {
2464024640 assert(result_ptr->type->id == ZigTypeIdPointer);
24641 IrInstGenConst *const_inst = ir_create_inst_noval<IrInstGenConst>(
24641 Stage1AirInstConst *const_inst = ir_create_inst_noval<Stage1AirInstConst>(
2464224642 &ira->new_irb, stage1_air->begin_scope, stage1_air->source_node);
2464324643 const_inst->base.value = result_ptr;
2464424644 ira->return_ptr = &const_inst->base;
......@@ -24650,7 +24650,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
2465024650 }
2465124651
2465224652 while (ira->old_bb_index < ira->zir->basic_block_list.length) {
24653 IrInstSrc *old_instruction = ira->zir_current_basic_block->instruction_list.at(ira->instruction_index);
24653 Stage1ZirInst *old_instruction = ira->zir_current_basic_block->instruction_list.at(ira->instruction_index);
2465424654
2465524655 if (old_instruction->ref_count == 0 && !ir_inst_src_has_side_effects(old_instruction)) {
2465624656 ira->instruction_index += 1;
......@@ -24664,7 +24664,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
2466424664 ir_print_inst_src(codegen, stderr, old_instruction, 0);
2466524665 }
2466624666 ira->suspend_source_instr = old_instruction;
24667 IrInstGen *new_instruction = ir_analyze_instruction_base(ira, old_instruction);
24667 Stage1AirInst *new_instruction = ir_analyze_instruction_base(ira, old_instruction);
2466824668 if (new_instruction != nullptr) {
2466924669 src_assert(new_instruction->value->type != nullptr || new_instruction->value->type != nullptr, old_instruction->source_node);
2467024670 old_instruction->child = new_instruction;
......@@ -24732,283 +24732,283 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
2473224732 return res_type;
2473324733}
2473424734
24735bool ir_inst_gen_has_side_effects(IrInstGen *instruction) {
24735bool ir_inst_gen_has_side_effects(Stage1AirInst *instruction) {
2473624736 switch (instruction->id) {
24737 case IrInstGenIdInvalid:
24737 case Stage1AirInstIdInvalid:
2473824738 zig_unreachable();
24739 case IrInstGenIdBr:
24740 case IrInstGenIdCondBr:
24741 case IrInstGenIdSwitchBr:
24742 case IrInstGenIdDeclVar:
24743 case IrInstGenIdStorePtr:
24744 case IrInstGenIdVectorStoreElem:
24745 case IrInstGenIdCall:
24746 case IrInstGenIdReturn:
24747 case IrInstGenIdUnreachable:
24748 case IrInstGenIdFence:
24749 case IrInstGenIdMemset:
24750 case IrInstGenIdMemcpy:
24751 case IrInstGenIdBreakpoint:
24752 case IrInstGenIdOverflowOp: // TODO when we support multiple returns this can be side effect free
24753 case IrInstGenIdPanic:
24754 case IrInstGenIdSaveErrRetAddr:
24755 case IrInstGenIdAtomicRmw:
24756 case IrInstGenIdAtomicStore:
24757 case IrInstGenIdCmpxchg:
24758 case IrInstGenIdAssertZero:
24759 case IrInstGenIdAssertNonNull:
24760 case IrInstGenIdPtrOfArrayToSlice:
24761 case IrInstGenIdSlice:
24762 case IrInstGenIdOptionalWrap:
24763 case IrInstGenIdVectorToArray:
24764 case IrInstGenIdSuspendBegin:
24765 case IrInstGenIdSuspendFinish:
24766 case IrInstGenIdResume:
24767 case IrInstGenIdAwait:
24768 case IrInstGenIdSpillBegin:
24769 case IrInstGenIdWasmMemoryGrow:
24770 case IrInstGenIdExtern:
24739 case Stage1AirInstIdBr:
24740 case Stage1AirInstIdCondBr:
24741 case Stage1AirInstIdSwitchBr:
24742 case Stage1AirInstIdDeclVar:
24743 case Stage1AirInstIdStorePtr:
24744 case Stage1AirInstIdVectorStoreElem:
24745 case Stage1AirInstIdCall:
24746 case Stage1AirInstIdReturn:
24747 case Stage1AirInstIdUnreachable:
24748 case Stage1AirInstIdFence:
24749 case Stage1AirInstIdMemset:
24750 case Stage1AirInstIdMemcpy:
24751 case Stage1AirInstIdBreakpoint:
24752 case Stage1AirInstIdOverflowOp: // TODO when we support multiple returns this can be side effect free
24753 case Stage1AirInstIdPanic:
24754 case Stage1AirInstIdSaveErrRetAddr:
24755 case Stage1AirInstIdAtomicRmw:
24756 case Stage1AirInstIdAtomicStore:
24757 case Stage1AirInstIdCmpxchg:
24758 case Stage1AirInstIdAssertZero:
24759 case Stage1AirInstIdAssertNonNull:
24760 case Stage1AirInstIdPtrOfArrayToSlice:
24761 case Stage1AirInstIdSlice:
24762 case Stage1AirInstIdOptionalWrap:
24763 case Stage1AirInstIdVectorToArray:
24764 case Stage1AirInstIdSuspendBegin:
24765 case Stage1AirInstIdSuspendFinish:
24766 case Stage1AirInstIdResume:
24767 case Stage1AirInstIdAwait:
24768 case Stage1AirInstIdSpillBegin:
24769 case Stage1AirInstIdWasmMemoryGrow:
24770 case Stage1AirInstIdExtern:
2477124771 return true;
2477224772
24773 case IrInstGenIdPhi:
24774 case IrInstGenIdBinOp:
24775 case IrInstGenIdConst:
24776 case IrInstGenIdCast:
24777 case IrInstGenIdElemPtr:
24778 case IrInstGenIdVarPtr:
24779 case IrInstGenIdReturnPtr:
24780 case IrInstGenIdStructFieldPtr:
24781 case IrInstGenIdTestNonNull:
24782 case IrInstGenIdClz:
24783 case IrInstGenIdCtz:
24784 case IrInstGenIdPopCount:
24785 case IrInstGenIdBswap:
24786 case IrInstGenIdBitReverse:
24787 case IrInstGenIdUnionTag:
24788 case IrInstGenIdTruncate:
24789 case IrInstGenIdShuffleVector:
24790 case IrInstGenIdSplat:
24791 case IrInstGenIdBoolNot:
24792 case IrInstGenIdReturnAddress:
24793 case IrInstGenIdFrameAddress:
24794 case IrInstGenIdFrameHandle:
24795 case IrInstGenIdFrameSize:
24796 case IrInstGenIdTestErr:
24797 case IrInstGenIdPtrCast:
24798 case IrInstGenIdBitCast:
24799 case IrInstGenIdWidenOrShorten:
24800 case IrInstGenIdPtrToInt:
24801 case IrInstGenIdIntToPtr:
24802 case IrInstGenIdIntToEnum:
24803 case IrInstGenIdIntToErr:
24804 case IrInstGenIdErrToInt:
24805 case IrInstGenIdErrName:
24806 case IrInstGenIdTagName:
24807 case IrInstGenIdFieldParentPtr:
24808 case IrInstGenIdAlignCast:
24809 case IrInstGenIdErrorReturnTrace:
24810 case IrInstGenIdFloatOp:
24811 case IrInstGenIdMulAdd:
24812 case IrInstGenIdAtomicLoad:
24813 case IrInstGenIdArrayToVector:
24814 case IrInstGenIdAlloca:
24815 case IrInstGenIdSpillEnd:
24816 case IrInstGenIdVectorExtractElem:
24817 case IrInstGenIdBinaryNot:
24818 case IrInstGenIdNegation:
24819 case IrInstGenIdWasmMemorySize:
24820 case IrInstGenIdReduce:
24773 case Stage1AirInstIdPhi:
24774 case Stage1AirInstIdBinOp:
24775 case Stage1AirInstIdConst:
24776 case Stage1AirInstIdCast:
24777 case Stage1AirInstIdElemPtr:
24778 case Stage1AirInstIdVarPtr:
24779 case Stage1AirInstIdReturnPtr:
24780 case Stage1AirInstIdStructFieldPtr:
24781 case Stage1AirInstIdTestNonNull:
24782 case Stage1AirInstIdClz:
24783 case Stage1AirInstIdCtz:
24784 case Stage1AirInstIdPopCount:
24785 case Stage1AirInstIdBswap:
24786 case Stage1AirInstIdBitReverse:
24787 case Stage1AirInstIdUnionTag:
24788 case Stage1AirInstIdTruncate:
24789 case Stage1AirInstIdShuffleVector:
24790 case Stage1AirInstIdSplat:
24791 case Stage1AirInstIdBoolNot:
24792 case Stage1AirInstIdReturnAddress:
24793 case Stage1AirInstIdFrameAddress:
24794 case Stage1AirInstIdFrameHandle:
24795 case Stage1AirInstIdFrameSize:
24796 case Stage1AirInstIdTestErr:
24797 case Stage1AirInstIdPtrCast:
24798 case Stage1AirInstIdBitCast:
24799 case Stage1AirInstIdWidenOrShorten:
24800 case Stage1AirInstIdPtrToInt:
24801 case Stage1AirInstIdIntToPtr:
24802 case Stage1AirInstIdIntToEnum:
24803 case Stage1AirInstIdIntToErr:
24804 case Stage1AirInstIdErrToInt:
24805 case Stage1AirInstIdErrName:
24806 case Stage1AirInstIdTagName:
24807 case Stage1AirInstIdFieldParentPtr:
24808 case Stage1AirInstIdAlignCast:
24809 case Stage1AirInstIdErrorReturnTrace:
24810 case Stage1AirInstIdFloatOp:
24811 case Stage1AirInstIdMulAdd:
24812 case Stage1AirInstIdAtomicLoad:
24813 case Stage1AirInstIdArrayToVector:
24814 case Stage1AirInstIdAlloca:
24815 case Stage1AirInstIdSpillEnd:
24816 case Stage1AirInstIdVectorExtractElem:
24817 case Stage1AirInstIdBinaryNot:
24818 case Stage1AirInstIdNegation:
24819 case Stage1AirInstIdWasmMemorySize:
24820 case Stage1AirInstIdReduce:
2482124821 return false;
2482224822
24823 case IrInstGenIdAsm:
24823 case Stage1AirInstIdAsm:
2482424824 {
24825 IrInstGenAsm *asm_instruction = (IrInstGenAsm *)instruction;
24825 Stage1AirInstAsm *asm_instruction = (Stage1AirInstAsm *)instruction;
2482624826 return asm_instruction->has_side_effects;
2482724827 }
24828 case IrInstGenIdUnwrapErrPayload:
24828 case Stage1AirInstIdUnwrapErrPayload:
2482924829 {
24830 IrInstGenUnwrapErrPayload *unwrap_err_payload_instruction =
24831 (IrInstGenUnwrapErrPayload *)instruction;
24830 Stage1AirInstUnwrapErrPayload *unwrap_err_payload_instruction =
24831 (Stage1AirInstUnwrapErrPayload *)instruction;
2483224832 return unwrap_err_payload_instruction->safety_check_on ||
2483324833 unwrap_err_payload_instruction->initializing;
2483424834 }
24835 case IrInstGenIdUnwrapErrCode:
24836 return reinterpret_cast<IrInstGenUnwrapErrCode *>(instruction)->initializing;
24837 case IrInstGenIdUnionFieldPtr:
24838 return reinterpret_cast<IrInstGenUnionFieldPtr *>(instruction)->initializing;
24839 case IrInstGenIdOptionalUnwrapPtr:
24840 return reinterpret_cast<IrInstGenOptionalUnwrapPtr *>(instruction)->initializing;
24841 case IrInstGenIdErrWrapPayload:
24842 return reinterpret_cast<IrInstGenErrWrapPayload *>(instruction)->result_loc != nullptr;
24843 case IrInstGenIdErrWrapCode:
24844 return reinterpret_cast<IrInstGenErrWrapCode *>(instruction)->result_loc != nullptr;
24845 case IrInstGenIdLoadPtr:
24846 return reinterpret_cast<IrInstGenLoadPtr *>(instruction)->result_loc != nullptr;
24847 case IrInstGenIdRef:
24848 return reinterpret_cast<IrInstGenRef *>(instruction)->result_loc != nullptr;
24835 case Stage1AirInstIdUnwrapErrCode:
24836 return reinterpret_cast<Stage1AirInstUnwrapErrCode *>(instruction)->initializing;
24837 case Stage1AirInstIdUnionFieldPtr:
24838 return reinterpret_cast<Stage1AirInstUnionFieldPtr *>(instruction)->initializing;
24839 case Stage1AirInstIdOptionalUnwrapPtr:
24840 return reinterpret_cast<Stage1AirInstOptionalUnwrapPtr *>(instruction)->initializing;
24841 case Stage1AirInstIdErrWrapPayload:
24842 return reinterpret_cast<Stage1AirInstErrWrapPayload *>(instruction)->result_loc != nullptr;
24843 case Stage1AirInstIdErrWrapCode:
24844 return reinterpret_cast<Stage1AirInstErrWrapCode *>(instruction)->result_loc != nullptr;
24845 case Stage1AirInstIdLoadPtr:
24846 return reinterpret_cast<Stage1AirInstLoadPtr *>(instruction)->result_loc != nullptr;
24847 case Stage1AirInstIdRef:
24848 return reinterpret_cast<Stage1AirInstRef *>(instruction)->result_loc != nullptr;
2484924849 }
2485024850 zig_unreachable();
2485124851}
2485224852
24853bool ir_inst_src_has_side_effects(IrInstSrc *instruction) {
24853bool ir_inst_src_has_side_effects(Stage1ZirInst *instruction) {
2485424854 switch (instruction->id) {
24855 case IrInstSrcIdInvalid:
24855 case Stage1ZirInstIdInvalid:
2485624856 zig_unreachable();
24857 case IrInstSrcIdBr:
24858 case IrInstSrcIdCondBr:
24859 case IrInstSrcIdSwitchBr:
24860 case IrInstSrcIdDeclVar:
24861 case IrInstSrcIdStorePtr:
24862 case IrInstSrcIdCallExtra:
24863 case IrInstSrcIdAsyncCallExtra:
24864 case IrInstSrcIdCall:
24865 case IrInstSrcIdCallArgs:
24866 case IrInstSrcIdReturn:
24867 case IrInstSrcIdUnreachable:
24868 case IrInstSrcIdSetCold:
24869 case IrInstSrcIdSetRuntimeSafety:
24870 case IrInstSrcIdSetFloatMode:
24871 case IrInstSrcIdImport:
24872 case IrInstSrcIdCompileErr:
24873 case IrInstSrcIdCompileLog:
24874 case IrInstSrcIdCImport:
24875 case IrInstSrcIdCInclude:
24876 case IrInstSrcIdCDefine:
24877 case IrInstSrcIdCUndef:
24878 case IrInstSrcIdFence:
24879 case IrInstSrcIdMemset:
24880 case IrInstSrcIdMemcpy:
24881 case IrInstSrcIdBreakpoint:
24882 case IrInstSrcIdOverflowOp: // TODO when we support multiple returns this can be side effect free
24883 case IrInstSrcIdCheckSwitchProngsUnderNo:
24884 case IrInstSrcIdCheckSwitchProngsUnderYes:
24885 case IrInstSrcIdCheckStatementIsVoid:
24886 case IrInstSrcIdCheckRuntimeScope:
24887 case IrInstSrcIdPanic:
24888 case IrInstSrcIdSetEvalBranchQuota:
24889 case IrInstSrcIdPtrType:
24890 case IrInstSrcIdPtrTypeSimple:
24891 case IrInstSrcIdPtrTypeSimpleConst:
24892 case IrInstSrcIdSetAlignStack:
24893 case IrInstSrcIdExport:
24894 case IrInstSrcIdExtern:
24895 case IrInstSrcIdSaveErrRetAddr:
24896 case IrInstSrcIdAddImplicitReturnType:
24897 case IrInstSrcIdAtomicRmw:
24898 case IrInstSrcIdAtomicStore:
24899 case IrInstSrcIdCmpxchg:
24900 case IrInstSrcIdUndeclaredIdent:
24901 case IrInstSrcIdEndExpr:
24902 case IrInstSrcIdResetResult:
24903 case IrInstSrcIdSuspendBegin:
24904 case IrInstSrcIdSuspendFinish:
24905 case IrInstSrcIdResume:
24906 case IrInstSrcIdAwait:
24907 case IrInstSrcIdSpillBegin:
24908 case IrInstSrcIdWasmMemoryGrow:
24857 case Stage1ZirInstIdBr:
24858 case Stage1ZirInstIdCondBr:
24859 case Stage1ZirInstIdSwitchBr:
24860 case Stage1ZirInstIdDeclVar:
24861 case Stage1ZirInstIdStorePtr:
24862 case Stage1ZirInstIdCallExtra:
24863 case Stage1ZirInstIdAsyncCallExtra:
24864 case Stage1ZirInstIdCall:
24865 case Stage1ZirInstIdCallArgs:
24866 case Stage1ZirInstIdReturn:
24867 case Stage1ZirInstIdUnreachable:
24868 case Stage1ZirInstIdSetCold:
24869 case Stage1ZirInstIdSetRuntimeSafety:
24870 case Stage1ZirInstIdSetFloatMode:
24871 case Stage1ZirInstIdImport:
24872 case Stage1ZirInstIdCompileErr:
24873 case Stage1ZirInstIdCompileLog:
24874 case Stage1ZirInstIdCImport:
24875 case Stage1ZirInstIdCInclude:
24876 case Stage1ZirInstIdCDefine:
24877 case Stage1ZirInstIdCUndef:
24878 case Stage1ZirInstIdFence:
24879 case Stage1ZirInstIdMemset:
24880 case Stage1ZirInstIdMemcpy:
24881 case Stage1ZirInstIdBreakpoint:
24882 case Stage1ZirInstIdOverflowOp: // TODO when we support multiple returns this can be side effect free
24883 case Stage1ZirInstIdCheckSwitchProngsUnderNo:
24884 case Stage1ZirInstIdCheckSwitchProngsUnderYes:
24885 case Stage1ZirInstIdCheckStatementIsVoid:
24886 case Stage1ZirInstIdCheckRuntimeScope:
24887 case Stage1ZirInstIdPanic:
24888 case Stage1ZirInstIdSetEvalBranchQuota:
24889 case Stage1ZirInstIdPtrType:
24890 case Stage1ZirInstIdPtrTypeSimple:
24891 case Stage1ZirInstIdPtrTypeSimpleConst:
24892 case Stage1ZirInstIdSetAlignStack:
24893 case Stage1ZirInstIdExport:
24894 case Stage1ZirInstIdExtern:
24895 case Stage1ZirInstIdSaveErrRetAddr:
24896 case Stage1ZirInstIdAddImplicitReturnType:
24897 case Stage1ZirInstIdAtomicRmw:
24898 case Stage1ZirInstIdAtomicStore:
24899 case Stage1ZirInstIdCmpxchg:
24900 case Stage1ZirInstIdUndeclaredIdent:
24901 case Stage1ZirInstIdEndExpr:
24902 case Stage1ZirInstIdResetResult:
24903 case Stage1ZirInstIdSuspendBegin:
24904 case Stage1ZirInstIdSuspendFinish:
24905 case Stage1ZirInstIdResume:
24906 case Stage1ZirInstIdAwait:
24907 case Stage1ZirInstIdSpillBegin:
24908 case Stage1ZirInstIdWasmMemoryGrow:
2490924909 return true;
2491024910
24911 case IrInstSrcIdPhi:
24912 case IrInstSrcIdUnOp:
24913 case IrInstSrcIdBinOp:
24914 case IrInstSrcIdMergeErrSets:
24915 case IrInstSrcIdLoadPtr:
24916 case IrInstSrcIdConst:
24917 case IrInstSrcIdContainerInitList:
24918 case IrInstSrcIdContainerInitFields:
24919 case IrInstSrcIdUnionInitNamedField:
24920 case IrInstSrcIdFieldPtr:
24921 case IrInstSrcIdElemPtr:
24922 case IrInstSrcIdVarPtr:
24923 case IrInstSrcIdTypeOf:
24924 case IrInstSrcIdArrayType:
24925 case IrInstSrcIdSliceType:
24926 case IrInstSrcIdAnyFrameType:
24927 case IrInstSrcIdSizeOf:
24928 case IrInstSrcIdTestNonNull:
24929 case IrInstSrcIdOptionalUnwrapPtr:
24930 case IrInstSrcIdClz:
24931 case IrInstSrcIdCtz:
24932 case IrInstSrcIdPopCount:
24933 case IrInstSrcIdBswap:
24934 case IrInstSrcIdBitReverse:
24935 case IrInstSrcIdSwitchVar:
24936 case IrInstSrcIdSwitchElseVar:
24937 case IrInstSrcIdSwitchTarget:
24938 case IrInstSrcIdRef:
24939 case IrInstSrcIdEmbedFile:
24940 case IrInstSrcIdTruncate:
24941 case IrInstSrcIdVectorType:
24942 case IrInstSrcIdShuffleVector:
24943 case IrInstSrcIdSplat:
24944 case IrInstSrcIdBoolNot:
24945 case IrInstSrcIdSlice:
24946 case IrInstSrcIdAlignOf:
24947 case IrInstSrcIdReturnAddress:
24948 case IrInstSrcIdFrameAddress:
24949 case IrInstSrcIdFrameHandle:
24950 case IrInstSrcIdFrameType:
24951 case IrInstSrcIdFrameSize:
24952 case IrInstSrcIdTestErr:
24953 case IrInstSrcIdFnProto:
24954 case IrInstSrcIdTestComptime:
24955 case IrInstSrcIdPtrCast:
24956 case IrInstSrcIdBitCast:
24957 case IrInstSrcIdPtrToInt:
24958 case IrInstSrcIdIntToPtr:
24959 case IrInstSrcIdIntToEnum:
24960 case IrInstSrcIdIntToErr:
24961 case IrInstSrcIdErrToInt:
24962 case IrInstSrcIdDeclRef:
24963 case IrInstSrcIdErrName:
24964 case IrInstSrcIdTypeName:
24965 case IrInstSrcIdTagName:
24966 case IrInstSrcIdFieldParentPtr:
24967 case IrInstSrcIdOffsetOf:
24968 case IrInstSrcIdBitOffsetOf:
24969 case IrInstSrcIdTypeInfo:
24970 case IrInstSrcIdType:
24971 case IrInstSrcIdHasField:
24972 case IrInstSrcIdAlignCast:
24973 case IrInstSrcIdImplicitCast:
24974 case IrInstSrcIdResolveResult:
24975 case IrInstSrcIdArgTypeAllowVarFalse:
24976 case IrInstSrcIdArgTypeAllowVarTrue:
24977 case IrInstSrcIdErrorReturnTrace:
24978 case IrInstSrcIdErrorUnion:
24979 case IrInstSrcIdFloatOp:
24980 case IrInstSrcIdMulAdd:
24981 case IrInstSrcIdAtomicLoad:
24982 case IrInstSrcIdIntCast:
24983 case IrInstSrcIdFloatCast:
24984 case IrInstSrcIdErrSetCast:
24985 case IrInstSrcIdIntToFloat:
24986 case IrInstSrcIdFloatToInt:
24987 case IrInstSrcIdBoolToInt:
24988 case IrInstSrcIdEnumToInt:
24989 case IrInstSrcIdHasDecl:
24990 case IrInstSrcIdAlloca:
24991 case IrInstSrcIdSpillEnd:
24992 case IrInstSrcIdWasmMemorySize:
24993 case IrInstSrcIdSrc:
24994 case IrInstSrcIdReduce:
24911 case Stage1ZirInstIdPhi:
24912 case Stage1ZirInstIdUnOp:
24913 case Stage1ZirInstIdBinOp:
24914 case Stage1ZirInstIdMergeErrSets:
24915 case Stage1ZirInstIdLoadPtr:
24916 case Stage1ZirInstIdConst:
24917 case Stage1ZirInstIdContainerInitList:
24918 case Stage1ZirInstIdContainerInitFields:
24919 case Stage1ZirInstIdUnionInitNamedField:
24920 case Stage1ZirInstIdFieldPtr:
24921 case Stage1ZirInstIdElemPtr:
24922 case Stage1ZirInstIdVarPtr:
24923 case Stage1ZirInstIdTypeOf:
24924 case Stage1ZirInstIdArrayType:
24925 case Stage1ZirInstIdSliceType:
24926 case Stage1ZirInstIdAnyFrameType:
24927 case Stage1ZirInstIdSizeOf:
24928 case Stage1ZirInstIdTestNonNull:
24929 case Stage1ZirInstIdOptionalUnwrapPtr:
24930 case Stage1ZirInstIdClz:
24931 case Stage1ZirInstIdCtz:
24932 case Stage1ZirInstIdPopCount:
24933 case Stage1ZirInstIdBswap:
24934 case Stage1ZirInstIdBitReverse:
24935 case Stage1ZirInstIdSwitchVar:
24936 case Stage1ZirInstIdSwitchElseVar:
24937 case Stage1ZirInstIdSwitchTarget:
24938 case Stage1ZirInstIdRef:
24939 case Stage1ZirInstIdEmbedFile:
24940 case Stage1ZirInstIdTruncate:
24941 case Stage1ZirInstIdVectorType:
24942 case Stage1ZirInstIdShuffleVector:
24943 case Stage1ZirInstIdSplat:
24944 case Stage1ZirInstIdBoolNot:
24945 case Stage1ZirInstIdSlice:
24946 case Stage1ZirInstIdAlignOf:
24947 case Stage1ZirInstIdReturnAddress:
24948 case Stage1ZirInstIdFrameAddress:
24949 case Stage1ZirInstIdFrameHandle:
24950 case Stage1ZirInstIdFrameType:
24951 case Stage1ZirInstIdFrameSize:
24952 case Stage1ZirInstIdTestErr:
24953 case Stage1ZirInstIdFnProto:
24954 case Stage1ZirInstIdTestComptime:
24955 case Stage1ZirInstIdPtrCast:
24956 case Stage1ZirInstIdBitCast:
24957 case Stage1ZirInstIdPtrToInt:
24958 case Stage1ZirInstIdIntToPtr:
24959 case Stage1ZirInstIdIntToEnum:
24960 case Stage1ZirInstIdIntToErr:
24961 case Stage1ZirInstIdErrToInt:
24962 case Stage1ZirInstIdDeclRef:
24963 case Stage1ZirInstIdErrName:
24964 case Stage1ZirInstIdTypeName:
24965 case Stage1ZirInstIdTagName:
24966 case Stage1ZirInstIdFieldParentPtr:
24967 case Stage1ZirInstIdOffsetOf:
24968 case Stage1ZirInstIdBitOffsetOf:
24969 case Stage1ZirInstIdTypeInfo:
24970 case Stage1ZirInstIdType:
24971 case Stage1ZirInstIdHasField:
24972 case Stage1ZirInstIdAlignCast:
24973 case Stage1ZirInstIdImplicitCast:
24974 case Stage1ZirInstIdResolveResult:
24975 case Stage1ZirInstIdArgTypeAllowVarFalse:
24976 case Stage1ZirInstIdArgTypeAllowVarTrue:
24977 case Stage1ZirInstIdErrorReturnTrace:
24978 case Stage1ZirInstIdErrorUnion:
24979 case Stage1ZirInstIdFloatOp:
24980 case Stage1ZirInstIdMulAdd:
24981 case Stage1ZirInstIdAtomicLoad:
24982 case Stage1ZirInstIdIntCast:
24983 case Stage1ZirInstIdFloatCast:
24984 case Stage1ZirInstIdErrSetCast:
24985 case Stage1ZirInstIdIntToFloat:
24986 case Stage1ZirInstIdFloatToInt:
24987 case Stage1ZirInstIdBoolToInt:
24988 case Stage1ZirInstIdEnumToInt:
24989 case Stage1ZirInstIdHasDecl:
24990 case Stage1ZirInstIdAlloca:
24991 case Stage1ZirInstIdSpillEnd:
24992 case Stage1ZirInstIdWasmMemorySize:
24993 case Stage1ZirInstIdSrc:
24994 case Stage1ZirInstIdReduce:
2499524995 return false;
2499624996
24997 case IrInstSrcIdAsm:
24997 case Stage1ZirInstIdAsm:
2499824998 {
24999 IrInstSrcAsm *asm_instruction = (IrInstSrcAsm *)instruction;
24999 Stage1ZirInstAsm *asm_instruction = (Stage1ZirInstAsm *)instruction;
2500025000 return asm_instruction->has_side_effects;
2500125001 }
2500225002
25003 case IrInstSrcIdUnwrapErrPayload:
25003 case Stage1ZirInstIdUnwrapErrPayload:
2500425004 {
25005 IrInstSrcUnwrapErrPayload *unwrap_err_payload_instruction =
25006 (IrInstSrcUnwrapErrPayload *)instruction;
25005 Stage1ZirInstUnwrapErrPayload *unwrap_err_payload_instruction =
25006 (Stage1ZirInstUnwrapErrPayload *)instruction;
2500725007 return unwrap_err_payload_instruction->safety_check_on ||
2500825008 unwrap_err_payload_instruction->initializing;
2500925009 }
25010 case IrInstSrcIdUnwrapErrCode:
25011 return reinterpret_cast<IrInstSrcUnwrapErrCode *>(instruction)->initializing;
25010 case Stage1ZirInstIdUnwrapErrCode:
25011 return reinterpret_cast<Stage1ZirInstUnwrapErrCode *>(instruction)->initializing;
2501225012 }
2501325013 zig_unreachable();
2501425014}
......@@ -25047,7 +25047,7 @@ static ZigType *ir_resolve_lazy_fn_type(IrAnalyze *ira, AstNode *source_node, La
2504725047 param_info->type = nullptr;
2504825048 return get_generic_fn_type(ira->codegen, &fn_type_id);
2504925049 } else {
25050 IrInstGen *param_type_inst = lazy_fn_type->param_types[fn_type_id.next_param_index];
25050 Stage1AirInst *param_type_inst = lazy_fn_type->param_types[fn_type_id.next_param_index];
2505125051 ZigType *param_type = ir_resolve_type(ira, param_type_inst);
2505225052 if (type_is_invalid(param_type))
2505325053 return nullptr;
......@@ -25257,7 +25257,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) {
2525725257 if (lazy_slice_type->sentinel != nullptr) {
2525825258 if (type_is_invalid(lazy_slice_type->sentinel->value->type))
2525925259 return ErrorSemanticAnalyzeFail;
25260 IrInstGen *sentinel = ir_implicit_cast(ira, lazy_slice_type->sentinel, elem_type);
25260 Stage1AirInst *sentinel = ir_implicit_cast(ira, lazy_slice_type->sentinel, elem_type);
2526125261 if (type_is_invalid(sentinel->value->type))
2526225262 return ErrorSemanticAnalyzeFail;
2526325263 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);
......@@ -25336,7 +25336,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) {
2533625336 if (lazy_ptr_type->sentinel != nullptr) {
2533725337 if (type_is_invalid(lazy_ptr_type->sentinel->value->type))
2533825338 return ErrorSemanticAnalyzeFail;
25339 IrInstGen *sentinel = ir_implicit_cast(ira, lazy_ptr_type->sentinel, elem_type);
25339 Stage1AirInst *sentinel = ir_implicit_cast(ira, lazy_ptr_type->sentinel, elem_type);
2534025340 if (type_is_invalid(sentinel->value->type))
2534125341 return ErrorSemanticAnalyzeFail;
2534225342 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);
......@@ -25500,7 +25500,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) {
2550025500 if (lazy_array_type->sentinel != nullptr) {
2550125501 if (type_is_invalid(lazy_array_type->sentinel->value->type))
2550225502 return ErrorSemanticAnalyzeFail;
25503 IrInstGen *sentinel = ir_implicit_cast(ira, lazy_array_type->sentinel, elem_type);
25503 Stage1AirInst *sentinel = ir_implicit_cast(ira, lazy_array_type->sentinel, elem_type);
2550425504 if (type_is_invalid(sentinel->value->type))
2550525505 return ErrorSemanticAnalyzeFail;
2550625506 sentinel_val = ir_resolve_const(ira, sentinel, UndefBad);
......@@ -25691,8 +25691,8 @@ Error ir_resolve_lazy(CodeGen *codegen, AstNode *source_node, ZigValue *val) {
2569125691 return ErrorNone;
2569225692}
2569325693
25694void IrInstGen::src() {
25695 IrInstGen *inst = this;
25694void Stage1AirInst::src() {
25695 Stage1AirInst *inst = this;
2569625696 if (inst->source_node != nullptr) {
2569725697 inst->source_node->src();
2569825698 } else {
......@@ -25700,8 +25700,8 @@ void IrInstGen::src() {
2570025700 }
2570125701}
2570225702
25703void IrInstGen::dump() {
25704 IrInstGen *inst = this;
25703void Stage1AirInst::dump() {
25704 Stage1AirInst *inst = this;
2570525705 inst->src();
2570625706 if (inst->scope == nullptr) {
2570725707 fprintf(stderr, "(null scope)\n");
src/stage1/ir.hpp+2-2
......@@ -10,7 +10,7 @@
1010
1111#include "all_types.hpp"
1212
13IrInstGen *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn,
13Stage1AirInst *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn,
1414 ZigType *var_type, const char *name_hint);
1515
1616Error ir_eval_const_value(CodeGen *codegen, Scope *scope, AstNode *node,
......@@ -25,7 +25,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
2525 ZigType *expected_type, AstNode *expected_type_source_node, ZigValue *result_ptr,
2626 ZigFn *fn);
2727
28bool ir_inst_gen_has_side_effects(IrInstGen *inst);
28bool ir_inst_gen_has_side_effects(Stage1AirInst *inst);
2929
3030struct IrAnalyze;
3131ZigValue *const_ptr_pointee(IrAnalyze *ira, CodeGen *codegen, ZigValue *const_val,
src/stage1/ir_print.cpp+955-955
......@@ -12,26 +12,26 @@
1212#include "ir_print.hpp"
1313#include "os.hpp"
1414
15static uint32_t hash_inst_src_ptr(IrInstSrc* instruction) {
15static uint32_t hash_inst_src_ptr(Stage1ZirInst* instruction) {
1616 return (uint32_t)(uintptr_t)instruction;
1717}
1818
19static uint32_t hash_inst_gen_ptr(IrInstGen* instruction) {
19static uint32_t hash_inst_gen_ptr(Stage1AirInst* instruction) {
2020 return (uint32_t)(uintptr_t)instruction;
2121}
2222
23static bool inst_src_ptr_eql(IrInstSrc* a, IrInstSrc* b) {
23static bool inst_src_ptr_eql(Stage1ZirInst* a, Stage1ZirInst* b) {
2424 return a == b;
2525}
2626
27static bool inst_gen_ptr_eql(IrInstGen* a, IrInstGen* b) {
27static bool inst_gen_ptr_eql(Stage1AirInst* a, Stage1AirInst* b) {
2828 return a == b;
2929}
3030
31using InstSetSrc = HashMap<IrInstSrc*, uint8_t, hash_inst_src_ptr, inst_src_ptr_eql>;
32using InstSetGen = HashMap<IrInstGen*, uint8_t, hash_inst_gen_ptr, inst_gen_ptr_eql>;
33using InstListSrc = ZigList<IrInstSrc*>;
34using InstListGen = ZigList<IrInstGen*>;
31using InstSetSrc = HashMap<Stage1ZirInst*, uint8_t, hash_inst_src_ptr, inst_src_ptr_eql>;
32using InstSetGen = HashMap<Stage1AirInst*, uint8_t, hash_inst_gen_ptr, inst_gen_ptr_eql>;
33using InstListSrc = ZigList<Stage1ZirInst*>;
34using InstListGen = ZigList<Stage1AirInst*>;
3535
3636struct IrPrintSrc {
3737 CodeGen *codegen;
......@@ -54,8 +54,8 @@ struct IrPrintGen {
5454 InstListGen pending;
5555};
5656
57static void ir_print_other_inst_src(IrPrintSrc *irp, IrInstSrc *inst);
58static void ir_print_other_inst_gen(IrPrintGen *irp, IrInstGen *inst);
57static void ir_print_other_inst_src(IrPrintSrc *irp, Stage1ZirInst *inst);
58static void ir_print_other_inst_gen(IrPrintGen *irp, Stage1AirInst *inst);
5959
6060static void ir_print_call_modifier(FILE *f, CallModifier modifier) {
6161 switch (modifier) {
......@@ -87,473 +87,473 @@ static void ir_print_call_modifier(FILE *f, CallModifier modifier) {
8787 }
8888}
8989
90const char* ir_inst_src_type_str(IrInstSrcId id) {
90const char* ir_inst_src_type_str(Stage1ZirInstId id) {
9191 switch (id) {
92 case IrInstSrcIdInvalid:
92 case Stage1ZirInstIdInvalid:
9393 return "SrcInvalid";
94 case IrInstSrcIdShuffleVector:
94 case Stage1ZirInstIdShuffleVector:
9595 return "SrcShuffle";
96 case IrInstSrcIdSplat:
96 case Stage1ZirInstIdSplat:
9797 return "SrcSplat";
98 case IrInstSrcIdDeclVar:
98 case Stage1ZirInstIdDeclVar:
9999 return "SrcDeclVar";
100 case IrInstSrcIdBr:
100 case Stage1ZirInstIdBr:
101101 return "SrcBr";
102 case IrInstSrcIdCondBr:
102 case Stage1ZirInstIdCondBr:
103103 return "SrcCondBr";
104 case IrInstSrcIdSwitchBr:
104 case Stage1ZirInstIdSwitchBr:
105105 return "SrcSwitchBr";
106 case IrInstSrcIdSwitchVar:
106 case Stage1ZirInstIdSwitchVar:
107107 return "SrcSwitchVar";
108 case IrInstSrcIdSwitchElseVar:
108 case Stage1ZirInstIdSwitchElseVar:
109109 return "SrcSwitchElseVar";
110 case IrInstSrcIdSwitchTarget:
110 case Stage1ZirInstIdSwitchTarget:
111111 return "SrcSwitchTarget";
112 case IrInstSrcIdPhi:
112 case Stage1ZirInstIdPhi:
113113 return "SrcPhi";
114 case IrInstSrcIdUnOp:
114 case Stage1ZirInstIdUnOp:
115115 return "SrcUnOp";
116 case IrInstSrcIdBinOp:
116 case Stage1ZirInstIdBinOp:
117117 return "SrcBinOp";
118 case IrInstSrcIdMergeErrSets:
118 case Stage1ZirInstIdMergeErrSets:
119119 return "SrcMergeErrSets";
120 case IrInstSrcIdLoadPtr:
120 case Stage1ZirInstIdLoadPtr:
121121 return "SrcLoadPtr";
122 case IrInstSrcIdStorePtr:
122 case Stage1ZirInstIdStorePtr:
123123 return "SrcStorePtr";
124 case IrInstSrcIdFieldPtr:
124 case Stage1ZirInstIdFieldPtr:
125125 return "SrcFieldPtr";
126 case IrInstSrcIdElemPtr:
126 case Stage1ZirInstIdElemPtr:
127127 return "SrcElemPtr";
128 case IrInstSrcIdVarPtr:
128 case Stage1ZirInstIdVarPtr:
129129 return "SrcVarPtr";
130 case IrInstSrcIdCallExtra:
130 case Stage1ZirInstIdCallExtra:
131131 return "SrcCallExtra";
132 case IrInstSrcIdAsyncCallExtra:
132 case Stage1ZirInstIdAsyncCallExtra:
133133 return "SrcAsyncCallExtra";
134 case IrInstSrcIdCall:
134 case Stage1ZirInstIdCall:
135135 return "SrcCall";
136 case IrInstSrcIdCallArgs:
136 case Stage1ZirInstIdCallArgs:
137137 return "SrcCallArgs";
138 case IrInstSrcIdConst:
138 case Stage1ZirInstIdConst:
139139 return "SrcConst";
140 case IrInstSrcIdReturn:
140 case Stage1ZirInstIdReturn:
141141 return "SrcReturn";
142 case IrInstSrcIdContainerInitList:
142 case Stage1ZirInstIdContainerInitList:
143143 return "SrcContainerInitList";
144 case IrInstSrcIdContainerInitFields:
144 case Stage1ZirInstIdContainerInitFields:
145145 return "SrcContainerInitFields";
146 case IrInstSrcIdUnreachable:
146 case Stage1ZirInstIdUnreachable:
147147 return "SrcUnreachable";
148 case IrInstSrcIdTypeOf:
148 case Stage1ZirInstIdTypeOf:
149149 return "SrcTypeOf";
150 case IrInstSrcIdSetCold:
150 case Stage1ZirInstIdSetCold:
151151 return "SrcSetCold";
152 case IrInstSrcIdSetRuntimeSafety:
152 case Stage1ZirInstIdSetRuntimeSafety:
153153 return "SrcSetRuntimeSafety";
154 case IrInstSrcIdSetFloatMode:
154 case Stage1ZirInstIdSetFloatMode:
155155 return "SrcSetFloatMode";
156 case IrInstSrcIdArrayType:
156 case Stage1ZirInstIdArrayType:
157157 return "SrcArrayType";
158 case IrInstSrcIdAnyFrameType:
158 case Stage1ZirInstIdAnyFrameType:
159159 return "SrcAnyFrameType";
160 case IrInstSrcIdSliceType:
160 case Stage1ZirInstIdSliceType:
161161 return "SrcSliceType";
162 case IrInstSrcIdAsm:
162 case Stage1ZirInstIdAsm:
163163 return "SrcAsm";
164 case IrInstSrcIdSizeOf:
164 case Stage1ZirInstIdSizeOf:
165165 return "SrcSizeOf";
166 case IrInstSrcIdTestNonNull:
166 case Stage1ZirInstIdTestNonNull:
167167 return "SrcTestNonNull";
168 case IrInstSrcIdOptionalUnwrapPtr:
168 case Stage1ZirInstIdOptionalUnwrapPtr:
169169 return "SrcOptionalUnwrapPtr";
170 case IrInstSrcIdClz:
170 case Stage1ZirInstIdClz:
171171 return "SrcClz";
172 case IrInstSrcIdCtz:
172 case Stage1ZirInstIdCtz:
173173 return "SrcCtz";
174 case IrInstSrcIdPopCount:
174 case Stage1ZirInstIdPopCount:
175175 return "SrcPopCount";
176 case IrInstSrcIdBswap:
176 case Stage1ZirInstIdBswap:
177177 return "SrcBswap";
178 case IrInstSrcIdBitReverse:
178 case Stage1ZirInstIdBitReverse:
179179 return "SrcBitReverse";
180 case IrInstSrcIdImport:
180 case Stage1ZirInstIdImport:
181181 return "SrcImport";
182 case IrInstSrcIdCImport:
182 case Stage1ZirInstIdCImport:
183183 return "SrcCImport";
184 case IrInstSrcIdCInclude:
184 case Stage1ZirInstIdCInclude:
185185 return "SrcCInclude";
186 case IrInstSrcIdCDefine:
186 case Stage1ZirInstIdCDefine:
187187 return "SrcCDefine";
188 case IrInstSrcIdCUndef:
188 case Stage1ZirInstIdCUndef:
189189 return "SrcCUndef";
190 case IrInstSrcIdRef:
190 case Stage1ZirInstIdRef:
191191 return "SrcRef";
192 case IrInstSrcIdCompileErr:
192 case Stage1ZirInstIdCompileErr:
193193 return "SrcCompileErr";
194 case IrInstSrcIdCompileLog:
194 case Stage1ZirInstIdCompileLog:
195195 return "SrcCompileLog";
196 case IrInstSrcIdErrName:
196 case Stage1ZirInstIdErrName:
197197 return "SrcErrName";
198 case IrInstSrcIdEmbedFile:
198 case Stage1ZirInstIdEmbedFile:
199199 return "SrcEmbedFile";
200 case IrInstSrcIdCmpxchg:
200 case Stage1ZirInstIdCmpxchg:
201201 return "SrcCmpxchg";
202 case IrInstSrcIdFence:
202 case Stage1ZirInstIdFence:
203203 return "SrcFence";
204 case IrInstSrcIdReduce:
204 case Stage1ZirInstIdReduce:
205205 return "SrcReduce";
206 case IrInstSrcIdTruncate:
206 case Stage1ZirInstIdTruncate:
207207 return "SrcTruncate";
208 case IrInstSrcIdIntCast:
208 case Stage1ZirInstIdIntCast:
209209 return "SrcIntCast";
210 case IrInstSrcIdFloatCast:
210 case Stage1ZirInstIdFloatCast:
211211 return "SrcFloatCast";
212 case IrInstSrcIdIntToFloat:
212 case Stage1ZirInstIdIntToFloat:
213213 return "SrcIntToFloat";
214 case IrInstSrcIdFloatToInt:
214 case Stage1ZirInstIdFloatToInt:
215215 return "SrcFloatToInt";
216 case IrInstSrcIdBoolToInt:
216 case Stage1ZirInstIdBoolToInt:
217217 return "SrcBoolToInt";
218 case IrInstSrcIdVectorType:
218 case Stage1ZirInstIdVectorType:
219219 return "SrcVectorType";
220 case IrInstSrcIdBoolNot:
220 case Stage1ZirInstIdBoolNot:
221221 return "SrcBoolNot";
222 case IrInstSrcIdMemset:
222 case Stage1ZirInstIdMemset:
223223 return "SrcMemset";
224 case IrInstSrcIdMemcpy:
224 case Stage1ZirInstIdMemcpy:
225225 return "SrcMemcpy";
226 case IrInstSrcIdSlice:
226 case Stage1ZirInstIdSlice:
227227 return "SrcSlice";
228 case IrInstSrcIdBreakpoint:
228 case Stage1ZirInstIdBreakpoint:
229229 return "SrcBreakpoint";
230 case IrInstSrcIdReturnAddress:
230 case Stage1ZirInstIdReturnAddress:
231231 return "SrcReturnAddress";
232 case IrInstSrcIdFrameAddress:
232 case Stage1ZirInstIdFrameAddress:
233233 return "SrcFrameAddress";
234 case IrInstSrcIdFrameHandle:
234 case Stage1ZirInstIdFrameHandle:
235235 return "SrcFrameHandle";
236 case IrInstSrcIdFrameType:
236 case Stage1ZirInstIdFrameType:
237237 return "SrcFrameType";
238 case IrInstSrcIdFrameSize:
238 case Stage1ZirInstIdFrameSize:
239239 return "SrcFrameSize";
240 case IrInstSrcIdAlignOf:
240 case Stage1ZirInstIdAlignOf:
241241 return "SrcAlignOf";
242 case IrInstSrcIdOverflowOp:
242 case Stage1ZirInstIdOverflowOp:
243243 return "SrcOverflowOp";
244 case IrInstSrcIdTestErr:
244 case Stage1ZirInstIdTestErr:
245245 return "SrcTestErr";
246 case IrInstSrcIdMulAdd:
246 case Stage1ZirInstIdMulAdd:
247247 return "SrcMulAdd";
248 case IrInstSrcIdFloatOp:
248 case Stage1ZirInstIdFloatOp:
249249 return "SrcFloatOp";
250 case IrInstSrcIdUnwrapErrCode:
250 case Stage1ZirInstIdUnwrapErrCode:
251251 return "SrcUnwrapErrCode";
252 case IrInstSrcIdUnwrapErrPayload:
252 case Stage1ZirInstIdUnwrapErrPayload:
253253 return "SrcUnwrapErrPayload";
254 case IrInstSrcIdFnProto:
254 case Stage1ZirInstIdFnProto:
255255 return "SrcFnProto";
256 case IrInstSrcIdTestComptime:
256 case Stage1ZirInstIdTestComptime:
257257 return "SrcTestComptime";
258 case IrInstSrcIdPtrCast:
258 case Stage1ZirInstIdPtrCast:
259259 return "SrcPtrCast";
260 case IrInstSrcIdBitCast:
260 case Stage1ZirInstIdBitCast:
261261 return "SrcBitCast";
262 case IrInstSrcIdIntToPtr:
262 case Stage1ZirInstIdIntToPtr:
263263 return "SrcIntToPtr";
264 case IrInstSrcIdPtrToInt:
264 case Stage1ZirInstIdPtrToInt:
265265 return "SrcPtrToInt";
266 case IrInstSrcIdIntToEnum:
266 case Stage1ZirInstIdIntToEnum:
267267 return "SrcIntToEnum";
268 case IrInstSrcIdEnumToInt:
268 case Stage1ZirInstIdEnumToInt:
269269 return "SrcEnumToInt";
270 case IrInstSrcIdIntToErr:
270 case Stage1ZirInstIdIntToErr:
271271 return "SrcIntToErr";
272 case IrInstSrcIdErrToInt:
272 case Stage1ZirInstIdErrToInt:
273273 return "SrcErrToInt";
274 case IrInstSrcIdCheckSwitchProngsUnderNo:
274 case Stage1ZirInstIdCheckSwitchProngsUnderNo:
275275 return "SrcCheckSwitchProngsUnderNo";
276 case IrInstSrcIdCheckSwitchProngsUnderYes:
276 case Stage1ZirInstIdCheckSwitchProngsUnderYes:
277277 return "SrcCheckSwitchProngsUnderYes";
278 case IrInstSrcIdCheckStatementIsVoid:
278 case Stage1ZirInstIdCheckStatementIsVoid:
279279 return "SrcCheckStatementIsVoid";
280 case IrInstSrcIdTypeName:
280 case Stage1ZirInstIdTypeName:
281281 return "SrcTypeName";
282 case IrInstSrcIdDeclRef:
282 case Stage1ZirInstIdDeclRef:
283283 return "SrcDeclRef";
284 case IrInstSrcIdPanic:
284 case Stage1ZirInstIdPanic:
285285 return "SrcPanic";
286 case IrInstSrcIdTagName:
286 case Stage1ZirInstIdTagName:
287287 return "SrcTagName";
288 case IrInstSrcIdFieldParentPtr:
288 case Stage1ZirInstIdFieldParentPtr:
289289 return "SrcFieldParentPtr";
290 case IrInstSrcIdOffsetOf:
290 case Stage1ZirInstIdOffsetOf:
291291 return "SrcOffsetOf";
292 case IrInstSrcIdBitOffsetOf:
292 case Stage1ZirInstIdBitOffsetOf:
293293 return "SrcBitOffsetOf";
294 case IrInstSrcIdTypeInfo:
294 case Stage1ZirInstIdTypeInfo:
295295 return "SrcTypeInfo";
296 case IrInstSrcIdType:
296 case Stage1ZirInstIdType:
297297 return "SrcType";
298 case IrInstSrcIdHasField:
298 case Stage1ZirInstIdHasField:
299299 return "SrcHasField";
300 case IrInstSrcIdSetEvalBranchQuota:
300 case Stage1ZirInstIdSetEvalBranchQuota:
301301 return "SrcSetEvalBranchQuota";
302 case IrInstSrcIdPtrType:
302 case Stage1ZirInstIdPtrType:
303303 return "SrcPtrType";
304 case IrInstSrcIdPtrTypeSimple:
304 case Stage1ZirInstIdPtrTypeSimple:
305305 return "SrcPtrTypeSimple";
306 case IrInstSrcIdPtrTypeSimpleConst:
306 case Stage1ZirInstIdPtrTypeSimpleConst:
307307 return "SrcPtrTypeSimpleConst";
308 case IrInstSrcIdAlignCast:
308 case Stage1ZirInstIdAlignCast:
309309 return "SrcAlignCast";
310 case IrInstSrcIdImplicitCast:
310 case Stage1ZirInstIdImplicitCast:
311311 return "SrcImplicitCast";
312 case IrInstSrcIdResolveResult:
312 case Stage1ZirInstIdResolveResult:
313313 return "SrcResolveResult";
314 case IrInstSrcIdResetResult:
314 case Stage1ZirInstIdResetResult:
315315 return "SrcResetResult";
316 case IrInstSrcIdSetAlignStack:
316 case Stage1ZirInstIdSetAlignStack:
317317 return "SrcSetAlignStack";
318 case IrInstSrcIdArgTypeAllowVarFalse:
318 case Stage1ZirInstIdArgTypeAllowVarFalse:
319319 return "SrcArgTypeAllowVarFalse";
320 case IrInstSrcIdArgTypeAllowVarTrue:
320 case Stage1ZirInstIdArgTypeAllowVarTrue:
321321 return "SrcArgTypeAllowVarTrue";
322 case IrInstSrcIdExport:
322 case Stage1ZirInstIdExport:
323323 return "SrcExport";
324 case IrInstSrcIdExtern:
324 case Stage1ZirInstIdExtern:
325325 return "SrcExtern";
326 case IrInstSrcIdErrorReturnTrace:
326 case Stage1ZirInstIdErrorReturnTrace:
327327 return "SrcErrorReturnTrace";
328 case IrInstSrcIdErrorUnion:
328 case Stage1ZirInstIdErrorUnion:
329329 return "SrcErrorUnion";
330 case IrInstSrcIdAtomicRmw:
330 case Stage1ZirInstIdAtomicRmw:
331331 return "SrcAtomicRmw";
332 case IrInstSrcIdAtomicLoad:
332 case Stage1ZirInstIdAtomicLoad:
333333 return "SrcAtomicLoad";
334 case IrInstSrcIdAtomicStore:
334 case Stage1ZirInstIdAtomicStore:
335335 return "SrcAtomicStore";
336 case IrInstSrcIdSaveErrRetAddr:
336 case Stage1ZirInstIdSaveErrRetAddr:
337337 return "SrcSaveErrRetAddr";
338 case IrInstSrcIdAddImplicitReturnType:
338 case Stage1ZirInstIdAddImplicitReturnType:
339339 return "SrcAddImplicitReturnType";
340 case IrInstSrcIdErrSetCast:
340 case Stage1ZirInstIdErrSetCast:
341341 return "SrcErrSetCast";
342 case IrInstSrcIdCheckRuntimeScope:
342 case Stage1ZirInstIdCheckRuntimeScope:
343343 return "SrcCheckRuntimeScope";
344 case IrInstSrcIdHasDecl:
344 case Stage1ZirInstIdHasDecl:
345345 return "SrcHasDecl";
346 case IrInstSrcIdUndeclaredIdent:
346 case Stage1ZirInstIdUndeclaredIdent:
347347 return "SrcUndeclaredIdent";
348 case IrInstSrcIdAlloca:
348 case Stage1ZirInstIdAlloca:
349349 return "SrcAlloca";
350 case IrInstSrcIdEndExpr:
350 case Stage1ZirInstIdEndExpr:
351351 return "SrcEndExpr";
352 case IrInstSrcIdUnionInitNamedField:
352 case Stage1ZirInstIdUnionInitNamedField:
353353 return "SrcUnionInitNamedField";
354 case IrInstSrcIdSuspendBegin:
354 case Stage1ZirInstIdSuspendBegin:
355355 return "SrcSuspendBegin";
356 case IrInstSrcIdSuspendFinish:
356 case Stage1ZirInstIdSuspendFinish:
357357 return "SrcSuspendFinish";
358 case IrInstSrcIdAwait:
358 case Stage1ZirInstIdAwait:
359359 return "SrcAwaitSr";
360 case IrInstSrcIdResume:
360 case Stage1ZirInstIdResume:
361361 return "SrcResume";
362 case IrInstSrcIdSpillBegin:
362 case Stage1ZirInstIdSpillBegin:
363363 return "SrcSpillBegin";
364 case IrInstSrcIdSpillEnd:
364 case Stage1ZirInstIdSpillEnd:
365365 return "SrcSpillEnd";
366 case IrInstSrcIdWasmMemorySize:
366 case Stage1ZirInstIdWasmMemorySize:
367367 return "SrcWasmMemorySize";
368 case IrInstSrcIdWasmMemoryGrow:
368 case Stage1ZirInstIdWasmMemoryGrow:
369369 return "SrcWasmMemoryGrow";
370 case IrInstSrcIdSrc:
370 case Stage1ZirInstIdSrc:
371371 return "SrcSrc";
372372 }
373373 zig_unreachable();
374374}
375375
376const char* ir_inst_gen_type_str(IrInstGenId id) {
376const char* ir_inst_gen_type_str(Stage1AirInstId id) {
377377 switch (id) {
378 case IrInstGenIdInvalid:
378 case Stage1AirInstIdInvalid:
379379 return "GenInvalid";
380 case IrInstGenIdShuffleVector:
380 case Stage1AirInstIdShuffleVector:
381381 return "GenShuffle";
382 case IrInstGenIdSplat:
382 case Stage1AirInstIdSplat:
383383 return "GenSplat";
384 case IrInstGenIdDeclVar:
384 case Stage1AirInstIdDeclVar:
385385 return "GenDeclVar";
386 case IrInstGenIdBr:
386 case Stage1AirInstIdBr:
387387 return "GenBr";
388 case IrInstGenIdCondBr:
388 case Stage1AirInstIdCondBr:
389389 return "GenCondBr";
390 case IrInstGenIdSwitchBr:
390 case Stage1AirInstIdSwitchBr:
391391 return "GenSwitchBr";
392 case IrInstGenIdPhi:
392 case Stage1AirInstIdPhi:
393393 return "GenPhi";
394 case IrInstGenIdBinOp:
394 case Stage1AirInstIdBinOp:
395395 return "GenBinOp";
396 case IrInstGenIdLoadPtr:
396 case Stage1AirInstIdLoadPtr:
397397 return "GenLoadPtr";
398 case IrInstGenIdStorePtr:
398 case Stage1AirInstIdStorePtr:
399399 return "GenStorePtr";
400 case IrInstGenIdVectorStoreElem:
400 case Stage1AirInstIdVectorStoreElem:
401401 return "GenVectorStoreElem";
402 case IrInstGenIdStructFieldPtr:
402 case Stage1AirInstIdStructFieldPtr:
403403 return "GenStructFieldPtr";
404 case IrInstGenIdUnionFieldPtr:
404 case Stage1AirInstIdUnionFieldPtr:
405405 return "GenUnionFieldPtr";
406 case IrInstGenIdElemPtr:
406 case Stage1AirInstIdElemPtr:
407407 return "GenElemPtr";
408 case IrInstGenIdVarPtr:
408 case Stage1AirInstIdVarPtr:
409409 return "GenVarPtr";
410 case IrInstGenIdReturnPtr:
410 case Stage1AirInstIdReturnPtr:
411411 return "GenReturnPtr";
412 case IrInstGenIdCall:
412 case Stage1AirInstIdCall:
413413 return "GenCall";
414 case IrInstGenIdConst:
414 case Stage1AirInstIdConst:
415415 return "GenConst";
416 case IrInstGenIdReturn:
416 case Stage1AirInstIdReturn:
417417 return "GenReturn";
418 case IrInstGenIdCast:
418 case Stage1AirInstIdCast:
419419 return "GenCast";
420 case IrInstGenIdUnreachable:
420 case Stage1AirInstIdUnreachable:
421421 return "GenUnreachable";
422 case IrInstGenIdAsm:
422 case Stage1AirInstIdAsm:
423423 return "GenAsm";
424 case IrInstGenIdTestNonNull:
424 case Stage1AirInstIdTestNonNull:
425425 return "GenTestNonNull";
426 case IrInstGenIdOptionalUnwrapPtr:
426 case Stage1AirInstIdOptionalUnwrapPtr:
427427 return "GenOptionalUnwrapPtr";
428 case IrInstGenIdOptionalWrap:
428 case Stage1AirInstIdOptionalWrap:
429429 return "GenOptionalWrap";
430 case IrInstGenIdUnionTag:
430 case Stage1AirInstIdUnionTag:
431431 return "GenUnionTag";
432 case IrInstGenIdClz:
432 case Stage1AirInstIdClz:
433433 return "GenClz";
434 case IrInstGenIdCtz:
434 case Stage1AirInstIdCtz:
435435 return "GenCtz";
436 case IrInstGenIdPopCount:
436 case Stage1AirInstIdPopCount:
437437 return "GenPopCount";
438 case IrInstGenIdBswap:
438 case Stage1AirInstIdBswap:
439439 return "GenBswap";
440 case IrInstGenIdBitReverse:
440 case Stage1AirInstIdBitReverse:
441441 return "GenBitReverse";
442 case IrInstGenIdRef:
442 case Stage1AirInstIdRef:
443443 return "GenRef";
444 case IrInstGenIdErrName:
444 case Stage1AirInstIdErrName:
445445 return "GenErrName";
446 case IrInstGenIdCmpxchg:
446 case Stage1AirInstIdCmpxchg:
447447 return "GenCmpxchg";
448 case IrInstGenIdFence:
448 case Stage1AirInstIdFence:
449449 return "GenFence";
450 case IrInstGenIdReduce:
450 case Stage1AirInstIdReduce:
451451 return "GenReduce";
452 case IrInstGenIdTruncate:
452 case Stage1AirInstIdTruncate:
453453 return "GenTruncate";
454 case IrInstGenIdBoolNot:
454 case Stage1AirInstIdBoolNot:
455455 return "GenBoolNot";
456 case IrInstGenIdMemset:
456 case Stage1AirInstIdMemset:
457457 return "GenMemset";
458 case IrInstGenIdMemcpy:
458 case Stage1AirInstIdMemcpy:
459459 return "GenMemcpy";
460 case IrInstGenIdSlice:
460 case Stage1AirInstIdSlice:
461461 return "GenSlice";
462 case IrInstGenIdBreakpoint:
462 case Stage1AirInstIdBreakpoint:
463463 return "GenBreakpoint";
464 case IrInstGenIdReturnAddress:
464 case Stage1AirInstIdReturnAddress:
465465 return "GenReturnAddress";
466 case IrInstGenIdFrameAddress:
466 case Stage1AirInstIdFrameAddress:
467467 return "GenFrameAddress";
468 case IrInstGenIdFrameHandle:
468 case Stage1AirInstIdFrameHandle:
469469 return "GenFrameHandle";
470 case IrInstGenIdFrameSize:
470 case Stage1AirInstIdFrameSize:
471471 return "GenFrameSize";
472 case IrInstGenIdOverflowOp:
472 case Stage1AirInstIdOverflowOp:
473473 return "GenOverflowOp";
474 case IrInstGenIdTestErr:
474 case Stage1AirInstIdTestErr:
475475 return "GenTestErr";
476 case IrInstGenIdMulAdd:
476 case Stage1AirInstIdMulAdd:
477477 return "GenMulAdd";
478 case IrInstGenIdFloatOp:
478 case Stage1AirInstIdFloatOp:
479479 return "GenFloatOp";
480 case IrInstGenIdUnwrapErrCode:
480 case Stage1AirInstIdUnwrapErrCode:
481481 return "GenUnwrapErrCode";
482 case IrInstGenIdUnwrapErrPayload:
482 case Stage1AirInstIdUnwrapErrPayload:
483483 return "GenUnwrapErrPayload";
484 case IrInstGenIdErrWrapCode:
484 case Stage1AirInstIdErrWrapCode:
485485 return "GenErrWrapCode";
486 case IrInstGenIdErrWrapPayload:
486 case Stage1AirInstIdErrWrapPayload:
487487 return "GenErrWrapPayload";
488 case IrInstGenIdPtrCast:
488 case Stage1AirInstIdPtrCast:
489489 return "GenPtrCast";
490 case IrInstGenIdBitCast:
490 case Stage1AirInstIdBitCast:
491491 return "GenBitCast";
492 case IrInstGenIdWidenOrShorten:
492 case Stage1AirInstIdWidenOrShorten:
493493 return "GenWidenOrShorten";
494 case IrInstGenIdIntToPtr:
494 case Stage1AirInstIdIntToPtr:
495495 return "GenIntToPtr";
496 case IrInstGenIdPtrToInt:
496 case Stage1AirInstIdPtrToInt:
497497 return "GenPtrToInt";
498 case IrInstGenIdIntToEnum:
498 case Stage1AirInstIdIntToEnum:
499499 return "GenIntToEnum";
500 case IrInstGenIdIntToErr:
500 case Stage1AirInstIdIntToErr:
501501 return "GenIntToErr";
502 case IrInstGenIdErrToInt:
502 case Stage1AirInstIdErrToInt:
503503 return "GenErrToInt";
504 case IrInstGenIdPanic:
504 case Stage1AirInstIdPanic:
505505 return "GenPanic";
506 case IrInstGenIdTagName:
506 case Stage1AirInstIdTagName:
507507 return "GenTagName";
508 case IrInstGenIdFieldParentPtr:
508 case Stage1AirInstIdFieldParentPtr:
509509 return "GenFieldParentPtr";
510 case IrInstGenIdAlignCast:
510 case Stage1AirInstIdAlignCast:
511511 return "GenAlignCast";
512 case IrInstGenIdErrorReturnTrace:
512 case Stage1AirInstIdErrorReturnTrace:
513513 return "GenErrorReturnTrace";
514 case IrInstGenIdAtomicRmw:
514 case Stage1AirInstIdAtomicRmw:
515515 return "GenAtomicRmw";
516 case IrInstGenIdAtomicLoad:
516 case Stage1AirInstIdAtomicLoad:
517517 return "GenAtomicLoad";
518 case IrInstGenIdAtomicStore:
518 case Stage1AirInstIdAtomicStore:
519519 return "GenAtomicStore";
520 case IrInstGenIdSaveErrRetAddr:
520 case Stage1AirInstIdSaveErrRetAddr:
521521 return "GenSaveErrRetAddr";
522 case IrInstGenIdVectorToArray:
522 case Stage1AirInstIdVectorToArray:
523523 return "GenVectorToArray";
524 case IrInstGenIdArrayToVector:
524 case Stage1AirInstIdArrayToVector:
525525 return "GenArrayToVector";
526 case IrInstGenIdAssertZero:
526 case Stage1AirInstIdAssertZero:
527527 return "GenAssertZero";
528 case IrInstGenIdAssertNonNull:
528 case Stage1AirInstIdAssertNonNull:
529529 return "GenAssertNonNull";
530 case IrInstGenIdAlloca:
530 case Stage1AirInstIdAlloca:
531531 return "GenAlloca";
532 case IrInstGenIdPtrOfArrayToSlice:
532 case Stage1AirInstIdPtrOfArrayToSlice:
533533 return "GenPtrOfArrayToSlice";
534 case IrInstGenIdSuspendBegin:
534 case Stage1AirInstIdSuspendBegin:
535535 return "GenSuspendBegin";
536 case IrInstGenIdSuspendFinish:
536 case Stage1AirInstIdSuspendFinish:
537537 return "GenSuspendFinish";
538 case IrInstGenIdAwait:
538 case Stage1AirInstIdAwait:
539539 return "GenAwait";
540 case IrInstGenIdResume:
540 case Stage1AirInstIdResume:
541541 return "GenResume";
542 case IrInstGenIdSpillBegin:
542 case Stage1AirInstIdSpillBegin:
543543 return "GenSpillBegin";
544 case IrInstGenIdSpillEnd:
544 case Stage1AirInstIdSpillEnd:
545545 return "GenSpillEnd";
546 case IrInstGenIdVectorExtractElem:
546 case Stage1AirInstIdVectorExtractElem:
547547 return "GenVectorExtractElem";
548 case IrInstGenIdBinaryNot:
548 case Stage1AirInstIdBinaryNot:
549549 return "GenBinaryNot";
550 case IrInstGenIdNegation:
550 case Stage1AirInstIdNegation:
551551 return "GenNegation";
552 case IrInstGenIdWasmMemorySize:
552 case Stage1AirInstIdWasmMemorySize:
553553 return "GenWasmMemorySize";
554 case IrInstGenIdWasmMemoryGrow:
554 case Stage1AirInstIdWasmMemoryGrow:
555555 return "GenWasmMemoryGrow";
556 case IrInstGenIdExtern:
556 case Stage1AirInstIdExtern:
557557 return "GenExtrern";
558558 }
559559 zig_unreachable();
......@@ -571,12 +571,12 @@ static void ir_print_indent_gen(IrPrintGen *irp) {
571571 }
572572}
573573
574static void ir_print_prefix_src(IrPrintSrc *irp, IrInstSrc *instruction, bool trailing) {
574static void ir_print_prefix_src(IrPrintSrc *irp, Stage1ZirInst *instruction, bool trailing) {
575575 ir_print_indent_src(irp);
576576 const char mark = trailing ? ':' : '#';
577577 const char *type_name;
578 if (instruction->id == IrInstSrcIdConst) {
579 type_name = buf_ptr(&reinterpret_cast<IrInstSrcConst *>(instruction)->value->type->name);
578 if (instruction->id == Stage1ZirInstIdConst) {
579 type_name = buf_ptr(&reinterpret_cast<Stage1ZirInstConst *>(instruction)->value->type->name);
580580 } else {
581581 type_name = "(unknown)";
582582 }
......@@ -586,7 +586,7 @@ static void ir_print_prefix_src(IrPrintSrc *irp, IrInstSrc *instruction, bool tr
586586 ir_inst_src_type_str(instruction->id), type_name, ref_count);
587587}
588588
589static void ir_print_prefix_gen(IrPrintGen *irp, IrInstGen *instruction, bool trailing) {
589static void ir_print_prefix_gen(IrPrintGen *irp, Stage1AirInst *instruction, bool trailing) {
590590 ir_print_indent_gen(irp);
591591 const char mark = trailing ? ':' : '#';
592592 const char *type_name = instruction->value->type ? buf_ptr(&instruction->value->type->name) : "(unknown)";
......@@ -596,11 +596,11 @@ static void ir_print_prefix_gen(IrPrintGen *irp, IrInstGen *instruction, bool tr
596596 ir_inst_gen_type_str(instruction->id), type_name, ref_count);
597597}
598598
599static void ir_print_var_src(IrPrintSrc *irp, IrInstSrc *inst) {
599static void ir_print_var_src(IrPrintSrc *irp, Stage1ZirInst *inst) {
600600 fprintf(irp->f, "#%" PRIu32 "", inst->debug_id);
601601}
602602
603static void ir_print_var_gen(IrPrintGen *irp, IrInstGen *inst) {
603static void ir_print_var_gen(IrPrintGen *irp, Stage1AirInst *inst) {
604604 fprintf(irp->f, "#%" PRIu32 "", inst->debug_id);
605605 if (irp->printed.maybe_get(inst) == nullptr) {
606606 irp->printed.put(inst, 0);
......@@ -608,7 +608,7 @@ static void ir_print_var_gen(IrPrintGen *irp, IrInstGen *inst) {
608608 }
609609}
610610
611static void ir_print_other_inst_src(IrPrintSrc *irp, IrInstSrc *inst) {
611static void ir_print_other_inst_src(IrPrintSrc *irp, Stage1ZirInst *inst) {
612612 if (inst == nullptr) {
613613 fprintf(irp->f, "(null)");
614614 return;
......@@ -623,7 +623,7 @@ static void ir_print_const_value(CodeGen *g, FILE *f, ZigValue *const_val) {
623623 fprintf(f, "%s", buf_ptr(&buf));
624624}
625625
626static void ir_print_other_inst_gen(IrPrintGen *irp, IrInstGen *inst) {
626static void ir_print_other_inst_gen(IrPrintGen *irp, Stage1AirInst *inst) {
627627 if (inst == nullptr) {
628628 fprintf(irp->f, "(null)");
629629 } else {
......@@ -639,7 +639,7 @@ static void ir_print_other_block(IrPrintSrc *irp, Stage1ZirBasicBlock *bb) {
639639 }
640640}
641641
642static void ir_print_other_block_gen(IrPrintGen *irp, IrBasicBlockGen *bb) {
642static void ir_print_other_block_gen(IrPrintGen *irp, Stage1AirBasicBlock *bb) {
643643 if (bb == nullptr) {
644644 fprintf(irp->f, "(null block)");
645645 } else {
......@@ -647,21 +647,21 @@ static void ir_print_other_block_gen(IrPrintGen *irp, IrBasicBlockGen *bb) {
647647 }
648648}
649649
650static void ir_print_return_src(IrPrintSrc *irp, IrInstSrcReturn *inst) {
650static void ir_print_return_src(IrPrintSrc *irp, Stage1ZirInstReturn *inst) {
651651 fprintf(irp->f, "return ");
652652 ir_print_other_inst_src(irp, inst->operand);
653653}
654654
655static void ir_print_return_gen(IrPrintGen *irp, IrInstGenReturn *inst) {
655static void ir_print_return_gen(IrPrintGen *irp, Stage1AirInstReturn *inst) {
656656 fprintf(irp->f, "return ");
657657 ir_print_other_inst_gen(irp, inst->operand);
658658}
659659
660static void ir_print_const(IrPrintSrc *irp, IrInstSrcConst *const_instruction) {
660static void ir_print_const(IrPrintSrc *irp, Stage1ZirInstConst *const_instruction) {
661661 ir_print_const_value(irp->codegen, irp->f, const_instruction->value);
662662}
663663
664static void ir_print_const(IrPrintGen *irp, IrInstGenConst *const_instruction) {
664static void ir_print_const(IrPrintGen *irp, Stage1AirInstConst *const_instruction) {
665665 ir_print_const_value(irp->codegen, irp->f, const_instruction->base.value);
666666}
667667
......@@ -751,12 +751,12 @@ static const char *ir_un_op_id_str(IrUnOp op_id) {
751751 zig_unreachable();
752752}
753753
754static void ir_print_un_op(IrPrintSrc *irp, IrInstSrcUnOp *inst) {
754static void ir_print_un_op(IrPrintSrc *irp, Stage1ZirInstUnOp *inst) {
755755 fprintf(irp->f, "%s ", ir_un_op_id_str(inst->op_id));
756756 ir_print_other_inst_src(irp, inst->value);
757757}
758758
759static void ir_print_bin_op(IrPrintSrc *irp, IrInstSrcBinOp *bin_op_instruction) {
759static void ir_print_bin_op(IrPrintSrc *irp, Stage1ZirInstBinOp *bin_op_instruction) {
760760 ir_print_other_inst_src(irp, bin_op_instruction->op1);
761761 fprintf(irp->f, " %s ", ir_bin_op_id_str(bin_op_instruction->op_id));
762762 ir_print_other_inst_src(irp, bin_op_instruction->op2);
......@@ -765,7 +765,7 @@ static void ir_print_bin_op(IrPrintSrc *irp, IrInstSrcBinOp *bin_op_instruction)
765765 }
766766}
767767
768static void ir_print_bin_op(IrPrintGen *irp, IrInstGenBinOp *bin_op_instruction) {
768static void ir_print_bin_op(IrPrintGen *irp, Stage1AirInstBinOp *bin_op_instruction) {
769769 ir_print_other_inst_gen(irp, bin_op_instruction->op1);
770770 fprintf(irp->f, " %s ", ir_bin_op_id_str(bin_op_instruction->op_id));
771771 ir_print_other_inst_gen(irp, bin_op_instruction->op2);
......@@ -774,7 +774,7 @@ static void ir_print_bin_op(IrPrintGen *irp, IrInstGenBinOp *bin_op_instruction)
774774 }
775775}
776776
777static void ir_print_merge_err_sets(IrPrintSrc *irp, IrInstSrcMergeErrSets *instruction) {
777static void ir_print_merge_err_sets(IrPrintSrc *irp, Stage1ZirInstMergeErrSets *instruction) {
778778 ir_print_other_inst_src(irp, instruction->op1);
779779 fprintf(irp->f, " || ");
780780 ir_print_other_inst_src(irp, instruction->op2);
......@@ -783,7 +783,7 @@ static void ir_print_merge_err_sets(IrPrintSrc *irp, IrInstSrcMergeErrSets *inst
783783 }
784784}
785785
786static void ir_print_decl_var_src(IrPrintSrc *irp, IrInstSrcDeclVar *decl_var_instruction) {
786static void ir_print_decl_var_src(IrPrintSrc *irp, Stage1ZirInstDeclVar *decl_var_instruction) {
787787 const char *var_or_const = decl_var_instruction->var->gen_is_const ? "const" : "var";
788788 const char *name = decl_var_instruction->var->name;
789789 if (decl_var_instruction->var_type) {
......@@ -820,7 +820,7 @@ static const char *cast_op_str(CastOp op) {
820820 zig_unreachable();
821821}
822822
823static void ir_print_cast(IrPrintGen *irp, IrInstGenCast *cast_instruction) {
823static void ir_print_cast(IrPrintGen *irp, Stage1AirInstCast *cast_instruction) {
824824 fprintf(irp->f, "%s cast ", cast_op_str(cast_instruction->cast_op));
825825 ir_print_other_inst_gen(irp, cast_instruction->value);
826826}
......@@ -882,7 +882,7 @@ static void ir_print_result_loc(IrPrintSrc *irp, ResultLoc *result_loc) {
882882 zig_unreachable();
883883}
884884
885static void ir_print_call_extra(IrPrintSrc *irp, IrInstSrcCallExtra *instruction) {
885static void ir_print_call_extra(IrPrintSrc *irp, Stage1ZirInstCallExtra *instruction) {
886886 fprintf(irp->f, "opts=");
887887 ir_print_other_inst_src(irp, instruction->options);
888888 fprintf(irp->f, ", fn=");
......@@ -893,7 +893,7 @@ static void ir_print_call_extra(IrPrintSrc *irp, IrInstSrcCallExtra *instruction
893893 ir_print_result_loc(irp, instruction->result_loc);
894894}
895895
896static void ir_print_async_call_extra(IrPrintSrc *irp, IrInstSrcAsyncCallExtra *instruction) {
896static void ir_print_async_call_extra(IrPrintSrc *irp, Stage1ZirInstAsyncCallExtra *instruction) {
897897 fprintf(irp->f, "modifier=");
898898 ir_print_call_modifier(irp->f, instruction->modifier);
899899 fprintf(irp->f, ", fn=");
......@@ -910,14 +910,14 @@ static void ir_print_async_call_extra(IrPrintSrc *irp, IrInstSrcAsyncCallExtra *
910910 ir_print_result_loc(irp, instruction->result_loc);
911911}
912912
913static void ir_print_call_args(IrPrintSrc *irp, IrInstSrcCallArgs *instruction) {
913static void ir_print_call_args(IrPrintSrc *irp, Stage1ZirInstCallArgs *instruction) {
914914 fprintf(irp->f, "opts=");
915915 ir_print_other_inst_src(irp, instruction->options);
916916 fprintf(irp->f, ", fn=");
917917 ir_print_other_inst_src(irp, instruction->fn_ref);
918918 fprintf(irp->f, ", args=(");
919919 for (size_t i = 0; i < instruction->args_len; i += 1) {
920 IrInstSrc *arg = instruction->args_ptr[i];
920 Stage1ZirInst *arg = instruction->args_ptr[i];
921921 if (i != 0)
922922 fprintf(irp->f, ", ");
923923 ir_print_other_inst_src(irp, arg);
......@@ -926,7 +926,7 @@ static void ir_print_call_args(IrPrintSrc *irp, IrInstSrcCallArgs *instruction)
926926 ir_print_result_loc(irp, instruction->result_loc);
927927}
928928
929static void ir_print_call_src(IrPrintSrc *irp, IrInstSrcCall *call_instruction) {
929static void ir_print_call_src(IrPrintSrc *irp, Stage1ZirInstCall *call_instruction) {
930930 ir_print_call_modifier(irp->f, call_instruction->modifier);
931931 if (call_instruction->fn_entry) {
932932 fprintf(irp->f, "%s", buf_ptr(&call_instruction->fn_entry->symbol_name));
......@@ -936,7 +936,7 @@ static void ir_print_call_src(IrPrintSrc *irp, IrInstSrcCall *call_instruction)
936936 }
937937 fprintf(irp->f, "(");
938938 for (size_t i = 0; i < call_instruction->arg_count; i += 1) {
939 IrInstSrc *arg = call_instruction->args[i];
939 Stage1ZirInst *arg = call_instruction->args[i];
940940 if (i != 0)
941941 fprintf(irp->f, ", ");
942942 ir_print_other_inst_src(irp, arg);
......@@ -945,7 +945,7 @@ static void ir_print_call_src(IrPrintSrc *irp, IrInstSrcCall *call_instruction)
945945 ir_print_result_loc(irp, call_instruction->result_loc);
946946}
947947
948static void ir_print_call_gen(IrPrintGen *irp, IrInstGenCall *call_instruction) {
948static void ir_print_call_gen(IrPrintGen *irp, Stage1AirInstCall *call_instruction) {
949949 ir_print_call_modifier(irp->f, call_instruction->modifier);
950950 if (call_instruction->fn_entry) {
951951 fprintf(irp->f, "%s", buf_ptr(&call_instruction->fn_entry->symbol_name));
......@@ -955,7 +955,7 @@ static void ir_print_call_gen(IrPrintGen *irp, IrInstGenCall *call_instruction)
955955 }
956956 fprintf(irp->f, "(");
957957 for (size_t i = 0; i < call_instruction->arg_count; i += 1) {
958 IrInstGen *arg = call_instruction->args[i];
958 Stage1AirInst *arg = call_instruction->args[i];
959959 if (i != 0)
960960 fprintf(irp->f, ", ");
961961 ir_print_other_inst_gen(irp, arg);
......@@ -964,7 +964,7 @@ static void ir_print_call_gen(IrPrintGen *irp, IrInstGenCall *call_instruction)
964964 ir_print_other_inst_gen(irp, call_instruction->result_loc);
965965}
966966
967static void ir_print_cond_br(IrPrintSrc *irp, IrInstSrcCondBr *inst) {
967static void ir_print_cond_br(IrPrintSrc *irp, Stage1ZirInstCondBr *inst) {
968968 fprintf(irp->f, "if (");
969969 ir_print_other_inst_src(irp, inst->condition);
970970 fprintf(irp->f, ") ");
......@@ -977,7 +977,7 @@ static void ir_print_cond_br(IrPrintSrc *irp, IrInstSrcCondBr *inst) {
977977 }
978978}
979979
980static void ir_print_cond_br(IrPrintGen *irp, IrInstGenCondBr *inst) {
980static void ir_print_cond_br(IrPrintGen *irp, Stage1AirInstCondBr *inst) {
981981 fprintf(irp->f, "if (");
982982 ir_print_other_inst_gen(irp, inst->condition);
983983 fprintf(irp->f, ") ");
......@@ -986,7 +986,7 @@ static void ir_print_cond_br(IrPrintGen *irp, IrInstGenCondBr *inst) {
986986 ir_print_other_block_gen(irp, inst->else_block);
987987}
988988
989static void ir_print_br(IrPrintSrc *irp, IrInstSrcBr *br_instruction) {
989static void ir_print_br(IrPrintSrc *irp, Stage1ZirInstBr *br_instruction) {
990990 fprintf(irp->f, "goto ");
991991 ir_print_other_block(irp, br_instruction->dest_block);
992992 if (br_instruction->is_comptime != nullptr) {
......@@ -995,17 +995,17 @@ static void ir_print_br(IrPrintSrc *irp, IrInstSrcBr *br_instruction) {
995995 }
996996}
997997
998static void ir_print_br(IrPrintGen *irp, IrInstGenBr *inst) {
998static void ir_print_br(IrPrintGen *irp, Stage1AirInstBr *inst) {
999999 fprintf(irp->f, "goto ");
10001000 ir_print_other_block_gen(irp, inst->dest_block);
10011001}
10021002
1003static void ir_print_phi(IrPrintSrc *irp, IrInstSrcPhi *phi_instruction) {
1003static void ir_print_phi(IrPrintSrc *irp, Stage1ZirInstPhi *phi_instruction) {
10041004 assert(phi_instruction->incoming_count != 0);
10051005 assert(phi_instruction->incoming_count != SIZE_MAX);
10061006 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
10071007 Stage1ZirBasicBlock *incoming_block = phi_instruction->incoming_blocks[i];
1008 IrInstSrc *incoming_value = phi_instruction->incoming_values[i];
1008 Stage1ZirInst *incoming_value = phi_instruction->incoming_values[i];
10091009 if (i != 0)
10101010 fprintf(irp->f, " ");
10111011 ir_print_other_block(irp, incoming_block);
......@@ -1014,12 +1014,12 @@ static void ir_print_phi(IrPrintSrc *irp, IrInstSrcPhi *phi_instruction) {
10141014 }
10151015}
10161016
1017static void ir_print_phi(IrPrintGen *irp, IrInstGenPhi *phi_instruction) {
1017static void ir_print_phi(IrPrintGen *irp, Stage1AirInstPhi *phi_instruction) {
10181018 assert(phi_instruction->incoming_count != 0);
10191019 assert(phi_instruction->incoming_count != SIZE_MAX);
10201020 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
1021 IrBasicBlockGen *incoming_block = phi_instruction->incoming_blocks[i];
1022 IrInstGen *incoming_value = phi_instruction->incoming_values[i];
1021 Stage1AirBasicBlock *incoming_block = phi_instruction->incoming_blocks[i];
1022 Stage1AirInst *incoming_value = phi_instruction->incoming_values[i];
10231023 if (i != 0)
10241024 fprintf(irp->f, " ");
10251025 ir_print_other_block_gen(irp, incoming_block);
......@@ -1028,13 +1028,13 @@ static void ir_print_phi(IrPrintGen *irp, IrInstGenPhi *phi_instruction) {
10281028 }
10291029}
10301030
1031static void ir_print_container_init_list(IrPrintSrc *irp, IrInstSrcContainerInitList *instruction) {
1031static void ir_print_container_init_list(IrPrintSrc *irp, Stage1ZirInstContainerInitList *instruction) {
10321032 fprintf(irp->f, "{");
10331033 if (instruction->item_count > 50) {
10341034 fprintf(irp->f, "...(%" ZIG_PRI_usize " items)...", instruction->item_count);
10351035 } else {
10361036 for (size_t i = 0; i < instruction->item_count; i += 1) {
1037 IrInstSrc *result_loc = instruction->elem_result_loc_list[i];
1037 Stage1ZirInst *result_loc = instruction->elem_result_loc_list[i];
10381038 if (i != 0)
10391039 fprintf(irp->f, ", ");
10401040 ir_print_other_inst_src(irp, result_loc);
......@@ -1044,10 +1044,10 @@ static void ir_print_container_init_list(IrPrintSrc *irp, IrInstSrcContainerInit
10441044 ir_print_other_inst_src(irp, instruction->result_loc);
10451045}
10461046
1047static void ir_print_container_init_fields(IrPrintSrc *irp, IrInstSrcContainerInitFields *instruction) {
1047static void ir_print_container_init_fields(IrPrintSrc *irp, Stage1ZirInstContainerInitFields *instruction) {
10481048 fprintf(irp->f, "{");
10491049 for (size_t i = 0; i < instruction->field_count; i += 1) {
1050 IrInstSrcContainerInitFieldsField *field = &instruction->fields[i];
1050 Stage1ZirInstContainerInitFieldsField *field = &instruction->fields[i];
10511051 const char *comma = (i == 0) ? "" : ", ";
10521052 fprintf(irp->f, "%s.%s = ", comma, buf_ptr(field->name));
10531053 ir_print_other_inst_src(irp, field->result_loc);
......@@ -1056,15 +1056,15 @@ static void ir_print_container_init_fields(IrPrintSrc *irp, IrInstSrcContainerIn
10561056 ir_print_other_inst_src(irp, instruction->result_loc);
10571057}
10581058
1059static void ir_print_unreachable(IrPrintSrc *irp, IrInstSrcUnreachable *instruction) {
1059static void ir_print_unreachable(IrPrintSrc *irp, Stage1ZirInstUnreachable *instruction) {
10601060 fprintf(irp->f, "unreachable");
10611061}
10621062
1063static void ir_print_unreachable(IrPrintGen *irp, IrInstGenUnreachable *instruction) {
1063static void ir_print_unreachable(IrPrintGen *irp, Stage1AirInstUnreachable *instruction) {
10641064 fprintf(irp->f, "unreachable");
10651065}
10661066
1067static void ir_print_elem_ptr(IrPrintSrc *irp, IrInstSrcElemPtr *instruction) {
1067static void ir_print_elem_ptr(IrPrintSrc *irp, Stage1ZirInstElemPtr *instruction) {
10681068 fprintf(irp->f, "&");
10691069 ir_print_other_inst_src(irp, instruction->array_ptr);
10701070 fprintf(irp->f, "[");
......@@ -1075,7 +1075,7 @@ static void ir_print_elem_ptr(IrPrintSrc *irp, IrInstSrcElemPtr *instruction) {
10751075 }
10761076}
10771077
1078static void ir_print_elem_ptr(IrPrintGen *irp, IrInstGenElemPtr *instruction) {
1078static void ir_print_elem_ptr(IrPrintGen *irp, Stage1AirInstElemPtr *instruction) {
10791079 fprintf(irp->f, "&");
10801080 ir_print_other_inst_gen(irp, instruction->array_ptr);
10811081 fprintf(irp->f, "[");
......@@ -1086,45 +1086,45 @@ static void ir_print_elem_ptr(IrPrintGen *irp, IrInstGenElemPtr *instruction) {
10861086 }
10871087}
10881088
1089static void ir_print_var_ptr(IrPrintSrc *irp, IrInstSrcVarPtr *instruction) {
1089static void ir_print_var_ptr(IrPrintSrc *irp, Stage1ZirInstVarPtr *instruction) {
10901090 fprintf(irp->f, "&%s", instruction->var->name);
10911091}
10921092
1093static void ir_print_var_ptr(IrPrintGen *irp, IrInstGenVarPtr *instruction) {
1093static void ir_print_var_ptr(IrPrintGen *irp, Stage1AirInstVarPtr *instruction) {
10941094 fprintf(irp->f, "&%s", instruction->var->name);
10951095}
10961096
1097static void ir_print_return_ptr(IrPrintGen *irp, IrInstGenReturnPtr *instruction) {
1097static void ir_print_return_ptr(IrPrintGen *irp, Stage1AirInstReturnPtr *instruction) {
10981098 fprintf(irp->f, "@ReturnPtr");
10991099}
11001100
1101static void ir_print_load_ptr(IrPrintSrc *irp, IrInstSrcLoadPtr *instruction) {
1101static void ir_print_load_ptr(IrPrintSrc *irp, Stage1ZirInstLoadPtr *instruction) {
11021102 ir_print_other_inst_src(irp, instruction->ptr);
11031103 fprintf(irp->f, ".*");
11041104}
11051105
1106static void ir_print_load_ptr_gen(IrPrintGen *irp, IrInstGenLoadPtr *instruction) {
1106static void ir_print_load_ptr_gen(IrPrintGen *irp, Stage1AirInstLoadPtr *instruction) {
11071107 fprintf(irp->f, "loadptr(");
11081108 ir_print_other_inst_gen(irp, instruction->ptr);
11091109 fprintf(irp->f, ")result=");
11101110 ir_print_other_inst_gen(irp, instruction->result_loc);
11111111}
11121112
1113static void ir_print_store_ptr(IrPrintSrc *irp, IrInstSrcStorePtr *instruction) {
1113static void ir_print_store_ptr(IrPrintSrc *irp, Stage1ZirInstStorePtr *instruction) {
11141114 fprintf(irp->f, "*");
11151115 ir_print_var_src(irp, instruction->ptr);
11161116 fprintf(irp->f, " = ");
11171117 ir_print_other_inst_src(irp, instruction->value);
11181118}
11191119
1120static void ir_print_store_ptr(IrPrintGen *irp, IrInstGenStorePtr *instruction) {
1120static void ir_print_store_ptr(IrPrintGen *irp, Stage1AirInstStorePtr *instruction) {
11211121 fprintf(irp->f, "*");
11221122 ir_print_var_gen(irp, instruction->ptr);
11231123 fprintf(irp->f, " = ");
11241124 ir_print_other_inst_gen(irp, instruction->value);
11251125}
11261126
1127static void ir_print_vector_store_elem(IrPrintGen *irp, IrInstGenVectorStoreElem *instruction) {
1127static void ir_print_vector_store_elem(IrPrintGen *irp, Stage1AirInstVectorStoreElem *instruction) {
11281128 fprintf(irp->f, "vector_ptr=");
11291129 ir_print_var_gen(irp, instruction->vector_ptr);
11301130 fprintf(irp->f, ",index=");
......@@ -1133,7 +1133,7 @@ static void ir_print_vector_store_elem(IrPrintGen *irp, IrInstGenVectorStoreElem
11331133 ir_print_other_inst_gen(irp, instruction->value);
11341134}
11351135
1136static void ir_print_typeof(IrPrintSrc *irp, IrInstSrcTypeOf *instruction) {
1136static void ir_print_typeof(IrPrintSrc *irp, Stage1ZirInstTypeOf *instruction) {
11371137 fprintf(irp->f, "@TypeOf(");
11381138 if (instruction->value_count == 1) {
11391139 ir_print_other_inst_src(irp, instruction->value.scalar);
......@@ -1145,17 +1145,17 @@ static void ir_print_typeof(IrPrintSrc *irp, IrInstSrcTypeOf *instruction) {
11451145 fprintf(irp->f, ")");
11461146}
11471147
1148static void ir_print_binary_not(IrPrintGen *irp, IrInstGenBinaryNot *instruction) {
1148static void ir_print_binary_not(IrPrintGen *irp, Stage1AirInstBinaryNot *instruction) {
11491149 fprintf(irp->f, "~");
11501150 ir_print_other_inst_gen(irp, instruction->operand);
11511151}
11521152
1153static void ir_print_negation(IrPrintGen *irp, IrInstGenNegation *instruction) {
1153static void ir_print_negation(IrPrintGen *irp, Stage1AirInstNegation *instruction) {
11541154 fprintf(irp->f, instruction->wrapping ? "-%%" : "-");
11551155 ir_print_other_inst_gen(irp, instruction->operand);
11561156}
11571157
1158static void ir_print_field_ptr(IrPrintSrc *irp, IrInstSrcFieldPtr *instruction) {
1158static void ir_print_field_ptr(IrPrintSrc *irp, Stage1ZirInstFieldPtr *instruction) {
11591159 if (instruction->field_name_buffer) {
11601160 fprintf(irp->f, "fieldptr ");
11611161 ir_print_other_inst_src(irp, instruction->container_ptr);
......@@ -1170,33 +1170,33 @@ static void ir_print_field_ptr(IrPrintSrc *irp, IrInstSrcFieldPtr *instruction)
11701170 }
11711171}
11721172
1173static void ir_print_struct_field_ptr(IrPrintGen *irp, IrInstGenStructFieldPtr *instruction) {
1173static void ir_print_struct_field_ptr(IrPrintGen *irp, Stage1AirInstStructFieldPtr *instruction) {
11741174 fprintf(irp->f, "@StructFieldPtr(&");
11751175 ir_print_other_inst_gen(irp, instruction->struct_ptr);
11761176 fprintf(irp->f, ".%s", buf_ptr(instruction->field->name));
11771177 fprintf(irp->f, ")");
11781178}
11791179
1180static void ir_print_union_field_ptr(IrPrintGen *irp, IrInstGenUnionFieldPtr *instruction) {
1180static void ir_print_union_field_ptr(IrPrintGen *irp, Stage1AirInstUnionFieldPtr *instruction) {
11811181 fprintf(irp->f, "@UnionFieldPtr(&");
11821182 ir_print_other_inst_gen(irp, instruction->union_ptr);
11831183 fprintf(irp->f, ".%s", buf_ptr(instruction->field->enum_field->name));
11841184 fprintf(irp->f, ")");
11851185}
11861186
1187static void ir_print_set_cold(IrPrintSrc *irp, IrInstSrcSetCold *instruction) {
1187static void ir_print_set_cold(IrPrintSrc *irp, Stage1ZirInstSetCold *instruction) {
11881188 fprintf(irp->f, "@setCold(");
11891189 ir_print_other_inst_src(irp, instruction->is_cold);
11901190 fprintf(irp->f, ")");
11911191}
11921192
1193static void ir_print_set_runtime_safety(IrPrintSrc *irp, IrInstSrcSetRuntimeSafety *instruction) {
1193static void ir_print_set_runtime_safety(IrPrintSrc *irp, Stage1ZirInstSetRuntimeSafety *instruction) {
11941194 fprintf(irp->f, "@setRuntimeSafety(");
11951195 ir_print_other_inst_src(irp, instruction->safety_on);
11961196 fprintf(irp->f, ")");
11971197}
11981198
1199static void ir_print_set_float_mode(IrPrintSrc *irp, IrInstSrcSetFloatMode *instruction) {
1199static void ir_print_set_float_mode(IrPrintSrc *irp, Stage1ZirInstSetFloatMode *instruction) {
12001200 fprintf(irp->f, "@setFloatMode(");
12011201 ir_print_other_inst_src(irp, instruction->scope_value);
12021202 fprintf(irp->f, ", ");
......@@ -1204,7 +1204,7 @@ static void ir_print_set_float_mode(IrPrintSrc *irp, IrInstSrcSetFloatMode *inst
12041204 fprintf(irp->f, ")");
12051205}
12061206
1207static void ir_print_array_type(IrPrintSrc *irp, IrInstSrcArrayType *instruction) {
1207static void ir_print_array_type(IrPrintSrc *irp, Stage1ZirInstArrayType *instruction) {
12081208 fprintf(irp->f, "[");
12091209 ir_print_other_inst_src(irp, instruction->size);
12101210 if (instruction->sentinel != nullptr) {
......@@ -1215,13 +1215,13 @@ static void ir_print_array_type(IrPrintSrc *irp, IrInstSrcArrayType *instruction
12151215 ir_print_other_inst_src(irp, instruction->child_type);
12161216}
12171217
1218static void ir_print_slice_type(IrPrintSrc *irp, IrInstSrcSliceType *instruction) {
1218static void ir_print_slice_type(IrPrintSrc *irp, Stage1ZirInstSliceType *instruction) {
12191219 const char *const_kw = instruction->is_const ? "const " : "";
12201220 fprintf(irp->f, "[]%s", const_kw);
12211221 ir_print_other_inst_src(irp, instruction->child_type);
12221222}
12231223
1224static void ir_print_any_frame_type(IrPrintSrc *irp, IrInstSrcAnyFrameType *instruction) {
1224static void ir_print_any_frame_type(IrPrintSrc *irp, Stage1ZirInstAnyFrameType *instruction) {
12251225 if (instruction->payload_type == nullptr) {
12261226 fprintf(irp->f, "anyframe");
12271227 } else {
......@@ -1230,7 +1230,7 @@ static void ir_print_any_frame_type(IrPrintSrc *irp, IrInstSrcAnyFrameType *inst
12301230 }
12311231}
12321232
1233static void ir_print_asm_src(IrPrintSrc *irp, IrInstSrcAsm *instruction) {
1233static void ir_print_asm_src(IrPrintSrc *irp, Stage1ZirInstAsm *instruction) {
12341234 assert(instruction->base.source_node->type == NodeTypeAsmExpr);
12351235 AstNodeAsmExpr *asm_expr = &instruction->base.source_node->data.asm_expr;
12361236 const char *volatile_kw = instruction->has_side_effects ? " volatile" : "";
......@@ -1273,7 +1273,7 @@ static void ir_print_asm_src(IrPrintSrc *irp, IrInstSrcAsm *instruction) {
12731273 fprintf(irp->f, ")");
12741274}
12751275
1276static void ir_print_asm_gen(IrPrintGen *irp, IrInstGenAsm *instruction) {
1276static void ir_print_asm_gen(IrPrintGen *irp, Stage1AirInstAsm *instruction) {
12771277 assert(instruction->base.source_node->type == NodeTypeAsmExpr);
12781278 AstNodeAsmExpr *asm_expr = &instruction->base.source_node->data.asm_expr;
12791279 const char *volatile_kw = instruction->has_side_effects ? " volatile" : "";
......@@ -1315,7 +1315,7 @@ static void ir_print_asm_gen(IrPrintGen *irp, IrInstGenAsm *instruction) {
13151315 fprintf(irp->f, ")");
13161316}
13171317
1318static void ir_print_size_of(IrPrintSrc *irp, IrInstSrcSizeOf *instruction) {
1318static void ir_print_size_of(IrPrintSrc *irp, Stage1ZirInstSizeOf *instruction) {
13191319 if (instruction->bit_size)
13201320 fprintf(irp->f, "@bitSizeOf(");
13211321 else
......@@ -1324,17 +1324,17 @@ static void ir_print_size_of(IrPrintSrc *irp, IrInstSrcSizeOf *instruction) {
13241324 fprintf(irp->f, ")");
13251325}
13261326
1327static void ir_print_test_non_null(IrPrintSrc *irp, IrInstSrcTestNonNull *instruction) {
1327static void ir_print_test_non_null(IrPrintSrc *irp, Stage1ZirInstTestNonNull *instruction) {
13281328 ir_print_other_inst_src(irp, instruction->value);
13291329 fprintf(irp->f, " != null");
13301330}
13311331
1332static void ir_print_test_non_null(IrPrintGen *irp, IrInstGenTestNonNull *instruction) {
1332static void ir_print_test_non_null(IrPrintGen *irp, Stage1AirInstTestNonNull *instruction) {
13331333 ir_print_other_inst_gen(irp, instruction->value);
13341334 fprintf(irp->f, " != null");
13351335}
13361336
1337static void ir_print_optional_unwrap_ptr(IrPrintSrc *irp, IrInstSrcOptionalUnwrapPtr *instruction) {
1337static void ir_print_optional_unwrap_ptr(IrPrintSrc *irp, Stage1ZirInstOptionalUnwrapPtr *instruction) {
13381338 fprintf(irp->f, "&");
13391339 ir_print_other_inst_src(irp, instruction->base_ptr);
13401340 fprintf(irp->f, ".*.?");
......@@ -1343,7 +1343,7 @@ static void ir_print_optional_unwrap_ptr(IrPrintSrc *irp, IrInstSrcOptionalUnwra
13431343 }
13441344}
13451345
1346static void ir_print_optional_unwrap_ptr(IrPrintGen *irp, IrInstGenOptionalUnwrapPtr *instruction) {
1346static void ir_print_optional_unwrap_ptr(IrPrintGen *irp, Stage1AirInstOptionalUnwrapPtr *instruction) {
13471347 fprintf(irp->f, "&");
13481348 ir_print_other_inst_gen(irp, instruction->base_ptr);
13491349 fprintf(irp->f, ".*.?");
......@@ -1352,7 +1352,7 @@ static void ir_print_optional_unwrap_ptr(IrPrintGen *irp, IrInstGenOptionalUnwra
13521352 }
13531353}
13541354
1355static void ir_print_clz(IrPrintSrc *irp, IrInstSrcClz *instruction) {
1355static void ir_print_clz(IrPrintSrc *irp, Stage1ZirInstClz *instruction) {
13561356 fprintf(irp->f, "@clz(");
13571357 ir_print_other_inst_src(irp, instruction->type);
13581358 fprintf(irp->f, ",");
......@@ -1360,13 +1360,13 @@ static void ir_print_clz(IrPrintSrc *irp, IrInstSrcClz *instruction) {
13601360 fprintf(irp->f, ")");
13611361}
13621362
1363static void ir_print_clz(IrPrintGen *irp, IrInstGenClz *instruction) {
1363static void ir_print_clz(IrPrintGen *irp, Stage1AirInstClz *instruction) {
13641364 fprintf(irp->f, "@clz(");
13651365 ir_print_other_inst_gen(irp, instruction->op);
13661366 fprintf(irp->f, ")");
13671367}
13681368
1369static void ir_print_ctz(IrPrintSrc *irp, IrInstSrcCtz *instruction) {
1369static void ir_print_ctz(IrPrintSrc *irp, Stage1ZirInstCtz *instruction) {
13701370 fprintf(irp->f, "@ctz(");
13711371 ir_print_other_inst_src(irp, instruction->type);
13721372 fprintf(irp->f, ",");
......@@ -1374,13 +1374,13 @@ static void ir_print_ctz(IrPrintSrc *irp, IrInstSrcCtz *instruction) {
13741374 fprintf(irp->f, ")");
13751375}
13761376
1377static void ir_print_ctz(IrPrintGen *irp, IrInstGenCtz *instruction) {
1377static void ir_print_ctz(IrPrintGen *irp, Stage1AirInstCtz *instruction) {
13781378 fprintf(irp->f, "@ctz(");
13791379 ir_print_other_inst_gen(irp, instruction->op);
13801380 fprintf(irp->f, ")");
13811381}
13821382
1383static void ir_print_pop_count(IrPrintSrc *irp, IrInstSrcPopCount *instruction) {
1383static void ir_print_pop_count(IrPrintSrc *irp, Stage1ZirInstPopCount *instruction) {
13841384 fprintf(irp->f, "@popCount(");
13851385 ir_print_other_inst_src(irp, instruction->type);
13861386 fprintf(irp->f, ",");
......@@ -1388,13 +1388,13 @@ static void ir_print_pop_count(IrPrintSrc *irp, IrInstSrcPopCount *instruction)
13881388 fprintf(irp->f, ")");
13891389}
13901390
1391static void ir_print_pop_count(IrPrintGen *irp, IrInstGenPopCount *instruction) {
1391static void ir_print_pop_count(IrPrintGen *irp, Stage1AirInstPopCount *instruction) {
13921392 fprintf(irp->f, "@popCount(");
13931393 ir_print_other_inst_gen(irp, instruction->op);
13941394 fprintf(irp->f, ")");
13951395}
13961396
1397static void ir_print_bswap(IrPrintSrc *irp, IrInstSrcBswap *instruction) {
1397static void ir_print_bswap(IrPrintSrc *irp, Stage1ZirInstBswap *instruction) {
13981398 fprintf(irp->f, "@byteSwap(");
13991399 ir_print_other_inst_src(irp, instruction->type);
14001400 fprintf(irp->f, ",");
......@@ -1402,13 +1402,13 @@ static void ir_print_bswap(IrPrintSrc *irp, IrInstSrcBswap *instruction) {
14021402 fprintf(irp->f, ")");
14031403}
14041404
1405static void ir_print_bswap(IrPrintGen *irp, IrInstGenBswap *instruction) {
1405static void ir_print_bswap(IrPrintGen *irp, Stage1AirInstBswap *instruction) {
14061406 fprintf(irp->f, "@byteSwap(");
14071407 ir_print_other_inst_gen(irp, instruction->op);
14081408 fprintf(irp->f, ")");
14091409}
14101410
1411static void ir_print_bit_reverse(IrPrintSrc *irp, IrInstSrcBitReverse *instruction) {
1411static void ir_print_bit_reverse(IrPrintSrc *irp, Stage1ZirInstBitReverse *instruction) {
14121412 fprintf(irp->f, "@bitReverse(");
14131413 ir_print_other_inst_src(irp, instruction->type);
14141414 fprintf(irp->f, ",");
......@@ -1416,18 +1416,18 @@ static void ir_print_bit_reverse(IrPrintSrc *irp, IrInstSrcBitReverse *instructi
14161416 fprintf(irp->f, ")");
14171417}
14181418
1419static void ir_print_bit_reverse(IrPrintGen *irp, IrInstGenBitReverse *instruction) {
1419static void ir_print_bit_reverse(IrPrintGen *irp, Stage1AirInstBitReverse *instruction) {
14201420 fprintf(irp->f, "@bitReverse(");
14211421 ir_print_other_inst_gen(irp, instruction->op);
14221422 fprintf(irp->f, ")");
14231423}
14241424
1425static void ir_print_switch_br(IrPrintSrc *irp, IrInstSrcSwitchBr *instruction) {
1425static void ir_print_switch_br(IrPrintSrc *irp, Stage1ZirInstSwitchBr *instruction) {
14261426 fprintf(irp->f, "switch (");
14271427 ir_print_other_inst_src(irp, instruction->target_value);
14281428 fprintf(irp->f, ") ");
14291429 for (size_t i = 0; i < instruction->case_count; i += 1) {
1430 IrInstSrcSwitchBrCase *this_case = &instruction->cases[i];
1430 Stage1ZirInstSwitchBrCase *this_case = &instruction->cases[i];
14311431 ir_print_other_inst_src(irp, this_case->value);
14321432 fprintf(irp->f, " => ");
14331433 ir_print_other_block(irp, this_case->block);
......@@ -1441,12 +1441,12 @@ static void ir_print_switch_br(IrPrintSrc *irp, IrInstSrcSwitchBr *instruction)
14411441 }
14421442}
14431443
1444static void ir_print_switch_br(IrPrintGen *irp, IrInstGenSwitchBr *instruction) {
1444static void ir_print_switch_br(IrPrintGen *irp, Stage1AirInstSwitchBr *instruction) {
14451445 fprintf(irp->f, "switch (");
14461446 ir_print_other_inst_gen(irp, instruction->target_value);
14471447 fprintf(irp->f, ") ");
14481448 for (size_t i = 0; i < instruction->case_count; i += 1) {
1449 IrInstGenSwitchBrCase *this_case = &instruction->cases[i];
1449 Stage1AirInstSwitchBrCase *this_case = &instruction->cases[i];
14501450 ir_print_other_inst_gen(irp, this_case->value);
14511451 fprintf(irp->f, " => ");
14521452 ir_print_other_block_gen(irp, this_case->block);
......@@ -1456,7 +1456,7 @@ static void ir_print_switch_br(IrPrintGen *irp, IrInstGenSwitchBr *instruction)
14561456 ir_print_other_block_gen(irp, instruction->else_block);
14571457}
14581458
1459static void ir_print_switch_var(IrPrintSrc *irp, IrInstSrcSwitchVar *instruction) {
1459static void ir_print_switch_var(IrPrintSrc *irp, Stage1ZirInstSwitchVar *instruction) {
14601460 fprintf(irp->f, "switchvar ");
14611461 ir_print_other_inst_src(irp, instruction->target_value_ptr);
14621462 for (size_t i = 0; i < instruction->prongs_len; i += 1) {
......@@ -1465,79 +1465,79 @@ static void ir_print_switch_var(IrPrintSrc *irp, IrInstSrcSwitchVar *instruction
14651465 }
14661466}
14671467
1468static void ir_print_switch_else_var(IrPrintSrc *irp, IrInstSrcSwitchElseVar *instruction) {
1468static void ir_print_switch_else_var(IrPrintSrc *irp, Stage1ZirInstSwitchElseVar *instruction) {
14691469 fprintf(irp->f, "switchelsevar ");
14701470 ir_print_other_inst_src(irp, &instruction->switch_br->base);
14711471}
14721472
1473static void ir_print_switch_target(IrPrintSrc *irp, IrInstSrcSwitchTarget *instruction) {
1473static void ir_print_switch_target(IrPrintSrc *irp, Stage1ZirInstSwitchTarget *instruction) {
14741474 fprintf(irp->f, "switchtarget ");
14751475 ir_print_other_inst_src(irp, instruction->target_value_ptr);
14761476}
14771477
1478static void ir_print_union_tag(IrPrintGen *irp, IrInstGenUnionTag *instruction) {
1478static void ir_print_union_tag(IrPrintGen *irp, Stage1AirInstUnionTag *instruction) {
14791479 fprintf(irp->f, "uniontag ");
14801480 ir_print_other_inst_gen(irp, instruction->value);
14811481}
14821482
1483static void ir_print_import(IrPrintSrc *irp, IrInstSrcImport *instruction) {
1483static void ir_print_import(IrPrintSrc *irp, Stage1ZirInstImport *instruction) {
14841484 fprintf(irp->f, "@import(");
14851485 ir_print_other_inst_src(irp, instruction->name);
14861486 fprintf(irp->f, ")");
14871487}
14881488
1489static void ir_print_ref(IrPrintSrc *irp, IrInstSrcRef *instruction) {
1489static void ir_print_ref(IrPrintSrc *irp, Stage1ZirInstRef *instruction) {
14901490 fprintf(irp->f, "ref ");
14911491 ir_print_other_inst_src(irp, instruction->value);
14921492}
14931493
1494static void ir_print_ref_gen(IrPrintGen *irp, IrInstGenRef *instruction) {
1494static void ir_print_ref_gen(IrPrintGen *irp, Stage1AirInstRef *instruction) {
14951495 fprintf(irp->f, "@ref(");
14961496 ir_print_other_inst_gen(irp, instruction->operand);
14971497 fprintf(irp->f, ")result=");
14981498 ir_print_other_inst_gen(irp, instruction->result_loc);
14991499}
15001500
1501static void ir_print_compile_err(IrPrintSrc *irp, IrInstSrcCompileErr *instruction) {
1501static void ir_print_compile_err(IrPrintSrc *irp, Stage1ZirInstCompileErr *instruction) {
15021502 fprintf(irp->f, "@compileError(");
15031503 ir_print_other_inst_src(irp, instruction->msg);
15041504 fprintf(irp->f, ")");
15051505}
15061506
1507static void ir_print_compile_log(IrPrintSrc *irp, IrInstSrcCompileLog *instruction) {
1507static void ir_print_compile_log(IrPrintSrc *irp, Stage1ZirInstCompileLog *instruction) {
15081508 fprintf(irp->f, "@compileLog(");
15091509 for (size_t i = 0; i < instruction->msg_count; i += 1) {
15101510 if (i != 0)
15111511 fprintf(irp->f, ",");
1512 IrInstSrc *msg = instruction->msg_list[i];
1512 Stage1ZirInst *msg = instruction->msg_list[i];
15131513 ir_print_other_inst_src(irp, msg);
15141514 }
15151515 fprintf(irp->f, ")");
15161516}
15171517
1518static void ir_print_err_name(IrPrintSrc *irp, IrInstSrcErrName *instruction) {
1518static void ir_print_err_name(IrPrintSrc *irp, Stage1ZirInstErrName *instruction) {
15191519 fprintf(irp->f, "@errorName(");
15201520 ir_print_other_inst_src(irp, instruction->value);
15211521 fprintf(irp->f, ")");
15221522}
15231523
1524static void ir_print_err_name(IrPrintGen *irp, IrInstGenErrName *instruction) {
1524static void ir_print_err_name(IrPrintGen *irp, Stage1AirInstErrName *instruction) {
15251525 fprintf(irp->f, "@errorName(");
15261526 ir_print_other_inst_gen(irp, instruction->value);
15271527 fprintf(irp->f, ")");
15281528}
15291529
1530static void ir_print_c_import(IrPrintSrc *irp, IrInstSrcCImport *instruction) {
1530static void ir_print_c_import(IrPrintSrc *irp, Stage1ZirInstCImport *instruction) {
15311531 fprintf(irp->f, "@cImport(...)");
15321532}
15331533
1534static void ir_print_c_include(IrPrintSrc *irp, IrInstSrcCInclude *instruction) {
1534static void ir_print_c_include(IrPrintSrc *irp, Stage1ZirInstCInclude *instruction) {
15351535 fprintf(irp->f, "@cInclude(");
15361536 ir_print_other_inst_src(irp, instruction->name);
15371537 fprintf(irp->f, ")");
15381538}
15391539
1540static void ir_print_c_define(IrPrintSrc *irp, IrInstSrcCDefine *instruction) {
1540static void ir_print_c_define(IrPrintSrc *irp, Stage1ZirInstCDefine *instruction) {
15411541 fprintf(irp->f, "@cDefine(");
15421542 ir_print_other_inst_src(irp, instruction->name);
15431543 fprintf(irp->f, ", ");
......@@ -1545,19 +1545,19 @@ static void ir_print_c_define(IrPrintSrc *irp, IrInstSrcCDefine *instruction) {
15451545 fprintf(irp->f, ")");
15461546}
15471547
1548static void ir_print_c_undef(IrPrintSrc *irp, IrInstSrcCUndef *instruction) {
1548static void ir_print_c_undef(IrPrintSrc *irp, Stage1ZirInstCUndef *instruction) {
15491549 fprintf(irp->f, "@cUndef(");
15501550 ir_print_other_inst_src(irp, instruction->name);
15511551 fprintf(irp->f, ")");
15521552}
15531553
1554static void ir_print_embed_file(IrPrintSrc *irp, IrInstSrcEmbedFile *instruction) {
1554static void ir_print_embed_file(IrPrintSrc *irp, Stage1ZirInstEmbedFile *instruction) {
15551555 fprintf(irp->f, "@embedFile(");
15561556 ir_print_other_inst_src(irp, instruction->name);
15571557 fprintf(irp->f, ")");
15581558}
15591559
1560static void ir_print_cmpxchg_src(IrPrintSrc *irp, IrInstSrcCmpxchg *instruction) {
1560static void ir_print_cmpxchg_src(IrPrintSrc *irp, Stage1ZirInstCmpxchg *instruction) {
15611561 fprintf(irp->f, "@cmpxchg(");
15621562 ir_print_other_inst_src(irp, instruction->ptr);
15631563 fprintf(irp->f, ", ");
......@@ -1572,7 +1572,7 @@ static void ir_print_cmpxchg_src(IrPrintSrc *irp, IrInstSrcCmpxchg *instruction)
15721572 ir_print_result_loc(irp, instruction->result_loc);
15731573}
15741574
1575static void ir_print_cmpxchg_gen(IrPrintGen *irp, IrInstGenCmpxchg *instruction) {
1575static void ir_print_cmpxchg_gen(IrPrintGen *irp, Stage1AirInstCmpxchg *instruction) {
15761576 fprintf(irp->f, "@cmpxchg(");
15771577 ir_print_other_inst_gen(irp, instruction->ptr);
15781578 fprintf(irp->f, ", ");
......@@ -1583,13 +1583,13 @@ static void ir_print_cmpxchg_gen(IrPrintGen *irp, IrInstGenCmpxchg *instruction)
15831583 ir_print_other_inst_gen(irp, instruction->result_loc);
15841584}
15851585
1586static void ir_print_fence(IrPrintSrc *irp, IrInstSrcFence *instruction) {
1586static void ir_print_fence(IrPrintSrc *irp, Stage1ZirInstFence *instruction) {
15871587 fprintf(irp->f, "@fence(");
15881588 ir_print_other_inst_src(irp, instruction->order);
15891589 fprintf(irp->f, ")");
15901590}
15911591
1592static void ir_print_reduce(IrPrintSrc *irp, IrInstSrcReduce *instruction) {
1592static void ir_print_reduce(IrPrintSrc *irp, Stage1ZirInstReduce *instruction) {
15931593 fprintf(irp->f, "@reduce(");
15941594 ir_print_other_inst_src(irp, instruction->op);
15951595 fprintf(irp->f, ", ");
......@@ -1609,7 +1609,7 @@ static const char *atomic_order_str(AtomicOrder order) {
16091609 zig_unreachable();
16101610}
16111611
1612static void ir_print_fence(IrPrintGen *irp, IrInstGenFence *instruction) {
1612static void ir_print_fence(IrPrintGen *irp, Stage1AirInstFence *instruction) {
16131613 fprintf(irp->f, "fence %s", atomic_order_str(instruction->order));
16141614}
16151615
......@@ -1626,13 +1626,13 @@ static const char *reduce_op_str(ReduceOp op) {
16261626 zig_unreachable();
16271627}
16281628
1629static void ir_print_reduce(IrPrintGen *irp, IrInstGenReduce *instruction) {
1629static void ir_print_reduce(IrPrintGen *irp, Stage1AirInstReduce *instruction) {
16301630 fprintf(irp->f, "@reduce(.%s, ", reduce_op_str(instruction->op));
16311631 ir_print_other_inst_gen(irp, instruction->value);
16321632 fprintf(irp->f, ")");
16331633}
16341634
1635static void ir_print_truncate(IrPrintSrc *irp, IrInstSrcTruncate *instruction) {
1635static void ir_print_truncate(IrPrintSrc *irp, Stage1ZirInstTruncate *instruction) {
16361636 fprintf(irp->f, "@truncate(");
16371637 ir_print_other_inst_src(irp, instruction->dest_type);
16381638 fprintf(irp->f, ", ");
......@@ -1640,13 +1640,13 @@ static void ir_print_truncate(IrPrintSrc *irp, IrInstSrcTruncate *instruction) {
16401640 fprintf(irp->f, ")");
16411641}
16421642
1643static void ir_print_truncate(IrPrintGen *irp, IrInstGenTruncate *instruction) {
1643static void ir_print_truncate(IrPrintGen *irp, Stage1AirInstTruncate *instruction) {
16441644 fprintf(irp->f, "@truncate(");
16451645 ir_print_other_inst_gen(irp, instruction->target);
16461646 fprintf(irp->f, ")");
16471647}
16481648
1649static void ir_print_int_cast(IrPrintSrc *irp, IrInstSrcIntCast *instruction) {
1649static void ir_print_int_cast(IrPrintSrc *irp, Stage1ZirInstIntCast *instruction) {
16501650 fprintf(irp->f, "@intCast(");
16511651 ir_print_other_inst_src(irp, instruction->dest_type);
16521652 fprintf(irp->f, ", ");
......@@ -1654,7 +1654,7 @@ static void ir_print_int_cast(IrPrintSrc *irp, IrInstSrcIntCast *instruction) {
16541654 fprintf(irp->f, ")");
16551655}
16561656
1657static void ir_print_float_cast(IrPrintSrc *irp, IrInstSrcFloatCast *instruction) {
1657static void ir_print_float_cast(IrPrintSrc *irp, Stage1ZirInstFloatCast *instruction) {
16581658 fprintf(irp->f, "@floatCast(");
16591659 ir_print_other_inst_src(irp, instruction->dest_type);
16601660 fprintf(irp->f, ", ");
......@@ -1662,7 +1662,7 @@ static void ir_print_float_cast(IrPrintSrc *irp, IrInstSrcFloatCast *instruction
16621662 fprintf(irp->f, ")");
16631663}
16641664
1665static void ir_print_err_set_cast(IrPrintSrc *irp, IrInstSrcErrSetCast *instruction) {
1665static void ir_print_err_set_cast(IrPrintSrc *irp, Stage1ZirInstErrSetCast *instruction) {
16661666 fprintf(irp->f, "@errSetCast(");
16671667 ir_print_other_inst_src(irp, instruction->dest_type);
16681668 fprintf(irp->f, ", ");
......@@ -1670,7 +1670,7 @@ static void ir_print_err_set_cast(IrPrintSrc *irp, IrInstSrcErrSetCast *instruct
16701670 fprintf(irp->f, ")");
16711671}
16721672
1673static void ir_print_int_to_float(IrPrintSrc *irp, IrInstSrcIntToFloat *instruction) {
1673static void ir_print_int_to_float(IrPrintSrc *irp, Stage1ZirInstIntToFloat *instruction) {
16741674 fprintf(irp->f, "@intToFloat(");
16751675 ir_print_other_inst_src(irp, instruction->dest_type);
16761676 fprintf(irp->f, ", ");
......@@ -1678,7 +1678,7 @@ static void ir_print_int_to_float(IrPrintSrc *irp, IrInstSrcIntToFloat *instruct
16781678 fprintf(irp->f, ")");
16791679}
16801680
1681static void ir_print_float_to_int(IrPrintSrc *irp, IrInstSrcFloatToInt *instruction) {
1681static void ir_print_float_to_int(IrPrintSrc *irp, Stage1ZirInstFloatToInt *instruction) {
16821682 fprintf(irp->f, "@floatToInt(");
16831683 ir_print_other_inst_src(irp, instruction->dest_type);
16841684 fprintf(irp->f, ", ");
......@@ -1686,13 +1686,13 @@ static void ir_print_float_to_int(IrPrintSrc *irp, IrInstSrcFloatToInt *instruct
16861686 fprintf(irp->f, ")");
16871687}
16881688
1689static void ir_print_bool_to_int(IrPrintSrc *irp, IrInstSrcBoolToInt *instruction) {
1689static void ir_print_bool_to_int(IrPrintSrc *irp, Stage1ZirInstBoolToInt *instruction) {
16901690 fprintf(irp->f, "@boolToInt(");
16911691 ir_print_other_inst_src(irp, instruction->target);
16921692 fprintf(irp->f, ")");
16931693}
16941694
1695static void ir_print_vector_type(IrPrintSrc *irp, IrInstSrcVectorType *instruction) {
1695static void ir_print_vector_type(IrPrintSrc *irp, Stage1ZirInstVectorType *instruction) {
16961696 fprintf(irp->f, "@Vector(");
16971697 ir_print_other_inst_src(irp, instruction->len);
16981698 fprintf(irp->f, ", ");
......@@ -1700,7 +1700,7 @@ static void ir_print_vector_type(IrPrintSrc *irp, IrInstSrcVectorType *instructi
17001700 fprintf(irp->f, ")");
17011701}
17021702
1703static void ir_print_shuffle_vector(IrPrintSrc *irp, IrInstSrcShuffleVector *instruction) {
1703static void ir_print_shuffle_vector(IrPrintSrc *irp, Stage1ZirInstShuffleVector *instruction) {
17041704 fprintf(irp->f, "@shuffle(");
17051705 ir_print_other_inst_src(irp, instruction->scalar_type);
17061706 fprintf(irp->f, ", ");
......@@ -1712,7 +1712,7 @@ static void ir_print_shuffle_vector(IrPrintSrc *irp, IrInstSrcShuffleVector *ins
17121712 fprintf(irp->f, ")");
17131713}
17141714
1715static void ir_print_shuffle_vector(IrPrintGen *irp, IrInstGenShuffleVector *instruction) {
1715static void ir_print_shuffle_vector(IrPrintGen *irp, Stage1AirInstShuffleVector *instruction) {
17161716 fprintf(irp->f, "@shuffle(");
17171717 ir_print_other_inst_gen(irp, instruction->a);
17181718 fprintf(irp->f, ", ");
......@@ -1722,7 +1722,7 @@ static void ir_print_shuffle_vector(IrPrintGen *irp, IrInstGenShuffleVector *ins
17221722 fprintf(irp->f, ")");
17231723}
17241724
1725static void ir_print_splat_src(IrPrintSrc *irp, IrInstSrcSplat *instruction) {
1725static void ir_print_splat_src(IrPrintSrc *irp, Stage1ZirInstSplat *instruction) {
17261726 fprintf(irp->f, "@splat(");
17271727 ir_print_other_inst_src(irp, instruction->len);
17281728 fprintf(irp->f, ", ");
......@@ -1730,35 +1730,35 @@ static void ir_print_splat_src(IrPrintSrc *irp, IrInstSrcSplat *instruction) {
17301730 fprintf(irp->f, ")");
17311731}
17321732
1733static void ir_print_splat_gen(IrPrintGen *irp, IrInstGenSplat *instruction) {
1733static void ir_print_splat_gen(IrPrintGen *irp, Stage1AirInstSplat *instruction) {
17341734 fprintf(irp->f, "@splat(");
17351735 ir_print_other_inst_gen(irp, instruction->scalar);
17361736 fprintf(irp->f, ")");
17371737}
17381738
1739static void ir_print_bool_not(IrPrintSrc *irp, IrInstSrcBoolNot *instruction) {
1739static void ir_print_bool_not(IrPrintSrc *irp, Stage1ZirInstBoolNot *instruction) {
17401740 fprintf(irp->f, "! ");
17411741 ir_print_other_inst_src(irp, instruction->value);
17421742}
17431743
1744static void ir_print_bool_not(IrPrintGen *irp, IrInstGenBoolNot *instruction) {
1744static void ir_print_bool_not(IrPrintGen *irp, Stage1AirInstBoolNot *instruction) {
17451745 fprintf(irp->f, "! ");
17461746 ir_print_other_inst_gen(irp, instruction->value);
17471747}
17481748
1749static void ir_print_wasm_memory_size(IrPrintSrc *irp, IrInstSrcWasmMemorySize *instruction) {
1749static void ir_print_wasm_memory_size(IrPrintSrc *irp, Stage1ZirInstWasmMemorySize *instruction) {
17501750 fprintf(irp->f, "@wasmMemorySize(");
17511751 ir_print_other_inst_src(irp, instruction->index);
17521752 fprintf(irp->f, ")");
17531753}
17541754
1755static void ir_print_wasm_memory_size(IrPrintGen *irp, IrInstGenWasmMemorySize *instruction) {
1755static void ir_print_wasm_memory_size(IrPrintGen *irp, Stage1AirInstWasmMemorySize *instruction) {
17561756 fprintf(irp->f, "@wasmMemorySize(");
17571757 ir_print_other_inst_gen(irp, instruction->index);
17581758 fprintf(irp->f, ")");
17591759}
17601760
1761static void ir_print_wasm_memory_grow(IrPrintSrc *irp, IrInstSrcWasmMemoryGrow *instruction) {
1761static void ir_print_wasm_memory_grow(IrPrintSrc *irp, Stage1ZirInstWasmMemoryGrow *instruction) {
17621762 fprintf(irp->f, "@wasmMemoryGrow(");
17631763 ir_print_other_inst_src(irp, instruction->index);
17641764 fprintf(irp->f, ", ");
......@@ -1766,7 +1766,7 @@ static void ir_print_wasm_memory_grow(IrPrintSrc *irp, IrInstSrcWasmMemoryGrow *
17661766 fprintf(irp->f, ")");
17671767}
17681768
1769static void ir_print_wasm_memory_grow(IrPrintGen *irp, IrInstGenWasmMemoryGrow *instruction) {
1769static void ir_print_wasm_memory_grow(IrPrintGen *irp, Stage1AirInstWasmMemoryGrow *instruction) {
17701770 fprintf(irp->f, "@wasmMemoryGrow(");
17711771 ir_print_other_inst_gen(irp, instruction->index);
17721772 fprintf(irp->f, ", ");
......@@ -1774,11 +1774,11 @@ static void ir_print_wasm_memory_grow(IrPrintGen *irp, IrInstGenWasmMemoryGrow *
17741774 fprintf(irp->f, ")");
17751775}
17761776
1777static void ir_print_builtin_src(IrPrintSrc *irp, IrInstSrcSrc *instruction) {
1777static void ir_print_builtin_src(IrPrintSrc *irp, Stage1ZirInstSrc *instruction) {
17781778 fprintf(irp->f, "@src()");
17791779}
17801780
1781static void ir_print_memset(IrPrintSrc *irp, IrInstSrcMemset *instruction) {
1781static void ir_print_memset(IrPrintSrc *irp, Stage1ZirInstMemset *instruction) {
17821782 fprintf(irp->f, "@memset(");
17831783 ir_print_other_inst_src(irp, instruction->dest_ptr);
17841784 fprintf(irp->f, ", ");
......@@ -1788,7 +1788,7 @@ static void ir_print_memset(IrPrintSrc *irp, IrInstSrcMemset *instruction) {
17881788 fprintf(irp->f, ")");
17891789}
17901790
1791static void ir_print_memset(IrPrintGen *irp, IrInstGenMemset *instruction) {
1791static void ir_print_memset(IrPrintGen *irp, Stage1AirInstMemset *instruction) {
17921792 fprintf(irp->f, "@memset(");
17931793 ir_print_other_inst_gen(irp, instruction->dest_ptr);
17941794 fprintf(irp->f, ", ");
......@@ -1798,7 +1798,7 @@ static void ir_print_memset(IrPrintGen *irp, IrInstGenMemset *instruction) {
17981798 fprintf(irp->f, ")");
17991799}
18001800
1801static void ir_print_memcpy(IrPrintSrc *irp, IrInstSrcMemcpy *instruction) {
1801static void ir_print_memcpy(IrPrintSrc *irp, Stage1ZirInstMemcpy *instruction) {
18021802 fprintf(irp->f, "@memcpy(");
18031803 ir_print_other_inst_src(irp, instruction->dest_ptr);
18041804 fprintf(irp->f, ", ");
......@@ -1808,7 +1808,7 @@ static void ir_print_memcpy(IrPrintSrc *irp, IrInstSrcMemcpy *instruction) {
18081808 fprintf(irp->f, ")");
18091809}
18101810
1811static void ir_print_memcpy(IrPrintGen *irp, IrInstGenMemcpy *instruction) {
1811static void ir_print_memcpy(IrPrintGen *irp, Stage1AirInstMemcpy *instruction) {
18121812 fprintf(irp->f, "@memcpy(");
18131813 ir_print_other_inst_gen(irp, instruction->dest_ptr);
18141814 fprintf(irp->f, ", ");
......@@ -1818,7 +1818,7 @@ static void ir_print_memcpy(IrPrintGen *irp, IrInstGenMemcpy *instruction) {
18181818 fprintf(irp->f, ")");
18191819}
18201820
1821static void ir_print_slice_src(IrPrintSrc *irp, IrInstSrcSlice *instruction) {
1821static void ir_print_slice_src(IrPrintSrc *irp, Stage1ZirInstSlice *instruction) {
18221822 ir_print_other_inst_src(irp, instruction->ptr);
18231823 fprintf(irp->f, "[");
18241824 ir_print_other_inst_src(irp, instruction->start);
......@@ -1829,7 +1829,7 @@ static void ir_print_slice_src(IrPrintSrc *irp, IrInstSrcSlice *instruction) {
18291829 ir_print_result_loc(irp, instruction->result_loc);
18301830}
18311831
1832static void ir_print_slice_gen(IrPrintGen *irp, IrInstGenSlice *instruction) {
1832static void ir_print_slice_gen(IrPrintGen *irp, Stage1AirInstSlice *instruction) {
18331833 ir_print_other_inst_gen(irp, instruction->ptr);
18341834 fprintf(irp->f, "[");
18351835 ir_print_other_inst_gen(irp, instruction->start);
......@@ -1840,63 +1840,63 @@ static void ir_print_slice_gen(IrPrintGen *irp, IrInstGenSlice *instruction) {
18401840 ir_print_other_inst_gen(irp, instruction->result_loc);
18411841}
18421842
1843static void ir_print_breakpoint(IrPrintSrc *irp, IrInstSrcBreakpoint *instruction) {
1843static void ir_print_breakpoint(IrPrintSrc *irp, Stage1ZirInstBreakpoint *instruction) {
18441844 fprintf(irp->f, "@breakpoint()");
18451845}
18461846
1847static void ir_print_breakpoint(IrPrintGen *irp, IrInstGenBreakpoint *instruction) {
1847static void ir_print_breakpoint(IrPrintGen *irp, Stage1AirInstBreakpoint *instruction) {
18481848 fprintf(irp->f, "@breakpoint()");
18491849}
18501850
1851static void ir_print_frame_address(IrPrintSrc *irp, IrInstSrcFrameAddress *instruction) {
1851static void ir_print_frame_address(IrPrintSrc *irp, Stage1ZirInstFrameAddress *instruction) {
18521852 fprintf(irp->f, "@frameAddress()");
18531853}
18541854
1855static void ir_print_frame_address(IrPrintGen *irp, IrInstGenFrameAddress *instruction) {
1855static void ir_print_frame_address(IrPrintGen *irp, Stage1AirInstFrameAddress *instruction) {
18561856 fprintf(irp->f, "@frameAddress()");
18571857}
18581858
1859static void ir_print_handle(IrPrintSrc *irp, IrInstSrcFrameHandle *instruction) {
1859static void ir_print_handle(IrPrintSrc *irp, Stage1ZirInstFrameHandle *instruction) {
18601860 fprintf(irp->f, "@frame()");
18611861}
18621862
1863static void ir_print_handle(IrPrintGen *irp, IrInstGenFrameHandle *instruction) {
1863static void ir_print_handle(IrPrintGen *irp, Stage1AirInstFrameHandle *instruction) {
18641864 fprintf(irp->f, "@frame()");
18651865}
18661866
1867static void ir_print_frame_type(IrPrintSrc *irp, IrInstSrcFrameType *instruction) {
1867static void ir_print_frame_type(IrPrintSrc *irp, Stage1ZirInstFrameType *instruction) {
18681868 fprintf(irp->f, "@Frame(");
18691869 ir_print_other_inst_src(irp, instruction->fn);
18701870 fprintf(irp->f, ")");
18711871}
18721872
1873static void ir_print_frame_size_src(IrPrintSrc *irp, IrInstSrcFrameSize *instruction) {
1873static void ir_print_frame_size_src(IrPrintSrc *irp, Stage1ZirInstFrameSize *instruction) {
18741874 fprintf(irp->f, "@frameSize(");
18751875 ir_print_other_inst_src(irp, instruction->fn);
18761876 fprintf(irp->f, ")");
18771877}
18781878
1879static void ir_print_frame_size_gen(IrPrintGen *irp, IrInstGenFrameSize *instruction) {
1879static void ir_print_frame_size_gen(IrPrintGen *irp, Stage1AirInstFrameSize *instruction) {
18801880 fprintf(irp->f, "@frameSize(");
18811881 ir_print_other_inst_gen(irp, instruction->fn);
18821882 fprintf(irp->f, ")");
18831883}
18841884
1885static void ir_print_return_address(IrPrintSrc *irp, IrInstSrcReturnAddress *instruction) {
1885static void ir_print_return_address(IrPrintSrc *irp, Stage1ZirInstReturnAddress *instruction) {
18861886 fprintf(irp->f, "@returnAddress()");
18871887}
18881888
1889static void ir_print_return_address(IrPrintGen *irp, IrInstGenReturnAddress *instruction) {
1889static void ir_print_return_address(IrPrintGen *irp, Stage1AirInstReturnAddress *instruction) {
18901890 fprintf(irp->f, "@returnAddress()");
18911891}
18921892
1893static void ir_print_align_of(IrPrintSrc *irp, IrInstSrcAlignOf *instruction) {
1893static void ir_print_align_of(IrPrintSrc *irp, Stage1ZirInstAlignOf *instruction) {
18941894 fprintf(irp->f, "@alignOf(");
18951895 ir_print_other_inst_src(irp, instruction->type_value);
18961896 fprintf(irp->f, ")");
18971897}
18981898
1899static void ir_print_overflow_op(IrPrintSrc *irp, IrInstSrcOverflowOp *instruction) {
1899static void ir_print_overflow_op(IrPrintSrc *irp, Stage1ZirInstOverflowOp *instruction) {
19001900 switch (instruction->op) {
19011901 case IrOverflowOpAdd:
19021902 fprintf(irp->f, "@addWithOverflow(");
......@@ -1921,7 +1921,7 @@ static void ir_print_overflow_op(IrPrintSrc *irp, IrInstSrcOverflowOp *instructi
19211921 fprintf(irp->f, ")");
19221922}
19231923
1924static void ir_print_overflow_op(IrPrintGen *irp, IrInstGenOverflowOp *instruction) {
1924static void ir_print_overflow_op(IrPrintGen *irp, Stage1AirInstOverflowOp *instruction) {
19251925 switch (instruction->op) {
19261926 case IrOverflowOpAdd:
19271927 fprintf(irp->f, "@addWithOverflow(");
......@@ -1944,64 +1944,64 @@ static void ir_print_overflow_op(IrPrintGen *irp, IrInstGenOverflowOp *instructi
19441944 fprintf(irp->f, ")");
19451945}
19461946
1947static void ir_print_test_err_src(IrPrintSrc *irp, IrInstSrcTestErr *instruction) {
1947static void ir_print_test_err_src(IrPrintSrc *irp, Stage1ZirInstTestErr *instruction) {
19481948 fprintf(irp->f, "@testError(");
19491949 ir_print_other_inst_src(irp, instruction->base_ptr);
19501950 fprintf(irp->f, ")");
19511951}
19521952
1953static void ir_print_test_err_gen(IrPrintGen *irp, IrInstGenTestErr *instruction) {
1953static void ir_print_test_err_gen(IrPrintGen *irp, Stage1AirInstTestErr *instruction) {
19541954 fprintf(irp->f, "@testError(");
19551955 ir_print_other_inst_gen(irp, instruction->err_union);
19561956 fprintf(irp->f, ")");
19571957}
19581958
1959static void ir_print_unwrap_err_code(IrPrintSrc *irp, IrInstSrcUnwrapErrCode *instruction) {
1959static void ir_print_unwrap_err_code(IrPrintSrc *irp, Stage1ZirInstUnwrapErrCode *instruction) {
19601960 fprintf(irp->f, "UnwrapErrorCode(");
19611961 ir_print_other_inst_src(irp, instruction->err_union_ptr);
19621962 fprintf(irp->f, ")");
19631963}
19641964
1965static void ir_print_unwrap_err_code(IrPrintGen *irp, IrInstGenUnwrapErrCode *instruction) {
1965static void ir_print_unwrap_err_code(IrPrintGen *irp, Stage1AirInstUnwrapErrCode *instruction) {
19661966 fprintf(irp->f, "UnwrapErrorCode(");
19671967 ir_print_other_inst_gen(irp, instruction->err_union_ptr);
19681968 fprintf(irp->f, ")");
19691969}
19701970
1971static void ir_print_unwrap_err_payload(IrPrintSrc *irp, IrInstSrcUnwrapErrPayload *instruction) {
1971static void ir_print_unwrap_err_payload(IrPrintSrc *irp, Stage1ZirInstUnwrapErrPayload *instruction) {
19721972 fprintf(irp->f, "ErrorUnionFieldPayload(");
19731973 ir_print_other_inst_src(irp, instruction->value);
19741974 fprintf(irp->f, ")safety=%d,init=%d",instruction->safety_check_on, instruction->initializing);
19751975}
19761976
1977static void ir_print_unwrap_err_payload(IrPrintGen *irp, IrInstGenUnwrapErrPayload *instruction) {
1977static void ir_print_unwrap_err_payload(IrPrintGen *irp, Stage1AirInstUnwrapErrPayload *instruction) {
19781978 fprintf(irp->f, "ErrorUnionFieldPayload(");
19791979 ir_print_other_inst_gen(irp, instruction->value);
19801980 fprintf(irp->f, ")safety=%d,init=%d",instruction->safety_check_on, instruction->initializing);
19811981}
19821982
1983static void ir_print_optional_wrap(IrPrintGen *irp, IrInstGenOptionalWrap *instruction) {
1983static void ir_print_optional_wrap(IrPrintGen *irp, Stage1AirInstOptionalWrap *instruction) {
19841984 fprintf(irp->f, "@optionalWrap(");
19851985 ir_print_other_inst_gen(irp, instruction->operand);
19861986 fprintf(irp->f, ")result=");
19871987 ir_print_other_inst_gen(irp, instruction->result_loc);
19881988}
19891989
1990static void ir_print_err_wrap_code(IrPrintGen *irp, IrInstGenErrWrapCode *instruction) {
1990static void ir_print_err_wrap_code(IrPrintGen *irp, Stage1AirInstErrWrapCode *instruction) {
19911991 fprintf(irp->f, "@errWrapCode(");
19921992 ir_print_other_inst_gen(irp, instruction->operand);
19931993 fprintf(irp->f, ")result=");
19941994 ir_print_other_inst_gen(irp, instruction->result_loc);
19951995}
19961996
1997static void ir_print_err_wrap_payload(IrPrintGen *irp, IrInstGenErrWrapPayload *instruction) {
1997static void ir_print_err_wrap_payload(IrPrintGen *irp, Stage1AirInstErrWrapPayload *instruction) {
19981998 fprintf(irp->f, "@errWrapPayload(");
19991999 ir_print_other_inst_gen(irp, instruction->operand);
20002000 fprintf(irp->f, ")result=");
20012001 ir_print_other_inst_gen(irp, instruction->result_loc);
20022002}
20032003
2004static void ir_print_fn_proto(IrPrintSrc *irp, IrInstSrcFnProto *instruction) {
2004static void ir_print_fn_proto(IrPrintSrc *irp, Stage1ZirInstFnProto *instruction) {
20052005 fprintf(irp->f, "fn(");
20062006 for (size_t i = 0; i < instruction->base.source_node->data.fn_proto.params.length; i += 1) {
20072007 if (i != 0)
......@@ -2022,13 +2022,13 @@ static void ir_print_fn_proto(IrPrintSrc *irp, IrInstSrcFnProto *instruction) {
20222022 ir_print_other_inst_src(irp, instruction->return_type);
20232023}
20242024
2025static void ir_print_test_comptime(IrPrintSrc *irp, IrInstSrcTestComptime *instruction) {
2025static void ir_print_test_comptime(IrPrintSrc *irp, Stage1ZirInstTestComptime *instruction) {
20262026 fprintf(irp->f, "@testComptime(");
20272027 ir_print_other_inst_src(irp, instruction->value);
20282028 fprintf(irp->f, ")");
20292029}
20302030
2031static void ir_print_ptr_cast_src(IrPrintSrc *irp, IrInstSrcPtrCast *instruction) {
2031static void ir_print_ptr_cast_src(IrPrintSrc *irp, Stage1ZirInstPtrCast *instruction) {
20322032 fprintf(irp->f, "@ptrCast(");
20332033 if (instruction->dest_type) {
20342034 ir_print_other_inst_src(irp, instruction->dest_type);
......@@ -2038,51 +2038,51 @@ static void ir_print_ptr_cast_src(IrPrintSrc *irp, IrInstSrcPtrCast *instruction
20382038 fprintf(irp->f, ")");
20392039}
20402040
2041static void ir_print_ptr_cast_gen(IrPrintGen *irp, IrInstGenPtrCast *instruction) {
2041static void ir_print_ptr_cast_gen(IrPrintGen *irp, Stage1AirInstPtrCast *instruction) {
20422042 fprintf(irp->f, "@ptrCast(");
20432043 ir_print_other_inst_gen(irp, instruction->ptr);
20442044 fprintf(irp->f, ")");
20452045}
20462046
2047static void ir_print_implicit_cast(IrPrintSrc *irp, IrInstSrcImplicitCast *instruction) {
2047static void ir_print_implicit_cast(IrPrintSrc *irp, Stage1ZirInstImplicitCast *instruction) {
20482048 fprintf(irp->f, "@implicitCast(");
20492049 ir_print_other_inst_src(irp, instruction->operand);
20502050 fprintf(irp->f, ")result=");
20512051 ir_print_result_loc(irp, &instruction->result_loc_cast->base);
20522052}
20532053
2054static void ir_print_bit_cast_src(IrPrintSrc *irp, IrInstSrcBitCast *instruction) {
2054static void ir_print_bit_cast_src(IrPrintSrc *irp, Stage1ZirInstBitCast *instruction) {
20552055 fprintf(irp->f, "@bitCast(");
20562056 ir_print_other_inst_src(irp, instruction->operand);
20572057 fprintf(irp->f, ")result=");
20582058 ir_print_result_loc(irp, &instruction->result_loc_bit_cast->base);
20592059}
20602060
2061static void ir_print_bit_cast_gen(IrPrintGen *irp, IrInstGenBitCast *instruction) {
2061static void ir_print_bit_cast_gen(IrPrintGen *irp, Stage1AirInstBitCast *instruction) {
20622062 fprintf(irp->f, "@bitCast(");
20632063 ir_print_other_inst_gen(irp, instruction->operand);
20642064 fprintf(irp->f, ")");
20652065}
20662066
2067static void ir_print_widen_or_shorten(IrPrintGen *irp, IrInstGenWidenOrShorten *instruction) {
2067static void ir_print_widen_or_shorten(IrPrintGen *irp, Stage1AirInstWidenOrShorten *instruction) {
20682068 fprintf(irp->f, "WidenOrShorten(");
20692069 ir_print_other_inst_gen(irp, instruction->target);
20702070 fprintf(irp->f, ")");
20712071}
20722072
2073static void ir_print_ptr_to_int(IrPrintSrc *irp, IrInstSrcPtrToInt *instruction) {
2073static void ir_print_ptr_to_int(IrPrintSrc *irp, Stage1ZirInstPtrToInt *instruction) {
20742074 fprintf(irp->f, "@ptrToInt(");
20752075 ir_print_other_inst_src(irp, instruction->target);
20762076 fprintf(irp->f, ")");
20772077}
20782078
2079static void ir_print_ptr_to_int(IrPrintGen *irp, IrInstGenPtrToInt *instruction) {
2079static void ir_print_ptr_to_int(IrPrintGen *irp, Stage1AirInstPtrToInt *instruction) {
20802080 fprintf(irp->f, "@ptrToInt(");
20812081 ir_print_other_inst_gen(irp, instruction->target);
20822082 fprintf(irp->f, ")");
20832083}
20842084
2085static void ir_print_int_to_ptr(IrPrintSrc *irp, IrInstSrcIntToPtr *instruction) {
2085static void ir_print_int_to_ptr(IrPrintSrc *irp, Stage1ZirInstIntToPtr *instruction) {
20862086 fprintf(irp->f, "@intToPtr(");
20872087 ir_print_other_inst_src(irp, instruction->dest_type);
20882088 fprintf(irp->f, ",");
......@@ -2090,13 +2090,13 @@ static void ir_print_int_to_ptr(IrPrintSrc *irp, IrInstSrcIntToPtr *instruction)
20902090 fprintf(irp->f, ")");
20912091}
20922092
2093static void ir_print_int_to_ptr(IrPrintGen *irp, IrInstGenIntToPtr *instruction) {
2093static void ir_print_int_to_ptr(IrPrintGen *irp, Stage1AirInstIntToPtr *instruction) {
20942094 fprintf(irp->f, "@intToPtr(");
20952095 ir_print_other_inst_gen(irp, instruction->target);
20962096 fprintf(irp->f, ")");
20972097}
20982098
2099static void ir_print_int_to_enum(IrPrintSrc *irp, IrInstSrcIntToEnum *instruction) {
2099static void ir_print_int_to_enum(IrPrintSrc *irp, Stage1ZirInstIntToEnum *instruction) {
21002100 fprintf(irp->f, "@intToEnum(");
21012101 ir_print_other_inst_src(irp, instruction->dest_type);
21022102 fprintf(irp->f, ",");
......@@ -2104,19 +2104,19 @@ static void ir_print_int_to_enum(IrPrintSrc *irp, IrInstSrcIntToEnum *instructio
21042104 fprintf(irp->f, ")");
21052105}
21062106
2107static void ir_print_int_to_enum(IrPrintGen *irp, IrInstGenIntToEnum *instruction) {
2107static void ir_print_int_to_enum(IrPrintGen *irp, Stage1AirInstIntToEnum *instruction) {
21082108 fprintf(irp->f, "@intToEnum(");
21092109 ir_print_other_inst_gen(irp, instruction->target);
21102110 fprintf(irp->f, ")");
21112111}
21122112
2113static void ir_print_enum_to_int(IrPrintSrc *irp, IrInstSrcEnumToInt *instruction) {
2113static void ir_print_enum_to_int(IrPrintSrc *irp, Stage1ZirInstEnumToInt *instruction) {
21142114 fprintf(irp->f, "@enumToInt(");
21152115 ir_print_other_inst_src(irp, instruction->target);
21162116 fprintf(irp->f, ")");
21172117}
21182118
2119static void ir_print_check_runtime_scope(IrPrintSrc *irp, IrInstSrcCheckRuntimeScope *instruction) {
2119static void ir_print_check_runtime_scope(IrPrintSrc *irp, Stage1ZirInstCheckRuntimeScope *instruction) {
21202120 fprintf(irp->f, "@checkRuntimeScope(");
21212121 ir_print_other_inst_src(irp, instruction->scope_is_comptime);
21222122 fprintf(irp->f, ",");
......@@ -2124,49 +2124,49 @@ static void ir_print_check_runtime_scope(IrPrintSrc *irp, IrInstSrcCheckRuntimeS
21242124 fprintf(irp->f, ")");
21252125}
21262126
2127static void ir_print_array_to_vector(IrPrintGen *irp, IrInstGenArrayToVector *instruction) {
2127static void ir_print_array_to_vector(IrPrintGen *irp, Stage1AirInstArrayToVector *instruction) {
21282128 fprintf(irp->f, "ArrayToVector(");
21292129 ir_print_other_inst_gen(irp, instruction->array);
21302130 fprintf(irp->f, ")");
21312131}
21322132
2133static void ir_print_vector_to_array(IrPrintGen *irp, IrInstGenVectorToArray *instruction) {
2133static void ir_print_vector_to_array(IrPrintGen *irp, Stage1AirInstVectorToArray *instruction) {
21342134 fprintf(irp->f, "VectorToArray(");
21352135 ir_print_other_inst_gen(irp, instruction->vector);
21362136 fprintf(irp->f, ")result=");
21372137 ir_print_other_inst_gen(irp, instruction->result_loc);
21382138}
21392139
2140static void ir_print_ptr_of_array_to_slice(IrPrintGen *irp, IrInstGenPtrOfArrayToSlice *instruction) {
2140static void ir_print_ptr_of_array_to_slice(IrPrintGen *irp, Stage1AirInstPtrOfArrayToSlice *instruction) {
21412141 fprintf(irp->f, "PtrOfArrayToSlice(");
21422142 ir_print_other_inst_gen(irp, instruction->operand);
21432143 fprintf(irp->f, ")result=");
21442144 ir_print_other_inst_gen(irp, instruction->result_loc);
21452145}
21462146
2147static void ir_print_assert_zero(IrPrintGen *irp, IrInstGenAssertZero *instruction) {
2147static void ir_print_assert_zero(IrPrintGen *irp, Stage1AirInstAssertZero *instruction) {
21482148 fprintf(irp->f, "AssertZero(");
21492149 ir_print_other_inst_gen(irp, instruction->target);
21502150 fprintf(irp->f, ")");
21512151}
21522152
2153static void ir_print_assert_non_null(IrPrintGen *irp, IrInstGenAssertNonNull *instruction) {
2153static void ir_print_assert_non_null(IrPrintGen *irp, Stage1AirInstAssertNonNull *instruction) {
21542154 fprintf(irp->f, "AssertNonNull(");
21552155 ir_print_other_inst_gen(irp, instruction->target);
21562156 fprintf(irp->f, ")");
21572157}
21582158
2159static void ir_print_alloca_src(IrPrintSrc *irp, IrInstSrcAlloca *instruction) {
2159static void ir_print_alloca_src(IrPrintSrc *irp, Stage1ZirInstAlloca *instruction) {
21602160 fprintf(irp->f, "Alloca(align=");
21612161 ir_print_other_inst_src(irp, instruction->align);
21622162 fprintf(irp->f, ",name=%s)", instruction->name_hint);
21632163}
21642164
2165static void ir_print_alloca_gen(IrPrintGen *irp, IrInstGenAlloca *instruction) {
2165static void ir_print_alloca_gen(IrPrintGen *irp, Stage1AirInstAlloca *instruction) {
21662166 fprintf(irp->f, "Alloca(align=%" PRIu32 ",name=%s)", instruction->align, instruction->name_hint);
21672167}
21682168
2169static void ir_print_end_expr(IrPrintSrc *irp, IrInstSrcEndExpr *instruction) {
2169static void ir_print_end_expr(IrPrintSrc *irp, Stage1ZirInstEndExpr *instruction) {
21702170 fprintf(irp->f, "EndExpr(result=");
21712171 ir_print_result_loc(irp, instruction->result_loc);
21722172 fprintf(irp->f, ",value=");
......@@ -2174,27 +2174,27 @@ static void ir_print_end_expr(IrPrintSrc *irp, IrInstSrcEndExpr *instruction) {
21742174 fprintf(irp->f, ")");
21752175}
21762176
2177static void ir_print_int_to_err(IrPrintSrc *irp, IrInstSrcIntToErr *instruction) {
2177static void ir_print_int_to_err(IrPrintSrc *irp, Stage1ZirInstIntToErr *instruction) {
21782178 fprintf(irp->f, "inttoerr ");
21792179 ir_print_other_inst_src(irp, instruction->target);
21802180}
21812181
2182static void ir_print_int_to_err(IrPrintGen *irp, IrInstGenIntToErr *instruction) {
2182static void ir_print_int_to_err(IrPrintGen *irp, Stage1AirInstIntToErr *instruction) {
21832183 fprintf(irp->f, "inttoerr ");
21842184 ir_print_other_inst_gen(irp, instruction->target);
21852185}
21862186
2187static void ir_print_err_to_int(IrPrintSrc *irp, IrInstSrcErrToInt *instruction) {
2187static void ir_print_err_to_int(IrPrintSrc *irp, Stage1ZirInstErrToInt *instruction) {
21882188 fprintf(irp->f, "errtoint ");
21892189 ir_print_other_inst_src(irp, instruction->target);
21902190}
21912191
2192static void ir_print_err_to_int(IrPrintGen *irp, IrInstGenErrToInt *instruction) {
2192static void ir_print_err_to_int(IrPrintGen *irp, Stage1AirInstErrToInt *instruction) {
21932193 fprintf(irp->f, "errtoint ");
21942194 ir_print_other_inst_gen(irp, instruction->target);
21952195}
21962196
2197static void ir_print_check_switch_prongs(IrPrintSrc *irp, IrInstSrcCheckSwitchProngs *instruction,
2197static void ir_print_check_switch_prongs(IrPrintSrc *irp, Stage1ZirInstCheckSwitchProngs *instruction,
21982198 bool have_underscore_prong)
21992199{
22002200 fprintf(irp->f, "@checkSwitchProngs(");
......@@ -2213,28 +2213,28 @@ static void ir_print_check_switch_prongs(IrPrintSrc *irp, IrInstSrcCheckSwitchPr
22132213 fprintf(irp->f, " _:%s", have_under_str);
22142214}
22152215
2216static void ir_print_check_statement_is_void(IrPrintSrc *irp, IrInstSrcCheckStatementIsVoid *instruction) {
2216static void ir_print_check_statement_is_void(IrPrintSrc *irp, Stage1ZirInstCheckStatementIsVoid *instruction) {
22172217 fprintf(irp->f, "@checkStatementIsVoid(");
22182218 ir_print_other_inst_src(irp, instruction->statement_value);
22192219 fprintf(irp->f, ")");
22202220}
22212221
2222static void ir_print_type_name(IrPrintSrc *irp, IrInstSrcTypeName *instruction) {
2222static void ir_print_type_name(IrPrintSrc *irp, Stage1ZirInstTypeName *instruction) {
22232223 fprintf(irp->f, "typename ");
22242224 ir_print_other_inst_src(irp, instruction->type_value);
22252225}
22262226
2227static void ir_print_tag_name(IrPrintSrc *irp, IrInstSrcTagName *instruction) {
2227static void ir_print_tag_name(IrPrintSrc *irp, Stage1ZirInstTagName *instruction) {
22282228 fprintf(irp->f, "tagname ");
22292229 ir_print_other_inst_src(irp, instruction->target);
22302230}
22312231
2232static void ir_print_tag_name(IrPrintGen *irp, IrInstGenTagName *instruction) {
2232static void ir_print_tag_name(IrPrintGen *irp, Stage1AirInstTagName *instruction) {
22332233 fprintf(irp->f, "tagname ");
22342234 ir_print_other_inst_gen(irp, instruction->target);
22352235}
22362236
2237static void ir_print_ptr_type(IrPrintSrc *irp, IrInstSrcPtrType *instruction) {
2237static void ir_print_ptr_type(IrPrintSrc *irp, Stage1ZirInstPtrType *instruction) {
22382238 fprintf(irp->f, "&");
22392239 if (instruction->align_value != nullptr) {
22402240 fprintf(irp->f, "align(");
......@@ -2248,7 +2248,7 @@ static void ir_print_ptr_type(IrPrintSrc *irp, IrInstSrcPtrType *instruction) {
22482248 ir_print_other_inst_src(irp, instruction->child_type);
22492249}
22502250
2251static void ir_print_ptr_type_simple(IrPrintSrc *irp, IrInstSrcPtrTypeSimple *instruction,
2251static void ir_print_ptr_type_simple(IrPrintSrc *irp, Stage1ZirInstPtrTypeSimple *instruction,
22522252 bool is_const)
22532253{
22542254 fprintf(irp->f, "&");
......@@ -2257,24 +2257,24 @@ static void ir_print_ptr_type_simple(IrPrintSrc *irp, IrInstSrcPtrTypeSimple *in
22572257 ir_print_other_inst_src(irp, instruction->child_type);
22582258}
22592259
2260static void ir_print_decl_ref(IrPrintSrc *irp, IrInstSrcDeclRef *instruction) {
2260static void ir_print_decl_ref(IrPrintSrc *irp, Stage1ZirInstDeclRef *instruction) {
22612261 const char *ptr_str = (instruction->lval != LValNone) ? "ptr " : "";
22622262 fprintf(irp->f, "declref %s%s", ptr_str, buf_ptr(instruction->tld->name));
22632263}
22642264
2265static void ir_print_panic(IrPrintSrc *irp, IrInstSrcPanic *instruction) {
2265static void ir_print_panic(IrPrintSrc *irp, Stage1ZirInstPanic *instruction) {
22662266 fprintf(irp->f, "@panic(");
22672267 ir_print_other_inst_src(irp, instruction->msg);
22682268 fprintf(irp->f, ")");
22692269}
22702270
2271static void ir_print_panic(IrPrintGen *irp, IrInstGenPanic *instruction) {
2271static void ir_print_panic(IrPrintGen *irp, Stage1AirInstPanic *instruction) {
22722272 fprintf(irp->f, "@panic(");
22732273 ir_print_other_inst_gen(irp, instruction->msg);
22742274 fprintf(irp->f, ")");
22752275}
22762276
2277static void ir_print_field_parent_ptr(IrPrintSrc *irp, IrInstSrcFieldParentPtr *instruction) {
2277static void ir_print_field_parent_ptr(IrPrintSrc *irp, Stage1ZirInstFieldParentPtr *instruction) {
22782278 fprintf(irp->f, "@fieldParentPtr(");
22792279 ir_print_other_inst_src(irp, instruction->type_value);
22802280 fprintf(irp->f, ",");
......@@ -2284,13 +2284,13 @@ static void ir_print_field_parent_ptr(IrPrintSrc *irp, IrInstSrcFieldParentPtr *
22842284 fprintf(irp->f, ")");
22852285}
22862286
2287static void ir_print_field_parent_ptr(IrPrintGen *irp, IrInstGenFieldParentPtr *instruction) {
2287static void ir_print_field_parent_ptr(IrPrintGen *irp, Stage1AirInstFieldParentPtr *instruction) {
22882288 fprintf(irp->f, "@fieldParentPtr(%s,", buf_ptr(instruction->field->name));
22892289 ir_print_other_inst_gen(irp, instruction->field_ptr);
22902290 fprintf(irp->f, ")");
22912291}
22922292
2293static void ir_print_offset_of(IrPrintSrc *irp, IrInstSrcOffsetOf *instruction) {
2293static void ir_print_offset_of(IrPrintSrc *irp, Stage1ZirInstOffsetOf *instruction) {
22942294 fprintf(irp->f, "@offset_of(");
22952295 ir_print_other_inst_src(irp, instruction->type_value);
22962296 fprintf(irp->f, ",");
......@@ -2298,7 +2298,7 @@ static void ir_print_offset_of(IrPrintSrc *irp, IrInstSrcOffsetOf *instruction)
22982298 fprintf(irp->f, ")");
22992299}
23002300
2301static void ir_print_bit_offset_of(IrPrintSrc *irp, IrInstSrcBitOffsetOf *instruction) {
2301static void ir_print_bit_offset_of(IrPrintSrc *irp, Stage1ZirInstBitOffsetOf *instruction) {
23022302 fprintf(irp->f, "@bit_offset_of(");
23032303 ir_print_other_inst_src(irp, instruction->type_value);
23042304 fprintf(irp->f, ",");
......@@ -2306,19 +2306,19 @@ static void ir_print_bit_offset_of(IrPrintSrc *irp, IrInstSrcBitOffsetOf *instru
23062306 fprintf(irp->f, ")");
23072307}
23082308
2309static void ir_print_type_info(IrPrintSrc *irp, IrInstSrcTypeInfo *instruction) {
2309static void ir_print_type_info(IrPrintSrc *irp, Stage1ZirInstTypeInfo *instruction) {
23102310 fprintf(irp->f, "@typeInfo(");
23112311 ir_print_other_inst_src(irp, instruction->type_value);
23122312 fprintf(irp->f, ")");
23132313}
23142314
2315static void ir_print_type(IrPrintSrc *irp, IrInstSrcType *instruction) {
2315static void ir_print_type(IrPrintSrc *irp, Stage1ZirInstType *instruction) {
23162316 fprintf(irp->f, "@Type(");
23172317 ir_print_other_inst_src(irp, instruction->type_info);
23182318 fprintf(irp->f, ")");
23192319}
23202320
2321static void ir_print_has_field(IrPrintSrc *irp, IrInstSrcHasField *instruction) {
2321static void ir_print_has_field(IrPrintSrc *irp, Stage1ZirInstHasField *instruction) {
23222322 fprintf(irp->f, "@hasField(");
23232323 ir_print_other_inst_src(irp, instruction->container_type);
23242324 fprintf(irp->f, ",");
......@@ -2326,13 +2326,13 @@ static void ir_print_has_field(IrPrintSrc *irp, IrInstSrcHasField *instruction)
23262326 fprintf(irp->f, ")");
23272327}
23282328
2329static void ir_print_set_eval_branch_quota(IrPrintSrc *irp, IrInstSrcSetEvalBranchQuota *instruction) {
2329static void ir_print_set_eval_branch_quota(IrPrintSrc *irp, Stage1ZirInstSetEvalBranchQuota *instruction) {
23302330 fprintf(irp->f, "@setEvalBranchQuota(");
23312331 ir_print_other_inst_src(irp, instruction->new_quota);
23322332 fprintf(irp->f, ")");
23332333}
23342334
2335static void ir_print_align_cast(IrPrintSrc *irp, IrInstSrcAlignCast *instruction) {
2335static void ir_print_align_cast(IrPrintSrc *irp, Stage1ZirInstAlignCast *instruction) {
23362336 fprintf(irp->f, "@alignCast(");
23372337 ir_print_other_inst_src(irp, instruction->align_bytes);
23382338 fprintf(irp->f, ",");
......@@ -2340,31 +2340,31 @@ static void ir_print_align_cast(IrPrintSrc *irp, IrInstSrcAlignCast *instruction
23402340 fprintf(irp->f, ")");
23412341}
23422342
2343static void ir_print_align_cast(IrPrintGen *irp, IrInstGenAlignCast *instruction) {
2343static void ir_print_align_cast(IrPrintGen *irp, Stage1AirInstAlignCast *instruction) {
23442344 fprintf(irp->f, "@alignCast(");
23452345 ir_print_other_inst_gen(irp, instruction->target);
23462346 fprintf(irp->f, ")");
23472347}
23482348
2349static void ir_print_resolve_result(IrPrintSrc *irp, IrInstSrcResolveResult *instruction) {
2349static void ir_print_resolve_result(IrPrintSrc *irp, Stage1ZirInstResolveResult *instruction) {
23502350 fprintf(irp->f, "ResolveResult(");
23512351 ir_print_result_loc(irp, instruction->result_loc);
23522352 fprintf(irp->f, ")");
23532353}
23542354
2355static void ir_print_reset_result(IrPrintSrc *irp, IrInstSrcResetResult *instruction) {
2355static void ir_print_reset_result(IrPrintSrc *irp, Stage1ZirInstResetResult *instruction) {
23562356 fprintf(irp->f, "ResetResult(");
23572357 ir_print_result_loc(irp, instruction->result_loc);
23582358 fprintf(irp->f, ")");
23592359}
23602360
2361static void ir_print_set_align_stack(IrPrintSrc *irp, IrInstSrcSetAlignStack *instruction) {
2361static void ir_print_set_align_stack(IrPrintSrc *irp, Stage1ZirInstSetAlignStack *instruction) {
23622362 fprintf(irp->f, "@setAlignStack(");
23632363 ir_print_other_inst_src(irp, instruction->align_bytes);
23642364 fprintf(irp->f, ")");
23652365}
23662366
2367static void ir_print_arg_type(IrPrintSrc *irp, IrInstSrcArgType *instruction, bool allow_var) {
2367static void ir_print_arg_type(IrPrintSrc *irp, Stage1ZirInstArgType *instruction, bool allow_var) {
23682368 fprintf(irp->f, "@ArgType(");
23692369 ir_print_other_inst_src(irp, instruction->fn_type);
23702370 fprintf(irp->f, ",");
......@@ -2378,7 +2378,7 @@ static void ir_print_arg_type(IrPrintSrc *irp, IrInstSrcArgType *instruction, bo
23782378 fprintf(irp->f, ")");
23792379}
23802380
2381static void ir_print_export(IrPrintSrc *irp, IrInstSrcExport *instruction) {
2381static void ir_print_export(IrPrintSrc *irp, Stage1ZirInstExport *instruction) {
23822382 fprintf(irp->f, "@export(");
23832383 ir_print_other_inst_src(irp, instruction->target);
23842384 fprintf(irp->f, ",");
......@@ -2386,11 +2386,11 @@ static void ir_print_export(IrPrintSrc *irp, IrInstSrcExport *instruction) {
23862386 fprintf(irp->f, ")");
23872387}
23882388
2389static void ir_print_extern(IrPrintGen *irp, IrInstGenExtern *instruction) {
2389static void ir_print_extern(IrPrintGen *irp, Stage1AirInstExtern *instruction) {
23902390 fprintf(irp->f, "@extern(...)");
23912391}
23922392
2393static void ir_print_extern(IrPrintSrc *irp, IrInstSrcExtern *instruction) {
2393static void ir_print_extern(IrPrintSrc *irp, Stage1ZirInstExtern *instruction) {
23942394 fprintf(irp->f, "@extern(");
23952395 ir_print_other_inst_src(irp, instruction->type);
23962396 fprintf(irp->f, ",");
......@@ -2398,7 +2398,7 @@ static void ir_print_extern(IrPrintSrc *irp, IrInstSrcExtern *instruction) {
23982398 fprintf(irp->f, ")");
23992399}
24002400
2401static void ir_print_error_return_trace(IrPrintSrc *irp, IrInstSrcErrorReturnTrace *instruction) {
2401static void ir_print_error_return_trace(IrPrintSrc *irp, Stage1ZirInstErrorReturnTrace *instruction) {
24022402 fprintf(irp->f, "@errorReturnTrace(");
24032403 switch (instruction->optional) {
24042404 case IrInstErrorReturnTraceNull:
......@@ -2411,7 +2411,7 @@ static void ir_print_error_return_trace(IrPrintSrc *irp, IrInstSrcErrorReturnTra
24112411 fprintf(irp->f, ")");
24122412}
24132413
2414static void ir_print_error_return_trace(IrPrintGen *irp, IrInstGenErrorReturnTrace *instruction) {
2414static void ir_print_error_return_trace(IrPrintGen *irp, Stage1AirInstErrorReturnTrace *instruction) {
24152415 fprintf(irp->f, "@errorReturnTrace(");
24162416 switch (instruction->optional) {
24172417 case IrInstErrorReturnTraceNull:
......@@ -2424,13 +2424,13 @@ static void ir_print_error_return_trace(IrPrintGen *irp, IrInstGenErrorReturnTra
24242424 fprintf(irp->f, ")");
24252425}
24262426
2427static void ir_print_error_union(IrPrintSrc *irp, IrInstSrcErrorUnion *instruction) {
2427static void ir_print_error_union(IrPrintSrc *irp, Stage1ZirInstErrorUnion *instruction) {
24282428 ir_print_other_inst_src(irp, instruction->err_set);
24292429 fprintf(irp->f, "!");
24302430 ir_print_other_inst_src(irp, instruction->payload);
24312431}
24322432
2433static void ir_print_atomic_rmw(IrPrintSrc *irp, IrInstSrcAtomicRmw *instruction) {
2433static void ir_print_atomic_rmw(IrPrintSrc *irp, Stage1ZirInstAtomicRmw *instruction) {
24342434 fprintf(irp->f, "@atomicRmw(");
24352435 ir_print_other_inst_src(irp, instruction->operand_type);
24362436 fprintf(irp->f, ",");
......@@ -2444,7 +2444,7 @@ static void ir_print_atomic_rmw(IrPrintSrc *irp, IrInstSrcAtomicRmw *instruction
24442444 fprintf(irp->f, ")");
24452445}
24462446
2447static void ir_print_atomic_rmw(IrPrintGen *irp, IrInstGenAtomicRmw *instruction) {
2447static void ir_print_atomic_rmw(IrPrintGen *irp, Stage1AirInstAtomicRmw *instruction) {
24482448 fprintf(irp->f, "@atomicRmw(");
24492449 ir_print_other_inst_gen(irp, instruction->ptr);
24502450 fprintf(irp->f, ",[TODO print op],");
......@@ -2452,7 +2452,7 @@ static void ir_print_atomic_rmw(IrPrintGen *irp, IrInstGenAtomicRmw *instruction
24522452 fprintf(irp->f, ",%s)", atomic_order_str(instruction->ordering));
24532453}
24542454
2455static void ir_print_atomic_load(IrPrintSrc *irp, IrInstSrcAtomicLoad *instruction) {
2455static void ir_print_atomic_load(IrPrintSrc *irp, Stage1ZirInstAtomicLoad *instruction) {
24562456 fprintf(irp->f, "@atomicLoad(");
24572457 ir_print_other_inst_src(irp, instruction->operand_type);
24582458 fprintf(irp->f, ",");
......@@ -2462,13 +2462,13 @@ static void ir_print_atomic_load(IrPrintSrc *irp, IrInstSrcAtomicLoad *instructi
24622462 fprintf(irp->f, ")");
24632463}
24642464
2465static void ir_print_atomic_load(IrPrintGen *irp, IrInstGenAtomicLoad *instruction) {
2465static void ir_print_atomic_load(IrPrintGen *irp, Stage1AirInstAtomicLoad *instruction) {
24662466 fprintf(irp->f, "@atomicLoad(");
24672467 ir_print_other_inst_gen(irp, instruction->ptr);
24682468 fprintf(irp->f, ",%s)", atomic_order_str(instruction->ordering));
24692469}
24702470
2471static void ir_print_atomic_store(IrPrintSrc *irp, IrInstSrcAtomicStore *instruction) {
2471static void ir_print_atomic_store(IrPrintSrc *irp, Stage1ZirInstAtomicStore *instruction) {
24722472 fprintf(irp->f, "@atomicStore(");
24732473 ir_print_other_inst_src(irp, instruction->operand_type);
24742474 fprintf(irp->f, ",");
......@@ -2480,7 +2480,7 @@ static void ir_print_atomic_store(IrPrintSrc *irp, IrInstSrcAtomicStore *instruc
24802480 fprintf(irp->f, ")");
24812481}
24822482
2483static void ir_print_atomic_store(IrPrintGen *irp, IrInstGenAtomicStore *instruction) {
2483static void ir_print_atomic_store(IrPrintGen *irp, Stage1AirInstAtomicStore *instruction) {
24842484 fprintf(irp->f, "@atomicStore(");
24852485 ir_print_other_inst_gen(irp, instruction->ptr);
24862486 fprintf(irp->f, ",");
......@@ -2489,33 +2489,33 @@ static void ir_print_atomic_store(IrPrintGen *irp, IrInstGenAtomicStore *instruc
24892489}
24902490
24912491
2492static void ir_print_save_err_ret_addr(IrPrintSrc *irp, IrInstSrcSaveErrRetAddr *instruction) {
2492static void ir_print_save_err_ret_addr(IrPrintSrc *irp, Stage1ZirInstSaveErrRetAddr *instruction) {
24932493 fprintf(irp->f, "@saveErrRetAddr()");
24942494}
24952495
2496static void ir_print_save_err_ret_addr(IrPrintGen *irp, IrInstGenSaveErrRetAddr *instruction) {
2496static void ir_print_save_err_ret_addr(IrPrintGen *irp, Stage1AirInstSaveErrRetAddr *instruction) {
24972497 fprintf(irp->f, "@saveErrRetAddr()");
24982498}
24992499
2500static void ir_print_add_implicit_return_type(IrPrintSrc *irp, IrInstSrcAddImplicitReturnType *instruction) {
2500static void ir_print_add_implicit_return_type(IrPrintSrc *irp, Stage1ZirInstAddImplicitReturnType *instruction) {
25012501 fprintf(irp->f, "@addImplicitReturnType(");
25022502 ir_print_other_inst_src(irp, instruction->value);
25032503 fprintf(irp->f, ")");
25042504}
25052505
2506static void ir_print_float_op(IrPrintSrc *irp, IrInstSrcFloatOp *instruction) {
2506static void ir_print_float_op(IrPrintSrc *irp, Stage1ZirInstFloatOp *instruction) {
25072507 fprintf(irp->f, "@%s(", float_op_to_name(instruction->fn_id));
25082508 ir_print_other_inst_src(irp, instruction->operand);
25092509 fprintf(irp->f, ")");
25102510}
25112511
2512static void ir_print_float_op(IrPrintGen *irp, IrInstGenFloatOp *instruction) {
2512static void ir_print_float_op(IrPrintGen *irp, Stage1AirInstFloatOp *instruction) {
25132513 fprintf(irp->f, "@%s(", float_op_to_name(instruction->fn_id));
25142514 ir_print_other_inst_gen(irp, instruction->operand);
25152515 fprintf(irp->f, ")");
25162516}
25172517
2518static void ir_print_mul_add(IrPrintSrc *irp, IrInstSrcMulAdd *instruction) {
2518static void ir_print_mul_add(IrPrintSrc *irp, Stage1ZirInstMulAdd *instruction) {
25192519 fprintf(irp->f, "@mulAdd(");
25202520 ir_print_other_inst_src(irp, instruction->type_value);
25212521 fprintf(irp->f, ",");
......@@ -2527,7 +2527,7 @@ static void ir_print_mul_add(IrPrintSrc *irp, IrInstSrcMulAdd *instruction) {
25272527 fprintf(irp->f, ")");
25282528}
25292529
2530static void ir_print_mul_add(IrPrintGen *irp, IrInstGenMulAdd *instruction) {
2530static void ir_print_mul_add(IrPrintGen *irp, Stage1AirInstMulAdd *instruction) {
25312531 fprintf(irp->f, "@mulAdd(");
25322532 ir_print_other_inst_gen(irp, instruction->op1);
25332533 fprintf(irp->f, ",");
......@@ -2537,7 +2537,7 @@ static void ir_print_mul_add(IrPrintGen *irp, IrInstGenMulAdd *instruction) {
25372537 fprintf(irp->f, ")");
25382538}
25392539
2540static void ir_print_decl_var_gen(IrPrintGen *irp, IrInstGenDeclVar *decl_var_instruction) {
2540static void ir_print_decl_var_gen(IrPrintGen *irp, Stage1AirInstDeclVar *decl_var_instruction) {
25412541 ZigVar *var = decl_var_instruction->var;
25422542 const char *var_or_const = decl_var_instruction->var->gen_is_const ? "const" : "var";
25432543 const char *name = decl_var_instruction->var->name;
......@@ -2547,7 +2547,7 @@ static void ir_print_decl_var_gen(IrPrintGen *irp, IrInstGenDeclVar *decl_var_in
25472547 ir_print_other_inst_gen(irp, decl_var_instruction->var_ptr);
25482548}
25492549
2550static void ir_print_has_decl(IrPrintSrc *irp, IrInstSrcHasDecl *instruction) {
2550static void ir_print_has_decl(IrPrintSrc *irp, Stage1ZirInstHasDecl *instruction) {
25512551 fprintf(irp->f, "@hasDecl(");
25522552 ir_print_other_inst_src(irp, instruction->container);
25532553 fprintf(irp->f, ",");
......@@ -2555,11 +2555,11 @@ static void ir_print_has_decl(IrPrintSrc *irp, IrInstSrcHasDecl *instruction) {
25552555 fprintf(irp->f, ")");
25562556}
25572557
2558static void ir_print_undeclared_ident(IrPrintSrc *irp, IrInstSrcUndeclaredIdent *instruction) {
2558static void ir_print_undeclared_ident(IrPrintSrc *irp, Stage1ZirInstUndeclaredIdent *instruction) {
25592559 fprintf(irp->f, "@undeclaredIdent(%s)", buf_ptr(instruction->name));
25602560}
25612561
2562static void ir_print_union_init_named_field(IrPrintSrc *irp, IrInstSrcUnionInitNamedField *instruction) {
2562static void ir_print_union_init_named_field(IrPrintSrc *irp, Stage1ZirInstUnionInitNamedField *instruction) {
25632563 fprintf(irp->f, "@unionInit(");
25642564 ir_print_other_inst_src(irp, instruction->union_type);
25652565 fprintf(irp->f, ", ");
......@@ -2571,33 +2571,33 @@ static void ir_print_union_init_named_field(IrPrintSrc *irp, IrInstSrcUnionInitN
25712571 fprintf(irp->f, ")");
25722572}
25732573
2574static void ir_print_suspend_begin(IrPrintSrc *irp, IrInstSrcSuspendBegin *instruction) {
2574static void ir_print_suspend_begin(IrPrintSrc *irp, Stage1ZirInstSuspendBegin *instruction) {
25752575 fprintf(irp->f, "@suspendBegin()");
25762576}
25772577
2578static void ir_print_suspend_begin(IrPrintGen *irp, IrInstGenSuspendBegin *instruction) {
2578static void ir_print_suspend_begin(IrPrintGen *irp, Stage1AirInstSuspendBegin *instruction) {
25792579 fprintf(irp->f, "@suspendBegin()");
25802580}
25812581
2582static void ir_print_suspend_finish(IrPrintSrc *irp, IrInstSrcSuspendFinish *instruction) {
2582static void ir_print_suspend_finish(IrPrintSrc *irp, Stage1ZirInstSuspendFinish *instruction) {
25832583 fprintf(irp->f, "@suspendFinish()");
25842584}
25852585
2586static void ir_print_suspend_finish(IrPrintGen *irp, IrInstGenSuspendFinish *instruction) {
2586static void ir_print_suspend_finish(IrPrintGen *irp, Stage1AirInstSuspendFinish *instruction) {
25872587 fprintf(irp->f, "@suspendFinish()");
25882588}
25892589
2590static void ir_print_resume(IrPrintSrc *irp, IrInstSrcResume *instruction) {
2590static void ir_print_resume(IrPrintSrc *irp, Stage1ZirInstResume *instruction) {
25912591 fprintf(irp->f, "resume ");
25922592 ir_print_other_inst_src(irp, instruction->frame);
25932593}
25942594
2595static void ir_print_resume(IrPrintGen *irp, IrInstGenResume *instruction) {
2595static void ir_print_resume(IrPrintGen *irp, Stage1AirInstResume *instruction) {
25962596 fprintf(irp->f, "resume ");
25972597 ir_print_other_inst_gen(irp, instruction->frame);
25982598}
25992599
2600static void ir_print_await_src(IrPrintSrc *irp, IrInstSrcAwait *instruction) {
2600static void ir_print_await_src(IrPrintSrc *irp, Stage1ZirInstAwait *instruction) {
26012601 fprintf(irp->f, "@await(");
26022602 ir_print_other_inst_src(irp, instruction->frame);
26032603 fprintf(irp->f, ",");
......@@ -2605,7 +2605,7 @@ static void ir_print_await_src(IrPrintSrc *irp, IrInstSrcAwait *instruction) {
26052605 fprintf(irp->f, ")");
26062606}
26072607
2608static void ir_print_await_gen(IrPrintGen *irp, IrInstGenAwait *instruction) {
2608static void ir_print_await_gen(IrPrintGen *irp, Stage1AirInstAwait *instruction) {
26092609 fprintf(irp->f, "@await(");
26102610 ir_print_other_inst_gen(irp, instruction->frame);
26112611 fprintf(irp->f, ",");
......@@ -2613,31 +2613,31 @@ static void ir_print_await_gen(IrPrintGen *irp, IrInstGenAwait *instruction) {
26132613 fprintf(irp->f, ")");
26142614}
26152615
2616static void ir_print_spill_begin(IrPrintSrc *irp, IrInstSrcSpillBegin *instruction) {
2616static void ir_print_spill_begin(IrPrintSrc *irp, Stage1ZirInstSpillBegin *instruction) {
26172617 fprintf(irp->f, "@spillBegin(");
26182618 ir_print_other_inst_src(irp, instruction->operand);
26192619 fprintf(irp->f, ")");
26202620}
26212621
2622static void ir_print_spill_begin(IrPrintGen *irp, IrInstGenSpillBegin *instruction) {
2622static void ir_print_spill_begin(IrPrintGen *irp, Stage1AirInstSpillBegin *instruction) {
26232623 fprintf(irp->f, "@spillBegin(");
26242624 ir_print_other_inst_gen(irp, instruction->operand);
26252625 fprintf(irp->f, ")");
26262626}
26272627
2628static void ir_print_spill_end(IrPrintSrc *irp, IrInstSrcSpillEnd *instruction) {
2628static void ir_print_spill_end(IrPrintSrc *irp, Stage1ZirInstSpillEnd *instruction) {
26292629 fprintf(irp->f, "@spillEnd(");
26302630 ir_print_other_inst_src(irp, &instruction->begin->base);
26312631 fprintf(irp->f, ")");
26322632}
26332633
2634static void ir_print_spill_end(IrPrintGen *irp, IrInstGenSpillEnd *instruction) {
2634static void ir_print_spill_end(IrPrintGen *irp, Stage1AirInstSpillEnd *instruction) {
26352635 fprintf(irp->f, "@spillEnd(");
26362636 ir_print_other_inst_gen(irp, &instruction->begin->base);
26372637 fprintf(irp->f, ")");
26382638}
26392639
2640static void ir_print_vector_extract_elem(IrPrintGen *irp, IrInstGenVectorExtractElem *instruction) {
2640static void ir_print_vector_extract_elem(IrPrintGen *irp, Stage1AirInstVectorExtractElem *instruction) {
26412641 fprintf(irp->f, "@vectorExtractElem(");
26422642 ir_print_other_inst_gen(irp, instruction->vector);
26432643 fprintf(irp->f, ",");
......@@ -2645,703 +2645,703 @@ static void ir_print_vector_extract_elem(IrPrintGen *irp, IrInstGenVectorExtract
26452645 fprintf(irp->f, ")");
26462646}
26472647
2648static void ir_print_inst_src(IrPrintSrc *irp, IrInstSrc *instruction, bool trailing) {
2648static void ir_print_inst_src(IrPrintSrc *irp, Stage1ZirInst *instruction, bool trailing) {
26492649 ir_print_prefix_src(irp, instruction, trailing);
26502650 switch (instruction->id) {
2651 case IrInstSrcIdInvalid:
2651 case Stage1ZirInstIdInvalid:
26522652 zig_unreachable();
2653 case IrInstSrcIdReturn:
2654 ir_print_return_src(irp, (IrInstSrcReturn *)instruction);
2653 case Stage1ZirInstIdReturn:
2654 ir_print_return_src(irp, (Stage1ZirInstReturn *)instruction);
26552655 break;
2656 case IrInstSrcIdConst:
2657 ir_print_const(irp, (IrInstSrcConst *)instruction);
2656 case Stage1ZirInstIdConst:
2657 ir_print_const(irp, (Stage1ZirInstConst *)instruction);
26582658 break;
2659 case IrInstSrcIdBinOp:
2660 ir_print_bin_op(irp, (IrInstSrcBinOp *)instruction);
2659 case Stage1ZirInstIdBinOp:
2660 ir_print_bin_op(irp, (Stage1ZirInstBinOp *)instruction);
26612661 break;
2662 case IrInstSrcIdMergeErrSets:
2663 ir_print_merge_err_sets(irp, (IrInstSrcMergeErrSets *)instruction);
2662 case Stage1ZirInstIdMergeErrSets:
2663 ir_print_merge_err_sets(irp, (Stage1ZirInstMergeErrSets *)instruction);
26642664 break;
2665 case IrInstSrcIdDeclVar:
2666 ir_print_decl_var_src(irp, (IrInstSrcDeclVar *)instruction);
2665 case Stage1ZirInstIdDeclVar:
2666 ir_print_decl_var_src(irp, (Stage1ZirInstDeclVar *)instruction);
26672667 break;
2668 case IrInstSrcIdCallExtra:
2669 ir_print_call_extra(irp, (IrInstSrcCallExtra *)instruction);
2668 case Stage1ZirInstIdCallExtra:
2669 ir_print_call_extra(irp, (Stage1ZirInstCallExtra *)instruction);
26702670 break;
2671 case IrInstSrcIdAsyncCallExtra:
2672 ir_print_async_call_extra(irp, (IrInstSrcAsyncCallExtra *)instruction);
2671 case Stage1ZirInstIdAsyncCallExtra:
2672 ir_print_async_call_extra(irp, (Stage1ZirInstAsyncCallExtra *)instruction);
26732673 break;
2674 case IrInstSrcIdCall:
2675 ir_print_call_src(irp, (IrInstSrcCall *)instruction);
2674 case Stage1ZirInstIdCall:
2675 ir_print_call_src(irp, (Stage1ZirInstCall *)instruction);
26762676 break;
2677 case IrInstSrcIdCallArgs:
2678 ir_print_call_args(irp, (IrInstSrcCallArgs *)instruction);
2677 case Stage1ZirInstIdCallArgs:
2678 ir_print_call_args(irp, (Stage1ZirInstCallArgs *)instruction);
26792679 break;
2680 case IrInstSrcIdUnOp:
2681 ir_print_un_op(irp, (IrInstSrcUnOp *)instruction);
2680 case Stage1ZirInstIdUnOp:
2681 ir_print_un_op(irp, (Stage1ZirInstUnOp *)instruction);
26822682 break;
2683 case IrInstSrcIdCondBr:
2684 ir_print_cond_br(irp, (IrInstSrcCondBr *)instruction);
2683 case Stage1ZirInstIdCondBr:
2684 ir_print_cond_br(irp, (Stage1ZirInstCondBr *)instruction);
26852685 break;
2686 case IrInstSrcIdBr:
2687 ir_print_br(irp, (IrInstSrcBr *)instruction);
2686 case Stage1ZirInstIdBr:
2687 ir_print_br(irp, (Stage1ZirInstBr *)instruction);
26882688 break;
2689 case IrInstSrcIdPhi:
2690 ir_print_phi(irp, (IrInstSrcPhi *)instruction);
2689 case Stage1ZirInstIdPhi:
2690 ir_print_phi(irp, (Stage1ZirInstPhi *)instruction);
26912691 break;
2692 case IrInstSrcIdContainerInitList:
2693 ir_print_container_init_list(irp, (IrInstSrcContainerInitList *)instruction);
2692 case Stage1ZirInstIdContainerInitList:
2693 ir_print_container_init_list(irp, (Stage1ZirInstContainerInitList *)instruction);
26942694 break;
2695 case IrInstSrcIdContainerInitFields:
2696 ir_print_container_init_fields(irp, (IrInstSrcContainerInitFields *)instruction);
2695 case Stage1ZirInstIdContainerInitFields:
2696 ir_print_container_init_fields(irp, (Stage1ZirInstContainerInitFields *)instruction);
26972697 break;
2698 case IrInstSrcIdUnreachable:
2699 ir_print_unreachable(irp, (IrInstSrcUnreachable *)instruction);
2698 case Stage1ZirInstIdUnreachable:
2699 ir_print_unreachable(irp, (Stage1ZirInstUnreachable *)instruction);
27002700 break;
2701 case IrInstSrcIdElemPtr:
2702 ir_print_elem_ptr(irp, (IrInstSrcElemPtr *)instruction);
2701 case Stage1ZirInstIdElemPtr:
2702 ir_print_elem_ptr(irp, (Stage1ZirInstElemPtr *)instruction);
27032703 break;
2704 case IrInstSrcIdVarPtr:
2705 ir_print_var_ptr(irp, (IrInstSrcVarPtr *)instruction);
2704 case Stage1ZirInstIdVarPtr:
2705 ir_print_var_ptr(irp, (Stage1ZirInstVarPtr *)instruction);
27062706 break;
2707 case IrInstSrcIdLoadPtr:
2708 ir_print_load_ptr(irp, (IrInstSrcLoadPtr *)instruction);
2707 case Stage1ZirInstIdLoadPtr:
2708 ir_print_load_ptr(irp, (Stage1ZirInstLoadPtr *)instruction);
27092709 break;
2710 case IrInstSrcIdStorePtr:
2711 ir_print_store_ptr(irp, (IrInstSrcStorePtr *)instruction);
2710 case Stage1ZirInstIdStorePtr:
2711 ir_print_store_ptr(irp, (Stage1ZirInstStorePtr *)instruction);
27122712 break;
2713 case IrInstSrcIdTypeOf:
2714 ir_print_typeof(irp, (IrInstSrcTypeOf *)instruction);
2713 case Stage1ZirInstIdTypeOf:
2714 ir_print_typeof(irp, (Stage1ZirInstTypeOf *)instruction);
27152715 break;
2716 case IrInstSrcIdFieldPtr:
2717 ir_print_field_ptr(irp, (IrInstSrcFieldPtr *)instruction);
2716 case Stage1ZirInstIdFieldPtr:
2717 ir_print_field_ptr(irp, (Stage1ZirInstFieldPtr *)instruction);
27182718 break;
2719 case IrInstSrcIdSetCold:
2720 ir_print_set_cold(irp, (IrInstSrcSetCold *)instruction);
2719 case Stage1ZirInstIdSetCold:
2720 ir_print_set_cold(irp, (Stage1ZirInstSetCold *)instruction);
27212721 break;
2722 case IrInstSrcIdSetRuntimeSafety:
2723 ir_print_set_runtime_safety(irp, (IrInstSrcSetRuntimeSafety *)instruction);
2722 case Stage1ZirInstIdSetRuntimeSafety:
2723 ir_print_set_runtime_safety(irp, (Stage1ZirInstSetRuntimeSafety *)instruction);
27242724 break;
2725 case IrInstSrcIdSetFloatMode:
2726 ir_print_set_float_mode(irp, (IrInstSrcSetFloatMode *)instruction);
2725 case Stage1ZirInstIdSetFloatMode:
2726 ir_print_set_float_mode(irp, (Stage1ZirInstSetFloatMode *)instruction);
27272727 break;
2728 case IrInstSrcIdArrayType:
2729 ir_print_array_type(irp, (IrInstSrcArrayType *)instruction);
2728 case Stage1ZirInstIdArrayType:
2729 ir_print_array_type(irp, (Stage1ZirInstArrayType *)instruction);
27302730 break;
2731 case IrInstSrcIdSliceType:
2732 ir_print_slice_type(irp, (IrInstSrcSliceType *)instruction);
2731 case Stage1ZirInstIdSliceType:
2732 ir_print_slice_type(irp, (Stage1ZirInstSliceType *)instruction);
27332733 break;
2734 case IrInstSrcIdAnyFrameType:
2735 ir_print_any_frame_type(irp, (IrInstSrcAnyFrameType *)instruction);
2734 case Stage1ZirInstIdAnyFrameType:
2735 ir_print_any_frame_type(irp, (Stage1ZirInstAnyFrameType *)instruction);
27362736 break;
2737 case IrInstSrcIdAsm:
2738 ir_print_asm_src(irp, (IrInstSrcAsm *)instruction);
2737 case Stage1ZirInstIdAsm:
2738 ir_print_asm_src(irp, (Stage1ZirInstAsm *)instruction);
27392739 break;
2740 case IrInstSrcIdSizeOf:
2741 ir_print_size_of(irp, (IrInstSrcSizeOf *)instruction);
2740 case Stage1ZirInstIdSizeOf:
2741 ir_print_size_of(irp, (Stage1ZirInstSizeOf *)instruction);
27422742 break;
2743 case IrInstSrcIdTestNonNull:
2744 ir_print_test_non_null(irp, (IrInstSrcTestNonNull *)instruction);
2743 case Stage1ZirInstIdTestNonNull:
2744 ir_print_test_non_null(irp, (Stage1ZirInstTestNonNull *)instruction);
27452745 break;
2746 case IrInstSrcIdOptionalUnwrapPtr:
2747 ir_print_optional_unwrap_ptr(irp, (IrInstSrcOptionalUnwrapPtr *)instruction);
2746 case Stage1ZirInstIdOptionalUnwrapPtr:
2747 ir_print_optional_unwrap_ptr(irp, (Stage1ZirInstOptionalUnwrapPtr *)instruction);
27482748 break;
2749 case IrInstSrcIdPopCount:
2750 ir_print_pop_count(irp, (IrInstSrcPopCount *)instruction);
2749 case Stage1ZirInstIdPopCount:
2750 ir_print_pop_count(irp, (Stage1ZirInstPopCount *)instruction);
27512751 break;
2752 case IrInstSrcIdCtz:
2753 ir_print_ctz(irp, (IrInstSrcCtz *)instruction);
2752 case Stage1ZirInstIdCtz:
2753 ir_print_ctz(irp, (Stage1ZirInstCtz *)instruction);
27542754 break;
2755 case IrInstSrcIdBswap:
2756 ir_print_bswap(irp, (IrInstSrcBswap *)instruction);
2755 case Stage1ZirInstIdBswap:
2756 ir_print_bswap(irp, (Stage1ZirInstBswap *)instruction);
27572757 break;
2758 case IrInstSrcIdBitReverse:
2759 ir_print_bit_reverse(irp, (IrInstSrcBitReverse *)instruction);
2758 case Stage1ZirInstIdBitReverse:
2759 ir_print_bit_reverse(irp, (Stage1ZirInstBitReverse *)instruction);
27602760 break;
2761 case IrInstSrcIdSwitchBr:
2762 ir_print_switch_br(irp, (IrInstSrcSwitchBr *)instruction);
2761 case Stage1ZirInstIdSwitchBr:
2762 ir_print_switch_br(irp, (Stage1ZirInstSwitchBr *)instruction);
27632763 break;
2764 case IrInstSrcIdSwitchVar:
2765 ir_print_switch_var(irp, (IrInstSrcSwitchVar *)instruction);
2764 case Stage1ZirInstIdSwitchVar:
2765 ir_print_switch_var(irp, (Stage1ZirInstSwitchVar *)instruction);
27662766 break;
2767 case IrInstSrcIdSwitchElseVar:
2768 ir_print_switch_else_var(irp, (IrInstSrcSwitchElseVar *)instruction);
2767 case Stage1ZirInstIdSwitchElseVar:
2768 ir_print_switch_else_var(irp, (Stage1ZirInstSwitchElseVar *)instruction);
27692769 break;
2770 case IrInstSrcIdSwitchTarget:
2771 ir_print_switch_target(irp, (IrInstSrcSwitchTarget *)instruction);
2770 case Stage1ZirInstIdSwitchTarget:
2771 ir_print_switch_target(irp, (Stage1ZirInstSwitchTarget *)instruction);
27722772 break;
2773 case IrInstSrcIdImport:
2774 ir_print_import(irp, (IrInstSrcImport *)instruction);
2773 case Stage1ZirInstIdImport:
2774 ir_print_import(irp, (Stage1ZirInstImport *)instruction);
27752775 break;
2776 case IrInstSrcIdRef:
2777 ir_print_ref(irp, (IrInstSrcRef *)instruction);
2776 case Stage1ZirInstIdRef:
2777 ir_print_ref(irp, (Stage1ZirInstRef *)instruction);
27782778 break;
2779 case IrInstSrcIdCompileErr:
2780 ir_print_compile_err(irp, (IrInstSrcCompileErr *)instruction);
2779 case Stage1ZirInstIdCompileErr:
2780 ir_print_compile_err(irp, (Stage1ZirInstCompileErr *)instruction);
27812781 break;
2782 case IrInstSrcIdCompileLog:
2783 ir_print_compile_log(irp, (IrInstSrcCompileLog *)instruction);
2782 case Stage1ZirInstIdCompileLog:
2783 ir_print_compile_log(irp, (Stage1ZirInstCompileLog *)instruction);
27842784 break;
2785 case IrInstSrcIdErrName:
2786 ir_print_err_name(irp, (IrInstSrcErrName *)instruction);
2785 case Stage1ZirInstIdErrName:
2786 ir_print_err_name(irp, (Stage1ZirInstErrName *)instruction);
27872787 break;
2788 case IrInstSrcIdCImport:
2789 ir_print_c_import(irp, (IrInstSrcCImport *)instruction);
2788 case Stage1ZirInstIdCImport:
2789 ir_print_c_import(irp, (Stage1ZirInstCImport *)instruction);
27902790 break;
2791 case IrInstSrcIdCInclude:
2792 ir_print_c_include(irp, (IrInstSrcCInclude *)instruction);
2791 case Stage1ZirInstIdCInclude:
2792 ir_print_c_include(irp, (Stage1ZirInstCInclude *)instruction);
27932793 break;
2794 case IrInstSrcIdCDefine:
2795 ir_print_c_define(irp, (IrInstSrcCDefine *)instruction);
2794 case Stage1ZirInstIdCDefine:
2795 ir_print_c_define(irp, (Stage1ZirInstCDefine *)instruction);
27962796 break;
2797 case IrInstSrcIdCUndef:
2798 ir_print_c_undef(irp, (IrInstSrcCUndef *)instruction);
2797 case Stage1ZirInstIdCUndef:
2798 ir_print_c_undef(irp, (Stage1ZirInstCUndef *)instruction);
27992799 break;
2800 case IrInstSrcIdEmbedFile:
2801 ir_print_embed_file(irp, (IrInstSrcEmbedFile *)instruction);
2800 case Stage1ZirInstIdEmbedFile:
2801 ir_print_embed_file(irp, (Stage1ZirInstEmbedFile *)instruction);
28022802 break;
2803 case IrInstSrcIdCmpxchg:
2804 ir_print_cmpxchg_src(irp, (IrInstSrcCmpxchg *)instruction);
2803 case Stage1ZirInstIdCmpxchg:
2804 ir_print_cmpxchg_src(irp, (Stage1ZirInstCmpxchg *)instruction);
28052805 break;
2806 case IrInstSrcIdFence:
2807 ir_print_fence(irp, (IrInstSrcFence *)instruction);
2806 case Stage1ZirInstIdFence:
2807 ir_print_fence(irp, (Stage1ZirInstFence *)instruction);
28082808 break;
2809 case IrInstSrcIdReduce:
2810 ir_print_reduce(irp, (IrInstSrcReduce *)instruction);
2809 case Stage1ZirInstIdReduce:
2810 ir_print_reduce(irp, (Stage1ZirInstReduce *)instruction);
28112811 break;
2812 case IrInstSrcIdTruncate:
2813 ir_print_truncate(irp, (IrInstSrcTruncate *)instruction);
2812 case Stage1ZirInstIdTruncate:
2813 ir_print_truncate(irp, (Stage1ZirInstTruncate *)instruction);
28142814 break;
2815 case IrInstSrcIdIntCast:
2816 ir_print_int_cast(irp, (IrInstSrcIntCast *)instruction);
2815 case Stage1ZirInstIdIntCast:
2816 ir_print_int_cast(irp, (Stage1ZirInstIntCast *)instruction);
28172817 break;
2818 case IrInstSrcIdFloatCast:
2819 ir_print_float_cast(irp, (IrInstSrcFloatCast *)instruction);
2818 case Stage1ZirInstIdFloatCast:
2819 ir_print_float_cast(irp, (Stage1ZirInstFloatCast *)instruction);
28202820 break;
2821 case IrInstSrcIdErrSetCast:
2822 ir_print_err_set_cast(irp, (IrInstSrcErrSetCast *)instruction);
2821 case Stage1ZirInstIdErrSetCast:
2822 ir_print_err_set_cast(irp, (Stage1ZirInstErrSetCast *)instruction);
28232823 break;
2824 case IrInstSrcIdIntToFloat:
2825 ir_print_int_to_float(irp, (IrInstSrcIntToFloat *)instruction);
2824 case Stage1ZirInstIdIntToFloat:
2825 ir_print_int_to_float(irp, (Stage1ZirInstIntToFloat *)instruction);
28262826 break;
2827 case IrInstSrcIdFloatToInt:
2828 ir_print_float_to_int(irp, (IrInstSrcFloatToInt *)instruction);
2827 case Stage1ZirInstIdFloatToInt:
2828 ir_print_float_to_int(irp, (Stage1ZirInstFloatToInt *)instruction);
28292829 break;
2830 case IrInstSrcIdBoolToInt:
2831 ir_print_bool_to_int(irp, (IrInstSrcBoolToInt *)instruction);
2830 case Stage1ZirInstIdBoolToInt:
2831 ir_print_bool_to_int(irp, (Stage1ZirInstBoolToInt *)instruction);
28322832 break;
2833 case IrInstSrcIdVectorType:
2834 ir_print_vector_type(irp, (IrInstSrcVectorType *)instruction);
2833 case Stage1ZirInstIdVectorType:
2834 ir_print_vector_type(irp, (Stage1ZirInstVectorType *)instruction);
28352835 break;
2836 case IrInstSrcIdShuffleVector:
2837 ir_print_shuffle_vector(irp, (IrInstSrcShuffleVector *)instruction);
2836 case Stage1ZirInstIdShuffleVector:
2837 ir_print_shuffle_vector(irp, (Stage1ZirInstShuffleVector *)instruction);
28382838 break;
2839 case IrInstSrcIdSplat:
2840 ir_print_splat_src(irp, (IrInstSrcSplat *)instruction);
2839 case Stage1ZirInstIdSplat:
2840 ir_print_splat_src(irp, (Stage1ZirInstSplat *)instruction);
28412841 break;
2842 case IrInstSrcIdBoolNot:
2843 ir_print_bool_not(irp, (IrInstSrcBoolNot *)instruction);
2842 case Stage1ZirInstIdBoolNot:
2843 ir_print_bool_not(irp, (Stage1ZirInstBoolNot *)instruction);
28442844 break;
2845 case IrInstSrcIdMemset:
2846 ir_print_memset(irp, (IrInstSrcMemset *)instruction);
2845 case Stage1ZirInstIdMemset:
2846 ir_print_memset(irp, (Stage1ZirInstMemset *)instruction);
28472847 break;
2848 case IrInstSrcIdMemcpy:
2849 ir_print_memcpy(irp, (IrInstSrcMemcpy *)instruction);
2848 case Stage1ZirInstIdMemcpy:
2849 ir_print_memcpy(irp, (Stage1ZirInstMemcpy *)instruction);
28502850 break;
2851 case IrInstSrcIdSlice:
2852 ir_print_slice_src(irp, (IrInstSrcSlice *)instruction);
2851 case Stage1ZirInstIdSlice:
2852 ir_print_slice_src(irp, (Stage1ZirInstSlice *)instruction);
28532853 break;
2854 case IrInstSrcIdBreakpoint:
2855 ir_print_breakpoint(irp, (IrInstSrcBreakpoint *)instruction);
2854 case Stage1ZirInstIdBreakpoint:
2855 ir_print_breakpoint(irp, (Stage1ZirInstBreakpoint *)instruction);
28562856 break;
2857 case IrInstSrcIdReturnAddress:
2858 ir_print_return_address(irp, (IrInstSrcReturnAddress *)instruction);
2857 case Stage1ZirInstIdReturnAddress:
2858 ir_print_return_address(irp, (Stage1ZirInstReturnAddress *)instruction);
28592859 break;
2860 case IrInstSrcIdFrameAddress:
2861 ir_print_frame_address(irp, (IrInstSrcFrameAddress *)instruction);
2860 case Stage1ZirInstIdFrameAddress:
2861 ir_print_frame_address(irp, (Stage1ZirInstFrameAddress *)instruction);
28622862 break;
2863 case IrInstSrcIdFrameHandle:
2864 ir_print_handle(irp, (IrInstSrcFrameHandle *)instruction);
2863 case Stage1ZirInstIdFrameHandle:
2864 ir_print_handle(irp, (Stage1ZirInstFrameHandle *)instruction);
28652865 break;
2866 case IrInstSrcIdFrameType:
2867 ir_print_frame_type(irp, (IrInstSrcFrameType *)instruction);
2866 case Stage1ZirInstIdFrameType:
2867 ir_print_frame_type(irp, (Stage1ZirInstFrameType *)instruction);
28682868 break;
2869 case IrInstSrcIdFrameSize:
2870 ir_print_frame_size_src(irp, (IrInstSrcFrameSize *)instruction);
2869 case Stage1ZirInstIdFrameSize:
2870 ir_print_frame_size_src(irp, (Stage1ZirInstFrameSize *)instruction);
28712871 break;
2872 case IrInstSrcIdAlignOf:
2873 ir_print_align_of(irp, (IrInstSrcAlignOf *)instruction);
2872 case Stage1ZirInstIdAlignOf:
2873 ir_print_align_of(irp, (Stage1ZirInstAlignOf *)instruction);
28742874 break;
2875 case IrInstSrcIdOverflowOp:
2876 ir_print_overflow_op(irp, (IrInstSrcOverflowOp *)instruction);
2875 case Stage1ZirInstIdOverflowOp:
2876 ir_print_overflow_op(irp, (Stage1ZirInstOverflowOp *)instruction);
28772877 break;
2878 case IrInstSrcIdTestErr:
2879 ir_print_test_err_src(irp, (IrInstSrcTestErr *)instruction);
2878 case Stage1ZirInstIdTestErr:
2879 ir_print_test_err_src(irp, (Stage1ZirInstTestErr *)instruction);
28802880 break;
2881 case IrInstSrcIdUnwrapErrCode:
2882 ir_print_unwrap_err_code(irp, (IrInstSrcUnwrapErrCode *)instruction);
2881 case Stage1ZirInstIdUnwrapErrCode:
2882 ir_print_unwrap_err_code(irp, (Stage1ZirInstUnwrapErrCode *)instruction);
28832883 break;
2884 case IrInstSrcIdUnwrapErrPayload:
2885 ir_print_unwrap_err_payload(irp, (IrInstSrcUnwrapErrPayload *)instruction);
2884 case Stage1ZirInstIdUnwrapErrPayload:
2885 ir_print_unwrap_err_payload(irp, (Stage1ZirInstUnwrapErrPayload *)instruction);
28862886 break;
2887 case IrInstSrcIdFnProto:
2888 ir_print_fn_proto(irp, (IrInstSrcFnProto *)instruction);
2887 case Stage1ZirInstIdFnProto:
2888 ir_print_fn_proto(irp, (Stage1ZirInstFnProto *)instruction);
28892889 break;
2890 case IrInstSrcIdTestComptime:
2891 ir_print_test_comptime(irp, (IrInstSrcTestComptime *)instruction);
2890 case Stage1ZirInstIdTestComptime:
2891 ir_print_test_comptime(irp, (Stage1ZirInstTestComptime *)instruction);
28922892 break;
2893 case IrInstSrcIdPtrCast:
2894 ir_print_ptr_cast_src(irp, (IrInstSrcPtrCast *)instruction);
2893 case Stage1ZirInstIdPtrCast:
2894 ir_print_ptr_cast_src(irp, (Stage1ZirInstPtrCast *)instruction);
28952895 break;
2896 case IrInstSrcIdBitCast:
2897 ir_print_bit_cast_src(irp, (IrInstSrcBitCast *)instruction);
2896 case Stage1ZirInstIdBitCast:
2897 ir_print_bit_cast_src(irp, (Stage1ZirInstBitCast *)instruction);
28982898 break;
2899 case IrInstSrcIdPtrToInt:
2900 ir_print_ptr_to_int(irp, (IrInstSrcPtrToInt *)instruction);
2899 case Stage1ZirInstIdPtrToInt:
2900 ir_print_ptr_to_int(irp, (Stage1ZirInstPtrToInt *)instruction);
29012901 break;
2902 case IrInstSrcIdIntToPtr:
2903 ir_print_int_to_ptr(irp, (IrInstSrcIntToPtr *)instruction);
2902 case Stage1ZirInstIdIntToPtr:
2903 ir_print_int_to_ptr(irp, (Stage1ZirInstIntToPtr *)instruction);
29042904 break;
2905 case IrInstSrcIdIntToEnum:
2906 ir_print_int_to_enum(irp, (IrInstSrcIntToEnum *)instruction);
2905 case Stage1ZirInstIdIntToEnum:
2906 ir_print_int_to_enum(irp, (Stage1ZirInstIntToEnum *)instruction);
29072907 break;
2908 case IrInstSrcIdIntToErr:
2909 ir_print_int_to_err(irp, (IrInstSrcIntToErr *)instruction);
2908 case Stage1ZirInstIdIntToErr:
2909 ir_print_int_to_err(irp, (Stage1ZirInstIntToErr *)instruction);
29102910 break;
2911 case IrInstSrcIdErrToInt:
2912 ir_print_err_to_int(irp, (IrInstSrcErrToInt *)instruction);
2911 case Stage1ZirInstIdErrToInt:
2912 ir_print_err_to_int(irp, (Stage1ZirInstErrToInt *)instruction);
29132913 break;
2914 case IrInstSrcIdCheckSwitchProngsUnderNo:
2915 ir_print_check_switch_prongs(irp, (IrInstSrcCheckSwitchProngs *)instruction, false);
2914 case Stage1ZirInstIdCheckSwitchProngsUnderNo:
2915 ir_print_check_switch_prongs(irp, (Stage1ZirInstCheckSwitchProngs *)instruction, false);
29162916 break;
2917 case IrInstSrcIdCheckSwitchProngsUnderYes:
2918 ir_print_check_switch_prongs(irp, (IrInstSrcCheckSwitchProngs *)instruction, true);
2917 case Stage1ZirInstIdCheckSwitchProngsUnderYes:
2918 ir_print_check_switch_prongs(irp, (Stage1ZirInstCheckSwitchProngs *)instruction, true);
29192919 break;
2920 case IrInstSrcIdCheckStatementIsVoid:
2921 ir_print_check_statement_is_void(irp, (IrInstSrcCheckStatementIsVoid *)instruction);
2920 case Stage1ZirInstIdCheckStatementIsVoid:
2921 ir_print_check_statement_is_void(irp, (Stage1ZirInstCheckStatementIsVoid *)instruction);
29222922 break;
2923 case IrInstSrcIdTypeName:
2924 ir_print_type_name(irp, (IrInstSrcTypeName *)instruction);
2923 case Stage1ZirInstIdTypeName:
2924 ir_print_type_name(irp, (Stage1ZirInstTypeName *)instruction);
29252925 break;
2926 case IrInstSrcIdTagName:
2927 ir_print_tag_name(irp, (IrInstSrcTagName *)instruction);
2926 case Stage1ZirInstIdTagName:
2927 ir_print_tag_name(irp, (Stage1ZirInstTagName *)instruction);
29282928 break;
2929 case IrInstSrcIdPtrType:
2930 ir_print_ptr_type(irp, (IrInstSrcPtrType *)instruction);
2929 case Stage1ZirInstIdPtrType:
2930 ir_print_ptr_type(irp, (Stage1ZirInstPtrType *)instruction);
29312931 break;
2932 case IrInstSrcIdPtrTypeSimple:
2933 ir_print_ptr_type_simple(irp, (IrInstSrcPtrTypeSimple *)instruction, false);
2932 case Stage1ZirInstIdPtrTypeSimple:
2933 ir_print_ptr_type_simple(irp, (Stage1ZirInstPtrTypeSimple *)instruction, false);
29342934 break;
2935 case IrInstSrcIdPtrTypeSimpleConst:
2936 ir_print_ptr_type_simple(irp, (IrInstSrcPtrTypeSimple *)instruction, true);
2935 case Stage1ZirInstIdPtrTypeSimpleConst:
2936 ir_print_ptr_type_simple(irp, (Stage1ZirInstPtrTypeSimple *)instruction, true);
29372937 break;
2938 case IrInstSrcIdDeclRef:
2939 ir_print_decl_ref(irp, (IrInstSrcDeclRef *)instruction);
2938 case Stage1ZirInstIdDeclRef:
2939 ir_print_decl_ref(irp, (Stage1ZirInstDeclRef *)instruction);
29402940 break;
2941 case IrInstSrcIdPanic:
2942 ir_print_panic(irp, (IrInstSrcPanic *)instruction);
2941 case Stage1ZirInstIdPanic:
2942 ir_print_panic(irp, (Stage1ZirInstPanic *)instruction);
29432943 break;
2944 case IrInstSrcIdFieldParentPtr:
2945 ir_print_field_parent_ptr(irp, (IrInstSrcFieldParentPtr *)instruction);
2944 case Stage1ZirInstIdFieldParentPtr:
2945 ir_print_field_parent_ptr(irp, (Stage1ZirInstFieldParentPtr *)instruction);
29462946 break;
2947 case IrInstSrcIdOffsetOf:
2948 ir_print_offset_of(irp, (IrInstSrcOffsetOf *)instruction);
2947 case Stage1ZirInstIdOffsetOf:
2948 ir_print_offset_of(irp, (Stage1ZirInstOffsetOf *)instruction);
29492949 break;
2950 case IrInstSrcIdBitOffsetOf:
2951 ir_print_bit_offset_of(irp, (IrInstSrcBitOffsetOf *)instruction);
2950 case Stage1ZirInstIdBitOffsetOf:
2951 ir_print_bit_offset_of(irp, (Stage1ZirInstBitOffsetOf *)instruction);
29522952 break;
2953 case IrInstSrcIdTypeInfo:
2954 ir_print_type_info(irp, (IrInstSrcTypeInfo *)instruction);
2953 case Stage1ZirInstIdTypeInfo:
2954 ir_print_type_info(irp, (Stage1ZirInstTypeInfo *)instruction);
29552955 break;
2956 case IrInstSrcIdType:
2957 ir_print_type(irp, (IrInstSrcType *)instruction);
2956 case Stage1ZirInstIdType:
2957 ir_print_type(irp, (Stage1ZirInstType *)instruction);
29582958 break;
2959 case IrInstSrcIdHasField:
2960 ir_print_has_field(irp, (IrInstSrcHasField *)instruction);
2959 case Stage1ZirInstIdHasField:
2960 ir_print_has_field(irp, (Stage1ZirInstHasField *)instruction);
29612961 break;
2962 case IrInstSrcIdSetEvalBranchQuota:
2963 ir_print_set_eval_branch_quota(irp, (IrInstSrcSetEvalBranchQuota *)instruction);
2962 case Stage1ZirInstIdSetEvalBranchQuota:
2963 ir_print_set_eval_branch_quota(irp, (Stage1ZirInstSetEvalBranchQuota *)instruction);
29642964 break;
2965 case IrInstSrcIdAlignCast:
2966 ir_print_align_cast(irp, (IrInstSrcAlignCast *)instruction);
2965 case Stage1ZirInstIdAlignCast:
2966 ir_print_align_cast(irp, (Stage1ZirInstAlignCast *)instruction);
29672967 break;
2968 case IrInstSrcIdImplicitCast:
2969 ir_print_implicit_cast(irp, (IrInstSrcImplicitCast *)instruction);
2968 case Stage1ZirInstIdImplicitCast:
2969 ir_print_implicit_cast(irp, (Stage1ZirInstImplicitCast *)instruction);
29702970 break;
2971 case IrInstSrcIdResolveResult:
2972 ir_print_resolve_result(irp, (IrInstSrcResolveResult *)instruction);
2971 case Stage1ZirInstIdResolveResult:
2972 ir_print_resolve_result(irp, (Stage1ZirInstResolveResult *)instruction);
29732973 break;
2974 case IrInstSrcIdResetResult:
2975 ir_print_reset_result(irp, (IrInstSrcResetResult *)instruction);
2974 case Stage1ZirInstIdResetResult:
2975 ir_print_reset_result(irp, (Stage1ZirInstResetResult *)instruction);
29762976 break;
2977 case IrInstSrcIdSetAlignStack:
2978 ir_print_set_align_stack(irp, (IrInstSrcSetAlignStack *)instruction);
2977 case Stage1ZirInstIdSetAlignStack:
2978 ir_print_set_align_stack(irp, (Stage1ZirInstSetAlignStack *)instruction);
29792979 break;
2980 case IrInstSrcIdArgTypeAllowVarFalse:
2981 ir_print_arg_type(irp, (IrInstSrcArgType *)instruction, false);
2980 case Stage1ZirInstIdArgTypeAllowVarFalse:
2981 ir_print_arg_type(irp, (Stage1ZirInstArgType *)instruction, false);
29822982 break;
2983 case IrInstSrcIdArgTypeAllowVarTrue:
2984 ir_print_arg_type(irp, (IrInstSrcArgType *)instruction, true);
2983 case Stage1ZirInstIdArgTypeAllowVarTrue:
2984 ir_print_arg_type(irp, (Stage1ZirInstArgType *)instruction, true);
29852985 break;
2986 case IrInstSrcIdExport:
2987 ir_print_export(irp, (IrInstSrcExport *)instruction);
2986 case Stage1ZirInstIdExport:
2987 ir_print_export(irp, (Stage1ZirInstExport *)instruction);
29882988 break;
2989 case IrInstSrcIdExtern:
2990 ir_print_extern(irp, (IrInstSrcExtern*)instruction);
2989 case Stage1ZirInstIdExtern:
2990 ir_print_extern(irp, (Stage1ZirInstExtern*)instruction);
29912991 break;
2992 case IrInstSrcIdErrorReturnTrace:
2993 ir_print_error_return_trace(irp, (IrInstSrcErrorReturnTrace *)instruction);
2992 case Stage1ZirInstIdErrorReturnTrace:
2993 ir_print_error_return_trace(irp, (Stage1ZirInstErrorReturnTrace *)instruction);
29942994 break;
2995 case IrInstSrcIdErrorUnion:
2996 ir_print_error_union(irp, (IrInstSrcErrorUnion *)instruction);
2995 case Stage1ZirInstIdErrorUnion:
2996 ir_print_error_union(irp, (Stage1ZirInstErrorUnion *)instruction);
29972997 break;
2998 case IrInstSrcIdAtomicRmw:
2999 ir_print_atomic_rmw(irp, (IrInstSrcAtomicRmw *)instruction);
2998 case Stage1ZirInstIdAtomicRmw:
2999 ir_print_atomic_rmw(irp, (Stage1ZirInstAtomicRmw *)instruction);
30003000 break;
3001 case IrInstSrcIdSaveErrRetAddr:
3002 ir_print_save_err_ret_addr(irp, (IrInstSrcSaveErrRetAddr *)instruction);
3001 case Stage1ZirInstIdSaveErrRetAddr:
3002 ir_print_save_err_ret_addr(irp, (Stage1ZirInstSaveErrRetAddr *)instruction);
30033003 break;
3004 case IrInstSrcIdAddImplicitReturnType:
3005 ir_print_add_implicit_return_type(irp, (IrInstSrcAddImplicitReturnType *)instruction);
3004 case Stage1ZirInstIdAddImplicitReturnType:
3005 ir_print_add_implicit_return_type(irp, (Stage1ZirInstAddImplicitReturnType *)instruction);
30063006 break;
3007 case IrInstSrcIdFloatOp:
3008 ir_print_float_op(irp, (IrInstSrcFloatOp *)instruction);
3007 case Stage1ZirInstIdFloatOp:
3008 ir_print_float_op(irp, (Stage1ZirInstFloatOp *)instruction);
30093009 break;
3010 case IrInstSrcIdMulAdd:
3011 ir_print_mul_add(irp, (IrInstSrcMulAdd *)instruction);
3010 case Stage1ZirInstIdMulAdd:
3011 ir_print_mul_add(irp, (Stage1ZirInstMulAdd *)instruction);
30123012 break;
3013 case IrInstSrcIdAtomicLoad:
3014 ir_print_atomic_load(irp, (IrInstSrcAtomicLoad *)instruction);
3013 case Stage1ZirInstIdAtomicLoad:
3014 ir_print_atomic_load(irp, (Stage1ZirInstAtomicLoad *)instruction);
30153015 break;
3016 case IrInstSrcIdAtomicStore:
3017 ir_print_atomic_store(irp, (IrInstSrcAtomicStore *)instruction);
3016 case Stage1ZirInstIdAtomicStore:
3017 ir_print_atomic_store(irp, (Stage1ZirInstAtomicStore *)instruction);
30183018 break;
3019 case IrInstSrcIdEnumToInt:
3020 ir_print_enum_to_int(irp, (IrInstSrcEnumToInt *)instruction);
3019 case Stage1ZirInstIdEnumToInt:
3020 ir_print_enum_to_int(irp, (Stage1ZirInstEnumToInt *)instruction);
30213021 break;
3022 case IrInstSrcIdCheckRuntimeScope:
3023 ir_print_check_runtime_scope(irp, (IrInstSrcCheckRuntimeScope *)instruction);
3022 case Stage1ZirInstIdCheckRuntimeScope:
3023 ir_print_check_runtime_scope(irp, (Stage1ZirInstCheckRuntimeScope *)instruction);
30243024 break;
3025 case IrInstSrcIdHasDecl:
3026 ir_print_has_decl(irp, (IrInstSrcHasDecl *)instruction);
3025 case Stage1ZirInstIdHasDecl:
3026 ir_print_has_decl(irp, (Stage1ZirInstHasDecl *)instruction);
30273027 break;
3028 case IrInstSrcIdUndeclaredIdent:
3029 ir_print_undeclared_ident(irp, (IrInstSrcUndeclaredIdent *)instruction);
3028 case Stage1ZirInstIdUndeclaredIdent:
3029 ir_print_undeclared_ident(irp, (Stage1ZirInstUndeclaredIdent *)instruction);
30303030 break;
3031 case IrInstSrcIdAlloca:
3032 ir_print_alloca_src(irp, (IrInstSrcAlloca *)instruction);
3031 case Stage1ZirInstIdAlloca:
3032 ir_print_alloca_src(irp, (Stage1ZirInstAlloca *)instruction);
30333033 break;
3034 case IrInstSrcIdEndExpr:
3035 ir_print_end_expr(irp, (IrInstSrcEndExpr *)instruction);
3034 case Stage1ZirInstIdEndExpr:
3035 ir_print_end_expr(irp, (Stage1ZirInstEndExpr *)instruction);
30363036 break;
3037 case IrInstSrcIdUnionInitNamedField:
3038 ir_print_union_init_named_field(irp, (IrInstSrcUnionInitNamedField *)instruction);
3037 case Stage1ZirInstIdUnionInitNamedField:
3038 ir_print_union_init_named_field(irp, (Stage1ZirInstUnionInitNamedField *)instruction);
30393039 break;
3040 case IrInstSrcIdSuspendBegin:
3041 ir_print_suspend_begin(irp, (IrInstSrcSuspendBegin *)instruction);
3040 case Stage1ZirInstIdSuspendBegin:
3041 ir_print_suspend_begin(irp, (Stage1ZirInstSuspendBegin *)instruction);
30423042 break;
3043 case IrInstSrcIdSuspendFinish:
3044 ir_print_suspend_finish(irp, (IrInstSrcSuspendFinish *)instruction);
3043 case Stage1ZirInstIdSuspendFinish:
3044 ir_print_suspend_finish(irp, (Stage1ZirInstSuspendFinish *)instruction);
30453045 break;
3046 case IrInstSrcIdResume:
3047 ir_print_resume(irp, (IrInstSrcResume *)instruction);
3046 case Stage1ZirInstIdResume:
3047 ir_print_resume(irp, (Stage1ZirInstResume *)instruction);
30483048 break;
3049 case IrInstSrcIdAwait:
3050 ir_print_await_src(irp, (IrInstSrcAwait *)instruction);
3049 case Stage1ZirInstIdAwait:
3050 ir_print_await_src(irp, (Stage1ZirInstAwait *)instruction);
30513051 break;
3052 case IrInstSrcIdSpillBegin:
3053 ir_print_spill_begin(irp, (IrInstSrcSpillBegin *)instruction);
3052 case Stage1ZirInstIdSpillBegin:
3053 ir_print_spill_begin(irp, (Stage1ZirInstSpillBegin *)instruction);
30543054 break;
3055 case IrInstSrcIdSpillEnd:
3056 ir_print_spill_end(irp, (IrInstSrcSpillEnd *)instruction);
3055 case Stage1ZirInstIdSpillEnd:
3056 ir_print_spill_end(irp, (Stage1ZirInstSpillEnd *)instruction);
30573057 break;
3058 case IrInstSrcIdClz:
3059 ir_print_clz(irp, (IrInstSrcClz *)instruction);
3058 case Stage1ZirInstIdClz:
3059 ir_print_clz(irp, (Stage1ZirInstClz *)instruction);
30603060 break;
3061 case IrInstSrcIdWasmMemorySize:
3062 ir_print_wasm_memory_size(irp, (IrInstSrcWasmMemorySize *)instruction);
3061 case Stage1ZirInstIdWasmMemorySize:
3062 ir_print_wasm_memory_size(irp, (Stage1ZirInstWasmMemorySize *)instruction);
30633063 break;
3064 case IrInstSrcIdWasmMemoryGrow:
3065 ir_print_wasm_memory_grow(irp, (IrInstSrcWasmMemoryGrow *)instruction);
3064 case Stage1ZirInstIdWasmMemoryGrow:
3065 ir_print_wasm_memory_grow(irp, (Stage1ZirInstWasmMemoryGrow *)instruction);
30663066 break;
3067 case IrInstSrcIdSrc:
3068 ir_print_builtin_src(irp, (IrInstSrcSrc *)instruction);
3067 case Stage1ZirInstIdSrc:
3068 ir_print_builtin_src(irp, (Stage1ZirInstSrc *)instruction);
30693069 break;
30703070 }
30713071 fprintf(irp->f, "\n");
30723072}
30733073
3074static void ir_print_inst_gen(IrPrintGen *irp, IrInstGen *instruction, bool trailing) {
3074static void ir_print_inst_gen(IrPrintGen *irp, Stage1AirInst *instruction, bool trailing) {
30753075 ir_print_prefix_gen(irp, instruction, trailing);
30763076 switch (instruction->id) {
3077 case IrInstGenIdInvalid:
3077 case Stage1AirInstIdInvalid:
30783078 zig_unreachable();
3079 case IrInstGenIdReturn:
3080 ir_print_return_gen(irp, (IrInstGenReturn *)instruction);
3079 case Stage1AirInstIdReturn:
3080 ir_print_return_gen(irp, (Stage1AirInstReturn *)instruction);
30813081 break;
3082 case IrInstGenIdConst:
3083 ir_print_const(irp, (IrInstGenConst *)instruction);
3082 case Stage1AirInstIdConst:
3083 ir_print_const(irp, (Stage1AirInstConst *)instruction);
30843084 break;
3085 case IrInstGenIdBinOp:
3086 ir_print_bin_op(irp, (IrInstGenBinOp *)instruction);
3085 case Stage1AirInstIdBinOp:
3086 ir_print_bin_op(irp, (Stage1AirInstBinOp *)instruction);
30873087 break;
3088 case IrInstGenIdDeclVar:
3089 ir_print_decl_var_gen(irp, (IrInstGenDeclVar *)instruction);
3088 case Stage1AirInstIdDeclVar:
3089 ir_print_decl_var_gen(irp, (Stage1AirInstDeclVar *)instruction);
30903090 break;
3091 case IrInstGenIdCast:
3092 ir_print_cast(irp, (IrInstGenCast *)instruction);
3091 case Stage1AirInstIdCast:
3092 ir_print_cast(irp, (Stage1AirInstCast *)instruction);
30933093 break;
3094 case IrInstGenIdCall:
3095 ir_print_call_gen(irp, (IrInstGenCall *)instruction);
3094 case Stage1AirInstIdCall:
3095 ir_print_call_gen(irp, (Stage1AirInstCall *)instruction);
30963096 break;
3097 case IrInstGenIdCondBr:
3098 ir_print_cond_br(irp, (IrInstGenCondBr *)instruction);
3097 case Stage1AirInstIdCondBr:
3098 ir_print_cond_br(irp, (Stage1AirInstCondBr *)instruction);
30993099 break;
3100 case IrInstGenIdBr:
3101 ir_print_br(irp, (IrInstGenBr *)instruction);
3100 case Stage1AirInstIdBr:
3101 ir_print_br(irp, (Stage1AirInstBr *)instruction);
31023102 break;
3103 case IrInstGenIdPhi:
3104 ir_print_phi(irp, (IrInstGenPhi *)instruction);
3103 case Stage1AirInstIdPhi:
3104 ir_print_phi(irp, (Stage1AirInstPhi *)instruction);
31053105 break;
3106 case IrInstGenIdUnreachable:
3107 ir_print_unreachable(irp, (IrInstGenUnreachable *)instruction);
3106 case Stage1AirInstIdUnreachable:
3107 ir_print_unreachable(irp, (Stage1AirInstUnreachable *)instruction);
31083108 break;
3109 case IrInstGenIdElemPtr:
3110 ir_print_elem_ptr(irp, (IrInstGenElemPtr *)instruction);
3109 case Stage1AirInstIdElemPtr:
3110 ir_print_elem_ptr(irp, (Stage1AirInstElemPtr *)instruction);
31113111 break;
3112 case IrInstGenIdVarPtr:
3113 ir_print_var_ptr(irp, (IrInstGenVarPtr *)instruction);
3112 case Stage1AirInstIdVarPtr:
3113 ir_print_var_ptr(irp, (Stage1AirInstVarPtr *)instruction);
31143114 break;
3115 case IrInstGenIdReturnPtr:
3116 ir_print_return_ptr(irp, (IrInstGenReturnPtr *)instruction);
3115 case Stage1AirInstIdReturnPtr:
3116 ir_print_return_ptr(irp, (Stage1AirInstReturnPtr *)instruction);
31173117 break;
3118 case IrInstGenIdLoadPtr:
3119 ir_print_load_ptr_gen(irp, (IrInstGenLoadPtr *)instruction);
3118 case Stage1AirInstIdLoadPtr:
3119 ir_print_load_ptr_gen(irp, (Stage1AirInstLoadPtr *)instruction);
31203120 break;
3121 case IrInstGenIdStorePtr:
3122 ir_print_store_ptr(irp, (IrInstGenStorePtr *)instruction);
3121 case Stage1AirInstIdStorePtr:
3122 ir_print_store_ptr(irp, (Stage1AirInstStorePtr *)instruction);
31233123 break;
3124 case IrInstGenIdStructFieldPtr:
3125 ir_print_struct_field_ptr(irp, (IrInstGenStructFieldPtr *)instruction);
3124 case Stage1AirInstIdStructFieldPtr:
3125 ir_print_struct_field_ptr(irp, (Stage1AirInstStructFieldPtr *)instruction);
31263126 break;
3127 case IrInstGenIdUnionFieldPtr:
3128 ir_print_union_field_ptr(irp, (IrInstGenUnionFieldPtr *)instruction);
3127 case Stage1AirInstIdUnionFieldPtr:
3128 ir_print_union_field_ptr(irp, (Stage1AirInstUnionFieldPtr *)instruction);
31293129 break;
3130 case IrInstGenIdAsm:
3131 ir_print_asm_gen(irp, (IrInstGenAsm *)instruction);
3130 case Stage1AirInstIdAsm:
3131 ir_print_asm_gen(irp, (Stage1AirInstAsm *)instruction);
31323132 break;
3133 case IrInstGenIdTestNonNull:
3134 ir_print_test_non_null(irp, (IrInstGenTestNonNull *)instruction);
3133 case Stage1AirInstIdTestNonNull:
3134 ir_print_test_non_null(irp, (Stage1AirInstTestNonNull *)instruction);
31353135 break;
3136 case IrInstGenIdOptionalUnwrapPtr:
3137 ir_print_optional_unwrap_ptr(irp, (IrInstGenOptionalUnwrapPtr *)instruction);
3136 case Stage1AirInstIdOptionalUnwrapPtr:
3137 ir_print_optional_unwrap_ptr(irp, (Stage1AirInstOptionalUnwrapPtr *)instruction);
31383138 break;
3139 case IrInstGenIdPopCount:
3140 ir_print_pop_count(irp, (IrInstGenPopCount *)instruction);
3139 case Stage1AirInstIdPopCount:
3140 ir_print_pop_count(irp, (Stage1AirInstPopCount *)instruction);
31413141 break;
3142 case IrInstGenIdClz:
3143 ir_print_clz(irp, (IrInstGenClz *)instruction);
3142 case Stage1AirInstIdClz:
3143 ir_print_clz(irp, (Stage1AirInstClz *)instruction);
31443144 break;
3145 case IrInstGenIdCtz:
3146 ir_print_ctz(irp, (IrInstGenCtz *)instruction);
3145 case Stage1AirInstIdCtz:
3146 ir_print_ctz(irp, (Stage1AirInstCtz *)instruction);
31473147 break;
3148 case IrInstGenIdBswap:
3149 ir_print_bswap(irp, (IrInstGenBswap *)instruction);
3148 case Stage1AirInstIdBswap:
3149 ir_print_bswap(irp, (Stage1AirInstBswap *)instruction);
31503150 break;
3151 case IrInstGenIdBitReverse:
3152 ir_print_bit_reverse(irp, (IrInstGenBitReverse *)instruction);
3151 case Stage1AirInstIdBitReverse:
3152 ir_print_bit_reverse(irp, (Stage1AirInstBitReverse *)instruction);
31533153 break;
3154 case IrInstGenIdSwitchBr:
3155 ir_print_switch_br(irp, (IrInstGenSwitchBr *)instruction);
3154 case Stage1AirInstIdSwitchBr:
3155 ir_print_switch_br(irp, (Stage1AirInstSwitchBr *)instruction);
31563156 break;
3157 case IrInstGenIdUnionTag:
3158 ir_print_union_tag(irp, (IrInstGenUnionTag *)instruction);
3157 case Stage1AirInstIdUnionTag:
3158 ir_print_union_tag(irp, (Stage1AirInstUnionTag *)instruction);
31593159 break;
3160 case IrInstGenIdRef:
3161 ir_print_ref_gen(irp, (IrInstGenRef *)instruction);
3160 case Stage1AirInstIdRef:
3161 ir_print_ref_gen(irp, (Stage1AirInstRef *)instruction);
31623162 break;
3163 case IrInstGenIdErrName:
3164 ir_print_err_name(irp, (IrInstGenErrName *)instruction);
3163 case Stage1AirInstIdErrName:
3164 ir_print_err_name(irp, (Stage1AirInstErrName *)instruction);
31653165 break;
3166 case IrInstGenIdCmpxchg:
3167 ir_print_cmpxchg_gen(irp, (IrInstGenCmpxchg *)instruction);
3166 case Stage1AirInstIdCmpxchg:
3167 ir_print_cmpxchg_gen(irp, (Stage1AirInstCmpxchg *)instruction);
31683168 break;
3169 case IrInstGenIdFence:
3170 ir_print_fence(irp, (IrInstGenFence *)instruction);
3169 case Stage1AirInstIdFence:
3170 ir_print_fence(irp, (Stage1AirInstFence *)instruction);
31713171 break;
3172 case IrInstGenIdReduce:
3173 ir_print_reduce(irp, (IrInstGenReduce *)instruction);
3172 case Stage1AirInstIdReduce:
3173 ir_print_reduce(irp, (Stage1AirInstReduce *)instruction);
31743174 break;
3175 case IrInstGenIdTruncate:
3176 ir_print_truncate(irp, (IrInstGenTruncate *)instruction);
3175 case Stage1AirInstIdTruncate:
3176 ir_print_truncate(irp, (Stage1AirInstTruncate *)instruction);
31773177 break;
3178 case IrInstGenIdShuffleVector:
3179 ir_print_shuffle_vector(irp, (IrInstGenShuffleVector *)instruction);
3178 case Stage1AirInstIdShuffleVector:
3179 ir_print_shuffle_vector(irp, (Stage1AirInstShuffleVector *)instruction);
31803180 break;
3181 case IrInstGenIdSplat:
3182 ir_print_splat_gen(irp, (IrInstGenSplat *)instruction);
3181 case Stage1AirInstIdSplat:
3182 ir_print_splat_gen(irp, (Stage1AirInstSplat *)instruction);
31833183 break;
3184 case IrInstGenIdBoolNot:
3185 ir_print_bool_not(irp, (IrInstGenBoolNot *)instruction);
3184 case Stage1AirInstIdBoolNot:
3185 ir_print_bool_not(irp, (Stage1AirInstBoolNot *)instruction);
31863186 break;
3187 case IrInstGenIdMemset:
3188 ir_print_memset(irp, (IrInstGenMemset *)instruction);
3187 case Stage1AirInstIdMemset:
3188 ir_print_memset(irp, (Stage1AirInstMemset *)instruction);
31893189 break;
3190 case IrInstGenIdMemcpy:
3191 ir_print_memcpy(irp, (IrInstGenMemcpy *)instruction);
3190 case Stage1AirInstIdMemcpy:
3191 ir_print_memcpy(irp, (Stage1AirInstMemcpy *)instruction);
31923192 break;
3193 case IrInstGenIdSlice:
3194 ir_print_slice_gen(irp, (IrInstGenSlice *)instruction);
3193 case Stage1AirInstIdSlice:
3194 ir_print_slice_gen(irp, (Stage1AirInstSlice *)instruction);
31953195 break;
3196 case IrInstGenIdBreakpoint:
3197 ir_print_breakpoint(irp, (IrInstGenBreakpoint *)instruction);
3196 case Stage1AirInstIdBreakpoint:
3197 ir_print_breakpoint(irp, (Stage1AirInstBreakpoint *)instruction);
31983198 break;
3199 case IrInstGenIdReturnAddress:
3200 ir_print_return_address(irp, (IrInstGenReturnAddress *)instruction);
3199 case Stage1AirInstIdReturnAddress:
3200 ir_print_return_address(irp, (Stage1AirInstReturnAddress *)instruction);
32013201 break;
3202 case IrInstGenIdFrameAddress:
3203 ir_print_frame_address(irp, (IrInstGenFrameAddress *)instruction);
3202 case Stage1AirInstIdFrameAddress:
3203 ir_print_frame_address(irp, (Stage1AirInstFrameAddress *)instruction);
32043204 break;
3205 case IrInstGenIdFrameHandle:
3206 ir_print_handle(irp, (IrInstGenFrameHandle *)instruction);
3205 case Stage1AirInstIdFrameHandle:
3206 ir_print_handle(irp, (Stage1AirInstFrameHandle *)instruction);
32073207 break;
3208 case IrInstGenIdFrameSize:
3209 ir_print_frame_size_gen(irp, (IrInstGenFrameSize *)instruction);
3208 case Stage1AirInstIdFrameSize:
3209 ir_print_frame_size_gen(irp, (Stage1AirInstFrameSize *)instruction);
32103210 break;
3211 case IrInstGenIdOverflowOp:
3212 ir_print_overflow_op(irp, (IrInstGenOverflowOp *)instruction);
3211 case Stage1AirInstIdOverflowOp:
3212 ir_print_overflow_op(irp, (Stage1AirInstOverflowOp *)instruction);
32133213 break;
3214 case IrInstGenIdTestErr:
3215 ir_print_test_err_gen(irp, (IrInstGenTestErr *)instruction);
3214 case Stage1AirInstIdTestErr:
3215 ir_print_test_err_gen(irp, (Stage1AirInstTestErr *)instruction);
32163216 break;
3217 case IrInstGenIdUnwrapErrCode:
3218 ir_print_unwrap_err_code(irp, (IrInstGenUnwrapErrCode *)instruction);
3217 case Stage1AirInstIdUnwrapErrCode:
3218 ir_print_unwrap_err_code(irp, (Stage1AirInstUnwrapErrCode *)instruction);
32193219 break;
3220 case IrInstGenIdUnwrapErrPayload:
3221 ir_print_unwrap_err_payload(irp, (IrInstGenUnwrapErrPayload *)instruction);
3220 case Stage1AirInstIdUnwrapErrPayload:
3221 ir_print_unwrap_err_payload(irp, (Stage1AirInstUnwrapErrPayload *)instruction);
32223222 break;
3223 case IrInstGenIdOptionalWrap:
3224 ir_print_optional_wrap(irp, (IrInstGenOptionalWrap *)instruction);
3223 case Stage1AirInstIdOptionalWrap:
3224 ir_print_optional_wrap(irp, (Stage1AirInstOptionalWrap *)instruction);
32253225 break;
3226 case IrInstGenIdErrWrapCode:
3227 ir_print_err_wrap_code(irp, (IrInstGenErrWrapCode *)instruction);
3226 case Stage1AirInstIdErrWrapCode:
3227 ir_print_err_wrap_code(irp, (Stage1AirInstErrWrapCode *)instruction);
32283228 break;
3229 case IrInstGenIdErrWrapPayload:
3230 ir_print_err_wrap_payload(irp, (IrInstGenErrWrapPayload *)instruction);
3229 case Stage1AirInstIdErrWrapPayload:
3230 ir_print_err_wrap_payload(irp, (Stage1AirInstErrWrapPayload *)instruction);
32313231 break;
3232 case IrInstGenIdPtrCast:
3233 ir_print_ptr_cast_gen(irp, (IrInstGenPtrCast *)instruction);
3232 case Stage1AirInstIdPtrCast:
3233 ir_print_ptr_cast_gen(irp, (Stage1AirInstPtrCast *)instruction);
32343234 break;
3235 case IrInstGenIdBitCast:
3236 ir_print_bit_cast_gen(irp, (IrInstGenBitCast *)instruction);
3235 case Stage1AirInstIdBitCast:
3236 ir_print_bit_cast_gen(irp, (Stage1AirInstBitCast *)instruction);
32373237 break;
3238 case IrInstGenIdWidenOrShorten:
3239 ir_print_widen_or_shorten(irp, (IrInstGenWidenOrShorten *)instruction);
3238 case Stage1AirInstIdWidenOrShorten:
3239 ir_print_widen_or_shorten(irp, (Stage1AirInstWidenOrShorten *)instruction);
32403240 break;
3241 case IrInstGenIdPtrToInt:
3242 ir_print_ptr_to_int(irp, (IrInstGenPtrToInt *)instruction);
3241 case Stage1AirInstIdPtrToInt:
3242 ir_print_ptr_to_int(irp, (Stage1AirInstPtrToInt *)instruction);
32433243 break;
3244 case IrInstGenIdIntToPtr:
3245 ir_print_int_to_ptr(irp, (IrInstGenIntToPtr *)instruction);
3244 case Stage1AirInstIdIntToPtr:
3245 ir_print_int_to_ptr(irp, (Stage1AirInstIntToPtr *)instruction);
32463246 break;
3247 case IrInstGenIdIntToEnum:
3248 ir_print_int_to_enum(irp, (IrInstGenIntToEnum *)instruction);
3247 case Stage1AirInstIdIntToEnum:
3248 ir_print_int_to_enum(irp, (Stage1AirInstIntToEnum *)instruction);
32493249 break;
3250 case IrInstGenIdIntToErr:
3251 ir_print_int_to_err(irp, (IrInstGenIntToErr *)instruction);
3250 case Stage1AirInstIdIntToErr:
3251 ir_print_int_to_err(irp, (Stage1AirInstIntToErr *)instruction);
32523252 break;
3253 case IrInstGenIdErrToInt:
3254 ir_print_err_to_int(irp, (IrInstGenErrToInt *)instruction);
3253 case Stage1AirInstIdErrToInt:
3254 ir_print_err_to_int(irp, (Stage1AirInstErrToInt *)instruction);
32553255 break;
3256 case IrInstGenIdTagName:
3257 ir_print_tag_name(irp, (IrInstGenTagName *)instruction);
3256 case Stage1AirInstIdTagName:
3257 ir_print_tag_name(irp, (Stage1AirInstTagName *)instruction);
32583258 break;
3259 case IrInstGenIdPanic:
3260 ir_print_panic(irp, (IrInstGenPanic *)instruction);
3259 case Stage1AirInstIdPanic:
3260 ir_print_panic(irp, (Stage1AirInstPanic *)instruction);
32613261 break;
3262 case IrInstGenIdFieldParentPtr:
3263 ir_print_field_parent_ptr(irp, (IrInstGenFieldParentPtr *)instruction);
3262 case Stage1AirInstIdFieldParentPtr:
3263 ir_print_field_parent_ptr(irp, (Stage1AirInstFieldParentPtr *)instruction);
32643264 break;
3265 case IrInstGenIdAlignCast:
3266 ir_print_align_cast(irp, (IrInstGenAlignCast *)instruction);
3265 case Stage1AirInstIdAlignCast:
3266 ir_print_align_cast(irp, (Stage1AirInstAlignCast *)instruction);
32673267 break;
3268 case IrInstGenIdErrorReturnTrace:
3269 ir_print_error_return_trace(irp, (IrInstGenErrorReturnTrace *)instruction);
3268 case Stage1AirInstIdErrorReturnTrace:
3269 ir_print_error_return_trace(irp, (Stage1AirInstErrorReturnTrace *)instruction);
32703270 break;
3271 case IrInstGenIdAtomicRmw:
3272 ir_print_atomic_rmw(irp, (IrInstGenAtomicRmw *)instruction);
3271 case Stage1AirInstIdAtomicRmw:
3272 ir_print_atomic_rmw(irp, (Stage1AirInstAtomicRmw *)instruction);
32733273 break;
3274 case IrInstGenIdSaveErrRetAddr:
3275 ir_print_save_err_ret_addr(irp, (IrInstGenSaveErrRetAddr *)instruction);
3274 case Stage1AirInstIdSaveErrRetAddr:
3275 ir_print_save_err_ret_addr(irp, (Stage1AirInstSaveErrRetAddr *)instruction);
32763276 break;
3277 case IrInstGenIdFloatOp:
3278 ir_print_float_op(irp, (IrInstGenFloatOp *)instruction);
3277 case Stage1AirInstIdFloatOp:
3278 ir_print_float_op(irp, (Stage1AirInstFloatOp *)instruction);
32793279 break;
3280 case IrInstGenIdMulAdd:
3281 ir_print_mul_add(irp, (IrInstGenMulAdd *)instruction);
3280 case Stage1AirInstIdMulAdd:
3281 ir_print_mul_add(irp, (Stage1AirInstMulAdd *)instruction);
32823282 break;
3283 case IrInstGenIdAtomicLoad:
3284 ir_print_atomic_load(irp, (IrInstGenAtomicLoad *)instruction);
3283 case Stage1AirInstIdAtomicLoad:
3284 ir_print_atomic_load(irp, (Stage1AirInstAtomicLoad *)instruction);
32853285 break;
3286 case IrInstGenIdAtomicStore:
3287 ir_print_atomic_store(irp, (IrInstGenAtomicStore *)instruction);
3286 case Stage1AirInstIdAtomicStore:
3287 ir_print_atomic_store(irp, (Stage1AirInstAtomicStore *)instruction);
32883288 break;
3289 case IrInstGenIdArrayToVector:
3290 ir_print_array_to_vector(irp, (IrInstGenArrayToVector *)instruction);
3289 case Stage1AirInstIdArrayToVector:
3290 ir_print_array_to_vector(irp, (Stage1AirInstArrayToVector *)instruction);
32913291 break;
3292 case IrInstGenIdVectorToArray:
3293 ir_print_vector_to_array(irp, (IrInstGenVectorToArray *)instruction);
3292 case Stage1AirInstIdVectorToArray:
3293 ir_print_vector_to_array(irp, (Stage1AirInstVectorToArray *)instruction);
32943294 break;
3295 case IrInstGenIdPtrOfArrayToSlice:
3296 ir_print_ptr_of_array_to_slice(irp, (IrInstGenPtrOfArrayToSlice *)instruction);
3295 case Stage1AirInstIdPtrOfArrayToSlice:
3296 ir_print_ptr_of_array_to_slice(irp, (Stage1AirInstPtrOfArrayToSlice *)instruction);
32973297 break;
3298 case IrInstGenIdAssertZero:
3299 ir_print_assert_zero(irp, (IrInstGenAssertZero *)instruction);
3298 case Stage1AirInstIdAssertZero:
3299 ir_print_assert_zero(irp, (Stage1AirInstAssertZero *)instruction);
33003300 break;
3301 case IrInstGenIdAssertNonNull:
3302 ir_print_assert_non_null(irp, (IrInstGenAssertNonNull *)instruction);
3301 case Stage1AirInstIdAssertNonNull:
3302 ir_print_assert_non_null(irp, (Stage1AirInstAssertNonNull *)instruction);
33033303 break;
3304 case IrInstGenIdAlloca:
3305 ir_print_alloca_gen(irp, (IrInstGenAlloca *)instruction);
3304 case Stage1AirInstIdAlloca:
3305 ir_print_alloca_gen(irp, (Stage1AirInstAlloca *)instruction);
33063306 break;
3307 case IrInstGenIdSuspendBegin:
3308 ir_print_suspend_begin(irp, (IrInstGenSuspendBegin *)instruction);
3307 case Stage1AirInstIdSuspendBegin:
3308 ir_print_suspend_begin(irp, (Stage1AirInstSuspendBegin *)instruction);
33093309 break;
3310 case IrInstGenIdSuspendFinish:
3311 ir_print_suspend_finish(irp, (IrInstGenSuspendFinish *)instruction);
3310 case Stage1AirInstIdSuspendFinish:
3311 ir_print_suspend_finish(irp, (Stage1AirInstSuspendFinish *)instruction);
33123312 break;
3313 case IrInstGenIdResume:
3314 ir_print_resume(irp, (IrInstGenResume *)instruction);
3313 case Stage1AirInstIdResume:
3314 ir_print_resume(irp, (Stage1AirInstResume *)instruction);
33153315 break;
3316 case IrInstGenIdAwait:
3317 ir_print_await_gen(irp, (IrInstGenAwait *)instruction);
3316 case Stage1AirInstIdAwait:
3317 ir_print_await_gen(irp, (Stage1AirInstAwait *)instruction);
33183318 break;
3319 case IrInstGenIdSpillBegin:
3320 ir_print_spill_begin(irp, (IrInstGenSpillBegin *)instruction);
3319 case Stage1AirInstIdSpillBegin:
3320 ir_print_spill_begin(irp, (Stage1AirInstSpillBegin *)instruction);
33213321 break;
3322 case IrInstGenIdSpillEnd:
3323 ir_print_spill_end(irp, (IrInstGenSpillEnd *)instruction);
3322 case Stage1AirInstIdSpillEnd:
3323 ir_print_spill_end(irp, (Stage1AirInstSpillEnd *)instruction);
33243324 break;
3325 case IrInstGenIdVectorExtractElem:
3326 ir_print_vector_extract_elem(irp, (IrInstGenVectorExtractElem *)instruction);
3325 case Stage1AirInstIdVectorExtractElem:
3326 ir_print_vector_extract_elem(irp, (Stage1AirInstVectorExtractElem *)instruction);
33273327 break;
3328 case IrInstGenIdVectorStoreElem:
3329 ir_print_vector_store_elem(irp, (IrInstGenVectorStoreElem *)instruction);
3328 case Stage1AirInstIdVectorStoreElem:
3329 ir_print_vector_store_elem(irp, (Stage1AirInstVectorStoreElem *)instruction);
33303330 break;
3331 case IrInstGenIdBinaryNot:
3332 ir_print_binary_not(irp, (IrInstGenBinaryNot *)instruction);
3331 case Stage1AirInstIdBinaryNot:
3332 ir_print_binary_not(irp, (Stage1AirInstBinaryNot *)instruction);
33333333 break;
3334 case IrInstGenIdNegation:
3335 ir_print_negation(irp, (IrInstGenNegation *)instruction);
3334 case Stage1AirInstIdNegation:
3335 ir_print_negation(irp, (Stage1AirInstNegation *)instruction);
33363336 break;
3337 case IrInstGenIdWasmMemorySize:
3338 ir_print_wasm_memory_size(irp, (IrInstGenWasmMemorySize *)instruction);
3337 case Stage1AirInstIdWasmMemorySize:
3338 ir_print_wasm_memory_size(irp, (Stage1AirInstWasmMemorySize *)instruction);
33393339 break;
3340 case IrInstGenIdWasmMemoryGrow:
3341 ir_print_wasm_memory_grow(irp, (IrInstGenWasmMemoryGrow *)instruction);
3340 case Stage1AirInstIdWasmMemoryGrow:
3341 ir_print_wasm_memory_grow(irp, (Stage1AirInstWasmMemoryGrow *)instruction);
33423342 break;
3343 case IrInstGenIdExtern:
3344 ir_print_extern(irp, (IrInstGenExtern *)instruction);
3343 case Stage1AirInstIdExtern:
3344 ir_print_extern(irp, (Stage1AirInstExtern *)instruction);
33453345 break;
33463346
33473347 }
......@@ -3351,15 +3351,15 @@ static void ir_print_inst_gen(IrPrintGen *irp, IrInstGen *instruction, bool trai
33513351static void irp_print_basic_block_src(IrPrintSrc *irp, Stage1ZirBasicBlock *current_block) {
33523352 fprintf(irp->f, "%s_%" PRIu32 ":\n", current_block->name_hint, current_block->debug_id);
33533353 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {
3354 IrInstSrc *instruction = current_block->instruction_list.at(instr_i);
3354 Stage1ZirInst *instruction = current_block->instruction_list.at(instr_i);
33553355 ir_print_inst_src(irp, instruction, false);
33563356 }
33573357}
33583358
3359static void irp_print_basic_block_gen(IrPrintGen *irp, IrBasicBlockGen *current_block) {
3359static void irp_print_basic_block_gen(IrPrintGen *irp, Stage1AirBasicBlock *current_block) {
33603360 fprintf(irp->f, "%s_%" PRIu32 ":\n", current_block->name_hint, current_block->debug_id);
33613361 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {
3362 IrInstGen *instruction = current_block->instruction_list.at(instr_i);
3362 Stage1AirInst *instruction = current_block->instruction_list.at(instr_i);
33633363 irp->printed.put(instruction, 0);
33643364 irp->pending.clear();
33653365 ir_print_inst_gen(irp, instruction, false);
......@@ -3378,7 +3378,7 @@ void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb
33783378 irp_print_basic_block_src(&ir_print, bb);
33793379}
33803380
3381void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, IrBasicBlockGen *bb, int indent_size) {
3381void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, Stage1AirBasicBlock *bb, int indent_size) {
33823382 IrPrintGen ir_print = {};
33833383 ir_print.codegen = codegen;
33843384 ir_print.f = f;
......@@ -3426,7 +3426,7 @@ void ir_print_gen(CodeGen *codegen, FILE *f, Stage1Air *executable, int indent_s
34263426 irp->printed.deinit();
34273427}
34283428
3429void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *instruction, int indent_size) {
3429void ir_print_inst_src(CodeGen *codegen, FILE *f, Stage1ZirInst *instruction, int indent_size) {
34303430 IrPrintSrc ir_print = {};
34313431 IrPrintSrc *irp = &ir_print;
34323432 irp->codegen = codegen;
......@@ -3437,7 +3437,7 @@ void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *instruction, int in
34373437 ir_print_inst_src(irp, instruction, false);
34383438}
34393439
3440void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *instruction, int indent_size) {
3440void ir_print_inst_gen(CodeGen *codegen, FILE *f, Stage1AirInst *instruction, int indent_size) {
34413441 IrPrintGen ir_print = {};
34423442 IrPrintGen *irp = &ir_print;
34433443 irp->codegen = codegen;
......@@ -3451,8 +3451,8 @@ void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *instruction, int in
34513451 ir_print_inst_gen(irp, instruction, false);
34523452}
34533453
3454void IrInstSrc::dump() {
3455 IrInstSrc *inst = this;
3454void Stage1ZirInst::dump() {
3455 Stage1ZirInst *inst = this;
34563456 inst->src();
34573457 if (inst->scope == nullptr) {
34583458 fprintf(stderr, "(null scope)\n");
src/stage1/ir_print.hpp+5-5
......@@ -14,12 +14,12 @@
1414
1515void ir_print_src(CodeGen *codegen, FILE *f, Stage1Zir *executable, int indent_size);
1616void ir_print_gen(CodeGen *codegen, FILE *f, Stage1Air *executable, int indent_size);
17void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *inst, int indent_size);
18void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *inst, int indent_size);
17void ir_print_inst_src(CodeGen *codegen, FILE *f, Stage1ZirInst *inst, int indent_size);
18void ir_print_inst_gen(CodeGen *codegen, FILE *f, Stage1AirInst *inst, int indent_size);
1919void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb, int indent_size);
20void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, IrBasicBlockGen *bb, int indent_size);
20void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, Stage1AirBasicBlock *bb, int indent_size);
2121
22const char* ir_inst_src_type_str(IrInstSrcId id);
23const char* ir_inst_gen_type_str(IrInstGenId id);
22const char* ir_inst_src_type_str(Stage1ZirInstId id);
23const char* ir_inst_gen_type_str(Stage1AirInstId id);
2424
2525#endif