authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-08-15 23:09:55-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-08-15 23:09:55-07:00
log7adf15682ca263c7d4e0e5306517f22272310294
tree7e9846e9389d883fa4035f9abdfd5e331968e635
parentd6467dcf71c40d4f09993f8c449b33adeca55ce5

update target CPU features with LLVM 13 rc1 data

13 files changed, 720 insertions(+), 80 deletions(-)

lib/std/target.zig+1
...@@ -430,6 +430,7 @@ pub const Target = struct {...@@ -430,6 +430,7 @@ pub const Target = struct {
430 };430 };
431431
432 pub const aarch64 = @import("target/aarch64.zig");432 pub const aarch64 = @import("target/aarch64.zig");
433 pub const arc = @import("target/arc.zig");
433 pub const amdgpu = @import("target/amdgpu.zig");434 pub const amdgpu = @import("target/amdgpu.zig");
434 pub const arm = @import("target/arm.zig");435 pub const arm = @import("target/arm.zig");
435 pub const avr = @import("target/avr.zig");436 pub const avr = @import("target/avr.zig");
lib/std/target/aarch64.zig+107-19
...@@ -65,6 +65,7 @@ pub const Feature = enum {...@@ -65,6 +65,7 @@ pub const Feature = enum {
65 fuse_csel,65 fuse_csel,
66 fuse_literals,66 fuse_literals,
67 harden_sls_blr,67 harden_sls_blr,
68 harden_sls_nocomdat,
68 harden_sls_retbr,69 harden_sls_retbr,
69 hcx,70 hcx,
70 i8mm,71 i8mm,
...@@ -81,6 +82,7 @@ pub const Feature = enum {...@@ -81,6 +82,7 @@ pub const Feature = enum {
81 neoverse_n2,82 neoverse_n2,
82 neoverse_v1,83 neoverse_v1,
83 no_neg_immediates,84 no_neg_immediates,
85 no_zcz_fp,
84 nv,86 nv,
85 outline_atomics,87 outline_atomics,
86 pan,88 pan,
...@@ -120,6 +122,7 @@ pub const Feature = enum {...@@ -120,6 +122,7 @@ pub const Feature = enum {
120 reserve_x6,122 reserve_x6,
121 reserve_x7,123 reserve_x7,
122 reserve_x9,124 reserve_x9,
125 rme,
123 sb,126 sb,
124 sel2,127 sel2,
125 sha2,128 sha2,
...@@ -128,6 +131,9 @@ pub const Feature = enum {...@@ -128,6 +131,9 @@ pub const Feature = enum {
128 slow_paired_128,131 slow_paired_128,
129 slow_strqro_store,132 slow_strqro_store,
130 sm4,133 sm4,
134 sme,
135 sme_f64,
136 sme_i64,
131 spe,137 spe,
132 spe_eef,138 spe_eef,
133 specrestrict,139 specrestrict,
...@@ -148,7 +154,6 @@ pub const Feature = enum {...@@ -148,7 +154,6 @@ pub const Feature = enum {
148 tracev8_4,154 tracev8_4,
149 trbe,155 trbe,
150 uaops,156 uaops,
151 use_aa,
152 use_experimental_zeroing_pseudos,157 use_experimental_zeroing_pseudos,
153 use_postra_scheduler,158 use_postra_scheduler,
154 use_reciprocal_square_root,159 use_reciprocal_square_root,
...@@ -166,7 +171,6 @@ pub const Feature = enum {...@@ -166,7 +171,6 @@ pub const Feature = enum {
166 xs,171 xs,
167 zcm,172 zcm,
168 zcz,173 zcz,
169 zcz_fp,
170 zcz_fp_workaround,174 zcz_fp_workaround,
171 zcz_gp,175 zcz_gp,
172};176};
...@@ -594,6 +598,11 @@ pub const all_features = blk: {...@@ -594,6 +598,11 @@ pub const all_features = blk: {
594 .description = "Harden against straight line speculation across BLR instructions",598 .description = "Harden against straight line speculation across BLR instructions",
595 .dependencies = featureSet(&[_]Feature{}),599 .dependencies = featureSet(&[_]Feature{}),
596 };600 };
601 result[@enumToInt(Feature.harden_sls_nocomdat)] = .{
602 .llvm_name = "harden-sls-nocomdat",
603 .description = "Generate thunk code for SLS mitigation in the normal text section",
604 .dependencies = featureSet(&[_]Feature{}),
605 };
597 result[@enumToInt(Feature.harden_sls_retbr)] = .{606 result[@enumToInt(Feature.harden_sls_retbr)] = .{
598 .llvm_name = "harden-sls-retbr",607 .llvm_name = "harden-sls-retbr",
599 .description = "Harden against straight line speculation across RET and BR instructions",608 .description = "Harden against straight line speculation across RET and BR instructions",
...@@ -660,8 +669,10 @@ pub const all_features = blk: {...@@ -660,8 +669,10 @@ pub const all_features = blk: {
660 .crypto,669 .crypto,
661 .dotprod,670 .dotprod,
662 .fullfp16,671 .fullfp16,
672 .fuse_aes,
663 .rcpc,673 .rcpc,
664 .ssbs,674 .ssbs,
675 .use_postra_scheduler,
665 .v8_2a,676 .v8_2a,
666 }),677 }),
667 };678 };
...@@ -672,9 +683,11 @@ pub const all_features = blk: {...@@ -672,9 +683,11 @@ pub const all_features = blk: {
672 .crypto,683 .crypto,
673 .dotprod,684 .dotprod,
674 .fullfp16,685 .fullfp16,
686 .fuse_aes,
675 .rcpc,687 .rcpc,
676 .spe,688 .spe,
677 .ssbs,689 .ssbs,
690 .use_postra_scheduler,
678 .v8_2a,691 .v8_2a,
679 }),692 }),
680 };693 };
...@@ -683,10 +696,13 @@ pub const all_features = blk: {...@@ -683,10 +696,13 @@ pub const all_features = blk: {
683 .description = "Neoverse N2 ARM processors",696 .description = "Neoverse N2 ARM processors",
684 .dependencies = featureSet(&[_]Feature{697 .dependencies = featureSet(&[_]Feature{
685 .bf16,698 .bf16,
699 .crypto,
686 .ete,700 .ete,
701 .fuse_aes,
687 .i8mm,702 .i8mm,
688 .mte,703 .mte,
689 .sve2_bitperm,704 .sve2_bitperm,
705 .use_postra_scheduler,
690 .v8_5a,706 .v8_5a,
691 }),707 }),
692 };708 };
...@@ -714,6 +730,11 @@ pub const all_features = blk: {...@@ -714,6 +730,11 @@ pub const all_features = blk: {
714 .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",730 .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
715 .dependencies = featureSet(&[_]Feature{}),731 .dependencies = featureSet(&[_]Feature{}),
716 };732 };
733 result[@enumToInt(Feature.no_zcz_fp)] = .{
734 .llvm_name = "no-zcz-fp",
735 .description = "Has no zero-cycle zeroing instructions for FP registers",
736 .dependencies = featureSet(&[_]Feature{}),
737 };
717 result[@enumToInt(Feature.nv)] = .{738 result[@enumToInt(Feature.nv)] = .{
718 .llvm_name = "nv",739 .llvm_name = "nv",
719 .description = "Enable v8.4-A Nested Virtualization Enchancement",740 .description = "Enable v8.4-A Nested Virtualization Enchancement",
...@@ -913,6 +934,11 @@ pub const all_features = blk: {...@@ -913,6 +934,11 @@ pub const all_features = blk: {
913 .description = "Reserve X9, making it unavailable as a GPR",934 .description = "Reserve X9, making it unavailable as a GPR",
914 .dependencies = featureSet(&[_]Feature{}),935 .dependencies = featureSet(&[_]Feature{}),
915 };936 };
937 result[@enumToInt(Feature.rme)] = .{
938 .llvm_name = "rme",
939 .description = "Enable Realm Management Extension",
940 .dependencies = featureSet(&[_]Feature{}),
941 };
916 result[@enumToInt(Feature.sb)] = .{942 result[@enumToInt(Feature.sb)] = .{
917 .llvm_name = "sb",943 .llvm_name = "sb",
918 .description = "Enable v8.5 Speculation Barrier",944 .description = "Enable v8.5 Speculation Barrier",
...@@ -959,6 +985,28 @@ pub const all_features = blk: {...@@ -959,6 +985,28 @@ pub const all_features = blk: {
959 .neon,985 .neon,
960 }),986 }),
961 };987 };
988 result[@enumToInt(Feature.sme)] = .{
989 .llvm_name = "sme",
990 .description = "Enable Scalable Matrix Extension (SME)",
991 .dependencies = featureSet(&[_]Feature{
992 .bf16,
993 .sve2,
994 }),
995 };
996 result[@enumToInt(Feature.sme_f64)] = .{
997 .llvm_name = "sme-f64",
998 .description = "Enable Scalable Matrix Extension (SME) F64F64 instructions",
999 .dependencies = featureSet(&[_]Feature{
1000 .sme,
1001 }),
1002 };
1003 result[@enumToInt(Feature.sme_i64)] = .{
1004 .llvm_name = "sme-i64",
1005 .description = "Enable Scalable Matrix Extension (SME) I16I64 instructions",
1006 .dependencies = featureSet(&[_]Feature{
1007 .sme,
1008 }),
1009 };
962 result[@enumToInt(Feature.spe)] = .{1010 result[@enumToInt(Feature.spe)] = .{
963 .llvm_name = "spe",1011 .llvm_name = "spe",
964 .description = "Enable Statistical Profiling extension",1012 .description = "Enable Statistical Profiling extension",
...@@ -1074,11 +1122,6 @@ pub const all_features = blk: {...@@ -1074,11 +1122,6 @@ pub const all_features = blk: {
1074 .description = "Enable v8.2 UAO PState",1122 .description = "Enable v8.2 UAO PState",
1075 .dependencies = featureSet(&[_]Feature{}),1123 .dependencies = featureSet(&[_]Feature{}),
1076 };1124 };
1077 result[@enumToInt(Feature.use_aa)] = .{
1078 .llvm_name = "use-aa",
1079 .description = "Use alias analysis during codegen",
1080 .dependencies = featureSet(&[_]Feature{}),
1081 };
1082 result[@enumToInt(Feature.use_experimental_zeroing_pseudos)] = .{1125 result[@enumToInt(Feature.use_experimental_zeroing_pseudos)] = .{
1083 .llvm_name = "use-experimental-zeroing-pseudos",1126 .llvm_name = "use-experimental-zeroing-pseudos",
1084 .description = "Hint to the compiler that the MOVPRFX instruction is merged with destructive operations",1127 .description = "Hint to the compiler that the MOVPRFX instruction is merged with destructive operations",
...@@ -1251,15 +1294,9 @@ pub const all_features = blk: {...@@ -1251,15 +1294,9 @@ pub const all_features = blk: {
1251 .llvm_name = "zcz",1294 .llvm_name = "zcz",
1252 .description = "Has zero-cycle zeroing instructions",1295 .description = "Has zero-cycle zeroing instructions",
1253 .dependencies = featureSet(&[_]Feature{1296 .dependencies = featureSet(&[_]Feature{
1254 .zcz_fp,
1255 .zcz_gp,1297 .zcz_gp,
1256 }),1298 }),
1257 };1299 };
1258 result[@enumToInt(Feature.zcz_fp)] = .{
1259 .llvm_name = "zcz-fp",
1260 .description = "Has zero-cycle zeroing instructions for FP registers",
1261 .dependencies = featureSet(&[_]Feature{}),
1262 };
1263 result[@enumToInt(Feature.zcz_fp_workaround)] = .{1300 result[@enumToInt(Feature.zcz_fp_workaround)] = .{
1264 .llvm_name = "zcz-fp-workaround",1301 .llvm_name = "zcz-fp-workaround",
1265 .description = "The zero-cycle floating-point zeroing instruction has a bug",1302 .description = "The zero-cycle floating-point zeroing instruction has a bug",
...@@ -1403,7 +1440,62 @@ pub const cpu = struct {...@@ -1403,7 +1440,62 @@ pub const cpu = struct {
1403 .name = "apple_latest",1440 .name = "apple_latest",
1404 .llvm_name = "apple-latest",1441 .llvm_name = "apple-latest",
1405 .features = featureSet(&[_]Feature{1442 .features = featureSet(&[_]Feature{
1406 .apple_a13,1443 .aggressive_fma,
1444 .alternate_sextload_cvt_f32_pattern,
1445 .altnzcv,
1446 .arith_bcc_fusion,
1447 .arith_cbz_fusion,
1448 .ccdp,
1449 .crypto,
1450 .disable_latency_sched_heuristic,
1451 .fp16fml,
1452 .fptoint,
1453 .fuse_address,
1454 .fuse_aes,
1455 .fuse_arith_logic,
1456 .fuse_crypto_eor,
1457 .fuse_csel,
1458 .fuse_literals,
1459 .perfmon,
1460 .predres,
1461 .sb,
1462 .sha3,
1463 .specrestrict,
1464 .ssbs,
1465 .v8_4a,
1466 .zcm,
1467 .zcz,
1468 }),
1469 };
1470 pub const apple_m1 = CpuModel{
1471 .name = "apple_m1",
1472 .llvm_name = "apple-m1",
1473 .features = featureSet(&[_]Feature{
1474 .aggressive_fma,
1475 .alternate_sextload_cvt_f32_pattern,
1476 .altnzcv,
1477 .arith_bcc_fusion,
1478 .arith_cbz_fusion,
1479 .ccdp,
1480 .crypto,
1481 .disable_latency_sched_heuristic,
1482 .fp16fml,
1483 .fptoint,
1484 .fuse_address,
1485 .fuse_aes,
1486 .fuse_arith_logic,
1487 .fuse_crypto_eor,
1488 .fuse_csel,
1489 .fuse_literals,
1490 .perfmon,
1491 .predres,
1492 .sb,
1493 .sha3,
1494 .specrestrict,
1495 .ssbs,
1496 .v8_4a,
1497 .zcm,
1498 .zcz,
1407 }),1499 }),
1408 };1500 };
1409 pub const apple_s4 = CpuModel{1501 pub const apple_s4 = CpuModel{
...@@ -1459,7 +1551,6 @@ pub const cpu = struct {...@@ -1459,7 +1551,6 @@ pub const cpu = struct {
1459 .custom_cheap_as_move,1551 .custom_cheap_as_move,
1460 .fuse_aes,1552 .fuse_aes,
1461 .perfmon,1553 .perfmon,
1462 .use_aa,
1463 .use_postra_scheduler,1554 .use_postra_scheduler,
1464 .v8a,1555 .v8a,
1465 }),1556 }),
...@@ -1474,6 +1565,7 @@ pub const cpu = struct {...@@ -1474,6 +1565,7 @@ pub const cpu = struct {
1474 .fuse_aes,1565 .fuse_aes,
1475 .perfmon,1566 .perfmon,
1476 .rcpc,1567 .rcpc,
1568 .use_postra_scheduler,
1477 .v8_2a,1569 .v8_2a,
1478 }),1570 }),
1479 };1571 };
...@@ -1649,7 +1741,6 @@ pub const cpu = struct {...@@ -1649,7 +1741,6 @@ pub const cpu = struct {
1649 .use_postra_scheduler,1741 .use_postra_scheduler,
1650 .use_reciprocal_square_root,1742 .use_reciprocal_square_root,
1651 .v8a,1743 .v8a,
1652 .zcz_fp,
1653 }),1744 }),
1654 };1745 };
1655 pub const exynos_m2 = CpuModel{1746 pub const exynos_m2 = CpuModel{
...@@ -1666,7 +1757,6 @@ pub const cpu = struct {...@@ -1666,7 +1757,6 @@ pub const cpu = struct {
1666 .slow_paired_128,1757 .slow_paired_128,
1667 .use_postra_scheduler,1758 .use_postra_scheduler,
1668 .v8a,1759 .v8a,
1669 .zcz_fp,
1670 }),1760 }),
1671 };1761 };
1672 pub const exynos_m3 = CpuModel{1762 pub const exynos_m3 = CpuModel{
...@@ -1686,7 +1776,6 @@ pub const cpu = struct {...@@ -1686,7 +1776,6 @@ pub const cpu = struct {
1686 .predictable_select_expensive,1776 .predictable_select_expensive,
1687 .use_postra_scheduler,1777 .use_postra_scheduler,
1688 .v8a,1778 .v8a,
1689 .zcz_fp,
1690 }),1779 }),
1691 };1780 };
1692 pub const exynos_m4 = CpuModel{1781 pub const exynos_m4 = CpuModel{
...@@ -1824,7 +1913,6 @@ pub const cpu = struct {...@@ -1824,7 +1913,6 @@ pub const cpu = struct {
1824 .perfmon,1913 .perfmon,
1825 .predictable_select_expensive,1914 .predictable_select_expensive,
1826 .strict_align,1915 .strict_align,
1827 .use_aa,
1828 .use_postra_scheduler,1916 .use_postra_scheduler,
1829 .v8_3a,1917 .v8_3a,
1830 }),1918 }),
lib/std/target/amdgpu.zig+255-8
...@@ -9,6 +9,7 @@ pub const Feature = enum {...@@ -9,6 +9,7 @@ pub const Feature = enum {
9 a16,9 a16,
10 add_no_carry_insts,10 add_no_carry_insts,
11 aperture_regs,11 aperture_regs,
12 architected_flat_scratch,
12 atomic_fadd_insts,13 atomic_fadd_insts,
13 auto_waitcnt_before_barrier,14 auto_waitcnt_before_barrier,
14 ci_insts,15 ci_insts,
...@@ -20,11 +21,14 @@ pub const Feature = enum {...@@ -20,11 +21,14 @@ pub const Feature = enum {
20 dot4_insts,21 dot4_insts,
21 dot5_insts,22 dot5_insts,
22 dot6_insts,23 dot6_insts,
24 dot7_insts,
23 dpp,25 dpp,
24 dpp8,26 dpp8,
27 dpp_64bit,
25 ds_src2_insts,28 ds_src2_insts,
26 enable_ds128,29 enable_ds128,
27 enable_prt_strict_null,30 enable_prt_strict_null,
31 extended_image_insts,
28 fast_denormal_f32,32 fast_denormal_f32,
29 fast_fmaf,33 fast_fmaf,
30 flat_address_space,34 flat_address_space,
...@@ -36,16 +40,19 @@ pub const Feature = enum {...@@ -36,16 +40,19 @@ pub const Feature = enum {
36 fma_mix_insts,40 fma_mix_insts,
37 fmaf,41 fmaf,
38 fp64,42 fp64,
43 full_rate_64_ops,
39 g16,44 g16,
40 gcn3_encoding,45 gcn3_encoding,
41 get_wave_id_inst,46 get_wave_id_inst,
42 gfx10,47 gfx10,
43 gfx10_3_insts,48 gfx10_3_insts,
49 gfx10_a_encoding,
44 gfx10_b_encoding,50 gfx10_b_encoding,
45 gfx10_insts,51 gfx10_insts,
46 gfx7_gfx8_gfx9_insts,52 gfx7_gfx8_gfx9_insts,
47 gfx8_insts,53 gfx8_insts,
48 gfx9,54 gfx9,
55 gfx90a_insts,
49 gfx9_insts,56 gfx9_insts,
50 half_rate_64_ops,57 half_rate_64_ops,
51 image_gather4_d16_bug,58 image_gather4_d16_bug,
...@@ -70,11 +77,18 @@ pub const Feature = enum {...@@ -70,11 +77,18 @@ pub const Feature = enum {
70 mfma_inline_literal_bug,77 mfma_inline_literal_bug,
71 mimg_r128,78 mimg_r128,
72 movrel,79 movrel,
80 negative_scratch_offset_bug,
81 negative_unaligned_scratch_offset_bug,
73 no_data_dep_hazard,82 no_data_dep_hazard,
74 no_sdst_cmpx,83 no_sdst_cmpx,
84 nsa_clause_bug,
75 nsa_encoding,85 nsa_encoding,
86 nsa_max_size_13,
87 nsa_max_size_5,
76 nsa_to_vmem_bug,88 nsa_to_vmem_bug,
77 offset_3f_bug,89 offset_3f_bug,
90 packed_fp32_ops,
91 packed_tid,
78 pk_fmac_f16_inst,92 pk_fmac_f16_inst,
79 promote_alloca,93 promote_alloca,
80 r128_a16,94 r128_a16,
...@@ -92,11 +106,13 @@ pub const Feature = enum {...@@ -92,11 +106,13 @@ pub const Feature = enum {
92 sdwa_sdst,106 sdwa_sdst,
93 sea_islands,107 sea_islands,
94 sgpr_init_bug,108 sgpr_init_bug,
109 shader_cycles_register,
95 si_scheduler,110 si_scheduler,
96 smem_to_vector_write_hazard,111 smem_to_vector_write_hazard,
97 southern_islands,112 southern_islands,
98 sramecc,113 sramecc,
99 sramecc_support,114 sramecc_support,
115 tgsplit,
100 trap_handler,116 trap_handler,
101 trig_reduced_range,117 trig_reduced_range,
102 unaligned_access_mode,118 unaligned_access_mode,
...@@ -149,6 +165,11 @@ pub const all_features = blk: {...@@ -149,6 +165,11 @@ pub const all_features = blk: {
149 .description = "Has Memory Aperture Base and Size Registers",165 .description = "Has Memory Aperture Base and Size Registers",
150 .dependencies = featureSet(&[_]Feature{}),166 .dependencies = featureSet(&[_]Feature{}),
151 };167 };
168 result[@enumToInt(Feature.architected_flat_scratch)] = .{
169 .llvm_name = "architected-flat-scratch",
170 .description = "Flat Scratch register is a readonly SPI initialized architected register",
171 .dependencies = featureSet(&[_]Feature{}),
172 };
152 result[@enumToInt(Feature.atomic_fadd_insts)] = .{173 result[@enumToInt(Feature.atomic_fadd_insts)] = .{
153 .llvm_name = "atomic-fadd-insts",174 .llvm_name = "atomic-fadd-insts",
154 .description = "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions",175 .description = "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions",
...@@ -183,7 +204,7 @@ pub const all_features = blk: {...@@ -183,7 +204,7 @@ pub const all_features = blk: {
183 };204 };
184 result[@enumToInt(Feature.dot2_insts)] = .{205 result[@enumToInt(Feature.dot2_insts)] = .{
185 .llvm_name = "dot2-insts",206 .llvm_name = "dot2-insts",
186 .description = "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions",207 .description = "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions",
187 .dependencies = featureSet(&[_]Feature{}),208 .dependencies = featureSet(&[_]Feature{}),
188 };209 };
189 result[@enumToInt(Feature.dot3_insts)] = .{210 result[@enumToInt(Feature.dot3_insts)] = .{
...@@ -206,6 +227,11 @@ pub const all_features = blk: {...@@ -206,6 +227,11 @@ pub const all_features = blk: {
206 .description = "Has v_dot4c_i32_i8 instruction",227 .description = "Has v_dot4c_i32_i8 instruction",
207 .dependencies = featureSet(&[_]Feature{}),228 .dependencies = featureSet(&[_]Feature{}),
208 };229 };
230 result[@enumToInt(Feature.dot7_insts)] = .{
231 .llvm_name = "dot7-insts",
232 .description = "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions",
233 .dependencies = featureSet(&[_]Feature{}),
234 };
209 result[@enumToInt(Feature.dpp)] = .{235 result[@enumToInt(Feature.dpp)] = .{
210 .llvm_name = "dpp",236 .llvm_name = "dpp",
211 .description = "Support DPP (Data Parallel Primitives) extension",237 .description = "Support DPP (Data Parallel Primitives) extension",
...@@ -216,6 +242,11 @@ pub const all_features = blk: {...@@ -216,6 +242,11 @@ pub const all_features = blk: {
216 .description = "Support DPP8 (Data Parallel Primitives) extension",242 .description = "Support DPP8 (Data Parallel Primitives) extension",
217 .dependencies = featureSet(&[_]Feature{}),243 .dependencies = featureSet(&[_]Feature{}),
218 };244 };
245 result[@enumToInt(Feature.dpp_64bit)] = .{
246 .llvm_name = "dpp-64bit",
247 .description = "Support DPP (Data Parallel Primitives) extension",
248 .dependencies = featureSet(&[_]Feature{}),
249 };
219 result[@enumToInt(Feature.ds_src2_insts)] = .{250 result[@enumToInt(Feature.ds_src2_insts)] = .{
220 .llvm_name = "ds-src2-insts",251 .llvm_name = "ds-src2-insts",
221 .description = "Has ds_*_src2 instructions",252 .description = "Has ds_*_src2 instructions",
...@@ -231,6 +262,11 @@ pub const all_features = blk: {...@@ -231,6 +262,11 @@ pub const all_features = blk: {
231 .description = "Enable zeroing of result registers for sparse texture fetches",262 .description = "Enable zeroing of result registers for sparse texture fetches",
232 .dependencies = featureSet(&[_]Feature{}),263 .dependencies = featureSet(&[_]Feature{}),
233 };264 };
265 result[@enumToInt(Feature.extended_image_insts)] = .{
266 .llvm_name = "extended-image-insts",
267 .description = "Support mips != 0, lod != 0, gather4, and get_lod",
268 .dependencies = featureSet(&[_]Feature{}),
269 };
234 result[@enumToInt(Feature.fast_denormal_f32)] = .{270 result[@enumToInt(Feature.fast_denormal_f32)] = .{
235 .llvm_name = "fast-denormal-f32",271 .llvm_name = "fast-denormal-f32",
236 .description = "Enabling denormals does not cause f32 instructions to run at f64 rates",272 .description = "Enabling denormals does not cause f32 instructions to run at f64 rates",
...@@ -268,7 +304,7 @@ pub const all_features = blk: {...@@ -268,7 +304,7 @@ pub const all_features = blk: {
268 };304 };
269 result[@enumToInt(Feature.flat_segment_offset_bug)] = .{305 result[@enumToInt(Feature.flat_segment_offset_bug)] = .{
270 .llvm_name = "flat-segment-offset-bug",306 .llvm_name = "flat-segment-offset-bug",
271 .description = "GFX10 bug, inst_offset ignored in flat segment",307 .description = "GFX10 bug where inst_offset is ignored when flat instructions access global memory",
272 .dependencies = featureSet(&[_]Feature{}),308 .dependencies = featureSet(&[_]Feature{}),
273 };309 };
274 result[@enumToInt(Feature.fma_mix_insts)] = .{310 result[@enumToInt(Feature.fma_mix_insts)] = .{
...@@ -286,6 +322,11 @@ pub const all_features = blk: {...@@ -286,6 +322,11 @@ pub const all_features = blk: {
286 .description = "Enable double precision operations",322 .description = "Enable double precision operations",
287 .dependencies = featureSet(&[_]Feature{}),323 .dependencies = featureSet(&[_]Feature{}),
288 };324 };
325 result[@enumToInt(Feature.full_rate_64_ops)] = .{
326 .llvm_name = "full-rate-64-ops",
327 .description = "Most fp64 instructions are full rate",
328 .dependencies = featureSet(&[_]Feature{}),
329 };
289 result[@enumToInt(Feature.g16)] = .{330 result[@enumToInt(Feature.g16)] = .{
290 .llvm_name = "g16",331 .llvm_name = "g16",
291 .description = "Support G16 for 16-bit gradient image operands",332 .description = "Support G16 for 16-bit gradient image operands",
...@@ -312,6 +353,7 @@ pub const all_features = blk: {...@@ -312,6 +353,7 @@ pub const all_features = blk: {
312 .ci_insts,353 .ci_insts,
313 .dpp,354 .dpp,
314 .dpp8,355 .dpp8,
356 .extended_image_insts,
315 .fast_denormal_f32,357 .fast_denormal_f32,
316 .fast_fmaf,358 .fast_fmaf,
317 .flat_address_space,359 .flat_address_space,
...@@ -334,6 +376,7 @@ pub const all_features = blk: {...@@ -334,6 +376,7 @@ pub const all_features = blk: {
334 .pk_fmac_f16_inst,376 .pk_fmac_f16_inst,
335 .register_banking,377 .register_banking,
336 .s_memrealtime,378 .s_memrealtime,
379 .s_memtime_inst,
337 .sdwa,380 .sdwa,
338 .sdwa_omod,381 .sdwa_omod,
339 .sdwa_scalar,382 .sdwa_scalar,
...@@ -350,6 +393,11 @@ pub const all_features = blk: {...@@ -350,6 +393,11 @@ pub const all_features = blk: {
350 .description = "Additional instructions for GFX10.3",393 .description = "Additional instructions for GFX10.3",
351 .dependencies = featureSet(&[_]Feature{}),394 .dependencies = featureSet(&[_]Feature{}),
352 };395 };
396 result[@enumToInt(Feature.gfx10_a_encoding)] = .{
397 .llvm_name = "gfx10_a-encoding",
398 .description = "Has BVH ray tracing instructions",
399 .dependencies = featureSet(&[_]Feature{}),
400 };
353 result[@enumToInt(Feature.gfx10_b_encoding)] = .{401 result[@enumToInt(Feature.gfx10_b_encoding)] = .{
354 .llvm_name = "gfx10_b-encoding",402 .llvm_name = "gfx10_b-encoding",
355 .description = "Encoding format GFX10_B",403 .description = "Encoding format GFX10_B",
...@@ -379,7 +427,6 @@ pub const all_features = blk: {...@@ -379,7 +427,6 @@ pub const all_features = blk: {
379 .aperture_regs,427 .aperture_regs,
380 .ci_insts,428 .ci_insts,
381 .dpp,429 .dpp,
382 .ds_src2_insts,
383 .fast_denormal_f32,430 .fast_denormal_f32,
384 .fast_fmaf,431 .fast_fmaf,
385 .flat_address_space,432 .flat_address_space,
...@@ -394,7 +441,7 @@ pub const all_features = blk: {...@@ -394,7 +441,7 @@ pub const all_features = blk: {
394 .int_clamp_insts,441 .int_clamp_insts,
395 .inv_2pi_inline_imm,442 .inv_2pi_inline_imm,
396 .localmemorysize65536,443 .localmemorysize65536,
397 .mad_mac_f32_insts,444 .negative_scratch_offset_bug,
398 .r128_a16,445 .r128_a16,
399 .s_memrealtime,446 .s_memrealtime,
400 .s_memtime_inst,447 .s_memtime_inst,
...@@ -413,6 +460,11 @@ pub const all_features = blk: {...@@ -413,6 +460,11 @@ pub const all_features = blk: {
413 .xnack_support,460 .xnack_support,
414 }),461 }),
415 };462 };
463 result[@enumToInt(Feature.gfx90a_insts)] = .{
464 .llvm_name = "gfx90a-insts",
465 .description = "Additional instructions for GFX90A+",
466 .dependencies = featureSet(&[_]Feature{}),
467 };
416 result[@enumToInt(Feature.gfx9_insts)] = .{468 result[@enumToInt(Feature.gfx9_insts)] = .{
417 .llvm_name = "gfx9-insts",469 .llvm_name = "gfx9-insts",
418 .description = "Additional instructions for GFX9+",470 .description = "Additional instructions for GFX9+",
...@@ -533,6 +585,16 @@ pub const all_features = blk: {...@@ -533,6 +585,16 @@ pub const all_features = blk: {
533 .description = "Has v_movrel*_b32 instructions",585 .description = "Has v_movrel*_b32 instructions",
534 .dependencies = featureSet(&[_]Feature{}),586 .dependencies = featureSet(&[_]Feature{}),
535 };587 };
588 result[@enumToInt(Feature.negative_scratch_offset_bug)] = .{
589 .llvm_name = "negative-scratch-offset-bug",
590 .description = "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9",
591 .dependencies = featureSet(&[_]Feature{}),
592 };
593 result[@enumToInt(Feature.negative_unaligned_scratch_offset_bug)] = .{
594 .llvm_name = "negative-unaligned-scratch-offset-bug",
595 .description = "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10",
596 .dependencies = featureSet(&[_]Feature{}),
597 };
536 result[@enumToInt(Feature.no_data_dep_hazard)] = .{598 result[@enumToInt(Feature.no_data_dep_hazard)] = .{
537 .llvm_name = "no-data-dep-hazard",599 .llvm_name = "no-data-dep-hazard",
538 .description = "Does not need SW waitstates",600 .description = "Does not need SW waitstates",
...@@ -543,11 +605,26 @@ pub const all_features = blk: {...@@ -543,11 +605,26 @@ pub const all_features = blk: {
543 .description = "V_CMPX does not write VCC/SGPR in addition to EXEC",605 .description = "V_CMPX does not write VCC/SGPR in addition to EXEC",
544 .dependencies = featureSet(&[_]Feature{}),606 .dependencies = featureSet(&[_]Feature{}),
545 };607 };
608 result[@enumToInt(Feature.nsa_clause_bug)] = .{
609 .llvm_name = "nsa-clause-bug",
610 .description = "MIMG-NSA in a hard clause has unpredictable results on GFX10.1",
611 .dependencies = featureSet(&[_]Feature{}),
612 };
546 result[@enumToInt(Feature.nsa_encoding)] = .{613 result[@enumToInt(Feature.nsa_encoding)] = .{
547 .llvm_name = "nsa-encoding",614 .llvm_name = "nsa-encoding",
548 .description = "Support NSA encoding for image instructions",615 .description = "Support NSA encoding for image instructions",
549 .dependencies = featureSet(&[_]Feature{}),616 .dependencies = featureSet(&[_]Feature{}),
550 };617 };
618 result[@enumToInt(Feature.nsa_max_size_13)] = .{
619 .llvm_name = "nsa-max-size-13",
620 .description = "The maximum non-sequential address size in VGPRs.",
621 .dependencies = featureSet(&[_]Feature{}),
622 };
623 result[@enumToInt(Feature.nsa_max_size_5)] = .{
624 .llvm_name = "nsa-max-size-5",
625 .description = "The maximum non-sequential address size in VGPRs.",
626 .dependencies = featureSet(&[_]Feature{}),
627 };
551 result[@enumToInt(Feature.nsa_to_vmem_bug)] = .{628 result[@enumToInt(Feature.nsa_to_vmem_bug)] = .{
552 .llvm_name = "nsa-to-vmem-bug",629 .llvm_name = "nsa-to-vmem-bug",
553 .description = "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero",630 .description = "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero",
...@@ -558,6 +635,16 @@ pub const all_features = blk: {...@@ -558,6 +635,16 @@ pub const all_features = blk: {
558 .description = "Branch offset of 3f hardware bug",635 .description = "Branch offset of 3f hardware bug",
559 .dependencies = featureSet(&[_]Feature{}),636 .dependencies = featureSet(&[_]Feature{}),
560 };637 };
638 result[@enumToInt(Feature.packed_fp32_ops)] = .{
639 .llvm_name = "packed-fp32-ops",
640 .description = "Support packed fp32 instructions",
641 .dependencies = featureSet(&[_]Feature{}),
642 };
643 result[@enumToInt(Feature.packed_tid)] = .{
644 .llvm_name = "packed-tid",
645 .description = "Workitem IDs are packed into v0 at kernel launch",
646 .dependencies = featureSet(&[_]Feature{}),
647 };
561 result[@enumToInt(Feature.pk_fmac_f16_inst)] = .{648 result[@enumToInt(Feature.pk_fmac_f16_inst)] = .{
562 .llvm_name = "pk-fmac-f16-inst",649 .llvm_name = "pk-fmac-f16-inst",
563 .description = "Has v_pk_fmac_f16 instruction",650 .description = "Has v_pk_fmac_f16 instruction",
...@@ -639,6 +726,7 @@ pub const all_features = blk: {...@@ -639,6 +726,7 @@ pub const all_features = blk: {
639 .dependencies = featureSet(&[_]Feature{726 .dependencies = featureSet(&[_]Feature{
640 .ci_insts,727 .ci_insts,
641 .ds_src2_insts,728 .ds_src2_insts,
729 .extended_image_insts,
642 .flat_address_space,730 .flat_address_space,
643 .fp64,731 .fp64,
644 .gfx7_gfx8_gfx9_insts,732 .gfx7_gfx8_gfx9_insts,
...@@ -657,6 +745,11 @@ pub const all_features = blk: {...@@ -657,6 +745,11 @@ pub const all_features = blk: {
657 .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",745 .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",
658 .dependencies = featureSet(&[_]Feature{}),746 .dependencies = featureSet(&[_]Feature{}),
659 };747 };
748 result[@enumToInt(Feature.shader_cycles_register)] = .{
749 .llvm_name = "shader-cycles-register",
750 .description = "Has SHADER_CYCLES hardware register",
751 .dependencies = featureSet(&[_]Feature{}),
752 };
660 result[@enumToInt(Feature.si_scheduler)] = .{753 result[@enumToInt(Feature.si_scheduler)] = .{
661 .llvm_name = "si-scheduler",754 .llvm_name = "si-scheduler",
662 .description = "Enable SI Machine Scheduler",755 .description = "Enable SI Machine Scheduler",
...@@ -672,6 +765,7 @@ pub const all_features = blk: {...@@ -672,6 +765,7 @@ pub const all_features = blk: {
672 .description = "SOUTHERN_ISLANDS GPU generation",765 .description = "SOUTHERN_ISLANDS GPU generation",
673 .dependencies = featureSet(&[_]Feature{766 .dependencies = featureSet(&[_]Feature{
674 .ds_src2_insts,767 .ds_src2_insts,
768 .extended_image_insts,
675 .fp64,769 .fp64,
676 .ldsbankcount32,770 .ldsbankcount32,
677 .localmemorysize32768,771 .localmemorysize32768,
...@@ -693,6 +787,11 @@ pub const all_features = blk: {...@@ -693,6 +787,11 @@ pub const all_features = blk: {
693 .description = "Hardware supports SRAMECC",787 .description = "Hardware supports SRAMECC",
694 .dependencies = featureSet(&[_]Feature{}),788 .dependencies = featureSet(&[_]Feature{}),
695 };789 };
790 result[@enumToInt(Feature.tgsplit)] = .{
791 .llvm_name = "tgsplit",
792 .description = "Enable threadgroup split execution",
793 .dependencies = featureSet(&[_]Feature{}),
794 };
696 result[@enumToInt(Feature.trap_handler)] = .{795 result[@enumToInt(Feature.trap_handler)] = .{
697 .llvm_name = "trap-handler",796 .llvm_name = "trap-handler",
698 .description = "Trap handler support",797 .description = "Trap handler support",
...@@ -761,6 +860,7 @@ pub const all_features = blk: {...@@ -761,6 +860,7 @@ pub const all_features = blk: {
761 .ci_insts,860 .ci_insts,
762 .dpp,861 .dpp,
763 .ds_src2_insts,862 .ds_src2_insts,
863 .extended_image_insts,
764 .fast_denormal_f32,864 .fast_denormal_f32,
765 .flat_address_space,865 .flat_address_space,
766 .fp64,866 .fp64,
...@@ -892,10 +992,12 @@ pub const cpu = struct {...@@ -892,10 +992,12 @@ pub const cpu = struct {
892 .lds_misaligned_bug,992 .lds_misaligned_bug,
893 .ldsbankcount32,993 .ldsbankcount32,
894 .mad_mac_f32_insts,994 .mad_mac_f32_insts,
995 .negative_unaligned_scratch_offset_bug,
996 .nsa_clause_bug,
895 .nsa_encoding,997 .nsa_encoding,
998 .nsa_max_size_5,
896 .nsa_to_vmem_bug,999 .nsa_to_vmem_bug,
897 .offset_3f_bug,1000 .offset_3f_bug,
898 .s_memtime_inst,
899 .scalar_atomics,1001 .scalar_atomics,
900 .scalar_flat_scratch_insts,1002 .scalar_flat_scratch_insts,
901 .scalar_stores,1003 .scalar_stores,
...@@ -916,6 +1018,7 @@ pub const cpu = struct {...@@ -916,6 +1018,7 @@ pub const cpu = struct {
916 .dot2_insts,1018 .dot2_insts,
917 .dot5_insts,1019 .dot5_insts,
918 .dot6_insts,1020 .dot6_insts,
1021 .dot7_insts,
919 .ds_src2_insts,1022 .ds_src2_insts,
920 .flat_segment_offset_bug,1023 .flat_segment_offset_bug,
921 .get_wave_id_inst,1024 .get_wave_id_inst,
...@@ -925,10 +1028,12 @@ pub const cpu = struct {...@@ -925,10 +1028,12 @@ pub const cpu = struct {
925 .lds_misaligned_bug,1028 .lds_misaligned_bug,
926 .ldsbankcount32,1029 .ldsbankcount32,
927 .mad_mac_f32_insts,1030 .mad_mac_f32_insts,
1031 .negative_unaligned_scratch_offset_bug,
1032 .nsa_clause_bug,
928 .nsa_encoding,1033 .nsa_encoding,
1034 .nsa_max_size_5,
929 .nsa_to_vmem_bug,1035 .nsa_to_vmem_bug,
930 .offset_3f_bug,1036 .offset_3f_bug,
931 .s_memtime_inst,
932 .scalar_atomics,1037 .scalar_atomics,
933 .scalar_flat_scratch_insts,1038 .scalar_flat_scratch_insts,
934 .scalar_stores,1039 .scalar_stores,
...@@ -949,6 +1054,7 @@ pub const cpu = struct {...@@ -949,6 +1054,7 @@ pub const cpu = struct {
949 .dot2_insts,1054 .dot2_insts,
950 .dot5_insts,1055 .dot5_insts,
951 .dot6_insts,1056 .dot6_insts,
1057 .dot7_insts,
952 .ds_src2_insts,1058 .ds_src2_insts,
953 .flat_segment_offset_bug,1059 .flat_segment_offset_bug,
954 .get_wave_id_inst,1060 .get_wave_id_inst,
...@@ -958,10 +1064,44 @@ pub const cpu = struct {...@@ -958,10 +1064,44 @@ pub const cpu = struct {
958 .lds_misaligned_bug,1064 .lds_misaligned_bug,
959 .ldsbankcount32,1065 .ldsbankcount32,
960 .mad_mac_f32_insts,1066 .mad_mac_f32_insts,
1067 .negative_unaligned_scratch_offset_bug,
1068 .nsa_clause_bug,
961 .nsa_encoding,1069 .nsa_encoding,
1070 .nsa_max_size_5,
1071 .nsa_to_vmem_bug,
1072 .offset_3f_bug,
1073 .scalar_atomics,
1074 .scalar_flat_scratch_insts,
1075 .scalar_stores,
1076 .smem_to_vector_write_hazard,
1077 .vcmpx_exec_war_hazard,
1078 .vcmpx_permlane_hazard,
1079 .vmem_to_scalar_write_hazard,
1080 .wavefrontsize32,
1081 .xnack_support,
1082 }),
1083 };
1084 pub const gfx1013 = CpuModel{
1085 .name = "gfx1013",
1086 .llvm_name = "gfx1013",
1087 .features = featureSet(&[_]Feature{
1088 .dl_insts,
1089 .ds_src2_insts,
1090 .flat_segment_offset_bug,
1091 .get_wave_id_inst,
1092 .gfx10,
1093 .gfx10_a_encoding,
1094 .inst_fwd_prefetch_bug,
1095 .lds_branch_vmem_war_hazard,
1096 .lds_misaligned_bug,
1097 .ldsbankcount32,
1098 .mad_mac_f32_insts,
1099 .negative_unaligned_scratch_offset_bug,
1100 .nsa_clause_bug,
1101 .nsa_encoding,
1102 .nsa_max_size_5,
962 .nsa_to_vmem_bug,1103 .nsa_to_vmem_bug,
963 .offset_3f_bug,1104 .offset_3f_bug,
964 .s_memtime_inst,
965 .scalar_atomics,1105 .scalar_atomics,
966 .scalar_flat_scratch_insts,1106 .scalar_flat_scratch_insts,
967 .scalar_stores,1107 .scalar_stores,
...@@ -982,11 +1122,15 @@ pub const cpu = struct {...@@ -982,11 +1122,15 @@ pub const cpu = struct {
982 .dot2_insts,1122 .dot2_insts,
983 .dot5_insts,1123 .dot5_insts,
984 .dot6_insts,1124 .dot6_insts,
1125 .dot7_insts,
985 .gfx10,1126 .gfx10,
986 .gfx10_3_insts,1127 .gfx10_3_insts,
1128 .gfx10_a_encoding,
987 .gfx10_b_encoding,1129 .gfx10_b_encoding,
988 .ldsbankcount32,1130 .ldsbankcount32,
989 .nsa_encoding,1131 .nsa_encoding,
1132 .nsa_max_size_13,
1133 .shader_cycles_register,
990 .wavefrontsize32,1134 .wavefrontsize32,
991 }),1135 }),
992 };1136 };
...@@ -999,11 +1143,15 @@ pub const cpu = struct {...@@ -999,11 +1143,15 @@ pub const cpu = struct {
999 .dot2_insts,1143 .dot2_insts,
1000 .dot5_insts,1144 .dot5_insts,
1001 .dot6_insts,1145 .dot6_insts,
1146 .dot7_insts,
1002 .gfx10,1147 .gfx10,
1003 .gfx10_3_insts,1148 .gfx10_3_insts,
1149 .gfx10_a_encoding,
1004 .gfx10_b_encoding,1150 .gfx10_b_encoding,
1005 .ldsbankcount32,1151 .ldsbankcount32,
1006 .nsa_encoding,1152 .nsa_encoding,
1153 .nsa_max_size_13,
1154 .shader_cycles_register,
1007 .wavefrontsize32,1155 .wavefrontsize32,
1008 }),1156 }),
1009 };1157 };
...@@ -1016,11 +1164,15 @@ pub const cpu = struct {...@@ -1016,11 +1164,15 @@ pub const cpu = struct {
1016 .dot2_insts,1164 .dot2_insts,
1017 .dot5_insts,1165 .dot5_insts,
1018 .dot6_insts,1166 .dot6_insts,
1167 .dot7_insts,
1019 .gfx10,1168 .gfx10,
1020 .gfx10_3_insts,1169 .gfx10_3_insts,
1170 .gfx10_a_encoding,
1021 .gfx10_b_encoding,1171 .gfx10_b_encoding,
1022 .ldsbankcount32,1172 .ldsbankcount32,
1023 .nsa_encoding,1173 .nsa_encoding,
1174 .nsa_max_size_13,
1175 .shader_cycles_register,
1024 .wavefrontsize32,1176 .wavefrontsize32,
1025 }),1177 }),
1026 };1178 };
...@@ -1033,11 +1185,57 @@ pub const cpu = struct {...@@ -1033,11 +1185,57 @@ pub const cpu = struct {
1033 .dot2_insts,1185 .dot2_insts,
1034 .dot5_insts,1186 .dot5_insts,
1035 .dot6_insts,1187 .dot6_insts,
1188 .dot7_insts,
1189 .gfx10,
1190 .gfx10_3_insts,
1191 .gfx10_a_encoding,
1192 .gfx10_b_encoding,
1193 .ldsbankcount32,
1194 .nsa_encoding,
1195 .nsa_max_size_13,
1196 .shader_cycles_register,
1197 .wavefrontsize32,
1198 }),
1199 };
1200 pub const gfx1034 = CpuModel{
1201 .name = "gfx1034",
1202 .llvm_name = "gfx1034",
1203 .features = featureSet(&[_]Feature{
1204 .dl_insts,
1205 .dot1_insts,
1206 .dot2_insts,
1207 .dot5_insts,
1208 .dot6_insts,
1209 .dot7_insts,
1036 .gfx10,1210 .gfx10,
1037 .gfx10_3_insts,1211 .gfx10_3_insts,
1212 .gfx10_a_encoding,
1038 .gfx10_b_encoding,1213 .gfx10_b_encoding,
1039 .ldsbankcount32,1214 .ldsbankcount32,
1040 .nsa_encoding,1215 .nsa_encoding,
1216 .nsa_max_size_13,
1217 .shader_cycles_register,
1218 .wavefrontsize32,
1219 }),
1220 };
1221 pub const gfx1035 = CpuModel{
1222 .name = "gfx1035",
1223 .llvm_name = "gfx1035",
1224 .features = featureSet(&[_]Feature{
1225 .dl_insts,
1226 .dot1_insts,
1227 .dot2_insts,
1228 .dot5_insts,
1229 .dot6_insts,
1230 .dot7_insts,
1231 .gfx10,
1232 .gfx10_3_insts,
1233 .gfx10_a_encoding,
1234 .gfx10_b_encoding,
1235 .ldsbankcount32,
1236 .nsa_encoding,
1237 .nsa_max_size_13,
1238 .shader_cycles_register,
1041 .wavefrontsize32,1239 .wavefrontsize32,
1042 }),1240 }),
1043 };1241 };
...@@ -1171,9 +1369,12 @@ pub const cpu = struct {...@@ -1171,9 +1369,12 @@ pub const cpu = struct {
1171 .name = "gfx900",1369 .name = "gfx900",
1172 .llvm_name = "gfx900",1370 .llvm_name = "gfx900",
1173 .features = featureSet(&[_]Feature{1371 .features = featureSet(&[_]Feature{
1372 .ds_src2_insts,
1373 .extended_image_insts,
1174 .gfx9,1374 .gfx9,
1175 .image_gather4_d16_bug,1375 .image_gather4_d16_bug,
1176 .ldsbankcount32,1376 .ldsbankcount32,
1377 .mad_mac_f32_insts,
1177 .mad_mix_insts,1378 .mad_mix_insts,
1178 }),1379 }),
1179 };1380 };
...@@ -1181,9 +1382,12 @@ pub const cpu = struct {...@@ -1181,9 +1382,12 @@ pub const cpu = struct {
1181 .name = "gfx902",1382 .name = "gfx902",
1182 .llvm_name = "gfx902",1383 .llvm_name = "gfx902",
1183 .features = featureSet(&[_]Feature{1384 .features = featureSet(&[_]Feature{
1385 .ds_src2_insts,
1386 .extended_image_insts,
1184 .gfx9,1387 .gfx9,
1185 .image_gather4_d16_bug,1388 .image_gather4_d16_bug,
1186 .ldsbankcount32,1389 .ldsbankcount32,
1390 .mad_mac_f32_insts,
1187 .mad_mix_insts,1391 .mad_mix_insts,
1188 }),1392 }),
1189 };1393 };
...@@ -1191,10 +1395,13 @@ pub const cpu = struct {...@@ -1191,10 +1395,13 @@ pub const cpu = struct {
1191 .name = "gfx904",1395 .name = "gfx904",
1192 .llvm_name = "gfx904",1396 .llvm_name = "gfx904",
1193 .features = featureSet(&[_]Feature{1397 .features = featureSet(&[_]Feature{
1398 .ds_src2_insts,
1399 .extended_image_insts,
1194 .fma_mix_insts,1400 .fma_mix_insts,
1195 .gfx9,1401 .gfx9,
1196 .image_gather4_d16_bug,1402 .image_gather4_d16_bug,
1197 .ldsbankcount32,1403 .ldsbankcount32,
1404 .mad_mac_f32_insts,
1198 }),1405 }),
1199 };1406 };
1200 pub const gfx906 = CpuModel{1407 pub const gfx906 = CpuModel{
...@@ -1204,11 +1411,15 @@ pub const cpu = struct {...@@ -1204,11 +1411,15 @@ pub const cpu = struct {
1204 .dl_insts,1411 .dl_insts,
1205 .dot1_insts,1412 .dot1_insts,
1206 .dot2_insts,1413 .dot2_insts,
1414 .dot7_insts,
1415 .ds_src2_insts,
1416 .extended_image_insts,
1207 .fma_mix_insts,1417 .fma_mix_insts,
1208 .gfx9,1418 .gfx9,
1209 .half_rate_64_ops,1419 .half_rate_64_ops,
1210 .image_gather4_d16_bug,1420 .image_gather4_d16_bug,
1211 .ldsbankcount32,1421 .ldsbankcount32,
1422 .mad_mac_f32_insts,
1212 .sramecc_support,1423 .sramecc_support,
1213 }),1424 }),
1214 };1425 };
...@@ -1224,11 +1435,15 @@ pub const cpu = struct {...@@ -1224,11 +1435,15 @@ pub const cpu = struct {
1224 .dot4_insts,1435 .dot4_insts,
1225 .dot5_insts,1436 .dot5_insts,
1226 .dot6_insts,1437 .dot6_insts,
1438 .dot7_insts,
1439 .ds_src2_insts,
1440 .extended_image_insts,
1227 .fma_mix_insts,1441 .fma_mix_insts,
1228 .gfx9,1442 .gfx9,
1229 .half_rate_64_ops,1443 .half_rate_64_ops,
1230 .image_gather4_d16_bug,1444 .image_gather4_d16_bug,
1231 .ldsbankcount32,1445 .ldsbankcount32,
1446 .mad_mac_f32_insts,
1232 .mai_insts,1447 .mai_insts,
1233 .mfma_inline_literal_bug,1448 .mfma_inline_literal_bug,
1234 .pk_fmac_f16_inst,1449 .pk_fmac_f16_inst,
...@@ -1239,21 +1454,53 @@ pub const cpu = struct {...@@ -1239,21 +1454,53 @@ pub const cpu = struct {
1239 .name = "gfx909",1454 .name = "gfx909",
1240 .llvm_name = "gfx909",1455 .llvm_name = "gfx909",
1241 .features = featureSet(&[_]Feature{1456 .features = featureSet(&[_]Feature{
1457 .ds_src2_insts,
1458 .extended_image_insts,
1242 .gfx9,1459 .gfx9,
1243 .image_gather4_d16_bug,1460 .image_gather4_d16_bug,
1244 .ldsbankcount32,1461 .ldsbankcount32,
1462 .mad_mac_f32_insts,
1245 .mad_mix_insts,1463 .mad_mix_insts,
1246 }),1464 }),
1247 };1465 };
1466 pub const gfx90a = CpuModel{
1467 .name = "gfx90a",
1468 .llvm_name = "gfx90a",
1469 .features = featureSet(&[_]Feature{
1470 .atomic_fadd_insts,
1471 .dl_insts,
1472 .dot1_insts,
1473 .dot2_insts,
1474 .dot3_insts,
1475 .dot4_insts,
1476 .dot5_insts,
1477 .dot6_insts,
1478 .dot7_insts,
1479 .dpp_64bit,
1480 .fma_mix_insts,
1481 .full_rate_64_ops,
1482 .gfx9,
1483 .gfx90a_insts,
1484 .ldsbankcount32,
1485 .mad_mac_f32_insts,
1486 .mai_insts,
1487 .packed_fp32_ops,
1488 .packed_tid,
1489 .pk_fmac_f16_inst,
1490 .sramecc_support,
1491 }),
1492 };
1248 pub const gfx90c = CpuModel{1493 pub const gfx90c = CpuModel{
1249 .name = "gfx90c",1494 .name = "gfx90c",
1250 .llvm_name = "gfx90c",1495 .llvm_name = "gfx90c",
1251 .features = featureSet(&[_]Feature{1496 .features = featureSet(&[_]Feature{
1497 .ds_src2_insts,
1498 .extended_image_insts,
1252 .gfx9,1499 .gfx9,
1253 .image_gather4_d16_bug,1500 .image_gather4_d16_bug,
1254 .ldsbankcount32,1501 .ldsbankcount32,
1502 .mad_mac_f32_insts,
1255 .mad_mix_insts,1503 .mad_mix_insts,
1256 .xnack,
1257 }),1504 }),
1258 };1505 };
1259 pub const hainan = CpuModel{1506 pub const hainan = CpuModel{
lib/std/target/arc.zig created+39
...@@ -0,0 +1,39 @@
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 norm,
9};
10
11pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
12pub const featureSetHas = CpuFeature.feature_set_fns(Feature).featureSetHas;
13pub const featureSetHasAny = CpuFeature.feature_set_fns(Feature).featureSetHasAny;
14pub const featureSetHasAll = CpuFeature.feature_set_fns(Feature).featureSetHasAll;
15
16pub const all_features = blk: {
17 const len = @typeInfo(Feature).Enum.fields.len;
18 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
19 var result: [len]CpuFeature = undefined;
20 result[@enumToInt(Feature.norm)] = .{
21 .llvm_name = "norm",
22 .description = "Enable support for norm instruction.",
23 .dependencies = featureSet(&[_]Feature{}),
24 };
25 const ti = @typeInfo(Feature);
26 for (result) |*elem, i| {
27 elem.index = i;
28 elem.name = ti.Enum.fields[i].name;
29 }
30 break :blk result;
31};
32
33pub const cpu = struct {
34 pub const generic = CpuModel{
35 .name = "generic",
36 .llvm_name = "generic",
37 .features = featureSet(&[_]Feature{}),
38 };
39};
lib/std/target/arm.zig+12-8
...@@ -51,6 +51,7 @@ pub const Feature = enum {...@@ -51,6 +51,7 @@ pub const Feature = enum {
51 fuse_aes,51 fuse_aes,
52 fuse_literals,52 fuse_literals,
53 harden_sls_blr,53 harden_sls_blr,
54 harden_sls_nocomdat,
54 harden_sls_retbr,55 harden_sls_retbr,
55 has_v4t,56 has_v4t,
56 has_v5t,57 has_v5t,
...@@ -487,6 +488,11 @@ pub const all_features = blk: {...@@ -487,6 +488,11 @@ pub const all_features = blk: {
487 .description = "Harden against straight line speculation across indirect calls",488 .description = "Harden against straight line speculation across indirect calls",
488 .dependencies = featureSet(&[_]Feature{}),489 .dependencies = featureSet(&[_]Feature{}),
489 };490 };
491 result[@enumToInt(Feature.harden_sls_nocomdat)] = .{
492 .llvm_name = "harden-sls-nocomdat",
493 .description = "Generate thunk code for SLS mitigation in the normal text section",
494 .dependencies = featureSet(&[_]Feature{}),
495 };
490 result[@enumToInt(Feature.harden_sls_retbr)] = .{496 result[@enumToInt(Feature.harden_sls_retbr)] = .{
491 .llvm_name = "harden-sls-retbr",497 .llvm_name = "harden-sls-retbr",
492 .description = "Harden against straight line speculation across RETurn and BranchRegister instructions",498 .description = "Harden against straight line speculation across RETurn and BranchRegister instructions",
...@@ -1245,7 +1251,7 @@ pub const all_features = blk: {...@@ -1245,7 +1251,7 @@ pub const all_features = blk: {
1245 };1251 };
1246 result[@enumToInt(Feature.v8_7a)] = .{1252 result[@enumToInt(Feature.v8_7a)] = .{
1247 .llvm_name = "armv8.7-a",1253 .llvm_name = "armv8.7-a",
1248 .description = "ARMv86a architecture",1254 .description = "ARMv87a architecture",
1249 .dependencies = featureSet(&[_]Feature{1255 .dependencies = featureSet(&[_]Feature{
1250 .aclass,1256 .aclass,
1251 .crc,1257 .crc,
...@@ -1517,13 +1523,6 @@ pub const cpu = struct {...@@ -1517,13 +1523,6 @@ pub const cpu = struct {
1517 .vfp2,1523 .vfp2,
1518 }),1524 }),
1519 };1525 };
1520 pub const arm1176j_s = CpuModel{
1521 .name = "arm1176j_s",
1522 .llvm_name = "arm1176j-s",
1523 .features = featureSet(&[_]Feature{
1524 .v6kz,
1525 }),
1526 };
1527 pub const arm1176jz_s = CpuModel{1526 pub const arm1176jz_s = CpuModel{
1528 .name = "arm1176jz_s",1527 .name = "arm1176jz_s",
1529 .llvm_name = "arm1176jz-s",1528 .llvm_name = "arm1176jz-s",
...@@ -1889,6 +1888,7 @@ pub const cpu = struct {...@@ -1889,6 +1888,7 @@ pub const cpu = struct {
1889 .name = "cortex_m0",1888 .name = "cortex_m0",
1890 .llvm_name = "cortex-m0",1889 .llvm_name = "cortex-m0",
1891 .features = featureSet(&[_]Feature{1890 .features = featureSet(&[_]Feature{
1891 .no_branch_predictor,
1892 .v6m,1892 .v6m,
1893 }),1893 }),
1894 };1894 };
...@@ -1896,6 +1896,7 @@ pub const cpu = struct {...@@ -1896,6 +1896,7 @@ pub const cpu = struct {
1896 .name = "cortex_m0plus",1896 .name = "cortex_m0plus",
1897 .llvm_name = "cortex-m0plus",1897 .llvm_name = "cortex-m0plus",
1898 .features = featureSet(&[_]Feature{1898 .features = featureSet(&[_]Feature{
1899 .no_branch_predictor,
1899 .v6m,1900 .v6m,
1900 }),1901 }),
1901 };1902 };
...@@ -1903,6 +1904,7 @@ pub const cpu = struct {...@@ -1903,6 +1904,7 @@ pub const cpu = struct {
1903 .name = "cortex_m1",1904 .name = "cortex_m1",
1904 .llvm_name = "cortex-m1",1905 .llvm_name = "cortex-m1",
1905 .features = featureSet(&[_]Feature{1906 .features = featureSet(&[_]Feature{
1907 .no_branch_predictor,
1906 .v6m,1908 .v6m,
1907 }),1909 }),
1908 };1910 };
...@@ -1910,6 +1912,7 @@ pub const cpu = struct {...@@ -1910,6 +1912,7 @@ pub const cpu = struct {
1910 .name = "cortex_m23",1912 .name = "cortex_m23",
1911 .llvm_name = "cortex-m23",1913 .llvm_name = "cortex-m23",
1912 .features = featureSet(&[_]Feature{1914 .features = featureSet(&[_]Feature{
1915 .no_branch_predictor,
1913 .no_movt,1916 .no_movt,
1914 .v8m,1917 .v8m,
1915 }),1918 }),
...@@ -2225,6 +2228,7 @@ pub const cpu = struct {...@@ -2225,6 +2228,7 @@ pub const cpu = struct {
2225 .name = "sc000",2228 .name = "sc000",
2226 .llvm_name = "sc000",2229 .llvm_name = "sc000",
2227 .features = featureSet(&[_]Feature{2230 .features = featureSet(&[_]Feature{
2231 .no_branch_predictor,
2228 .v6m,2232 .v6m,
2229 }),2233 }),
2230 };2234 };
lib/std/target/hexagon.zig+35
...@@ -16,6 +16,7 @@ pub const Feature = enum {...@@ -16,6 +16,7 @@ pub const Feature = enum {
16 hvxv65,16 hvxv65,
17 hvxv66,17 hvxv66,
18 hvxv67,18 hvxv67,
19 hvxv68,
19 long_calls,20 long_calls,
20 mem_noshuf,21 mem_noshuf,
21 memops,22 memops,
...@@ -35,6 +36,7 @@ pub const Feature = enum {...@@ -35,6 +36,7 @@ pub const Feature = enum {
35 v65,36 v65,
36 v66,37 v66,
37 v67,38 v67,
39 v68,
38 zreg,40 zreg,
39};41};
4042
...@@ -117,6 +119,13 @@ pub const all_features = blk: {...@@ -117,6 +119,13 @@ pub const all_features = blk: {
117 .hvxv66,119 .hvxv66,
118 }),120 }),
119 };121 };
122 result[@enumToInt(Feature.hvxv68)] = .{
123 .llvm_name = "hvxv68",
124 .description = "Hexagon HVX instructions",
125 .dependencies = featureSet(&[_]Feature{
126 .hvxv67,
127 }),
128 };
120 result[@enumToInt(Feature.long_calls)] = .{129 result[@enumToInt(Feature.long_calls)] = .{
121 .llvm_name = "long-calls",130 .llvm_name = "long-calls",
122 .description = "Use constant-extended calls",131 .description = "Use constant-extended calls",
...@@ -216,6 +225,11 @@ pub const all_features = blk: {...@@ -216,6 +225,11 @@ pub const all_features = blk: {
216 .description = "Enable Hexagon V67 architecture",225 .description = "Enable Hexagon V67 architecture",
217 .dependencies = featureSet(&[_]Feature{}),226 .dependencies = featureSet(&[_]Feature{}),
218 };227 };
228 result[@enumToInt(Feature.v68)] = .{
229 .llvm_name = "v68",
230 .description = "Enable Hexagon V68 architecture",
231 .dependencies = featureSet(&[_]Feature{}),
232 };
219 result[@enumToInt(Feature.zreg)] = .{233 result[@enumToInt(Feature.zreg)] = .{
220 .llvm_name = "zreg",234 .llvm_name = "zreg",
221 .description = "Hexagon ZReg extension instructions",235 .description = "Hexagon ZReg extension instructions",
...@@ -385,4 +399,25 @@ pub const cpu = struct {...@@ -385,4 +399,25 @@ pub const cpu = struct {
385 .v67,399 .v67,
386 }),400 }),
387 };401 };
402 pub const hexagonv68 = CpuModel{
403 .name = "hexagonv68",
404 .llvm_name = "hexagonv68",
405 .features = featureSet(&[_]Feature{
406 .compound,
407 .duplex,
408 .mem_noshuf,
409 .memops,
410 .nvj,
411 .nvs,
412 .small_data,
413 .v5,
414 .v55,
415 .v60,
416 .v62,
417 .v65,
418 .v66,
419 .v67,
420 .v68,
421 }),
422 };
388};423};
lib/std/target/nvptx.zig+26
...@@ -17,6 +17,8 @@ pub const Feature = enum {...@@ -17,6 +17,8 @@ pub const Feature = enum {
17 ptx64,17 ptx64,
18 ptx65,18 ptx65,
19 ptx70,19 ptx70,
20 ptx71,
21 ptx72,
20 sm_20,22 sm_20,
21 sm_21,23 sm_21,
22 sm_30,24 sm_30,
...@@ -33,6 +35,7 @@ pub const Feature = enum {...@@ -33,6 +35,7 @@ pub const Feature = enum {
33 sm_72,35 sm_72,
34 sm_75,36 sm_75,
35 sm_80,37 sm_80,
38 sm_86,
36};39};
3740
38pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;41pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
...@@ -104,6 +107,16 @@ pub const all_features = blk: {...@@ -104,6 +107,16 @@ pub const all_features = blk: {
104 .description = "Use PTX version 7.0",107 .description = "Use PTX version 7.0",
105 .dependencies = featureSet(&[_]Feature{}),108 .dependencies = featureSet(&[_]Feature{}),
106 };109 };
110 result[@enumToInt(Feature.ptx71)] = .{
111 .llvm_name = "ptx71",
112 .description = "Use PTX version 7.1",
113 .dependencies = featureSet(&[_]Feature{}),
114 };
115 result[@enumToInt(Feature.ptx72)] = .{
116 .llvm_name = "ptx72",
117 .description = "Use PTX version 7.2",
118 .dependencies = featureSet(&[_]Feature{}),
119 };
107 result[@enumToInt(Feature.sm_20)] = .{120 result[@enumToInt(Feature.sm_20)] = .{
108 .llvm_name = "sm_20",121 .llvm_name = "sm_20",
109 .description = "Target SM 2.0",122 .description = "Target SM 2.0",
...@@ -184,6 +197,11 @@ pub const all_features = blk: {...@@ -184,6 +197,11 @@ pub const all_features = blk: {
184 .description = "Target SM 8.0",197 .description = "Target SM 8.0",
185 .dependencies = featureSet(&[_]Feature{}),198 .dependencies = featureSet(&[_]Feature{}),
186 };199 };
200 result[@enumToInt(Feature.sm_86)] = .{
201 .llvm_name = "sm_86",
202 .description = "Target SM 8.6",
203 .dependencies = featureSet(&[_]Feature{}),
204 };
187 const ti = @typeInfo(Feature);205 const ti = @typeInfo(Feature);
188 for (result) |*elem, i| {206 for (result) |*elem, i| {
189 elem.index = i;207 elem.index = i;
...@@ -317,4 +335,12 @@ pub const cpu = struct {...@@ -317,4 +335,12 @@ pub const cpu = struct {
317 .sm_80,335 .sm_80,
318 }),336 }),
319 };337 };
338 pub const sm_86 = CpuModel{
339 .name = "sm_86",
340 .llvm_name = "sm_86",
341 .features = featureSet(&[_]Feature{
342 .ptx71,
343 .sm_86,
344 }),
345 };
320};346};
lib/std/target/powerpc.zig+34-1
...@@ -37,6 +37,7 @@ pub const Feature = enum {...@@ -37,6 +37,7 @@ pub const Feature = enum {
37 htm,37 htm,
38 icbt,38 icbt,
39 invariant_function_descriptors,39 invariant_function_descriptors,
40 isa_v207_instructions,
40 isa_v30_instructions,41 isa_v30_instructions,
41 isa_v31_instructions,42 isa_v31_instructions,
42 isel,43 isel,
...@@ -62,7 +63,10 @@ pub const Feature = enum {...@@ -62,7 +63,10 @@ pub const Feature = enum {
62 ppc_prera_sched,63 ppc_prera_sched,
63 predictable_select_expensive,64 predictable_select_expensive,
64 prefix_instrs,65 prefix_instrs,
66 privileged,
67 quadword_atomics,
65 recipprec,68 recipprec,
69 rop_protect,
66 secure_plt,70 secure_plt,
67 slow_popcntd,71 slow_popcntd,
68 spe,72 spe,
...@@ -277,10 +281,17 @@ pub const all_features = blk: {...@@ -277,10 +281,17 @@ pub const all_features = blk: {
277 .description = "Assume function descriptors are invariant",281 .description = "Assume function descriptors are invariant",
278 .dependencies = featureSet(&[_]Feature{}),282 .dependencies = featureSet(&[_]Feature{}),
279 };283 };
284 result[@enumToInt(Feature.isa_v207_instructions)] = .{
285 .llvm_name = "isa-v207-instructions",
286 .description = "Enable instructions in ISA 2.07.",
287 .dependencies = featureSet(&[_]Feature{}),
288 };
280 result[@enumToInt(Feature.isa_v30_instructions)] = .{289 result[@enumToInt(Feature.isa_v30_instructions)] = .{
281 .llvm_name = "isa-v30-instructions",290 .llvm_name = "isa-v30-instructions",
282 .description = "Enable instructions in ISA 3.0.",291 .description = "Enable instructions in ISA 3.0.",
283 .dependencies = featureSet(&[_]Feature{}),292 .dependencies = featureSet(&[_]Feature{
293 .isa_v207_instructions,
294 }),
284 };295 };
285 result[@enumToInt(Feature.isa_v31_instructions)] = .{296 result[@enumToInt(Feature.isa_v31_instructions)] = .{
286 .llvm_name = "isa-v31-instructions",297 .llvm_name = "isa-v31-instructions",
...@@ -433,11 +444,26 @@ pub const all_features = blk: {...@@ -433,11 +444,26 @@ pub const all_features = blk: {
433 .power9_altivec,444 .power9_altivec,
434 }),445 }),
435 };446 };
447 result[@enumToInt(Feature.privileged)] = .{
448 .llvm_name = "privileged",
449 .description = "Add privileged instructions",
450 .dependencies = featureSet(&[_]Feature{}),
451 };
452 result[@enumToInt(Feature.quadword_atomics)] = .{
453 .llvm_name = "quadword-atomics",
454 .description = "Enable lqarx and stqcx.",
455 .dependencies = featureSet(&[_]Feature{}),
456 };
436 result[@enumToInt(Feature.recipprec)] = .{457 result[@enumToInt(Feature.recipprec)] = .{
437 .llvm_name = "recipprec",458 .llvm_name = "recipprec",
438 .description = "Assume higher precision reciprocal estimates",459 .description = "Assume higher precision reciprocal estimates",
439 .dependencies = featureSet(&[_]Feature{}),460 .dependencies = featureSet(&[_]Feature{}),
440 };461 };
462 result[@enumToInt(Feature.rop_protect)] = .{
463 .llvm_name = "rop-protect",
464 .description = "Add ROP protect",
465 .dependencies = featureSet(&[_]Feature{}),
466 };
441 result[@enumToInt(Feature.secure_plt)] = .{467 result[@enumToInt(Feature.secure_plt)] = .{
442 .llvm_name = "secure-plt",468 .llvm_name = "secure-plt",
443 .description = "Enable secure plt mode",469 .description = "Enable secure plt mode",
...@@ -696,6 +722,7 @@ pub const cpu = struct {...@@ -696,6 +722,7 @@ pub const cpu = struct {
696 .ppc_postra_sched,722 .ppc_postra_sched,
697 .ppc_prera_sched,723 .ppc_prera_sched,
698 .predictable_select_expensive,724 .predictable_select_expensive,
725 .quadword_atomics,
699 .recipprec,726 .recipprec,
700 .stfiwx,727 .stfiwx,
701 .two_const_nr,728 .two_const_nr,
...@@ -790,6 +817,7 @@ pub const cpu = struct {...@@ -790,6 +817,7 @@ pub const cpu = struct {
790 .fuse_addis_load,817 .fuse_addis_load,
791 .htm,818 .htm,
792 .icbt,819 .icbt,
820 .isa_v207_instructions,
793 .isel,821 .isel,
794 .ldbrx,822 .ldbrx,
795 .lfiwax,823 .lfiwax,
...@@ -798,6 +826,7 @@ pub const cpu = struct {...@@ -798,6 +826,7 @@ pub const cpu = struct {
798 .popcntd,826 .popcntd,
799 .power8_vector,827 .power8_vector,
800 .predictable_select_expensive,828 .predictable_select_expensive,
829 .quadword_atomics,
801 .recipprec,830 .recipprec,
802 .stfiwx,831 .stfiwx,
803 .two_const_nr,832 .two_const_nr,
...@@ -837,6 +866,7 @@ pub const cpu = struct {...@@ -837,6 +866,7 @@ pub const cpu = struct {
837 .ppc_postra_sched,866 .ppc_postra_sched,
838 .ppc_prera_sched,867 .ppc_prera_sched,
839 .predictable_select_expensive,868 .predictable_select_expensive,
869 .quadword_atomics,
840 .recipprec,870 .recipprec,
841 .stfiwx,871 .stfiwx,
842 .two_const_nr,872 .two_const_nr,
...@@ -989,6 +1019,7 @@ pub const cpu = struct {...@@ -989,6 +1019,7 @@ pub const cpu = struct {
989 .fuse_addis_load,1019 .fuse_addis_load,
990 .htm,1020 .htm,
991 .icbt,1021 .icbt,
1022 .isa_v207_instructions,
992 .isel,1023 .isel,
993 .ldbrx,1024 .ldbrx,
994 .lfiwax,1025 .lfiwax,
...@@ -997,6 +1028,7 @@ pub const cpu = struct {...@@ -997,6 +1028,7 @@ pub const cpu = struct {
997 .popcntd,1028 .popcntd,
998 .power8_vector,1029 .power8_vector,
999 .predictable_select_expensive,1030 .predictable_select_expensive,
1031 .quadword_atomics,
1000 .recipprec,1032 .recipprec,
1001 .stfiwx,1033 .stfiwx,
1002 .two_const_nr,1034 .two_const_nr,
...@@ -1033,6 +1065,7 @@ pub const cpu = struct {...@@ -1033,6 +1065,7 @@ pub const cpu = struct {
1033 .ppc_postra_sched,1065 .ppc_postra_sched,
1034 .ppc_prera_sched,1066 .ppc_prera_sched,
1035 .predictable_select_expensive,1067 .predictable_select_expensive,
1068 .quadword_atomics,
1036 .recipprec,1069 .recipprec,
1037 .stfiwx,1070 .stfiwx,
1038 .two_const_nr,1071 .two_const_nr,
lib/std/target/riscv.zig+1-1
...@@ -185,7 +185,7 @@ pub const all_features = blk: {...@@ -185,7 +185,7 @@ pub const all_features = blk: {
185 };185 };
186 result[@enumToInt(Feature.experimental_zvamo)] = .{186 result[@enumToInt(Feature.experimental_zvamo)] = .{
187 .llvm_name = "experimental-zvamo",187 .llvm_name = "experimental-zvamo",
188 .description = "'Zvamo'(Vector AMO Operations)",188 .description = "'Zvamo' (Vector AMO Operations)",
189 .dependencies = featureSet(&[_]Feature{189 .dependencies = featureSet(&[_]Feature{
190 .experimental_v,190 .experimental_v,
191 }),191 }),
lib/std/target/systemz.zig+76
...@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;...@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
66
7pub const Feature = enum {7pub const Feature = enum {
8 bear_enhancement,
8 deflate_conversion,9 deflate_conversion,
9 dfp_packed_conversion,10 dfp_packed_conversion,
10 dfp_zoned_conversion,11 dfp_zoned_conversion,
...@@ -31,8 +32,11 @@ pub const Feature = enum {...@@ -31,8 +32,11 @@ pub const Feature = enum {
31 miscellaneous_extensions,32 miscellaneous_extensions,
32 miscellaneous_extensions_2,33 miscellaneous_extensions_2,
33 miscellaneous_extensions_3,34 miscellaneous_extensions_3,
35 nnp_assist,
34 population_count,36 population_count,
37 processor_activity_instrumentation,
35 processor_assist,38 processor_assist,
39 reset_dat_protection,
36 reset_reference_bits_multiple,40 reset_reference_bits_multiple,
37 soft_float,41 soft_float,
38 transactional_execution,42 transactional_execution,
...@@ -41,6 +45,7 @@ pub const Feature = enum {...@@ -41,6 +45,7 @@ pub const Feature = enum {
41 vector_enhancements_2,45 vector_enhancements_2,
42 vector_packed_decimal,46 vector_packed_decimal,
43 vector_packed_decimal_enhancement,47 vector_packed_decimal_enhancement,
48 vector_packed_decimal_enhancement_2,
44};49};
4550
46pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;51pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
...@@ -52,6 +57,11 @@ pub const all_features = blk: {...@@ -52,6 +57,11 @@ pub const all_features = blk: {
52 const len = @typeInfo(Feature).Enum.fields.len;57 const len = @typeInfo(Feature).Enum.fields.len;
53 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);58 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
54 var result: [len]CpuFeature = undefined;59 var result: [len]CpuFeature = undefined;
60 result[@enumToInt(Feature.bear_enhancement)] = .{
61 .llvm_name = "bear-enhancement",
62 .description = "Assume that the BEAR-enhancement facility is installed",
63 .dependencies = featureSet(&[_]Feature{}),
64 };
55 result[@enumToInt(Feature.deflate_conversion)] = .{65 result[@enumToInt(Feature.deflate_conversion)] = .{
56 .llvm_name = "deflate-conversion",66 .llvm_name = "deflate-conversion",
57 .description = "Assume that the deflate-conversion facility is installed",67 .description = "Assume that the deflate-conversion facility is installed",
...@@ -182,16 +192,31 @@ pub const all_features = blk: {...@@ -182,16 +192,31 @@ pub const all_features = blk: {
182 .description = "Assume that the miscellaneous-extensions facility 3 is installed",192 .description = "Assume that the miscellaneous-extensions facility 3 is installed",
183 .dependencies = featureSet(&[_]Feature{}),193 .dependencies = featureSet(&[_]Feature{}),
184 };194 };
195 result[@enumToInt(Feature.nnp_assist)] = .{
196 .llvm_name = "nnp-assist",
197 .description = "Assume that the NNP-assist facility is installed",
198 .dependencies = featureSet(&[_]Feature{}),
199 };
185 result[@enumToInt(Feature.population_count)] = .{200 result[@enumToInt(Feature.population_count)] = .{
186 .llvm_name = "population-count",201 .llvm_name = "population-count",
187 .description = "Assume that the population-count facility is installed",202 .description = "Assume that the population-count facility is installed",
188 .dependencies = featureSet(&[_]Feature{}),203 .dependencies = featureSet(&[_]Feature{}),
189 };204 };
205 result[@enumToInt(Feature.processor_activity_instrumentation)] = .{
206 .llvm_name = "processor-activity-instrumentation",
207 .description = "Assume that the processor-activity-instrumentation facility is installed",
208 .dependencies = featureSet(&[_]Feature{}),
209 };
190 result[@enumToInt(Feature.processor_assist)] = .{210 result[@enumToInt(Feature.processor_assist)] = .{
191 .llvm_name = "processor-assist",211 .llvm_name = "processor-assist",
192 .description = "Assume that the processor-assist facility is installed",212 .description = "Assume that the processor-assist facility is installed",
193 .dependencies = featureSet(&[_]Feature{}),213 .dependencies = featureSet(&[_]Feature{}),
194 };214 };
215 result[@enumToInt(Feature.reset_dat_protection)] = .{
216 .llvm_name = "reset-dat-protection",
217 .description = "Assume that the reset-DAT-protection facility is installed",
218 .dependencies = featureSet(&[_]Feature{}),
219 };
195 result[@enumToInt(Feature.reset_reference_bits_multiple)] = .{220 result[@enumToInt(Feature.reset_reference_bits_multiple)] = .{
196 .llvm_name = "reset-reference-bits-multiple",221 .llvm_name = "reset-reference-bits-multiple",
197 .description = "Assume that the reset-reference-bits-multiple facility is installed",222 .description = "Assume that the reset-reference-bits-multiple facility is installed",
...@@ -232,6 +257,11 @@ pub const all_features = blk: {...@@ -232,6 +257,11 @@ pub const all_features = blk: {
232 .description = "Assume that the vector packed decimal enhancement facility is installed",257 .description = "Assume that the vector packed decimal enhancement facility is installed",
233 .dependencies = featureSet(&[_]Feature{}),258 .dependencies = featureSet(&[_]Feature{}),
234 };259 };
260 result[@enumToInt(Feature.vector_packed_decimal_enhancement_2)] = .{
261 .llvm_name = "vector-packed-decimal-enhancement-2",
262 .description = "Assume that the vector packed decimal enhancement facility 2 is installed",
263 .dependencies = featureSet(&[_]Feature{}),
264 };
235 const ti = @typeInfo(Feature);265 const ti = @typeInfo(Feature);
236 for (result) |*elem, i| {266 for (result) |*elem, i| {
237 elem.index = i;267 elem.index = i;
...@@ -368,6 +398,52 @@ pub const cpu = struct {...@@ -368,6 +398,52 @@ pub const cpu = struct {
368 .vector_packed_decimal_enhancement,398 .vector_packed_decimal_enhancement,
369 }),399 }),
370 };400 };
401 pub const arch14 = CpuModel{
402 .name = "arch14",
403 .llvm_name = "arch14",
404 .features = featureSet(&[_]Feature{
405 .bear_enhancement,
406 .deflate_conversion,
407 .dfp_packed_conversion,
408 .dfp_zoned_conversion,
409 .distinct_ops,
410 .enhanced_dat_2,
411 .enhanced_sort,
412 .execution_hint,
413 .fast_serialization,
414 .fp_extension,
415 .guarded_storage,
416 .high_word,
417 .insert_reference_bits_multiple,
418 .interlocked_access1,
419 .load_and_trap,
420 .load_and_zero_rightmost_byte,
421 .load_store_on_cond,
422 .load_store_on_cond_2,
423 .message_security_assist_extension3,
424 .message_security_assist_extension4,
425 .message_security_assist_extension5,
426 .message_security_assist_extension7,
427 .message_security_assist_extension8,
428 .message_security_assist_extension9,
429 .miscellaneous_extensions,
430 .miscellaneous_extensions_2,
431 .miscellaneous_extensions_3,
432 .nnp_assist,
433 .population_count,
434 .processor_activity_instrumentation,
435 .processor_assist,
436 .reset_dat_protection,
437 .reset_reference_bits_multiple,
438 .transactional_execution,
439 .vector,
440 .vector_enhancements_1,
441 .vector_enhancements_2,
442 .vector_packed_decimal,
443 .vector_packed_decimal_enhancement,
444 .vector_packed_decimal_enhancement_2,
445 }),
446 };
371 pub const arch8 = CpuModel{447 pub const arch8 = CpuModel{
372 .name = "arch8",448 .name = "arch8",
373 .llvm_name = "arch8",449 .llvm_name = "arch8",
lib/std/target/wasm.zig-8
...@@ -15,7 +15,6 @@ pub const Feature = enum {...@@ -15,7 +15,6 @@ pub const Feature = enum {
15 sign_ext,15 sign_ext,
16 simd128,16 simd128,
17 tail_call,17 tail_call,
18 unimplemented_simd128,
19};18};
2019
21pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;20pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
...@@ -77,13 +76,6 @@ pub const all_features = blk: {...@@ -77,13 +76,6 @@ pub const all_features = blk: {
77 .description = "Enable tail call instructions",76 .description = "Enable tail call instructions",
78 .dependencies = featureSet(&[_]Feature{}),77 .dependencies = featureSet(&[_]Feature{}),
79 };78 };
80 result[@enumToInt(Feature.unimplemented_simd128)] = .{
81 .llvm_name = "unimplemented-simd128",
82 .description = "Enable 128-bit SIMD not yet implemented in engines",
83 .dependencies = featureSet(&[_]Feature{
84 .simd128,
85 }),
86 };
87 const ti = @typeInfo(Feature);79 const ti = @typeInfo(Feature);
88 for (result) |*elem, i| {80 for (result) |*elem, i| {
89 elem.index = i;81 elem.index = i;
lib/std/target/x86.zig+134-33
...@@ -55,10 +55,12 @@ pub const Feature = enum {...@@ -55,10 +55,12 @@ pub const Feature = enum {
55 fast_gather,55 fast_gather,
56 fast_hops,56 fast_hops,
57 fast_lzcnt,57 fast_lzcnt,
58 fast_movbe,
58 fast_scalar_fsqrt,59 fast_scalar_fsqrt,
59 fast_scalar_shift_masks,60 fast_scalar_shift_masks,
60 fast_shld_rotate,61 fast_shld_rotate,
61 fast_variable_shuffle,62 fast_variable_crosslane_shuffle,
63 fast_variable_perlane_shuffle,
62 fast_vector_fsqrt,64 fast_vector_fsqrt,
63 fast_vector_shift_masks,65 fast_vector_shift_masks,
64 fma,66 fma,
...@@ -458,6 +460,11 @@ pub const all_features = blk: {...@@ -458,6 +460,11 @@ pub const all_features = blk: {
458 .description = "LZCNT instructions are as fast as most simple integer ops",460 .description = "LZCNT instructions are as fast as most simple integer ops",
459 .dependencies = featureSet(&[_]Feature{}),461 .dependencies = featureSet(&[_]Feature{}),
460 };462 };
463 result[@enumToInt(Feature.fast_movbe)] = .{
464 .llvm_name = "fast-movbe",
465 .description = "Prefer a movbe over a single-use load + bswap / single-use bswap + store",
466 .dependencies = featureSet(&[_]Feature{}),
467 };
461 result[@enumToInt(Feature.fast_scalar_fsqrt)] = .{468 result[@enumToInt(Feature.fast_scalar_fsqrt)] = .{
462 .llvm_name = "fast-scalar-fsqrt",469 .llvm_name = "fast-scalar-fsqrt",
463 .description = "Scalar SQRT is fast (disable Newton-Raphson)",470 .description = "Scalar SQRT is fast (disable Newton-Raphson)",
...@@ -473,9 +480,14 @@ pub const all_features = blk: {...@@ -473,9 +480,14 @@ pub const all_features = blk: {
473 .description = "SHLD can be used as a faster rotate",480 .description = "SHLD can be used as a faster rotate",
474 .dependencies = featureSet(&[_]Feature{}),481 .dependencies = featureSet(&[_]Feature{}),
475 };482 };
476 result[@enumToInt(Feature.fast_variable_shuffle)] = .{483 result[@enumToInt(Feature.fast_variable_crosslane_shuffle)] = .{
477 .llvm_name = "fast-variable-shuffle",484 .llvm_name = "fast-variable-crosslane-shuffle",
478 .description = "Shuffles with variable masks are fast",485 .description = "Cross-lane shuffles with variable masks are fast",
486 .dependencies = featureSet(&[_]Feature{}),
487 };
488 result[@enumToInt(Feature.fast_variable_perlane_shuffle)] = .{
489 .llvm_name = "fast-variable-perlane-shuffle",
490 .description = "Per-lane shuffles with variable masks are fast",
479 .dependencies = featureSet(&[_]Feature{}),491 .dependencies = featureSet(&[_]Feature{}),
480 };492 };
481 result[@enumToInt(Feature.fast_vector_fsqrt)] = .{493 result[@enumToInt(Feature.fast_vector_fsqrt)] = .{
...@@ -1010,26 +1022,27 @@ pub const cpu = struct {...@@ -1010,26 +1022,27 @@ pub const cpu = struct {
1010 .features = featureSet(&[_]Feature{1022 .features = featureSet(&[_]Feature{
1011 .@"64bit",1023 .@"64bit",
1012 .adx,1024 .adx,
1013 .aes,
1014 .avxvnni,1025 .avxvnni,
1015 .bmi,1026 .bmi,
1016 .bmi2,1027 .bmi2,
1017 .cldemote,1028 .cldemote,
1018 .clflushopt,1029 .clflushopt,
1030 .clwb,
1019 .cmov,1031 .cmov,
1020 .cx16,1032 .cx16,
1021 .ermsb,
1022 .f16c,1033 .f16c,
1023 .false_deps_popcnt,1034 .false_deps_popcnt,
1024 .fast_15bytenop,1035 .fast_15bytenop,
1025 .fast_gather,1036 .fast_gather,
1026 .fast_scalar_fsqrt,1037 .fast_scalar_fsqrt,
1027 .fast_shld_rotate,1038 .fast_shld_rotate,
1028 .fast_variable_shuffle,1039 .fast_variable_crosslane_shuffle,
1040 .fast_variable_perlane_shuffle,
1029 .fast_vector_fsqrt,1041 .fast_vector_fsqrt,
1030 .fma,1042 .fma,
1031 .fsgsbase,1043 .fsgsbase,
1032 .fxsr,1044 .fxsr,
1045 .gfni,
1033 .hreset,1046 .hreset,
1034 .idivq_to_divl,1047 .idivq_to_divl,
1035 .invpcid,1048 .invpcid,
...@@ -1037,19 +1050,27 @@ pub const cpu = struct {...@@ -1037,19 +1050,27 @@ pub const cpu = struct {
1037 .macrofusion,1050 .macrofusion,
1038 .mmx,1051 .mmx,
1039 .movbe,1052 .movbe,
1053 .movdir64b,
1054 .movdiri,
1040 .nopl,1055 .nopl,
1041 .pclmul,1056 .pconfig,
1057 .pku,
1042 .popcnt,1058 .popcnt,
1043 .prfchw,1059 .prfchw,
1044 .ptwrite,1060 .ptwrite,
1061 .rdpid,
1045 .rdrnd,1062 .rdrnd,
1046 .rdseed,1063 .rdseed,
1047 .sahf,1064 .sahf,
1048 .serialize,1065 .serialize,
1049 .sgx,1066 .sha,
1067 .shstk,
1050 .slow_3ops_lea,1068 .slow_3ops_lea,
1069 .vaes,
1070 .vpclmulqdq,
1051 .vzeroupper,1071 .vzeroupper,
1052 .waitpkg,1072 .waitpkg,
1073 .widekl,
1053 .x87,1074 .x87,
1054 .xsavec,1075 .xsavec,
1055 .xsaveopt,1076 .xsaveopt,
...@@ -1292,6 +1313,7 @@ pub const cpu = struct {...@@ -1292,6 +1313,7 @@ pub const cpu = struct {
1292 .f16c,1313 .f16c,
1293 .fast_11bytenop,1314 .fast_11bytenop,
1294 .fast_bextr,1315 .fast_bextr,
1316 .fast_movbe,
1295 .fast_scalar_shift_masks,1317 .fast_scalar_shift_masks,
1296 .fma,1318 .fma,
1297 .fxsr,1319 .fxsr,
...@@ -1324,6 +1346,7 @@ pub const cpu = struct {...@@ -1324,6 +1346,7 @@ pub const cpu = struct {
1324 .f16c,1346 .f16c,
1325 .fast_11bytenop,1347 .fast_11bytenop,
1326 .fast_bextr,1348 .fast_bextr,
1349 .fast_movbe,
1327 .fast_scalar_shift_masks,1350 .fast_scalar_shift_masks,
1328 .fma,1351 .fma,
1329 .fsgsbase,1352 .fsgsbase,
...@@ -1359,6 +1382,7 @@ pub const cpu = struct {...@@ -1359,6 +1382,7 @@ pub const cpu = struct {
1359 .f16c,1382 .f16c,
1360 .fast_11bytenop,1383 .fast_11bytenop,
1361 .fast_bextr,1384 .fast_bextr,
1385 .fast_movbe,
1362 .fast_scalar_shift_masks,1386 .fast_scalar_shift_masks,
1363 .fma,1387 .fma,
1364 .fsgsbase,1388 .fsgsbase,
...@@ -1424,7 +1448,8 @@ pub const cpu = struct {...@@ -1424,7 +1448,8 @@ pub const cpu = struct {
1424 .fast_15bytenop,1448 .fast_15bytenop,
1425 .fast_scalar_fsqrt,1449 .fast_scalar_fsqrt,
1426 .fast_shld_rotate,1450 .fast_shld_rotate,
1427 .fast_variable_shuffle,1451 .fast_variable_crosslane_shuffle,
1452 .fast_variable_perlane_shuffle,
1428 .fma,1453 .fma,
1429 .fsgsbase,1454 .fsgsbase,
1430 .fxsr,1455 .fxsr,
...@@ -1485,6 +1510,7 @@ pub const cpu = struct {...@@ -1485,6 +1510,7 @@ pub const cpu = struct {
1485 .fast_bextr,1510 .fast_bextr,
1486 .fast_hops,1511 .fast_hops,
1487 .fast_lzcnt,1512 .fast_lzcnt,
1513 .fast_movbe,
1488 .fast_scalar_shift_masks,1514 .fast_scalar_shift_masks,
1489 .fast_vector_shift_masks,1515 .fast_vector_shift_masks,
1490 .fxsr,1516 .fxsr,
...@@ -1548,7 +1574,8 @@ pub const cpu = struct {...@@ -1548,7 +1574,8 @@ pub const cpu = struct {
1548 .fast_gather,1574 .fast_gather,
1549 .fast_scalar_fsqrt,1575 .fast_scalar_fsqrt,
1550 .fast_shld_rotate,1576 .fast_shld_rotate,
1551 .fast_variable_shuffle,1577 .fast_variable_crosslane_shuffle,
1578 .fast_variable_perlane_shuffle,
1552 .fast_vector_fsqrt,1579 .fast_vector_fsqrt,
1553 .fsgsbase,1580 .fsgsbase,
1554 .fxsr,1581 .fxsr,
...@@ -1567,7 +1594,6 @@ pub const cpu = struct {...@@ -1567,7 +1594,6 @@ pub const cpu = struct {
1567 .rdrnd,1594 .rdrnd,
1568 .rdseed,1595 .rdseed,
1569 .sahf,1596 .sahf,
1570 .sgx,
1571 .sha,1597 .sha,
1572 .slow_3ops_lea,1598 .slow_3ops_lea,
1573 .vzeroupper,1599 .vzeroupper,
...@@ -1601,7 +1627,8 @@ pub const cpu = struct {...@@ -1601,7 +1627,8 @@ pub const cpu = struct {
1601 .fast_gather,1627 .fast_gather,
1602 .fast_scalar_fsqrt,1628 .fast_scalar_fsqrt,
1603 .fast_shld_rotate,1629 .fast_shld_rotate,
1604 .fast_variable_shuffle,1630 .fast_variable_crosslane_shuffle,
1631 .fast_variable_perlane_shuffle,
1605 .fast_vector_fsqrt,1632 .fast_vector_fsqrt,
1606 .fsgsbase,1633 .fsgsbase,
1607 .fxsr,1634 .fxsr,
...@@ -1652,7 +1679,8 @@ pub const cpu = struct {...@@ -1652,7 +1679,8 @@ pub const cpu = struct {
1652 .fast_gather,1679 .fast_gather,
1653 .fast_scalar_fsqrt,1680 .fast_scalar_fsqrt,
1654 .fast_shld_rotate,1681 .fast_shld_rotate,
1655 .fast_variable_shuffle,1682 .fast_variable_crosslane_shuffle,
1683 .fast_variable_perlane_shuffle,
1656 .fast_vector_fsqrt,1684 .fast_vector_fsqrt,
1657 .fsgsbase,1685 .fsgsbase,
1658 .fxsr,1686 .fxsr,
...@@ -1714,7 +1742,8 @@ pub const cpu = struct {...@@ -1714,7 +1742,8 @@ pub const cpu = struct {
1714 .fast_15bytenop,1742 .fast_15bytenop,
1715 .fast_scalar_fsqrt,1743 .fast_scalar_fsqrt,
1716 .fast_shld_rotate,1744 .fast_shld_rotate,
1717 .fast_variable_shuffle,1745 .fast_variable_crosslane_shuffle,
1746 .fast_variable_perlane_shuffle,
1718 .fma,1747 .fma,
1719 .fsgsbase,1748 .fsgsbase,
1720 .fxsr,1749 .fxsr,
...@@ -1844,6 +1873,7 @@ pub const cpu = struct {...@@ -1844,6 +1873,7 @@ pub const cpu = struct {
1844 .cmov,1873 .cmov,
1845 .cx16,1874 .cx16,
1846 .false_deps_popcnt,1875 .false_deps_popcnt,
1876 .fast_movbe,
1847 .fsgsbase,1877 .fsgsbase,
1848 .fxsr,1878 .fxsr,
1849 .mmx,1879 .mmx,
...@@ -1877,6 +1907,7 @@ pub const cpu = struct {...@@ -1877,6 +1907,7 @@ pub const cpu = struct {
1877 .clflushopt,1907 .clflushopt,
1878 .cmov,1908 .cmov,
1879 .cx16,1909 .cx16,
1910 .fast_movbe,
1880 .fsgsbase,1911 .fsgsbase,
1881 .fxsr,1912 .fxsr,
1882 .mmx,1913 .mmx,
...@@ -1890,7 +1921,6 @@ pub const cpu = struct {...@@ -1890,7 +1921,6 @@ pub const cpu = struct {
1890 .rdrnd,1921 .rdrnd,
1891 .rdseed,1922 .rdseed,
1892 .sahf,1923 .sahf,
1893 .sgx,
1894 .sha,1924 .sha,
1895 .slow_incdec,1925 .slow_incdec,
1896 .slow_lea,1926 .slow_lea,
...@@ -1921,7 +1951,8 @@ pub const cpu = struct {...@@ -1921,7 +1951,8 @@ pub const cpu = struct {
1921 .fast_15bytenop,1951 .fast_15bytenop,
1922 .fast_scalar_fsqrt,1952 .fast_scalar_fsqrt,
1923 .fast_shld_rotate,1953 .fast_shld_rotate,
1924 .fast_variable_shuffle,1954 .fast_variable_crosslane_shuffle,
1955 .fast_variable_perlane_shuffle,
1925 .fma,1956 .fma,
1926 .fsgsbase,1957 .fsgsbase,
1927 .fxsr,1958 .fxsr,
...@@ -1960,7 +1991,6 @@ pub const cpu = struct {...@@ -1960,7 +1991,6 @@ pub const cpu = struct {
1960 .bmi,1991 .bmi,
1961 .bmi2,1992 .bmi2,
1962 .clflushopt,1993 .clflushopt,
1963 .clwb,
1964 .cmov,1994 .cmov,
1965 .cx16,1995 .cx16,
1966 .ermsb,1996 .ermsb,
...@@ -1968,7 +1998,8 @@ pub const cpu = struct {...@@ -1968,7 +1998,8 @@ pub const cpu = struct {
1968 .fast_gather,1998 .fast_gather,
1969 .fast_scalar_fsqrt,1999 .fast_scalar_fsqrt,
1970 .fast_shld_rotate,2000 .fast_shld_rotate,
1971 .fast_variable_shuffle,2001 .fast_variable_crosslane_shuffle,
2002 .fast_variable_perlane_shuffle,
1972 .fast_vector_fsqrt,2003 .fast_vector_fsqrt,
1973 .fsgsbase,2004 .fsgsbase,
1974 .fsrm,2005 .fsrm,
...@@ -1989,7 +2020,6 @@ pub const cpu = struct {...@@ -1989,7 +2020,6 @@ pub const cpu = struct {
1989 .rdrnd,2020 .rdrnd,
1990 .rdseed,2021 .rdseed,
1991 .sahf,2022 .sahf,
1992 .sgx,
1993 .sha,2023 .sha,
1994 .slow_3ops_lea,2024 .slow_3ops_lea,
1995 .vaes,2025 .vaes,
...@@ -2027,7 +2057,8 @@ pub const cpu = struct {...@@ -2027,7 +2057,8 @@ pub const cpu = struct {
2027 .fast_gather,2057 .fast_gather,
2028 .fast_scalar_fsqrt,2058 .fast_scalar_fsqrt,
2029 .fast_shld_rotate,2059 .fast_shld_rotate,
2030 .fast_variable_shuffle,2060 .fast_variable_crosslane_shuffle,
2061 .fast_variable_perlane_shuffle,
2031 .fast_vector_fsqrt,2062 .fast_vector_fsqrt,
2032 .fsgsbase,2063 .fsgsbase,
2033 .fsrm,2064 .fsrm,
...@@ -2049,7 +2080,6 @@ pub const cpu = struct {...@@ -2049,7 +2080,6 @@ pub const cpu = struct {
2049 .rdrnd,2080 .rdrnd,
2050 .rdseed,2081 .rdseed,
2051 .sahf,2082 .sahf,
2052 .sgx,
2053 .sha,2083 .sha,
2054 .slow_3ops_lea,2084 .slow_3ops_lea,
2055 .vaes,2085 .vaes,
...@@ -2175,6 +2205,7 @@ pub const cpu = struct {...@@ -2175,6 +2205,7 @@ pub const cpu = struct {
2175 .cmov,2205 .cmov,
2176 .cx16,2206 .cx16,
2177 .fast_gather,2207 .fast_gather,
2208 .fast_movbe,
2178 .fsgsbase,2209 .fsgsbase,
2179 .fxsr,2210 .fxsr,
2180 .idivq_to_divl,2211 .idivq_to_divl,
...@@ -2214,6 +2245,7 @@ pub const cpu = struct {...@@ -2214,6 +2245,7 @@ pub const cpu = struct {
2214 .cmov,2245 .cmov,
2215 .cx16,2246 .cx16,
2216 .fast_gather,2247 .fast_gather,
2248 .fast_movbe,
2217 .fsgsbase,2249 .fsgsbase,
2218 .fxsr,2250 .fxsr,
2219 .idivq_to_divl,2251 .idivq_to_divl,
...@@ -2472,6 +2504,64 @@ pub const cpu = struct {...@@ -2472,6 +2504,64 @@ pub const cpu = struct {
2472 .x87,2504 .x87,
2473 }),2505 }),
2474 };2506 };
2507 pub const rocketlake = CpuModel{
2508 .name = "rocketlake",
2509 .llvm_name = "rocketlake",
2510 .features = featureSet(&[_]Feature{
2511 .@"64bit",
2512 .adx,
2513 .avx512bitalg,
2514 .avx512cd,
2515 .avx512dq,
2516 .avx512ifma,
2517 .avx512vbmi,
2518 .avx512vbmi2,
2519 .avx512vl,
2520 .avx512vnni,
2521 .avx512vpopcntdq,
2522 .bmi,
2523 .bmi2,
2524 .clflushopt,
2525 .cmov,
2526 .cx16,
2527 .ermsb,
2528 .fast_15bytenop,
2529 .fast_gather,
2530 .fast_scalar_fsqrt,
2531 .fast_shld_rotate,
2532 .fast_variable_crosslane_shuffle,
2533 .fast_variable_perlane_shuffle,
2534 .fast_vector_fsqrt,
2535 .fsgsbase,
2536 .fsrm,
2537 .fxsr,
2538 .gfni,
2539 .idivq_to_divl,
2540 .invpcid,
2541 .lzcnt,
2542 .macrofusion,
2543 .mmx,
2544 .movbe,
2545 .nopl,
2546 .pku,
2547 .popcnt,
2548 .prefer_256_bit,
2549 .prfchw,
2550 .rdpid,
2551 .rdrnd,
2552 .rdseed,
2553 .sahf,
2554 .sha,
2555 .slow_3ops_lea,
2556 .vaes,
2557 .vpclmulqdq,
2558 .vzeroupper,
2559 .x87,
2560 .xsavec,
2561 .xsaveopt,
2562 .xsaves,
2563 }),
2564 };
2475 pub const sandybridge = CpuModel{2565 pub const sandybridge = CpuModel{
2476 .name = "sandybridge",2566 .name = "sandybridge",
2477 .llvm_name = "sandybridge",2567 .llvm_name = "sandybridge",
...@@ -2532,7 +2622,8 @@ pub const cpu = struct {...@@ -2532,7 +2622,8 @@ pub const cpu = struct {
2532 .fast_gather,2622 .fast_gather,
2533 .fast_scalar_fsqrt,2623 .fast_scalar_fsqrt,
2534 .fast_shld_rotate,2624 .fast_shld_rotate,
2535 .fast_variable_shuffle,2625 .fast_variable_crosslane_shuffle,
2626 .fast_variable_perlane_shuffle,
2536 .fast_vector_fsqrt,2627 .fast_vector_fsqrt,
2537 .fsgsbase,2628 .fsgsbase,
2538 .fsrm,2629 .fsrm,
...@@ -2558,7 +2649,6 @@ pub const cpu = struct {...@@ -2558,7 +2649,6 @@ pub const cpu = struct {
2558 .rdseed,2649 .rdseed,
2559 .sahf,2650 .sahf,
2560 .serialize,2651 .serialize,
2561 .sgx,
2562 .sha,2652 .sha,
2563 .shstk,2653 .shstk,
2564 .slow_3ops_lea,2654 .slow_3ops_lea,
...@@ -2584,6 +2674,7 @@ pub const cpu = struct {...@@ -2584,6 +2674,7 @@ pub const cpu = struct {
2584 .cx16,2674 .cx16,
2585 .false_deps_popcnt,2675 .false_deps_popcnt,
2586 .fast_7bytenop,2676 .fast_7bytenop,
2677 .fast_movbe,
2587 .fxsr,2678 .fxsr,
2588 .idivq_to_divl,2679 .idivq_to_divl,
2589 .mmx,2680 .mmx,
...@@ -2626,7 +2717,8 @@ pub const cpu = struct {...@@ -2626,7 +2717,8 @@ pub const cpu = struct {
2626 .fast_gather,2717 .fast_gather,
2627 .fast_scalar_fsqrt,2718 .fast_scalar_fsqrt,
2628 .fast_shld_rotate,2719 .fast_shld_rotate,
2629 .fast_variable_shuffle,2720 .fast_variable_crosslane_shuffle,
2721 .fast_variable_perlane_shuffle,
2630 .fast_vector_fsqrt,2722 .fast_vector_fsqrt,
2631 .fsgsbase,2723 .fsgsbase,
2632 .fxsr,2724 .fxsr,
...@@ -2673,7 +2765,8 @@ pub const cpu = struct {...@@ -2673,7 +2765,8 @@ pub const cpu = struct {
2673 .fast_gather,2765 .fast_gather,
2674 .fast_scalar_fsqrt,2766 .fast_scalar_fsqrt,
2675 .fast_shld_rotate,2767 .fast_shld_rotate,
2676 .fast_variable_shuffle,2768 .fast_variable_crosslane_shuffle,
2769 .fast_variable_perlane_shuffle,
2677 .fast_vector_fsqrt,2770 .fast_vector_fsqrt,
2678 .fma,2771 .fma,
2679 .fsgsbase,2772 .fsgsbase,
...@@ -2691,7 +2784,6 @@ pub const cpu = struct {...@@ -2691,7 +2784,6 @@ pub const cpu = struct {
2691 .rdrnd,2784 .rdrnd,
2692 .rdseed,2785 .rdseed,
2693 .sahf,2786 .sahf,
2694 .sgx,
2695 .slow_3ops_lea,2787 .slow_3ops_lea,
2696 .vzeroupper,2788 .vzeroupper,
2697 .x87,2789 .x87,
...@@ -2723,7 +2815,8 @@ pub const cpu = struct {...@@ -2723,7 +2815,8 @@ pub const cpu = struct {
2723 .fast_gather,2815 .fast_gather,
2724 .fast_scalar_fsqrt,2816 .fast_scalar_fsqrt,
2725 .fast_shld_rotate,2817 .fast_shld_rotate,
2726 .fast_variable_shuffle,2818 .fast_variable_crosslane_shuffle,
2819 .fast_variable_perlane_shuffle,
2727 .fast_vector_fsqrt,2820 .fast_vector_fsqrt,
2728 .fsgsbase,2821 .fsgsbase,
2729 .fxsr,2822 .fxsr,
...@@ -2759,6 +2852,7 @@ pub const cpu = struct {...@@ -2759,6 +2852,7 @@ pub const cpu = struct {
2759 .cx16,2852 .cx16,
2760 .false_deps_popcnt,2853 .false_deps_popcnt,
2761 .fast_7bytenop,2854 .fast_7bytenop,
2855 .fast_movbe,
2762 .fxsr,2856 .fxsr,
2763 .idivq_to_divl,2857 .idivq_to_divl,
2764 .mmx,2858 .mmx,
...@@ -2805,7 +2899,8 @@ pub const cpu = struct {...@@ -2805,7 +2899,8 @@ pub const cpu = struct {
2805 .fast_gather,2899 .fast_gather,
2806 .fast_scalar_fsqrt,2900 .fast_scalar_fsqrt,
2807 .fast_shld_rotate,2901 .fast_shld_rotate,
2808 .fast_variable_shuffle,2902 .fast_variable_crosslane_shuffle,
2903 .fast_variable_perlane_shuffle,
2809 .fast_vector_fsqrt,2904 .fast_vector_fsqrt,
2810 .fsgsbase,2905 .fsgsbase,
2811 .fsrm,2906 .fsrm,
...@@ -2828,7 +2923,6 @@ pub const cpu = struct {...@@ -2828,7 +2923,6 @@ pub const cpu = struct {
2828 .rdrnd,2923 .rdrnd,
2829 .rdseed,2924 .rdseed,
2830 .sahf,2925 .sahf,
2831 .sgx,
2832 .sha,2926 .sha,
2833 .shstk,2927 .shstk,
2834 .slow_3ops_lea,2928 .slow_3ops_lea,
...@@ -2851,6 +2945,7 @@ pub const cpu = struct {...@@ -2851,6 +2945,7 @@ pub const cpu = struct {
2851 .clwb,2945 .clwb,
2852 .cmov,2946 .cmov,
2853 .cx16,2947 .cx16,
2948 .fast_movbe,
2854 .fsgsbase,2949 .fsgsbase,
2855 .fxsr,2950 .fxsr,
2856 .gfni,2951 .gfni,
...@@ -2865,7 +2960,6 @@ pub const cpu = struct {...@@ -2865,7 +2960,6 @@ pub const cpu = struct {
2865 .rdrnd,2960 .rdrnd,
2866 .rdseed,2961 .rdseed,
2867 .sahf,2962 .sahf,
2868 .sgx,
2869 .sha,2963 .sha,
2870 .slow_incdec,2964 .slow_incdec,
2871 .slow_lea,2965 .slow_lea,
...@@ -2978,7 +3072,8 @@ pub const cpu = struct {...@@ -2978,7 +3072,8 @@ pub const cpu = struct {
2978 .fast_15bytenop,3072 .fast_15bytenop,
2979 .fast_scalar_fsqrt,3073 .fast_scalar_fsqrt,
2980 .fast_shld_rotate,3074 .fast_shld_rotate,
2981 .fast_variable_shuffle,3075 .fast_variable_crosslane_shuffle,
3076 .fast_variable_perlane_shuffle,
2982 .fma,3077 .fma,
2983 .fxsr,3078 .fxsr,
2984 .idivq_to_divl,3079 .idivq_to_divl,
...@@ -3013,7 +3108,8 @@ pub const cpu = struct {...@@ -3013,7 +3108,8 @@ pub const cpu = struct {
3013 .fast_gather,3108 .fast_gather,
3014 .fast_scalar_fsqrt,3109 .fast_scalar_fsqrt,
3015 .fast_shld_rotate,3110 .fast_shld_rotate,
3016 .fast_variable_shuffle,3111 .fast_variable_crosslane_shuffle,
3112 .fast_variable_perlane_shuffle,
3017 .fast_vector_fsqrt,3113 .fast_vector_fsqrt,
3018 .fxsr,3114 .fxsr,
3019 .idivq_to_divl,3115 .idivq_to_divl,
...@@ -3065,6 +3161,7 @@ pub const cpu = struct {...@@ -3065,6 +3161,7 @@ pub const cpu = struct {
3065 .fast_15bytenop,3161 .fast_15bytenop,
3066 .fast_bextr,3162 .fast_bextr,
3067 .fast_lzcnt,3163 .fast_lzcnt,
3164 .fast_movbe,
3068 .fast_scalar_shift_masks,3165 .fast_scalar_shift_masks,
3069 .fma,3166 .fma,
3070 .fsgsbase,3167 .fsgsbase,
...@@ -3110,6 +3207,7 @@ pub const cpu = struct {...@@ -3110,6 +3207,7 @@ pub const cpu = struct {
3110 .fast_15bytenop,3207 .fast_15bytenop,
3111 .fast_bextr,3208 .fast_bextr,
3112 .fast_lzcnt,3209 .fast_lzcnt,
3210 .fast_movbe,
3113 .fast_scalar_shift_masks,3211 .fast_scalar_shift_masks,
3114 .fma,3212 .fma,
3115 .fsgsbase,3213 .fsgsbase,
...@@ -3156,13 +3254,16 @@ pub const cpu = struct {...@@ -3156,13 +3254,16 @@ pub const cpu = struct {
3156 .fast_15bytenop,3254 .fast_15bytenop,
3157 .fast_bextr,3255 .fast_bextr,
3158 .fast_lzcnt,3256 .fast_lzcnt,
3257 .fast_movbe,
3159 .fast_scalar_shift_masks,3258 .fast_scalar_shift_masks,
3259 .fast_variable_perlane_shuffle,
3160 .fma,3260 .fma,
3161 .fsgsbase,3261 .fsgsbase,
3162 .fsrm,3262 .fsrm,
3163 .fxsr,3263 .fxsr,
3164 .invpcid,3264 .invpcid,
3165 .lzcnt,3265 .lzcnt,
3266 .macrofusion,
3166 .mmx,3267 .mmx,
3167 .movbe,3268 .movbe,
3168 .mwaitx,3269 .mwaitx,
tools/update_cpu_features.zig-2
...@@ -219,7 +219,6 @@ const llvm_targets = [_]LlvmTarget{...@@ -219,7 +219,6 @@ const llvm_targets = [_]LlvmTarget{
219 "use_postra_scheduler",219 "use_postra_scheduler",
220 "use_reciprocal_square_root",220 "use_reciprocal_square_root",
221 "v8a",221 "v8a",
222 "zcz_fp",
223 },222 },
224 },223 },
225 .{224 .{
...@@ -236,7 +235,6 @@ const llvm_targets = [_]LlvmTarget{...@@ -236,7 +235,6 @@ const llvm_targets = [_]LlvmTarget{
236 "slow_paired_128",235 "slow_paired_128",
237 "use_postra_scheduler",236 "use_postra_scheduler",
238 "v8a",237 "v8a",
239 "zcz_fp",
240 },238 },
241 },239 },
242 .{240 .{