authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-08-15 23:09:55-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-08-15 23:09:55-07:00
log7adf15682ca263c7d4e0e5306517f22272310294
tree7e9846e9389d883fa4035f9abdfd5e331968e635
parentd6467dcf71c40d4f09993f8c449b33adeca55ce5

update target CPU features with LLVM 13 rc1 data

13 files changed, 720 insertions(+), 80 deletions(-)

lib/std/target.zig+1
......@@ -430,6 +430,7 @@ pub const Target = struct {
430430 };
431431
432432 pub const aarch64 = @import("target/aarch64.zig");
433 pub const arc = @import("target/arc.zig");
433434 pub const amdgpu = @import("target/amdgpu.zig");
434435 pub const arm = @import("target/arm.zig");
435436 pub const avr = @import("target/avr.zig");
lib/std/target/aarch64.zig+107-19
......@@ -65,6 +65,7 @@ pub const Feature = enum {
6565 fuse_csel,
6666 fuse_literals,
6767 harden_sls_blr,
68 harden_sls_nocomdat,
6869 harden_sls_retbr,
6970 hcx,
7071 i8mm,
......@@ -81,6 +82,7 @@ pub const Feature = enum {
8182 neoverse_n2,
8283 neoverse_v1,
8384 no_neg_immediates,
85 no_zcz_fp,
8486 nv,
8587 outline_atomics,
8688 pan,
......@@ -120,6 +122,7 @@ pub const Feature = enum {
120122 reserve_x6,
121123 reserve_x7,
122124 reserve_x9,
125 rme,
123126 sb,
124127 sel2,
125128 sha2,
......@@ -128,6 +131,9 @@ pub const Feature = enum {
128131 slow_paired_128,
129132 slow_strqro_store,
130133 sm4,
134 sme,
135 sme_f64,
136 sme_i64,
131137 spe,
132138 spe_eef,
133139 specrestrict,
......@@ -148,7 +154,6 @@ pub const Feature = enum {
148154 tracev8_4,
149155 trbe,
150156 uaops,
151 use_aa,
152157 use_experimental_zeroing_pseudos,
153158 use_postra_scheduler,
154159 use_reciprocal_square_root,
......@@ -166,7 +171,6 @@ pub const Feature = enum {
166171 xs,
167172 zcm,
168173 zcz,
169 zcz_fp,
170174 zcz_fp_workaround,
171175 zcz_gp,
172176};
......@@ -594,6 +598,11 @@ pub const all_features = blk: {
594598 .description = "Harden against straight line speculation across BLR instructions",
595599 .dependencies = featureSet(&[_]Feature{}),
596600 };
601 result[@enumToInt(Feature.harden_sls_nocomdat)] = .{
602 .llvm_name = "harden-sls-nocomdat",
603 .description = "Generate thunk code for SLS mitigation in the normal text section",
604 .dependencies = featureSet(&[_]Feature{}),
605 };
597606 result[@enumToInt(Feature.harden_sls_retbr)] = .{
598607 .llvm_name = "harden-sls-retbr",
599608 .description = "Harden against straight line speculation across RET and BR instructions",
......@@ -660,8 +669,10 @@ pub const all_features = blk: {
660669 .crypto,
661670 .dotprod,
662671 .fullfp16,
672 .fuse_aes,
663673 .rcpc,
664674 .ssbs,
675 .use_postra_scheduler,
665676 .v8_2a,
666677 }),
667678 };
......@@ -672,9 +683,11 @@ pub const all_features = blk: {
672683 .crypto,
673684 .dotprod,
674685 .fullfp16,
686 .fuse_aes,
675687 .rcpc,
676688 .spe,
677689 .ssbs,
690 .use_postra_scheduler,
678691 .v8_2a,
679692 }),
680693 };
......@@ -683,10 +696,13 @@ pub const all_features = blk: {
683696 .description = "Neoverse N2 ARM processors",
684697 .dependencies = featureSet(&[_]Feature{
685698 .bf16,
699 .crypto,
686700 .ete,
701 .fuse_aes,
687702 .i8mm,
688703 .mte,
689704 .sve2_bitperm,
705 .use_postra_scheduler,
690706 .v8_5a,
691707 }),
692708 };
......@@ -714,6 +730,11 @@ pub const all_features = blk: {
714730 .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
715731 .dependencies = featureSet(&[_]Feature{}),
716732 };
733 result[@enumToInt(Feature.no_zcz_fp)] = .{
734 .llvm_name = "no-zcz-fp",
735 .description = "Has no zero-cycle zeroing instructions for FP registers",
736 .dependencies = featureSet(&[_]Feature{}),
737 };
717738 result[@enumToInt(Feature.nv)] = .{
718739 .llvm_name = "nv",
719740 .description = "Enable v8.4-A Nested Virtualization Enchancement",
......@@ -913,6 +934,11 @@ pub const all_features = blk: {
913934 .description = "Reserve X9, making it unavailable as a GPR",
914935 .dependencies = featureSet(&[_]Feature{}),
915936 };
937 result[@enumToInt(Feature.rme)] = .{
938 .llvm_name = "rme",
939 .description = "Enable Realm Management Extension",
940 .dependencies = featureSet(&[_]Feature{}),
941 };
916942 result[@enumToInt(Feature.sb)] = .{
917943 .llvm_name = "sb",
918944 .description = "Enable v8.5 Speculation Barrier",
......@@ -959,6 +985,28 @@ pub const all_features = blk: {
959985 .neon,
960986 }),
961987 };
988 result[@enumToInt(Feature.sme)] = .{
989 .llvm_name = "sme",
990 .description = "Enable Scalable Matrix Extension (SME)",
991 .dependencies = featureSet(&[_]Feature{
992 .bf16,
993 .sve2,
994 }),
995 };
996 result[@enumToInt(Feature.sme_f64)] = .{
997 .llvm_name = "sme-f64",
998 .description = "Enable Scalable Matrix Extension (SME) F64F64 instructions",
999 .dependencies = featureSet(&[_]Feature{
1000 .sme,
1001 }),
1002 };
1003 result[@enumToInt(Feature.sme_i64)] = .{
1004 .llvm_name = "sme-i64",
1005 .description = "Enable Scalable Matrix Extension (SME) I16I64 instructions",
1006 .dependencies = featureSet(&[_]Feature{
1007 .sme,
1008 }),
1009 };
9621010 result[@enumToInt(Feature.spe)] = .{
9631011 .llvm_name = "spe",
9641012 .description = "Enable Statistical Profiling extension",
......@@ -1074,11 +1122,6 @@ pub const all_features = blk: {
10741122 .description = "Enable v8.2 UAO PState",
10751123 .dependencies = featureSet(&[_]Feature{}),
10761124 };
1077 result[@enumToInt(Feature.use_aa)] = .{
1078 .llvm_name = "use-aa",
1079 .description = "Use alias analysis during codegen",
1080 .dependencies = featureSet(&[_]Feature{}),
1081 };
10821125 result[@enumToInt(Feature.use_experimental_zeroing_pseudos)] = .{
10831126 .llvm_name = "use-experimental-zeroing-pseudos",
10841127 .description = "Hint to the compiler that the MOVPRFX instruction is merged with destructive operations",
......@@ -1251,15 +1294,9 @@ pub const all_features = blk: {
12511294 .llvm_name = "zcz",
12521295 .description = "Has zero-cycle zeroing instructions",
12531296 .dependencies = featureSet(&[_]Feature{
1254 .zcz_fp,
12551297 .zcz_gp,
12561298 }),
12571299 };
1258 result[@enumToInt(Feature.zcz_fp)] = .{
1259 .llvm_name = "zcz-fp",
1260 .description = "Has zero-cycle zeroing instructions for FP registers",
1261 .dependencies = featureSet(&[_]Feature{}),
1262 };
12631300 result[@enumToInt(Feature.zcz_fp_workaround)] = .{
12641301 .llvm_name = "zcz-fp-workaround",
12651302 .description = "The zero-cycle floating-point zeroing instruction has a bug",
......@@ -1403,7 +1440,62 @@ pub const cpu = struct {
14031440 .name = "apple_latest",
14041441 .llvm_name = "apple-latest",
14051442 .features = featureSet(&[_]Feature{
1406 .apple_a13,
1443 .aggressive_fma,
1444 .alternate_sextload_cvt_f32_pattern,
1445 .altnzcv,
1446 .arith_bcc_fusion,
1447 .arith_cbz_fusion,
1448 .ccdp,
1449 .crypto,
1450 .disable_latency_sched_heuristic,
1451 .fp16fml,
1452 .fptoint,
1453 .fuse_address,
1454 .fuse_aes,
1455 .fuse_arith_logic,
1456 .fuse_crypto_eor,
1457 .fuse_csel,
1458 .fuse_literals,
1459 .perfmon,
1460 .predres,
1461 .sb,
1462 .sha3,
1463 .specrestrict,
1464 .ssbs,
1465 .v8_4a,
1466 .zcm,
1467 .zcz,
1468 }),
1469 };
1470 pub const apple_m1 = CpuModel{
1471 .name = "apple_m1",
1472 .llvm_name = "apple-m1",
1473 .features = featureSet(&[_]Feature{
1474 .aggressive_fma,
1475 .alternate_sextload_cvt_f32_pattern,
1476 .altnzcv,
1477 .arith_bcc_fusion,
1478 .arith_cbz_fusion,
1479 .ccdp,
1480 .crypto,
1481 .disable_latency_sched_heuristic,
1482 .fp16fml,
1483 .fptoint,
1484 .fuse_address,
1485 .fuse_aes,
1486 .fuse_arith_logic,
1487 .fuse_crypto_eor,
1488 .fuse_csel,
1489 .fuse_literals,
1490 .perfmon,
1491 .predres,
1492 .sb,
1493 .sha3,
1494 .specrestrict,
1495 .ssbs,
1496 .v8_4a,
1497 .zcm,
1498 .zcz,
14071499 }),
14081500 };
14091501 pub const apple_s4 = CpuModel{
......@@ -1459,7 +1551,6 @@ pub const cpu = struct {
14591551 .custom_cheap_as_move,
14601552 .fuse_aes,
14611553 .perfmon,
1462 .use_aa,
14631554 .use_postra_scheduler,
14641555 .v8a,
14651556 }),
......@@ -1474,6 +1565,7 @@ pub const cpu = struct {
14741565 .fuse_aes,
14751566 .perfmon,
14761567 .rcpc,
1568 .use_postra_scheduler,
14771569 .v8_2a,
14781570 }),
14791571 };
......@@ -1649,7 +1741,6 @@ pub const cpu = struct {
16491741 .use_postra_scheduler,
16501742 .use_reciprocal_square_root,
16511743 .v8a,
1652 .zcz_fp,
16531744 }),
16541745 };
16551746 pub const exynos_m2 = CpuModel{
......@@ -1666,7 +1757,6 @@ pub const cpu = struct {
16661757 .slow_paired_128,
16671758 .use_postra_scheduler,
16681759 .v8a,
1669 .zcz_fp,
16701760 }),
16711761 };
16721762 pub const exynos_m3 = CpuModel{
......@@ -1686,7 +1776,6 @@ pub const cpu = struct {
16861776 .predictable_select_expensive,
16871777 .use_postra_scheduler,
16881778 .v8a,
1689 .zcz_fp,
16901779 }),
16911780 };
16921781 pub const exynos_m4 = CpuModel{
......@@ -1824,7 +1913,6 @@ pub const cpu = struct {
18241913 .perfmon,
18251914 .predictable_select_expensive,
18261915 .strict_align,
1827 .use_aa,
18281916 .use_postra_scheduler,
18291917 .v8_3a,
18301918 }),
lib/std/target/amdgpu.zig+255-8
......@@ -9,6 +9,7 @@ pub const Feature = enum {
99 a16,
1010 add_no_carry_insts,
1111 aperture_regs,
12 architected_flat_scratch,
1213 atomic_fadd_insts,
1314 auto_waitcnt_before_barrier,
1415 ci_insts,
......@@ -20,11 +21,14 @@ pub const Feature = enum {
2021 dot4_insts,
2122 dot5_insts,
2223 dot6_insts,
24 dot7_insts,
2325 dpp,
2426 dpp8,
27 dpp_64bit,
2528 ds_src2_insts,
2629 enable_ds128,
2730 enable_prt_strict_null,
31 extended_image_insts,
2832 fast_denormal_f32,
2933 fast_fmaf,
3034 flat_address_space,
......@@ -36,16 +40,19 @@ pub const Feature = enum {
3640 fma_mix_insts,
3741 fmaf,
3842 fp64,
43 full_rate_64_ops,
3944 g16,
4045 gcn3_encoding,
4146 get_wave_id_inst,
4247 gfx10,
4348 gfx10_3_insts,
49 gfx10_a_encoding,
4450 gfx10_b_encoding,
4551 gfx10_insts,
4652 gfx7_gfx8_gfx9_insts,
4753 gfx8_insts,
4854 gfx9,
55 gfx90a_insts,
4956 gfx9_insts,
5057 half_rate_64_ops,
5158 image_gather4_d16_bug,
......@@ -70,11 +77,18 @@ pub const Feature = enum {
7077 mfma_inline_literal_bug,
7178 mimg_r128,
7279 movrel,
80 negative_scratch_offset_bug,
81 negative_unaligned_scratch_offset_bug,
7382 no_data_dep_hazard,
7483 no_sdst_cmpx,
84 nsa_clause_bug,
7585 nsa_encoding,
86 nsa_max_size_13,
87 nsa_max_size_5,
7688 nsa_to_vmem_bug,
7789 offset_3f_bug,
90 packed_fp32_ops,
91 packed_tid,
7892 pk_fmac_f16_inst,
7993 promote_alloca,
8094 r128_a16,
......@@ -92,11 +106,13 @@ pub const Feature = enum {
92106 sdwa_sdst,
93107 sea_islands,
94108 sgpr_init_bug,
109 shader_cycles_register,
95110 si_scheduler,
96111 smem_to_vector_write_hazard,
97112 southern_islands,
98113 sramecc,
99114 sramecc_support,
115 tgsplit,
100116 trap_handler,
101117 trig_reduced_range,
102118 unaligned_access_mode,
......@@ -149,6 +165,11 @@ pub const all_features = blk: {
149165 .description = "Has Memory Aperture Base and Size Registers",
150166 .dependencies = featureSet(&[_]Feature{}),
151167 };
168 result[@enumToInt(Feature.architected_flat_scratch)] = .{
169 .llvm_name = "architected-flat-scratch",
170 .description = "Flat Scratch register is a readonly SPI initialized architected register",
171 .dependencies = featureSet(&[_]Feature{}),
172 };
152173 result[@enumToInt(Feature.atomic_fadd_insts)] = .{
153174 .llvm_name = "atomic-fadd-insts",
154175 .description = "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions",
......@@ -183,7 +204,7 @@ pub const all_features = blk: {
183204 };
184205 result[@enumToInt(Feature.dot2_insts)] = .{
185206 .llvm_name = "dot2-insts",
186 .description = "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions",
207 .description = "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions",
187208 .dependencies = featureSet(&[_]Feature{}),
188209 };
189210 result[@enumToInt(Feature.dot3_insts)] = .{
......@@ -206,6 +227,11 @@ pub const all_features = blk: {
206227 .description = "Has v_dot4c_i32_i8 instruction",
207228 .dependencies = featureSet(&[_]Feature{}),
208229 };
230 result[@enumToInt(Feature.dot7_insts)] = .{
231 .llvm_name = "dot7-insts",
232 .description = "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions",
233 .dependencies = featureSet(&[_]Feature{}),
234 };
209235 result[@enumToInt(Feature.dpp)] = .{
210236 .llvm_name = "dpp",
211237 .description = "Support DPP (Data Parallel Primitives) extension",
......@@ -216,6 +242,11 @@ pub const all_features = blk: {
216242 .description = "Support DPP8 (Data Parallel Primitives) extension",
217243 .dependencies = featureSet(&[_]Feature{}),
218244 };
245 result[@enumToInt(Feature.dpp_64bit)] = .{
246 .llvm_name = "dpp-64bit",
247 .description = "Support DPP (Data Parallel Primitives) extension",
248 .dependencies = featureSet(&[_]Feature{}),
249 };
219250 result[@enumToInt(Feature.ds_src2_insts)] = .{
220251 .llvm_name = "ds-src2-insts",
221252 .description = "Has ds_*_src2 instructions",
......@@ -231,6 +262,11 @@ pub const all_features = blk: {
231262 .description = "Enable zeroing of result registers for sparse texture fetches",
232263 .dependencies = featureSet(&[_]Feature{}),
233264 };
265 result[@enumToInt(Feature.extended_image_insts)] = .{
266 .llvm_name = "extended-image-insts",
267 .description = "Support mips != 0, lod != 0, gather4, and get_lod",
268 .dependencies = featureSet(&[_]Feature{}),
269 };
234270 result[@enumToInt(Feature.fast_denormal_f32)] = .{
235271 .llvm_name = "fast-denormal-f32",
236272 .description = "Enabling denormals does not cause f32 instructions to run at f64 rates",
......@@ -268,7 +304,7 @@ pub const all_features = blk: {
268304 };
269305 result[@enumToInt(Feature.flat_segment_offset_bug)] = .{
270306 .llvm_name = "flat-segment-offset-bug",
271 .description = "GFX10 bug, inst_offset ignored in flat segment",
307 .description = "GFX10 bug where inst_offset is ignored when flat instructions access global memory",
272308 .dependencies = featureSet(&[_]Feature{}),
273309 };
274310 result[@enumToInt(Feature.fma_mix_insts)] = .{
......@@ -286,6 +322,11 @@ pub const all_features = blk: {
286322 .description = "Enable double precision operations",
287323 .dependencies = featureSet(&[_]Feature{}),
288324 };
325 result[@enumToInt(Feature.full_rate_64_ops)] = .{
326 .llvm_name = "full-rate-64-ops",
327 .description = "Most fp64 instructions are full rate",
328 .dependencies = featureSet(&[_]Feature{}),
329 };
289330 result[@enumToInt(Feature.g16)] = .{
290331 .llvm_name = "g16",
291332 .description = "Support G16 for 16-bit gradient image operands",
......@@ -312,6 +353,7 @@ pub const all_features = blk: {
312353 .ci_insts,
313354 .dpp,
314355 .dpp8,
356 .extended_image_insts,
315357 .fast_denormal_f32,
316358 .fast_fmaf,
317359 .flat_address_space,
......@@ -334,6 +376,7 @@ pub const all_features = blk: {
334376 .pk_fmac_f16_inst,
335377 .register_banking,
336378 .s_memrealtime,
379 .s_memtime_inst,
337380 .sdwa,
338381 .sdwa_omod,
339382 .sdwa_scalar,
......@@ -350,6 +393,11 @@ pub const all_features = blk: {
350393 .description = "Additional instructions for GFX10.3",
351394 .dependencies = featureSet(&[_]Feature{}),
352395 };
396 result[@enumToInt(Feature.gfx10_a_encoding)] = .{
397 .llvm_name = "gfx10_a-encoding",
398 .description = "Has BVH ray tracing instructions",
399 .dependencies = featureSet(&[_]Feature{}),
400 };
353401 result[@enumToInt(Feature.gfx10_b_encoding)] = .{
354402 .llvm_name = "gfx10_b-encoding",
355403 .description = "Encoding format GFX10_B",
......@@ -379,7 +427,6 @@ pub const all_features = blk: {
379427 .aperture_regs,
380428 .ci_insts,
381429 .dpp,
382 .ds_src2_insts,
383430 .fast_denormal_f32,
384431 .fast_fmaf,
385432 .flat_address_space,
......@@ -394,7 +441,7 @@ pub const all_features = blk: {
394441 .int_clamp_insts,
395442 .inv_2pi_inline_imm,
396443 .localmemorysize65536,
397 .mad_mac_f32_insts,
444 .negative_scratch_offset_bug,
398445 .r128_a16,
399446 .s_memrealtime,
400447 .s_memtime_inst,
......@@ -413,6 +460,11 @@ pub const all_features = blk: {
413460 .xnack_support,
414461 }),
415462 };
463 result[@enumToInt(Feature.gfx90a_insts)] = .{
464 .llvm_name = "gfx90a-insts",
465 .description = "Additional instructions for GFX90A+",
466 .dependencies = featureSet(&[_]Feature{}),
467 };
416468 result[@enumToInt(Feature.gfx9_insts)] = .{
417469 .llvm_name = "gfx9-insts",
418470 .description = "Additional instructions for GFX9+",
......@@ -533,6 +585,16 @@ pub const all_features = blk: {
533585 .description = "Has v_movrel*_b32 instructions",
534586 .dependencies = featureSet(&[_]Feature{}),
535587 };
588 result[@enumToInt(Feature.negative_scratch_offset_bug)] = .{
589 .llvm_name = "negative-scratch-offset-bug",
590 .description = "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9",
591 .dependencies = featureSet(&[_]Feature{}),
592 };
593 result[@enumToInt(Feature.negative_unaligned_scratch_offset_bug)] = .{
594 .llvm_name = "negative-unaligned-scratch-offset-bug",
595 .description = "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10",
596 .dependencies = featureSet(&[_]Feature{}),
597 };
536598 result[@enumToInt(Feature.no_data_dep_hazard)] = .{
537599 .llvm_name = "no-data-dep-hazard",
538600 .description = "Does not need SW waitstates",
......@@ -543,11 +605,26 @@ pub const all_features = blk: {
543605 .description = "V_CMPX does not write VCC/SGPR in addition to EXEC",
544606 .dependencies = featureSet(&[_]Feature{}),
545607 };
608 result[@enumToInt(Feature.nsa_clause_bug)] = .{
609 .llvm_name = "nsa-clause-bug",
610 .description = "MIMG-NSA in a hard clause has unpredictable results on GFX10.1",
611 .dependencies = featureSet(&[_]Feature{}),
612 };
546613 result[@enumToInt(Feature.nsa_encoding)] = .{
547614 .llvm_name = "nsa-encoding",
548615 .description = "Support NSA encoding for image instructions",
549616 .dependencies = featureSet(&[_]Feature{}),
550617 };
618 result[@enumToInt(Feature.nsa_max_size_13)] = .{
619 .llvm_name = "nsa-max-size-13",
620 .description = "The maximum non-sequential address size in VGPRs.",
621 .dependencies = featureSet(&[_]Feature{}),
622 };
623 result[@enumToInt(Feature.nsa_max_size_5)] = .{
624 .llvm_name = "nsa-max-size-5",
625 .description = "The maximum non-sequential address size in VGPRs.",
626 .dependencies = featureSet(&[_]Feature{}),
627 };
551628 result[@enumToInt(Feature.nsa_to_vmem_bug)] = .{
552629 .llvm_name = "nsa-to-vmem-bug",
553630 .description = "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero",
......@@ -558,6 +635,16 @@ pub const all_features = blk: {
558635 .description = "Branch offset of 3f hardware bug",
559636 .dependencies = featureSet(&[_]Feature{}),
560637 };
638 result[@enumToInt(Feature.packed_fp32_ops)] = .{
639 .llvm_name = "packed-fp32-ops",
640 .description = "Support packed fp32 instructions",
641 .dependencies = featureSet(&[_]Feature{}),
642 };
643 result[@enumToInt(Feature.packed_tid)] = .{
644 .llvm_name = "packed-tid",
645 .description = "Workitem IDs are packed into v0 at kernel launch",
646 .dependencies = featureSet(&[_]Feature{}),
647 };
561648 result[@enumToInt(Feature.pk_fmac_f16_inst)] = .{
562649 .llvm_name = "pk-fmac-f16-inst",
563650 .description = "Has v_pk_fmac_f16 instruction",
......@@ -639,6 +726,7 @@ pub const all_features = blk: {
639726 .dependencies = featureSet(&[_]Feature{
640727 .ci_insts,
641728 .ds_src2_insts,
729 .extended_image_insts,
642730 .flat_address_space,
643731 .fp64,
644732 .gfx7_gfx8_gfx9_insts,
......@@ -657,6 +745,11 @@ pub const all_features = blk: {
657745 .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",
658746 .dependencies = featureSet(&[_]Feature{}),
659747 };
748 result[@enumToInt(Feature.shader_cycles_register)] = .{
749 .llvm_name = "shader-cycles-register",
750 .description = "Has SHADER_CYCLES hardware register",
751 .dependencies = featureSet(&[_]Feature{}),
752 };
660753 result[@enumToInt(Feature.si_scheduler)] = .{
661754 .llvm_name = "si-scheduler",
662755 .description = "Enable SI Machine Scheduler",
......@@ -672,6 +765,7 @@ pub const all_features = blk: {
672765 .description = "SOUTHERN_ISLANDS GPU generation",
673766 .dependencies = featureSet(&[_]Feature{
674767 .ds_src2_insts,
768 .extended_image_insts,
675769 .fp64,
676770 .ldsbankcount32,
677771 .localmemorysize32768,
......@@ -693,6 +787,11 @@ pub const all_features = blk: {
693787 .description = "Hardware supports SRAMECC",
694788 .dependencies = featureSet(&[_]Feature{}),
695789 };
790 result[@enumToInt(Feature.tgsplit)] = .{
791 .llvm_name = "tgsplit",
792 .description = "Enable threadgroup split execution",
793 .dependencies = featureSet(&[_]Feature{}),
794 };
696795 result[@enumToInt(Feature.trap_handler)] = .{
697796 .llvm_name = "trap-handler",
698797 .description = "Trap handler support",
......@@ -761,6 +860,7 @@ pub const all_features = blk: {
761860 .ci_insts,
762861 .dpp,
763862 .ds_src2_insts,
863 .extended_image_insts,
764864 .fast_denormal_f32,
765865 .flat_address_space,
766866 .fp64,
......@@ -892,10 +992,12 @@ pub const cpu = struct {
892992 .lds_misaligned_bug,
893993 .ldsbankcount32,
894994 .mad_mac_f32_insts,
995 .negative_unaligned_scratch_offset_bug,
996 .nsa_clause_bug,
895997 .nsa_encoding,
998 .nsa_max_size_5,
896999 .nsa_to_vmem_bug,
8971000 .offset_3f_bug,
898 .s_memtime_inst,
8991001 .scalar_atomics,
9001002 .scalar_flat_scratch_insts,
9011003 .scalar_stores,
......@@ -916,6 +1018,7 @@ pub const cpu = struct {
9161018 .dot2_insts,
9171019 .dot5_insts,
9181020 .dot6_insts,
1021 .dot7_insts,
9191022 .ds_src2_insts,
9201023 .flat_segment_offset_bug,
9211024 .get_wave_id_inst,
......@@ -925,10 +1028,12 @@ pub const cpu = struct {
9251028 .lds_misaligned_bug,
9261029 .ldsbankcount32,
9271030 .mad_mac_f32_insts,
1031 .negative_unaligned_scratch_offset_bug,
1032 .nsa_clause_bug,
9281033 .nsa_encoding,
1034 .nsa_max_size_5,
9291035 .nsa_to_vmem_bug,
9301036 .offset_3f_bug,
931 .s_memtime_inst,
9321037 .scalar_atomics,
9331038 .scalar_flat_scratch_insts,
9341039 .scalar_stores,
......@@ -949,6 +1054,7 @@ pub const cpu = struct {
9491054 .dot2_insts,
9501055 .dot5_insts,
9511056 .dot6_insts,
1057 .dot7_insts,
9521058 .ds_src2_insts,
9531059 .flat_segment_offset_bug,
9541060 .get_wave_id_inst,
......@@ -958,10 +1064,44 @@ pub const cpu = struct {
9581064 .lds_misaligned_bug,
9591065 .ldsbankcount32,
9601066 .mad_mac_f32_insts,
1067 .negative_unaligned_scratch_offset_bug,
1068 .nsa_clause_bug,
9611069 .nsa_encoding,
1070 .nsa_max_size_5,
1071 .nsa_to_vmem_bug,
1072 .offset_3f_bug,
1073 .scalar_atomics,
1074 .scalar_flat_scratch_insts,
1075 .scalar_stores,
1076 .smem_to_vector_write_hazard,
1077 .vcmpx_exec_war_hazard,
1078 .vcmpx_permlane_hazard,
1079 .vmem_to_scalar_write_hazard,
1080 .wavefrontsize32,
1081 .xnack_support,
1082 }),
1083 };
1084 pub const gfx1013 = CpuModel{
1085 .name = "gfx1013",
1086 .llvm_name = "gfx1013",
1087 .features = featureSet(&[_]Feature{
1088 .dl_insts,
1089 .ds_src2_insts,
1090 .flat_segment_offset_bug,
1091 .get_wave_id_inst,
1092 .gfx10,
1093 .gfx10_a_encoding,
1094 .inst_fwd_prefetch_bug,
1095 .lds_branch_vmem_war_hazard,
1096 .lds_misaligned_bug,
1097 .ldsbankcount32,
1098 .mad_mac_f32_insts,
1099 .negative_unaligned_scratch_offset_bug,
1100 .nsa_clause_bug,
1101 .nsa_encoding,
1102 .nsa_max_size_5,
9621103 .nsa_to_vmem_bug,
9631104 .offset_3f_bug,
964 .s_memtime_inst,
9651105 .scalar_atomics,
9661106 .scalar_flat_scratch_insts,
9671107 .scalar_stores,
......@@ -982,11 +1122,15 @@ pub const cpu = struct {
9821122 .dot2_insts,
9831123 .dot5_insts,
9841124 .dot6_insts,
1125 .dot7_insts,
9851126 .gfx10,
9861127 .gfx10_3_insts,
1128 .gfx10_a_encoding,
9871129 .gfx10_b_encoding,
9881130 .ldsbankcount32,
9891131 .nsa_encoding,
1132 .nsa_max_size_13,
1133 .shader_cycles_register,
9901134 .wavefrontsize32,
9911135 }),
9921136 };
......@@ -999,11 +1143,15 @@ pub const cpu = struct {
9991143 .dot2_insts,
10001144 .dot5_insts,
10011145 .dot6_insts,
1146 .dot7_insts,
10021147 .gfx10,
10031148 .gfx10_3_insts,
1149 .gfx10_a_encoding,
10041150 .gfx10_b_encoding,
10051151 .ldsbankcount32,
10061152 .nsa_encoding,
1153 .nsa_max_size_13,
1154 .shader_cycles_register,
10071155 .wavefrontsize32,
10081156 }),
10091157 };
......@@ -1016,11 +1164,15 @@ pub const cpu = struct {
10161164 .dot2_insts,
10171165 .dot5_insts,
10181166 .dot6_insts,
1167 .dot7_insts,
10191168 .gfx10,
10201169 .gfx10_3_insts,
1170 .gfx10_a_encoding,
10211171 .gfx10_b_encoding,
10221172 .ldsbankcount32,
10231173 .nsa_encoding,
1174 .nsa_max_size_13,
1175 .shader_cycles_register,
10241176 .wavefrontsize32,
10251177 }),
10261178 };
......@@ -1033,11 +1185,57 @@ pub const cpu = struct {
10331185 .dot2_insts,
10341186 .dot5_insts,
10351187 .dot6_insts,
1188 .dot7_insts,
1189 .gfx10,
1190 .gfx10_3_insts,
1191 .gfx10_a_encoding,
1192 .gfx10_b_encoding,
1193 .ldsbankcount32,
1194 .nsa_encoding,
1195 .nsa_max_size_13,
1196 .shader_cycles_register,
1197 .wavefrontsize32,
1198 }),
1199 };
1200 pub const gfx1034 = CpuModel{
1201 .name = "gfx1034",
1202 .llvm_name = "gfx1034",
1203 .features = featureSet(&[_]Feature{
1204 .dl_insts,
1205 .dot1_insts,
1206 .dot2_insts,
1207 .dot5_insts,
1208 .dot6_insts,
1209 .dot7_insts,
10361210 .gfx10,
10371211 .gfx10_3_insts,
1212 .gfx10_a_encoding,
10381213 .gfx10_b_encoding,
10391214 .ldsbankcount32,
10401215 .nsa_encoding,
1216 .nsa_max_size_13,
1217 .shader_cycles_register,
1218 .wavefrontsize32,
1219 }),
1220 };
1221 pub const gfx1035 = CpuModel{
1222 .name = "gfx1035",
1223 .llvm_name = "gfx1035",
1224 .features = featureSet(&[_]Feature{
1225 .dl_insts,
1226 .dot1_insts,
1227 .dot2_insts,
1228 .dot5_insts,
1229 .dot6_insts,
1230 .dot7_insts,
1231 .gfx10,
1232 .gfx10_3_insts,
1233 .gfx10_a_encoding,
1234 .gfx10_b_encoding,
1235 .ldsbankcount32,
1236 .nsa_encoding,
1237 .nsa_max_size_13,
1238 .shader_cycles_register,
10411239 .wavefrontsize32,
10421240 }),
10431241 };
......@@ -1171,9 +1369,12 @@ pub const cpu = struct {
11711369 .name = "gfx900",
11721370 .llvm_name = "gfx900",
11731371 .features = featureSet(&[_]Feature{
1372 .ds_src2_insts,
1373 .extended_image_insts,
11741374 .gfx9,
11751375 .image_gather4_d16_bug,
11761376 .ldsbankcount32,
1377 .mad_mac_f32_insts,
11771378 .mad_mix_insts,
11781379 }),
11791380 };
......@@ -1181,9 +1382,12 @@ pub const cpu = struct {
11811382 .name = "gfx902",
11821383 .llvm_name = "gfx902",
11831384 .features = featureSet(&[_]Feature{
1385 .ds_src2_insts,
1386 .extended_image_insts,
11841387 .gfx9,
11851388 .image_gather4_d16_bug,
11861389 .ldsbankcount32,
1390 .mad_mac_f32_insts,
11871391 .mad_mix_insts,
11881392 }),
11891393 };
......@@ -1191,10 +1395,13 @@ pub const cpu = struct {
11911395 .name = "gfx904",
11921396 .llvm_name = "gfx904",
11931397 .features = featureSet(&[_]Feature{
1398 .ds_src2_insts,
1399 .extended_image_insts,
11941400 .fma_mix_insts,
11951401 .gfx9,
11961402 .image_gather4_d16_bug,
11971403 .ldsbankcount32,
1404 .mad_mac_f32_insts,
11981405 }),
11991406 };
12001407 pub const gfx906 = CpuModel{
......@@ -1204,11 +1411,15 @@ pub const cpu = struct {
12041411 .dl_insts,
12051412 .dot1_insts,
12061413 .dot2_insts,
1414 .dot7_insts,
1415 .ds_src2_insts,
1416 .extended_image_insts,
12071417 .fma_mix_insts,
12081418 .gfx9,
12091419 .half_rate_64_ops,
12101420 .image_gather4_d16_bug,
12111421 .ldsbankcount32,
1422 .mad_mac_f32_insts,
12121423 .sramecc_support,
12131424 }),
12141425 };
......@@ -1224,11 +1435,15 @@ pub const cpu = struct {
12241435 .dot4_insts,
12251436 .dot5_insts,
12261437 .dot6_insts,
1438 .dot7_insts,
1439 .ds_src2_insts,
1440 .extended_image_insts,
12271441 .fma_mix_insts,
12281442 .gfx9,
12291443 .half_rate_64_ops,
12301444 .image_gather4_d16_bug,
12311445 .ldsbankcount32,
1446 .mad_mac_f32_insts,
12321447 .mai_insts,
12331448 .mfma_inline_literal_bug,
12341449 .pk_fmac_f16_inst,
......@@ -1239,21 +1454,53 @@ pub const cpu = struct {
12391454 .name = "gfx909",
12401455 .llvm_name = "gfx909",
12411456 .features = featureSet(&[_]Feature{
1457 .ds_src2_insts,
1458 .extended_image_insts,
12421459 .gfx9,
12431460 .image_gather4_d16_bug,
12441461 .ldsbankcount32,
1462 .mad_mac_f32_insts,
12451463 .mad_mix_insts,
12461464 }),
12471465 };
1466 pub const gfx90a = CpuModel{
1467 .name = "gfx90a",
1468 .llvm_name = "gfx90a",
1469 .features = featureSet(&[_]Feature{
1470 .atomic_fadd_insts,
1471 .dl_insts,
1472 .dot1_insts,
1473 .dot2_insts,
1474 .dot3_insts,
1475 .dot4_insts,
1476 .dot5_insts,
1477 .dot6_insts,
1478 .dot7_insts,
1479 .dpp_64bit,
1480 .fma_mix_insts,
1481 .full_rate_64_ops,
1482 .gfx9,
1483 .gfx90a_insts,
1484 .ldsbankcount32,
1485 .mad_mac_f32_insts,
1486 .mai_insts,
1487 .packed_fp32_ops,
1488 .packed_tid,
1489 .pk_fmac_f16_inst,
1490 .sramecc_support,
1491 }),
1492 };
12481493 pub const gfx90c = CpuModel{
12491494 .name = "gfx90c",
12501495 .llvm_name = "gfx90c",
12511496 .features = featureSet(&[_]Feature{
1497 .ds_src2_insts,
1498 .extended_image_insts,
12521499 .gfx9,
12531500 .image_gather4_d16_bug,
12541501 .ldsbankcount32,
1502 .mad_mac_f32_insts,
12551503 .mad_mix_insts,
1256 .xnack,
12571504 }),
12581505 };
12591506 pub const hainan = CpuModel{
lib/std/target/arc.zig created+39
......@@ -0,0 +1,39 @@
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 norm,
9};
10
11pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
12pub const featureSetHas = CpuFeature.feature_set_fns(Feature).featureSetHas;
13pub const featureSetHasAny = CpuFeature.feature_set_fns(Feature).featureSetHasAny;
14pub const featureSetHasAll = CpuFeature.feature_set_fns(Feature).featureSetHasAll;
15
16pub const all_features = blk: {
17 const len = @typeInfo(Feature).Enum.fields.len;
18 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
19 var result: [len]CpuFeature = undefined;
20 result[@enumToInt(Feature.norm)] = .{
21 .llvm_name = "norm",
22 .description = "Enable support for norm instruction.",
23 .dependencies = featureSet(&[_]Feature{}),
24 };
25 const ti = @typeInfo(Feature);
26 for (result) |*elem, i| {
27 elem.index = i;
28 elem.name = ti.Enum.fields[i].name;
29 }
30 break :blk result;
31};
32
33pub const cpu = struct {
34 pub const generic = CpuModel{
35 .name = "generic",
36 .llvm_name = "generic",
37 .features = featureSet(&[_]Feature{}),
38 };
39};
lib/std/target/arm.zig+12-8
......@@ -51,6 +51,7 @@ pub const Feature = enum {
5151 fuse_aes,
5252 fuse_literals,
5353 harden_sls_blr,
54 harden_sls_nocomdat,
5455 harden_sls_retbr,
5556 has_v4t,
5657 has_v5t,
......@@ -487,6 +488,11 @@ pub const all_features = blk: {
487488 .description = "Harden against straight line speculation across indirect calls",
488489 .dependencies = featureSet(&[_]Feature{}),
489490 };
491 result[@enumToInt(Feature.harden_sls_nocomdat)] = .{
492 .llvm_name = "harden-sls-nocomdat",
493 .description = "Generate thunk code for SLS mitigation in the normal text section",
494 .dependencies = featureSet(&[_]Feature{}),
495 };
490496 result[@enumToInt(Feature.harden_sls_retbr)] = .{
491497 .llvm_name = "harden-sls-retbr",
492498 .description = "Harden against straight line speculation across RETurn and BranchRegister instructions",
......@@ -1245,7 +1251,7 @@ pub const all_features = blk: {
12451251 };
12461252 result[@enumToInt(Feature.v8_7a)] = .{
12471253 .llvm_name = "armv8.7-a",
1248 .description = "ARMv86a architecture",
1254 .description = "ARMv87a architecture",
12491255 .dependencies = featureSet(&[_]Feature{
12501256 .aclass,
12511257 .crc,
......@@ -1517,13 +1523,6 @@ pub const cpu = struct {
15171523 .vfp2,
15181524 }),
15191525 };
1520 pub const arm1176j_s = CpuModel{
1521 .name = "arm1176j_s",
1522 .llvm_name = "arm1176j-s",
1523 .features = featureSet(&[_]Feature{
1524 .v6kz,
1525 }),
1526 };
15271526 pub const arm1176jz_s = CpuModel{
15281527 .name = "arm1176jz_s",
15291528 .llvm_name = "arm1176jz-s",
......@@ -1889,6 +1888,7 @@ pub const cpu = struct {
18891888 .name = "cortex_m0",
18901889 .llvm_name = "cortex-m0",
18911890 .features = featureSet(&[_]Feature{
1891 .no_branch_predictor,
18921892 .v6m,
18931893 }),
18941894 };
......@@ -1896,6 +1896,7 @@ pub const cpu = struct {
18961896 .name = "cortex_m0plus",
18971897 .llvm_name = "cortex-m0plus",
18981898 .features = featureSet(&[_]Feature{
1899 .no_branch_predictor,
18991900 .v6m,
19001901 }),
19011902 };
......@@ -1903,6 +1904,7 @@ pub const cpu = struct {
19031904 .name = "cortex_m1",
19041905 .llvm_name = "cortex-m1",
19051906 .features = featureSet(&[_]Feature{
1907 .no_branch_predictor,
19061908 .v6m,
19071909 }),
19081910 };
......@@ -1910,6 +1912,7 @@ pub const cpu = struct {
19101912 .name = "cortex_m23",
19111913 .llvm_name = "cortex-m23",
19121914 .features = featureSet(&[_]Feature{
1915 .no_branch_predictor,
19131916 .no_movt,
19141917 .v8m,
19151918 }),
......@@ -2225,6 +2228,7 @@ pub const cpu = struct {
22252228 .name = "sc000",
22262229 .llvm_name = "sc000",
22272230 .features = featureSet(&[_]Feature{
2231 .no_branch_predictor,
22282232 .v6m,
22292233 }),
22302234 };
lib/std/target/hexagon.zig+35
......@@ -16,6 +16,7 @@ pub const Feature = enum {
1616 hvxv65,
1717 hvxv66,
1818 hvxv67,
19 hvxv68,
1920 long_calls,
2021 mem_noshuf,
2122 memops,
......@@ -35,6 +36,7 @@ pub const Feature = enum {
3536 v65,
3637 v66,
3738 v67,
39 v68,
3840 zreg,
3941};
4042
......@@ -117,6 +119,13 @@ pub const all_features = blk: {
117119 .hvxv66,
118120 }),
119121 };
122 result[@enumToInt(Feature.hvxv68)] = .{
123 .llvm_name = "hvxv68",
124 .description = "Hexagon HVX instructions",
125 .dependencies = featureSet(&[_]Feature{
126 .hvxv67,
127 }),
128 };
120129 result[@enumToInt(Feature.long_calls)] = .{
121130 .llvm_name = "long-calls",
122131 .description = "Use constant-extended calls",
......@@ -216,6 +225,11 @@ pub const all_features = blk: {
216225 .description = "Enable Hexagon V67 architecture",
217226 .dependencies = featureSet(&[_]Feature{}),
218227 };
228 result[@enumToInt(Feature.v68)] = .{
229 .llvm_name = "v68",
230 .description = "Enable Hexagon V68 architecture",
231 .dependencies = featureSet(&[_]Feature{}),
232 };
219233 result[@enumToInt(Feature.zreg)] = .{
220234 .llvm_name = "zreg",
221235 .description = "Hexagon ZReg extension instructions",
......@@ -385,4 +399,25 @@ pub const cpu = struct {
385399 .v67,
386400 }),
387401 };
402 pub const hexagonv68 = CpuModel{
403 .name = "hexagonv68",
404 .llvm_name = "hexagonv68",
405 .features = featureSet(&[_]Feature{
406 .compound,
407 .duplex,
408 .mem_noshuf,
409 .memops,
410 .nvj,
411 .nvs,
412 .small_data,
413 .v5,
414 .v55,
415 .v60,
416 .v62,
417 .v65,
418 .v66,
419 .v67,
420 .v68,
421 }),
422 };
388423};
lib/std/target/nvptx.zig+26
......@@ -17,6 +17,8 @@ pub const Feature = enum {
1717 ptx64,
1818 ptx65,
1919 ptx70,
20 ptx71,
21 ptx72,
2022 sm_20,
2123 sm_21,
2224 sm_30,
......@@ -33,6 +35,7 @@ pub const Feature = enum {
3335 sm_72,
3436 sm_75,
3537 sm_80,
38 sm_86,
3639};
3740
3841pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
......@@ -104,6 +107,16 @@ pub const all_features = blk: {
104107 .description = "Use PTX version 7.0",
105108 .dependencies = featureSet(&[_]Feature{}),
106109 };
110 result[@enumToInt(Feature.ptx71)] = .{
111 .llvm_name = "ptx71",
112 .description = "Use PTX version 7.1",
113 .dependencies = featureSet(&[_]Feature{}),
114 };
115 result[@enumToInt(Feature.ptx72)] = .{
116 .llvm_name = "ptx72",
117 .description = "Use PTX version 7.2",
118 .dependencies = featureSet(&[_]Feature{}),
119 };
107120 result[@enumToInt(Feature.sm_20)] = .{
108121 .llvm_name = "sm_20",
109122 .description = "Target SM 2.0",
......@@ -184,6 +197,11 @@ pub const all_features = blk: {
184197 .description = "Target SM 8.0",
185198 .dependencies = featureSet(&[_]Feature{}),
186199 };
200 result[@enumToInt(Feature.sm_86)] = .{
201 .llvm_name = "sm_86",
202 .description = "Target SM 8.6",
203 .dependencies = featureSet(&[_]Feature{}),
204 };
187205 const ti = @typeInfo(Feature);
188206 for (result) |*elem, i| {
189207 elem.index = i;
......@@ -317,4 +335,12 @@ pub const cpu = struct {
317335 .sm_80,
318336 }),
319337 };
338 pub const sm_86 = CpuModel{
339 .name = "sm_86",
340 .llvm_name = "sm_86",
341 .features = featureSet(&[_]Feature{
342 .ptx71,
343 .sm_86,
344 }),
345 };
320346};
lib/std/target/powerpc.zig+34-1
......@@ -37,6 +37,7 @@ pub const Feature = enum {
3737 htm,
3838 icbt,
3939 invariant_function_descriptors,
40 isa_v207_instructions,
4041 isa_v30_instructions,
4142 isa_v31_instructions,
4243 isel,
......@@ -62,7 +63,10 @@ pub const Feature = enum {
6263 ppc_prera_sched,
6364 predictable_select_expensive,
6465 prefix_instrs,
66 privileged,
67 quadword_atomics,
6568 recipprec,
69 rop_protect,
6670 secure_plt,
6771 slow_popcntd,
6872 spe,
......@@ -277,10 +281,17 @@ pub const all_features = blk: {
277281 .description = "Assume function descriptors are invariant",
278282 .dependencies = featureSet(&[_]Feature{}),
279283 };
284 result[@enumToInt(Feature.isa_v207_instructions)] = .{
285 .llvm_name = "isa-v207-instructions",
286 .description = "Enable instructions in ISA 2.07.",
287 .dependencies = featureSet(&[_]Feature{}),
288 };
280289 result[@enumToInt(Feature.isa_v30_instructions)] = .{
281290 .llvm_name = "isa-v30-instructions",
282291 .description = "Enable instructions in ISA 3.0.",
283 .dependencies = featureSet(&[_]Feature{}),
292 .dependencies = featureSet(&[_]Feature{
293 .isa_v207_instructions,
294 }),
284295 };
285296 result[@enumToInt(Feature.isa_v31_instructions)] = .{
286297 .llvm_name = "isa-v31-instructions",
......@@ -433,11 +444,26 @@ pub const all_features = blk: {
433444 .power9_altivec,
434445 }),
435446 };
447 result[@enumToInt(Feature.privileged)] = .{
448 .llvm_name = "privileged",
449 .description = "Add privileged instructions",
450 .dependencies = featureSet(&[_]Feature{}),
451 };
452 result[@enumToInt(Feature.quadword_atomics)] = .{
453 .llvm_name = "quadword-atomics",
454 .description = "Enable lqarx and stqcx.",
455 .dependencies = featureSet(&[_]Feature{}),
456 };
436457 result[@enumToInt(Feature.recipprec)] = .{
437458 .llvm_name = "recipprec",
438459 .description = "Assume higher precision reciprocal estimates",
439460 .dependencies = featureSet(&[_]Feature{}),
440461 };
462 result[@enumToInt(Feature.rop_protect)] = .{
463 .llvm_name = "rop-protect",
464 .description = "Add ROP protect",
465 .dependencies = featureSet(&[_]Feature{}),
466 };
441467 result[@enumToInt(Feature.secure_plt)] = .{
442468 .llvm_name = "secure-plt",
443469 .description = "Enable secure plt mode",
......@@ -696,6 +722,7 @@ pub const cpu = struct {
696722 .ppc_postra_sched,
697723 .ppc_prera_sched,
698724 .predictable_select_expensive,
725 .quadword_atomics,
699726 .recipprec,
700727 .stfiwx,
701728 .two_const_nr,
......@@ -790,6 +817,7 @@ pub const cpu = struct {
790817 .fuse_addis_load,
791818 .htm,
792819 .icbt,
820 .isa_v207_instructions,
793821 .isel,
794822 .ldbrx,
795823 .lfiwax,
......@@ -798,6 +826,7 @@ pub const cpu = struct {
798826 .popcntd,
799827 .power8_vector,
800828 .predictable_select_expensive,
829 .quadword_atomics,
801830 .recipprec,
802831 .stfiwx,
803832 .two_const_nr,
......@@ -837,6 +866,7 @@ pub const cpu = struct {
837866 .ppc_postra_sched,
838867 .ppc_prera_sched,
839868 .predictable_select_expensive,
869 .quadword_atomics,
840870 .recipprec,
841871 .stfiwx,
842872 .two_const_nr,
......@@ -989,6 +1019,7 @@ pub const cpu = struct {
9891019 .fuse_addis_load,
9901020 .htm,
9911021 .icbt,
1022 .isa_v207_instructions,
9921023 .isel,
9931024 .ldbrx,
9941025 .lfiwax,
......@@ -997,6 +1028,7 @@ pub const cpu = struct {
9971028 .popcntd,
9981029 .power8_vector,
9991030 .predictable_select_expensive,
1031 .quadword_atomics,
10001032 .recipprec,
10011033 .stfiwx,
10021034 .two_const_nr,
......@@ -1033,6 +1065,7 @@ pub const cpu = struct {
10331065 .ppc_postra_sched,
10341066 .ppc_prera_sched,
10351067 .predictable_select_expensive,
1068 .quadword_atomics,
10361069 .recipprec,
10371070 .stfiwx,
10381071 .two_const_nr,
lib/std/target/riscv.zig+1-1
......@@ -185,7 +185,7 @@ pub const all_features = blk: {
185185 };
186186 result[@enumToInt(Feature.experimental_zvamo)] = .{
187187 .llvm_name = "experimental-zvamo",
188 .description = "'Zvamo'(Vector AMO Operations)",
188 .description = "'Zvamo' (Vector AMO Operations)",
189189 .dependencies = featureSet(&[_]Feature{
190190 .experimental_v,
191191 }),
lib/std/target/systemz.zig+76
......@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
55const CpuModel = std.Target.Cpu.Model;
66
77pub const Feature = enum {
8 bear_enhancement,
89 deflate_conversion,
910 dfp_packed_conversion,
1011 dfp_zoned_conversion,
......@@ -31,8 +32,11 @@ pub const Feature = enum {
3132 miscellaneous_extensions,
3233 miscellaneous_extensions_2,
3334 miscellaneous_extensions_3,
35 nnp_assist,
3436 population_count,
37 processor_activity_instrumentation,
3538 processor_assist,
39 reset_dat_protection,
3640 reset_reference_bits_multiple,
3741 soft_float,
3842 transactional_execution,
......@@ -41,6 +45,7 @@ pub const Feature = enum {
4145 vector_enhancements_2,
4246 vector_packed_decimal,
4347 vector_packed_decimal_enhancement,
48 vector_packed_decimal_enhancement_2,
4449};
4550
4651pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
......@@ -52,6 +57,11 @@ pub const all_features = blk: {
5257 const len = @typeInfo(Feature).Enum.fields.len;
5358 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
5459 var result: [len]CpuFeature = undefined;
60 result[@enumToInt(Feature.bear_enhancement)] = .{
61 .llvm_name = "bear-enhancement",
62 .description = "Assume that the BEAR-enhancement facility is installed",
63 .dependencies = featureSet(&[_]Feature{}),
64 };
5565 result[@enumToInt(Feature.deflate_conversion)] = .{
5666 .llvm_name = "deflate-conversion",
5767 .description = "Assume that the deflate-conversion facility is installed",
......@@ -182,16 +192,31 @@ pub const all_features = blk: {
182192 .description = "Assume that the miscellaneous-extensions facility 3 is installed",
183193 .dependencies = featureSet(&[_]Feature{}),
184194 };
195 result[@enumToInt(Feature.nnp_assist)] = .{
196 .llvm_name = "nnp-assist",
197 .description = "Assume that the NNP-assist facility is installed",
198 .dependencies = featureSet(&[_]Feature{}),
199 };
185200 result[@enumToInt(Feature.population_count)] = .{
186201 .llvm_name = "population-count",
187202 .description = "Assume that the population-count facility is installed",
188203 .dependencies = featureSet(&[_]Feature{}),
189204 };
205 result[@enumToInt(Feature.processor_activity_instrumentation)] = .{
206 .llvm_name = "processor-activity-instrumentation",
207 .description = "Assume that the processor-activity-instrumentation facility is installed",
208 .dependencies = featureSet(&[_]Feature{}),
209 };
190210 result[@enumToInt(Feature.processor_assist)] = .{
191211 .llvm_name = "processor-assist",
192212 .description = "Assume that the processor-assist facility is installed",
193213 .dependencies = featureSet(&[_]Feature{}),
194214 };
215 result[@enumToInt(Feature.reset_dat_protection)] = .{
216 .llvm_name = "reset-dat-protection",
217 .description = "Assume that the reset-DAT-protection facility is installed",
218 .dependencies = featureSet(&[_]Feature{}),
219 };
195220 result[@enumToInt(Feature.reset_reference_bits_multiple)] = .{
196221 .llvm_name = "reset-reference-bits-multiple",
197222 .description = "Assume that the reset-reference-bits-multiple facility is installed",
......@@ -232,6 +257,11 @@ pub const all_features = blk: {
232257 .description = "Assume that the vector packed decimal enhancement facility is installed",
233258 .dependencies = featureSet(&[_]Feature{}),
234259 };
260 result[@enumToInt(Feature.vector_packed_decimal_enhancement_2)] = .{
261 .llvm_name = "vector-packed-decimal-enhancement-2",
262 .description = "Assume that the vector packed decimal enhancement facility 2 is installed",
263 .dependencies = featureSet(&[_]Feature{}),
264 };
235265 const ti = @typeInfo(Feature);
236266 for (result) |*elem, i| {
237267 elem.index = i;
......@@ -368,6 +398,52 @@ pub const cpu = struct {
368398 .vector_packed_decimal_enhancement,
369399 }),
370400 };
401 pub const arch14 = CpuModel{
402 .name = "arch14",
403 .llvm_name = "arch14",
404 .features = featureSet(&[_]Feature{
405 .bear_enhancement,
406 .deflate_conversion,
407 .dfp_packed_conversion,
408 .dfp_zoned_conversion,
409 .distinct_ops,
410 .enhanced_dat_2,
411 .enhanced_sort,
412 .execution_hint,
413 .fast_serialization,
414 .fp_extension,
415 .guarded_storage,
416 .high_word,
417 .insert_reference_bits_multiple,
418 .interlocked_access1,
419 .load_and_trap,
420 .load_and_zero_rightmost_byte,
421 .load_store_on_cond,
422 .load_store_on_cond_2,
423 .message_security_assist_extension3,
424 .message_security_assist_extension4,
425 .message_security_assist_extension5,
426 .message_security_assist_extension7,
427 .message_security_assist_extension8,
428 .message_security_assist_extension9,
429 .miscellaneous_extensions,
430 .miscellaneous_extensions_2,
431 .miscellaneous_extensions_3,
432 .nnp_assist,
433 .population_count,
434 .processor_activity_instrumentation,
435 .processor_assist,
436 .reset_dat_protection,
437 .reset_reference_bits_multiple,
438 .transactional_execution,
439 .vector,
440 .vector_enhancements_1,
441 .vector_enhancements_2,
442 .vector_packed_decimal,
443 .vector_packed_decimal_enhancement,
444 .vector_packed_decimal_enhancement_2,
445 }),
446 };
371447 pub const arch8 = CpuModel{
372448 .name = "arch8",
373449 .llvm_name = "arch8",
lib/std/target/wasm.zig-8
......@@ -15,7 +15,6 @@ pub const Feature = enum {
1515 sign_ext,
1616 simd128,
1717 tail_call,
18 unimplemented_simd128,
1918};
2019
2120pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
......@@ -77,13 +76,6 @@ pub const all_features = blk: {
7776 .description = "Enable tail call instructions",
7877 .dependencies = featureSet(&[_]Feature{}),
7978 };
80 result[@enumToInt(Feature.unimplemented_simd128)] = .{
81 .llvm_name = "unimplemented-simd128",
82 .description = "Enable 128-bit SIMD not yet implemented in engines",
83 .dependencies = featureSet(&[_]Feature{
84 .simd128,
85 }),
86 };
8779 const ti = @typeInfo(Feature);
8880 for (result) |*elem, i| {
8981 elem.index = i;
lib/std/target/x86.zig+134-33
......@@ -55,10 +55,12 @@ pub const Feature = enum {
5555 fast_gather,
5656 fast_hops,
5757 fast_lzcnt,
58 fast_movbe,
5859 fast_scalar_fsqrt,
5960 fast_scalar_shift_masks,
6061 fast_shld_rotate,
61 fast_variable_shuffle,
62 fast_variable_crosslane_shuffle,
63 fast_variable_perlane_shuffle,
6264 fast_vector_fsqrt,
6365 fast_vector_shift_masks,
6466 fma,
......@@ -458,6 +460,11 @@ pub const all_features = blk: {
458460 .description = "LZCNT instructions are as fast as most simple integer ops",
459461 .dependencies = featureSet(&[_]Feature{}),
460462 };
463 result[@enumToInt(Feature.fast_movbe)] = .{
464 .llvm_name = "fast-movbe",
465 .description = "Prefer a movbe over a single-use load + bswap / single-use bswap + store",
466 .dependencies = featureSet(&[_]Feature{}),
467 };
461468 result[@enumToInt(Feature.fast_scalar_fsqrt)] = .{
462469 .llvm_name = "fast-scalar-fsqrt",
463470 .description = "Scalar SQRT is fast (disable Newton-Raphson)",
......@@ -473,9 +480,14 @@ pub const all_features = blk: {
473480 .description = "SHLD can be used as a faster rotate",
474481 .dependencies = featureSet(&[_]Feature{}),
475482 };
476 result[@enumToInt(Feature.fast_variable_shuffle)] = .{
477 .llvm_name = "fast-variable-shuffle",
478 .description = "Shuffles with variable masks are fast",
483 result[@enumToInt(Feature.fast_variable_crosslane_shuffle)] = .{
484 .llvm_name = "fast-variable-crosslane-shuffle",
485 .description = "Cross-lane shuffles with variable masks are fast",
486 .dependencies = featureSet(&[_]Feature{}),
487 };
488 result[@enumToInt(Feature.fast_variable_perlane_shuffle)] = .{
489 .llvm_name = "fast-variable-perlane-shuffle",
490 .description = "Per-lane shuffles with variable masks are fast",
479491 .dependencies = featureSet(&[_]Feature{}),
480492 };
481493 result[@enumToInt(Feature.fast_vector_fsqrt)] = .{
......@@ -1010,26 +1022,27 @@ pub const cpu = struct {
10101022 .features = featureSet(&[_]Feature{
10111023 .@"64bit",
10121024 .adx,
1013 .aes,
10141025 .avxvnni,
10151026 .bmi,
10161027 .bmi2,
10171028 .cldemote,
10181029 .clflushopt,
1030 .clwb,
10191031 .cmov,
10201032 .cx16,
1021 .ermsb,
10221033 .f16c,
10231034 .false_deps_popcnt,
10241035 .fast_15bytenop,
10251036 .fast_gather,
10261037 .fast_scalar_fsqrt,
10271038 .fast_shld_rotate,
1028 .fast_variable_shuffle,
1039 .fast_variable_crosslane_shuffle,
1040 .fast_variable_perlane_shuffle,
10291041 .fast_vector_fsqrt,
10301042 .fma,
10311043 .fsgsbase,
10321044 .fxsr,
1045 .gfni,
10331046 .hreset,
10341047 .idivq_to_divl,
10351048 .invpcid,
......@@ -1037,19 +1050,27 @@ pub const cpu = struct {
10371050 .macrofusion,
10381051 .mmx,
10391052 .movbe,
1053 .movdir64b,
1054 .movdiri,
10401055 .nopl,
1041 .pclmul,
1056 .pconfig,
1057 .pku,
10421058 .popcnt,
10431059 .prfchw,
10441060 .ptwrite,
1061 .rdpid,
10451062 .rdrnd,
10461063 .rdseed,
10471064 .sahf,
10481065 .serialize,
1049 .sgx,
1066 .sha,
1067 .shstk,
10501068 .slow_3ops_lea,
1069 .vaes,
1070 .vpclmulqdq,
10511071 .vzeroupper,
10521072 .waitpkg,
1073 .widekl,
10531074 .x87,
10541075 .xsavec,
10551076 .xsaveopt,
......@@ -1292,6 +1313,7 @@ pub const cpu = struct {
12921313 .f16c,
12931314 .fast_11bytenop,
12941315 .fast_bextr,
1316 .fast_movbe,
12951317 .fast_scalar_shift_masks,
12961318 .fma,
12971319 .fxsr,
......@@ -1324,6 +1346,7 @@ pub const cpu = struct {
13241346 .f16c,
13251347 .fast_11bytenop,
13261348 .fast_bextr,
1349 .fast_movbe,
13271350 .fast_scalar_shift_masks,
13281351 .fma,
13291352 .fsgsbase,
......@@ -1359,6 +1382,7 @@ pub const cpu = struct {
13591382 .f16c,
13601383 .fast_11bytenop,
13611384 .fast_bextr,
1385 .fast_movbe,
13621386 .fast_scalar_shift_masks,
13631387 .fma,
13641388 .fsgsbase,
......@@ -1424,7 +1448,8 @@ pub const cpu = struct {
14241448 .fast_15bytenop,
14251449 .fast_scalar_fsqrt,
14261450 .fast_shld_rotate,
1427 .fast_variable_shuffle,
1451 .fast_variable_crosslane_shuffle,
1452 .fast_variable_perlane_shuffle,
14281453 .fma,
14291454 .fsgsbase,
14301455 .fxsr,
......@@ -1485,6 +1510,7 @@ pub const cpu = struct {
14851510 .fast_bextr,
14861511 .fast_hops,
14871512 .fast_lzcnt,
1513 .fast_movbe,
14881514 .fast_scalar_shift_masks,
14891515 .fast_vector_shift_masks,
14901516 .fxsr,
......@@ -1548,7 +1574,8 @@ pub const cpu = struct {
15481574 .fast_gather,
15491575 .fast_scalar_fsqrt,
15501576 .fast_shld_rotate,
1551 .fast_variable_shuffle,
1577 .fast_variable_crosslane_shuffle,
1578 .fast_variable_perlane_shuffle,
15521579 .fast_vector_fsqrt,
15531580 .fsgsbase,
15541581 .fxsr,
......@@ -1567,7 +1594,6 @@ pub const cpu = struct {
15671594 .rdrnd,
15681595 .rdseed,
15691596 .sahf,
1570 .sgx,
15711597 .sha,
15721598 .slow_3ops_lea,
15731599 .vzeroupper,
......@@ -1601,7 +1627,8 @@ pub const cpu = struct {
16011627 .fast_gather,
16021628 .fast_scalar_fsqrt,
16031629 .fast_shld_rotate,
1604 .fast_variable_shuffle,
1630 .fast_variable_crosslane_shuffle,
1631 .fast_variable_perlane_shuffle,
16051632 .fast_vector_fsqrt,
16061633 .fsgsbase,
16071634 .fxsr,
......@@ -1652,7 +1679,8 @@ pub const cpu = struct {
16521679 .fast_gather,
16531680 .fast_scalar_fsqrt,
16541681 .fast_shld_rotate,
1655 .fast_variable_shuffle,
1682 .fast_variable_crosslane_shuffle,
1683 .fast_variable_perlane_shuffle,
16561684 .fast_vector_fsqrt,
16571685 .fsgsbase,
16581686 .fxsr,
......@@ -1714,7 +1742,8 @@ pub const cpu = struct {
17141742 .fast_15bytenop,
17151743 .fast_scalar_fsqrt,
17161744 .fast_shld_rotate,
1717 .fast_variable_shuffle,
1745 .fast_variable_crosslane_shuffle,
1746 .fast_variable_perlane_shuffle,
17181747 .fma,
17191748 .fsgsbase,
17201749 .fxsr,
......@@ -1844,6 +1873,7 @@ pub const cpu = struct {
18441873 .cmov,
18451874 .cx16,
18461875 .false_deps_popcnt,
1876 .fast_movbe,
18471877 .fsgsbase,
18481878 .fxsr,
18491879 .mmx,
......@@ -1877,6 +1907,7 @@ pub const cpu = struct {
18771907 .clflushopt,
18781908 .cmov,
18791909 .cx16,
1910 .fast_movbe,
18801911 .fsgsbase,
18811912 .fxsr,
18821913 .mmx,
......@@ -1890,7 +1921,6 @@ pub const cpu = struct {
18901921 .rdrnd,
18911922 .rdseed,
18921923 .sahf,
1893 .sgx,
18941924 .sha,
18951925 .slow_incdec,
18961926 .slow_lea,
......@@ -1921,7 +1951,8 @@ pub const cpu = struct {
19211951 .fast_15bytenop,
19221952 .fast_scalar_fsqrt,
19231953 .fast_shld_rotate,
1924 .fast_variable_shuffle,
1954 .fast_variable_crosslane_shuffle,
1955 .fast_variable_perlane_shuffle,
19251956 .fma,
19261957 .fsgsbase,
19271958 .fxsr,
......@@ -1960,7 +1991,6 @@ pub const cpu = struct {
19601991 .bmi,
19611992 .bmi2,
19621993 .clflushopt,
1963 .clwb,
19641994 .cmov,
19651995 .cx16,
19661996 .ermsb,
......@@ -1968,7 +1998,8 @@ pub const cpu = struct {
19681998 .fast_gather,
19691999 .fast_scalar_fsqrt,
19702000 .fast_shld_rotate,
1971 .fast_variable_shuffle,
2001 .fast_variable_crosslane_shuffle,
2002 .fast_variable_perlane_shuffle,
19722003 .fast_vector_fsqrt,
19732004 .fsgsbase,
19742005 .fsrm,
......@@ -1989,7 +2020,6 @@ pub const cpu = struct {
19892020 .rdrnd,
19902021 .rdseed,
19912022 .sahf,
1992 .sgx,
19932023 .sha,
19942024 .slow_3ops_lea,
19952025 .vaes,
......@@ -2027,7 +2057,8 @@ pub const cpu = struct {
20272057 .fast_gather,
20282058 .fast_scalar_fsqrt,
20292059 .fast_shld_rotate,
2030 .fast_variable_shuffle,
2060 .fast_variable_crosslane_shuffle,
2061 .fast_variable_perlane_shuffle,
20312062 .fast_vector_fsqrt,
20322063 .fsgsbase,
20332064 .fsrm,
......@@ -2049,7 +2080,6 @@ pub const cpu = struct {
20492080 .rdrnd,
20502081 .rdseed,
20512082 .sahf,
2052 .sgx,
20532083 .sha,
20542084 .slow_3ops_lea,
20552085 .vaes,
......@@ -2175,6 +2205,7 @@ pub const cpu = struct {
21752205 .cmov,
21762206 .cx16,
21772207 .fast_gather,
2208 .fast_movbe,
21782209 .fsgsbase,
21792210 .fxsr,
21802211 .idivq_to_divl,
......@@ -2214,6 +2245,7 @@ pub const cpu = struct {
22142245 .cmov,
22152246 .cx16,
22162247 .fast_gather,
2248 .fast_movbe,
22172249 .fsgsbase,
22182250 .fxsr,
22192251 .idivq_to_divl,
......@@ -2472,6 +2504,64 @@ pub const cpu = struct {
24722504 .x87,
24732505 }),
24742506 };
2507 pub const rocketlake = CpuModel{
2508 .name = "rocketlake",
2509 .llvm_name = "rocketlake",
2510 .features = featureSet(&[_]Feature{
2511 .@"64bit",
2512 .adx,
2513 .avx512bitalg,
2514 .avx512cd,
2515 .avx512dq,
2516 .avx512ifma,
2517 .avx512vbmi,
2518 .avx512vbmi2,
2519 .avx512vl,
2520 .avx512vnni,
2521 .avx512vpopcntdq,
2522 .bmi,
2523 .bmi2,
2524 .clflushopt,
2525 .cmov,
2526 .cx16,
2527 .ermsb,
2528 .fast_15bytenop,
2529 .fast_gather,
2530 .fast_scalar_fsqrt,
2531 .fast_shld_rotate,
2532 .fast_variable_crosslane_shuffle,
2533 .fast_variable_perlane_shuffle,
2534 .fast_vector_fsqrt,
2535 .fsgsbase,
2536 .fsrm,
2537 .fxsr,
2538 .gfni,
2539 .idivq_to_divl,
2540 .invpcid,
2541 .lzcnt,
2542 .macrofusion,
2543 .mmx,
2544 .movbe,
2545 .nopl,
2546 .pku,
2547 .popcnt,
2548 .prefer_256_bit,
2549 .prfchw,
2550 .rdpid,
2551 .rdrnd,
2552 .rdseed,
2553 .sahf,
2554 .sha,
2555 .slow_3ops_lea,
2556 .vaes,
2557 .vpclmulqdq,
2558 .vzeroupper,
2559 .x87,
2560 .xsavec,
2561 .xsaveopt,
2562 .xsaves,
2563 }),
2564 };
24752565 pub const sandybridge = CpuModel{
24762566 .name = "sandybridge",
24772567 .llvm_name = "sandybridge",
......@@ -2532,7 +2622,8 @@ pub const cpu = struct {
25322622 .fast_gather,
25332623 .fast_scalar_fsqrt,
25342624 .fast_shld_rotate,
2535 .fast_variable_shuffle,
2625 .fast_variable_crosslane_shuffle,
2626 .fast_variable_perlane_shuffle,
25362627 .fast_vector_fsqrt,
25372628 .fsgsbase,
25382629 .fsrm,
......@@ -2558,7 +2649,6 @@ pub const cpu = struct {
25582649 .rdseed,
25592650 .sahf,
25602651 .serialize,
2561 .sgx,
25622652 .sha,
25632653 .shstk,
25642654 .slow_3ops_lea,
......@@ -2584,6 +2674,7 @@ pub const cpu = struct {
25842674 .cx16,
25852675 .false_deps_popcnt,
25862676 .fast_7bytenop,
2677 .fast_movbe,
25872678 .fxsr,
25882679 .idivq_to_divl,
25892680 .mmx,
......@@ -2626,7 +2717,8 @@ pub const cpu = struct {
26262717 .fast_gather,
26272718 .fast_scalar_fsqrt,
26282719 .fast_shld_rotate,
2629 .fast_variable_shuffle,
2720 .fast_variable_crosslane_shuffle,
2721 .fast_variable_perlane_shuffle,
26302722 .fast_vector_fsqrt,
26312723 .fsgsbase,
26322724 .fxsr,
......@@ -2673,7 +2765,8 @@ pub const cpu = struct {
26732765 .fast_gather,
26742766 .fast_scalar_fsqrt,
26752767 .fast_shld_rotate,
2676 .fast_variable_shuffle,
2768 .fast_variable_crosslane_shuffle,
2769 .fast_variable_perlane_shuffle,
26772770 .fast_vector_fsqrt,
26782771 .fma,
26792772 .fsgsbase,
......@@ -2691,7 +2784,6 @@ pub const cpu = struct {
26912784 .rdrnd,
26922785 .rdseed,
26932786 .sahf,
2694 .sgx,
26952787 .slow_3ops_lea,
26962788 .vzeroupper,
26972789 .x87,
......@@ -2723,7 +2815,8 @@ pub const cpu = struct {
27232815 .fast_gather,
27242816 .fast_scalar_fsqrt,
27252817 .fast_shld_rotate,
2726 .fast_variable_shuffle,
2818 .fast_variable_crosslane_shuffle,
2819 .fast_variable_perlane_shuffle,
27272820 .fast_vector_fsqrt,
27282821 .fsgsbase,
27292822 .fxsr,
......@@ -2759,6 +2852,7 @@ pub const cpu = struct {
27592852 .cx16,
27602853 .false_deps_popcnt,
27612854 .fast_7bytenop,
2855 .fast_movbe,
27622856 .fxsr,
27632857 .idivq_to_divl,
27642858 .mmx,
......@@ -2805,7 +2899,8 @@ pub const cpu = struct {
28052899 .fast_gather,
28062900 .fast_scalar_fsqrt,
28072901 .fast_shld_rotate,
2808 .fast_variable_shuffle,
2902 .fast_variable_crosslane_shuffle,
2903 .fast_variable_perlane_shuffle,
28092904 .fast_vector_fsqrt,
28102905 .fsgsbase,
28112906 .fsrm,
......@@ -2828,7 +2923,6 @@ pub const cpu = struct {
28282923 .rdrnd,
28292924 .rdseed,
28302925 .sahf,
2831 .sgx,
28322926 .sha,
28332927 .shstk,
28342928 .slow_3ops_lea,
......@@ -2851,6 +2945,7 @@ pub const cpu = struct {
28512945 .clwb,
28522946 .cmov,
28532947 .cx16,
2948 .fast_movbe,
28542949 .fsgsbase,
28552950 .fxsr,
28562951 .gfni,
......@@ -2865,7 +2960,6 @@ pub const cpu = struct {
28652960 .rdrnd,
28662961 .rdseed,
28672962 .sahf,
2868 .sgx,
28692963 .sha,
28702964 .slow_incdec,
28712965 .slow_lea,
......@@ -2978,7 +3072,8 @@ pub const cpu = struct {
29783072 .fast_15bytenop,
29793073 .fast_scalar_fsqrt,
29803074 .fast_shld_rotate,
2981 .fast_variable_shuffle,
3075 .fast_variable_crosslane_shuffle,
3076 .fast_variable_perlane_shuffle,
29823077 .fma,
29833078 .fxsr,
29843079 .idivq_to_divl,
......@@ -3013,7 +3108,8 @@ pub const cpu = struct {
30133108 .fast_gather,
30143109 .fast_scalar_fsqrt,
30153110 .fast_shld_rotate,
3016 .fast_variable_shuffle,
3111 .fast_variable_crosslane_shuffle,
3112 .fast_variable_perlane_shuffle,
30173113 .fast_vector_fsqrt,
30183114 .fxsr,
30193115 .idivq_to_divl,
......@@ -3065,6 +3161,7 @@ pub const cpu = struct {
30653161 .fast_15bytenop,
30663162 .fast_bextr,
30673163 .fast_lzcnt,
3164 .fast_movbe,
30683165 .fast_scalar_shift_masks,
30693166 .fma,
30703167 .fsgsbase,
......@@ -3110,6 +3207,7 @@ pub const cpu = struct {
31103207 .fast_15bytenop,
31113208 .fast_bextr,
31123209 .fast_lzcnt,
3210 .fast_movbe,
31133211 .fast_scalar_shift_masks,
31143212 .fma,
31153213 .fsgsbase,
......@@ -3156,13 +3254,16 @@ pub const cpu = struct {
31563254 .fast_15bytenop,
31573255 .fast_bextr,
31583256 .fast_lzcnt,
3257 .fast_movbe,
31593258 .fast_scalar_shift_masks,
3259 .fast_variable_perlane_shuffle,
31603260 .fma,
31613261 .fsgsbase,
31623262 .fsrm,
31633263 .fxsr,
31643264 .invpcid,
31653265 .lzcnt,
3266 .macrofusion,
31663267 .mmx,
31673268 .movbe,
31683269 .mwaitx,
tools/update_cpu_features.zig-2
......@@ -219,7 +219,6 @@ const llvm_targets = [_]LlvmTarget{
219219 "use_postra_scheduler",
220220 "use_reciprocal_square_root",
221221 "v8a",
222 "zcz_fp",
223222 },
224223 },
225224 .{
......@@ -236,7 +235,6 @@ const llvm_targets = [_]LlvmTarget{
236235 "slow_paired_128",
237236 "use_postra_scheduler",
238237 "v8a",
239 "zcz_fp",
240238 },
241239 },
242240 .{