authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-02-17 22:49:01+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-02-18 09:14:15+01:00
log83744b92a1d1a923fb3faf3aca9d0f57b09cb97d
treeb5310b2971bd6bc1204b26fe4a590bc74bb1fed4
parent97c25fb8d049ebcced9f29241516c51e480fb8a0

x64: fix wrong regalloc with inst tracking in airCmp

We return compare flags rather than a register which than wrongly cheats the regalloc into thinking we carry the instruction in the register which we do not.

1 files changed, 10 insertions(+), 3 deletions(-)

src/arch/x86_64/CodeGen.zig+10-3
......@@ -1724,7 +1724,13 @@ fn airUnaryMath(self: *Self, inst: Air.Inst.Index) !void {
17241724 return self.finishAir(inst, result, .{ un_op, .none, .none });
17251725}
17261726
1727fn reuseOperand(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, op_index: Liveness.OperandInt, mcv: MCValue) bool {
1727fn reuseOperand(
1728 self: *Self,
1729 inst: Air.Inst.Index,
1730 operand: Air.Inst.Ref,
1731 op_index: Liveness.OperandInt,
1732 mcv: MCValue,
1733) bool {
17281734 if (!self.liveness.operandDies(inst, op_index))
17291735 return false;
17301736
......@@ -2267,13 +2273,14 @@ fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs:
22672273 // A potential opportunity for future optimization here would be keeping track
22682274 // of the fact that the instruction is available both as an immediate
22692275 // and as a register.
2276 // TODO consolidate with limitImmediateType() function
22702277 switch (src_mcv) {
22712278 .immediate => |imm| {
22722279 if (imm > math.maxInt(u31)) {
22732280 dst_mcv.freezeIfRegister(&self.register_manager);
22742281 defer dst_mcv.unfreezeIfRegister(&self.register_manager);
22752282
2276 src_mcv = try self.copyToNewRegister(inst, Type.u64, src_mcv);
2283 src_mcv = MCValue{ .register = try self.copyToTmpRegister(Type.usize, src_mcv) };
22772284 }
22782285 },
22792286 else => {},
......@@ -2907,7 +2914,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
29072914 // Either one, but not both, can be a memory operand.
29082915 // Source operand can be an immediate, 8 bits or 32 bits.
29092916 const dst_mcv = if (lhs.isImmediate() or (lhs.isMemory() and rhs.isMemory()))
2910 try self.copyToNewRegister(inst, ty, lhs)
2917 MCValue{ .register = try self.copyToTmpRegister(ty, lhs) }
29112918 else
29122919 lhs;
29132920 // This instruction supports only signed 32-bit immediates at most.