authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 10:09:01+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 10:10:06+02:00
log8e6ed0fedf350cd636349ee0bc75d733801a72dd
treee0d7b7ba955c576e87023eafd68e24737921dcd4
parent694c848c3e48176fb81941f0186d53100211e64c
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

compiler_rt.fmv: avoid depending on @import("aarch64_outline_atomics.zig").__aarch64_have_lse_atomics

3 files changed, 5 insertions(+), 3 deletions(-)

lib/compiler_rt/aarch64_outline_atomics.zig+1-1
......@@ -9,7 +9,7 @@ const always_has_lse = builtin.cpu.has(.aarch64, .lse);
99/// It is intentionally not exported in order to make the machine code that
1010/// uses it a statically predicted direct branch rather than using the PLT,
1111/// which ARM is concerned would have too much overhead.
12pub var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);
12var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);
1313
1414fn __aarch64_cas1_relax() align(16) callconv(.naked) void {
1515 @setRuntimeSafety(false);
lib/compiler_rt/fmv.zig+3-1
......@@ -18,7 +18,7 @@ comptime {
1818const aarch64 = struct {
1919 comptime {
2020 symbol(&__aarch64_cpu_features, "__aarch64_cpu_features");
21 symbol(&@import("aarch64_outline_atomics.zig").__aarch64_have_lse_atomics, "__aarch64_have_lse_atomics");
21 symbol(&__aarch64_have_lse_atomics, "__aarch64_have_lse_atomics");
2222 symbol(&__init_cpu_features_resolver, "__init_cpu_features_resolver");
2323 }
2424
......@@ -28,6 +28,8 @@ const aarch64 = struct {
2828 .features = 0,
2929 };
3030
31 var __aarch64_have_lse_atomics: bool = false;
32
3133 const __init_cpu_features_resolver = switch (builtin.target.os.tag) {
3234 .fuchsia,
3335 .driverkit,
tools/gen_outline_atomics.zig+1-1
......@@ -32,7 +32,7 @@ pub fn main(init: std.process.Init) !void {
3232 \\/// It is intentionally not exported in order to make the machine code that
3333 \\/// uses it a statically predicted direct branch rather than using the PLT,
3434 \\/// which ARM is concerned would have too much overhead.
35 \\pub var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);
35 \\var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);
3636 \\
3737 \\
3838 );