authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-06 09:09:30+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-06 10:31:01+02:00
log93cb0f1552b0c7285ef22f6713239675170a348b
tree429076b478ea9cb882966a9486534eaeb5b356c2
parentd30609829eb744b28a26a5161c2788dfdef3618d
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.zig.system.openbsd: implement powerpc CPU model detection

ref https://codeberg.org/ziglang/zig/issues/36726

1 files changed, 55 insertions(+), 0 deletions(-)

lib/std/zig/system/openbsd.zig+55
...@@ -43,9 +43,64 @@ const aarch64 = struct {...@@ -43,9 +43,64 @@ const aarch64 = struct {
43 }43 }
44};44};
4545
46const powerpc = struct {
47 const models = .{
48 .{ "601", &std.Target.powerpc.cpu.@"601" },
49 .{ "603ev", &std.Target.powerpc.cpu.@"603ev" },
50 .{ "603e", &std.Target.powerpc.cpu.@"603e" },
51 .{ "603", &std.Target.powerpc.cpu.@"603" },
52 .{ "604ev", &std.Target.powerpc.cpu.@"604e" },
53 .{ "604", &std.Target.powerpc.cpu.@"604" },
54 .{ "7400", &std.Target.powerpc.cpu.@"7400" },
55 .{ "7410", &std.Target.powerpc.cpu.@"7400" },
56 .{ "7450", &std.Target.powerpc.cpu.@"7450" },
57 .{ "7451", &std.Target.powerpc.cpu.@"7450" },
58 .{ "7455", &std.Target.powerpc.cpu.@"7450" },
59 .{ "7457", &std.Target.powerpc.cpu.@"7450" },
60 .{ "7447A", &std.Target.powerpc.cpu.@"7450" },
61 .{ "7448", &std.Target.powerpc.cpu.@"7450" },
62 .{ "750FX", &std.Target.powerpc.cpu.@"750" },
63 .{ "750", &std.Target.powerpc.cpu.@"750" },
64 .{ "970FX", &std.Target.powerpc.cpu.@"970" },
65 .{ "970MP", &std.Target.powerpc.cpu.@"970" },
66 .{ "970", &std.Target.powerpc.cpu.@"970" },
67 .{ "IBM POWER8E", &std.Target.powerpc.cpu.pwr8 },
68 .{ "IBM POWER8NVL", &std.Target.powerpc.cpu.pwr8 },
69 .{ "IBM POWER8", &std.Target.powerpc.cpu.pwr8 },
70 .{ "IBM POWER9P", &std.Target.powerpc.cpu.pwr9 },
71 .{ "IBM POWER9", &std.Target.powerpc.cpu.pwr9 },
72 };
73
74 fn detectNativeCpu(arch: std.Target.Cpu.Arch) ?std.Target.Cpu {
75 const mib: [2]c_int = [_]c_int{
76 std.c.CTL.HW,
77 std.c.HW.MODEL,
78 };
79 var buf: [64:0]u8 = undefined;
80 var len: usize = buf.len + 1;
81
82 std.posix.sysctl(&mib, &buf, &len, null, 0) catch |err| switch (err) {
83 error.NameTooLong => unreachable,
84 error.PermissionDenied => unreachable,
85 error.SystemResources => unreachable,
86 error.UnknownName => unreachable,
87 error.Unexpected => return null,
88 };
89
90 const name = buf[0 .. len - 1 :0];
91
92 inline for (models) |pair| {
93 if (std.mem.startsWith(u8, name, pair[0])) return pair[1].toCpu(arch);
94 }
95
96 return null;
97 }
98};
99
46pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu {100pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu {
47 return switch (native_arch) {101 return switch (native_arch) {
48 .aarch64 => aarch64.detectNativeCpuAndFeatures(native_arch),102 .aarch64 => aarch64.detectNativeCpuAndFeatures(native_arch),
103 .powerpc, .powerpc64 => powerpc.detectNativeCpu(native_arch),
49 else => null,104 else => null,
50 };105 };
51}106}