authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-01-24 00:22:43+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-02-17 19:17:55+01:00
logb541a7af1155a984bd41008ea337030d0373e0ea
treef8fb36f0e10cdadb8734254610567f799db206e3
parent55c46870b23ac16670beaa3ff1c082b703738307
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove Cpu.Arch.spu_2.

This was for a hobby project that appears to be dormant for now. This can be added back if the project is resumed in the future.

8 files changed, 0 insertions(+), 21 deletions(-)

lib/compiler/aro/aro/target.zig-4
...@@ -461,7 +461,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {...@@ -461,7 +461,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
461 .amdgcn,461 .amdgcn,
462 .avr,462 .avr,
463 .msp430,463 .msp430,
464 .spu_2,
465 .ve,464 .ve,
466 .bpfel,465 .bpfel,
467 .bpfeb,466 .bpfeb,
...@@ -522,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {...@@ -522,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
522 .lanai,521 .lanai,
523 .m68k,522 .m68k,
524 .msp430,523 .msp430,
525 .spu_2,
526 .xcore,524 .xcore,
527 .xtensa,525 .xtensa,
528 => return null,526 => return null,
...@@ -620,8 +618,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {...@@ -620,8 +618,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
620 .wasm32 => "wasm32",618 .wasm32 => "wasm32",
621 .wasm64 => "wasm64",619 .wasm64 => "wasm64",
622 .ve => "ve",620 .ve => "ve",
623 // Note: spu_2 is not supported in LLVM; this is the Zig arch name
624 .spu_2 => "spu_2",
625 };621 };
626 writer.writeAll(llvm_arch) catch unreachable;622 writer.writeAll(llvm_arch) catch unreachable;
627 writer.writeByte('-') catch unreachable;623 writer.writeByte('-') catch unreachable;
lib/std/Target.zig-9
...@@ -1085,7 +1085,6 @@ pub fn toElfMachine(target: Target) std.elf.EM {...@@ -1085,7 +1085,6 @@ pub fn toElfMachine(target: Target) std.elf.EM {
1085 .s390x => .S390,1085 .s390x => .S390,
1086 .sparc => if (Target.sparc.featureSetHas(target.cpu.features, .v9)) .SPARC32PLUS else .SPARC,1086 .sparc => if (Target.sparc.featureSetHas(target.cpu.features, .v9)) .SPARC32PLUS else .SPARC,
1087 .sparc64 => .SPARCV9,1087 .sparc64 => .SPARCV9,
1088 .spu_2 => .SPU_2,
1089 .ve => .VE,1088 .ve => .VE,
1090 .x86 => if (target.os.tag == .elfiamcu) .IAMCU else .@"386",1089 .x86 => if (target.os.tag == .elfiamcu) .IAMCU else .@"386",
1091 .x86_64 => .X86_64,1090 .x86_64 => .X86_64,
...@@ -1148,7 +1147,6 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {...@@ -1148,7 +1147,6 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {
1148 .spirv,1147 .spirv,
1149 .spirv32,1148 .spirv32,
1150 .spirv64,1149 .spirv64,
1151 .spu_2,
1152 .ve,1150 .ve,
1153 .wasm32,1151 .wasm32,
1154 .wasm64,1152 .wasm64,
...@@ -1378,7 +1376,6 @@ pub const Cpu = struct {...@@ -1378,7 +1376,6 @@ pub const Cpu = struct {
1378 spirv,1376 spirv,
1379 spirv32,1377 spirv32,
1380 spirv64,1378 spirv64,
1381 spu_2,
1382 ve,1379 ve,
1383 wasm32,1380 wasm32,
1384 wasm64,1381 wasm64,
...@@ -1564,7 +1561,6 @@ pub const Cpu = struct {...@@ -1564,7 +1561,6 @@ pub const Cpu = struct {
1564 .xcore,1561 .xcore,
1565 .thumb,1562 .thumb,
1566 .ve,1563 .ve,
1567 .spu_2,
1568 // GPU bitness is opaque. For now, assume little endian.1564 // GPU bitness is opaque. For now, assume little endian.
1569 .spirv,1565 .spirv,
1570 .spirv32,1566 .spirv32,
...@@ -1954,7 +1950,6 @@ pub const Cpu = struct {...@@ -1954,7 +1950,6 @@ pub const Cpu = struct {
1954 .xtensa => &xtensa.cpu.generic,1950 .xtensa => &xtensa.cpu.generic,
19551951
1956 .kalimba,1952 .kalimba,
1957 .spu_2,
1958 => &S.generic_model,1953 => &S.generic_model,
1959 };1954 };
1960 }1955 }
...@@ -2627,7 +2622,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {...@@ -2627,7 +2622,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
2627 return switch (cpu.arch) {2622 return switch (cpu.arch) {
2628 .avr,2623 .avr,
2629 .msp430,2624 .msp430,
2630 .spu_2,
2631 => 16,2625 => 16,
26322626
2633 .arc,2627 .arc,
...@@ -3164,7 +3158,6 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {...@@ -3164,7 +3158,6 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {
3164 .x86,3158 .x86,
3165 .xcore,3159 .xcore,
3166 .kalimba,3160 .kalimba,
3167 .spu_2,
3168 .xtensa,3161 .xtensa,
3169 .propeller1,3162 .propeller1,
3170 .propeller2,3163 .propeller2,
...@@ -3260,7 +3253,6 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {...@@ -3260,7 +3253,6 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {
3260 .csky,3253 .csky,
3261 .xcore,3254 .xcore,
3262 .kalimba,3255 .kalimba,
3263 .spu_2,
3264 .xtensa,3256 .xtensa,
3265 .propeller1,3257 .propeller1,
3266 .propeller2,3258 .propeller2,
...@@ -3371,7 +3363,6 @@ pub fn cCallingConvention(target: Target) ?std.builtin.CallingConvention {...@@ -3371,7 +3363,6 @@ pub fn cCallingConvention(target: Target) ?std.builtin.CallingConvention {
3371 .propeller1 => .{ .propeller1_sysv = .{} },3363 .propeller1 => .{ .propeller1_sysv = .{} },
3372 .propeller2 => .{ .propeller2_sysv = .{} },3364 .propeller2 => .{ .propeller2_sysv = .{} },
3373 .s390x => .{ .s390x_sysv = .{} },3365 .s390x => .{ .s390x_sysv = .{} },
3374 .spu_2 => null,
3375 .ve => .{ .ve_sysv = .{} },3366 .ve => .{ .ve_sysv = .{} },
3376 .xcore => .{ .xcore_xs1 = .{} },3367 .xcore => .{ .xcore_xs1 = .{} },
3377 .xtensa => .{ .xtensa_call0 = .{} },3368 .xtensa => .{ .xtensa_call0 = .{} },
lib/std/debug/Dwarf/abi.zig-1
...@@ -17,7 +17,6 @@ pub fn supportsUnwinding(target: std.Target) bool {...@@ -17,7 +17,6 @@ pub fn supportsUnwinding(target: std.Target) bool {
17 .spirv,17 .spirv,
18 .spirv32,18 .spirv32,
19 .spirv64,19 .spirv64,
20 .spu_2,
21 => false,20 => false,
2221
23 // Enabling this causes relocation errors such as:22 // Enabling this causes relocation errors such as:
lib/std/elf.zig-2
...@@ -1178,8 +1178,6 @@ pub const EM = enum(u16) {...@@ -1178,8 +1178,6 @@ pub const EM = enum(u16) {
1178 MIPS_RS3_LE = 10,1178 MIPS_RS3_LE = 10,
1179 /// Old version of Sparc v9, from before the ABI (deprecated)1179 /// Old version of Sparc v9, from before the ABI (deprecated)
1180 OLD_SPARCV9 = 11,1180 OLD_SPARCV9 = 11,
1181 /// SPU Mark II
1182 SPU_2 = 13,
1183 /// HPPA1181 /// HPPA
1184 PARISC = 15,1182 PARISC = 15,
1185 /// Fujitsu VPP500 (also old version of PowerPC; deprecated)1183 /// Fujitsu VPP500 (also old version of PowerPC; deprecated)
src/Type.zig-1
...@@ -1698,7 +1698,6 @@ pub fn maxIntAlignment(target: std.Target) u16 {...@@ -1698,7 +1698,6 @@ pub fn maxIntAlignment(target: std.Target) u16 {
16981698
1699 // Below this comment are unverified but based on the fact that C requires1699 // Below this comment are unverified but based on the fact that C requires
1700 // int128_t to be 16 bytes aligned, it's a safe default.1700 // int128_t to be 16 bytes aligned, it's a safe default.
1701 .spu_2,
1702 .csky,1701 .csky,
1703 .arc,1702 .arc,
1704 .m68k,1703 .m68k,
src/Zcu.zig-1
...@@ -3594,7 +3594,6 @@ pub fn atomicPtrAlignment(...@@ -3594,7 +3594,6 @@ pub fn atomicPtrAlignment(
3594 const max_atomic_bits: u16 = switch (target.cpu.arch) {3594 const max_atomic_bits: u16 = switch (target.cpu.arch) {
3595 .avr,3595 .avr,
3596 .msp430,3596 .msp430,
3597 .spu_2,
3598 => 16,3597 => 16,
35993598
3600 .arc,3599 .arc,
src/codegen/llvm.zig-2
...@@ -98,7 +98,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {...@@ -98,7 +98,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
98 .ve => "ve",98 .ve => "ve",
9999
100 .kalimba,100 .kalimba,
101 .spu_2,
102 .propeller1,101 .propeller1,
103 .propeller2,102 .propeller2,
104 => unreachable, // Gated by hasLlvmSupport().103 => unreachable, // Gated by hasLlvmSupport().
...@@ -13024,7 +13023,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {...@@ -13024,7 +13023,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1302413023
13025 // LLVM does does not have a backend for these.13024 // LLVM does does not have a backend for these.
13026 .kalimba,13025 .kalimba,
13027 .spu_2,
13028 .propeller1,13026 .propeller1,
13029 .propeller2,13027 .propeller2,
13030 => unreachable,13028 => unreachable,
src/target.zig-1
...@@ -195,7 +195,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {...@@ -195,7 +195,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
195195
196 // No LLVM backend exists.196 // No LLVM backend exists.
197 .kalimba,197 .kalimba,
198 .spu_2,
199 .propeller1,198 .propeller1,
200 .propeller2,199 .propeller2,
201 => false,200 => false,