authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-01-24 00:22:43+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-02-17 19:17:55+01:00
logb541a7af1155a984bd41008ea337030d0373e0ea
treef8fb36f0e10cdadb8734254610567f799db206e3
parent55c46870b23ac16670beaa3ff1c082b703738307
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove Cpu.Arch.spu_2.

This was for a hobby project that appears to be dormant for now. This can be added back if the project is resumed in the future.

8 files changed, 0 insertions(+), 21 deletions(-)

lib/compiler/aro/aro/target.zig-4
......@@ -461,7 +461,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
461461 .amdgcn,
462462 .avr,
463463 .msp430,
464 .spu_2,
465464 .ve,
466465 .bpfel,
467466 .bpfeb,
......@@ -522,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
522521 .lanai,
523522 .m68k,
524523 .msp430,
525 .spu_2,
526524 .xcore,
527525 .xtensa,
528526 => return null,
......@@ -620,8 +618,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
620618 .wasm32 => "wasm32",
621619 .wasm64 => "wasm64",
622620 .ve => "ve",
623 // Note: spu_2 is not supported in LLVM; this is the Zig arch name
624 .spu_2 => "spu_2",
625621 };
626622 writer.writeAll(llvm_arch) catch unreachable;
627623 writer.writeByte('-') catch unreachable;
lib/std/Target.zig-9
......@@ -1085,7 +1085,6 @@ pub fn toElfMachine(target: Target) std.elf.EM {
10851085 .s390x => .S390,
10861086 .sparc => if (Target.sparc.featureSetHas(target.cpu.features, .v9)) .SPARC32PLUS else .SPARC,
10871087 .sparc64 => .SPARCV9,
1088 .spu_2 => .SPU_2,
10891088 .ve => .VE,
10901089 .x86 => if (target.os.tag == .elfiamcu) .IAMCU else .@"386",
10911090 .x86_64 => .X86_64,
......@@ -1148,7 +1147,6 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {
11481147 .spirv,
11491148 .spirv32,
11501149 .spirv64,
1151 .spu_2,
11521150 .ve,
11531151 .wasm32,
11541152 .wasm64,
......@@ -1378,7 +1376,6 @@ pub const Cpu = struct {
13781376 spirv,
13791377 spirv32,
13801378 spirv64,
1381 spu_2,
13821379 ve,
13831380 wasm32,
13841381 wasm64,
......@@ -1564,7 +1561,6 @@ pub const Cpu = struct {
15641561 .xcore,
15651562 .thumb,
15661563 .ve,
1567 .spu_2,
15681564 // GPU bitness is opaque. For now, assume little endian.
15691565 .spirv,
15701566 .spirv32,
......@@ -1954,7 +1950,6 @@ pub const Cpu = struct {
19541950 .xtensa => &xtensa.cpu.generic,
19551951
19561952 .kalimba,
1957 .spu_2,
19581953 => &S.generic_model,
19591954 };
19601955 }
......@@ -2627,7 +2622,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
26272622 return switch (cpu.arch) {
26282623 .avr,
26292624 .msp430,
2630 .spu_2,
26312625 => 16,
26322626
26332627 .arc,
......@@ -3164,7 +3158,6 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {
31643158 .x86,
31653159 .xcore,
31663160 .kalimba,
3167 .spu_2,
31683161 .xtensa,
31693162 .propeller1,
31703163 .propeller2,
......@@ -3260,7 +3253,6 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {
32603253 .csky,
32613254 .xcore,
32623255 .kalimba,
3263 .spu_2,
32643256 .xtensa,
32653257 .propeller1,
32663258 .propeller2,
......@@ -3371,7 +3363,6 @@ pub fn cCallingConvention(target: Target) ?std.builtin.CallingConvention {
33713363 .propeller1 => .{ .propeller1_sysv = .{} },
33723364 .propeller2 => .{ .propeller2_sysv = .{} },
33733365 .s390x => .{ .s390x_sysv = .{} },
3374 .spu_2 => null,
33753366 .ve => .{ .ve_sysv = .{} },
33763367 .xcore => .{ .xcore_xs1 = .{} },
33773368 .xtensa => .{ .xtensa_call0 = .{} },
lib/std/debug/Dwarf/abi.zig-1
......@@ -17,7 +17,6 @@ pub fn supportsUnwinding(target: std.Target) bool {
1717 .spirv,
1818 .spirv32,
1919 .spirv64,
20 .spu_2,
2120 => false,
2221
2322 // Enabling this causes relocation errors such as:
lib/std/elf.zig-2
......@@ -1178,8 +1178,6 @@ pub const EM = enum(u16) {
11781178 MIPS_RS3_LE = 10,
11791179 /// Old version of Sparc v9, from before the ABI (deprecated)
11801180 OLD_SPARCV9 = 11,
1181 /// SPU Mark II
1182 SPU_2 = 13,
11831181 /// HPPA
11841182 PARISC = 15,
11851183 /// Fujitsu VPP500 (also old version of PowerPC; deprecated)
src/Type.zig-1
......@@ -1698,7 +1698,6 @@ pub fn maxIntAlignment(target: std.Target) u16 {
16981698
16991699 // Below this comment are unverified but based on the fact that C requires
17001700 // int128_t to be 16 bytes aligned, it's a safe default.
1701 .spu_2,
17021701 .csky,
17031702 .arc,
17041703 .m68k,
src/Zcu.zig-1
......@@ -3594,7 +3594,6 @@ pub fn atomicPtrAlignment(
35943594 const max_atomic_bits: u16 = switch (target.cpu.arch) {
35953595 .avr,
35963596 .msp430,
3597 .spu_2,
35983597 => 16,
35993598
36003599 .arc,
src/codegen/llvm.zig-2
......@@ -98,7 +98,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
9898 .ve => "ve",
9999
100100 .kalimba,
101 .spu_2,
102101 .propeller1,
103102 .propeller2,
104103 => unreachable, // Gated by hasLlvmSupport().
......@@ -13024,7 +13023,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1302413023
1302513024 // LLVM does does not have a backend for these.
1302613025 .kalimba,
13027 .spu_2,
1302813026 .propeller1,
1302913027 .propeller2,
1303013028 => unreachable,
src/target.zig-1
......@@ -195,7 +195,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
195195
196196 // No LLVM backend exists.
197197 .kalimba,
198 .spu_2,
199198 .propeller1,
200199 .propeller2,
201200 => false,