authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-05-09 01:36:51-04:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2021-05-09 01:36:51-04:00
logb88d381dec9d73c66462a54bfbdd9f01f311266c
treedd5e34850c189ddb7ddac0f1d04163ee1df3705d
parent67154d233ef68d9fd63e673e63e7d66f149060a5
parentcfeb412a4263809698f941081197cd0ff7f260aa
signaturebadge-question-mark Signed by PGP key 4AEE18F83AFDEB23

Merge pull request #8474 from gracefuu/grace/encode-instruction

stage2 x86_64: encoding helpers, fix bugs

5 files changed, 1212 insertions(+), 218 deletions(-)

src/Module.zig+60
...@@ -4330,6 +4330,33 @@ pub fn intSub(allocator: *Allocator, lhs: Value, rhs: Value) !Value {...@@ -4330,6 +4330,33 @@ pub fn intSub(allocator: *Allocator, lhs: Value, rhs: Value) !Value {
4330 }4330 }
4331}4331}
43324332
4333pub fn intMul(allocator: *Allocator, lhs: Value, rhs: Value) !Value {
4334 // TODO is this a performance issue? maybe we should try the operation without
4335 // resorting to BigInt first.
4336 var lhs_space: Value.BigIntSpace = undefined;
4337 var rhs_space: Value.BigIntSpace = undefined;
4338 const lhs_bigint = lhs.toBigInt(&lhs_space);
4339 const rhs_bigint = rhs.toBigInt(&rhs_space);
4340 const limbs = try allocator.alloc(
4341 std.math.big.Limb,
4342 lhs_bigint.limbs.len + rhs_bigint.limbs.len + 1,
4343 );
4344 var result_bigint = BigIntMutable{ .limbs = limbs, .positive = undefined, .len = undefined };
4345 var limbs_buffer = try allocator.alloc(
4346 std.math.big.Limb,
4347 std.math.big.int.calcMulLimbsBufferLen(lhs_bigint.limbs.len, rhs_bigint.limbs.len, 1),
4348 );
4349 defer allocator.free(limbs_buffer);
4350 result_bigint.mul(lhs_bigint, rhs_bigint, limbs_buffer, allocator);
4351 const result_limbs = result_bigint.limbs[0..result_bigint.len];
4352
4353 if (result_bigint.positive) {
4354 return Value.Tag.int_big_positive.create(allocator, result_limbs);
4355 } else {
4356 return Value.Tag.int_big_negative.create(allocator, result_limbs);
4357 }
4358}
4359
4333pub fn floatAdd(4360pub fn floatAdd(
4334 arena: *Allocator,4361 arena: *Allocator,
4335 float_type: Type,4362 float_type: Type,
...@@ -4396,6 +4423,39 @@ pub fn floatSub(...@@ -4396,6 +4423,39 @@ pub fn floatSub(
4396 }4423 }
4397}4424}
43984425
4426pub fn floatMul(
4427 arena: *Allocator,
4428 float_type: Type,
4429 src: LazySrcLoc,
4430 lhs: Value,
4431 rhs: Value,
4432) !Value {
4433 switch (float_type.tag()) {
4434 .f16 => {
4435 @panic("TODO add __trunctfhf2 to compiler-rt");
4436 //const lhs_val = lhs.toFloat(f16);
4437 //const rhs_val = rhs.toFloat(f16);
4438 //return Value.Tag.float_16.create(arena, lhs_val * rhs_val);
4439 },
4440 .f32 => {
4441 const lhs_val = lhs.toFloat(f32);
4442 const rhs_val = rhs.toFloat(f32);
4443 return Value.Tag.float_32.create(arena, lhs_val * rhs_val);
4444 },
4445 .f64 => {
4446 const lhs_val = lhs.toFloat(f64);
4447 const rhs_val = rhs.toFloat(f64);
4448 return Value.Tag.float_64.create(arena, lhs_val * rhs_val);
4449 },
4450 .f128, .comptime_float, .c_longdouble => {
4451 const lhs_val = lhs.toFloat(f128);
4452 const rhs_val = rhs.toFloat(f128);
4453 return Value.Tag.float_128.create(arena, lhs_val * rhs_val);
4454 },
4455 else => unreachable,
4456 }
4457}
4458
4399pub fn simplePtrType(4459pub fn simplePtrType(
4400 mod: *Module,4460 mod: *Module,
4401 arena: *Allocator,4461 arena: *Allocator,
src/Sema.zig+16-4
...@@ -3864,10 +3864,15 @@ fn analyzeArithmetic(...@@ -3864,10 +3864,15 @@ fn analyzeArithmetic(
3864 // incase rhs is 0, simply return lhs without doing any calculations3864 // incase rhs is 0, simply return lhs without doing any calculations
3865 // TODO Once division is implemented we should throw an error when dividing by 0.3865 // TODO Once division is implemented we should throw an error when dividing by 0.
3866 if (rhs_val.compareWithZero(.eq)) {3866 if (rhs_val.compareWithZero(.eq)) {
3867 return sema.mod.constInst(sema.arena, src, .{3867 switch (zir_tag) {
3868 .ty = scalar_type,3868 .add, .addwrap, .sub, .subwrap => {
3869 .val = lhs_val,3869 return sema.mod.constInst(sema.arena, src, .{
3870 });3870 .ty = scalar_type,
3871 .val = lhs_val,
3872 });
3873 },
3874 else => {},
3875 }
3871 }3876 }
38723877
3873 const value = switch (zir_tag) {3878 const value = switch (zir_tag) {
...@@ -3885,6 +3890,13 @@ fn analyzeArithmetic(...@@ -3885,6 +3890,13 @@ fn analyzeArithmetic(
3885 try Module.floatSub(sema.arena, scalar_type, src, lhs_val, rhs_val);3890 try Module.floatSub(sema.arena, scalar_type, src, lhs_val, rhs_val);
3886 break :blk val;3891 break :blk val;
3887 },3892 },
3893 .mul => blk: {
3894 const val = if (is_int)
3895 try Module.intMul(sema.arena, lhs_val, rhs_val)
3896 else
3897 try Module.floatMul(sema.arena, scalar_type, src, lhs_val, rhs_val);
3898 break :blk val;
3899 },
3888 else => return sema.mod.fail(&block.base, src, "TODO Implement arithmetic operand '{s}'", .{@tagName(zir_tag)}),3900 else => return sema.mod.fail(&block.base, src, "TODO Implement arithmetic operand '{s}'", .{@tagName(zir_tag)}),
3889 };3901 };
38903902
src/codegen.zig+522-201
...@@ -20,6 +20,8 @@ const build_options = @import("build_options");...@@ -20,6 +20,8 @@ const build_options = @import("build_options");
20const LazySrcLoc = Module.LazySrcLoc;20const LazySrcLoc = Module.LazySrcLoc;
21const RegisterManager = @import("register_manager.zig").RegisterManager;21const RegisterManager = @import("register_manager.zig").RegisterManager;
2222
23const X8664Encoder = @import("codegen/x86_64.zig").Encoder;
24
23/// The codegen-related data that is stored in `ir.Inst.Block` instructions.25/// The codegen-related data that is stored in `ir.Inst.Block` instructions.
24pub const BlockData = struct {26pub const BlockData = struct {
25 relocs: std.ArrayListUnmanaged(Reloc) = undefined,27 relocs: std.ArrayListUnmanaged(Reloc) = undefined,
...@@ -1038,7 +1040,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -1038,7 +1040,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
1038 },1040 },
1039 .val = Value.initTag(.bool_true),1041 .val = Value.initTag(.bool_true),
1040 };1042 };
1041 return try self.genX8664BinMath(&inst.base, inst.operand, &imm.base, 6, 0x30);1043 return try self.genX8664BinMath(&inst.base, inst.operand, &imm.base);
1042 },1044 },
1043 .arm, .armeb => {1045 .arm, .armeb => {
1044 var imm = ir.Inst.Constant{1046 var imm = ir.Inst.Constant{
...@@ -1062,7 +1064,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -1062,7 +1064,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
1062 return MCValue.dead;1064 return MCValue.dead;
1063 switch (arch) {1065 switch (arch) {
1064 .x86_64 => {1066 .x86_64 => {
1065 return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 0, 0x00);1067 return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs);
1066 },1068 },
1067 .arm, .armeb => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .add),1069 .arm, .armeb => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .add),
1068 else => return self.fail(inst.base.src, "TODO implement add for {}", .{self.target.cpu.arch}),1070 else => return self.fail(inst.base.src, "TODO implement add for {}", .{self.target.cpu.arch}),
...@@ -1083,6 +1085,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -1083,6 +1085,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
1083 if (inst.base.isUnused())1085 if (inst.base.isUnused())
1084 return MCValue.dead;1086 return MCValue.dead;
1085 switch (arch) {1087 switch (arch) {
1088 .x86_64 => return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs),
1086 .arm, .armeb => return try self.genArmMul(&inst.base, inst.lhs, inst.rhs),1089 .arm, .armeb => return try self.genArmMul(&inst.base, inst.lhs, inst.rhs),
1087 else => return self.fail(inst.base.src, "TODO implement mul for {}", .{self.target.cpu.arch}),1090 else => return self.fail(inst.base.src, "TODO implement mul for {}", .{self.target.cpu.arch}),
1088 }1091 }
...@@ -1361,7 +1364,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -1361,7 +1364,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
1361 return MCValue.dead;1364 return MCValue.dead;
1362 switch (arch) {1365 switch (arch) {
1363 .x86_64 => {1366 .x86_64 => {
1364 return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 5, 0x28);1367 return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs);
1365 },1368 },
1366 .arm, .armeb => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .sub),1369 .arm, .armeb => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .sub),
1367 else => return self.fail(inst.base.src, "TODO implement sub for {}", .{self.target.cpu.arch}),1370 else => return self.fail(inst.base.src, "TODO implement sub for {}", .{self.target.cpu.arch}),
...@@ -1506,8 +1509,20 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -1506,8 +1509,20 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
1506 return dst_mcv;1509 return dst_mcv;
1507 }1510 }
15081511
1512 /// Perform "binary" operators, excluding comparisons.
1513 /// Currently, the following ops are supported:
1509 /// ADD, SUB, XOR, OR, AND1514 /// ADD, SUB, XOR, OR, AND
1510 fn genX8664BinMath(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, opx: u8, mr: u8) !MCValue {1515 fn genX8664BinMath(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst) !MCValue {
1516 // We'll handle these ops in two steps.
1517 // 1) Prepare an output location (register or memory)
1518 // This location will be the location of the operand that dies (if one exists)
1519 // or just a temporary register (if one doesn't exist)
1520 // 2) Perform the op with the other argument
1521 // 3) Sometimes, the output location is memory but the op doesn't support it.
1522 // In this case, copy that location to a register, then perform the op to that register instead.
1523 //
1524 // TODO: make this algorithm less bad
1525
1511 try self.code.ensureCapacity(self.code.items.len + 8);1526 try self.code.ensureCapacity(self.code.items.len + 8);
15121527
1513 const lhs = try self.resolveInst(op_lhs);1528 const lhs = try self.resolveInst(op_lhs);
...@@ -1568,18 +1583,109 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -1568,18 +1583,109 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
1568 else => {},1583 else => {},
1569 }1584 }
15701585
1571 try self.genX8664BinMathCode(inst.src, inst.ty, dst_mcv, src_mcv, opx, mr);1586 // Now for step 2, we perform the actual op
1587 switch (inst.tag) {
1588 // TODO: Generate wrapping and non-wrapping versions separately
1589 .add, .addwrap => try self.genX8664BinMathCode(inst.src, inst.ty, dst_mcv, src_mcv, 0, 0x00),
1590 .bool_or, .bit_or => try self.genX8664BinMathCode(inst.src, inst.ty, dst_mcv, src_mcv, 1, 0x08),
1591 .bool_and, .bit_and => try self.genX8664BinMathCode(inst.src, inst.ty, dst_mcv, src_mcv, 4, 0x20),
1592 .sub, .subwrap => try self.genX8664BinMathCode(inst.src, inst.ty, dst_mcv, src_mcv, 5, 0x28),
1593 .xor, .not => try self.genX8664BinMathCode(inst.src, inst.ty, dst_mcv, src_mcv, 6, 0x30),
1594
1595 .mul, .mulwrap => try self.genX8664Imul(inst.src, inst.ty, dst_mcv, src_mcv),
1596 else => unreachable,
1597 }
15721598
1573 return dst_mcv;1599 return dst_mcv;
1574 }1600 }
15751601
1602 /// Wrap over Instruction.encodeInto to translate errors
1603 fn encodeX8664Instruction(
1604 self: *Self,
1605 src: LazySrcLoc,
1606 inst: Instruction,
1607 ) !void {
1608 inst.encodeInto(self.code) catch |err| {
1609 if (err == error.OutOfMemory)
1610 return error.OutOfMemory
1611 else
1612 return self.fail(src, "Instruction.encodeInto failed because {s}", .{@errorName(err)});
1613 };
1614 }
1615
1616 /// This function encodes a binary operation for x86_64
1617 /// intended for use with the following opcode ranges
1618 /// because they share the same structure.
1619 ///
1620 /// Thus not all binary operations can be used here
1621 /// -- multiplication needs to be done with imul,
1622 /// which doesn't have as convenient an interface.
1623 ///
1624 /// "opx"-style instructions use the opcode extension field to indicate which instruction to execute:
1625 ///
1626 /// opx = /0: add
1627 /// opx = /1: or
1628 /// opx = /2: adc
1629 /// opx = /3: sbb
1630 /// opx = /4: and
1631 /// opx = /5: sub
1632 /// opx = /6: xor
1633 /// opx = /7: cmp
1634 ///
1635 /// opcode | operand shape
1636 /// --------+----------------------
1637 /// 80 /opx | *r/m8*, imm8
1638 /// 81 /opx | *r/m16/32/64*, imm16/32
1639 /// 83 /opx | *r/m16/32/64*, imm8
1640 ///
1641 /// "mr"-style instructions use the low bits of opcode to indicate shape of instruction:
1642 ///
1643 /// mr = 00: add
1644 /// mr = 08: or
1645 /// mr = 10: adc
1646 /// mr = 18: sbb
1647 /// mr = 20: and
1648 /// mr = 28: sub
1649 /// mr = 30: xor
1650 /// mr = 38: cmp
1651 ///
1652 /// opcode | operand shape
1653 /// -------+-------------------------
1654 /// mr + 0 | *r/m8*, r8
1655 /// mr + 1 | *r/m16/32/64*, r16/32/64
1656 /// mr + 2 | *r8*, r/m8
1657 /// mr + 3 | *r16/32/64*, r/m16/32/64
1658 /// mr + 4 | *AL*, imm8
1659 /// mr + 5 | *rAX*, imm16/32
1660 ///
1661 /// TODO: rotates and shifts share the same structure, so we can potentially implement them
1662 /// at a later date with very similar code.
1663 /// They have "opx"-style instructions, but no "mr"-style instructions.
1664 ///
1665 /// opx = /0: rol,
1666 /// opx = /1: ror,
1667 /// opx = /2: rcl,
1668 /// opx = /3: rcr,
1669 /// opx = /4: shl sal,
1670 /// opx = /5: shr,
1671 /// opx = /6: sal shl,
1672 /// opx = /7: sar,
1673 ///
1674 /// opcode | operand shape
1675 /// --------+------------------
1676 /// c0 /opx | *r/m8*, imm8
1677 /// c1 /opx | *r/m16/32/64*, imm8
1678 /// d0 /opx | *r/m8*, 1
1679 /// d1 /opx | *r/m16/32/64*, 1
1680 /// d2 /opx | *r/m8*, CL (for context, CL is register 1)
1681 /// d3 /opx | *r/m16/32/64*, CL (for context, CL is register 1)
1576 fn genX8664BinMathCode(1682 fn genX8664BinMathCode(
1577 self: *Self,1683 self: *Self,
1578 src: LazySrcLoc,1684 src: LazySrcLoc,
1579 dst_ty: Type,1685 dst_ty: Type,
1580 dst_mcv: MCValue,1686 dst_mcv: MCValue,
1581 src_mcv: MCValue,1687 src_mcv: MCValue,
1582 opx: u8,1688 opx: u3,
1583 mr: u8,1689 mr: u8,
1584 ) !void {1690 ) !void {
1585 switch (dst_mcv) {1691 switch (dst_mcv) {
...@@ -1598,31 +1704,85 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -1598,31 +1704,85 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
1598 .ptr_stack_offset => unreachable,1704 .ptr_stack_offset => unreachable,
1599 .ptr_embedded_in_code => unreachable,1705 .ptr_embedded_in_code => unreachable,
1600 .register => |src_reg| {1706 .register => |src_reg| {
1601 self.rex(.{ .b = dst_reg.isExtended(), .r = src_reg.isExtended(), .w = dst_reg.size() == 64 });1707 // for register, register use mr + 1
1602 self.code.appendSliceAssumeCapacity(&[_]u8{ mr + 0x1, 0xC0 | (@as(u8, src_reg.id() & 0b111) << 3) | @as(u8, dst_reg.id() & 0b111) });1708 // addressing mode: *r/m16/32/64*, r16/32/64
1709 const abi_size = dst_ty.abiSize(self.target.*);
1710 const encoder = try X8664Encoder.init(self.code, 3);
1711 encoder.rex(.{
1712 .w = abi_size == 8,
1713 .r = src_reg.isExtended(),
1714 .b = dst_reg.isExtended(),
1715 });
1716 encoder.opcode_1byte(mr + 1);
1717 encoder.modRm_direct(
1718 src_reg.low_id(),
1719 dst_reg.low_id(),
1720 );
1603 },1721 },
1604 .immediate => |imm| {1722 .immediate => |imm| {
1605 const imm32 = @intCast(u31, imm); // This case must be handled before calling genX8664BinMathCode.1723 // register, immediate use opx = 81 or 83 addressing modes:
1606 // 81 /opx id1724 // opx = 81: r/m16/32/64, imm16/32
1607 if (imm32 <= math.maxInt(u7)) {1725 // opx = 83: r/m16/32/64, imm8
1608 self.rex(.{ .b = dst_reg.isExtended(), .w = dst_reg.size() == 64 });1726 const imm32 = @intCast(i32, imm); // This case must be handled before calling genX8664BinMathCode.
1609 self.code.appendSliceAssumeCapacity(&[_]u8{1727 if (imm32 <= math.maxInt(i8)) {
1610 0x83,1728 const abi_size = dst_ty.abiSize(self.target.*);
1611 0xC0 | (opx << 3) | @truncate(u3, dst_reg.id()),1729 const encoder = try X8664Encoder.init(self.code, 4);
1612 @intCast(u8, imm32),1730 encoder.rex(.{
1731 .w = abi_size == 8,
1732 .b = dst_reg.isExtended(),
1613 });1733 });
1734 encoder.opcode_1byte(0x83);
1735 encoder.modRm_direct(
1736 opx,
1737 dst_reg.low_id(),
1738 );
1739 encoder.imm8(@intCast(i8, imm32));
1614 } else {1740 } else {
1615 self.rex(.{ .r = dst_reg.isExtended(), .w = dst_reg.size() == 64 });1741 const abi_size = dst_ty.abiSize(self.target.*);
1616 self.code.appendSliceAssumeCapacity(&[_]u8{1742 const encoder = try X8664Encoder.init(self.code, 7);
1617 0x81,1743 encoder.rex(.{
1618 0xC0 | (opx << 3) | @truncate(u3, dst_reg.id()),1744 .w = abi_size == 8,
1745 .b = dst_reg.isExtended(),
1619 });1746 });
1620 std.mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), imm32);1747 encoder.opcode_1byte(0x81);
1748 encoder.modRm_direct(
1749 opx,
1750 dst_reg.low_id(),
1751 );
1752 encoder.imm32(@intCast(i32, imm32));
1621 }1753 }
1622 },1754 },
1623 .embedded_in_code, .memory, .stack_offset => {1755 .embedded_in_code, .memory => {
1624 return self.fail(src, "TODO implement x86 ADD/SUB/CMP source memory", .{});1756 return self.fail(src, "TODO implement x86 ADD/SUB/CMP source memory", .{});
1625 },1757 },
1758 .stack_offset => |off| {
1759 // register, indirect use mr + 3
1760 // addressing mode: *r16/32/64*, r/m16/32/64
1761 const abi_size = dst_ty.abiSize(self.target.*);
1762 const adj_off = off + abi_size;
1763 if (off > math.maxInt(i32)) {
1764 return self.fail(src, "stack offset too large", .{});
1765 }
1766 const encoder = try X8664Encoder.init(self.code, 7);
1767 encoder.rex(.{
1768 .w = abi_size == 8,
1769 .r = dst_reg.isExtended(),
1770 });
1771 encoder.opcode_1byte(mr + 3);
1772 if (adj_off <= std.math.maxInt(i8)) {
1773 encoder.modRm_indirectDisp8(
1774 dst_reg.low_id(),
1775 Register.ebp.low_id(),
1776 );
1777 encoder.disp8(-@intCast(i8, adj_off));
1778 } else {
1779 encoder.modRm_indirectDisp32(
1780 dst_reg.low_id(),
1781 Register.ebp.low_id(),
1782 );
1783 encoder.disp32(-@intCast(i32, adj_off));
1784 }
1785 },
1626 .compare_flags_unsigned => {1786 .compare_flags_unsigned => {
1627 return self.fail(src, "TODO implement x86 ADD/SUB/CMP source compare flag (unsigned)", .{});1787 return self.fail(src, "TODO implement x86 ADD/SUB/CMP source compare flag (unsigned)", .{});
1628 },1788 },
...@@ -1661,27 +1821,183 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -1661,27 +1821,183 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
1661 }1821 }
1662 }1822 }
16631823
1824 /// Performs integer multiplication between dst_mcv and src_mcv, storing the result in dst_mcv.
1825 fn genX8664Imul(
1826 self: *Self,
1827 src: LazySrcLoc,
1828 dst_ty: Type,
1829 dst_mcv: MCValue,
1830 src_mcv: MCValue,
1831 ) !void {
1832 switch (dst_mcv) {
1833 .none => unreachable,
1834 .undef => unreachable,
1835 .dead, .unreach, .immediate => unreachable,
1836 .compare_flags_unsigned => unreachable,
1837 .compare_flags_signed => unreachable,
1838 .ptr_stack_offset => unreachable,
1839 .ptr_embedded_in_code => unreachable,
1840 .register => |dst_reg| {
1841 switch (src_mcv) {
1842 .none => unreachable,
1843 .undef => try self.genSetReg(src, dst_ty, dst_reg, .undef),
1844 .dead, .unreach => unreachable,
1845 .ptr_stack_offset => unreachable,
1846 .ptr_embedded_in_code => unreachable,
1847 .register => |src_reg| {
1848 // register, register
1849 //
1850 // Use the following imul opcode
1851 // 0F AF /r: IMUL r32/64, r/m32/64
1852 const abi_size = dst_ty.abiSize(self.target.*);
1853 const encoder = try X8664Encoder.init(self.code, 4);
1854 encoder.rex(.{
1855 .w = abi_size == 8,
1856 .r = dst_reg.isExtended(),
1857 .b = src_reg.isExtended(),
1858 });
1859 encoder.opcode_2byte(0x0f, 0xaf);
1860 encoder.modRm_direct(
1861 dst_reg.low_id(),
1862 src_reg.low_id(),
1863 );
1864 },
1865 .immediate => |imm| {
1866 // register, immediate:
1867 // depends on size of immediate.
1868 //
1869 // immediate fits in i8:
1870 // 6B /r ib: IMUL r32/64, r/m32/64, imm8
1871 //
1872 // immediate fits in i32:
1873 // 69 /r id: IMUL r32/64, r/m32/64, imm32
1874 //
1875 // immediate is huge:
1876 // split into 2 instructions
1877 // 1) copy the 64 bit immediate into a tmp register
1878 // 2) perform register,register mul
1879 // 0F AF /r: IMUL r32/64, r/m32/64
1880 if (math.minInt(i8) <= imm and imm <= math.maxInt(i8)) {
1881 const abi_size = dst_ty.abiSize(self.target.*);
1882 const encoder = try X8664Encoder.init(self.code, 4);
1883 encoder.rex(.{
1884 .w = abi_size == 8,
1885 .r = dst_reg.isExtended(),
1886 .b = dst_reg.isExtended(),
1887 });
1888 encoder.opcode_1byte(0x6B);
1889 encoder.modRm_direct(
1890 dst_reg.low_id(),
1891 dst_reg.low_id(),
1892 );
1893 encoder.imm8(@intCast(i8, imm));
1894 } else if (math.minInt(i32) <= imm and imm <= math.maxInt(i32)) {
1895 const abi_size = dst_ty.abiSize(self.target.*);
1896 const encoder = try X8664Encoder.init(self.code, 7);
1897 encoder.rex(.{
1898 .w = abi_size == 8,
1899 .r = dst_reg.isExtended(),
1900 .b = dst_reg.isExtended(),
1901 });
1902 encoder.opcode_1byte(0x69);
1903 encoder.modRm_direct(
1904 dst_reg.low_id(),
1905 dst_reg.low_id(),
1906 );
1907 encoder.imm32(@intCast(i32, imm));
1908 } else {
1909 const src_reg = try self.copyToTmpRegister(src, dst_ty, src_mcv);
1910 return self.genX8664Imul(src, dst_ty, dst_mcv, MCValue{ .register = src_reg });
1911 }
1912 },
1913 .embedded_in_code, .memory, .stack_offset => {
1914 return self.fail(src, "TODO implement x86 multiply source memory", .{});
1915 },
1916 .compare_flags_unsigned => {
1917 return self.fail(src, "TODO implement x86 multiply source compare flag (unsigned)", .{});
1918 },
1919 .compare_flags_signed => {
1920 return self.fail(src, "TODO implement x86 multiply source compare flag (signed)", .{});
1921 },
1922 }
1923 },
1924 .stack_offset => |off| {
1925 switch (src_mcv) {
1926 .none => unreachable,
1927 .undef => return self.genSetStack(src, dst_ty, off, .undef),
1928 .dead, .unreach => unreachable,
1929 .ptr_stack_offset => unreachable,
1930 .ptr_embedded_in_code => unreachable,
1931 .register => |src_reg| {
1932 // copy dst to a register
1933 const dst_reg = try self.copyToTmpRegister(src, dst_ty, dst_mcv);
1934 // multiply into dst_reg
1935 // register, register
1936 // Use the following imul opcode
1937 // 0F AF /r: IMUL r32/64, r/m32/64
1938 const abi_size = dst_ty.abiSize(self.target.*);
1939 const encoder = try X8664Encoder.init(self.code, 4);
1940 encoder.rex(.{
1941 .w = abi_size == 8,
1942 .r = dst_reg.isExtended(),
1943 .b = src_reg.isExtended(),
1944 });
1945 encoder.opcode_2byte(0x0f, 0xaf);
1946 encoder.modRm_direct(
1947 dst_reg.low_id(),
1948 src_reg.low_id(),
1949 );
1950 // copy dst_reg back out
1951 return self.genSetStack(src, dst_ty, off, MCValue{ .register = dst_reg });
1952 },
1953 .immediate => |imm| {
1954 return self.fail(src, "TODO implement x86 multiply source immediate", .{});
1955 },
1956 .embedded_in_code, .memory, .stack_offset => {
1957 return self.fail(src, "TODO implement x86 multiply source memory", .{});
1958 },
1959 .compare_flags_unsigned => {
1960 return self.fail(src, "TODO implement x86 multiply source compare flag (unsigned)", .{});
1961 },
1962 .compare_flags_signed => {
1963 return self.fail(src, "TODO implement x86 multiply source compare flag (signed)", .{});
1964 },
1965 }
1966 },
1967 .embedded_in_code, .memory => {
1968 return self.fail(src, "TODO implement x86 multiply destination memory", .{});
1969 },
1970 }
1971 }
1972
1664 fn genX8664ModRMRegToStack(self: *Self, src: LazySrcLoc, ty: Type, off: u32, reg: Register, opcode: u8) !void {1973 fn genX8664ModRMRegToStack(self: *Self, src: LazySrcLoc, ty: Type, off: u32, reg: Register, opcode: u8) !void {
1665 const abi_size = ty.abiSize(self.target.*);1974 const abi_size = ty.abiSize(self.target.*);
1666 const adj_off = off + abi_size;1975 const adj_off = off + abi_size;
1667 try self.code.ensureCapacity(self.code.items.len + 7);1976 if (off > math.maxInt(i32)) {
1668 self.rex(.{ .w = reg.size() == 64, .r = reg.isExtended() });1977 return self.fail(src, "stack offset too large", .{});
1669 const reg_id: u8 = @truncate(u3, reg.id());1978 }
1670 if (adj_off <= 128) {1979
1980 const i_adj_off = -@intCast(i32, adj_off);
1981 const encoder = try X8664Encoder.init(self.code, 7);
1982 encoder.rex(.{
1983 .w = abi_size == 8,
1984 .r = reg.isExtended(),
1985 });
1986 encoder.opcode_1byte(opcode);
1987 if (i_adj_off < std.math.maxInt(i8)) {
1671 // example: 48 89 55 7f mov QWORD PTR [rbp+0x7f],rdx1988 // example: 48 89 55 7f mov QWORD PTR [rbp+0x7f],rdx
1672 const RM = @as(u8, 0b01_000_101) | (reg_id << 3);1989 encoder.modRm_indirectDisp8(
1673 const negative_offset = @intCast(i8, -@intCast(i32, adj_off));1990 reg.low_id(),
1674 const twos_comp = @bitCast(u8, negative_offset);1991 Register.ebp.low_id(),
1675 self.code.appendSliceAssumeCapacity(&[_]u8{ opcode, RM, twos_comp });1992 );
1676 } else if (adj_off <= 2147483648) {1993 encoder.disp8(@intCast(i8, i_adj_off));
1677 // example: 48 89 95 80 00 00 00 mov QWORD PTR [rbp+0x80],rdx
1678 const RM = @as(u8, 0b10_000_101) | (reg_id << 3);
1679 const negative_offset = @intCast(i32, -@intCast(i33, adj_off));
1680 const twos_comp = @bitCast(u32, negative_offset);
1681 self.code.appendSliceAssumeCapacity(&[_]u8{ opcode, RM });
1682 mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), twos_comp);
1683 } else {1994 } else {
1684 return self.fail(src, "stack offset too large", .{});1995 // example: 48 89 95 80 00 00 00 mov QWORD PTR [rbp+0x80],rdx
1996 encoder.modRm_indirectDisp32(
1997 reg.low_id(),
1998 Register.ebp.low_id(),
1999 );
2000 encoder.disp32(i_adj_off);
1685 }2001 }
1686 }2002 }
16872003
...@@ -2126,12 +2442,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -2126,12 +2442,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
2126 log.debug("got_addr = 0x{x}", .{got_addr});2442 log.debug("got_addr = 0x{x}", .{got_addr});
2127 switch (arch) {2443 switch (arch) {
2128 .x86_64 => {2444 .x86_64 => {
2129 try self.genSetReg(inst.base.src, Type.initTag(.u32), .rax, .{ .memory = got_addr });2445 try self.genSetReg(inst.base.src, Type.initTag(.u64), .rax, .{ .memory = got_addr });
2130 // callq *%rax2446 // callq *%rax
2447 try self.code.ensureCapacity(self.code.items.len + 2);
2131 self.code.appendSliceAssumeCapacity(&[2]u8{ 0xff, 0xd0 });2448 self.code.appendSliceAssumeCapacity(&[2]u8{ 0xff, 0xd0 });
2132 },2449 },
2133 .aarch64 => {2450 .aarch64 => {
2134 try self.genSetReg(inst.base.src, Type.initTag(.u32), .x30, .{ .memory = got_addr });2451 try self.genSetReg(inst.base.src, Type.initTag(.u64), .x30, .{ .memory = got_addr });
2135 // blr x302452 // blr x30
2136 writeInt(u32, try self.code.addManyAsArray(4), Instruction.blr(.x30).toU32());2453 writeInt(u32, try self.code.addManyAsArray(4), Instruction.blr(.x30).toU32());
2137 },2454 },
...@@ -2355,15 +2672,19 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -2355,15 +2672,19 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
2355 .register => |reg| blk: {2672 .register => |reg| blk: {
2356 // test reg, 12673 // test reg, 1
2357 // TODO detect al, ax, eax2674 // TODO detect al, ax, eax
2358 try self.code.ensureCapacity(self.code.items.len + 4);2675 const encoder = try X8664Encoder.init(self.code, 4);
2359 // TODO audit this codegen: we force w = true here to make2676 encoder.rex(.{
2360 // the value affect the big register2677 // TODO audit this codegen: we force w = true here to make
2361 self.rex(.{ .b = reg.isExtended(), .w = true });2678 // the value affect the big register
2362 self.code.appendSliceAssumeCapacity(&[_]u8{2679 .w = true,
2363 0xf6,2680 .b = reg.isExtended(),
2364 @as(u8, 0xC0) | (0 << 3) | @truncate(u3, reg.id()),
2365 0x01,
2366 });2681 });
2682 encoder.opcode_1byte(0xf6);
2683 encoder.modRm_direct(
2684 0,
2685 reg.low_id(),
2686 );
2687 encoder.disp8(1);
2367 break :blk 0x84;2688 break :blk 0x84;
2368 },2689 },
2369 else => return self.fail(inst.base.src, "TODO implement condbr {s} when condition is {s}", .{ self.target.cpu.arch, @tagName(cond) }),2690 else => return self.fail(inst.base.src, "TODO implement condbr {s} when condition is {s}", .{ self.target.cpu.arch, @tagName(cond) }),
...@@ -2673,9 +2994,9 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -2673,9 +2994,9 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
2673 switch (arch) {2994 switch (arch) {
2674 .x86_64 => switch (inst.base.tag) {2995 .x86_64 => switch (inst.base.tag) {
2675 // lhs AND rhs2996 // lhs AND rhs
2676 .bool_and => return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 4, 0x20),2997 .bool_and => return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs),
2677 // lhs OR rhs2998 // lhs OR rhs
2678 .bool_or => return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 1, 0x08),2999 .bool_or => return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs),
2679 else => unreachable, // Not a boolean operation3000 else => unreachable, // Not a boolean operation
2680 },3001 },
2681 .arm, .armeb => switch (inst.base.tag) {3002 .arm, .armeb => switch (inst.base.tag) {
...@@ -2882,39 +3203,6 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -2882,39 +3203,6 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
2882 }3203 }
2883 }3204 }
28843205
2885 /// Encodes a REX prefix as specified, and appends it to the instruction
2886 /// stream. This only modifies the instruction stream if at least one bit
2887 /// is set true, which has a few implications:
2888 ///
2889 /// * The length of the instruction buffer will be modified *if* the
2890 /// resulting REX is meaningful, but will remain the same if it is not.
2891 /// * Deliberately inserting a "meaningless REX" requires explicit usage of
2892 /// 0x40, and cannot be done via this function.
2893 /// W => 64 bit mode
2894 /// R => extension to the MODRM.reg field
2895 /// X => extension to the SIB.index field
2896 /// B => extension to the MODRM.rm field or the SIB.base field
2897 fn rex(self: *Self, arg: struct { b: bool = false, w: bool = false, x: bool = false, r: bool = false }) void {
2898 comptime assert(arch == .x86_64);
2899 // From section 2.2.1.2 of the manual, REX is encoded as b0100WRXB.
2900 var value: u8 = 0x40;
2901 if (arg.b) {
2902 value |= 0x1;
2903 }
2904 if (arg.x) {
2905 value |= 0x2;
2906 }
2907 if (arg.r) {
2908 value |= 0x4;
2909 }
2910 if (arg.w) {
2911 value |= 0x8;
2912 }
2913 if (value != 0x40) {
2914 self.code.appendAssumeCapacity(value);
2915 }
2916 }
2917
2918 /// Sets the value without any modifications to register allocation metadata or stack allocation metadata.3206 /// Sets the value without any modifications to register allocation metadata or stack allocation metadata.
2919 fn setRegOrMem(self: *Self, src: LazySrcLoc, ty: Type, loc: MCValue, val: MCValue) !void {3207 fn setRegOrMem(self: *Self, src: LazySrcLoc, ty: Type, loc: MCValue, val: MCValue) !void {
2920 switch (loc) {3208 switch (loc) {
...@@ -3462,20 +3750,25 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -3462,20 +3750,25 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
3462 }3750 }
3463 },3751 },
3464 .compare_flags_unsigned => |op| {3752 .compare_flags_unsigned => |op| {
3465 try self.code.ensureCapacity(self.code.items.len + 3);3753 const encoder = try X8664Encoder.init(self.code, 7);
3466 // TODO audit this codegen: we force w = true here to make3754 // TODO audit this codegen: we force w = true here to make
3467 // the value affect the big register3755 // the value affect the big register
3468 self.rex(.{ .b = reg.isExtended(), .w = true });3756 encoder.rex(.{
3469 const opcode: u8 = switch (op) {3757 .w = true,
3758 .b = reg.isExtended(),
3759 });
3760 encoder.opcode_2byte(0x0f, switch (op) {
3470 .gte => 0x93,3761 .gte => 0x93,
3471 .gt => 0x97,3762 .gt => 0x97,
3472 .neq => 0x95,3763 .neq => 0x95,
3473 .lt => 0x92,3764 .lt => 0x92,
3474 .lte => 0x96,3765 .lte => 0x96,
3475 .eq => 0x94,3766 .eq => 0x94,
3476 };3767 });
3477 const id = @as(u8, reg.id() & 0b111);3768 encoder.modRm_direct(
3478 self.code.appendSliceAssumeCapacity(&[_]u8{ 0x0f, opcode, 0xC0 | id });3769 0,
3770 reg.low_id(),
3771 );
3479 },3772 },
3480 .compare_flags_signed => |op| {3773 .compare_flags_signed => |op| {
3481 return self.fail(src, "TODO set register with compare flags value (signed)", .{});3774 return self.fail(src, "TODO set register with compare flags value (signed)", .{});
...@@ -3485,40 +3778,43 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -3485,40 +3778,43 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
3485 // register is the fastest way to zero a register.3778 // register is the fastest way to zero a register.
3486 if (x == 0) {3779 if (x == 0) {
3487 // The encoding for `xor r32, r32` is `0x31 /r`.3780 // The encoding for `xor r32, r32` is `0x31 /r`.
3488 // Section 3.1.1.1 of the Intel x64 Manual states that "/r indicates that the3781 const encoder = try X8664Encoder.init(self.code, 3);
3489 // ModR/M byte of the instruction contains a register operand and an r/m operand."3782
3490 //
3491 // R/M bytes are composed of two bits for the mode, then three bits for the register,
3492 // then three bits for the operand. Since we're zeroing a register, the two three-bit
3493 // values will be identical, and the mode is three (the raw register value).
3494 //
3495 // If we're accessing e.g. r8d, we need to use a REX prefix before the actual operation. Since3783 // If we're accessing e.g. r8d, we need to use a REX prefix before the actual operation. Since
3496 // this is a 32-bit operation, the W flag is set to zero. X is also zero, as we're not using a SIB.3784 // this is a 32-bit operation, the W flag is set to zero. X is also zero, as we're not using a SIB.
3497 // Both R and B are set, as we're extending, in effect, the register bits *and* the operand.3785 // Both R and B are set, as we're extending, in effect, the register bits *and* the operand.
3498 try self.code.ensureCapacity(self.code.items.len + 3);3786 encoder.rex(.{
3499 self.rex(.{ .r = reg.isExtended(), .b = reg.isExtended() });3787 .r = reg.isExtended(),
3500 const id = @as(u8, reg.id() & 0b111);3788 .b = reg.isExtended(),
3501 self.code.appendSliceAssumeCapacity(&[_]u8{ 0x31, 0xC0 | id << 3 | id });3789 });
3790 encoder.opcode_1byte(0x31);
3791 // Section 3.1.1.1 of the Intel x64 Manual states that "/r indicates that the
3792 // ModR/M byte of the instruction contains a register operand and an r/m operand."
3793 encoder.modRm_direct(
3794 reg.low_id(),
3795 reg.low_id(),
3796 );
3797
3502 return;3798 return;
3503 }3799 }
3504 if (x <= math.maxInt(u32)) {3800 if (x <= math.maxInt(i32)) {
3505 // Next best case: if we set the lower four bytes, the upper four will be zeroed.3801 // Next best case: if we set the lower four bytes, the upper four will be zeroed.
3506 //3802 //
3507 // The encoding for `mov IMM32 -> REG` is (0xB8 + R) IMM.3803 // The encoding for `mov IMM32 -> REG` is (0xB8 + R) IMM.
3508 if (reg.isExtended()) {3804
3509 // Just as with XORing, we need a REX prefix. This time though, we only3805 const encoder = try X8664Encoder.init(self.code, 6);
3510 // need the B bit set, as we're extending the opcode's register field,3806 // Just as with XORing, we need a REX prefix. This time though, we only
3511 // and there is no Mod R/M byte.3807 // need the B bit set, as we're extending the opcode's register field,
3512 //3808 // and there is no Mod R/M byte.
3513 // Thus, we need b01000001, or 0x41.3809 encoder.rex(.{
3514 try self.code.resize(self.code.items.len + 6);3810 .b = reg.isExtended(),
3515 self.code.items[self.code.items.len - 6] = 0x41;3811 });
3516 } else {3812 encoder.opcode_withReg(0xB8, reg.low_id());
3517 try self.code.resize(self.code.items.len + 5);3813
3518 }3814 // no ModR/M byte
3519 self.code.items[self.code.items.len - 5] = 0xB8 | @as(u8, reg.id() & 0b111);3815
3520 const imm_ptr = self.code.items[self.code.items.len - 4 ..][0..4];3816 // IMM
3521 mem.writeIntLittle(u32, imm_ptr, @intCast(u32, x));3817 encoder.imm32(@intCast(i32, x));
3522 return;3818 return;
3523 }3819 }
3524 // Worst case: we need to load the 64-bit register with the IMM. GNU's assemblers calls3820 // Worst case: we need to load the 64-bit register with the IMM. GNU's assemblers calls
...@@ -3528,79 +3824,98 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -3528,79 +3824,98 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
3528 // This encoding is, in fact, the *same* as the one used for 32-bit loads. The only3824 // This encoding is, in fact, the *same* as the one used for 32-bit loads. The only
3529 // difference is that we set REX.W before the instruction, which extends the load to3825 // difference is that we set REX.W before the instruction, which extends the load to
3530 // 64-bit and uses the full bit-width of the register.3826 // 64-bit and uses the full bit-width of the register.
3531 //3827 {
3532 // Since we always need a REX here, let's just check if we also need to set REX.B.3828 const encoder = try X8664Encoder.init(self.code, 10);
3533 //3829 encoder.rex(.{
3534 // In this case, the encoding of the REX byte is 0b0100100B3830 .w = true,
3535 try self.code.ensureCapacity(self.code.items.len + 10);3831 .b = reg.isExtended(),
3536 self.rex(.{ .w = reg.size() == 64, .b = reg.isExtended() });3832 });
3537 self.code.items.len += 9;3833 encoder.opcode_withReg(0xB8, reg.low_id());
3538 self.code.items[self.code.items.len - 9] = 0xB8 | @as(u8, reg.id() & 0b111);3834 encoder.imm64(x);
3539 const imm_ptr = self.code.items[self.code.items.len - 8 ..][0..8];3835 }
3540 mem.writeIntLittle(u64, imm_ptr, x);
3541 },3836 },
3542 .embedded_in_code => |code_offset| {3837 .embedded_in_code => |code_offset| {
3543 // We need the offset from RIP in a signed i32 twos complement.3838 // We need the offset from RIP in a signed i32 twos complement.
3544 // The instruction is 7 bytes long and RIP points to the next instruction.3839 // The instruction is 7 bytes long and RIP points to the next instruction.
3545 try self.code.ensureCapacity(self.code.items.len + 7);3840
3546 // 64-bit LEA is encoded as REX.W 8D /r. If the register is extended, the REX byte is modified,3841 // 64-bit LEA is encoded as REX.W 8D /r.
3547 // but the operation size is unchanged. Since we're using a disp32, we want mode 0 and lower three3842 const rip = self.code.items.len + 7;
3548 // bits as five.
3549 // REX 0x8D 0b00RRR101, where RRR is the lower three bits of the id.
3550 self.rex(.{ .w = reg.size() == 64, .b = reg.isExtended() });
3551 self.code.items.len += 6;
3552 const rip = self.code.items.len;
3553 const big_offset = @intCast(i64, code_offset) - @intCast(i64, rip);3843 const big_offset = @intCast(i64, code_offset) - @intCast(i64, rip);
3554 const offset = @intCast(i32, big_offset);3844 const offset = @intCast(i32, big_offset);
3555 self.code.items[self.code.items.len - 6] = 0x8D;3845 const encoder = try X8664Encoder.init(self.code, 7);
3556 self.code.items[self.code.items.len - 5] = 0b101 | (@as(u8, reg.id() & 0b111) << 3);3846
3557 const imm_ptr = self.code.items[self.code.items.len - 4 ..][0..4];3847 // byte 1, always exists because w = true
3558 mem.writeIntLittle(i32, imm_ptr, offset);3848 encoder.rex(.{
3849 .w = true,
3850 .r = reg.isExtended(),
3851 });
3852 // byte 2
3853 encoder.opcode_1byte(0x8D);
3854 // byte 3
3855 encoder.modRm_RIPDisp32(reg.low_id());
3856 // byte 4-7
3857 encoder.disp32(offset);
3858
3859 // Double check that we haven't done any math errors
3860 assert(rip == self.code.items.len);
3559 },3861 },
3560 .register => |src_reg| {3862 .register => |src_reg| {
3561 // If the registers are the same, nothing to do.3863 // If the registers are the same, nothing to do.
3562 if (src_reg.id() == reg.id())3864 if (src_reg.id() == reg.id())
3563 return;3865 return;
35643866
3565 // This is a variant of 8B /r. Since we're using 64-bit moves, we require a REX.3867 // This is a variant of 8B /r.
3566 // This is thus three bytes: REX 0x8B R/M.3868 const abi_size = ty.abiSize(self.target.*);
3567 // If the destination is extended, the R field must be 1.3869 const encoder = try X8664Encoder.init(self.code, 3);
3568 // If the *source* is extended, the B field must be 1.3870 encoder.rex(.{
3569 // Since the register is being accessed directly, the R/M mode is three. The reg field (the middle3871 .w = abi_size == 8,
3570 // three bits) contain the destination, and the R/M field (the lower three bits) contain the source.3872 .r = reg.isExtended(),
3571 try self.code.ensureCapacity(self.code.items.len + 3);3873 .b = src_reg.isExtended(),
3572 self.rex(.{ .w = reg.size() == 64, .r = reg.isExtended(), .b = src_reg.isExtended() });3874 });
3573 const R = 0xC0 | (@as(u8, reg.id() & 0b111) << 3) | @as(u8, src_reg.id() & 0b111);3875 encoder.opcode_1byte(0x8B);
3574 self.code.appendSliceAssumeCapacity(&[_]u8{ 0x8B, R });3876 encoder.modRm_direct(reg.low_id(), src_reg.low_id());
3575 },3877 },
3576 .memory => |x| {3878 .memory => |x| {
3577 if (self.bin_file.options.pie) {3879 if (self.bin_file.options.pie) {
3578 // RIP-relative displacement to the entry in the GOT table.3880 // RIP-relative displacement to the entry in the GOT table.
3881 const abi_size = ty.abiSize(self.target.*);
3882 const encoder = try X8664Encoder.init(self.code, 10);
3883
3884 // LEA reg, [<offset>]
3885
3886 // We encode the instruction FIRST because prefixes may or may not appear.
3887 // After we encode the instruction, we will know that the displacement bytes
3888 // for [<offset>] will be at self.code.items.len - 4.
3889 encoder.rex(.{
3890 .w = true, // force 64 bit because loading an address (to the GOT)
3891 .r = reg.isExtended(),
3892 });
3893 encoder.opcode_1byte(0x8D);
3894 encoder.modRm_RIPDisp32(reg.low_id());
3895 encoder.disp32(0);
3896
3579 // TODO we should come up with our own, backend independent relocation types3897 // TODO we should come up with our own, backend independent relocation types
3580 // which each backend (Elf, MachO, etc.) would then translate into an actual3898 // which each backend (Elf, MachO, etc.) would then translate into an actual
3581 // fixup when linking.3899 // fixup when linking.
3582 if (self.bin_file.cast(link.File.MachO)) |macho_file| {3900 if (self.bin_file.cast(link.File.MachO)) |macho_file| {
3583 try macho_file.pie_fixups.append(self.bin_file.allocator, .{3901 try macho_file.pie_fixups.append(self.bin_file.allocator, .{
3584 .target_addr = x,3902 .target_addr = x,
3585 .offset = self.code.items.len + 3,3903 .offset = self.code.items.len - 4,
3586 .size = 4,3904 .size = 4,
3587 });3905 });
3588 } else {3906 } else {
3589 return self.fail(src, "TODO implement genSetReg for PIE GOT indirection on this platform", .{});3907 return self.fail(src, "TODO implement genSetReg for PIE GOT indirection on this platform", .{});
3590 }3908 }
3591 try self.code.ensureCapacity(self.code.items.len + 7);
3592 self.rex(.{ .w = reg.size() == 64, .r = reg.isExtended() });
3593 self.code.appendSliceAssumeCapacity(&[_]u8{
3594 0x8D,
3595 0x05 | (@as(u8, reg.id() & 0b111) << 3),
3596 });
3597 mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), 0);
35983909
3599 try self.code.ensureCapacity(self.code.items.len + 3);3910 // MOV reg, [reg]
3600 self.rex(.{ .w = reg.size() == 64, .b = reg.isExtended(), .r = reg.isExtended() });3911 encoder.rex(.{
3601 const RM = (@as(u8, reg.id() & 0b111) << 3) | @truncate(u3, reg.id());3912 .w = abi_size == 8,
3602 self.code.appendSliceAssumeCapacity(&[_]u8{ 0x8B, RM });3913 .r = reg.isExtended(),
3603 } else if (x <= math.maxInt(u32)) {3914 .b = reg.isExtended(),
3915 });
3916 encoder.opcode_1byte(0x8B);
3917 encoder.modRm_indirectDisp0(reg.low_id(), reg.low_id());
3918 } else if (x <= math.maxInt(i32)) {
3604 // Moving from memory to a register is a variant of `8B /r`.3919 // Moving from memory to a register is a variant of `8B /r`.
3605 // Since we're using 64-bit moves, we require a REX.3920 // Since we're using 64-bit moves, we require a REX.
3606 // This variant also requires a SIB, as it would otherwise be RIP-relative.3921 // This variant also requires a SIB, as it would otherwise be RIP-relative.
...@@ -3608,14 +3923,18 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -3608,14 +3923,18 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
3608 // The SIB must be 0x25, to indicate a disp32 with no scaled index.3923 // The SIB must be 0x25, to indicate a disp32 with no scaled index.
3609 // 0b00RRR100, where RRR is the lower three bits of the register ID.3924 // 0b00RRR100, where RRR is the lower three bits of the register ID.
3610 // The instruction is thus eight bytes; REX 0x8B 0b00RRR100 0x25 followed by a four-byte disp32.3925 // The instruction is thus eight bytes; REX 0x8B 0b00RRR100 0x25 followed by a four-byte disp32.
3611 try self.code.ensureCapacity(self.code.items.len + 8);3926 const abi_size = ty.abiSize(self.target.*);
3612 self.rex(.{ .w = reg.size() == 64, .b = reg.isExtended() });3927 const encoder = try X8664Encoder.init(self.code, 8);
3613 self.code.appendSliceAssumeCapacity(&[_]u8{3928 encoder.rex(.{
3614 0x8B,3929 .w = abi_size == 8,
3615 0x04 | (@as(u8, reg.id() & 0b111) << 3), // R3930 .r = reg.isExtended(),
3616 0x25,
3617 });3931 });
3618 mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), @intCast(u32, x));3932 encoder.opcode_1byte(0x8B);
3933 // effective address = [SIB]
3934 encoder.modRm_SIBDisp0(reg.low_id());
3935 // SIB = disp32
3936 encoder.sib_disp32();
3937 encoder.disp32(@intCast(i32, x));
3619 } else {3938 } else {
3620 // If this is RAX, we can use a direct load; otherwise, we need to load the address, then indirectly load3939 // If this is RAX, we can use a direct load; otherwise, we need to load the address, then indirectly load
3621 // the value.3940 // the value.
...@@ -3623,12 +3942,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -3623,12 +3942,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
3623 // REX.W 0xA1 moffs64*3942 // REX.W 0xA1 moffs64*
3624 // moffs64* is a 64-bit offset "relative to segment base", which really just means the3943 // moffs64* is a 64-bit offset "relative to segment base", which really just means the
3625 // absolute address for all practical purposes.3944 // absolute address for all practical purposes.
3626 try self.code.resize(self.code.items.len + 10);3945
3627 // REX.W == 0x483946 const encoder = try X8664Encoder.init(self.code, 10);
3628 self.code.items[self.code.items.len - 10] = 0x48;3947 encoder.rex(.{
3629 self.code.items[self.code.items.len - 9] = 0xA1;3948 .w = true,
3630 const imm_ptr = self.code.items[self.code.items.len - 8 ..][0..8];3949 });
3631 mem.writeIntLittle(u64, imm_ptr, x);3950 encoder.opcode_1byte(0xA1);
3951 encoder.writeIntLittle(u64, x);
3632 } else {3952 } else {
3633 // This requires two instructions; a move imm as used above, followed by an indirect load using the register3953 // This requires two instructions; a move imm as used above, followed by an indirect load using the register
3634 // as the address and the register as the destination.3954 // as the address and the register as the destination.
...@@ -3645,40 +3965,41 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -3645,40 +3965,41 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
3645 // Now, the register contains the address of the value to load into it3965 // Now, the register contains the address of the value to load into it
3646 // Currently, we're only allowing 64-bit registers, so we need the `REX.W 8B /r` variant.3966 // Currently, we're only allowing 64-bit registers, so we need the `REX.W 8B /r` variant.
3647 // TODO: determine whether to allow other sized registers, and if so, handle them properly.3967 // TODO: determine whether to allow other sized registers, and if so, handle them properly.
3648 // This operation requires three bytes: REX 0x8B R/M3968
3649 try self.code.ensureCapacity(self.code.items.len + 3);3969 // mov reg, [reg]
3650 // For this operation, we want R/M mode *zero* (use register indirectly), and the two register3970 const abi_size = ty.abiSize(self.target.*);
3651 // values must match. Thus, it's 00ABCABC where ABC is the lower three bits of the register ID.3971 const encoder = try X8664Encoder.init(self.code, 3);
3652 //3972 encoder.rex(.{
3653 // Furthermore, if this is an extended register, both B and R must be set in the REX byte, as *both*3973 .w = abi_size == 8,
3654 // register operands need to be marked as extended.3974 .r = reg.isExtended(),
3655 self.rex(.{ .w = reg.size() == 64, .b = reg.isExtended(), .r = reg.isExtended() });3975 .b = reg.isExtended(),
3656 const RM = (@as(u8, reg.id() & 0b111) << 3) | @truncate(u3, reg.id());3976 });
3657 self.code.appendSliceAssumeCapacity(&[_]u8{ 0x8B, RM });3977 encoder.opcode_1byte(0x8B);
3978 encoder.modRm_indirectDisp0(reg.low_id(), reg.low_id());
3658 }3979 }
3659 }3980 }
3660 },3981 },
3661 .stack_offset => |unadjusted_off| {3982 .stack_offset => |unadjusted_off| {
3662 try self.code.ensureCapacity(self.code.items.len + 7);3983 const abi_size = ty.abiSize(self.target.*);
3663 const size_bytes = @divExact(reg.size(), 8);3984 const off = unadjusted_off + abi_size;
3664 const off = unadjusted_off + size_bytes;3985 if (off < std.math.minInt(i32) or off > std.math.maxInt(i32)) {
3665 self.rex(.{ .w = reg.size() == 64, .r = reg.isExtended() });3986 return self.fail(src, "stack offset too large", .{});
3666 const reg_id: u8 = @truncate(u3, reg.id());3987 }
3667 if (off <= 128) {3988 const ioff = -@intCast(i32, off);
3989 const encoder = try X8664Encoder.init(self.code, 3);
3990 encoder.rex(.{
3991 .w = abi_size == 8,
3992 .r = reg.isExtended(),
3993 });
3994 encoder.opcode_1byte(0x8B);
3995 if (std.math.minInt(i8) <= ioff and ioff <= std.math.maxInt(i8)) {
3668 // Example: 48 8b 4d 7f mov rcx,QWORD PTR [rbp+0x7f]3996 // Example: 48 8b 4d 7f mov rcx,QWORD PTR [rbp+0x7f]
3669 const RM = @as(u8, 0b01_000_101) | (reg_id << 3);3997 encoder.modRm_indirectDisp8(reg.low_id(), Register.ebp.low_id());
3670 const negative_offset = @intCast(i8, -@intCast(i32, off));3998 encoder.disp8(@intCast(i8, ioff));
3671 const twos_comp = @bitCast(u8, negative_offset);
3672 self.code.appendSliceAssumeCapacity(&[_]u8{ 0x8b, RM, twos_comp });
3673 } else if (off <= 2147483648) {
3674 // Example: 48 8b 8d 80 00 00 00 mov rcx,QWORD PTR [rbp+0x80]
3675 const RM = @as(u8, 0b10_000_101) | (reg_id << 3);
3676 const negative_offset = @intCast(i32, -@intCast(i33, off));
3677 const twos_comp = @bitCast(u32, negative_offset);
3678 self.code.appendSliceAssumeCapacity(&[_]u8{ 0x8b, RM });
3679 mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), twos_comp);
3680 } else {3999 } else {
3681 return self.fail(src, "stack offset too large", .{});4000 // Example: 48 8b 8d 80 00 00 00 mov rcx,QWORD PTR [rbp+0x80]
4001 encoder.modRm_indirectDisp32(reg.low_id(), Register.ebp.low_id());
4002 encoder.disp32(ioff);
3682 }4003 }
3683 },4004 },
3684 },4005 },
src/codegen/x86_64.zig+497
...@@ -1,4 +1,9 @@...@@ -1,4 +1,9 @@
1const std = @import("std");1const std = @import("std");
2const testing = std.testing;
3const mem = std.mem;
4const assert = std.debug.assert;
5const ArrayList = std.ArrayList;
6const Allocator = std.mem.Allocator;
2const Type = @import("../Type.zig");7const Type = @import("../Type.zig");
3const DW = std.dwarf;8const DW = std.dwarf;
49
...@@ -68,6 +73,11 @@ pub const Register = enum(u8) {...@@ -68,6 +73,11 @@ pub const Register = enum(u8) {
68 return @truncate(u4, @enumToInt(self));73 return @truncate(u4, @enumToInt(self));
69 }74 }
7075
76 /// Like id, but only returns the lower 3 bits.
77 pub fn low_id(self: Register) u3 {
78 return @truncate(u3, @enumToInt(self));
79 }
80
71 /// Returns the index into `callee_preserved_regs`.81 /// Returns the index into `callee_preserved_regs`.
72 pub fn allocIndex(self: Register) ?u4 {82 pub fn allocIndex(self: Register) ?u4 {
73 return switch (self) {83 return switch (self) {
...@@ -136,6 +146,493 @@ pub const callee_preserved_regs = [_]Register{ .rax, .rcx, .rdx, .rsi, .rdi, .r8...@@ -136,6 +146,493 @@ pub const callee_preserved_regs = [_]Register{ .rax, .rcx, .rdx, .rsi, .rdi, .r8
136pub const c_abi_int_param_regs = [_]Register{ .rdi, .rsi, .rdx, .rcx, .r8, .r9 };146pub const c_abi_int_param_regs = [_]Register{ .rdi, .rsi, .rdx, .rcx, .r8, .r9 };
137pub const c_abi_int_return_regs = [_]Register{ .rax, .rdx };147pub const c_abi_int_return_regs = [_]Register{ .rax, .rdx };
138148
149/// Encoding helper functions for x86_64 instructions
150///
151/// Many of these helpers do very little, but they can help make things
152/// slightly more readable with more descriptive field names / function names.
153///
154/// Some of them also have asserts to ensure that we aren't doing dumb things.
155/// For example, trying to use register 4 (esp) in an indirect modr/m byte is illegal,
156/// you need to encode it with an SIB byte.
157///
158/// Note that ALL of these helper functions will assume capacity,
159/// so ensure that the `code` has sufficient capacity before using them.
160/// The `init` method is the recommended way to ensure capacity.
161pub const Encoder = struct {
162 /// Non-owning reference to the code array
163 code: *ArrayList(u8),
164
165 const Self = @This();
166
167 /// Wrap `code` in Encoder to make it easier to call these helper functions
168 ///
169 /// maximum_inst_size should contain the maximum number of bytes
170 /// that the encoded instruction will take.
171 /// This is because the helper functions will assume capacity
172 /// in order to avoid bounds checking.
173 pub fn init(code: *ArrayList(u8), maximum_inst_size: u8) !Self {
174 try code.ensureCapacity(code.items.len + maximum_inst_size);
175 return Self{ .code = code };
176 }
177
178 /// Directly write a number to the code array with big endianness
179 pub fn writeIntBig(self: Self, comptime T: type, value: T) void {
180 mem.writeIntBig(
181 T,
182 self.code.addManyAsArrayAssumeCapacity(@divExact(@typeInfo(T).Int.bits, 8)),
183 value,
184 );
185 }
186
187 /// Directly write a number to the code array with little endianness
188 pub fn writeIntLittle(self: Self, comptime T: type, value: T) void {
189 mem.writeIntLittle(
190 T,
191 self.code.addManyAsArrayAssumeCapacity(@divExact(@typeInfo(T).Int.bits, 8)),
192 value,
193 );
194 }
195
196 // --------
197 // Prefixes
198 // --------
199
200 pub const LegacyPrefixes = packed struct {
201 /// LOCK
202 prefix_f0: bool = false,
203 /// REPNZ, REPNE, REP, Scalar Double-precision
204 prefix_f2: bool = false,
205 /// REPZ, REPE, REP, Scalar Single-precision
206 prefix_f3: bool = false,
207
208 /// CS segment override or Branch not taken
209 prefix_2e: bool = false,
210 /// DS segment override
211 prefix_36: bool = false,
212 /// ES segment override
213 prefix_26: bool = false,
214 /// FS segment override
215 prefix_64: bool = false,
216 /// GS segment override
217 prefix_65: bool = false,
218
219 /// Branch taken
220 prefix_3e: bool = false,
221
222 /// Operand size override (enables 16 bit operation)
223 prefix_66: bool = false,
224
225 /// Address size override (enables 16 bit address size)
226 prefix_67: bool = false,
227
228 padding: u5 = 0,
229 };
230
231 /// Encodes legacy prefixes
232 pub fn legacyPrefixes(self: Self, prefixes: LegacyPrefixes) void {
233 if (@bitCast(u16, prefixes) != 0) {
234 // Hopefully this path isn't taken very often, so we'll do it the slow way for now
235
236 // LOCK
237 if (prefixes.prefix_f0) self.code.appendAssumeCapacity(0xf0);
238 // REPNZ, REPNE, REP, Scalar Double-precision
239 if (prefixes.prefix_f2) self.code.appendAssumeCapacity(0xf2);
240 // REPZ, REPE, REP, Scalar Single-precision
241 if (prefixes.prefix_f3) self.code.appendAssumeCapacity(0xf3);
242
243 // CS segment override or Branch not taken
244 if (prefixes.prefix_2e) self.code.appendAssumeCapacity(0x2e);
245 // DS segment override
246 if (prefixes.prefix_36) self.code.appendAssumeCapacity(0x36);
247 // ES segment override
248 if (prefixes.prefix_26) self.code.appendAssumeCapacity(0x26);
249 // FS segment override
250 if (prefixes.prefix_64) self.code.appendAssumeCapacity(0x64);
251 // GS segment override
252 if (prefixes.prefix_65) self.code.appendAssumeCapacity(0x65);
253
254 // Branch taken
255 if (prefixes.prefix_3e) self.code.appendAssumeCapacity(0x3e);
256
257 // Operand size override
258 if (prefixes.prefix_66) self.code.appendAssumeCapacity(0x66);
259
260 // Address size override
261 if (prefixes.prefix_67) self.code.appendAssumeCapacity(0x67);
262 }
263 }
264
265 /// Use 16 bit operand size
266 ///
267 /// Note that this flag is overridden by REX.W, if both are present.
268 pub fn prefix16BitMode(self: Self) void {
269 self.code.appendAssumeCapacity(0x66);
270 }
271
272 /// From section 2.2.1.2 of the manual, REX is encoded as b0100WRXB
273 pub const Rex = struct {
274 /// Wide, enables 64-bit operation
275 w: bool = false,
276 /// Extends the reg field in the ModR/M byte
277 r: bool = false,
278 /// Extends the index field in the SIB byte
279 x: bool = false,
280 /// Extends the r/m field in the ModR/M byte,
281 /// or the base field in the SIB byte,
282 /// or the reg field in the Opcode byte
283 b: bool = false,
284 };
285
286 /// Encodes a REX prefix byte given all the fields
287 ///
288 /// Use this byte whenever you need 64 bit operation,
289 /// or one of reg, index, r/m, base, or opcode-reg might be extended.
290 ///
291 /// See struct `Rex` for a description of each field.
292 ///
293 /// Does not add a prefix byte if none of the fields are set!
294 pub fn rex(self: Self, byte: Rex) void {
295 var value: u8 = 0b0100_0000;
296
297 if (byte.w) value |= 0b1000;
298 if (byte.r) value |= 0b0100;
299 if (byte.x) value |= 0b0010;
300 if (byte.b) value |= 0b0001;
301
302 if (value != 0b0100_0000) {
303 self.code.appendAssumeCapacity(value);
304 }
305 }
306
307 // ------
308 // Opcode
309 // ------
310
311 /// Encodes a 1 byte opcode
312 pub fn opcode_1byte(self: Self, opcode: u8) void {
313 self.code.appendAssumeCapacity(opcode);
314 }
315
316 /// Encodes a 2 byte opcode
317 ///
318 /// e.g. IMUL has the opcode 0x0f 0xaf, so you use
319 ///
320 /// encoder.opcode_2byte(0x0f, 0xaf);
321 pub fn opcode_2byte(self: Self, prefix: u8, opcode: u8) void {
322 self.code.appendAssumeCapacity(prefix);
323 self.code.appendAssumeCapacity(opcode);
324 }
325
326 /// Encodes a 1 byte opcode with a reg field
327 ///
328 /// Remember to add a REX prefix byte if reg is extended!
329 pub fn opcode_withReg(self: Self, opcode: u8, reg: u3) void {
330 assert(opcode & 0b111 == 0);
331 self.code.appendAssumeCapacity(opcode | reg);
332 }
333
334 // ------
335 // ModR/M
336 // ------
337
338 /// Construct a ModR/M byte given all the fields
339 ///
340 /// Remember to add a REX prefix byte if reg or rm are extended!
341 pub fn modRm(self: Self, mod: u2, reg_or_opx: u3, rm: u3) void {
342 self.code.appendAssumeCapacity(
343 @as(u8, mod) << 6 | @as(u8, reg_or_opx) << 3 | rm,
344 );
345 }
346
347 /// Construct a ModR/M byte using direct r/m addressing
348 /// r/m effective address: r/m
349 ///
350 /// Note reg's effective address is always just reg for the ModR/M byte.
351 /// Remember to add a REX prefix byte if reg or rm are extended!
352 pub fn modRm_direct(self: Self, reg_or_opx: u3, rm: u3) void {
353 self.modRm(0b11, reg_or_opx, rm);
354 }
355
356 /// Construct a ModR/M byte using indirect r/m addressing
357 /// r/m effective address: [r/m]
358 ///
359 /// Note reg's effective address is always just reg for the ModR/M byte.
360 /// Remember to add a REX prefix byte if reg or rm are extended!
361 pub fn modRm_indirectDisp0(self: Self, reg_or_opx: u3, rm: u3) void {
362 assert(rm != 4 and rm != 5);
363 self.modRm(0b00, reg_or_opx, rm);
364 }
365
366 /// Construct a ModR/M byte using indirect SIB addressing
367 /// r/m effective address: [SIB]
368 ///
369 /// Note reg's effective address is always just reg for the ModR/M byte.
370 /// Remember to add a REX prefix byte if reg or rm are extended!
371 pub fn modRm_SIBDisp0(self: Self, reg_or_opx: u3) void {
372 self.modRm(0b00, reg_or_opx, 0b100);
373 }
374
375 /// Construct a ModR/M byte using RIP-relative addressing
376 /// r/m effective address: [RIP + disp32]
377 ///
378 /// Note reg's effective address is always just reg for the ModR/M byte.
379 /// Remember to add a REX prefix byte if reg or rm are extended!
380 pub fn modRm_RIPDisp32(self: Self, reg_or_opx: u3) void {
381 self.modRm(0b00, reg_or_opx, 0b101);
382 }
383
384 /// Construct a ModR/M byte using indirect r/m with a 8bit displacement
385 /// r/m effective address: [r/m + disp8]
386 ///
387 /// Note reg's effective address is always just reg for the ModR/M byte.
388 /// Remember to add a REX prefix byte if reg or rm are extended!
389 pub fn modRm_indirectDisp8(self: Self, reg_or_opx: u3, rm: u3) void {
390 assert(rm != 4);
391 self.modRm(0b01, reg_or_opx, rm);
392 }
393
394 /// Construct a ModR/M byte using indirect SIB with a 8bit displacement
395 /// r/m effective address: [SIB + disp8]
396 ///
397 /// Note reg's effective address is always just reg for the ModR/M byte.
398 /// Remember to add a REX prefix byte if reg or rm are extended!
399 pub fn modRm_SIBDisp8(self: Self, reg_or_opx: u3) void {
400 self.modRm(0b01, reg_or_opx, 0b100);
401 }
402
403 /// Construct a ModR/M byte using indirect r/m with a 32bit displacement
404 /// r/m effective address: [r/m + disp32]
405 ///
406 /// Note reg's effective address is always just reg for the ModR/M byte.
407 /// Remember to add a REX prefix byte if reg or rm are extended!
408 pub fn modRm_indirectDisp32(self: Self, reg_or_opx: u3, rm: u3) void {
409 assert(rm != 4);
410 self.modRm(0b10, reg_or_opx, rm);
411 }
412
413 /// Construct a ModR/M byte using indirect SIB with a 32bit displacement
414 /// r/m effective address: [SIB + disp32]
415 ///
416 /// Note reg's effective address is always just reg for the ModR/M byte.
417 /// Remember to add a REX prefix byte if reg or rm are extended!
418 pub fn modRm_SIBDisp32(self: Self, reg_or_opx: u3) void {
419 self.modRm(0b10, reg_or_opx, 0b100);
420 }
421
422 // ---
423 // SIB
424 // ---
425
426 /// Construct a SIB byte given all the fields
427 ///
428 /// Remember to add a REX prefix byte if index or base are extended!
429 pub fn sib(self: Self, scale: u2, index: u3, base: u3) void {
430 self.code.appendAssumeCapacity(
431 @as(u8, scale) << 6 | @as(u8, index) << 3 | base,
432 );
433 }
434
435 /// Construct a SIB byte with scale * index + base, no frills.
436 /// r/m effective address: [base + scale * index]
437 ///
438 /// Remember to add a REX prefix byte if index or base are extended!
439 pub fn sib_scaleIndexBase(self: Self, scale: u2, index: u3, base: u3) void {
440 assert(base != 5);
441
442 self.sib(scale, index, base);
443 }
444
445 /// Construct a SIB byte with scale * index + disp32
446 /// r/m effective address: [scale * index + disp32]
447 ///
448 /// Remember to add a REX prefix byte if index or base are extended!
449 pub fn sib_scaleIndexDisp32(self: Self, scale: u2, index: u3) void {
450 assert(index != 4);
451
452 // scale is actually ignored
453 // index = 4 means no index
454 // base = 5 means no base, if mod == 0.
455 self.sib(scale, index, 5);
456 }
457
458 /// Construct a SIB byte with just base
459 /// r/m effective address: [base]
460 ///
461 /// Remember to add a REX prefix byte if index or base are extended!
462 pub fn sib_base(self: Self, base: u3) void {
463 assert(base != 5);
464
465 // scale is actually ignored
466 // index = 4 means no index
467 self.sib(0, 4, base);
468 }
469
470 /// Construct a SIB byte with just disp32
471 /// r/m effective address: [disp32]
472 ///
473 /// Remember to add a REX prefix byte if index or base are extended!
474 pub fn sib_disp32(self: Self) void {
475 // scale is actually ignored
476 // index = 4 means no index
477 // base = 5 means no base, if mod == 0.
478 self.sib(0, 4, 5);
479 }
480
481 /// Construct a SIB byte with scale * index + base + disp8
482 /// r/m effective address: [base + scale * index + disp8]
483 ///
484 /// Remember to add a REX prefix byte if index or base are extended!
485 pub fn sib_scaleIndexBaseDisp8(self: Self, scale: u2, index: u3, base: u3) void {
486 self.sib(scale, index, base);
487 }
488
489 /// Construct a SIB byte with base + disp8, no index
490 /// r/m effective address: [base + disp8]
491 ///
492 /// Remember to add a REX prefix byte if index or base are extended!
493 pub fn sib_baseDisp8(self: Self, base: u3) void {
494 // scale is ignored
495 // index = 4 means no index
496 self.sib(0, 4, base);
497 }
498
499 /// Construct a SIB byte with scale * index + base + disp32
500 /// r/m effective address: [base + scale * index + disp32]
501 ///
502 /// Remember to add a REX prefix byte if index or base are extended!
503 pub fn sib_scaleIndexBaseDisp32(self: Self, scale: u2, index: u3, base: u3) void {
504 self.sib(scale, index, base);
505 }
506
507 /// Construct a SIB byte with base + disp32, no index
508 /// r/m effective address: [base + disp32]
509 ///
510 /// Remember to add a REX prefix byte if index or base are extended!
511 pub fn sib_baseDisp32(self: Self, base: u3) void {
512 // scale is ignored
513 // index = 4 means no index
514 self.sib(0, 4, base);
515 }
516
517 // -------------------------
518 // Trivial (no bit fiddling)
519 // -------------------------
520
521 /// Encode an 8 bit immediate
522 ///
523 /// It is sign-extended to 64 bits by the cpu.
524 pub fn imm8(self: Self, imm: i8) void {
525 self.code.appendAssumeCapacity(@bitCast(u8, imm));
526 }
527
528 /// Encode an 8 bit displacement
529 ///
530 /// It is sign-extended to 64 bits by the cpu.
531 pub fn disp8(self: Self, disp: i8) void {
532 self.code.appendAssumeCapacity(@bitCast(u8, disp));
533 }
534
535 /// Encode an 16 bit immediate
536 ///
537 /// It is sign-extended to 64 bits by the cpu.
538 pub fn imm16(self: Self, imm: i16) void {
539 self.writeIntLittle(i16, imm);
540 }
541
542 /// Encode an 32 bit immediate
543 ///
544 /// It is sign-extended to 64 bits by the cpu.
545 pub fn imm32(self: Self, imm: i32) void {
546 self.writeIntLittle(i32, imm);
547 }
548
549 /// Encode an 32 bit displacement
550 ///
551 /// It is sign-extended to 64 bits by the cpu.
552 pub fn disp32(self: Self, disp: i32) void {
553 self.writeIntLittle(i32, disp);
554 }
555
556 /// Encode an 64 bit immediate
557 ///
558 /// It is sign-extended to 64 bits by the cpu.
559 pub fn imm64(self: Self, imm: u64) void {
560 self.writeIntLittle(u64, imm);
561 }
562};
563
564test "x86_64 Encoder helpers" {
565 var code = ArrayList(u8).init(testing.allocator);
566 defer code.deinit();
567
568 // simple integer multiplication
569
570 // imul eax,edi
571 // 0faf c7
572 {
573 try code.resize(0);
574 const encoder = try Encoder.init(&code, 4);
575 encoder.rex(.{
576 .r = Register.eax.isExtended(),
577 .b = Register.edi.isExtended(),
578 });
579 encoder.opcode_2byte(0x0f, 0xaf);
580 encoder.modRm_direct(
581 Register.eax.low_id(),
582 Register.edi.low_id(),
583 );
584
585 testing.expectEqualSlices(u8, &[_]u8{ 0x0f, 0xaf, 0xc7 }, code.items);
586 }
587
588 // simple mov
589
590 // mov eax,edi
591 // 89 f8
592 {
593 try code.resize(0);
594 const encoder = try Encoder.init(&code, 3);
595 encoder.rex(.{
596 .r = Register.edi.isExtended(),
597 .b = Register.eax.isExtended(),
598 });
599 encoder.opcode_1byte(0x89);
600 encoder.modRm_direct(
601 Register.edi.low_id(),
602 Register.eax.low_id(),
603 );
604
605 testing.expectEqualSlices(u8, &[_]u8{ 0x89, 0xf8 }, code.items);
606 }
607
608 // signed integer addition of 32-bit sign extended immediate to 64 bit register
609
610 // add rcx, 2147483647
611 //
612 // Using the following opcode: REX.W + 81 /0 id, we expect the following encoding
613 //
614 // 48 : REX.W set for 64 bit operand (*r*cx)
615 // 81 : opcode for "<arithmetic> with immediate"
616 // c1 : id = rcx,
617 // : c1 = 11 <-- mod = 11 indicates r/m is register (rcx)
618 // : 000 <-- opcode_extension = 0 because opcode extension is /0. /0 specifies ADD
619 // : 001 <-- 001 is rcx
620 // ffffff7f : 2147483647
621 {
622 try code.resize(0);
623 const encoder = try Encoder.init(&code, 7);
624 encoder.rex(.{ .w = true }); // use 64 bit operation
625 encoder.opcode_1byte(0x81);
626 encoder.modRm_direct(
627 0,
628 Register.rcx.low_id(),
629 );
630 encoder.imm32(2147483647);
631
632 testing.expectEqualSlices(u8, &[_]u8{ 0x48, 0x81, 0xc1, 0xff, 0xff, 0xff, 0x7f }, code.items);
633 }
634}
635
139// TODO add these registers to the enum and populate dwarfLocOp636// TODO add these registers to the enum and populate dwarfLocOp
140// // Return Address register. This is stored in `0(%rsp, "")` and is not a physical register.637// // Return Address register. This is stored in `0(%rsp, "")` and is not a physical register.
141// RA = (16, "RA"),638// RA = (16, "RA"),
test/stage2/test.zig+117-13
...@@ -318,6 +318,81 @@ pub fn addCases(ctx: *TestContext) !void {...@@ -318,6 +318,81 @@ pub fn addCases(ctx: *TestContext) !void {
318 , &[_][]const u8{":2:15: error: incompatible types: 'bool' and 'comptime_int'"});318 , &[_][]const u8{":2:15: error: incompatible types: 'bool' and 'comptime_int'"});
319 }319 }
320320
321 {
322 var case = ctx.exe("multiplying numbers at runtime and comptime", linux_x64);
323 case.addCompareOutput(
324 \\export fn _start() noreturn {
325 \\ mul(3, 4);
326 \\
327 \\ exit();
328 \\}
329 \\
330 \\fn mul(a: u32, b: u32) void {
331 \\ if (a * b != 12) unreachable;
332 \\}
333 \\
334 \\fn exit() noreturn {
335 \\ asm volatile ("syscall"
336 \\ :
337 \\ : [number] "{rax}" (231),
338 \\ [arg1] "{rdi}" (0)
339 \\ : "rcx", "r11", "memory"
340 \\ );
341 \\ unreachable;
342 \\}
343 ,
344 "",
345 );
346 // comptime function call
347 case.addCompareOutput(
348 \\export fn _start() noreturn {
349 \\ exit();
350 \\}
351 \\
352 \\fn mul(a: u32, b: u32) u32 {
353 \\ return a * b;
354 \\}
355 \\
356 \\const x = mul(3, 4);
357 \\
358 \\fn exit() noreturn {
359 \\ asm volatile ("syscall"
360 \\ :
361 \\ : [number] "{rax}" (231),
362 \\ [arg1] "{rdi}" (x - 12)
363 \\ : "rcx", "r11", "memory"
364 \\ );
365 \\ unreachable;
366 \\}
367 ,
368 "",
369 );
370 // Inline function call
371 case.addCompareOutput(
372 \\export fn _start() noreturn {
373 \\ var x: usize = 5;
374 \\ const y = mul(2, 3, x);
375 \\ exit(y - 30);
376 \\}
377 \\
378 \\fn mul(a: usize, b: usize, c: usize) callconv(.Inline) usize {
379 \\ return a * b * c;
380 \\}
381 \\
382 \\fn exit(code: usize) noreturn {
383 \\ asm volatile ("syscall"
384 \\ :
385 \\ : [number] "{rax}" (231),
386 \\ [arg1] "{rdi}" (code)
387 \\ : "rcx", "r11", "memory"
388 \\ );
389 \\ unreachable;
390 \\}
391 ,
392 "",
393 );
394 }
395
321 {396 {
322 var case = ctx.exe("assert function", linux_x64);397 var case = ctx.exe("assert function", linux_x64);
323 case.addCompareOutput(398 case.addCompareOutput(
...@@ -700,7 +775,8 @@ pub fn addCases(ctx: *TestContext) !void {...@@ -700,7 +775,8 @@ pub fn addCases(ctx: *TestContext) !void {
700 // Spilling registers to the stack.775 // Spilling registers to the stack.
701 case.addCompareOutput(776 case.addCompareOutput(
702 \\export fn _start() noreturn {777 \\export fn _start() noreturn {
703 \\ assert(add(3, 4) == 791);778 \\ assert(add(3, 4) == 1221);
779 \\ assert(mul(3, 4) == 21609);
704 \\780 \\
705 \\ exit();781 \\ exit();
706 \\}782 \\}
...@@ -716,19 +792,47 @@ pub fn addCases(ctx: *TestContext) !void {...@@ -716,19 +792,47 @@ pub fn addCases(ctx: *TestContext) !void {
716 \\ const i = g + h; // 100792 \\ const i = g + h; // 100
717 \\ const j = i + d; // 110793 \\ const j = i + d; // 110
718 \\ const k = i + j; // 210794 \\ const k = i + j; // 210
719 \\ const l = k + c; // 217795 \\ const l = j + k; // 320
720 \\ const m = l + d; // 227796 \\ const m = l + c; // 327
721 \\ const n = m + e; // 241797 \\ const n = m + d; // 337
722 \\ const o = n + f; // 265798 \\ const o = n + e; // 351
723 \\ const p = o + g; // 303799 \\ const p = o + f; // 375
724 \\ const q = p + h; // 365800 \\ const q = p + g; // 413
725 \\ const r = q + i; // 465801 \\ const r = q + h; // 475
726 \\ const s = r + j; // 575802 \\ const s = r + i; // 575
727 \\ const t = s + k; // 785803 \\ const t = s + j; // 685
728 \\ break :blk t;804 \\ const u = t + k; // 895
805 \\ const v = u + l; // 1215
806 \\ break :blk v;
807 \\ };
808 \\ const y = x + a; // 1218
809 \\ const z = y + a; // 1221
810 \\ return z;
811 \\}
812 \\
813 \\fn mul(a: u32, b: u32) u32 {
814 \\ const x: u32 = blk: {
815 \\ const c = a * a * a * a; // 81
816 \\ const d = a * a * a * b; // 108
817 \\ const e = a * a * b * a; // 108
818 \\ const f = a * a * b * b; // 144
819 \\ const g = a * b * a * a; // 108
820 \\ const h = a * b * a * b; // 144
821 \\ const i = a * b * b * a; // 144
822 \\ const j = a * b * b * b; // 192
823 \\ const k = b * a * a * a; // 108
824 \\ const l = b * a * a * b; // 144
825 \\ const m = b * a * b * a; // 144
826 \\ const n = b * a * b * b; // 192
827 \\ const o = b * b * a * a; // 144
828 \\ const p = b * b * a * b; // 192
829 \\ const q = b * b * b * a; // 192
830 \\ const r = b * b * b * b; // 256
831 \\ const s = c + d + e + f + g + h + i + j + k + l + m + n + o + p + q + r; // 2401
832 \\ break :blk s;
729 \\ };833 \\ };
730 \\ const y = x + a; // 788834 \\ const y = x * a; // 7203
731 \\ const z = y + a; // 791835 \\ const z = y * a; // 21609
732 \\ return z;836 \\ return z;
733 \\}837 \\}
734 \\838 \\