authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-30 02:31:25+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-30 06:30:25+02:00
logc8ca05e93a5ad482279c9dd95e330ed6c1027c3b
treec80cd59dea5f48141fa3c5d81889473cde1a0d66
parent1e9278d718f7eec0aaad4dc296757c70e7f0f68b
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove `sparcel` architecture tag.

What is `sparcel`, you might ask? Good question! If you take a peek in the SPARC v8 manual, §2.2, it is quite explicit that SPARC v8 is a big-endian architecture. No little-endian or mixed-endian support to be found here. On the other hand, the SPARC v9 manual, in §3.2.1.2, states that it has support for mixed-endian operation, with big-endian mode being the default. Ok, so `sparcel` must just be referring to SPARC v9 running in little-endian mode, surely? Nope: * https://github.com/llvm/llvm-project/blob/40b4fd7a3e81d32b29364a1b15337bcf817659c0/llvm/lib/Target/Sparc/SparcTargetMachine.cpp#L226 * https://github.com/llvm/llvm-project/blob/40b4fd7a3e81d32b29364a1b15337bcf817659c0/llvm/lib/Target/Sparc/SparcTargetMachine.cpp#L104 So, `sparcel` in LLVM is referring to some sort of fantastical little-endian SPARC v8 architecture. I've scoured the internet and I can find absolutely no evidence that such a thing exists or has ever existed. In fact, I can find no evidence that a little-endian implementation of SPARC v9 ever existed, either. Or any SPARC version, actually! The support was added here: https://reviews.llvm.org/D8741 Notably, there is no mention whatsoever of what CPU this might be referring to, and no justification given for the "but some are little" comment added in the patch. My best guess is that this might have been some private exercise in creating a little-endian version of SPARC that never saw the light of day. Given that SPARC v8 explicitly doesn't support little-endian operation (let alone little-endian instruction encoding!), and no CPU is known to be implemented as such, I think it's very reasonable for us to just remove this support.

21 files changed, 27 insertions(+), 55 deletions(-)

lib/compiler/aro/aro/Compilation.zig+2-2
...@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {...@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
363 \\#define __sparc_v9__ 1363 \\#define __sparc_v9__ 1
364 \\364 \\
365 ),365 ),
366 .sparc, .sparcel => try w.writeAll(366 .sparc => try w.writeAll(
367 \\#define __sparc__ 1367 \\#define __sparc__ 1
368 \\#define __sparc 1368 \\#define __sparc 1
369 \\369 \\
...@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi...@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi
534534
535 if (system_defines_mode == .include_system_defines) {535 if (system_defines_mode == .include_system_defines) {
536 try buf.appendSlice(536 try buf.appendSlice(
537 \\#define __VERSION__ "Aro 537 \\#define __VERSION__ "Aro
538 ++ @import("../backend.zig").version_str ++ "\"\n" ++538 ++ @import("../backend.zig").version_str ++ "\"\n" ++
539 \\#define __Aro__539 \\#define __Aro__
540 \\540 \\
lib/compiler/aro/aro/Driver/GCCDetector.zig+1-1
...@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(...@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
376 biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);376 biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
377 biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);377 biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
378 },378 },
379 .sparc, .sparcel => {379 .sparc => {
380 lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);380 lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
381 triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);381 triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
382 biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);382 biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
lib/compiler/aro/aro/target.zig+3-6
...@@ -58,7 +58,7 @@ pub fn intPtrType(target: std.Target) Type {...@@ -58,7 +58,7 @@ pub fn intPtrType(target: std.Target) Type {
58 .avr,58 .avr,
59 => return .{ .specifier = .int },59 => return .{ .specifier = .int },
6060
61 .sparc, .sparcel => switch (target.os.tag) {61 .sparc => switch (target.os.tag) {
62 .netbsd, .openbsd => {},62 .netbsd, .openbsd => {},
63 else => return .{ .specifier = .int },63 else => return .{ .specifier = .int },
64 },64 },
...@@ -132,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {...@@ -132,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
132 return switch (target.cpu.arch) {132 return switch (target.cpu.arch) {
133 .arm, .armeb => 4,133 .arm, .armeb => 4,
134 .aarch64, .aarch64_be => 4,134 .aarch64, .aarch64_be => 4,
135 .sparc, .sparcel, .sparc64 => 4,135 .sparc, .sparc64 => 4,
136 .riscv64 => 2,136 .riscv64 => 2,
137 else => 1,137 else => 1,
138 };138 };
...@@ -426,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian...@@ -426,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
426 .powerpc64le => "elf64lppc",426 .powerpc64le => "elf64lppc",
427 .riscv32 => "elf32lriscv",427 .riscv32 => "elf32lriscv",
428 .riscv64 => "elf64lriscv",428 .riscv64 => "elf64lriscv",
429 .sparc, .sparcel => "elf32_sparc",429 .sparc => "elf32_sparc",
430 .sparc64 => "elf64_sparc",430 .sparc64 => "elf64_sparc",
431 .loongarch32 => "elf32loongarch",431 .loongarch32 => "elf32loongarch",
432 .loongarch64 => "elf64loongarch",432 .loongarch64 => "elf64loongarch",
...@@ -466,7 +466,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {...@@ -466,7 +466,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
466 .powerpcle,466 .powerpcle,
467 .riscv32,467 .riscv32,
468 .sparc,468 .sparc,
469 .sparcel,
470 .thumb,469 .thumb,
471 .thumbeb,470 .thumbeb,
472 .x86,471 .x86,
...@@ -510,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {...@@ -510,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
510 .lanai,509 .lanai,
511 .m68k,510 .m68k,
512 .msp430,511 .msp430,
513 .sparcel,
514 .spu_2,512 .spu_2,
515 .xcore,513 .xcore,
516 .xtensa,514 .xtensa,
...@@ -592,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {...@@ -592,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
592 .riscv64 => "riscv64",590 .riscv64 => "riscv64",
593 .sparc => "sparc",591 .sparc => "sparc",
594 .sparc64 => "sparc64",592 .sparc64 => "sparc64",
595 .sparcel => "sparcel",
596 .s390x => "s390x",593 .s390x => "s390x",
597 .thumb => "thumb",594 .thumb => "thumb",
598 .thumbeb => "thumbeb",595 .thumbeb => "thumbeb",
lib/compiler/aro/aro/toolchains/Linux.zig-1
...@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {...@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
357 .powerpc,357 .powerpc,
358 .powerpcle,358 .powerpcle,
359 .sparc,359 .sparc,
360 .sparcel,
361 => return "lib32",360 => return "lib32",
362 else => {},361 else => {},
363 }362 }
lib/compiler_rt/atomics.zig+1-1
...@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {...@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
30 // On SPARC systems that lacks CAS and/or swap instructions, the only30 // On SPARC systems that lacks CAS and/or swap instructions, the only
31 // available atomic operation is a test-and-set (`ldstub`), so we force31 // available atomic operation is a test-and-set (`ldstub`), so we force
32 // every atomic memory access to go through the lock.32 // every atomic memory access to go through the lock.
33 .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,33 .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
3434
35 // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b35 // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
36 // and set this parameter accordingly.36 // and set this parameter accordingly.
lib/compiler_rt/clear_cache.zig+1-1
...@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {...@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
41 else => false,41 else => false,
42 };42 };
43 const sparc = switch (arch) {43 const sparc = switch (arch) {
44 .sparc, .sparc64, .sparcel => true,44 .sparc, .sparc64 => true,
45 else => false,45 else => false,
46 };46 };
47 const apple = switch (os) {47 const apple = switch (os) {
lib/std/Target.zig+8-18
...@@ -201,7 +201,7 @@ pub const Os = struct {...@@ -201,7 +201,7 @@ pub const Os = struct {
201 .mips, .mipsel, .mips64, .mips64el => "mips",201 .mips, .mipsel, .mips64, .mips64el => "mips",
202 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",202 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
203 .riscv32, .riscv64 => "riscv",203 .riscv32, .riscv64 => "riscv",
204 .sparc, .sparcel, .sparc64 => "sparc",204 .sparc, .sparc64 => "sparc",
205 .x86, .x86_64 => "x86",205 .x86, .x86_64 => "x86",
206 else => @tagName(arch),206 else => @tagName(arch),
207 },207 },
...@@ -1017,7 +1017,6 @@ pub const Cpu = struct {...@@ -1017,7 +1017,6 @@ pub const Cpu = struct {
1017 riscv64,1017 riscv64,
1018 sparc,1018 sparc,
1019 sparc64,1019 sparc64,
1020 sparcel,
1021 s390x,1020 s390x,
1022 thumb,1021 thumb,
1023 thumbeb,1022 thumbeb,
...@@ -1040,6 +1039,7 @@ pub const Cpu = struct {...@@ -1040,6 +1039,7 @@ pub const Cpu = struct {
1040 // LLVM tags deliberately omitted:1039 // LLVM tags deliberately omitted:
1041 // - aarch64_321040 // - aarch64_32
1042 // - r6001041 // - r600
1042 // - sparcel
1043 // - le321043 // - le32
1044 // - le641044 // - le64
1045 // - amdil1045 // - amdil
...@@ -1121,7 +1121,7 @@ pub const Cpu = struct {...@@ -1121,7 +1121,7 @@ pub const Cpu = struct {
11211121
1122 pub inline fn isSPARC(arch: Arch) bool {1122 pub inline fn isSPARC(arch: Arch) bool {
1123 return switch (arch) {1123 return switch (arch) {
1124 .sparc, .sparcel, .sparc64 => true,1124 .sparc, .sparc64 => true,
1125 else => false,1125 else => false,
1126 };1126 };
1127 }1127 }
...@@ -1171,7 +1171,6 @@ pub const Cpu = struct {...@@ -1171,7 +1171,6 @@ pub const Cpu = struct {
1171 .powerpc, .powerpcle => .PPC,1171 .powerpc, .powerpcle => .PPC,
1172 .riscv32 => .RISCV,1172 .riscv32 => .RISCV,
1173 .sparc => .SPARC,1173 .sparc => .SPARC,
1174 .sparcel => .SPARC,
1175 .thumb => .ARM,1174 .thumb => .ARM,
1176 .thumbeb => .ARM,1175 .thumbeb => .ARM,
1177 .x86 => .@"386",1176 .x86 => .@"386",
...@@ -1222,7 +1221,6 @@ pub const Cpu = struct {...@@ -1222,7 +1221,6 @@ pub const Cpu = struct {
1222 .powerpc, .powerpcle => .POWERPC,1221 .powerpc, .powerpcle => .POWERPC,
1223 .riscv32 => .RISCV32,1222 .riscv32 => .RISCV32,
1224 .sparc => .Unknown,1223 .sparc => .Unknown,
1225 .sparcel => .Unknown,
1226 .thumb => .Thumb,1224 .thumb => .Thumb,
1227 .thumbeb => .Thumb,1225 .thumbeb => .Thumb,
1228 .x86 => .I386,1226 .x86 => .I386,
...@@ -1274,7 +1272,6 @@ pub const Cpu = struct {...@@ -1274,7 +1272,6 @@ pub const Cpu = struct {
1274 .msp430,1272 .msp430,
1275 .nvptx,1273 .nvptx,
1276 .nvptx64,1274 .nvptx64,
1277 .sparcel,
1278 .powerpcle,1275 .powerpcle,
1279 .powerpc64le,1276 .powerpc64le,
1280 .riscv32,1277 .riscv32,
...@@ -1341,7 +1338,7 @@ pub const Cpu = struct {...@@ -1341,7 +1338,7 @@ pub const Cpu = struct {
1341 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",1338 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
1342 .amdgcn => "amdgpu",1339 .amdgcn => "amdgpu",
1343 .riscv32, .riscv64 => "riscv",1340 .riscv32, .riscv64 => "riscv",
1344 .sparc, .sparc64, .sparcel => "sparc",1341 .sparc, .sparc64 => "sparc",
1345 .s390x => "s390x",1342 .s390x => "s390x",
1346 .x86, .x86_64 => "x86",1343 .x86, .x86_64 => "x86",
1347 .nvptx, .nvptx64 => "nvptx",1344 .nvptx, .nvptx64 => "nvptx",
...@@ -1368,7 +1365,7 @@ pub const Cpu = struct {...@@ -1368,7 +1365,7 @@ pub const Cpu = struct {
1368 .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,1365 .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
1369 .amdgcn => &amdgpu.all_features,1366 .amdgcn => &amdgpu.all_features,
1370 .riscv32, .riscv64 => &riscv.all_features,1367 .riscv32, .riscv64 => &riscv.all_features,
1371 .sparc, .sparc64, .sparcel => &sparc.all_features,1368 .sparc, .sparc64 => &sparc.all_features,
1372 .spirv32, .spirv64 => &spirv.all_features,1369 .spirv32, .spirv64 => &spirv.all_features,
1373 .s390x => &s390x.all_features,1370 .s390x => &s390x.all_features,
1374 .x86, .x86_64 => &x86.all_features,1371 .x86, .x86_64 => &x86.all_features,
...@@ -1398,7 +1395,7 @@ pub const Cpu = struct {...@@ -1398,7 +1395,7 @@ pub const Cpu = struct {
1398 .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),1395 .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
1399 .amdgcn => comptime allCpusFromDecls(amdgpu.cpu),1396 .amdgcn => comptime allCpusFromDecls(amdgpu.cpu),
1400 .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),1397 .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
1401 .sparc, .sparc64, .sparcel => comptime allCpusFromDecls(sparc.cpu),1398 .sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu),
1402 .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),1399 .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
1403 .s390x => comptime allCpusFromDecls(s390x.cpu),1400 .s390x => comptime allCpusFromDecls(s390x.cpu),
1404 .x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),1401 .x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),
...@@ -1490,7 +1487,7 @@ pub const Cpu = struct {...@@ -1490,7 +1487,7 @@ pub const Cpu = struct {
1490 .riscv32 => &riscv.cpu.generic_rv32,1487 .riscv32 => &riscv.cpu.generic_rv32,
1491 .riscv64 => &riscv.cpu.generic_rv64,1488 .riscv64 => &riscv.cpu.generic_rv64,
1492 .spirv32, .spirv64 => &spirv.cpu.generic,1489 .spirv32, .spirv64 => &spirv.cpu.generic,
1493 .sparc, .sparcel => &sparc.cpu.generic,1490 .sparc => &sparc.cpu.generic,
1494 .sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline1491 .sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline
1495 .s390x => &s390x.cpu.generic,1492 .s390x => &s390x.cpu.generic,
1496 .x86 => &x86.cpu.i386,1493 .x86 => &x86.cpu.i386,
...@@ -1511,7 +1508,7 @@ pub const Cpu = struct {...@@ -1511,7 +1508,7 @@ pub const Cpu = struct {
1511 .x86 => &x86.cpu.pentium4,1508 .x86 => &x86.cpu.pentium4,
1512 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,1509 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
1513 .s390x => &s390x.cpu.arch8,1510 .s390x => &s390x.cpu.arch8,
1514 .sparc, .sparcel => &sparc.cpu.v8,1511 .sparc => &sparc.cpu.v8,
1515 .loongarch64 => &loongarch.cpu.loongarch64,1512 .loongarch64 => &loongarch.cpu.loongarch64,
15161513
1517 else => generic(arch),1514 else => generic(arch),
...@@ -1696,7 +1693,6 @@ pub const DynamicLinker = struct {...@@ -1696,7 +1693,6 @@ pub const DynamicLinker = struct {
1696 .linux => switch (cpu.arch) {1693 .linux => switch (cpu.arch) {
1697 .x86,1694 .x86,
1698 .sparc,1695 .sparc,
1699 .sparcel,
1700 => init("/lib/ld-linux.so.2"),1696 => init("/lib/ld-linux.so.2"),
17011697
1702 .aarch64 => init("/lib/ld-linux-aarch64.so.1"),1698 .aarch64 => init("/lib/ld-linux-aarch64.so.1"),
...@@ -1854,7 +1850,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {...@@ -1854,7 +1850,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
1854 .powerpc,1850 .powerpc,
1855 .powerpcle,1851 .powerpcle,
1856 .riscv32,1852 .riscv32,
1857 .sparcel,
1858 .thumb,1853 .thumb,
1859 .thumbeb,1854 .thumbeb,
1860 .x86,1855 .x86,
...@@ -1914,7 +1909,6 @@ pub fn stackAlignment(target: Target) u16 {...@@ -1914,7 +1909,6 @@ pub fn stackAlignment(target: Target) u16 {
1914 .mips,1909 .mips,
1915 .mipsel,1910 .mipsel,
1916 .sparc,1911 .sparc,
1917 .sparcel,
1918 => 8,1912 => 8,
1919 .aarch64,1913 .aarch64,
1920 .aarch64_be,1914 .aarch64_be,
...@@ -2075,7 +2069,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {...@@ -2075,7 +2069,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
2075 .s390x,2069 .s390x,
2076 .sparc,2070 .sparc,
2077 .sparc64,2071 .sparc64,
2078 .sparcel,
2079 .wasm32,2072 .wasm32,
2080 .wasm64,2073 .wasm64,
2081 => return 128,2074 => return 128,
...@@ -2180,7 +2173,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {...@@ -2180,7 +2173,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
2180 .mips64el,2173 .mips64el,
2181 .sparc,2174 .sparc,
2182 .sparc64,2175 .sparc64,
2183 .sparcel,
2184 .wasm32,2176 .wasm32,
2185 .wasm64,2177 .wasm64,
2186 => return 128,2178 => return 128,
...@@ -2374,7 +2366,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {...@@ -2374,7 +2366,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
2374 .mips,2366 .mips,
2375 .mipsel,2367 .mipsel,
2376 .sparc,2368 .sparc,
2377 .sparcel,
2378 .sparc64,2369 .sparc64,
2379 .lanai,2370 .lanai,
2380 .nvptx,2371 .nvptx,
...@@ -2487,7 +2478,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {...@@ -2487,7 +2478,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
2487 .mips,2478 .mips,
2488 .mipsel,2479 .mipsel,
2489 .sparc,2480 .sparc,
2490 .sparcel,
2491 .sparc64,2481 .sparc64,
2492 .lanai,2482 .lanai,
2493 .nvptx,2483 .nvptx,
lib/std/atomic.zig-1
...@@ -486,7 +486,6 @@ pub const cache_line = switch (builtin.cpu.arch) {...@@ -486,7 +486,6 @@ pub const cache_line = switch (builtin.cpu.arch) {
486 .riscv32,486 .riscv32,
487 .riscv64,487 .riscv64,
488 .sparc,488 .sparc,
489 .sparcel,
490 .sparc64,489 .sparc64,
491 => 32,490 => 32,
492491
lib/std/builtin.zig+1-1
...@@ -615,7 +615,7 @@ pub const VaList = switch (builtin.cpu.arch) {...@@ -615,7 +615,7 @@ pub const VaList = switch (builtin.cpu.arch) {
615 else => VaListPowerPc,615 else => VaListPowerPc,
616 },616 },
617 .powerpc64, .powerpc64le => *u8,617 .powerpc64, .powerpc64le => *u8,
618 .sparc, .sparcel, .sparc64 => *anyopaque,618 .sparc, .sparc64 => *anyopaque,
619 .spirv32, .spirv64 => *anyopaque,619 .spirv32, .spirv64 => *anyopaque,
620 .s390x => VaListS390x,620 .s390x => VaListS390x,
621 .wasm32, .wasm64 => *anyopaque,621 .wasm32, .wasm64 => *anyopaque,
lib/std/c.zig+3-3
...@@ -5779,7 +5779,7 @@ pub const ucontext_t = switch (native_os) {...@@ -5779,7 +5779,7 @@ pub const ucontext_t = switch (native_os) {
5779 .x86 => 4,5779 .x86 => 4,
5780 .mips, .mipsel, .mips64, .mips64el => 14,5780 .mips, .mipsel, .mips64, .mips64el => 14,
5781 .arm, .armeb, .thumb, .thumbeb => 1,5781 .arm, .armeb, .thumb, .thumbeb => 1,
5782 .sparc, .sparcel, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,5782 .sparc, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,
5783 else => 0,5783 else => 0,
5784 }5784 }
5785 ]u32,5785 ]u32,
...@@ -6821,7 +6821,7 @@ pub const pthread_key_t = switch (native_os) {...@@ -6821,7 +6821,7 @@ pub const pthread_key_t = switch (native_os) {
6821pub const padded_pthread_spin_t = switch (native_os) {6821pub const padded_pthread_spin_t = switch (native_os) {
6822 .netbsd => switch (builtin.cpu.arch) {6822 .netbsd => switch (builtin.cpu.arch) {
6823 .x86, .x86_64 => u32,6823 .x86, .x86_64 => u32,
6824 .sparc, .sparcel, .sparc64 => u32,6824 .sparc, .sparc64 => u32,
6825 else => pthread_spin_t,6825 else => pthread_spin_t,
6826 },6826 },
6827 else => void,6827 else => void,
...@@ -6834,7 +6834,7 @@ pub const pthread_spin_t = switch (native_os) {...@@ -6834,7 +6834,7 @@ pub const pthread_spin_t = switch (native_os) {
6834 .powerpc, .powerpc64, .powerpc64le => i32,6834 .powerpc, .powerpc64, .powerpc64le => i32,
6835 .x86, .x86_64 => u8,6835 .x86, .x86_64 => u8,
6836 .arm, .armeb, .thumb, .thumbeb => i32,6836 .arm, .armeb, .thumb, .thumbeb => i32,
6837 .sparc, .sparcel, .sparc64 => u8,6837 .sparc, .sparc64 => u8,
6838 .riscv32, .riscv64 => u32,6838 .riscv32, .riscv64 => u32,
6839 else => @compileError("undefined pthread_spin_t for this arch"),6839 else => @compileError("undefined pthread_spin_t for this arch"),
6840 },6840 },
lib/std/os/linux.zig+1-3
...@@ -2485,7 +2485,7 @@ pub const E = switch (native_arch) {...@@ -2485,7 +2485,7 @@ pub const E = switch (native_arch) {
24852485
2486 pub const init = errnoFromSyscall;2486 pub const init = errnoFromSyscall;
2487 },2487 },
2488 .sparc, .sparcel, .sparc64 => enum(u16) {2488 .sparc, .sparc64 => enum(u16) {
2489 /// No error occurred.2489 /// No error occurred.
2490 SUCCESS = 0,2490 SUCCESS = 0,
24912491
...@@ -4832,7 +4832,6 @@ pub const MINSIGSTKSZ = switch (native_arch) {...@@ -4832,7 +4832,6 @@ pub const MINSIGSTKSZ = switch (native_arch) {
4832 => 2048,4832 => 2048,
4833 .loongarch64,4833 .loongarch64,
4834 .sparc,4834 .sparc,
4835 .sparcel,
4836 .sparc64,4835 .sparc64,
4837 => 4096,4836 => 4096,
4838 .aarch64,4837 .aarch64,
...@@ -4869,7 +4868,6 @@ pub const SIGSTKSZ = switch (native_arch) {...@@ -4869,7 +4868,6 @@ pub const SIGSTKSZ = switch (native_arch) {
4869 .aarch64_be,4868 .aarch64_be,
4870 .loongarch64,4869 .loongarch64,
4871 .sparc,4870 .sparc,
4872 .sparcel,
4873 .sparc64,4871 .sparc64,
4874 => 16384,4872 => 16384,
4875 .powerpc64,4873 .powerpc64,
lib/std/os/linux/ioctl.zig-1
...@@ -11,7 +11,6 @@ const bits = switch (@import("builtin").cpu.arch) {...@@ -11,7 +11,6 @@ const bits = switch (@import("builtin").cpu.arch) {
11 .powerpc64le,11 .powerpc64le,
12 .sparc,12 .sparc,
13 .sparc64,13 .sparc64,
14 .sparcel,
15 => .{ .size = 13, .dir = 3, .none = 1, .read = 2, .write = 4 },14 => .{ .size = 13, .dir = 3, .none = 1, .read = 2, .write = 4 },
16 else => .{ .size = 14, .dir = 2, .none = 0, .read = 2, .write = 1 },15 else => .{ .size = 14, .dir = 2, .none = 0, .read = 2, .write = 1 },
17};16};
src/Type.zig-1
...@@ -1602,7 +1602,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {...@@ -1602,7 +1602,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
1602 .amdgcn,1602 .amdgcn,
1603 .riscv32,1603 .riscv32,
1604 .sparc,1604 .sparc,
1605 .sparcel,
1606 .s390x,1605 .s390x,
1607 .lanai,1606 .lanai,
1608 .wasm32,1607 .wasm32,
src/Zcu.zig-1
...@@ -3248,7 +3248,6 @@ pub fn atomicPtrAlignment(...@@ -3248,7 +3248,6 @@ pub fn atomicPtrAlignment(
3248 .powerpcle,3248 .powerpcle,
3249 .riscv32,3249 .riscv32,
3250 .sparc,3250 .sparc,
3251 .sparcel,
3252 .thumb,3251 .thumb,
3253 .thumbeb,3252 .thumbeb,
3254 .x86,3253 .x86,
src/codegen/llvm.zig+1-4
...@@ -69,7 +69,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {...@@ -69,7 +69,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
69 .riscv64 => "riscv64",69 .riscv64 => "riscv64",
70 .sparc => "sparc",70 .sparc => "sparc",
71 .sparc64 => "sparc64",71 .sparc64 => "sparc64",
72 .sparcel => "sparcel",
73 .s390x => "s390x",72 .s390x => "s390x",
74 .thumb => "thumb",73 .thumb => "thumb",
75 .thumbeb => "thumbeb",74 .thumbeb => "thumbeb",
...@@ -280,7 +279,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {...@@ -280,7 +279,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
280 .riscv64 => .riscv64,279 .riscv64 => .riscv64,
281 .sparc => .sparc,280 .sparc => .sparc,
282 .sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9.281 .sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9.
283 .sparcel => .sparcel,
284 .s390x => .systemz,282 .s390x => .systemz,
285 .thumb => .thumb,283 .thumb => .thumb,
286 .thumbeb => .thumbeb,284 .thumbeb => .thumbeb,
...@@ -469,7 +467,6 @@ const DataLayoutBuilder = struct {...@@ -469,7 +467,6 @@ const DataLayoutBuilder = struct {
469 .powerpcle,467 .powerpcle,
470 .riscv32,468 .riscv32,
471 .sparc,469 .sparc,
472 .sparcel,
473 .thumb,470 .thumb,
474 .thumbeb,471 .thumbeb,
475 .xtensa,472 .xtensa,
...@@ -12004,7 +12001,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {...@@ -12004,7 +12001,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
12004 llvm.LLVMInitializeRISCVAsmPrinter();12001 llvm.LLVMInitializeRISCVAsmPrinter();
12005 llvm.LLVMInitializeRISCVAsmParser();12002 llvm.LLVMInitializeRISCVAsmParser();
12006 },12003 },
12007 .sparc, .sparc64, .sparcel => {12004 .sparc, .sparc64 => {
12008 llvm.LLVMInitializeSparcTarget();12005 llvm.LLVMInitializeSparcTarget();
12009 llvm.LLVMInitializeSparcTargetInfo();12006 llvm.LLVMInitializeSparcTargetInfo();
12010 llvm.LLVMInitializeSparcTargetMC();12007 llvm.LLVMInitializeSparcTargetMC();
src/glibc.zig+2-2
...@@ -394,7 +394,7 @@ fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![...@@ -394,7 +394,7 @@ fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![
394 const arch = comp.getTarget().cpu.arch;394 const arch = comp.getTarget().cpu.arch;
395 const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;395 const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
396 const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;396 const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
397 const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;397 const is_sparc = arch == .sparc or arch == .sparc64;
398 const is_64 = comp.getTarget().ptrBitWidth() == 64;398 const is_64 = comp.getTarget().ptrBitWidth() == 64;
399399
400 const s = path.sep_str;400 const s = path.sep_str;
...@@ -532,7 +532,7 @@ fn add_include_dirs_arch(...@@ -532,7 +532,7 @@ fn add_include_dirs_arch(
532 const is_x86 = arch == .x86 or arch == .x86_64;532 const is_x86 = arch == .x86 or arch == .x86_64;
533 const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;533 const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
534 const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;534 const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
535 const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;535 const is_sparc = arch == .sparc or arch == .sparc64;
536 const is_64 = target.ptrBitWidth() == 64;536 const is_64 = target.ptrBitWidth() == 64;
537537
538 const s = path.sep_str;538 const s = path.sep_str;
src/link/Elf.zig+1-1
...@@ -5175,7 +5175,7 @@ fn getLDMOption(target: std.Target) ?[]const u8 {...@@ -5175,7 +5175,7 @@ fn getLDMOption(target: std.Target) ?[]const u8 {
5175 .powerpc => return "elf32ppclinux",5175 .powerpc => return "elf32ppclinux",
5176 .powerpc64 => return "elf64ppc",5176 .powerpc64 => return "elf64ppc",
5177 .powerpc64le => return "elf64lppc",5177 .powerpc64le => return "elf64lppc",
5178 .sparc, .sparcel => return "elf32_sparc",5178 .sparc => return "elf32_sparc",
5179 .sparc64 => return "elf64_sparc",5179 .sparc64 => return "elf64_sparc",
5180 .mips => return "elf32btsmip",5180 .mips => return "elf32btsmip",
5181 .mipsel => return "elf32ltsmip",5181 .mipsel => return "elf32ltsmip",
src/link/Plan9/aout.zig+1-1
...@@ -110,7 +110,7 @@ pub const R_MAGIC = _MAGIC(HDR_MAGIC, 28); // arm64...@@ -110,7 +110,7 @@ pub const R_MAGIC = _MAGIC(HDR_MAGIC, 28); // arm64
110pub fn magicFromArch(arch: std.Target.Cpu.Arch) !u32 {110pub fn magicFromArch(arch: std.Target.Cpu.Arch) !u32 {
111 return switch (arch) {111 return switch (arch) {
112 .x86 => I_MAGIC,112 .x86 => I_MAGIC,
113 .sparc => K_MAGIC, // TODO should sparc64 and sparcel go here?113 .sparc => K_MAGIC, // TODO should sparc64 go here?
114 .mips => V_MAGIC,114 .mips => V_MAGIC,
115 .arm => E_MAGIC,115 .arm => E_MAGIC,
116 .aarch64 => R_MAGIC,116 .aarch64 => R_MAGIC,
src/target.zig+1-3
...@@ -138,7 +138,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {...@@ -138,7 +138,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
138 .riscv64,138 .riscv64,
139 .sparc,139 .sparc,
140 .sparc64,140 .sparc64,
141 .sparcel,
142 .s390x,141 .s390x,
143 .thumb,142 .thumb,
144 .thumbeb,143 .thumbeb,
...@@ -408,7 +407,7 @@ pub fn defaultFunctionAlignment(target: std.Target) Alignment {...@@ -408,7 +407,7 @@ pub fn defaultFunctionAlignment(target: std.Target) Alignment {
408 return switch (target.cpu.arch) {407 return switch (target.cpu.arch) {
409 .arm, .armeb => .@"4",408 .arm, .armeb => .@"4",
410 .aarch64, .aarch64_be => .@"4",409 .aarch64, .aarch64_be => .@"4",
411 .sparc, .sparcel, .sparc64 => .@"4",410 .sparc, .sparc64 => .@"4",
412 .riscv64 => .@"2",411 .riscv64 => .@"2",
413 else => .@"1",412 else => .@"1",
414 };413 };
...@@ -423,7 +422,6 @@ pub fn minFunctionAlignment(target: std.Target) Alignment {...@@ -423,7 +422,6 @@ pub fn minFunctionAlignment(target: std.Target) Alignment {
423 .riscv32,422 .riscv32,
424 .riscv64,423 .riscv64,
425 .sparc,424 .sparc,
426 .sparcel,
427 .sparc64,425 .sparc64,
428 => .@"2",426 => .@"2",
429 else => .@"1",427 else => .@"1",
test/behavior/align.zig-1
...@@ -95,7 +95,6 @@ test "alignment and size of structs with 128-bit fields" {...@@ -95,7 +95,6 @@ test "alignment and size of structs with 128-bit fields" {
95 .amdgcn,95 .amdgcn,
96 .riscv32,96 .riscv32,
97 .sparc,97 .sparc,
98 .sparcel,
99 .s390x,98 .s390x,
100 .lanai,99 .lanai,
101 .wasm32,100 .wasm32,
test/llvm_targets.zig-2
...@@ -87,8 +87,6 @@ const targets = [_]std.Target.Query{...@@ -87,8 +87,6 @@ const targets = [_]std.Target.Query{
87 .{ .cpu_arch = .sparc, .os_tag = .freestanding, .abi = .none },87 .{ .cpu_arch = .sparc, .os_tag = .freestanding, .abi = .none },
88 .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .gnu },88 .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .gnu },
89 .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .none },89 .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .none },
90 .{ .cpu_arch = .sparcel, .os_tag = .freestanding, .abi = .none },
91 .{ .cpu_arch = .sparcel, .os_tag = .linux, .abi = .gnu },
92 .{ .cpu_arch = .sparc64, .os_tag = .freestanding, .abi = .none },90 .{ .cpu_arch = .sparc64, .os_tag = .freestanding, .abi = .none },
93 .{ .cpu_arch = .sparc64, .os_tag = .linux, .abi = .gnu },91 .{ .cpu_arch = .sparc64, .os_tag = .linux, .abi = .gnu },
94 //.{ .cpu_arch = .spirv32, .os_tag = .opencl, .abi = .none },92 //.{ .cpu_arch = .spirv32, .os_tag = .opencl, .abi = .none },