authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-30 02:31:25+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-30 06:30:25+02:00
logc8ca05e93a5ad482279c9dd95e330ed6c1027c3b
treec80cd59dea5f48141fa3c5d81889473cde1a0d66
parent1e9278d718f7eec0aaad4dc296757c70e7f0f68b
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove `sparcel` architecture tag.

What is `sparcel`, you might ask? Good question! If you take a peek in the SPARC v8 manual, §2.2, it is quite explicit that SPARC v8 is a big-endian architecture. No little-endian or mixed-endian support to be found here. On the other hand, the SPARC v9 manual, in §3.2.1.2, states that it has support for mixed-endian operation, with big-endian mode being the default. Ok, so `sparcel` must just be referring to SPARC v9 running in little-endian mode, surely? Nope: * https://github.com/llvm/llvm-project/blob/40b4fd7a3e81d32b29364a1b15337bcf817659c0/llvm/lib/Target/Sparc/SparcTargetMachine.cpp#L226 * https://github.com/llvm/llvm-project/blob/40b4fd7a3e81d32b29364a1b15337bcf817659c0/llvm/lib/Target/Sparc/SparcTargetMachine.cpp#L104 So, `sparcel` in LLVM is referring to some sort of fantastical little-endian SPARC v8 architecture. I've scoured the internet and I can find absolutely no evidence that such a thing exists or has ever existed. In fact, I can find no evidence that a little-endian implementation of SPARC v9 ever existed, either. Or any SPARC version, actually! The support was added here: https://reviews.llvm.org/D8741 Notably, there is no mention whatsoever of what CPU this might be referring to, and no justification given for the "but some are little" comment added in the patch. My best guess is that this might have been some private exercise in creating a little-endian version of SPARC that never saw the light of day. Given that SPARC v8 explicitly doesn't support little-endian operation (let alone little-endian instruction encoding!), and no CPU is known to be implemented as such, I think it's very reasonable for us to just remove this support.

21 files changed, 27 insertions(+), 55 deletions(-)

lib/compiler/aro/aro/Compilation.zig+2-2
......@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
363363 \\#define __sparc_v9__ 1
364364 \\
365365 ),
366 .sparc, .sparcel => try w.writeAll(
366 .sparc => try w.writeAll(
367367 \\#define __sparc__ 1
368368 \\#define __sparc 1
369369 \\
......@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi
534534
535535 if (system_defines_mode == .include_system_defines) {
536536 try buf.appendSlice(
537 \\#define __VERSION__ "Aro
537 \\#define __VERSION__ "Aro
538538 ++ @import("../backend.zig").version_str ++ "\"\n" ++
539539 \\#define __Aro__
540540 \\
lib/compiler/aro/aro/Driver/GCCDetector.zig+1-1
......@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
376376 biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
377377 biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
378378 },
379 .sparc, .sparcel => {
379 .sparc => {
380380 lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
381381 triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
382382 biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
lib/compiler/aro/aro/target.zig+3-6
......@@ -58,7 +58,7 @@ pub fn intPtrType(target: std.Target) Type {
5858 .avr,
5959 => return .{ .specifier = .int },
6060
61 .sparc, .sparcel => switch (target.os.tag) {
61 .sparc => switch (target.os.tag) {
6262 .netbsd, .openbsd => {},
6363 else => return .{ .specifier = .int },
6464 },
......@@ -132,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
132132 return switch (target.cpu.arch) {
133133 .arm, .armeb => 4,
134134 .aarch64, .aarch64_be => 4,
135 .sparc, .sparcel, .sparc64 => 4,
135 .sparc, .sparc64 => 4,
136136 .riscv64 => 2,
137137 else => 1,
138138 };
......@@ -426,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
426426 .powerpc64le => "elf64lppc",
427427 .riscv32 => "elf32lriscv",
428428 .riscv64 => "elf64lriscv",
429 .sparc, .sparcel => "elf32_sparc",
429 .sparc => "elf32_sparc",
430430 .sparc64 => "elf64_sparc",
431431 .loongarch32 => "elf32loongarch",
432432 .loongarch64 => "elf64loongarch",
......@@ -466,7 +466,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
466466 .powerpcle,
467467 .riscv32,
468468 .sparc,
469 .sparcel,
470469 .thumb,
471470 .thumbeb,
472471 .x86,
......@@ -510,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
510509 .lanai,
511510 .m68k,
512511 .msp430,
513 .sparcel,
514512 .spu_2,
515513 .xcore,
516514 .xtensa,
......@@ -592,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
592590 .riscv64 => "riscv64",
593591 .sparc => "sparc",
594592 .sparc64 => "sparc64",
595 .sparcel => "sparcel",
596593 .s390x => "s390x",
597594 .thumb => "thumb",
598595 .thumbeb => "thumbeb",
lib/compiler/aro/aro/toolchains/Linux.zig-1
......@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
357357 .powerpc,
358358 .powerpcle,
359359 .sparc,
360 .sparcel,
361360 => return "lib32",
362361 else => {},
363362 }
lib/compiler_rt/atomics.zig+1-1
......@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
3030 // On SPARC systems that lacks CAS and/or swap instructions, the only
3131 // available atomic operation is a test-and-set (`ldstub`), so we force
3232 // every atomic memory access to go through the lock.
33 .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
33 .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
3434
3535 // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
3636 // and set this parameter accordingly.
lib/compiler_rt/clear_cache.zig+1-1
......@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
4141 else => false,
4242 };
4343 const sparc = switch (arch) {
44 .sparc, .sparc64, .sparcel => true,
44 .sparc, .sparc64 => true,
4545 else => false,
4646 };
4747 const apple = switch (os) {
lib/std/Target.zig+8-18
......@@ -201,7 +201,7 @@ pub const Os = struct {
201201 .mips, .mipsel, .mips64, .mips64el => "mips",
202202 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
203203 .riscv32, .riscv64 => "riscv",
204 .sparc, .sparcel, .sparc64 => "sparc",
204 .sparc, .sparc64 => "sparc",
205205 .x86, .x86_64 => "x86",
206206 else => @tagName(arch),
207207 },
......@@ -1017,7 +1017,6 @@ pub const Cpu = struct {
10171017 riscv64,
10181018 sparc,
10191019 sparc64,
1020 sparcel,
10211020 s390x,
10221021 thumb,
10231022 thumbeb,
......@@ -1040,6 +1039,7 @@ pub const Cpu = struct {
10401039 // LLVM tags deliberately omitted:
10411040 // - aarch64_32
10421041 // - r600
1042 // - sparcel
10431043 // - le32
10441044 // - le64
10451045 // - amdil
......@@ -1121,7 +1121,7 @@ pub const Cpu = struct {
11211121
11221122 pub inline fn isSPARC(arch: Arch) bool {
11231123 return switch (arch) {
1124 .sparc, .sparcel, .sparc64 => true,
1124 .sparc, .sparc64 => true,
11251125 else => false,
11261126 };
11271127 }
......@@ -1171,7 +1171,6 @@ pub const Cpu = struct {
11711171 .powerpc, .powerpcle => .PPC,
11721172 .riscv32 => .RISCV,
11731173 .sparc => .SPARC,
1174 .sparcel => .SPARC,
11751174 .thumb => .ARM,
11761175 .thumbeb => .ARM,
11771176 .x86 => .@"386",
......@@ -1222,7 +1221,6 @@ pub const Cpu = struct {
12221221 .powerpc, .powerpcle => .POWERPC,
12231222 .riscv32 => .RISCV32,
12241223 .sparc => .Unknown,
1225 .sparcel => .Unknown,
12261224 .thumb => .Thumb,
12271225 .thumbeb => .Thumb,
12281226 .x86 => .I386,
......@@ -1274,7 +1272,6 @@ pub const Cpu = struct {
12741272 .msp430,
12751273 .nvptx,
12761274 .nvptx64,
1277 .sparcel,
12781275 .powerpcle,
12791276 .powerpc64le,
12801277 .riscv32,
......@@ -1341,7 +1338,7 @@ pub const Cpu = struct {
13411338 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
13421339 .amdgcn => "amdgpu",
13431340 .riscv32, .riscv64 => "riscv",
1344 .sparc, .sparc64, .sparcel => "sparc",
1341 .sparc, .sparc64 => "sparc",
13451342 .s390x => "s390x",
13461343 .x86, .x86_64 => "x86",
13471344 .nvptx, .nvptx64 => "nvptx",
......@@ -1368,7 +1365,7 @@ pub const Cpu = struct {
13681365 .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
13691366 .amdgcn => &amdgpu.all_features,
13701367 .riscv32, .riscv64 => &riscv.all_features,
1371 .sparc, .sparc64, .sparcel => &sparc.all_features,
1368 .sparc, .sparc64 => &sparc.all_features,
13721369 .spirv32, .spirv64 => &spirv.all_features,
13731370 .s390x => &s390x.all_features,
13741371 .x86, .x86_64 => &x86.all_features,
......@@ -1398,7 +1395,7 @@ pub const Cpu = struct {
13981395 .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
13991396 .amdgcn => comptime allCpusFromDecls(amdgpu.cpu),
14001397 .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
1401 .sparc, .sparc64, .sparcel => comptime allCpusFromDecls(sparc.cpu),
1398 .sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu),
14021399 .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
14031400 .s390x => comptime allCpusFromDecls(s390x.cpu),
14041401 .x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),
......@@ -1490,7 +1487,7 @@ pub const Cpu = struct {
14901487 .riscv32 => &riscv.cpu.generic_rv32,
14911488 .riscv64 => &riscv.cpu.generic_rv64,
14921489 .spirv32, .spirv64 => &spirv.cpu.generic,
1493 .sparc, .sparcel => &sparc.cpu.generic,
1490 .sparc => &sparc.cpu.generic,
14941491 .sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline
14951492 .s390x => &s390x.cpu.generic,
14961493 .x86 => &x86.cpu.i386,
......@@ -1511,7 +1508,7 @@ pub const Cpu = struct {
15111508 .x86 => &x86.cpu.pentium4,
15121509 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
15131510 .s390x => &s390x.cpu.arch8,
1514 .sparc, .sparcel => &sparc.cpu.v8,
1511 .sparc => &sparc.cpu.v8,
15151512 .loongarch64 => &loongarch.cpu.loongarch64,
15161513
15171514 else => generic(arch),
......@@ -1696,7 +1693,6 @@ pub const DynamicLinker = struct {
16961693 .linux => switch (cpu.arch) {
16971694 .x86,
16981695 .sparc,
1699 .sparcel,
17001696 => init("/lib/ld-linux.so.2"),
17011697
17021698 .aarch64 => init("/lib/ld-linux-aarch64.so.1"),
......@@ -1854,7 +1850,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
18541850 .powerpc,
18551851 .powerpcle,
18561852 .riscv32,
1857 .sparcel,
18581853 .thumb,
18591854 .thumbeb,
18601855 .x86,
......@@ -1914,7 +1909,6 @@ pub fn stackAlignment(target: Target) u16 {
19141909 .mips,
19151910 .mipsel,
19161911 .sparc,
1917 .sparcel,
19181912 => 8,
19191913 .aarch64,
19201914 .aarch64_be,
......@@ -2075,7 +2069,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
20752069 .s390x,
20762070 .sparc,
20772071 .sparc64,
2078 .sparcel,
20792072 .wasm32,
20802073 .wasm64,
20812074 => return 128,
......@@ -2180,7 +2173,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
21802173 .mips64el,
21812174 .sparc,
21822175 .sparc64,
2183 .sparcel,
21842176 .wasm32,
21852177 .wasm64,
21862178 => return 128,
......@@ -2374,7 +2366,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
23742366 .mips,
23752367 .mipsel,
23762368 .sparc,
2377 .sparcel,
23782369 .sparc64,
23792370 .lanai,
23802371 .nvptx,
......@@ -2487,7 +2478,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
24872478 .mips,
24882479 .mipsel,
24892480 .sparc,
2490 .sparcel,
24912481 .sparc64,
24922482 .lanai,
24932483 .nvptx,
lib/std/atomic.zig-1
......@@ -486,7 +486,6 @@ pub const cache_line = switch (builtin.cpu.arch) {
486486 .riscv32,
487487 .riscv64,
488488 .sparc,
489 .sparcel,
490489 .sparc64,
491490 => 32,
492491
lib/std/builtin.zig+1-1
......@@ -615,7 +615,7 @@ pub const VaList = switch (builtin.cpu.arch) {
615615 else => VaListPowerPc,
616616 },
617617 .powerpc64, .powerpc64le => *u8,
618 .sparc, .sparcel, .sparc64 => *anyopaque,
618 .sparc, .sparc64 => *anyopaque,
619619 .spirv32, .spirv64 => *anyopaque,
620620 .s390x => VaListS390x,
621621 .wasm32, .wasm64 => *anyopaque,
lib/std/c.zig+3-3
......@@ -5779,7 +5779,7 @@ pub const ucontext_t = switch (native_os) {
57795779 .x86 => 4,
57805780 .mips, .mipsel, .mips64, .mips64el => 14,
57815781 .arm, .armeb, .thumb, .thumbeb => 1,
5782 .sparc, .sparcel, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,
5782 .sparc, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,
57835783 else => 0,
57845784 }
57855785 ]u32,
......@@ -6821,7 +6821,7 @@ pub const pthread_key_t = switch (native_os) {
68216821pub const padded_pthread_spin_t = switch (native_os) {
68226822 .netbsd => switch (builtin.cpu.arch) {
68236823 .x86, .x86_64 => u32,
6824 .sparc, .sparcel, .sparc64 => u32,
6824 .sparc, .sparc64 => u32,
68256825 else => pthread_spin_t,
68266826 },
68276827 else => void,
......@@ -6834,7 +6834,7 @@ pub const pthread_spin_t = switch (native_os) {
68346834 .powerpc, .powerpc64, .powerpc64le => i32,
68356835 .x86, .x86_64 => u8,
68366836 .arm, .armeb, .thumb, .thumbeb => i32,
6837 .sparc, .sparcel, .sparc64 => u8,
6837 .sparc, .sparc64 => u8,
68386838 .riscv32, .riscv64 => u32,
68396839 else => @compileError("undefined pthread_spin_t for this arch"),
68406840 },
lib/std/os/linux.zig+1-3
......@@ -2485,7 +2485,7 @@ pub const E = switch (native_arch) {
24852485
24862486 pub const init = errnoFromSyscall;
24872487 },
2488 .sparc, .sparcel, .sparc64 => enum(u16) {
2488 .sparc, .sparc64 => enum(u16) {
24892489 /// No error occurred.
24902490 SUCCESS = 0,
24912491
......@@ -4832,7 +4832,6 @@ pub const MINSIGSTKSZ = switch (native_arch) {
48324832 => 2048,
48334833 .loongarch64,
48344834 .sparc,
4835 .sparcel,
48364835 .sparc64,
48374836 => 4096,
48384837 .aarch64,
......@@ -4869,7 +4868,6 @@ pub const SIGSTKSZ = switch (native_arch) {
48694868 .aarch64_be,
48704869 .loongarch64,
48714870 .sparc,
4872 .sparcel,
48734871 .sparc64,
48744872 => 16384,
48754873 .powerpc64,
lib/std/os/linux/ioctl.zig-1
......@@ -11,7 +11,6 @@ const bits = switch (@import("builtin").cpu.arch) {
1111 .powerpc64le,
1212 .sparc,
1313 .sparc64,
14 .sparcel,
1514 => .{ .size = 13, .dir = 3, .none = 1, .read = 2, .write = 4 },
1615 else => .{ .size = 14, .dir = 2, .none = 0, .read = 2, .write = 1 },
1716};
src/Type.zig-1
......@@ -1602,7 +1602,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
16021602 .amdgcn,
16031603 .riscv32,
16041604 .sparc,
1605 .sparcel,
16061605 .s390x,
16071606 .lanai,
16081607 .wasm32,
src/Zcu.zig-1
......@@ -3248,7 +3248,6 @@ pub fn atomicPtrAlignment(
32483248 .powerpcle,
32493249 .riscv32,
32503250 .sparc,
3251 .sparcel,
32523251 .thumb,
32533252 .thumbeb,
32543253 .x86,
src/codegen/llvm.zig+1-4
......@@ -69,7 +69,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
6969 .riscv64 => "riscv64",
7070 .sparc => "sparc",
7171 .sparc64 => "sparc64",
72 .sparcel => "sparcel",
7372 .s390x => "s390x",
7473 .thumb => "thumb",
7574 .thumbeb => "thumbeb",
......@@ -280,7 +279,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
280279 .riscv64 => .riscv64,
281280 .sparc => .sparc,
282281 .sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9.
283 .sparcel => .sparcel,
284282 .s390x => .systemz,
285283 .thumb => .thumb,
286284 .thumbeb => .thumbeb,
......@@ -469,7 +467,6 @@ const DataLayoutBuilder = struct {
469467 .powerpcle,
470468 .riscv32,
471469 .sparc,
472 .sparcel,
473470 .thumb,
474471 .thumbeb,
475472 .xtensa,
......@@ -12004,7 +12001,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1200412001 llvm.LLVMInitializeRISCVAsmPrinter();
1200512002 llvm.LLVMInitializeRISCVAsmParser();
1200612003 },
12007 .sparc, .sparc64, .sparcel => {
12004 .sparc, .sparc64 => {
1200812005 llvm.LLVMInitializeSparcTarget();
1200912006 llvm.LLVMInitializeSparcTargetInfo();
1201012007 llvm.LLVMInitializeSparcTargetMC();
src/glibc.zig+2-2
......@@ -394,7 +394,7 @@ fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![
394394 const arch = comp.getTarget().cpu.arch;
395395 const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
396396 const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
397 const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;
397 const is_sparc = arch == .sparc or arch == .sparc64;
398398 const is_64 = comp.getTarget().ptrBitWidth() == 64;
399399
400400 const s = path.sep_str;
......@@ -532,7 +532,7 @@ fn add_include_dirs_arch(
532532 const is_x86 = arch == .x86 or arch == .x86_64;
533533 const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
534534 const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
535 const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;
535 const is_sparc = arch == .sparc or arch == .sparc64;
536536 const is_64 = target.ptrBitWidth() == 64;
537537
538538 const s = path.sep_str;
src/link/Elf.zig+1-1
......@@ -5175,7 +5175,7 @@ fn getLDMOption(target: std.Target) ?[]const u8 {
51755175 .powerpc => return "elf32ppclinux",
51765176 .powerpc64 => return "elf64ppc",
51775177 .powerpc64le => return "elf64lppc",
5178 .sparc, .sparcel => return "elf32_sparc",
5178 .sparc => return "elf32_sparc",
51795179 .sparc64 => return "elf64_sparc",
51805180 .mips => return "elf32btsmip",
51815181 .mipsel => return "elf32ltsmip",
src/link/Plan9/aout.zig+1-1
......@@ -110,7 +110,7 @@ pub const R_MAGIC = _MAGIC(HDR_MAGIC, 28); // arm64
110110pub fn magicFromArch(arch: std.Target.Cpu.Arch) !u32 {
111111 return switch (arch) {
112112 .x86 => I_MAGIC,
113 .sparc => K_MAGIC, // TODO should sparc64 and sparcel go here?
113 .sparc => K_MAGIC, // TODO should sparc64 go here?
114114 .mips => V_MAGIC,
115115 .arm => E_MAGIC,
116116 .aarch64 => R_MAGIC,
src/target.zig+1-3
......@@ -138,7 +138,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
138138 .riscv64,
139139 .sparc,
140140 .sparc64,
141 .sparcel,
142141 .s390x,
143142 .thumb,
144143 .thumbeb,
......@@ -408,7 +407,7 @@ pub fn defaultFunctionAlignment(target: std.Target) Alignment {
408407 return switch (target.cpu.arch) {
409408 .arm, .armeb => .@"4",
410409 .aarch64, .aarch64_be => .@"4",
411 .sparc, .sparcel, .sparc64 => .@"4",
410 .sparc, .sparc64 => .@"4",
412411 .riscv64 => .@"2",
413412 else => .@"1",
414413 };
......@@ -423,7 +422,6 @@ pub fn minFunctionAlignment(target: std.Target) Alignment {
423422 .riscv32,
424423 .riscv64,
425424 .sparc,
426 .sparcel,
427425 .sparc64,
428426 => .@"2",
429427 else => .@"1",
test/behavior/align.zig-1
......@@ -95,7 +95,6 @@ test "alignment and size of structs with 128-bit fields" {
9595 .amdgcn,
9696 .riscv32,
9797 .sparc,
98 .sparcel,
9998 .s390x,
10099 .lanai,
101100 .wasm32,
test/llvm_targets.zig-2
......@@ -87,8 +87,6 @@ const targets = [_]std.Target.Query{
8787 .{ .cpu_arch = .sparc, .os_tag = .freestanding, .abi = .none },
8888 .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .gnu },
8989 .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .none },
90 .{ .cpu_arch = .sparcel, .os_tag = .freestanding, .abi = .none },
91 .{ .cpu_arch = .sparcel, .os_tag = .linux, .abi = .gnu },
9290 .{ .cpu_arch = .sparc64, .os_tag = .freestanding, .abi = .none },
9391 .{ .cpu_arch = .sparc64, .os_tag = .linux, .abi = .gnu },
9492 //.{ .cpu_arch = .spirv32, .os_tag = .opencl, .abi = .none },