authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-05-22 21:12:28+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-05-22 21:12:51+02:00
logd70b56429c4f518c92f6419ce369d6098650ff96
tree550b6bddad1bae9d74dd6e702966c1117e0859b8
parentc717b0d08df5a0d1ca94d718fd4d28d3334eed57
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.zig.system.linux: add detection for more RISC-V CPU models

1 files changed, 4 insertions(+), 0 deletions(-)

lib/std/zig/system/linux.zig+4
...@@ -70,12 +70,16 @@ const RiscvCpuinfoImpl = struct {...@@ -70,12 +70,16 @@ const RiscvCpuinfoImpl = struct {
70 model: ?*const Target.Cpu.Model = null,70 model: ?*const Target.Cpu.Model = null,
7171
72 const cpu_names = .{72 const cpu_names = .{
73 .{ "andestech,ax45mp", &Target.riscv.cpu.andes_ax45 },
74 .{ "sifive,p550", &Target.riscv.cpu.sifive_p550 },
73 .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },75 .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
74 .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },76 .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
75 .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },77 .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
76 .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },78 .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
77 .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },79 .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
80 .{ "sifive,x280", &Target.riscv.cpu.sifive_x280 },
78 .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },81 .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
82 .{ "spacemit,x100", &Target.riscv.cpu.spacemit_x100 },
79 };83 };
8084
81 fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {85 fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {