authorgravatar for paul.verigo@gmail.comPavel Verigo <paul.verigo@gmail.com> 2026-04-19 17:30:35+02:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2026-04-19 21:49:51+02:00
logd840583458f03f5dcf75982e187e36796db8a9c8
treef64d8886b5b26bed461bc97df94121824b983863
parentdea6914aaa615c91c0e23ce3c4d4dfb2095de2b0

remove AIR .bool_or/.bool_and

14 files changed, 29 insertions(+), 85 deletions(-)

src/Air.zig-10
...@@ -538,12 +538,6 @@ pub const Inst = struct {...@@ -538,12 +538,6 @@ pub const Inst = struct {
538 /// Result type is always bool.538 /// Result type is always bool.
539 /// Uses the `un_op` field.539 /// Uses the `un_op` field.
540 is_non_err_ptr,540 is_non_err_ptr,
541 /// Result type is always bool.
542 /// Uses the `bin_op` field.
543 bool_and,
544 /// Result type is always bool.
545 /// Uses the `bin_op` field.
546 bool_or,
547 /// Read a value from a pointer.541 /// Read a value from a pointer.
548 /// Uses the `ty_op` field.542 /// Uses the `ty_op` field.
549 load,543 load,
...@@ -1580,8 +1574,6 @@ pub fn typeOfIndex(air: *const Air, inst: Air.Inst.Index, ip: *const InternPool)...@@ -1580,8 +1574,6 @@ pub fn typeOfIndex(air: *const Air, inst: Air.Inst.Index, ip: *const InternPool)
1580 .shl_sat,1574 .shl_sat,
1581 .min,1575 .min,
1582 .max,1576 .max,
1583 .bool_and,
1584 .bool_or,
1585 .add_optimized,1577 .add_optimized,
1586 .sub_optimized,1578 .sub_optimized,
1587 .mul_optimized,1579 .mul_optimized,
...@@ -2010,8 +2002,6 @@ pub fn mustLower(air: Air, inst: Air.Inst.Index, ip: *const InternPool) bool {...@@ -2010,8 +2002,6 @@ pub fn mustLower(air: Air, inst: Air.Inst.Index, ip: *const InternPool) bool {
2010 .is_non_null,2002 .is_non_null,
2011 .is_err,2003 .is_err,
2012 .is_non_err,2004 .is_non_err,
2013 .bool_and,
2014 .bool_or,
2015 .fptrunc,2005 .fptrunc,
2016 .fpext,2006 .fpext,
2017 .intcast,2007 .intcast,
src/Air/Legalize.zig+2-4
...@@ -713,8 +713,6 @@ fn legalizeBody(l: *Legalize, body_start: usize, body_len: usize) Error!void {...@@ -713,8 +713,6 @@ fn legalizeBody(l: *Legalize, body_start: usize, body_len: usize) Error!void {
713 .is_non_err,713 .is_non_err,
714 .is_err_ptr,714 .is_err_ptr,
715 .is_non_err_ptr,715 .is_non_err_ptr,
716 .bool_and,
717 .bool_or,
718 => {},716 => {},
719 .load => if (l.features.has(.expand_packed_load)) {717 .load => if (l.features.has(.expand_packed_load)) {
720 const ty_op = l.air_instructions.items(.data)[@intFromEnum(inst)].ty_op;718 const ty_op = l.air_instructions.items(.data)[@intFromEnum(inst)].ty_op;
...@@ -2018,7 +2016,7 @@ fn safeIntcastBlockPayload(l: *Legalize, orig_inst: Air.Inst.Index) Error!Air.In...@@ -2018,7 +2016,7 @@ fn safeIntcastBlockPayload(l: *Legalize, orig_inst: Air.Inst.Index) Error!Air.In
2018 } else undefined;2016 } else undefined;
2019 const out_of_range_inst: Air.Inst.Index = inst: {2017 const out_of_range_inst: Air.Inst.Index = inst: {
2020 if (have_min_check and have_max_check) break :inst cur_block.add(l, .{2018 if (have_min_check and have_max_check) break :inst cur_block.add(l, .{
2021 .tag = .bool_or,2019 .tag = .bit_or,
2022 .data = .{ .bin_op = .{2020 .data = .{ .bin_op = .{
2023 .lhs = below_min_inst.toRef(),2021 .lhs = below_min_inst.toRef(),
2024 .rhs = above_max_inst.toRef(),2022 .rhs = above_max_inst.toRef(),
...@@ -2156,7 +2154,7 @@ fn safeIntFromFloatBlockPayload(l: *Legalize, orig_inst: Air.Inst.Index, optimiz...@@ -2156,7 +2154,7 @@ fn safeIntFromFloatBlockPayload(l: *Legalize, orig_inst: Air.Inst.Index, optimiz
21562154
2157 // Combine the conditions.2155 // Combine the conditions.
2158 const out_of_bounds_inst: Air.Inst.Index = main_block.add(l, .{2156 const out_of_bounds_inst: Air.Inst.Index = main_block.add(l, .{
2159 .tag = .bool_or,2157 .tag = .bit_or,
2160 .data = .{ .bin_op = .{2158 .data = .{ .bin_op = .{
2161 .lhs = below_min_inst.toRef(),2159 .lhs = below_min_inst.toRef(),
2162 .rhs = above_max_inst.toRef(),2160 .rhs = above_max_inst.toRef(),
src/Air/Liveness.zig-2
...@@ -436,8 +436,6 @@ fn analyzeInst(...@@ -436,8 +436,6 @@ fn analyzeInst(
436 .cmp_gt_optimized,436 .cmp_gt_optimized,
437 .cmp_neq,437 .cmp_neq,
438 .cmp_neq_optimized,438 .cmp_neq_optimized,
439 .bool_and,
440 .bool_or,
441 .store,439 .store,
442 .store_safe,440 .store_safe,
443 .array_elem_val,441 .array_elem_val,
src/Air/Liveness/Verify.zig-2
...@@ -249,8 +249,6 @@ fn verifyBody(self: *Verify, body: []const Air.Inst.Index) Error!void {...@@ -249,8 +249,6 @@ fn verifyBody(self: *Verify, body: []const Air.Inst.Index) Error!void {
249 .cmp_gt_optimized,249 .cmp_gt_optimized,
250 .cmp_neq,250 .cmp_neq,
251 .cmp_neq_optimized,251 .cmp_neq_optimized,
252 .bool_and,
253 .bool_or,
254 .store,252 .store,
255 .store_safe,253 .store_safe,
256 .array_elem_val,254 .array_elem_val,
src/Air/print.zig-2
...@@ -148,8 +148,6 @@ const Writer = struct {...@@ -148,8 +148,6 @@ const Writer = struct {
148 .cmp_gte,148 .cmp_gte,
149 .cmp_gt,149 .cmp_gt,
150 .cmp_neq,150 .cmp_neq,
151 .bool_and,
152 .bool_or,
153 .store,151 .store,
154 .store_safe,152 .store_safe,
155 .array_elem_val,153 .array_elem_val,
src/Sema.zig+9-9
...@@ -4109,7 +4109,7 @@ fn zirForLen(sema: *Sema, block: *Block, inst: Zir.Inst.Index) CompileError!Air....@@ -4109,7 +4109,7 @@ fn zirForLen(sema: *Sema, block: *Block, inst: Zir.Inst.Index) CompileError!Air.
4109 if (i == len_idx) continue;4109 if (i == len_idx) continue;
4110 const eq = try block.addBinOp(.cmp_eq, len, arg_len);4110 const eq = try block.addBinOp(.cmp_eq, len, arg_len);
4111 ok = if (ok != .none)4111 ok = if (ok != .none)
4112 try block.addBinOp(.bool_and, ok, eq)4112 try block.addBinOp(.bit_and, ok, eq)
4113 else4113 else
4114 eq;4114 eq;
4115 }4115 }
...@@ -7699,7 +7699,7 @@ fn zirErrorFromInt(sema: *Sema, block: *Block, extended: Zir.Inst.Extended.InstD...@@ -7699,7 +7699,7 @@ fn zirErrorFromInt(sema: *Sema, block: *Block, extended: Zir.Inst.Extended.InstD
7699 const is_lte_len = try block.addUnOp(.cmp_lte_errors_len, operand);7699 const is_lte_len = try block.addUnOp(.cmp_lte_errors_len, operand);
7700 const zero_val = Air.internedToRef((try pt.intValue(err_int_ty, 0)).toIntern());7700 const zero_val = Air.internedToRef((try pt.intValue(err_int_ty, 0)).toIntern());
7701 const is_non_zero = try block.addBinOp(.cmp_neq, operand, zero_val);7701 const is_non_zero = try block.addBinOp(.cmp_neq, operand, zero_val);
7702 const ok = try block.addBinOp(.bool_and, is_lte_len, is_non_zero);7702 const ok = try block.addBinOp(.bit_and, is_lte_len, is_non_zero);
7703 try sema.addSafetyCheck(block, src, ok, .invalid_error_code);7703 try sema.addSafetyCheck(block, src, ok, .invalid_error_code);
7704 }7704 }
7705 return block.addInst(.{7705 return block.addInst(.{
...@@ -14561,7 +14561,7 @@ fn addDivIntOverflowSafety(...@@ -14561,7 +14561,7 @@ fn addDivIntOverflowSafety(
14561 break :ok try block.addCmpVector(casted_rhs, neg_one_ref, .neq);14561 break :ok try block.addCmpVector(casted_rhs, neg_one_ref, .neq);
14562 };14562 };
1456314563
14564 const ok = try block.addReduce(try block.addBinOp(.bool_or, lhs_ok, rhs_ok), .And);14564 const ok = try block.addReduce(try block.addBinOp(.bit_or, lhs_ok, rhs_ok), .And);
14565 try sema.addSafetyCheck(block, src, ok, .integer_overflow);14565 try sema.addSafetyCheck(block, src, ok, .integer_overflow);
14566 } else {14566 } else {
14567 const lhs_ok: Air.Inst.Ref = if (maybe_lhs_val == null) ok: {14567 const lhs_ok: Air.Inst.Ref = if (maybe_lhs_val == null) ok: {
...@@ -14574,7 +14574,7 @@ fn addDivIntOverflowSafety(...@@ -14574,7 +14574,7 @@ fn addDivIntOverflowSafety(
14574 } else .none; // means false14574 } else .none; // means false
1457514575
14576 const ok = if (lhs_ok != .none and rhs_ok != .none)14576 const ok = if (lhs_ok != .none and rhs_ok != .none)
14577 try block.addBinOp(.bool_or, lhs_ok, rhs_ok)14577 try block.addBinOp(.bit_or, lhs_ok, rhs_ok)
14578 else if (lhs_ok != .none)14578 else if (lhs_ok != .none)
14579 lhs_ok14579 lhs_ok
14580 else if (rhs_ok != .none)14580 else if (rhs_ok != .none)
...@@ -21236,7 +21236,7 @@ fn zirErrorCast(sema: *Sema, block: *Block, extended: Zir.Inst.Extended.InstData...@@ -21236,7 +21236,7 @@ fn zirErrorCast(sema: *Sema, block: *Block, extended: Zir.Inst.Extended.InstData
21236 } else {21236 } else {
21237 // Error must be in destination set or zero.21237 // Error must be in destination set or zero.
21238 const has_value = try block.addTyOp(.error_set_has_value, dest_err_ty, err_int_inst);21238 const has_value = try block.addTyOp(.error_set_has_value, dest_err_ty, err_int_inst);
21239 const ok = try block.addBinOp(.bool_or, has_value, is_zero);21239 const ok = try block.addBinOp(.bit_or, has_value, is_zero);
21240 try sema.addSafetyCheck(block, src, ok, .invalid_error_code);21240 try sema.addSafetyCheck(block, src, ok, .invalid_error_code);
21241 }21241 }
21242 } else {21242 } else {
...@@ -21794,7 +21794,7 @@ fn ptrCastFull(...@@ -21794,7 +21794,7 @@ fn ptrCastFull(
21794 assert(operand_ptr_int != .none);21794 assert(operand_ptr_int != .none);
21795 const ptr_is_non_zero = try block.addBinOp(.cmp_neq, operand_ptr_int, .zero_usize);21795 const ptr_is_non_zero = try block.addBinOp(.cmp_neq, operand_ptr_int, .zero_usize);
21796 const ok = if (src_info.flags.size == .slice and dest_info.flags.size == .slice) ok: {21796 const ok = if (src_info.flags.size == .slice and dest_info.flags.size == .slice) ok: {
21797 break :ok try block.addBinOp(.bool_or, operand_len_is_zero, ptr_is_non_zero);21797 break :ok try block.addBinOp(.bit_or, operand_len_is_zero, ptr_is_non_zero);
21798 } else ptr_is_non_zero;21798 } else ptr_is_non_zero;
21799 try sema.addSafetyCheck(block, src, ok, .cast_to_null);21799 try sema.addSafetyCheck(block, src, ok, .cast_to_null);
21800 }21800 }
...@@ -21807,7 +21807,7 @@ fn ptrCastFull(...@@ -21807,7 +21807,7 @@ fn ptrCastFull(
21807 const ptr_masked = try block.addBinOp(.bit_and, operand_ptr_int, align_mask);21807 const ptr_masked = try block.addBinOp(.bit_and, operand_ptr_int, align_mask);
21808 const is_aligned = try block.addBinOp(.cmp_eq, ptr_masked, .zero_usize);21808 const is_aligned = try block.addBinOp(.cmp_eq, ptr_masked, .zero_usize);
21809 const ok = if (src_info.flags.size == .slice and dest_info.flags.size == .slice) ok: {21809 const ok = if (src_info.flags.size == .slice and dest_info.flags.size == .slice) ok: {
21810 break :ok try block.addBinOp(.bool_or, operand_len_is_zero, is_aligned);21810 break :ok try block.addBinOp(.bit_or, operand_len_is_zero, is_aligned);
21811 } else is_aligned;21811 } else is_aligned;
21812 try sema.addSafetyCheck(block, src, ok, .incorrect_alignment);21812 try sema.addSafetyCheck(block, src, ok, .incorrect_alignment);
21813 }21813 }
...@@ -24317,7 +24317,7 @@ fn zirMemcpy(...@@ -24317,7 +24317,7 @@ fn zirMemcpy(
24317 const dest_plus_len = try sema.analyzePtrArithmetic(block, src, raw_dest_ptr, len, .ptr_add, src);24317 const dest_plus_len = try sema.analyzePtrArithmetic(block, src, raw_dest_ptr, len, .ptr_add, src);
24318 const ok1 = try block.addBinOp(.cmp_gte, raw_dest_ptr, src_plus_len);24318 const ok1 = try block.addBinOp(.cmp_gte, raw_dest_ptr, src_plus_len);
24319 const ok2 = try block.addBinOp(.cmp_gte, new_src_ptr, dest_plus_len);24319 const ok2 = try block.addBinOp(.cmp_gte, new_src_ptr, dest_plus_len);
24320 const ok = try block.addBinOp(.bool_or, ok1, ok2);24320 const ok = try block.addBinOp(.bit_or, ok1, ok2);
24321 try sema.addSafetyCheck(block, src, ok, .memcpy_alias);24321 try sema.addSafetyCheck(block, src, ok, .memcpy_alias);
24322 }24322 }
2432324323
...@@ -29524,7 +29524,7 @@ fn coerceCompatiblePtrs(...@@ -29524,7 +29524,7 @@ fn coerceCompatiblePtrs(
29524 const ok = if (inst_ty.isSlice(zcu)) ok: {29524 const ok = if (inst_ty.isSlice(zcu)) ok: {
29525 const len = try sema.analyzeSliceLen(block, inst_src, inst);29525 const len = try sema.analyzeSliceLen(block, inst_src, inst);
29526 const len_zero = try block.addBinOp(.cmp_eq, len, .zero_usize);29526 const len_zero = try block.addBinOp(.cmp_eq, len, .zero_usize);
29527 break :ok try block.addBinOp(.bool_or, len_zero, is_non_zero);29527 break :ok try block.addBinOp(.bit_or, len_zero, is_non_zero);
29528 } else is_non_zero;29528 } else is_non_zero;
29529 try sema.addSafetyCheck(block, inst_src, ok, .cast_to_null);29529 try sema.addSafetyCheck(block, inst_src, ok, .cast_to_null);
29530 }29530 }
src/codegen/aarch64/Select.zig+3-5
...@@ -203,8 +203,6 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {...@@ -203,8 +203,6 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {
203 .cmp_gt_optimized,203 .cmp_gt_optimized,
204 .cmp_neq,204 .cmp_neq,
205 .cmp_neq_optimized,205 .cmp_neq_optimized,
206 .bool_and,
207 .bool_or,
208 .array_elem_val,206 .array_elem_val,
209 .slice_elem_val,207 .slice_elem_val,
210 .ptr_elem_val,208 .ptr_elem_val,
...@@ -2883,7 +2881,7 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,...@@ -2883,7 +2881,7 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
28832881
2884 if (air.next()) |next_air_tag| continue :air_tag next_air_tag;2882 if (air.next()) |next_air_tag| continue :air_tag next_air_tag;
2885 },2883 },
2886 .bit_and, .bit_or, .xor, .bool_and, .bool_or => |air_tag| {2884 .bit_and, .bit_or, .xor => |air_tag| {
2887 if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| {2885 if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| {
2888 defer res_vi.value.deref(isel);2886 defer res_vi.value.deref(isel);
28892887
...@@ -2914,12 +2912,12 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,...@@ -2914,12 +2912,12 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
2914 const rhs_part_mat = try rhs_part_vi.?.matReg(isel);2912 const rhs_part_mat = try rhs_part_vi.?.matReg(isel);
2915 try isel.emit(switch (air_tag) {2913 try isel.emit(switch (air_tag) {
2916 else => unreachable,2914 else => unreachable,
2917 .bit_and, .bool_and => switch (size) {2915 .bit_and => switch (size) {
2918 else => unreachable,2916 else => unreachable,
2919 1, 2, 4 => .@"and"(res_part_ra.w(), lhs_part_mat.ra.w(), .{ .register = rhs_part_mat.ra.w() }),2917 1, 2, 4 => .@"and"(res_part_ra.w(), lhs_part_mat.ra.w(), .{ .register = rhs_part_mat.ra.w() }),
2920 8 => .@"and"(res_part_ra.x(), lhs_part_mat.ra.x(), .{ .register = rhs_part_mat.ra.x() }),2918 8 => .@"and"(res_part_ra.x(), lhs_part_mat.ra.x(), .{ .register = rhs_part_mat.ra.x() }),
2921 },2919 },
2922 .bit_or, .bool_or => switch (size) {2920 .bit_or => switch (size) {
2923 else => unreachable,2921 else => unreachable,
2924 1, 2, 4 => .orr(res_part_ra.w(), lhs_part_mat.ra.w(), .{ .register = rhs_part_mat.ra.w() }),2922 1, 2, 4 => .orr(res_part_ra.w(), lhs_part_mat.ra.w(), .{ .register = rhs_part_mat.ra.w() }),
2925 8 => .orr(res_part_ra.x(), lhs_part_mat.ra.x(), .{ .register = rhs_part_mat.ra.x() }),2923 8 => .orr(res_part_ra.x(), lhs_part_mat.ra.x(), .{ .register = rhs_part_mat.ra.x() }),
src/codegen/c.zig+2-3
...@@ -2728,9 +2728,8 @@ fn genBodyInner(f: *Function, body: []const Air.Inst.Index) Error!void {...@@ -2728,9 +2728,8 @@ fn genBodyInner(f: *Function, body: []const Air.Inst.Index) Error!void {
2728 },2728 },
2729 .cmp_lte_errors_len => try airCmpLteErrorsLen(f, inst),2729 .cmp_lte_errors_len => try airCmpLteErrorsLen(f, inst),
27302730
2731 // bool_and and bool_or are non-short-circuit operations2731 .bit_and => try airBinOp(f, inst, "&", "and", .none),
2732 .bool_and, .bit_and => try airBinOp(f, inst, "&", "and", .none),2732 .bit_or => try airBinOp(f, inst, "|", "or", .none),
2733 .bool_or, .bit_or => try airBinOp(f, inst, "|", "or", .none),
2734 .xor => try airBinOp(f, inst, "^", "xor", .none),2733 .xor => try airBinOp(f, inst, "^", "xor", .none),
2735 .shr, .shr_exact => try airBinBuiltinCall(f, inst, "shr", .none),2734 .shr, .shr_exact => try airBinBuiltinCall(f, inst, "shr", .none),
2736 .shl, => try airBinBuiltinCall(f, inst, "shlw", .bits),2735 .shl, => try airBinBuiltinCall(f, inst, "shlw", .bits),
src/codegen/llvm/FuncGen.zig+5-5
...@@ -258,11 +258,11 @@ pub fn genBody(self: *FuncGen, body: []const Air.Inst.Index, coverage_point: Air...@@ -258,11 +258,11 @@ pub fn genBody(self: *FuncGen, body: []const Air.Inst.Index, coverage_point: Air
258 .mul_with_overflow => try self.airOverflow(inst, .@"smul.with.overflow", .@"umul.with.overflow"),258 .mul_with_overflow => try self.airOverflow(inst, .@"smul.with.overflow", .@"umul.with.overflow"),
259 .shl_with_overflow => try self.airShlWithOverflow(inst),259 .shl_with_overflow => try self.airShlWithOverflow(inst),
260260
261 .bit_and, .bool_and => try self.airAnd(inst),261 .bit_and => try self.airAnd(inst),
262 .bit_or, .bool_or => try self.airOr(inst),262 .bit_or => try self.airOr(inst),
263 .xor => try self.airXor(inst),263 .xor => try self.airXor(inst),
264 .shr => try self.airShr(inst, false),264 .shr => try self.airShr(inst, false),
265 .shr_exact => try self.airShr(inst, true),265 .shr_exact => try self.airShr(inst, true),
266266
267 .sqrt => try self.airUnaryOp(inst, .sqrt),267 .sqrt => try self.airUnaryOp(inst, .sqrt),
268 .sin => try self.airUnaryOp(inst, .sin),268 .sin => try self.airUnaryOp(inst, .sin),
src/codegen/riscv64/CodeGen.zig+2-13
...@@ -1415,8 +1415,6 @@ fn genBody(func: *Func, body: []const Air.Inst.Index) InnerError!void {...@@ -1415,8 +1415,6 @@ fn genBody(func: *Func, body: []const Air.Inst.Index) InnerError!void {
1415 .shl, .shl_exact,1415 .shl, .shl_exact,
1416 .shr, .shr_exact,1416 .shr, .shr_exact,
14171417
1418 .bool_and,
1419 .bool_or,
1420 .bit_and,1418 .bit_and,
1421 .bit_or,1419 .bit_or,
14221420
...@@ -2702,13 +2700,11 @@ fn genBinOp(...@@ -2702,13 +2700,11 @@ fn genBinOp(
27022700
2703 .bit_and,2701 .bit_and,
2704 .bit_or,2702 .bit_or,
2705 .bool_and,
2706 .bool_or,
2707 => {2703 => {
2708 _ = try func.addInst(.{2704 _ = try func.addInst(.{
2709 .tag = switch (tag) {2705 .tag = switch (tag) {
2710 .bit_and, .bool_and => .@"and",2706 .bit_and => .@"and",
2711 .bit_or, .bool_or => .@"or",2707 .bit_or => .@"or",
2712 else => unreachable,2708 else => unreachable,
2713 },2709 },
2714 .data = .{2710 .data = .{
...@@ -2719,13 +2715,6 @@ fn genBinOp(...@@ -2719,13 +2715,6 @@ fn genBinOp(
2719 },2715 },
2720 },2716 },
2721 });2717 });
2722
2723 switch (tag) {
2724 .bool_and,
2725 .bool_or,
2726 => try func.truncateRegister(Type.bool, dst_reg),
2727 else => {},
2728 }
2729 },2718 },
27302719
2731 .shr,2720 .shr,
src/codegen/sparc64/CodeGen.zig-22
...@@ -499,8 +499,6 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {...@@ -499,8 +499,6 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
499 .shl_exact => try self.airBinOp(inst, .shl_exact),499 .shl_exact => try self.airBinOp(inst, .shl_exact),
500 .shr => try self.airBinOp(inst, .shr),500 .shr => try self.airBinOp(inst, .shr),
501 .shr_exact => try self.airBinOp(inst, .shr_exact),501 .shr_exact => try self.airBinOp(inst, .shr_exact),
502 .bool_and => try self.airBinOp(inst, .bool_and),
503 .bool_or => try self.airBinOp(inst, .bool_or),
504 .bit_and => try self.airBinOp(inst, .bit_and),502 .bit_and => try self.airBinOp(inst, .bit_and),
505 .bit_or => try self.airBinOp(inst, .bit_or),503 .bit_or => try self.airBinOp(inst, .bit_or),
506 .xor => try self.airBinOp(inst, .xor),504 .xor => try self.airBinOp(inst, .xor),
...@@ -2941,26 +2939,6 @@ fn binOp(...@@ -2941,26 +2939,6 @@ fn binOp(
2941 }2939 }
2942 },2940 },
29432941
2944 .bool_and,
2945 .bool_or,
2946 => {
2947 switch (lhs_ty.zigTypeTag(zcu)) {
2948 .bool => {
2949 assert(lhs != .immediate); // should have been handled by Sema
2950 assert(rhs != .immediate); // should have been handled by Sema
2951
2952 const mir_tag: Mir.Inst.Tag = switch (tag) {
2953 .bool_and => .@"and",
2954 .bool_or => .@"or",
2955 else => unreachable,
2956 };
2957
2958 return try self.binOpRegister(mir_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
2959 },
2960 else => unreachable,
2961 }
2962 },
2963
2964 .shl,2942 .shl,
2965 .shr,2943 .shr,
2966 => {2944 => {
src/codegen/spirv/CodeGen.zig-2
...@@ -2693,8 +2693,6 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) Error!void {...@@ -2693,8 +2693,6 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) Error!void {
2693 .bit_and => try cg.airBinOpSimple(inst, .OpBitwiseAnd),2693 .bit_and => try cg.airBinOpSimple(inst, .OpBitwiseAnd),
2694 .bit_or => try cg.airBinOpSimple(inst, .OpBitwiseOr),2694 .bit_or => try cg.airBinOpSimple(inst, .OpBitwiseOr),
2695 .xor => try cg.airBinOpSimple(inst, .OpBitwiseXor),2695 .xor => try cg.airBinOpSimple(inst, .OpBitwiseXor),
2696 .bool_and => try cg.airBinOpSimple(inst, .OpLogicalAnd),
2697 .bool_or => try cg.airBinOpSimple(inst, .OpLogicalOr),
26982696
2699 .shl, .shl_exact => try cg.airShift(inst, .OpShiftLeftLogical, .OpShiftLeftLogical),2697 .shl, .shl_exact => try cg.airShift(inst, .OpShiftLeftLogical, .OpShiftLeftLogical),
2700 .shr, .shr_exact => try cg.airShift(inst, .OpShiftRightLogical, .OpShiftRightArithmetic),2698 .shr, .shr_exact => try cg.airShift(inst, .OpShiftRightLogical, .OpShiftRightArithmetic),
src/codegen/wasm/CodeGen.zig+3-3
...@@ -1516,7 +1516,7 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) InnerError!void {...@@ -1516,7 +1516,7 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) InnerError!void {
1516 try cg.finishAir(inst, result, &.{ bin_op.lhs, bin_op.rhs });1516 try cg.finishAir(inst, result, &.{ bin_op.lhs, bin_op.rhs });
1517 },1517 },
15181518
1519 .bit_and, .bit_or, .bool_and, .bool_or, .xor, .shl_exact, .shr, .shr_exact => |tag| {1519 .bit_and, .bit_or, .xor, .shl_exact, .shr, .shr_exact => |tag| {
1520 const bin_op = cg.air.instructions.items(.data)[@intFromEnum(inst)].bin_op;1520 const bin_op = cg.air.instructions.items(.data)[@intFromEnum(inst)].bin_op;
1521 const lhs = try cg.resolveInst(bin_op.lhs);1521 const lhs = try cg.resolveInst(bin_op.lhs);
1522 const rhs = try cg.resolveInst(bin_op.rhs);1522 const rhs = try cg.resolveInst(bin_op.rhs);
...@@ -1528,8 +1528,8 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) InnerError!void {...@@ -1528,8 +1528,8 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) InnerError!void {
15281528
1529 const int_ty: IntType = .fromType(cg, ty);1529 const int_ty: IntType = .fromType(cg, ty);
1530 const result = switch (tag) {1530 const result = switch (tag) {
1531 .bit_and, .bool_and => try cg.intAnd(int_ty, lhs, rhs),1531 .bit_and => try cg.intAnd(int_ty, lhs, rhs),
1532 .bit_or, .bool_or => try cg.intOr(int_ty, lhs, rhs),1532 .bit_or => try cg.intOr(int_ty, lhs, rhs),
1533 .xor => try cg.intXor(int_ty, lhs, rhs),1533 .xor => try cg.intXor(int_ty, lhs, rhs),
1534 .shl_exact => try cg.intShl(int_ty, lhs, rhs),1534 .shl_exact => try cg.intShl(int_ty, lhs, rhs),
1535 .shr, .shr_exact => try cg.intShr(int_ty, lhs, rhs),1535 .shr, .shr_exact => try cg.intShr(int_ty, lhs, rhs),
src/codegen/x86_64/CodeGen.zig+3-3
...@@ -60839,14 +60839,14 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {...@@ -60839,14 +60839,14 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {
60839 try slot.finish(inst, &.{}, &.{}, cg);60839 try slot.finish(inst, &.{}, &.{}, cg);
60840 },60840 },
60841 .assembly => try cg.airAsm(inst),60841 .assembly => try cg.airAsm(inst),
60842 .bit_and, .bit_or, .xor, .bool_and, .bool_or => |air_tag| {60842 .bit_and, .bit_or, .xor => |air_tag| {
60843 const bin_op = air_datas[@intFromEnum(inst)].bin_op;60843 const bin_op = air_datas[@intFromEnum(inst)].bin_op;
60844 var ops = try cg.tempsFromOperands(inst, .{ bin_op.lhs, bin_op.rhs });60844 var ops = try cg.tempsFromOperands(inst, .{ bin_op.lhs, bin_op.rhs });
60845 var res: [1]Temp = undefined;60845 var res: [1]Temp = undefined;
60846 cg.select(&res, &.{cg.typeOf(bin_op.lhs)}, &ops, switch (@as(Mir.Inst.Tag, switch (air_tag) {60846 cg.select(&res, &.{cg.typeOf(bin_op.lhs)}, &ops, switch (@as(Mir.Inst.Tag, switch (air_tag) {
60847 else => unreachable,60847 else => unreachable,
60848 .bit_and, .bool_and => .@"and",60848 .bit_and => .@"and",
60849 .bit_or, .bool_or => .@"or",60849 .bit_or => .@"or",
60850 .xor => .xor,60850 .xor => .xor,
60851 })) {60851 })) {
60852 else => unreachable,60852 else => unreachable,