authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-05 12:33:52+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-05 12:34:21+02:00
logd9909ecefcc2f806a58ffb756ee2a91a58f4afd9
treef59b2ed3a4c709e6ffc49ba4b740eb411e862ded
parent7b905d6a2b8f6fadc55e6c58a3d558a3d5899326
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.zig.system: tiny refactor of aarch64 namespacing

2 files changed, 38 insertions(+), 34 deletions(-)

lib/std/zig/system/freebsd.zig+19-17
...@@ -3,28 +3,30 @@ const std = @import("std");...@@ -3,28 +3,30 @@ const std = @import("std");
33
4const native_arch = builtin.target.cpu.arch;4const native_arch = builtin.target.cpu.arch;
55
6inline fn getAArch64CpuFeature(comptime feat_reg: []const u8) u64 {6const aarch64 = struct {
7 return asm ("mrs %[ret], " ++ feat_reg7 inline fn mrs(comptime feat_reg: []const u8) u64 {
8 : [ret] "=r" (-> u64),8 return asm ("mrs %[ret], " ++ feat_reg
9 );9 : [ret] "=r" (-> u64),
10}10 );
11 }
12};
1113
12pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu {14pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu {
13 return switch (native_arch) {15 return switch (native_arch) {
14 .aarch64, .aarch64_be => b: {16 .aarch64, .aarch64_be => b: {
15 const registers = [12]u64{17 const registers = [12]u64{
16 getAArch64CpuFeature("MIDR_EL1"),18 aarch64.mrs("MIDR_EL1"),
17 getAArch64CpuFeature("ID_AA64PFR0_EL1"),19 aarch64.mrs("ID_AA64PFR0_EL1"),
18 getAArch64CpuFeature("ID_AA64PFR1_EL1"),20 aarch64.mrs("ID_AA64PFR1_EL1"),
19 getAArch64CpuFeature("ID_AA64DFR0_EL1"),21 aarch64.mrs("ID_AA64DFR0_EL1"),
20 getAArch64CpuFeature("ID_AA64DFR1_EL1"),22 aarch64.mrs("ID_AA64DFR1_EL1"),
21 getAArch64CpuFeature("ID_AA64AFR0_EL1"),23 aarch64.mrs("ID_AA64AFR0_EL1"),
22 getAArch64CpuFeature("ID_AA64AFR1_EL1"),24 aarch64.mrs("ID_AA64AFR1_EL1"),
23 getAArch64CpuFeature("ID_AA64ISAR0_EL1"),25 aarch64.mrs("ID_AA64ISAR0_EL1"),
24 getAArch64CpuFeature("ID_AA64ISAR1_EL1"),26 aarch64.mrs("ID_AA64ISAR1_EL1"),
25 getAArch64CpuFeature("ID_AA64MMFR0_EL1"),27 aarch64.mrs("ID_AA64MMFR0_EL1"),
26 getAArch64CpuFeature("ID_AA64MMFR1_EL1"),28 aarch64.mrs("ID_AA64MMFR1_EL1"),
27 getAArch64CpuFeature("ID_AA64MMFR2_EL1"),29 aarch64.mrs("ID_AA64MMFR2_EL1"),
28 };30 };
2931
30 break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(native_arch, registers);32 break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(native_arch, registers);
lib/std/zig/system/linux.zig+19-17
...@@ -441,11 +441,13 @@ fn CpuinfoParser(comptime impl: anytype) type {...@@ -441,11 +441,13 @@ fn CpuinfoParser(comptime impl: anytype) type {
441 };441 };
442}442}
443443
444inline fn getAArch64CpuFeature(comptime feat_reg: []const u8) u64 {444const aarch64 = struct {
445 return asm ("mrs %[ret], " ++ feat_reg445 inline fn mrs(comptime feat_reg: []const u8) u64 {
446 : [ret] "=r" (-> u64),446 return asm ("mrs %[ret], " ++ feat_reg
447 );447 : [ret] "=r" (-> u64),
448}448 );
449 }
450};
449451
450const riscv = struct {452const riscv = struct {
451 const linux = std.os.linux;453 const linux = std.os.linux;
...@@ -596,18 +598,18 @@ pub fn detectNativeCpuAndFeatures(io: Io) ?Target.Cpu {...@@ -596,18 +598,18 @@ pub fn detectNativeCpuAndFeatures(io: Io) ?Target.Cpu {
596 return switch (current_arch) {598 return switch (current_arch) {
597 .aarch64, .aarch64_be => b: {599 .aarch64, .aarch64_be => b: {
598 const registers = [12]u64{600 const registers = [12]u64{
599 getAArch64CpuFeature("MIDR_EL1"),601 aarch64.mrs("MIDR_EL1"),
600 getAArch64CpuFeature("ID_AA64PFR0_EL1"),602 aarch64.mrs("ID_AA64PFR0_EL1"),
601 getAArch64CpuFeature("ID_AA64PFR1_EL1"),603 aarch64.mrs("ID_AA64PFR1_EL1"),
602 getAArch64CpuFeature("ID_AA64DFR0_EL1"),604 aarch64.mrs("ID_AA64DFR0_EL1"),
603 getAArch64CpuFeature("ID_AA64DFR1_EL1"),605 aarch64.mrs("ID_AA64DFR1_EL1"),
604 getAArch64CpuFeature("ID_AA64AFR0_EL1"),606 aarch64.mrs("ID_AA64AFR0_EL1"),
605 getAArch64CpuFeature("ID_AA64AFR1_EL1"),607 aarch64.mrs("ID_AA64AFR1_EL1"),
606 getAArch64CpuFeature("ID_AA64ISAR0_EL1"),608 aarch64.mrs("ID_AA64ISAR0_EL1"),
607 getAArch64CpuFeature("ID_AA64ISAR1_EL1"),609 aarch64.mrs("ID_AA64ISAR1_EL1"),
608 getAArch64CpuFeature("ID_AA64MMFR0_EL1"),610 aarch64.mrs("ID_AA64MMFR0_EL1"),
609 getAArch64CpuFeature("ID_AA64MMFR1_EL1"),611 aarch64.mrs("ID_AA64MMFR1_EL1"),
610 getAArch64CpuFeature("ID_AA64MMFR2_EL1"),612 aarch64.mrs("ID_AA64MMFR2_EL1"),
611 };613 };
612614
613 break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(current_arch, registers);615 break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(current_arch, registers);