| author |  Alex Rønne Petersen <alex@alexrp.com> 2026-09-05 12:33:52+02:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2026-09-05 12:34:21+02:00 |
| log | d9909ecefcc2f806a58ffb756ee2a91a58f4afd9 |
| tree | f59b2ed3a4c709e6ffc49ba4b740eb411e862ded |
| parent | 7b905d6a2b8f6fadc55e6c58a3d558a3d5899326 |
| signature |  Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
std.zig.system: tiny refactor of aarch64 namespacing
2 files changed, 38 insertions(+), 34 deletions(-)
lib- std
- zig
- system
lib/std/zig/system/freebsd.zig+19-17
| ... | ... | @@ -3,28 +3,30 @@ const std = @import("std"); |
| 3 | 3 | |
| 4 | 4 | const native_arch = builtin.target.cpu.arch; |
| 5 | 5 | |
| 6 | inline fn getAArch64CpuFeature(comptime feat_reg: []const u8) u64 { | |
| 7 | return asm ("mrs %[ret], " ++ feat_reg | |
| 8 | : [ret] "=r" (-> u64), | |
| 9 | ); | |
| 10 | } | |
| 6 | const aarch64 = struct { | |
| 7 | inline fn mrs(comptime feat_reg: []const u8) u64 { | |
| 8 | return asm ("mrs %[ret], " ++ feat_reg | |
| 9 | : [ret] "=r" (-> u64), | |
| 10 | ); | |
| 11 | } | |
| 12 | }; | |
| 11 | 13 | |
| 12 | 14 | pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu { |
| 13 | 15 | return switch (native_arch) { |
| 14 | 16 | .aarch64, .aarch64_be => b: { |
| 15 | 17 | const registers = [12]u64{ |
| 16 | getAArch64CpuFeature("MIDR_EL1"), | |
| 17 | getAArch64CpuFeature("ID_AA64PFR0_EL1"), | |
| 18 | getAArch64CpuFeature("ID_AA64PFR1_EL1"), | |
| 19 | getAArch64CpuFeature("ID_AA64DFR0_EL1"), | |
| 20 | getAArch64CpuFeature("ID_AA64DFR1_EL1"), | |
| 21 | getAArch64CpuFeature("ID_AA64AFR0_EL1"), | |
| 22 | getAArch64CpuFeature("ID_AA64AFR1_EL1"), | |
| 23 | getAArch64CpuFeature("ID_AA64ISAR0_EL1"), | |
| 24 | getAArch64CpuFeature("ID_AA64ISAR1_EL1"), | |
| 25 | getAArch64CpuFeature("ID_AA64MMFR0_EL1"), | |
| 26 | getAArch64CpuFeature("ID_AA64MMFR1_EL1"), | |
| 27 | getAArch64CpuFeature("ID_AA64MMFR2_EL1"), | |
| 18 | aarch64.mrs("MIDR_EL1"), | |
| 19 | aarch64.mrs("ID_AA64PFR0_EL1"), | |
| 20 | aarch64.mrs("ID_AA64PFR1_EL1"), | |
| 21 | aarch64.mrs("ID_AA64DFR0_EL1"), | |
| 22 | aarch64.mrs("ID_AA64DFR1_EL1"), | |
| 23 | aarch64.mrs("ID_AA64AFR0_EL1"), | |
| 24 | aarch64.mrs("ID_AA64AFR1_EL1"), | |
| 25 | aarch64.mrs("ID_AA64ISAR0_EL1"), | |
| 26 | aarch64.mrs("ID_AA64ISAR1_EL1"), | |
| 27 | aarch64.mrs("ID_AA64MMFR0_EL1"), | |
| 28 | aarch64.mrs("ID_AA64MMFR1_EL1"), | |
| 29 | aarch64.mrs("ID_AA64MMFR2_EL1"), | |
| 28 | 30 | }; |
| 29 | 31 | |
| 30 | 32 | break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(native_arch, registers); |
lib/std/zig/system/linux.zig+19-17
| ... | ... | @@ -441,11 +441,13 @@ fn CpuinfoParser(comptime impl: anytype) type { |
| 441 | 441 | }; |
| 442 | 442 | } |
| 443 | 443 | |
| 444 | inline fn getAArch64CpuFeature(comptime feat_reg: []const u8) u64 { | |
| 445 | return asm ("mrs %[ret], " ++ feat_reg | |
| 446 | : [ret] "=r" (-> u64), | |
| 447 | ); | |
| 448 | } | |
| 444 | const aarch64 = struct { | |
| 445 | inline fn mrs(comptime feat_reg: []const u8) u64 { | |
| 446 | return asm ("mrs %[ret], " ++ feat_reg | |
| 447 | : [ret] "=r" (-> u64), | |
| 448 | ); | |
| 449 | } | |
| 450 | }; | |
| 449 | 451 | |
| 450 | 452 | const riscv = struct { |
| 451 | 453 | const linux = std.os.linux; |
| ... | ... | @@ -596,18 +598,18 @@ pub fn detectNativeCpuAndFeatures(io: Io) ?Target.Cpu { |
| 596 | 598 | return switch (current_arch) { |
| 597 | 599 | .aarch64, .aarch64_be => b: { |
| 598 | 600 | const registers = [12]u64{ |
| 599 | getAArch64CpuFeature("MIDR_EL1"), | |
| 600 | getAArch64CpuFeature("ID_AA64PFR0_EL1"), | |
| 601 | getAArch64CpuFeature("ID_AA64PFR1_EL1"), | |
| 602 | getAArch64CpuFeature("ID_AA64DFR0_EL1"), | |
| 603 | getAArch64CpuFeature("ID_AA64DFR1_EL1"), | |
| 604 | getAArch64CpuFeature("ID_AA64AFR0_EL1"), | |
| 605 | getAArch64CpuFeature("ID_AA64AFR1_EL1"), | |
| 606 | getAArch64CpuFeature("ID_AA64ISAR0_EL1"), | |
| 607 | getAArch64CpuFeature("ID_AA64ISAR1_EL1"), | |
| 608 | getAArch64CpuFeature("ID_AA64MMFR0_EL1"), | |
| 609 | getAArch64CpuFeature("ID_AA64MMFR1_EL1"), | |
| 610 | getAArch64CpuFeature("ID_AA64MMFR2_EL1"), | |
| 601 | aarch64.mrs("MIDR_EL1"), | |
| 602 | aarch64.mrs("ID_AA64PFR0_EL1"), | |
| 603 | aarch64.mrs("ID_AA64PFR1_EL1"), | |
| 604 | aarch64.mrs("ID_AA64DFR0_EL1"), | |
| 605 | aarch64.mrs("ID_AA64DFR1_EL1"), | |
| 606 | aarch64.mrs("ID_AA64AFR0_EL1"), | |
| 607 | aarch64.mrs("ID_AA64AFR1_EL1"), | |
| 608 | aarch64.mrs("ID_AA64ISAR0_EL1"), | |
| 609 | aarch64.mrs("ID_AA64ISAR1_EL1"), | |
| 610 | aarch64.mrs("ID_AA64MMFR0_EL1"), | |
| 611 | aarch64.mrs("ID_AA64MMFR1_EL1"), | |
| 612 | aarch64.mrs("ID_AA64MMFR2_EL1"), | |
| 611 | 613 | }; |
| 612 | 614 | |
| 613 | 615 | break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(current_arch, registers); |