authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-07-07 10:35:08+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-07-07 10:35:08+02:00
loge672555f4f92725ac82c1aa687932ece2c91595f
tree1820a8bb22d17a9b31c25b064600b4ed107e51b5
parent160e1b229b6859861108270fc8783851a38517c6
parent773a555397684e602fc2a645f221babdfb0a5042

Merge pull request '`std.zig.system.loongarch`: use generic CPU model if we can't determine the model' (#36063) from alexrp/zig:loongarch-detect-generic into master

Reviewed-on: https://codeberg.org/ziglang/zig/pulls/36063

5 files changed, 28 insertions(+), 7 deletions(-)

lib/std/Target/loongarch.zig+1-3
...@@ -168,11 +168,9 @@ pub const cpu = struct {...@@ -168,11 +168,9 @@ pub const cpu = struct {
168 };168 };
169 pub const generic_la64: CpuModel = .{169 pub const generic_la64: CpuModel = .{
170 .name = "generic_la64",170 .name = "generic_la64",
171 .llvm_name = "generic-la64",171 .llvm_name = null,
172 .features = featureSet(&[_]Feature{172 .features = featureSet(&[_]Feature{
173 .@"64bit",173 .@"64bit",
174 .lsx,
175 .ual,
176 }),174 }),
177 };175 };
178 pub const la32rv1_0: CpuModel = .{176 pub const la32rv1_0: CpuModel = .{
lib/std/zig/system/loongarch.zig+17-2
...@@ -1,6 +1,13 @@...@@ -1,6 +1,13 @@
1const builtin = @import("builtin");1const builtin = @import("builtin");
2const std = @import("std");2const std = @import("std");
33
4const Variant = enum(u2) {
5 la32r = 0b00,
6 la32 = 0b01,
7 la64 = 0b10,
8 reserved = 0b11,
9};
10
4inline fn bit(input: u32, offset: u5) bool {11inline fn bit(input: u32, offset: u5) bool {
5 return (input >> offset) & 1 != 0;12 return (input >> offset) & 1 != 0;
6}13}
...@@ -19,10 +26,16 @@ pub fn detectNativeCpuAndFeatures(...@@ -19,10 +26,16 @@ pub fn detectNativeCpuAndFeatures(
19 _ = os;26 _ = os;
20 _ = query;27 _ = query;
2128
29 const variant: Variant = @enumFromInt(cpucfg(1) & 0b11);
30
22 var cpu: std.Target.Cpu = .{31 var cpu: std.Target.Cpu = .{
23 .arch = arch,32 .arch = arch,
24 .model = switch (cpucfg(0) & 0xf000) {33 .model = switch (cpucfg(0) & 0b1111000000000000) {
25 else => return null,34 else => switch (variant) {
35 .la32r, .la32 => &std.Target.loongarch.cpu.generic_la32,
36 .la64 => &std.Target.loongarch.cpu.generic_la64,
37 .reserved => unreachable,
38 },
26 0xc000 => &std.Target.loongarch.cpu.la464,39 0xc000 => &std.Target.loongarch.cpu.la464,
27 0xd000 => &std.Target.loongarch.cpu.la664,40 0xd000 => &std.Target.loongarch.cpu.la664,
28 },41 },
...@@ -31,6 +44,8 @@ pub fn detectNativeCpuAndFeatures(...@@ -31,6 +44,8 @@ pub fn detectNativeCpuAndFeatures(
3144
32 cpu.features.addFeatureSet(cpu.model.features);45 cpu.features.addFeatureSet(cpu.model.features);
3346
47 setFeature(&cpu, .@"32s", variant != .la32r);
48
34 const cfg2 = cpucfg(2);49 const cfg2 = cpucfg(2);
35 const cfg3 = cpucfg(3);50 const cfg3 = cpucfg(3);
3651
lib/zig.h+1-1
...@@ -4636,7 +4636,7 @@ static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) z...@@ -4636,7 +4636,7 @@ static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) z
46364636
4637static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) {4637static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) {
4638#if defined(zig_gnuc_asm)4638#if defined(zig_gnuc_asm)
4639 __asm__("cpucfg %[result], %[word]" : [result] "=r" (result) : [word] "r" (word));4639 __asm__("cpucfg %[result], %[word]" : [result] "=r" (*result) : [word] "r" (word));
4640#else4640#else
4641 *result = 0;4641 *result = 0;
4642#endif4642#endif
stage1/zig.h+1-1
...@@ -4636,7 +4636,7 @@ static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) z...@@ -4636,7 +4636,7 @@ static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) z
46364636
4637static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) {4637static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) {
4638#if defined(zig_gnuc_asm)4638#if defined(zig_gnuc_asm)
4639 __asm__("cpucfg %[result], %[word]" : [result] "=r" (result) : [word] "r" (word));4639 __asm__("cpucfg %[result], %[word]" : [result] "=r" (*result) : [word] "r" (word));
4640#else4640#else
4641 *result = 0;4641 *result = 0;
4642#endif4642#endif
tools/update_cpu_features.zig+8
...@@ -1345,6 +1345,13 @@ const targets = [_]ArchTarget{...@@ -1345,6 +1345,13 @@ const targets = [_]ArchTarget{
1345 .td_name = "LoongArch",1345 .td_name = "LoongArch",
1346 },1346 },
1347 .extra_cpus = &.{1347 .extra_cpus = &.{
1348 .{
1349 .llvm_name = null,
1350 .zig_name = "generic_la64",
1351 .features = &.{
1352 "64bit",
1353 },
1354 },
1348 .{1355 .{
1349 .llvm_name = null,1356 .llvm_name = null,
1350 .zig_name = "la32v1_0",1357 .zig_name = "la32v1_0",
...@@ -1390,6 +1397,7 @@ const targets = [_]ArchTarget{...@@ -1390,6 +1397,7 @@ const targets = [_]ArchTarget{
1390 },1397 },
1391 .omit_cpus = &.{1398 .omit_cpus = &.{
1392 "generic",1399 "generic",
1400 "generic-la64",
1393 "loongarch32",1401 "loongarch32",
1394 "loongarch64",1402 "loongarch64",
1395 },1403 },