| author |  Alex Rønne Petersen <alex@alexrp.com> 2026-10-20 02:49:30+02:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2026-10-20 03:29:36+02:00 |
| log | e76f969f1a3c961cb308a7d4887b0d4c4ccf985b |
| tree | 248879a4d503b174d89da222a03bf3bb050599f7 |
| parent | acc1233c8b2d007d6f515bb80944a8d8cfe53a4f |
| signature | Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
update_cpu_features: flesh out ve data
3 files changed, 52 insertions(+), 3 deletions(-)
lib
std
- Target.zig
Target
lib/std/Target.zig+1
| ... | @@ -2066,6 +2066,7 @@ pub const Cpu = struct { | ... | @@ -2066,6 +2066,7 @@ pub const Cpu = struct { |
| 2066 | .riscv64, .riscv64be => &riscv.cpu.generic_rv64, | 2066 | .riscv64, .riscv64be => &riscv.cpu.generic_rv64, |
| 2067 | .sparc => &sparc.cpu.v7, | 2067 | .sparc => &sparc.cpu.v7, |
| 2068 | .sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up. | 2068 | .sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up. |
| 2069 | .ve => &ve.cpu.ve10, | ||
| 2069 | .wasm32, .wasm64 => &wasm.cpu.mvp, | 2070 | .wasm32, .wasm64 => &wasm.cpu.mvp, |
| 2070 | .x86_16 => &x86.cpu.i86, | 2071 | .x86_16 => &x86.cpu.i86, |
| 2071 | .x86 => &x86.cpu.i386, | 2072 | .x86 => &x86.cpu.i386, |
lib/std/Target/ve.zig+24-3
| ... | @@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature; | ... | @@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature; |
| 5 | const CpuModel = std.Target.Cpu.Model; | 5 | const CpuModel = std.Target.Cpu.Model; |
| 6 | 6 | ||
| 7 | pub const Feature = enum { | 7 | pub const Feature = enum { |
| 8 | ve3, | ||
| 8 | vpu, | 9 | vpu, |
| 9 | }; | 10 | }; |
| 10 | 11 | ||
| ... | @@ -17,6 +18,11 @@ pub const all_features = blk: { | ... | @@ -17,6 +18,11 @@ pub const all_features = blk: { |
| 17 | const len = @typeInfo(Feature).@"enum".field_names.len; | 18 | const len = @typeInfo(Feature).@"enum".field_names.len; |
| 18 | std.debug.assert(len <= CpuFeature.Set.needed_bit_count); | 19 | std.debug.assert(len <= CpuFeature.Set.needed_bit_count); |
| 19 | var result: [len]CpuFeature = undefined; | 20 | var result: [len]CpuFeature = undefined; |
| 21 | result[@backingInt(Feature.ve3)] = .{ | ||
| 22 | .llvm_name = null, | ||
| 23 | .description = "Enable VE3 instructions", | ||
| 24 | .dependencies = featureSet(&[_]Feature{}), | ||
| 25 | }; | ||
| 20 | result[@backingInt(Feature.vpu)] = .{ | 26 | result[@backingInt(Feature.vpu)] = .{ |
| 21 | .llvm_name = "vpu", | 27 | .llvm_name = "vpu", |
| 22 | .description = "Enable the VPU", | 28 | .description = "Enable the VPU", |
| ... | @@ -31,10 +37,25 @@ pub const all_features = blk: { | ... | @@ -31,10 +37,25 @@ pub const all_features = blk: { |
| 31 | }; | 37 | }; |
| 32 | 38 | ||
| 33 | pub const cpu = struct { | 39 | pub const cpu = struct { |
| 34 | pub const generic: CpuModel = .{ | 40 | pub const ve10: CpuModel = .{ |
| 35 | .name = "generic", | 41 | .name = "ve10", |
| 36 | .llvm_name = "generic", | 42 | .llvm_name = null, |
| 43 | .features = featureSet(&[_]Feature{ | ||
| 44 | .vpu, | ||
| 45 | }), | ||
| 46 | }; | ||
| 47 | pub const ve20: CpuModel = .{ | ||
| 48 | .name = "ve20", | ||
| 49 | .llvm_name = null, | ||
| 50 | .features = featureSet(&[_]Feature{ | ||
| 51 | .vpu, | ||
| 52 | }), | ||
| 53 | }; | ||
| 54 | pub const ve30: CpuModel = .{ | ||
| 55 | .name = "ve30", | ||
| 56 | .llvm_name = null, | ||
| 37 | .features = featureSet(&[_]Feature{ | 57 | .features = featureSet(&[_]Feature{ |
| 58 | .ve3, | ||
| 38 | .vpu, | 59 | .vpu, |
| 39 | }), | 60 | }), |
| 40 | }; | 61 | }; |
tools/update_cpu_features.zig+27
| ... | @@ -1737,6 +1737,33 @@ const targets = [_]ArchTarget{ | ... | @@ -1737,6 +1737,33 @@ const targets = [_]ArchTarget{ |
| 1737 | .name = "VE", | 1737 | .name = "VE", |
| 1738 | .td_name = "VE", | 1738 | .td_name = "VE", |
| 1739 | }, | 1739 | }, |
| 1740 | .extra_features = &.{ | ||
| 1741 | .{ | ||
| 1742 | .zig_name = "ve3", | ||
| 1743 | .desc = "Enable VE3 instructions", | ||
| 1744 | .deps = &.{}, | ||
| 1745 | }, | ||
| 1746 | }, | ||
| 1747 | .extra_cpus = &.{ | ||
| 1748 | .{ | ||
| 1749 | .llvm_name = null, | ||
| 1750 | .zig_name = "ve10", | ||
| 1751 | .features = &.{"vpu"}, | ||
| 1752 | }, | ||
| 1753 | .{ | ||
| 1754 | .llvm_name = null, | ||
| 1755 | .zig_name = "ve20", | ||
| 1756 | .features = &.{"vpu"}, | ||
| 1757 | }, | ||
| 1758 | .{ | ||
| 1759 | .llvm_name = null, | ||
| 1760 | .zig_name = "ve30", | ||
| 1761 | .features = &.{ "ve3", "vpu" }, | ||
| 1762 | }, | ||
| 1763 | }, | ||
| 1764 | .omit_cpus = &.{ | ||
| 1765 | "generic", | ||
| 1766 | }, | ||
| 1740 | }, | 1767 | }, |
| 1741 | .{ | 1768 | .{ |
| 1742 | .zig_name = "wasm", | 1769 | .zig_name = "wasm", |