Commit e771583d88f18548b3b012df004ea9ef5201e5cf | zig

author	Alex Rønne Petersen <alex@alexrp.com> 2026-10-20 09:52:48+02:00
committer	Alex Rønne Petersen <alex@alexrp.com> 2026-10-20 09:52:48+02:00
log	e771583d88f18548b3b012df004ea9ef5201e5cf
tree	f527f4b6a4159d1d25681c2268e1bd9e3da23898
parent	099361c14699cc28eb3fcefd1adf3bfd509883a0
parent	ffe1510d292ce7cf21dab97a7d33c3627d23ebf9

Merge pull request '`std.Target`: more fixes' (#37334) from alexrp/zig:target-fixes into master

Reviewed-on: https://codeberg.org/ziglang/zig/pulls/37334

15 files changed, 1142 insertions(+), 1030 deletions(-)

lib
- compiler_rt
  - atomics.zig
- std
  - Target.zig
  - Target
    alpha.zig
    arm.zig
    bpf.zig
    csky.zig
    hppa.zig
    kvx.zig
    ve.zig
    wasm.zig
    x86.zig
    xcore.zig
src
- Type.zig
test
- c_abi
  - main.zig
tools
- update_cpu_features.zig

lib/compiler_rt/atomics.zig+1-1

...	...	@@ -13,7 +13,7 @@ const symbol = compiler_rt.symbol;
13	13	// detail to keep the export logic clean and because we need some kind of CAS to
14	14	// implement the spinlocks.
15	15	const supports_atomic_ops = switch (arch) {
16		.msp430, .avr, .bpfel, .bpfeb => false,
	16	.msp430, .avr, .bpfel, .bpfeb, .lanai => false,
17	17	.arm, .armeb, .thumb, .thumbeb =>
18	18	// The ARM v6m ISA has no ldrex/strex and so it's impossible to do CAS
19	19	// operations (unless we're targeting Linux, the kernel provides a way to

lib/std/Target.zig+113-101

...	...	@@ -2069,10 +2069,12 @@ pub const Cpu = struct {
2069	2069	.riscv64, .riscv64be => &riscv.cpu.generic_rv64,
2070	2070	.sparc => &sparc.cpu.v7,
2071	2071	.sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.
	2072	.ve => &ve.cpu.ve10,
2072	2073	.wasm32, .wasm64 => &wasm.cpu.mvp,
2073	2074	.x86_16 => &x86.cpu.i86,
2074	2075	.x86 => &x86.cpu.i386,
2075	2076	.x86_64 => &x86.cpu.x86_64,
	2077	.xcore => &xcore.cpu.xs1b,
2076	2078	inline else => \|a\| &@field(Target, @tagName(a.family())).cpu.generic,
2077	2079	};
2078	2080	}
...	...	@@ -2087,16 +2089,16 @@ pub const Cpu = struct {
2087	2089	/// `Os.Tag.freestanding`.
2088	2090	pub fn baseline(arch: Arch, os: Os) *const Model {
2089	2091	return switch (arch) {
2090		.alpha => &alpha.cpu.ev6,
	2092	.alpha => &alpha.cpu.ev56,
2091	2093	.amdgcn => &amdgcn.cpu.gfx906,
2092	2094	.arm => switch (os.tag) {
2093	2095	.@"3ds" => &arm.cpu.mpcore,
2094		.vita => &arm.cpu.cortex_a9,
	2096	.vita => &arm.cpu.kermit,
2095	2097	.gba => &arm.cpu.arm7tdmi,
2096	2098	else => &arm.cpu.baseline,
2097	2099	},
2098	2100	.thumb => switch (os.tag) {
2099		.vita => &arm.cpu.cortex_a9,
	2101	.vita => &arm.cpu.kermit,
2100	2102	.gba => &arm.cpu.arm7tdmi,
2101	2103	else => &arm.cpu.baseline,
2102	2104	},
...	...	@@ -2114,8 +2116,7 @@ pub const Cpu = struct {
2114	2116	.bpfel, .bpfeb => &bpf.cpu.v3,
2115	2117	.csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model.
2116	2118	.hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model.
2117		.hppa => &hppa.cpu.pa_7300lc,
2118		.kvx => &kvx.cpu.coolidge_v2,
	2119	.hppa => &hppa.cpu.pa_7000,
2119	2120	.lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
2120	2121	.loongarch32 => &loongarch.cpu.la32v1_0,
2121	2122	.loongarch64 => &loongarch.cpu.la64v1_0,
...	...	@@ -2160,7 +2161,6 @@ pub const Cpu = struct {
2160	2161	.ps5 => &x86.cpu.znver2,
2161	2162	else => generic(arch),
2162	2163	},
2163		.xcore => &xcore.cpu.xs1b_generic,
2164	2164	.xtensa => &xtensa.cpu.esp32,
2165	2165	.wasm32, .wasm64 => &wasm.cpu.lime1,
2166	2166
...	...	@@ -2599,6 +2599,16 @@ pub const DynamicLinker = struct {
2599	2599	if (ptrBitWidth_cpu_abi(cpu, abi) == 64) "64" else "",
2600	2600	}) else none,
2601	2601
	2602	else => none,
	2603	}
	2604	else if (abi.isOpenHarmony())
	2605	switch (cpu.arch) {
	2606	.aarch64,
	2607	.x86_64,
	2608	=> \|arch\| if (abi == .ohos) initFmt("/lib/ld-musl-{s}.so.1", .{@tagName(arch)}) else none,
	2609
	2610	.arm => if (abi == .ohoseabi) init("/lib/ld-musl-arm.so.1") else none,
	2611
2602	2612	else => none,
2603	2613	}
2604	2614	else if (abi.isMusl())
...	...	@@ -2750,7 +2760,6 @@ pub const DynamicLinker = struct {
2750	2760	},
2751	2761	}),
2752	2762
2753		.hppa,
2754	2763	.m68k,
2755	2764	.microblaze,
2756	2765	.microblazeel,
...	...	@@ -2780,7 +2789,9 @@ pub const DynamicLinker = struct {
2780	2789	if (cpu.has(.mips, .nan2008)) "-linux-mipsn8" else "",
2781	2790	}),
2782	2791
2783		.powerpc => switch (abi) {
	2792	.hppa,
	2793	.powerpc,
	2794	=> switch (abi) {
2784	2795	.gnueabi,
2785	2796	.gnueabihf,
2786	2797	=> init("/lib/ld.so.1"),
...	...	@@ -3058,14 +3069,17 @@ pub fn ptrBitWidth(target: *const Target) u16 {
3058	3069	pub fn stackAlignment(target: *const Target) u16 {
3059	3070	// Overrides for when the stack alignment is not equal to the pointer width.
3060	3071	switch (target.cpu.arch) {
3061		.ez80 => return 1,
	3072	.avr,
	3073	.ez80,
	3074	=> return 1,
3062	3075
3063		.m68k => return 2,
	3076	.m68k => if (target.os.tag != .netbsd) return 2,
3064	3077
3065	3078	.amdgcn => return 4,
3066	3079
3067	3080	.arm,
3068	3081	.armeb,
	3082	.hexagon,
3069	3083	.hppa,
3070	3084	.lanai,
3071	3085	.mips,
...	...	@@ -3083,28 +3097,34 @@ pub fn stackAlignment(target: *const Target) u16 {
3083	3097	.hppa64,
3084	3098	.loongarch32,
3085	3099	.loongarch64,
	3100	.m88k,
3086	3101	.mips64,
3087	3102	.mips64el,
	3103	.powerpc,
	3104	.powerpcle,
	3105	.powerpc64,
	3106	.powerpc64le,
3088	3107	.sparc64,
3089	3108	.ve,
3090	3109	.wasm32,
3091	3110	.wasm64,
3092	3111	.x86_64,
	3112	.xtensa,
	3113	.xtensaeb,
3093	3114	=> return 16,
3094	3115
3095		// Some of the following prongs should really be testing the ABI, but our current `Abi` enum
3096		// can't handle that level of nuance yet.
3097		.powerpc64,
3098		.powerpc64le,
3099		=> if (target.os.tag == .linux) return 16,
3100
3101	3116	.riscv32,
3102	3117	.riscv32be,
3103	3118	.riscv64,
3104	3119	.riscv64be,
3105	3120	=> if (!target.cpu.has(.riscv, .e)) return 16,
3106	3121
3107		.x86 => if (target.os.tag != .windows and target.os.tag != .uefi) return 16,
	3122	.x86 => switch (target.os.tag) {
	3123	.hurd,
	3124	.linux,
	3125	=> return 16,
	3126	else => {},
	3127	},
3108	3128
3109	3129	.kvx => return 32,
3110	3130
...	...	@@ -3160,6 +3180,7 @@ pub fn cCharSignedness(target: *const Target) ?std.builtin.Signedness {
3160	3180	.powerpcle,
3161	3181	.powerpc64,
3162	3182	.powerpc64le,
	3183	.propeller,
3163	3184	.s390x,
3164	3185	.riscv32,
3165	3186	.riscv32be,
...	...	@@ -3223,6 +3244,7 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 {
3223	3244	.freestanding,
3224	3245	.other,
3225	3246	.ashetos,
	3247	.tios,
3226	3248	=> switch (target.cpu.arch) {
3227	3249	.msp430,
3228	3250	.x86_16,
...	...	@@ -3245,6 +3267,13 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 {
3245	3267	.long, .ulong, .float => 32,
3246	3268	.double, .longdouble, .longlong, .ulonglong => 64,
3247	3269	},
	3270	.ez80 => switch (c_type) {
	3271	.char => 8,
	3272	.short, .ushort => 16,
	3273	.int, .uint => 24,
	3274	.long, .ulong, .float, .double => 32,
	3275	.longlong, .ulonglong, .longdouble => 64,
	3276	},
3248	3277	else => switch (c_type) {
3249	3278	.char => 8,
3250	3279	.short, .ushort => 16,
...	...	@@ -3302,88 +3331,73 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 {
3302	3331
3303	3332	.wasi,
3304	3333	.emscripten,
3305		=> switch (target.cpu.arch) {
3306		.mips64,
3307		.mips64el,
3308		=> switch (c_type) {
3309		.char => 8,
3310		.short, .ushort => 16,
3311		.int, .uint, .float => 32,
3312		.long, .ulong => switch (target.abi) {
3313		.gnuabin32, .muslabin32, .abin32 => 32,
3314		else => 64,
3315		},
3316		.longlong, .ulonglong, .double => 64,
3317		.longdouble => 128,
	3334	=> switch (c_type) {
	3335	.char => 8,
	3336	.short, .ushort => 16,
	3337	.int, .uint, .float => 32,
	3338	.long, .ulong => switch (target.os.tag) {
	3339	.plan9 => 32, // This is certainly A Choice.
	3340	else => target.ptrBitWidth(),
3318	3341	},
3319		.x86_64 => switch (c_type) {
3320		.char => 8,
3321		.short, .ushort => 16,
3322		.int, .uint, .float => 32,
3323		.long, .ulong => switch (target.abi) {
3324		.gnux32, .muslx32, .x32 => 32,
3325		else => 64,
	3342	.longlong, .ulonglong, .double => 64,
	3343	.longdouble => switch (target.cpu.arch) {
	3344	.x86,
	3345	.x86_64,
	3346	=> switch (target.abi) {
	3347	.android, .ohos => 64,
	3348	else => 80,
3326	3349	},
3327		.longlong, .ulonglong, .double => 64,
3328		.longdouble => 80,
3329		},
3330		else => switch (c_type) {
3331		.char => 8,
3332		.short, .ushort => 16,
3333		.int, .uint, .float => 32,
3334		.long, .ulong => target.ptrBitWidth(),
3335		.longlong, .ulonglong, .double => 64,
3336		.longdouble => switch (target.cpu.arch) {
3337		.x86 => switch (target.abi) {
3338		.android => 64,
3339		else => 80,
3340		},
3341	3350
3342		.powerpc,
3343		.powerpcle,
3344		=> switch (target.abi) {
3345		.musleabi, .musleabihf => 64,
3346		else => switch (target.os.tag) {
3347		.netbsd,
3348		.openbsd,
3349		=> 64,
3350		else => 128,
3351		},
	3351	.powerpc,
	3352	.powerpcle,
	3353	=> switch (target.abi) {
	3354	.musleabi, .musleabihf => 64,
	3355	else => switch (target.os.tag) {
	3356	.netbsd,
	3357	.openbsd,
	3358	=> 64,
	3359	else => 128,
3352	3360	},
	3361	},
3353	3362
3354		.powerpc64,
3355		.powerpc64le,
3356		=> switch (target.abi) {
3357		.musl => 64,
3358		else => switch (target.os.tag) {
3359		.freebsd,
3360		.openbsd,
3361		=> 64,
3362		else => 128,
3363		},
	3363	.powerpc64,
	3364	.powerpc64le,
	3365	=> switch (target.abi) {
	3366	.musl => 64,
	3367	else => switch (target.os.tag) {
	3368	.freebsd,
	3369	.openbsd,
	3370	=> 64,
	3371	else => 128,
3364	3372	},
	3373	},
3365	3374
3366		.alpha,
3367		.riscv32,
3368		.riscv32be,
3369		.riscv64,
3370		.riscv64be,
3371		.aarch64,
3372		.aarch64_be,
3373		.s390x,
3374		.mips64,
3375		.mips64el,
3376		.sparc,
3377		.sparc64,
3378		.wasm32,
3379		.wasm64,
3380		.loongarch32,
3381		.loongarch64,
3382		.ve,
3383		=> 128,
3384
3385		else => 64,
	3375	.alpha => switch (target.os.tag) {
	3376	.netbsd,
	3377	.openbsd,
	3378	=> 64,
	3379	else => 128,
3386	3380	},
	3381
	3382	.riscv32,
	3383	.riscv32be,
	3384	.riscv64,
	3385	.riscv64be,
	3386	.aarch64,
	3387	.aarch64_be,
	3388	.s390x,
	3389	.mips64,
	3390	.mips64el,
	3391	.sparc,
	3392	.sparc64,
	3393	.wasm32,
	3394	.wasm64,
	3395	.loongarch32,
	3396	.loongarch64,
	3397	.ve,
	3398	=> 128,
	3399
	3400	else => 64,
3387	3401	},
3388	3402	},
3389	3403
...	...	@@ -3481,14 +3495,6 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 {
3481	3495	.longdouble => 80,
3482	3496	},
3483	3497
3484		.tios => switch (c_type) {
3485		.char => 8,
3486		.short, .ushort => 16,
3487		.int, .uint => 24,
3488		.long, .ulong, .float, .double => 32,
3489		.longlong, .ulonglong, .longdouble => 64,
3490		},
3491
3492	3498	.opengl => null,
3493	3499	};
3494	3500	}
...	...	@@ -3739,7 +3745,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3739	3745	.lanai => .{ .lanai_sysv = .{} },
3740	3746	.loongarch64 => .{ .loongarch64_lp64 = .{} },
3741	3747	.loongarch32 => .{ .loongarch32_ilp32 = .{} },
3742		.m68k => .{ .m68k_gnu = .{} },
	3748	.m68k => switch (target.os.tag) {
	3749	.netbsd => .{ .m68k_sysv = .{} },
	3750	else => .{ .m68k_gnu = .{} },
	3751	},
3743	3752	.m88k => .{ .m88k_sysv = .{} },
3744	3753	.microblaze, .microblazeel => .{ .microblaze_std = .{} },
3745	3754	.msp430 => .{ .msp430_eabi = .{} },
...	...	@@ -3749,7 +3758,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3749	3758	.sh, .sheb => .{ .sh_gnu = .{} },
3750	3759	.ve => .{ .ve_sysv = .{} },
3751	3760	.xcore => .{ .xcore_xs1 = .{} },
3752		.xtensa, .xtensaeb => .{ .xtensa_call0 = .{} },
	3761	.xtensa, .xtensaeb => switch (target.abi) {
	3762	.call0 => .{ .xtensa_call0 = .{} },
	3763	else => .{ .xtensa_windowed = .{} },
	3764	},
3753	3765	.amdgcn => .{ .amdgcn_device = .{} },
3754	3766	.nvptx, .nvptx64 => .nvptx_device,
3755	3767	.spirv32, .spirv64 => .spirv_device,

lib/std/Target/alpha.zig+1-1

...	...	@@ -32,7 +32,7 @@ pub const all_features = blk: {
32	32	};
33	33	result[@backingInt(Feature.fix)] = .{
34	34	.llvm_name = null,
35		.description = "Enable floating point move and square root extensions",
	35	.description = "Enable FPR-to-GPR move and square root extensions",
36	36	.dependencies = featureSet(&[_]Feature{}),
37	37	};
38	38	result[@backingInt(Feature.max)] = .{

lib/std/Target/arm.zig+37-39

...	...	@@ -1200,7 +1200,6 @@ pub const all_features = blk: {
1200	1200	.db,
1201	1201	.dsp,
1202	1202	.has_v7,
1203		.neon,
1204	1203	.perfmon,
1205	1204	}),
1206	1205	};
...	...	@@ -1250,7 +1249,6 @@ pub const all_features = blk: {
1250	1249	.dsp,
1251	1250	.has_v7,
1252	1251	.mp,
1253		.neon,
1254	1252	.perfmon,
1255	1253	.trustzone,
1256	1254	.virtualization,
...	...	@@ -1262,12 +1260,12 @@ pub const all_features = blk: {
1262	1260	.dependencies = featureSet(&[_]Feature{
1263	1261	.aclass,
1264	1262	.crc,
1265		.crypto,
1266	1263	.db,
1267	1264	.dsp,
1268	1265	.fp_armv8,
1269	1266	.has_v8_1a,
1270	1267	.mp,
	1268	.neon,
1271	1269	.trustzone,
1272	1270	.virtualization,
1273	1271	}),
...	...	@@ -1276,7 +1274,6 @@ pub const all_features = blk: {
1276	1274	.llvm_name = "armv8.1-m.main",
1277	1275	.description = "ARMv81mMainline architecture",
1278	1276	.dependencies = featureSet(&[_]Feature{
1279		.@"8msecext",
1280	1277	.acquire_release,
1281	1278	.db,
1282	1279	.has_v8_1m_main,
...	...	@@ -1294,12 +1291,12 @@ pub const all_features = blk: {
1294	1291	.dependencies = featureSet(&[_]Feature{
1295	1292	.aclass,
1296	1293	.crc,
1297		.crypto,
1298	1294	.db,
1299	1295	.dsp,
1300	1296	.fp_armv8,
1301	1297	.has_v8_2a,
1302	1298	.mp,
	1299	.neon,
1303	1300	.ras,
1304	1301	.trustzone,
1305	1302	.virtualization,
...	...	@@ -1311,12 +1308,12 @@ pub const all_features = blk: {
1311	1308	.dependencies = featureSet(&[_]Feature{
1312	1309	.aclass,
1313	1310	.crc,
1314		.crypto,
1315	1311	.db,
1316	1312	.dsp,
1317	1313	.fp_armv8,
1318	1314	.has_v8_3a,
1319	1315	.mp,
	1316	.neon,
1320	1317	.ras,
1321	1318	.trustzone,
1322	1319	.virtualization,
...	...	@@ -1328,7 +1325,6 @@ pub const all_features = blk: {
1328	1325	.dependencies = featureSet(&[_]Feature{
1329	1326	.aclass,
1330	1327	.crc,
1331		.crypto,
1332	1328	.db,
1333	1329	.dsp,
1334	1330	.fp_armv8,
...	...	@@ -1345,7 +1341,6 @@ pub const all_features = blk: {
1345	1341	.dependencies = featureSet(&[_]Feature{
1346	1342	.aclass,
1347	1343	.crc,
1348		.crypto,
1349	1344	.db,
1350	1345	.dsp,
1351	1346	.fp_armv8,
...	...	@@ -1362,7 +1357,6 @@ pub const all_features = blk: {
1362	1357	.dependencies = featureSet(&[_]Feature{
1363	1358	.aclass,
1364	1359	.crc,
1365		.crypto,
1366	1360	.db,
1367	1361	.dsp,
1368	1362	.fp_armv8,
...	...	@@ -1379,7 +1373,6 @@ pub const all_features = blk: {
1379	1373	.dependencies = featureSet(&[_]Feature{
1380	1374	.aclass,
1381	1375	.crc,
1382		.crypto,
1383	1376	.db,
1384	1377	.dsp,
1385	1378	.fp_armv8,
...	...	@@ -1396,7 +1389,6 @@ pub const all_features = blk: {
1396	1389	.dependencies = featureSet(&[_]Feature{
1397	1390	.aclass,
1398	1391	.crc,
1399		.crypto,
1400	1392	.db,
1401	1393	.dsp,
1402	1394	.fp_armv8,
...	...	@@ -1413,7 +1405,6 @@ pub const all_features = blk: {
1413	1405	.dependencies = featureSet(&[_]Feature{
1414	1406	.aclass,
1415	1407	.crc,
1416		.crypto,
1417	1408	.db,
1418	1409	.dsp,
1419	1410	.fp_armv8,
...	...	@@ -1430,12 +1421,12 @@ pub const all_features = blk: {
1430	1421	.dependencies = featureSet(&[_]Feature{
1431	1422	.aclass,
1432	1423	.crc,
1433		.crypto,
1434	1424	.db,
1435	1425	.dsp,
1436	1426	.fp_armv8,
1437	1427	.has_v8,
1438	1428	.mp,
	1429	.neon,
1439	1430	.trustzone,
1440	1431	.virtualization,
1441	1432	}),
...	...	@@ -1444,7 +1435,6 @@ pub const all_features = blk: {
1444	1435	.llvm_name = "armv8-m.base",
1445	1436	.description = "ARMv8mBaseline architecture",
1446	1437	.dependencies = featureSet(&[_]Feature{
1447		.@"8msecext",
1448	1438	.acquire_release,
1449	1439	.db,
1450	1440	.has_v7clrex,
...	...	@@ -1460,7 +1450,6 @@ pub const all_features = blk: {
1460	1450	.llvm_name = "armv8-m.main",
1461	1451	.description = "ARMv8mMainline architecture",
1462	1452	.dependencies = featureSet(&[_]Feature{
1463		.@"8msecext",
1464	1453	.acquire_release,
1465	1454	.db,
1466	1455	.has_v8m_main,
...	...	@@ -1523,7 +1512,6 @@ pub const all_features = blk: {
1523	1512	.dependencies = featureSet(&[_]Feature{
1524	1513	.aclass,
1525	1514	.crc,
1526		.crypto,
1527	1515	.db,
1528	1516	.dsp,
1529	1517	.fp_armv8,
...	...	@@ -1949,6 +1937,7 @@ pub const cpu = struct {
1949	1937	.llvm_name = "generic",
1950	1938	.features = featureSet(&[_]Feature{
1951	1939	.v7a,
	1940	.vfp3d16,
1952	1941	}),
1953	1942	};
1954	1943	pub const cortex_a12: CpuModel = .{
...	...	@@ -1960,7 +1949,6 @@ pub const cpu = struct {
1960	1949	.ret_addr_stack,
1961	1950	.trustzone,
1962	1951	.v7a,
1963		.vfp4,
1964	1952	.virtualization,
1965	1953	.vmlx_forwarding,
1966	1954	}),
...	...	@@ -1976,7 +1964,6 @@ pub const cpu = struct {
1976	1964	.splat_vfp_neon,
1977	1965	.trustzone,
1978	1966	.v7a,
1979		.vfp4,
1980	1967	.virtualization,
1981	1968	.vldn_align,
1982	1969	}),
...	...	@@ -1990,7 +1977,6 @@ pub const cpu = struct {
1990	1977	.ret_addr_stack,
1991	1978	.trustzone,
1992	1979	.v7a,
1993		.vfp4,
1994	1980	.virtualization,
1995	1981	.vmlx_forwarding,
1996	1982	}),
...	...	@@ -2020,7 +2006,6 @@ pub const cpu = struct {
2020	2006	.slowfpvmlx,
2021	2007	.trustzone,
2022	2008	.v7a,
2023		.vfp4,
2024	2009	.vmlx_forwarding,
2025	2010	}),
2026	2011	};
...	...	@@ -2072,7 +2057,6 @@ pub const cpu = struct {
2072	2057	.slowfpvmlx,
2073	2058	.trustzone,
2074	2059	.v7a,
2075		.vfp4,
2076	2060	.virtualization,
2077	2061	.vmlx_forwarding,
2078	2062	.vmlx_hazards,
...	...	@@ -2186,7 +2170,6 @@ pub const cpu = struct {
2186	2170	.features = featureSet(&[_]Feature{
2187	2171	.avoid_partial_cpsr,
2188	2172	.expand_fp_mlx,
2189		.fp16,
2190	2173	.mp,
2191	2174	.muxed_units,
2192	2175	.neon_fpmovs,
...	...	@@ -2285,12 +2268,10 @@ pub const cpu = struct {
2285	2268	.name = "cortex_m52",
2286	2269	.llvm_name = "cortex-m52",
2287	2270	.features = featureSet(&[_]Feature{
2288		.fp_armv8d16,
	2271	.dsp,
2289	2272	.loop_align,
2290	2273	.mve1beat,
2291		.mve_fp,
2292	2274	.no_branch_predictor,
2293		.pacbti,
2294	2275	.slowfpvmlx,
2295	2276	.use_misched,
2296	2277	.v8_1m_main,
...	...	@@ -2324,6 +2305,7 @@ pub const cpu = struct {
2324	2305	.name = "cortex_m85",
2325	2306	.llvm_name = "cortex-m85",
2326	2307	.features = featureSet(&[_]Feature{
	2308	.@"8msecext",
2327	2309	.branch_align_64,
2328	2310	.dsp,
2329	2311	.m85,
...	...	@@ -2364,16 +2346,13 @@ pub const cpu = struct {
2364	2346	.slowfpvfmx,
2365	2347	.slowfpvmlx,
2366	2348	.v7r,
2367		.vfp3d16,
2368	2349	}),
2369	2350	};
2370	2351	pub const cortex_r52: CpuModel = .{
2371	2352	.name = "cortex_r52",
2372	2353	.llvm_name = "cortex-r52",
2373	2354	.features = featureSet(&[_]Feature{
2374		.fp_armv8,
2375	2355	.fpao,
2376		.neon,
2377	2356	.use_misched,
2378	2357	.v8r,
2379	2358	}),
...	...	@@ -2382,9 +2361,7 @@ pub const cpu = struct {
2382	2361	.name = "cortex_r52plus",
2383	2362	.llvm_name = "cortex-r52plus",
2384	2363	.features = featureSet(&[_]Feature{
2385		.fp_armv8,
2386	2364	.fpao,
2387		.neon,
2388	2365	.use_misched,
2389	2366	.v8r,
2390	2367	}),
...	...	@@ -2394,7 +2371,6 @@ pub const cpu = struct {
2394	2371	.llvm_name = "cortex-r7",
2395	2372	.features = featureSet(&[_]Feature{
2396	2373	.avoid_partial_cpsr,
2397		.fp16,
2398	2374	.hwdiv_arm,
2399	2375	.mp,
2400	2376	.ret_addr_stack,
...	...	@@ -2402,7 +2378,6 @@ pub const cpu = struct {
2402	2378	.slowfpvfmx,
2403	2379	.slowfpvmlx,
2404	2380	.v7r,
2405		.vfp3d16,
2406	2381	}),
2407	2382	};
2408	2383	pub const cortex_r8: CpuModel = .{
...	...	@@ -2410,7 +2385,6 @@ pub const cpu = struct {
2410	2385	.llvm_name = "cortex-r8",
2411	2386	.features = featureSet(&[_]Feature{
2412	2387	.avoid_partial_cpsr,
2413		.fp16,
2414	2388	.hwdiv_arm,
2415	2389	.mp,
2416	2390	.ret_addr_stack,
...	...	@@ -2418,7 +2392,6 @@ pub const cpu = struct {
2418	2392	.slowfpvfmx,
2419	2393	.slowfpvmlx,
2420	2394	.v7r,
2421		.vfp3d16,
2422	2395	}),
2423	2396	};
2424	2397	pub const cortex_x1: CpuModel = .{
...	...	@@ -2445,6 +2418,7 @@ pub const cpu = struct {
2445	2418	.features = featureSet(&[_]Feature{
2446	2419	.avoid_movs_shop,
2447	2420	.avoid_partial_cpsr,
	2421	.crypto,
2448	2422	.disable_postra_scheduler,
2449	2423	.neonfp,
2450	2424	.ret_addr_stack,
...	...	@@ -2466,6 +2440,7 @@ pub const cpu = struct {
2466	2440	.name = "exynos_m1",
2467	2441	.llvm_name = null,
2468	2442	.features = featureSet(&[_]Feature{
	2443	.crypto,
2469	2444	.expand_fp_mlx,
2470	2445	.fuse_aes,
2471	2446	.fuse_literals,
...	...	@@ -2486,6 +2461,7 @@ pub const cpu = struct {
2486	2461	.name = "exynos_m2",
2487	2462	.llvm_name = null,
2488	2463	.features = featureSet(&[_]Feature{
	2464	.crypto,
2489	2465	.expand_fp_mlx,
2490	2466	.fuse_aes,
2491	2467	.fuse_literals,
...	...	@@ -2506,6 +2482,7 @@ pub const cpu = struct {
2506	2482	.name = "exynos_m3",
2507	2483	.llvm_name = "exynos-m3",
2508	2484	.features = featureSet(&[_]Feature{
	2485	.crypto,
2509	2486	.expand_fp_mlx,
2510	2487	.fuse_aes,
2511	2488	.fuse_literals,
...	...	@@ -2526,6 +2503,7 @@ pub const cpu = struct {
2526	2503	.name = "exynos_m4",
2527	2504	.llvm_name = "exynos-m4",
2528	2505	.features = featureSet(&[_]Feature{
	2506	.crypto,
2529	2507	.dotprod,
2530	2508	.expand_fp_mlx,
2531	2509	.fullfp16,
...	...	@@ -2548,6 +2526,7 @@ pub const cpu = struct {
2548	2526	.name = "exynos_m5",
2549	2527	.llvm_name = "exynos-m5",
2550	2528	.features = featureSet(&[_]Feature{
	2529	.crypto,
2551	2530	.dotprod,
2552	2531	.expand_fp_mlx,
2553	2532	.fullfp16,
...	...	@@ -2578,6 +2557,26 @@ pub const cpu = struct {
2578	2557	.v5te,
2579	2558	}),
2580	2559	};
	2560	pub const kermit: CpuModel = .{
	2561	.name = "kermit",
	2562	.llvm_name = "cortex-a9",
	2563	.features = featureSet(&[_]Feature{
	2564	.avoid_partial_cpsr,
	2565	.expand_fp_mlx,
	2566	.fp16,
	2567	.mp,
	2568	.muxed_units,
	2569	.neon,
	2570	.neon_fpmovs,
	2571	.prefer_vmovsr,
	2572	.ret_addr_stack,
	2573	.trustzone,
	2574	.v7a,
	2575	.vldn_align,
	2576	.vmlx_forwarding,
	2577	.vmlx_hazards,
	2578	}),
	2579	};
2581	2580	pub const krait: CpuModel = .{
2582	2581	.name = "krait",
2583	2582	.llvm_name = "krait",
...	...	@@ -2586,6 +2585,7 @@ pub const cpu = struct {
2586	2585	.hwdiv,
2587	2586	.hwdiv_arm,
2588	2587	.muxed_units,
	2588	.neon,
2589	2589	.ret_addr_stack,
2590	2590	.v7a,
2591	2591	.vfp4,
...	...	@@ -2597,6 +2597,7 @@ pub const cpu = struct {
2597	2597	.name = "kryo",
2598	2598	.llvm_name = "kryo",
2599	2599	.features = featureSet(&[_]Feature{
	2600	.crypto,
2600	2601	.v8a,
2601	2602	}),
2602	2603	};
...	...	@@ -2666,9 +2667,7 @@ pub const cpu = struct {
2666	2667	.llvm_name = "star-mc1",
2667	2668	.features = featureSet(&[_]Feature{
2668	2669	.avoid_muls,
2669		.dsp,
2670	2670	.fix_cmse_cve_2021_35465,
2671		.fp_armv8d16sp,
2672	2671	.loop_align,
2673	2672	.no_branch_predictor,
2674	2673	.slowfpvfmx,
...	...	@@ -2681,12 +2680,10 @@ pub const cpu = struct {
2681	2680	.name = "star_mc3",
2682	2681	.llvm_name = "star-mc3",
2683	2682	.features = featureSet(&[_]Feature{
2684		.fp_armv8d16,
	2683	.dsp,
2685	2684	.loop_align,
2686	2685	.mve1beat,
2687		.mve_fp,
2688	2686	.no_branch_predictor,
2689		.pacbti,
2690	2687	.slowfpvmlx,
2691	2688	.use_misched,
2692	2689	.v8_1m_main,
...	...	@@ -2730,6 +2727,7 @@ pub const cpu = struct {
2730	2727	.hwdiv,
2731	2728	.hwdiv_arm,
2732	2729	.mp,
	2730	.neon,
2733	2731	.neonfp,
2734	2732	.prefer_ishst,
2735	2733	.prof_unpr,

lib/std/Target/bpf.zig-12

...	...	@@ -7,8 +7,6 @@ const CpuModel = std.Target.Cpu.Model;
7	7	pub const Feature = enum {
8	8	allows_misaligned_mem_access,
9	9	alu32,
10		dummy,
11		dwarfris,
12	10	};
13	11
14	12	pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
...	...	@@ -30,16 +28,6 @@ pub const all_features = blk: {
30	28	.description = "Enable ALU32 instructions",
31	29	.dependencies = featureSet(&[_]Feature{}),
32	30	};
33		result[@backingInt(Feature.dummy)] = .{
34		.llvm_name = "dummy",
35		.description = "unused feature",
36		.dependencies = featureSet(&[_]Feature{}),
37		};
38		result[@backingInt(Feature.dwarfris)] = .{
39		.llvm_name = "dwarfris",
40		.description = "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections",
41		.dependencies = featureSet(&[_]Feature{}),
42		};
43	31	const ti = @typeInfo(Feature);
44	32	for (&result, 0..) \|*elem, i\| {
45	33	elem.index = i;

lib/std/Target/csky.zig-457

...	...	@@ -14,19 +14,6 @@ pub const Feature = enum {
14	14	@"7e10",
15	15	btst16,
16	16	cache,
17		ccrt,
18		ck801,
19		ck802,
20		ck803,
21		ck803s,
22		ck804,
23		ck805,
24		ck807,
25		ck810,
26		ck810v,
27		ck860,
28		ck860v,
29		constpool,
30	17	doloop,
31	18	dsp1e2,
32	19	dsp_silan,
...	...	@@ -57,10 +44,6 @@ pub const Feature = enum {
57	44	java,
58	45	mp,
59	46	mp1e2,
60		multiple_stld,
61		nvic,
62		pushpop,
63		smart,
64	47	soft_tp,
65	48	stack_size,
66	49	trust,
...	...	@@ -137,71 +120,6 @@ pub const all_features = blk: {
137	120	.description = "Enable cache",
138	121	.dependencies = featureSet(&[_]Feature{}),
139	122	};
140		result[@backingInt(Feature.ccrt)] = .{
141		.llvm_name = "ccrt",
142		.description = "Use CSKY compiler runtime",
143		.dependencies = featureSet(&[_]Feature{}),
144		};
145		result[@backingInt(Feature.ck801)] = .{
146		.llvm_name = "ck801",
147		.description = "CSKY ck801 processors",
148		.dependencies = featureSet(&[_]Feature{}),
149		};
150		result[@backingInt(Feature.ck802)] = .{
151		.llvm_name = "ck802",
152		.description = "CSKY ck802 processors",
153		.dependencies = featureSet(&[_]Feature{}),
154		};
155		result[@backingInt(Feature.ck803)] = .{
156		.llvm_name = "ck803",
157		.description = "CSKY ck803 processors",
158		.dependencies = featureSet(&[_]Feature{}),
159		};
160		result[@backingInt(Feature.ck803s)] = .{
161		.llvm_name = "ck803s",
162		.description = "CSKY ck803s processors",
163		.dependencies = featureSet(&[_]Feature{}),
164		};
165		result[@backingInt(Feature.ck804)] = .{
166		.llvm_name = "ck804",
167		.description = "CSKY ck804 processors",
168		.dependencies = featureSet(&[_]Feature{}),
169		};
170		result[@backingInt(Feature.ck805)] = .{
171		.llvm_name = "ck805",
172		.description = "CSKY ck805 processors",
173		.dependencies = featureSet(&[_]Feature{}),
174		};
175		result[@backingInt(Feature.ck807)] = .{
176		.llvm_name = "ck807",
177		.description = "CSKY ck807 processors",
178		.dependencies = featureSet(&[_]Feature{}),
179		};
180		result[@backingInt(Feature.ck810)] = .{
181		.llvm_name = "ck810",
182		.description = "CSKY ck810 processors",
183		.dependencies = featureSet(&[_]Feature{}),
184		};
185		result[@backingInt(Feature.ck810v)] = .{
186		.llvm_name = "ck810v",
187		.description = "CSKY ck810v processors",
188		.dependencies = featureSet(&[_]Feature{}),
189		};
190		result[@backingInt(Feature.ck860)] = .{
191		.llvm_name = "ck860",
192		.description = "CSKY ck860 processors",
193		.dependencies = featureSet(&[_]Feature{}),
194		};
195		result[@backingInt(Feature.ck860v)] = .{
196		.llvm_name = "ck860v",
197		.description = "CSKY ck860v processors",
198		.dependencies = featureSet(&[_]Feature{}),
199		};
200		result[@backingInt(Feature.constpool)] = .{
201		.llvm_name = "constpool",
202		.description = "Dump the constant pool by compiler",
203		.dependencies = featureSet(&[_]Feature{}),
204		};
205	123	result[@backingInt(Feature.doloop)] = .{
206	124	.llvm_name = "doloop",
207	125	.description = "Enable doloop instructions",
...	...	@@ -360,26 +278,6 @@ pub const all_features = blk: {
360	278	.@"3e7",
361	279	}),
362	280	};
363		result[@backingInt(Feature.multiple_stld)] = .{
364		.llvm_name = "multiple_stld",
365		.description = "Enable multiple load/store instructions",
366		.dependencies = featureSet(&[_]Feature{}),
367		};
368		result[@backingInt(Feature.nvic)] = .{
369		.llvm_name = "nvic",
370		.description = "Enable NVIC",
371		.dependencies = featureSet(&[_]Feature{}),
372		};
373		result[@backingInt(Feature.pushpop)] = .{
374		.llvm_name = "pushpop",
375		.description = "Enable push/pop instructions",
376		.dependencies = featureSet(&[_]Feature{}),
377		};
378		result[@backingInt(Feature.smart)] = .{
379		.llvm_name = "smart",
380		.description = "Let CPU work in Smart Mode",
381		.dependencies = featureSet(&[_]Feature{}),
382		};
383	281	result[@backingInt(Feature.soft_tp)] = .{
384	282	.llvm_name = "soft-tp",
385	283	.description = "Disable TLS Pointer register",
...	...	@@ -429,7 +327,6 @@ pub const cpu = struct {
429	327	.llvm_name = "c807",
430	328	.features = featureSet(&[_]Feature{
431	329	.cache,
432		.ck807,
433	330	.dsp1e2,
434	331	.dspe60,
435	332	.edsp,
...	...	@@ -438,7 +335,6 @@ pub const cpu = struct {
438	335	.hwdiv,
439	336	.mp,
440	337	.mp1e2,
441		.nvic,
442	338	.trust,
443	339	}),
444	340	};
...	...	@@ -447,7 +343,6 @@ pub const cpu = struct {
447	343	.llvm_name = "c807f",
448	344	.features = featureSet(&[_]Feature{
449	345	.cache,
450		.ck807,
451	346	.dsp1e2,
452	347	.dspe60,
453	348	.edsp,
...	...	@@ -463,7 +358,6 @@ pub const cpu = struct {
463	358	.hwdiv,
464	359	.mp,
465	360	.mp1e2,
466		.nvic,
467	361	.trust,
468	362	}),
469	363	};
...	...	@@ -473,7 +367,6 @@ pub const cpu = struct {
473	367	.features = featureSet(&[_]Feature{
474	368	.@"7e10",
475	369	.cache,
476		.ck810,
477	370	.dsp1e2,
478	371	.dspe60,
479	372	.edsp,
...	...	@@ -487,7 +380,6 @@ pub const cpu = struct {
487	380	.hwdiv,
488	381	.mp,
489	382	.mp1e2,
490		.nvic,
491	383	.trust,
492	384	}),
493	385	};
...	...	@@ -497,7 +389,6 @@ pub const cpu = struct {
497	389	.features = featureSet(&[_]Feature{
498	390	.@"7e10",
499	391	.cache,
500		.ck810,
501	392	.dsp1e2,
502	393	.dspe60,
503	394	.edsp,
...	...	@@ -511,7 +402,6 @@ pub const cpu = struct {
511	402	.hwdiv,
512	403	.mp,
513	404	.mp1e2,
514		.nvic,
515	405	.trust,
516	406	}),
517	407	};
...	...	@@ -521,8 +411,6 @@ pub const cpu = struct {
521	411	.features = featureSet(&[_]Feature{
522	412	.@"7e10",
523	413	.cache,
524		.ck810,
525		.ck810v,
526	414	.dsp1e2,
527	415	.dspe60,
528	416	.edsp,
...	...	@@ -536,7 +424,6 @@ pub const cpu = struct {
536	424	.hwdiv,
537	425	.mp,
538	426	.mp1e2,
539		.nvic,
540	427	.trust,
541	428	.vdspv1,
542	429	}),
...	...	@@ -547,8 +434,6 @@ pub const cpu = struct {
547	434	.features = featureSet(&[_]Feature{
548	435	.@"7e10",
549	436	.cache,
550		.ck810,
551		.ck810v,
552	437	.dsp1e2,
553	438	.dspe60,
554	439	.edsp,
...	...	@@ -562,7 +447,6 @@ pub const cpu = struct {
562	447	.hwdiv,
563	448	.mp,
564	449	.mp1e2,
565		.nvic,
566	450	.trust,
567	451	.vdspv1,
568	452	}),
...	...	@@ -576,7 +460,6 @@ pub const cpu = struct {
576	460	.@"3e3r3",
577	461	.btst16,
578	462	.cache,
579		.ck860,
580	463	.dspe60,
581	464	.float7e60,
582	465	.fpuv3_df,
...	...	@@ -588,7 +471,6 @@ pub const cpu = struct {
588	471	.hwdiv,
589	472	.mp,
590	473	.mp1e2,
591		.nvic,
592	474	.trust,
593	475	}),
594	476	};
...	...	@@ -601,8 +483,6 @@ pub const cpu = struct {
601	483	.@"3e3r3",
602	484	.btst16,
603	485	.cache,
604		.ck860,
605		.ck860v,
606	486	.dspe60,
607	487	.float7e60,
608	488	.fpuv3_df,
...	...	@@ -614,7 +494,6 @@ pub const cpu = struct {
614	494	.hwdiv,
615	495	.mp,
616	496	.mp1e2,
617		.nvic,
618	497	.trust,
619	498	.vdsp2e60f,
620	499	.vdspv2,
...	...	@@ -625,7 +504,6 @@ pub const cpu = struct {
625	504	.llvm_name = "ck801",
626	505	.features = featureSet(&[_]Feature{
627	506	.btst16,
628		.ck801,
629	507	.e1,
630	508	.trust,
631	509	}),
...	...	@@ -635,7 +513,6 @@ pub const cpu = struct {
635	513	.llvm_name = "ck801t",
636	514	.features = featureSet(&[_]Feature{
637	515	.btst16,
638		.ck801,
639	516	.e1,
640	517	.trust,
641	518	}),
...	...	@@ -645,9 +522,7 @@ pub const cpu = struct {
645	522	.llvm_name = "ck802",
646	523	.features = featureSet(&[_]Feature{
647	524	.btst16,
648		.ck802,
649	525	.e2,
650		.nvic,
651	526	.trust,
652	527	}),
653	528	};
...	...	@@ -656,10 +531,8 @@ pub const cpu = struct {
656	531	.llvm_name = "ck802j",
657	532	.features = featureSet(&[_]Feature{
658	533	.btst16,
659		.ck802,
660	534	.e2,
661	535	.java,
662		.nvic,
663	536	.trust,
664	537	}),
665	538	};
...	...	@@ -668,9 +541,7 @@ pub const cpu = struct {
668	541	.llvm_name = "ck802t",
669	542	.features = featureSet(&[_]Feature{
670	543	.btst16,
671		.ck802,
672	544	.e2,
673		.nvic,
674	545	.trust,
675	546	}),
676	547	};
...	...	@@ -679,10 +550,8 @@ pub const cpu = struct {
679	550	.llvm_name = "ck803",
680	551	.features = featureSet(&[_]Feature{
681	552	.btst16,
682		.ck803,
683	553	.hwdiv,
684	554	.mp,
685		.nvic,
686	555	.trust,
687	556	}),
688	557	};
...	...	@@ -691,13 +560,11 @@ pub const cpu = struct {
691	560	.llvm_name = "ck803e",
692	561	.features = featureSet(&[_]Feature{
693	562	.btst16,
694		.ck803,
695	563	.dsp1e2,
696	564	.dspe60,
697	565	.edsp,
698	566	.hwdiv,
699	567	.mp,
700		.nvic,
701	568	.trust,
702	569	}),
703	570	};
...	...	@@ -706,7 +573,6 @@ pub const cpu = struct {
706	573	.llvm_name = "ck803ef",
707	574	.features = featureSet(&[_]Feature{
708	575	.btst16,
709		.ck803,
710	576	.dsp1e2,
711	577	.dspe60,
712	578	.edsp,
...	...	@@ -715,7 +581,6 @@ pub const cpu = struct {
715	581	.fpuv2_sf,
716	582	.hwdiv,
717	583	.mp,
718		.nvic,
719	584	.trust,
720	585	}),
721	586	};
...	...	@@ -724,7 +589,6 @@ pub const cpu = struct {
724	589	.llvm_name = "ck803efh",
725	590	.features = featureSet(&[_]Feature{
726	591	.btst16,
727		.ck803,
728	592	.dsp1e2,
729	593	.dspe60,
730	594	.edsp,
...	...	@@ -733,7 +597,6 @@ pub const cpu = struct {
733	597	.fpuv2_sf,
734	598	.hwdiv,
735	599	.mp,
736		.nvic,
737	600	.trust,
738	601	}),
739	602	};
...	...	@@ -743,7 +606,6 @@ pub const cpu = struct {
743	606	.features = featureSet(&[_]Feature{
744	607	.@"3e3r1",
745	608	.btst16,
746		.ck803,
747	609	.dsp1e2,
748	610	.dspe60,
749	611	.dspv2,
...	...	@@ -754,7 +616,6 @@ pub const cpu = struct {
754	616	.high_registers,
755	617	.hwdiv,
756	618	.mp,
757		.nvic,
758	619	.trust,
759	620	}),
760	621	};
...	...	@@ -765,7 +626,6 @@ pub const cpu = struct {
765	626	.@"3e3r2",
766	627	.@"3e3r3",
767	628	.btst16,
768		.ck803,
769	629	.dsp1e2,
770	630	.dspe60,
771	631	.dspv2,
...	...	@@ -776,7 +636,6 @@ pub const cpu = struct {
776	636	.high_registers,
777	637	.hwdiv,
778	638	.mp,
779		.nvic,
780	639	.trust,
781	640	}),
782	641	};
...	...	@@ -787,7 +646,6 @@ pub const cpu = struct {
787	646	.@"3e3r2",
788	647	.@"3e3r3",
789	648	.btst16,
790		.ck803,
791	649	.dsp1e2,
792	650	.dspe60,
793	651	.dspv2,
...	...	@@ -798,7 +656,6 @@ pub const cpu = struct {
798	656	.high_registers,
799	657	.hwdiv,
800	658	.mp,
801		.nvic,
802	659	.trust,
803	660	}),
804	661	};
...	...	@@ -807,7 +664,6 @@ pub const cpu = struct {
807	664	.llvm_name = "ck803efht",
808	665	.features = featureSet(&[_]Feature{
809	666	.btst16,
810		.ck803,
811	667	.dsp1e2,
812	668	.dspe60,
813	669	.edsp,
...	...	@@ -816,7 +672,6 @@ pub const cpu = struct {
816	672	.fpuv2_sf,
817	673	.hwdiv,
818	674	.mp,
819		.nvic,
820	675	.trust,
821	676	}),
822	677	};
...	...	@@ -826,7 +681,6 @@ pub const cpu = struct {
826	681	.features = featureSet(&[_]Feature{
827	682	.@"3e3r1",
828	683	.btst16,
829		.ck803,
830	684	.dsp1e2,
831	685	.dspe60,
832	686	.dspv2,
...	...	@@ -837,7 +691,6 @@ pub const cpu = struct {
837	691	.high_registers,
838	692	.hwdiv,
839	693	.mp,
840		.nvic,
841	694	.trust,
842	695	}),
843	696	};
...	...	@@ -848,7 +701,6 @@ pub const cpu = struct {
848	701	.@"3e3r2",
849	702	.@"3e3r3",
850	703	.btst16,
851		.ck803,
852	704	.dsp1e2,
853	705	.dspe60,
854	706	.dspv2,
...	...	@@ -859,7 +711,6 @@ pub const cpu = struct {
859	711	.high_registers,
860	712	.hwdiv,
861	713	.mp,
862		.nvic,
863	714	.trust,
864	715	}),
865	716	};
...	...	@@ -870,7 +721,6 @@ pub const cpu = struct {
870	721	.@"3e3r2",
871	722	.@"3e3r3",
872	723	.btst16,
873		.ck803,
874	724	.dsp1e2,
875	725	.dspe60,
876	726	.dspv2,
...	...	@@ -881,7 +731,6 @@ pub const cpu = struct {
881	731	.high_registers,
882	732	.hwdiv,
883	733	.mp,
884		.nvic,
885	734	.trust,
886	735	}),
887	736	};
...	...	@@ -891,7 +740,6 @@ pub const cpu = struct {
891	740	.features = featureSet(&[_]Feature{
892	741	.@"3e3r1",
893	742	.btst16,
894		.ck803,
895	743	.dsp1e2,
896	744	.dspe60,
897	745	.dspv2,
...	...	@@ -902,7 +750,6 @@ pub const cpu = struct {
902	750	.high_registers,
903	751	.hwdiv,
904	752	.mp,
905		.nvic,
906	753	.trust,
907	754	}),
908	755	};
...	...	@@ -913,7 +760,6 @@ pub const cpu = struct {
913	760	.@"3e3r2",
914	761	.@"3e3r3",
915	762	.btst16,
916		.ck803,
917	763	.dsp1e2,
918	764	.dspe60,
919	765	.dspv2,
...	...	@@ -924,7 +770,6 @@ pub const cpu = struct {
924	770	.high_registers,
925	771	.hwdiv,
926	772	.mp,
927		.nvic,
928	773	.trust,
929	774	}),
930	775	};
...	...	@@ -935,7 +780,6 @@ pub const cpu = struct {
935	780	.@"3e3r2",
936	781	.@"3e3r3",
937	782	.btst16,
938		.ck803,
939	783	.dsp1e2,
940	784	.dspe60,
941	785	.dspv2,
...	...	@@ -946,7 +790,6 @@ pub const cpu = struct {
946	790	.high_registers,
947	791	.hwdiv,
948	792	.mp,
949		.nvic,
950	793	.trust,
951	794	}),
952	795	};
...	...	@@ -955,7 +798,6 @@ pub const cpu = struct {
955	798	.llvm_name = "ck803eft",
956	799	.features = featureSet(&[_]Feature{
957	800	.btst16,
958		.ck803,
959	801	.dsp1e2,
960	802	.dspe60,
961	803	.edsp,
...	...	@@ -964,7 +806,6 @@ pub const cpu = struct {
964	806	.fpuv2_sf,
965	807	.hwdiv,
966	808	.mp,
967		.nvic,
968	809	.trust,
969	810	}),
970	811	};
...	...	@@ -974,7 +815,6 @@ pub const cpu = struct {
974	815	.features = featureSet(&[_]Feature{
975	816	.@"3e3r1",
976	817	.btst16,
977		.ck803,
978	818	.dsp1e2,
979	819	.dspe60,
980	820	.dspv2,
...	...	@@ -985,7 +825,6 @@ pub const cpu = struct {
985	825	.high_registers,
986	826	.hwdiv,
987	827	.mp,
988		.nvic,
989	828	.trust,
990	829	}),
991	830	};
...	...	@@ -996,7 +835,6 @@ pub const cpu = struct {
996	835	.@"3e3r2",
997	836	.@"3e3r3",
998	837	.btst16,
999		.ck803,
1000	838	.dsp1e2,
1001	839	.dspe60,
1002	840	.dspv2,
...	...	@@ -1007,7 +845,6 @@ pub const cpu = struct {
1007	845	.high_registers,
1008	846	.hwdiv,
1009	847	.mp,
1010		.nvic,
1011	848	.trust,
1012	849	}),
1013	850	};
...	...	@@ -1018,7 +855,6 @@ pub const cpu = struct {
1018	855	.@"3e3r2",
1019	856	.@"3e3r3",
1020	857	.btst16,
1021		.ck803,
1022	858	.dsp1e2,
1023	859	.dspe60,
1024	860	.dspv2,
...	...	@@ -1029,7 +865,6 @@ pub const cpu = struct {
1029	865	.high_registers,
1030	866	.hwdiv,
1031	867	.mp,
1032		.nvic,
1033	868	.trust,
1034	869	}),
1035	870	};
...	...	@@ -1038,13 +873,11 @@ pub const cpu = struct {
1038	873	.llvm_name = "ck803eh",
1039	874	.features = featureSet(&[_]Feature{
1040	875	.btst16,
1041		.ck803,
1042	876	.dsp1e2,
1043	877	.dspe60,
1044	878	.edsp,
1045	879	.hwdiv,
1046	880	.mp,
1047		.nvic,
1048	881	.trust,
1049	882	}),
1050	883	};
...	...	@@ -1055,7 +888,6 @@ pub const cpu = struct {
1055	888	.@"3e3r1",
1056	889	.@"3e3r3",
1057	890	.btst16,
1058		.ck803,
1059	891	.dsp1e2,
1060	892	.dspe60,
1061	893	.dspv2,
...	...	@@ -1063,7 +895,6 @@ pub const cpu = struct {
1063	895	.high_registers,
1064	896	.hwdiv,
1065	897	.mp,
1066		.nvic,
1067	898	.trust,
1068	899	}),
1069	900	};
...	...	@@ -1074,7 +905,6 @@ pub const cpu = struct {
1074	905	.@"3e3r2",
1075	906	.@"3e3r3",
1076	907	.btst16,
1077		.ck803,
1078	908	.dsp1e2,
1079	909	.dspe60,
1080	910	.dspv2,
...	...	@@ -1082,7 +912,6 @@ pub const cpu = struct {
1082	912	.high_registers,
1083	913	.hwdiv,
1084	914	.mp,
1085		.nvic,
1086	915	.trust,
1087	916	}),
1088	917	};
...	...	@@ -1093,7 +922,6 @@ pub const cpu = struct {
1093	922	.@"3e3r2",
1094	923	.@"3e3r3",
1095	924	.btst16,
1096		.ck803,
1097	925	.dsp1e2,
1098	926	.dspe60,
1099	927	.dspv2,
...	...	@@ -1101,7 +929,6 @@ pub const cpu = struct {
1101	929	.high_registers,
1102	930	.hwdiv,
1103	931	.mp,
1104		.nvic,
1105	932	.trust,
1106	933	}),
1107	934	};
...	...	@@ -1110,13 +937,11 @@ pub const cpu = struct {
1110	937	.llvm_name = "ck803eht",
1111	938	.features = featureSet(&[_]Feature{
1112	939	.btst16,
1113		.ck803,
1114	940	.dsp1e2,
1115	941	.dspe60,
1116	942	.edsp,
1117	943	.hwdiv,
1118	944	.mp,
1119		.nvic,
1120	945	.trust,
1121	946	}),
1122	947	};
...	...	@@ -1127,7 +952,6 @@ pub const cpu = struct {
1127	952	.@"3e3r1",
1128	953	.@"3e3r3",
1129	954	.btst16,
1130		.ck803,
1131	955	.dsp1e2,
1132	956	.dspe60,
1133	957	.dspv2,
...	...	@@ -1135,7 +959,6 @@ pub const cpu = struct {
1135	959	.high_registers,
1136	960	.hwdiv,
1137	961	.mp,
1138		.nvic,
1139	962	.trust,
1140	963	}),
1141	964	};
...	...	@@ -1146,7 +969,6 @@ pub const cpu = struct {
1146	969	.@"3e3r2",
1147	970	.@"3e3r3",
1148	971	.btst16,
1149		.ck803,
1150	972	.dsp1e2,
1151	973	.dspe60,
1152	974	.dspv2,
...	...	@@ -1154,7 +976,6 @@ pub const cpu = struct {
1154	976	.high_registers,
1155	977	.hwdiv,
1156	978	.mp,
1157		.nvic,
1158	979	.trust,
1159	980	}),
1160	981	};
...	...	@@ -1165,7 +986,6 @@ pub const cpu = struct {
1165	986	.@"3e3r2",
1166	987	.@"3e3r3",
1167	988	.btst16,
1168		.ck803,
1169	989	.dsp1e2,
1170	990	.dspe60,
1171	991	.dspv2,
...	...	@@ -1173,7 +993,6 @@ pub const cpu = struct {
1173	993	.high_registers,
1174	994	.hwdiv,
1175	995	.mp,
1176		.nvic,
1177	996	.trust,
1178	997	}),
1179	998	};
...	...	@@ -1184,7 +1003,6 @@ pub const cpu = struct {
1184	1003	.@"3e3r1",
1185	1004	.@"3e3r3",
1186	1005	.btst16,
1187		.ck803,
1188	1006	.dsp1e2,
1189	1007	.dspe60,
1190	1008	.dspv2,
...	...	@@ -1192,7 +1010,6 @@ pub const cpu = struct {
1192	1010	.high_registers,
1193	1011	.hwdiv,
1194	1012	.mp,
1195		.nvic,
1196	1013	.trust,
1197	1014	}),
1198	1015	};
...	...	@@ -1203,7 +1020,6 @@ pub const cpu = struct {
1203	1020	.@"3e3r2",
1204	1021	.@"3e3r3",
1205	1022	.btst16,
1206		.ck803,
1207	1023	.dsp1e2,
1208	1024	.dspe60,
1209	1025	.dspv2,
...	...	@@ -1211,7 +1027,6 @@ pub const cpu = struct {
1211	1027	.high_registers,
1212	1028	.hwdiv,
1213	1029	.mp,
1214		.nvic,
1215	1030	.trust,
1216	1031	}),
1217	1032	};
...	...	@@ -1222,7 +1037,6 @@ pub const cpu = struct {
1222	1037	.@"3e3r2",
1223	1038	.@"3e3r3",
1224	1039	.btst16,
1225		.ck803,
1226	1040	.dsp1e2,
1227	1041	.dspe60,
1228	1042	.dspv2,
...	...	@@ -1230,7 +1044,6 @@ pub const cpu = struct {
1230	1044	.high_registers,
1231	1045	.hwdiv,
1232	1046	.mp,
1233		.nvic,
1234	1047	.trust,
1235	1048	}),
1236	1049	};
...	...	@@ -1239,13 +1052,11 @@ pub const cpu = struct {
1239	1052	.llvm_name = "ck803et",
1240	1053	.features = featureSet(&[_]Feature{
1241	1054	.btst16,
1242		.ck803,
1243	1055	.dsp1e2,
1244	1056	.dspe60,
1245	1057	.edsp,
1246	1058	.hwdiv,
1247	1059	.mp,
1248		.nvic,
1249	1060	.trust,
1250	1061	}),
1251	1062	};
...	...	@@ -1256,7 +1067,6 @@ pub const cpu = struct {
1256	1067	.@"3e3r1",
1257	1068	.@"3e3r3",
1258	1069	.btst16,
1259		.ck803,
1260	1070	.dsp1e2,
1261	1071	.dspe60,
1262	1072	.dspv2,
...	...	@@ -1264,7 +1074,6 @@ pub const cpu = struct {
1264	1074	.high_registers,
1265	1075	.hwdiv,
1266	1076	.mp,
1267		.nvic,
1268	1077	.trust,
1269	1078	}),
1270	1079	};
...	...	@@ -1275,7 +1084,6 @@ pub const cpu = struct {
1275	1084	.@"3e3r2",
1276	1085	.@"3e3r3",
1277	1086	.btst16,
1278		.ck803,
1279	1087	.dsp1e2,
1280	1088	.dspe60,
1281	1089	.dspv2,
...	...	@@ -1283,7 +1091,6 @@ pub const cpu = struct {
1283	1091	.high_registers,
1284	1092	.hwdiv,
1285	1093	.mp,
1286		.nvic,
1287	1094	.trust,
1288	1095	}),
1289	1096	};
...	...	@@ -1294,7 +1101,6 @@ pub const cpu = struct {
1294	1101	.@"3e3r2",
1295	1102	.@"3e3r3",
1296	1103	.btst16,
1297		.ck803,
1298	1104	.dsp1e2,
1299	1105	.dspe60,
1300	1106	.dspv2,
...	...	@@ -1302,7 +1108,6 @@ pub const cpu = struct {
1302	1108	.high_registers,
1303	1109	.hwdiv,
1304	1110	.mp,
1305		.nvic,
1306	1111	.trust,
1307	1112	}),
1308	1113	};
...	...	@@ -1311,13 +1116,11 @@ pub const cpu = struct {
1311	1116	.llvm_name = "ck803f",
1312	1117	.features = featureSet(&[_]Feature{
1313	1118	.btst16,
1314		.ck803,
1315	1119	.float1e3,
1316	1120	.floate1,
1317	1121	.fpuv2_sf,
1318	1122	.hwdiv,
1319	1123	.mp,
1320		.nvic,
1321	1124	.trust,
1322	1125	}),
1323	1126	};
...	...	@@ -1326,13 +1129,11 @@ pub const cpu = struct {
1326	1129	.llvm_name = "ck803fh",
1327	1130	.features = featureSet(&[_]Feature{
1328	1131	.btst16,
1329		.ck803,
1330	1132	.float1e3,
1331	1133	.floate1,
1332	1134	.fpuv2_sf,
1333	1135	.hwdiv,
1334	1136	.mp,
1335		.nvic,
1336	1137	.trust,
1337	1138	}),
1338	1139	};
...	...	@@ -1343,14 +1144,12 @@ pub const cpu = struct {
1343	1144	.@"3e3r1",
1344	1145	.@"3e3r3",
1345	1146	.btst16,
1346		.ck803,
1347	1147	.dspv2,
1348	1148	.float1e3,
1349	1149	.floate1,
1350	1150	.fpuv2_sf,
1351	1151	.hwdiv,
1352	1152	.mp,
1353		.nvic,
1354	1153	.trust,
1355	1154	}),
1356	1155	};
...	...	@@ -1361,14 +1160,12 @@ pub const cpu = struct {
1361	1160	.@"3e3r2",
1362	1161	.@"3e3r3",
1363	1162	.btst16,
1364		.ck803,
1365	1163	.dspv2,
1366	1164	.float1e3,
1367	1165	.floate1,
1368	1166	.fpuv2_sf,
1369	1167	.hwdiv,
1370	1168	.mp,
1371		.nvic,
1372	1169	.trust,
1373	1170	}),
1374	1171	};
...	...	@@ -1379,14 +1176,12 @@ pub const cpu = struct {
1379	1176	.@"3e3r2",
1380	1177	.@"3e3r3",
1381	1178	.btst16,
1382		.ck803,
1383	1179	.dspv2,
1384	1180	.float1e3,
1385	1181	.floate1,
1386	1182	.fpuv2_sf,
1387	1183	.hwdiv,
1388	1184	.mp,
1389		.nvic,
1390	1185	.trust,
1391	1186	}),
1392	1187	};
...	...	@@ -1397,14 +1192,12 @@ pub const cpu = struct {
1397	1192	.@"3e3r1",
1398	1193	.@"3e3r3",
1399	1194	.btst16,
1400		.ck803,
1401	1195	.dspv2,
1402	1196	.float1e3,
1403	1197	.floate1,
1404	1198	.fpuv2_sf,
1405	1199	.hwdiv,
1406	1200	.mp,
1407		.nvic,
1408	1201	.trust,
1409	1202	}),
1410	1203	};
...	...	@@ -1415,14 +1208,12 @@ pub const cpu = struct {
1415	1208	.@"3e3r2",
1416	1209	.@"3e3r3",
1417	1210	.btst16,
1418		.ck803,
1419	1211	.dspv2,
1420	1212	.float1e3,
1421	1213	.floate1,
1422	1214	.fpuv2_sf,
1423	1215	.hwdiv,
1424	1216	.mp,
1425		.nvic,
1426	1217	.trust,
1427	1218	}),
1428	1219	};
...	...	@@ -1433,14 +1224,12 @@ pub const cpu = struct {
1433	1224	.@"3e3r2",
1434	1225	.@"3e3r3",
1435	1226	.btst16,
1436		.ck803,
1437	1227	.dspv2,
1438	1228	.float1e3,
1439	1229	.floate1,
1440	1230	.fpuv2_sf,
1441	1231	.hwdiv,
1442	1232	.mp,
1443		.nvic,
1444	1233	.trust,
1445	1234	}),
1446	1235	};
...	...	@@ -1449,13 +1238,11 @@ pub const cpu = struct {
1449	1238	.llvm_name = "ck803ft",
1450	1239	.features = featureSet(&[_]Feature{
1451	1240	.btst16,
1452		.ck803,
1453	1241	.float1e3,
1454	1242	.floate1,
1455	1243	.fpuv2_sf,
1456	1244	.hwdiv,
1457	1245	.mp,
1458		.nvic,
1459	1246	.trust,
1460	1247	}),
1461	1248	};
...	...	@@ -1465,14 +1252,12 @@ pub const cpu = struct {
1465	1252	.features = featureSet(&[_]Feature{
1466	1253	.@"3e3r1",
1467	1254	.btst16,
1468		.ck803,
1469	1255	.dspv2,
1470	1256	.float1e3,
1471	1257	.floate1,
1472	1258	.fpuv2_sf,
1473	1259	.hwdiv,
1474	1260	.mp,
1475		.nvic,
1476	1261	.trust,
1477	1262	}),
1478	1263	};
...	...	@@ -1483,14 +1268,12 @@ pub const cpu = struct {
1483	1268	.@"3e3r2",
1484	1269	.@"3e3r3",
1485	1270	.btst16,
1486		.ck803,
1487	1271	.dspv2,
1488	1272	.float1e3,
1489	1273	.floate1,
1490	1274	.fpuv2_sf,
1491	1275	.hwdiv,
1492	1276	.mp,
1493		.nvic,
1494	1277	.trust,
1495	1278	}),
1496	1279	};
...	...	@@ -1501,14 +1284,12 @@ pub const cpu = struct {
1501	1284	.@"3e3r2",
1502	1285	.@"3e3r3",
1503	1286	.btst16,
1504		.ck803,
1505	1287	.dspv2,
1506	1288	.float1e3,
1507	1289	.floate1,
1508	1290	.fpuv2_sf,
1509	1291	.hwdiv,
1510	1292	.mp,
1511		.nvic,
1512	1293	.trust,
1513	1294	}),
1514	1295	};
...	...	@@ -1517,10 +1298,8 @@ pub const cpu = struct {
1517	1298	.llvm_name = "ck803h",
1518	1299	.features = featureSet(&[_]Feature{
1519	1300	.btst16,
1520		.ck803,
1521	1301	.hwdiv,
1522	1302	.mp,
1523		.nvic,
1524	1303	.trust,
1525	1304	}),
1526	1305	};
...	...	@@ -1531,11 +1310,9 @@ pub const cpu = struct {
1531	1310	.@"3e3r1",
1532	1311	.@"3e3r3",
1533	1312	.btst16,
1534		.ck803,
1535	1313	.dspv2,
1536	1314	.hwdiv,
1537	1315	.mp,
1538		.nvic,
1539	1316	.trust,
1540	1317	}),
1541	1318	};
...	...	@@ -1546,11 +1323,9 @@ pub const cpu = struct {
1546	1323	.@"3e3r2",
1547	1324	.@"3e3r3",
1548	1325	.btst16,
1549		.ck803,
1550	1326	.dspv2,
1551	1327	.hwdiv,
1552	1328	.mp,
1553		.nvic,
1554	1329	.trust,
1555	1330	}),
1556	1331	};
...	...	@@ -1561,11 +1336,9 @@ pub const cpu = struct {
1561	1336	.@"3e3r2",
1562	1337	.@"3e3r3",
1563	1338	.btst16,
1564		.ck803,
1565	1339	.dspv2,
1566	1340	.hwdiv,
1567	1341	.mp,
1568		.nvic,
1569	1342	.trust,
1570	1343	}),
1571	1344	};
...	...	@@ -1574,10 +1347,8 @@ pub const cpu = struct {
1574	1347	.llvm_name = "ck803ht",
1575	1348	.features = featureSet(&[_]Feature{
1576	1349	.btst16,
1577		.ck803,
1578	1350	.hwdiv,
1579	1351	.mp,
1580		.nvic,
1581	1352	.trust,
1582	1353	}),
1583	1354	};
...	...	@@ -1588,11 +1359,9 @@ pub const cpu = struct {
1588	1359	.@"3e3r1",
1589	1360	.@"3e3r3",
1590	1361	.btst16,
1591		.ck803,
1592	1362	.dspv2,
1593	1363	.hwdiv,
1594	1364	.mp,
1595		.nvic,
1596	1365	.trust,
1597	1366	}),
1598	1367	};
...	...	@@ -1603,11 +1372,9 @@ pub const cpu = struct {
1603	1372	.@"3e3r2",
1604	1373	.@"3e3r3",
1605	1374	.btst16,
1606		.ck803,
1607	1375	.dspv2,
1608	1376	.hwdiv,
1609	1377	.mp,
1610		.nvic,
1611	1378	.trust,
1612	1379	}),
1613	1380	};
...	...	@@ -1618,11 +1385,9 @@ pub const cpu = struct {
1618	1385	.@"3e3r2",
1619	1386	.@"3e3r3",
1620	1387	.btst16,
1621		.ck803,
1622	1388	.dspv2,
1623	1389	.hwdiv,
1624	1390	.mp,
1625		.nvic,
1626	1391	.trust,
1627	1392	}),
1628	1393	};
...	...	@@ -1633,11 +1398,9 @@ pub const cpu = struct {
1633	1398	.@"3e3r1",
1634	1399	.@"3e3r3",
1635	1400	.btst16,
1636		.ck803,
1637	1401	.dspv2,
1638	1402	.hwdiv,
1639	1403	.mp,
1640		.nvic,
1641	1404	.trust,
1642	1405	}),
1643	1406	};
...	...	@@ -1648,11 +1411,9 @@ pub const cpu = struct {
1648	1411	.@"3e3r2",
1649	1412	.@"3e3r3",
1650	1413	.btst16,
1651		.ck803,
1652	1414	.dspv2,
1653	1415	.hwdiv,
1654	1416	.mp,
1655		.nvic,
1656	1417	.trust,
1657	1418	}),
1658	1419	};
...	...	@@ -1663,11 +1424,9 @@ pub const cpu = struct {
1663	1424	.@"3e3r2",
1664	1425	.@"3e3r3",
1665	1426	.btst16,
1666		.ck803,
1667	1427	.dspv2,
1668	1428	.hwdiv,
1669	1429	.mp,
1670		.nvic,
1671	1430	.trust,
1672	1431	}),
1673	1432	};
...	...	@@ -1677,11 +1436,8 @@ pub const cpu = struct {
1677	1436	.features = featureSet(&[_]Feature{
1678	1437	.@"3e3r1",
1679	1438	.btst16,
1680		.ck803,
1681		.ck803s,
1682	1439	.hwdiv,
1683	1440	.mp,
1684		.nvic,
1685	1441	.trust,
1686	1442	}),
1687	1443	};
...	...	@@ -1691,14 +1447,11 @@ pub const cpu = struct {
1691	1447	.features = featureSet(&[_]Feature{
1692	1448	.@"3e3r1",
1693	1449	.btst16,
1694		.ck803,
1695		.ck803s,
1696	1450	.dsp1e2,
1697	1451	.dspe60,
1698	1452	.edsp,
1699	1453	.hwdiv,
1700	1454	.mp,
1701		.nvic,
1702	1455	.trust,
1703	1456	}),
1704	1457	};
...	...	@@ -1708,8 +1461,6 @@ pub const cpu = struct {
1708	1461	.features = featureSet(&[_]Feature{
1709	1462	.@"3e3r1",
1710	1463	.btst16,
1711		.ck803,
1712		.ck803s,
1713	1464	.dsp1e2,
1714	1465	.dspe60,
1715	1466	.edsp,
...	...	@@ -1718,7 +1469,6 @@ pub const cpu = struct {
1718	1469	.fpuv2_sf,
1719	1470	.hwdiv,
1720	1471	.mp,
1721		.nvic,
1722	1472	.trust,
1723	1473	}),
1724	1474	};
...	...	@@ -1728,8 +1478,6 @@ pub const cpu = struct {
1728	1478	.features = featureSet(&[_]Feature{
1729	1479	.@"3e3r1",
1730	1480	.btst16,
1731		.ck803,
1732		.ck803s,
1733	1481	.dsp1e2,
1734	1482	.dsp_silan,
1735	1483	.dspe60,
...	...	@@ -1739,7 +1487,6 @@ pub const cpu = struct {
1739	1487	.fpuv2_sf,
1740	1488	.hwdiv,
1741	1489	.mp,
1742		.nvic,
1743	1490	.trust,
1744	1491	}),
1745	1492	};
...	...	@@ -1749,8 +1496,6 @@ pub const cpu = struct {
1749	1496	.features = featureSet(&[_]Feature{
1750	1497	.@"3e3r1",
1751	1498	.btst16,
1752		.ck803,
1753		.ck803s,
1754	1499	.dsp1e2,
1755	1500	.dsp_silan,
1756	1501	.dspe60,
...	...	@@ -1760,7 +1505,6 @@ pub const cpu = struct {
1760	1505	.fpuv2_sf,
1761	1506	.hwdiv,
1762	1507	.mp,
1763		.nvic,
1764	1508	.trust,
1765	1509	}),
1766	1510	};
...	...	@@ -1770,8 +1514,6 @@ pub const cpu = struct {
1770	1514	.features = featureSet(&[_]Feature{
1771	1515	.@"3e3r1",
1772	1516	.btst16,
1773		.ck803,
1774		.ck803s,
1775	1517	.dsp1e2,
1776	1518	.dspe60,
1777	1519	.edsp,
...	...	@@ -1780,7 +1522,6 @@ pub const cpu = struct {
1780	1522	.fpuv2_sf,
1781	1523	.hwdiv,
1782	1524	.mp,
1783		.nvic,
1784	1525	.trust,
1785	1526	}),
1786	1527	};
...	...	@@ -1790,15 +1531,12 @@ pub const cpu = struct {
1790	1531	.features = featureSet(&[_]Feature{
1791	1532	.@"3e3r1",
1792	1533	.btst16,
1793		.ck803,
1794		.ck803s,
1795	1534	.dsp1e2,
1796	1535	.dsp_silan,
1797	1536	.dspe60,
1798	1537	.edsp,
1799	1538	.hwdiv,
1800	1539	.mp,
1801		.nvic,
1802	1540	.trust,
1803	1541	}),
1804	1542	};
...	...	@@ -1808,14 +1546,11 @@ pub const cpu = struct {
1808	1546	.features = featureSet(&[_]Feature{
1809	1547	.@"3e3r1",
1810	1548	.btst16,
1811		.ck803,
1812		.ck803s,
1813	1549	.float1e3,
1814	1550	.floate1,
1815	1551	.fpuv2_sf,
1816	1552	.hwdiv,
1817	1553	.mp,
1818		.nvic,
1819	1554	.trust,
1820	1555	}),
1821	1556	};
...	...	@@ -1825,15 +1560,12 @@ pub const cpu = struct {
1825	1560	.features = featureSet(&[_]Feature{
1826	1561	.@"3e3r1",
1827	1562	.btst16,
1828		.ck803,
1829		.ck803s,
1830	1563	.dsp_silan,
1831	1564	.float1e3,
1832	1565	.floate1,
1833	1566	.fpuv2_sf,
1834	1567	.hwdiv,
1835	1568	.mp,
1836		.nvic,
1837	1569	.trust,
1838	1570	}),
1839	1571	};
...	...	@@ -1843,12 +1575,9 @@ pub const cpu = struct {
1843	1575	.features = featureSet(&[_]Feature{
1844	1576	.@"3e3r1",
1845	1577	.btst16,
1846		.ck803,
1847		.ck803s,
1848	1578	.dsp_silan,
1849	1579	.hwdiv,
1850	1580	.mp,
1851		.nvic,
1852	1581	.trust,
1853	1582	}),
1854	1583	};
...	...	@@ -1858,12 +1587,9 @@ pub const cpu = struct {
1858	1587	.features = featureSet(&[_]Feature{
1859	1588	.@"3e3r1",
1860	1589	.btst16,
1861		.ck803,
1862		.ck803s,
1863	1590	.dsp_silan,
1864	1591	.hwdiv,
1865	1592	.mp,
1866		.nvic,
1867	1593	.trust,
1868	1594	}),
1869	1595	};
...	...	@@ -1873,11 +1599,8 @@ pub const cpu = struct {
1873	1599	.features = featureSet(&[_]Feature{
1874	1600	.@"3e3r1",
1875	1601	.btst16,
1876		.ck803,
1877		.ck803s,
1878	1602	.hwdiv,
1879	1603	.mp,
1880		.nvic,
1881	1604	.trust,
1882	1605	}),
1883	1606	};
...	...	@@ -1886,10 +1609,8 @@ pub const cpu = struct {
1886	1609	.llvm_name = "ck803t",
1887	1610	.features = featureSet(&[_]Feature{
1888	1611	.btst16,
1889		.ck803,
1890	1612	.hwdiv,
1891	1613	.mp,
1892		.nvic,
1893	1614	.trust,
1894	1615	}),
1895	1616	};
...	...	@@ -1900,11 +1621,9 @@ pub const cpu = struct {
1900	1621	.@"3e3r1",
1901	1622	.@"3e3r3",
1902	1623	.btst16,
1903		.ck803,
1904	1624	.dspv2,
1905	1625	.hwdiv,
1906	1626	.mp,
1907		.nvic,
1908	1627	.trust,
1909	1628	}),
1910	1629	};
...	...	@@ -1915,11 +1634,9 @@ pub const cpu = struct {
1915	1634	.@"3e3r2",
1916	1635	.@"3e3r3",
1917	1636	.btst16,
1918		.ck803,
1919	1637	.dspv2,
1920	1638	.hwdiv,
1921	1639	.mp,
1922		.nvic,
1923	1640	.trust,
1924	1641	}),
1925	1642	};
...	...	@@ -1930,11 +1647,9 @@ pub const cpu = struct {
1930	1647	.@"3e3r2",
1931	1648	.@"3e3r3",
1932	1649	.btst16,
1933		.ck803,
1934	1650	.dspv2,
1935	1651	.hwdiv,
1936	1652	.mp,
1937		.nvic,
1938	1653	.trust,
1939	1654	}),
1940	1655	};
...	...	@@ -1945,11 +1660,8 @@ pub const cpu = struct {
1945	1660	.@"3e3r2",
1946	1661	.@"3e3r3",
1947	1662	.btst16,
1948		.ck803,
1949		.ck804,
1950	1663	.hwdiv,
1951	1664	.mp,
1952		.nvic,
1953	1665	.trust,
1954	1666	}),
1955	1667	};
...	...	@@ -1960,13 +1672,10 @@ pub const cpu = struct {
1960	1672	.@"3e3r2",
1961	1673	.@"3e3r3",
1962	1674	.btst16,
1963		.ck803,
1964		.ck804,
1965	1675	.dspv2,
1966	1676	.high_registers,
1967	1677	.hwdiv,
1968	1678	.mp,
1969		.nvic,
1970	1679	.trust,
1971	1680	}),
1972	1681	};
...	...	@@ -1977,8 +1686,6 @@ pub const cpu = struct {
1977	1686	.@"3e3r2",
1978	1687	.@"3e3r3",
1979	1688	.btst16,
1980		.ck803,
1981		.ck804,
1982	1689	.dspv2,
1983	1690	.float1e3,
1984	1691	.floate1,
...	...	@@ -1986,7 +1693,6 @@ pub const cpu = struct {
1986	1693	.high_registers,
1987	1694	.hwdiv,
1988	1695	.mp,
1989		.nvic,
1990	1696	.trust,
1991	1697	}),
1992	1698	};
...	...	@@ -1997,8 +1703,6 @@ pub const cpu = struct {
1997	1703	.@"3e3r2",
1998	1704	.@"3e3r3",
1999	1705	.btst16,
2000		.ck803,
2001		.ck804,
2002	1706	.dspv2,
2003	1707	.float1e3,
2004	1708	.floate1,
...	...	@@ -2006,7 +1710,6 @@ pub const cpu = struct {
2006	1710	.high_registers,
2007	1711	.hwdiv,
2008	1712	.mp,
2009		.nvic,
2010	1713	.trust,
2011	1714	}),
2012	1715	};
...	...	@@ -2017,8 +1720,6 @@ pub const cpu = struct {
2017	1720	.@"3e3r2",
2018	1721	.@"3e3r3",
2019	1722	.btst16,
2020		.ck803,
2021		.ck804,
2022	1723	.dspv2,
2023	1724	.float1e3,
2024	1725	.floate1,
...	...	@@ -2026,7 +1727,6 @@ pub const cpu = struct {
2026	1727	.high_registers,
2027	1728	.hwdiv,
2028	1729	.mp,
2029		.nvic,
2030	1730	.trust,
2031	1731	}),
2032	1732	};
...	...	@@ -2037,8 +1737,6 @@ pub const cpu = struct {
2037	1737	.@"3e3r2",
2038	1738	.@"3e3r3",
2039	1739	.btst16,
2040		.ck803,
2041		.ck804,
2042	1740	.dspv2,
2043	1741	.float1e3,
2044	1742	.floate1,
...	...	@@ -2046,7 +1744,6 @@ pub const cpu = struct {
2046	1744	.high_registers,
2047	1745	.hwdiv,
2048	1746	.mp,
2049		.nvic,
2050	1747	.trust,
2051	1748	}),
2052	1749	};
...	...	@@ -2057,13 +1754,10 @@ pub const cpu = struct {
2057	1754	.@"3e3r2",
2058	1755	.@"3e3r3",
2059	1756	.btst16,
2060		.ck803,
2061		.ck804,
2062	1757	.dspv2,
2063	1758	.high_registers,
2064	1759	.hwdiv,
2065	1760	.mp,
2066		.nvic,
2067	1761	.trust,
2068	1762	}),
2069	1763	};
...	...	@@ -2074,13 +1768,10 @@ pub const cpu = struct {
2074	1768	.@"3e3r2",
2075	1769	.@"3e3r3",
2076	1770	.btst16,
2077		.ck803,
2078		.ck804,
2079	1771	.dspv2,
2080	1772	.high_registers,
2081	1773	.hwdiv,
2082	1774	.mp,
2083		.nvic,
2084	1775	.trust,
2085	1776	}),
2086	1777	};
...	...	@@ -2091,13 +1782,10 @@ pub const cpu = struct {
2091	1782	.@"3e3r2",
2092	1783	.@"3e3r3",
2093	1784	.btst16,
2094		.ck803,
2095		.ck804,
2096	1785	.dspv2,
2097	1786	.high_registers,
2098	1787	.hwdiv,
2099	1788	.mp,
2100		.nvic,
2101	1789	.trust,
2102	1790	}),
2103	1791	};
...	...	@@ -2108,14 +1796,11 @@ pub const cpu = struct {
2108	1796	.@"3e3r2",
2109	1797	.@"3e3r3",
2110	1798	.btst16,
2111		.ck803,
2112		.ck804,
2113	1799	.float1e3,
2114	1800	.floate1,
2115	1801	.fpuv2_sf,
2116	1802	.hwdiv,
2117	1803	.mp,
2118		.nvic,
2119	1804	.trust,
2120	1805	}),
2121	1806	};
...	...	@@ -2126,14 +1811,11 @@ pub const cpu = struct {
2126	1811	.@"3e3r2",
2127	1812	.@"3e3r3",
2128	1813	.btst16,
2129		.ck803,
2130		.ck804,
2131	1814	.float1e3,
2132	1815	.floate1,
2133	1816	.fpuv2_sf,
2134	1817	.hwdiv,
2135	1818	.mp,
2136		.nvic,
2137	1819	.trust,
2138	1820	}),
2139	1821	};
...	...	@@ -2144,14 +1826,11 @@ pub const cpu = struct {
2144	1826	.@"3e3r2",
2145	1827	.@"3e3r3",
2146	1828	.btst16,
2147		.ck803,
2148		.ck804,
2149	1829	.float1e3,
2150	1830	.floate1,
2151	1831	.fpuv2_sf,
2152	1832	.hwdiv,
2153	1833	.mp,
2154		.nvic,
2155	1834	.trust,
2156	1835	}),
2157	1836	};
...	...	@@ -2162,11 +1841,8 @@ pub const cpu = struct {
2162	1841	.@"3e3r2",
2163	1842	.@"3e3r3",
2164	1843	.btst16,
2165		.ck803,
2166		.ck804,
2167	1844	.hwdiv,
2168	1845	.mp,
2169		.nvic,
2170	1846	.trust,
2171	1847	}),
2172	1848	};
...	...	@@ -2177,11 +1853,8 @@ pub const cpu = struct {
2177	1853	.@"3e3r2",
2178	1854	.@"3e3r3",
2179	1855	.btst16,
2180		.ck803,
2181		.ck804,
2182	1856	.hwdiv,
2183	1857	.mp,
2184		.nvic,
2185	1858	.trust,
2186	1859	}),
2187	1860	};
...	...	@@ -2192,11 +1865,8 @@ pub const cpu = struct {
2192	1865	.@"3e3r2",
2193	1866	.@"3e3r3",
2194	1867	.btst16,
2195		.ck803,
2196		.ck804,
2197	1868	.hwdiv,
2198	1869	.mp,
2199		.nvic,
2200	1870	.trust,
2201	1871	}),
2202	1872	};
...	...	@@ -2207,12 +1877,9 @@ pub const cpu = struct {
2207	1877	.@"3e3r2",
2208	1878	.@"3e3r3",
2209	1879	.btst16,
2210		.ck803,
2211		.ck805,
2212	1880	.high_registers,
2213	1881	.hwdiv,
2214	1882	.mp,
2215		.nvic,
2216	1883	.trust,
2217	1884	.vdsp2e3,
2218	1885	.vdspv2,
...	...	@@ -2225,13 +1892,10 @@ pub const cpu = struct {
2225	1892	.@"3e3r2",
2226	1893	.@"3e3r3",
2227	1894	.btst16,
2228		.ck803,
2229		.ck805,
2230	1895	.dspv2,
2231	1896	.high_registers,
2232	1897	.hwdiv,
2233	1898	.mp,
2234		.nvic,
2235	1899	.trust,
2236	1900	.vdsp2e3,
2237	1901	.vdspv2,
...	...	@@ -2244,8 +1908,6 @@ pub const cpu = struct {
2244	1908	.@"3e3r2",
2245	1909	.@"3e3r3",
2246	1910	.btst16,
2247		.ck803,
2248		.ck805,
2249	1911	.dspv2,
2250	1912	.float1e3,
2251	1913	.floate1,
...	...	@@ -2253,7 +1915,6 @@ pub const cpu = struct {
2253	1915	.high_registers,
2254	1916	.hwdiv,
2255	1917	.mp,
2256		.nvic,
2257	1918	.trust,
2258	1919	.vdsp2e3,
2259	1920	.vdspv2,
...	...	@@ -2266,8 +1927,6 @@ pub const cpu = struct {
2266	1927	.@"3e3r2",
2267	1928	.@"3e3r3",
2268	1929	.btst16,
2269		.ck803,
2270		.ck805,
2271	1930	.dspv2,
2272	1931	.float1e3,
2273	1932	.floate1,
...	...	@@ -2275,7 +1934,6 @@ pub const cpu = struct {
2275	1934	.high_registers,
2276	1935	.hwdiv,
2277	1936	.mp,
2278		.nvic,
2279	1937	.trust,
2280	1938	.vdsp2e3,
2281	1939	.vdspv2,
...	...	@@ -2288,13 +1946,10 @@ pub const cpu = struct {
2288	1946	.@"3e3r2",
2289	1947	.@"3e3r3",
2290	1948	.btst16,
2291		.ck803,
2292		.ck805,
2293	1949	.dspv2,
2294	1950	.high_registers,
2295	1951	.hwdiv,
2296	1952	.mp,
2297		.nvic,
2298	1953	.trust,
2299	1954	.vdsp2e3,
2300	1955	.vdspv2,
...	...	@@ -2307,15 +1962,12 @@ pub const cpu = struct {
2307	1962	.@"3e3r2",
2308	1963	.@"3e3r3",
2309	1964	.btst16,
2310		.ck803,
2311		.ck805,
2312	1965	.float1e3,
2313	1966	.floate1,
2314	1967	.fpuv2_sf,
2315	1968	.high_registers,
2316	1969	.hwdiv,
2317	1970	.mp,
2318		.nvic,
2319	1971	.trust,
2320	1972	.vdsp2e3,
2321	1973	.vdspv2,
...	...	@@ -2328,15 +1980,12 @@ pub const cpu = struct {
2328	1980	.@"3e3r2",
2329	1981	.@"3e3r3",
2330	1982	.btst16,
2331		.ck803,
2332		.ck805,
2333	1983	.float1e3,
2334	1984	.floate1,
2335	1985	.fpuv2_sf,
2336	1986	.high_registers,
2337	1987	.hwdiv,
2338	1988	.mp,
2339		.nvic,
2340	1989	.trust,
2341	1990	.vdsp2e3,
2342	1991	.vdspv2,
...	...	@@ -2349,12 +1998,9 @@ pub const cpu = struct {
2349	1998	.@"3e3r2",
2350	1999	.@"3e3r3",
2351	2000	.btst16,
2352		.ck803,
2353		.ck805,
2354	2001	.high_registers,
2355	2002	.hwdiv,
2356	2003	.mp,
2357		.nvic,
2358	2004	.trust,
2359	2005	.vdsp2e3,
2360	2006	.vdspv2,
...	...	@@ -2365,7 +2011,6 @@ pub const cpu = struct {
2365	2011	.llvm_name = "ck807",
2366	2012	.features = featureSet(&[_]Feature{
2367	2013	.cache,
2368		.ck807,
2369	2014	.dsp1e2,
2370	2015	.dspe60,
2371	2016	.edsp,
...	...	@@ -2374,7 +2019,6 @@ pub const cpu = struct {
2374	2019	.hwdiv,
2375	2020	.mp,
2376	2021	.mp1e2,
2377		.nvic,
2378	2022	.trust,
2379	2023	}),
2380	2024	};
...	...	@@ -2383,7 +2027,6 @@ pub const cpu = struct {
2383	2027	.llvm_name = "ck807e",
2384	2028	.features = featureSet(&[_]Feature{
2385	2029	.cache,
2386		.ck807,
2387	2030	.dsp1e2,
2388	2031	.dspe60,
2389	2032	.edsp,
...	...	@@ -2392,7 +2035,6 @@ pub const cpu = struct {
2392	2035	.hwdiv,
2393	2036	.mp,
2394	2037	.mp1e2,
2395		.nvic,
2396	2038	.trust,
2397	2039	}),
2398	2040	};
...	...	@@ -2401,7 +2043,6 @@ pub const cpu = struct {
2401	2043	.llvm_name = "ck807ef",
2402	2044	.features = featureSet(&[_]Feature{
2403	2045	.cache,
2404		.ck807,
2405	2046	.dsp1e2,
2406	2047	.dspe60,
2407	2048	.edsp,
...	...	@@ -2417,7 +2058,6 @@ pub const cpu = struct {
2417	2058	.hwdiv,
2418	2059	.mp,
2419	2060	.mp1e2,
2420		.nvic,
2421	2061	.trust,
2422	2062	}),
2423	2063	};
...	...	@@ -2426,7 +2066,6 @@ pub const cpu = struct {
2426	2066	.llvm_name = "ck807f",
2427	2067	.features = featureSet(&[_]Feature{
2428	2068	.cache,
2429		.ck807,
2430	2069	.dsp1e2,
2431	2070	.dspe60,
2432	2071	.edsp,
...	...	@@ -2442,7 +2081,6 @@ pub const cpu = struct {
2442	2081	.hwdiv,
2443	2082	.mp,
2444	2083	.mp1e2,
2445		.nvic,
2446	2084	.trust,
2447	2085	}),
2448	2086	};
...	...	@@ -2452,7 +2090,6 @@ pub const cpu = struct {
2452	2090	.features = featureSet(&[_]Feature{
2453	2091	.@"7e10",
2454	2092	.cache,
2455		.ck810,
2456	2093	.dsp1e2,
2457	2094	.dspe60,
2458	2095	.edsp,
...	...	@@ -2461,7 +2098,6 @@ pub const cpu = struct {
2461	2098	.hwdiv,
2462	2099	.mp,
2463	2100	.mp1e2,
2464		.nvic,
2465	2101	.trust,
2466	2102	}),
2467	2103	};
...	...	@@ -2471,7 +2107,6 @@ pub const cpu = struct {
2471	2107	.features = featureSet(&[_]Feature{
2472	2108	.@"7e10",
2473	2109	.cache,
2474		.ck810,
2475	2110	.dsp1e2,
2476	2111	.dspe60,
2477	2112	.edsp,
...	...	@@ -2480,7 +2115,6 @@ pub const cpu = struct {
2480	2115	.hwdiv,
2481	2116	.mp,
2482	2117	.mp1e2,
2483		.nvic,
2484	2118	.trust,
2485	2119	}),
2486	2120	};
...	...	@@ -2490,7 +2124,6 @@ pub const cpu = struct {
2490	2124	.features = featureSet(&[_]Feature{
2491	2125	.@"7e10",
2492	2126	.cache,
2493		.ck810,
2494	2127	.dsp1e2,
2495	2128	.dspe60,
2496	2129	.edsp,
...	...	@@ -2504,7 +2137,6 @@ pub const cpu = struct {
2504	2137	.hwdiv,
2505	2138	.mp,
2506	2139	.mp1e2,
2507		.nvic,
2508	2140	.trust,
2509	2141	}),
2510	2142	};
...	...	@@ -2514,7 +2146,6 @@ pub const cpu = struct {
2514	2146	.features = featureSet(&[_]Feature{
2515	2147	.@"7e10",
2516	2148	.cache,
2517		.ck810,
2518	2149	.dsp1e2,
2519	2150	.dspe60,
2520	2151	.edsp,
...	...	@@ -2528,7 +2159,6 @@ pub const cpu = struct {
2528	2159	.hwdiv,
2529	2160	.mp,
2530	2161	.mp1e2,
2531		.nvic,
2532	2162	.trust,
2533	2163	}),
2534	2164	};
...	...	@@ -2538,8 +2168,6 @@ pub const cpu = struct {
2538	2168	.features = featureSet(&[_]Feature{
2539	2169	.@"7e10",
2540	2170	.cache,
2541		.ck810,
2542		.ck810v,
2543	2171	.dsp1e2,
2544	2172	.dspe60,
2545	2173	.edsp,
...	...	@@ -2553,7 +2181,6 @@ pub const cpu = struct {
2553	2181	.hwdiv,
2554	2182	.mp,
2555	2183	.mp1e2,
2556		.nvic,
2557	2184	.trust,
2558	2185	.vdspv1,
2559	2186	}),
...	...	@@ -2564,8 +2191,6 @@ pub const cpu = struct {
2564	2191	.features = featureSet(&[_]Feature{
2565	2192	.@"7e10",
2566	2193	.cache,
2567		.ck810,
2568		.ck810v,
2569	2194	.dsp1e2,
2570	2195	.dspe60,
2571	2196	.edsp,
...	...	@@ -2579,7 +2204,6 @@ pub const cpu = struct {
2579	2204	.hwdiv,
2580	2205	.mp,
2581	2206	.mp1e2,
2582		.nvic,
2583	2207	.trust,
2584	2208	.vdspv1,
2585	2209	}),
...	...	@@ -2590,7 +2214,6 @@ pub const cpu = struct {
2590	2214	.features = featureSet(&[_]Feature{
2591	2215	.@"7e10",
2592	2216	.cache,
2593		.ck810,
2594	2217	.dsp1e2,
2595	2218	.dspe60,
2596	2219	.edsp,
...	...	@@ -2599,7 +2222,6 @@ pub const cpu = struct {
2599	2222	.hwdiv,
2600	2223	.mp,
2601	2224	.mp1e2,
2602		.nvic,
2603	2225	.trust,
2604	2226	}),
2605	2227	};
...	...	@@ -2609,8 +2231,6 @@ pub const cpu = struct {
2609	2231	.features = featureSet(&[_]Feature{
2610	2232	.@"7e10",
2611	2233	.cache,
2612		.ck810,
2613		.ck810v,
2614	2234	.dsp1e2,
2615	2235	.dspe60,
2616	2236	.edsp,
...	...	@@ -2619,7 +2239,6 @@ pub const cpu = struct {
2619	2239	.hwdiv,
2620	2240	.mp,
2621	2241	.mp1e2,
2622		.nvic,
2623	2242	.trust,
2624	2243	.vdspv1,
2625	2244	}),
...	...	@@ -2630,8 +2249,6 @@ pub const cpu = struct {
2630	2249	.features = featureSet(&[_]Feature{
2631	2250	.@"7e10",
2632	2251	.cache,
2633		.ck810,
2634		.ck810v,
2635	2252	.dsp1e2,
2636	2253	.dspe60,
2637	2254	.edsp,
...	...	@@ -2640,7 +2257,6 @@ pub const cpu = struct {
2640	2257	.hwdiv,
2641	2258	.mp,
2642	2259	.mp1e2,
2643		.nvic,
2644	2260	.trust,
2645	2261	.vdspv1,
2646	2262	}),
...	...	@@ -2651,7 +2267,6 @@ pub const cpu = struct {
2651	2267	.features = featureSet(&[_]Feature{
2652	2268	.@"7e10",
2653	2269	.cache,
2654		.ck810,
2655	2270	.dsp1e2,
2656	2271	.dspe60,
2657	2272	.edsp,
...	...	@@ -2665,7 +2280,6 @@ pub const cpu = struct {
2665	2280	.hwdiv,
2666	2281	.mp,
2667	2282	.mp1e2,
2668		.nvic,
2669	2283	.trust,
2670	2284	}),
2671	2285	};
...	...	@@ -2675,7 +2289,6 @@ pub const cpu = struct {
2675	2289	.features = featureSet(&[_]Feature{
2676	2290	.@"7e10",
2677	2291	.cache,
2678		.ck810,
2679	2292	.dsp1e2,
2680	2293	.dspe60,
2681	2294	.edsp,
...	...	@@ -2689,7 +2302,6 @@ pub const cpu = struct {
2689	2302	.hwdiv,
2690	2303	.mp,
2691	2304	.mp1e2,
2692		.nvic,
2693	2305	.trust,
2694	2306	}),
2695	2307	};
...	...	@@ -2699,8 +2311,6 @@ pub const cpu = struct {
2699	2311	.features = featureSet(&[_]Feature{
2700	2312	.@"7e10",
2701	2313	.cache,
2702		.ck810,
2703		.ck810v,
2704	2314	.dsp1e2,
2705	2315	.dspe60,
2706	2316	.edsp,
...	...	@@ -2714,7 +2324,6 @@ pub const cpu = struct {
2714	2324	.hwdiv,
2715	2325	.mp,
2716	2326	.mp1e2,
2717		.nvic,
2718	2327	.trust,
2719	2328	.vdspv1,
2720	2329	}),
...	...	@@ -2725,8 +2334,6 @@ pub const cpu = struct {
2725	2334	.features = featureSet(&[_]Feature{
2726	2335	.@"7e10",
2727	2336	.cache,
2728		.ck810,
2729		.ck810v,
2730	2337	.dsp1e2,
2731	2338	.dspe60,
2732	2339	.edsp,
...	...	@@ -2740,7 +2347,6 @@ pub const cpu = struct {
2740	2347	.hwdiv,
2741	2348	.mp,
2742	2349	.mp1e2,
2743		.nvic,
2744	2350	.trust,
2745	2351	.vdspv1,
2746	2352	}),
...	...	@@ -2751,7 +2357,6 @@ pub const cpu = struct {
2751	2357	.features = featureSet(&[_]Feature{
2752	2358	.@"7e10",
2753	2359	.cache,
2754		.ck810,
2755	2360	.dsp1e2,
2756	2361	.dspe60,
2757	2362	.edsp,
...	...	@@ -2760,7 +2365,6 @@ pub const cpu = struct {
2760	2365	.hwdiv,
2761	2366	.mp,
2762	2367	.mp1e2,
2763		.nvic,
2764	2368	.trust,
2765	2369	}),
2766	2370	};
...	...	@@ -2770,8 +2374,6 @@ pub const cpu = struct {
2770	2374	.features = featureSet(&[_]Feature{
2771	2375	.@"7e10",
2772	2376	.cache,
2773		.ck810,
2774		.ck810v,
2775	2377	.dsp1e2,
2776	2378	.dspe60,
2777	2379	.edsp,
...	...	@@ -2780,7 +2382,6 @@ pub const cpu = struct {
2780	2382	.hwdiv,
2781	2383	.mp,
2782	2384	.mp1e2,
2783		.nvic,
2784	2385	.trust,
2785	2386	.vdspv1,
2786	2387	}),
...	...	@@ -2791,8 +2392,6 @@ pub const cpu = struct {
2791	2392	.features = featureSet(&[_]Feature{
2792	2393	.@"7e10",
2793	2394	.cache,
2794		.ck810,
2795		.ck810v,
2796	2395	.dsp1e2,
2797	2396	.dspe60,
2798	2397	.edsp,
...	...	@@ -2801,7 +2400,6 @@ pub const cpu = struct {
2801	2400	.hwdiv,
2802	2401	.mp,
2803	2402	.mp1e2,
2804		.nvic,
2805	2403	.trust,
2806	2404	.vdspv1,
2807	2405	}),
...	...	@@ -2815,14 +2413,12 @@ pub const cpu = struct {
2815	2413	.@"3e3r3",
2816	2414	.btst16,
2817	2415	.cache,
2818		.ck860,
2819	2416	.dspe60,
2820	2417	.hard_tp,
2821	2418	.high_registers,
2822	2419	.hwdiv,
2823	2420	.mp,
2824	2421	.mp1e2,
2825		.nvic,
2826	2422	.trust,
2827	2423	}),
2828	2424	};
...	...	@@ -2835,7 +2431,6 @@ pub const cpu = struct {
2835	2431	.@"3e3r3",
2836	2432	.btst16,
2837	2433	.cache,
2838		.ck860,
2839	2434	.dspe60,
2840	2435	.float7e60,
2841	2436	.fpuv3_df,
...	...	@@ -2847,7 +2442,6 @@ pub const cpu = struct {
2847	2442	.hwdiv,
2848	2443	.mp,
2849	2444	.mp1e2,
2850		.nvic,
2851	2445	.trust,
2852	2446	}),
2853	2447	};
...	...	@@ -2860,8 +2454,6 @@ pub const cpu = struct {
2860	2454	.@"3e3r3",
2861	2455	.btst16,
2862	2456	.cache,
2863		.ck860,
2864		.ck860v,
2865	2457	.dspe60,
2866	2458	.float7e60,
2867	2459	.fpuv3_df,
...	...	@@ -2873,7 +2465,6 @@ pub const cpu = struct {
2873	2465	.hwdiv,
2874	2466	.mp,
2875	2467	.mp1e2,
2876		.nvic,
2877	2468	.trust,
2878	2469	.vdsp2e60f,
2879	2470	.vdspv2,
...	...	@@ -2888,15 +2479,12 @@ pub const cpu = struct {
2888	2479	.@"3e3r3",
2889	2480	.btst16,
2890	2481	.cache,
2891		.ck860,
2892		.ck860v,
2893	2482	.dspe60,
2894	2483	.hard_tp,
2895	2484	.high_registers,
2896	2485	.hwdiv,
2897	2486	.mp,
2898	2487	.mp1e2,
2899		.nvic,
2900	2488	.trust,
2901	2489	.vdsp2e60f,
2902	2490	.vdspv2,
...	...	@@ -2907,7 +2495,6 @@ pub const cpu = struct {
2907	2495	.llvm_name = "e801",
2908	2496	.features = featureSet(&[_]Feature{
2909	2497	.btst16,
2910		.ck801,
2911	2498	.e1,
2912	2499	.trust,
2913	2500	}),
...	...	@@ -2917,9 +2504,7 @@ pub const cpu = struct {
2917	2504	.llvm_name = "e802",
2918	2505	.features = featureSet(&[_]Feature{
2919	2506	.btst16,
2920		.ck802,
2921	2507	.e2,
2922		.nvic,
2923	2508	.trust,
2924	2509	}),
2925	2510	};
...	...	@@ -2928,9 +2513,7 @@ pub const cpu = struct {
2928	2513	.llvm_name = "e802t",
2929	2514	.features = featureSet(&[_]Feature{
2930	2515	.btst16,
2931		.ck802,
2932	2516	.e2,
2933		.nvic,
2934	2517	.trust,
2935	2518	}),
2936	2519	};
...	...	@@ -2941,10 +2524,8 @@ pub const cpu = struct {
2941	2524	.@"3e3r2",
2942	2525	.@"3e3r3",
2943	2526	.btst16,
2944		.ck803,
2945	2527	.hwdiv,
2946	2528	.mp,
2947		.nvic,
2948	2529	.trust,
2949	2530	}),
2950	2531	};
...	...	@@ -2955,10 +2536,8 @@ pub const cpu = struct {
2955	2536	.@"3e3r2",
2956	2537	.@"3e3r3",
2957	2538	.btst16,
2958		.ck803,
2959	2539	.hwdiv,
2960	2540	.mp,
2961		.nvic,
2962	2541	.trust,
2963	2542	}),
2964	2543	};
...	...	@@ -2969,13 +2548,10 @@ pub const cpu = struct {
2969	2548	.@"3e3r2",
2970	2549	.@"3e3r3",
2971	2550	.btst16,
2972		.ck803,
2973		.ck804,
2974	2551	.dspv2,
2975	2552	.high_registers,
2976	2553	.hwdiv,
2977	2554	.mp,
2978		.nvic,
2979	2555	.trust,
2980	2556	}),
2981	2557	};
...	...	@@ -2986,8 +2562,6 @@ pub const cpu = struct {
2986	2562	.@"3e3r2",
2987	2563	.@"3e3r3",
2988	2564	.btst16,
2989		.ck803,
2990		.ck804,
2991	2565	.dspv2,
2992	2566	.float1e3,
2993	2567	.floate1,
...	...	@@ -2995,7 +2569,6 @@ pub const cpu = struct {
2995	2569	.high_registers,
2996	2570	.hwdiv,
2997	2571	.mp,
2998		.nvic,
2999	2572	.trust,
3000	2573	}),
3001	2574	};
...	...	@@ -3006,8 +2579,6 @@ pub const cpu = struct {
3006	2579	.@"3e3r2",
3007	2580	.@"3e3r3",
3008	2581	.btst16,
3009		.ck803,
3010		.ck804,
3011	2582	.dspv2,
3012	2583	.float1e3,
3013	2584	.floate1,
...	...	@@ -3015,7 +2586,6 @@ pub const cpu = struct {
3015	2586	.high_registers,
3016	2587	.hwdiv,
3017	2588	.mp,
3018		.nvic,
3019	2589	.trust,
3020	2590	}),
3021	2591	};
...	...	@@ -3026,13 +2596,10 @@ pub const cpu = struct {
3026	2596	.@"3e3r2",
3027	2597	.@"3e3r3",
3028	2598	.btst16,
3029		.ck803,
3030		.ck804,
3031	2599	.dspv2,
3032	2600	.high_registers,
3033	2601	.hwdiv,
3034	2602	.mp,
3035		.nvic,
3036	2603	.trust,
3037	2604	}),
3038	2605	};
...	...	@@ -3043,14 +2610,11 @@ pub const cpu = struct {
3043	2610	.@"3e3r2",
3044	2611	.@"3e3r3",
3045	2612	.btst16,
3046		.ck803,
3047		.ck804,
3048	2613	.float1e3,
3049	2614	.floate1,
3050	2615	.fpuv2_sf,
3051	2616	.hwdiv,
3052	2617	.mp,
3053		.nvic,
3054	2618	.trust,
3055	2619	}),
3056	2620	};
...	...	@@ -3061,14 +2625,11 @@ pub const cpu = struct {
3061	2625	.@"3e3r2",
3062	2626	.@"3e3r3",
3063	2627	.btst16,
3064		.ck803,
3065		.ck804,
3066	2628	.float1e3,
3067	2629	.floate1,
3068	2630	.fpuv2_sf,
3069	2631	.hwdiv,
3070	2632	.mp,
3071		.nvic,
3072	2633	.trust,
3073	2634	}),
3074	2635	};
...	...	@@ -3086,12 +2647,9 @@ pub const cpu = struct {
3086	2647	.@"3e3r2",
3087	2648	.@"3e3r3",
3088	2649	.btst16,
3089		.ck803,
3090		.ck805,
3091	2650	.high_registers,
3092	2651	.hwdiv,
3093	2652	.mp,
3094		.nvic,
3095	2653	.trust,
3096	2654	.vdsp2e3,
3097	2655	.vdspv2,
...	...	@@ -3104,15 +2662,12 @@ pub const cpu = struct {
3104	2662	.@"3e3r2",
3105	2663	.@"3e3r3",
3106	2664	.btst16,
3107		.ck803,
3108		.ck805,
3109	2665	.float1e3,
3110	2666	.floate1,
3111	2667	.fpuv2_sf,
3112	2668	.high_registers,
3113	2669	.hwdiv,
3114	2670	.mp,
3115		.nvic,
3116	2671	.trust,
3117	2672	.vdsp2e3,
3118	2673	.vdspv2,
...	...	@@ -3123,7 +2678,6 @@ pub const cpu = struct {
3123	2678	.llvm_name = "r807",
3124	2679	.features = featureSet(&[_]Feature{
3125	2680	.cache,
3126		.ck807,
3127	2681	.dsp1e2,
3128	2682	.dspe60,
3129	2683	.edsp,
...	...	@@ -3132,7 +2686,6 @@ pub const cpu = struct {
3132	2686	.hwdiv,
3133	2687	.mp,
3134	2688	.mp1e2,
3135		.nvic,
3136	2689	.trust,
3137	2690	}),
3138	2691	};
...	...	@@ -3141,7 +2694,6 @@ pub const cpu = struct {
3141	2694	.llvm_name = "r807f",
3142	2695	.features = featureSet(&[_]Feature{
3143	2696	.cache,
3144		.ck807,
3145	2697	.dsp1e2,
3146	2698	.dspe60,
3147	2699	.edsp,
...	...	@@ -3157,7 +2709,6 @@ pub const cpu = struct {
3157	2709	.hwdiv,
3158	2710	.mp,
3159	2711	.mp1e2,
3160		.nvic,
3161	2712	.trust,
3162	2713	}),
3163	2714	};
...	...	@@ -3166,9 +2717,7 @@ pub const cpu = struct {
3166	2717	.llvm_name = "s802",
3167	2718	.features = featureSet(&[_]Feature{
3168	2719	.btst16,
3169		.ck802,
3170	2720	.e2,
3171		.nvic,
3172	2721	.trust,
3173	2722	}),
3174	2723	};
...	...	@@ -3177,9 +2726,7 @@ pub const cpu = struct {
3177	2726	.llvm_name = "s802t",
3178	2727	.features = featureSet(&[_]Feature{
3179	2728	.btst16,
3180		.ck802,
3181	2729	.e2,
3182		.nvic,
3183	2730	.trust,
3184	2731	}),
3185	2732	};
...	...	@@ -3190,10 +2737,8 @@ pub const cpu = struct {
3190	2737	.@"3e3r2",
3191	2738	.@"3e3r3",
3192	2739	.btst16,
3193		.ck803,
3194	2740	.hwdiv,
3195	2741	.mp,
3196		.nvic,
3197	2742	.trust,
3198	2743	}),
3199	2744	};
...	...	@@ -3204,10 +2749,8 @@ pub const cpu = struct {
3204	2749	.@"3e3r2",
3205	2750	.@"3e3r3",
3206	2751	.btst16,
3207		.ck803,
3208	2752	.hwdiv,
3209	2753	.mp,
3210		.nvic,
3211	2754	.trust,
3212	2755	}),
3213	2756	};

lib/std/Target/hppa.zig+7-15

...	...	@@ -5,7 +5,6 @@ const CpuFeature = std.Target.Cpu.Feature;
5	5	const CpuModel = std.Target.Cpu.Model;
6	6
7	7	pub const Feature = enum {
8		@"64bit",
9	8	max_1,
10	9	max_2,
11	10	v1_1,
...	...	@@ -21,13 +20,6 @@ pub const all_features = blk: {
21	20	const len = @typeInfo(Feature).@"enum".field_names.len;
22	21	std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
23	22	var result: [len]CpuFeature = undefined;
24		result[@backingInt(Feature.@"64bit")] = .{
25		.llvm_name = null,
26		.description = "Enable 64-bit PA-RISC 2.0",
27		.dependencies = featureSet(&[_]Feature{
28		.v2_0,
29		}),
30		};
31	23	result[@backingInt(Feature.max_1)] = .{
32	24	.llvm_name = null,
33	25	.description = "Enable MAX-1 multimedia acceleration extensions",
...	...	@@ -120,49 +112,49 @@ pub const cpu = struct {
120	112	.name = "pa_8000",
121	113	.llvm_name = null,
122	114	.features = featureSet(&[_]Feature{
123		.@"64bit",
	115	.v2_0,
124	116	}),
125	117	};
126	118	pub const pa_8200: CpuModel = .{
127	119	.name = "pa_8200",
128	120	.llvm_name = null,
129	121	.features = featureSet(&[_]Feature{
130		.@"64bit",
	122	.v2_0,
131	123	}),
132	124	};
133	125	pub const pa_8500: CpuModel = .{
134	126	.name = "pa_8500",
135	127	.llvm_name = null,
136	128	.features = featureSet(&[_]Feature{
137		.@"64bit",
	129	.v2_0,
138	130	}),
139	131	};
140	132	pub const pa_8600: CpuModel = .{
141	133	.name = "pa_8600",
142	134	.llvm_name = null,
143	135	.features = featureSet(&[_]Feature{
144		.@"64bit",
	136	.v2_0,
145	137	}),
146	138	};
147	139	pub const pa_8700: CpuModel = .{
148	140	.name = "pa_8700",
149	141	.llvm_name = null,
150	142	.features = featureSet(&[_]Feature{
151		.@"64bit",
	143	.v2_0,
152	144	}),
153	145	};
154	146	pub const pa_8800: CpuModel = .{
155	147	.name = "pa_8800",
156	148	.llvm_name = null,
157	149	.features = featureSet(&[_]Feature{
158		.@"64bit",
	150	.v2_0,
159	151	}),
160	152	};
161	153	pub const pa_8900: CpuModel = .{
162	154	.name = "pa_8900",
163	155	.llvm_name = null,
164	156	.features = featureSet(&[_]Feature{
165		.@"64bit",
	157	.v2_0,
166	158	}),
167	159	};
168	160	pub const pcx: CpuModel = .{

lib/std/Target/kvx.zig+1-3

...	...	@@ -27,9 +27,7 @@ pub const all_features = blk: {
27	27	result[@backingInt(Feature.v3_2)] = .{
28	28	.llvm_name = null,
29	29	.description = "Enable ISA v3.2",
30		.dependencies = featureSet(&[_]Feature{
31		.v3_1,
32		}),
	30	.dependencies = featureSet(&[_]Feature{}),
33	31	};
34	32	result[@backingInt(Feature.v4_1)] = .{
35	33	.llvm_name = null,

lib/std/Target/ve.zig+24-3

...	...	@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
5	5	const CpuModel = std.Target.Cpu.Model;
6	6
7	7	pub const Feature = enum {
	8	ve3,
8	9	vpu,
9	10	};
10	11
...	...	@@ -17,6 +18,11 @@ pub const all_features = blk: {
17	18	const len = @typeInfo(Feature).@"enum".field_names.len;
18	19	std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
19	20	var result: [len]CpuFeature = undefined;
	21	result[@backingInt(Feature.ve3)] = .{
	22	.llvm_name = null,
	23	.description = "Enable VE3 instructions",
	24	.dependencies = featureSet(&[_]Feature{}),
	25	};
20	26	result[@backingInt(Feature.vpu)] = .{
21	27	.llvm_name = "vpu",
22	28	.description = "Enable the VPU",
...	...	@@ -31,10 +37,25 @@ pub const all_features = blk: {
31	37	};
32	38
33	39	pub const cpu = struct {
34		pub const generic: CpuModel = .{
35		.name = "generic",
36		.llvm_name = "generic",
	40	pub const ve10: CpuModel = .{
	41	.name = "ve10",
	42	.llvm_name = null,
	43	.features = featureSet(&[_]Feature{
	44	.vpu,
	45	}),
	46	};
	47	pub const ve20: CpuModel = .{
	48	.name = "ve20",
	49	.llvm_name = null,
	50	.features = featureSet(&[_]Feature{
	51	.vpu,
	52	}),
	53	};
	54	pub const ve30: CpuModel = .{
	55	.name = "ve30",
	56	.llvm_name = null,
37	57	.features = featureSet(&[_]Feature{
	58	.ve3,
38	59	.vpu,
39	60	}),
40	61	};

lib/std/Target/wasm.zig+36-28

...	...	@@ -114,6 +114,7 @@ pub const all_features = blk: {
114	114	.llvm_name = "reference-types",
115	115	.description = "Enable reference types",
116	116	.dependencies = featureSet(&[_]Feature{
	117	.bulk_memory,
117	118	.call_indirect_overlong,
118	119	}),
119	120	};
...	...	@@ -125,7 +126,9 @@ pub const all_features = blk: {
125	126	result[@backingInt(Feature.relaxed_simd)] = .{
126	127	.llvm_name = "relaxed-simd",
127	128	.description = "Enable relaxed-simd instructions",
128		.dependencies = featureSet(&[_]Feature{}),
	129	.dependencies = featureSet(&[_]Feature{
	130	.simd128,
	131	}),
129	132	};
130	133	result[@backingInt(Feature.sign_ext)] = .{
131	134	.llvm_name = "sign-ext",
...	...	@@ -156,53 +159,58 @@ pub const all_features = blk: {
156	159	};
157	160
158	161	pub const cpu = struct {
159		pub const bleeding_edge: CpuModel = .{
160		.name = "bleeding_edge",
161		.llvm_name = "bleeding-edge",
	162	pub const lime1: CpuModel = .{
	163	.name = "lime1",
	164	.llvm_name = "lime1",
162	165	.features = featureSet(&[_]Feature{
163		.atomics,
164		.bulk_memory,
165		.exception_handling,
	166	.bulk_memory_opt,
	167	.call_indirect_overlong,
166	168	.extended_const,
167		.fp16,
168		.gc,
169		.multimemory,
	169	.multivalue,
170	170	.mutable_globals,
171	171	.nontrapping_fptoint,
172		.relaxed_simd,
173	172	.sign_ext,
174		.simd128,
175		.tail_call,
176	173	}),
177	174	};
178		pub const generic: CpuModel = .{
179		.name = "generic",
180		.llvm_name = "generic",
	175	pub const mvp: CpuModel = .{
	176	.name = "mvp",
	177	.llvm_name = "mvp",
	178	.features = featureSet(&[_]Feature{}),
	179	};
	180	pub const wasm_v1_0: CpuModel = .{
	181	.name = "wasm_v1_0",
	182	.llvm_name = null,
	183	.features = featureSet(&[_]Feature{
	184	.mutable_globals,
	185	}),
	186	};
	187	pub const wasm_v2_0: CpuModel = .{
	188	.name = "wasm_v2_0",
	189	.llvm_name = null,
181	190	.features = featureSet(&[_]Feature{
182		.bulk_memory,
183	191	.multivalue,
184	192	.mutable_globals,
185	193	.nontrapping_fptoint,
186	194	.reference_types,
187	195	.sign_ext,
	196	.simd128,
188	197	}),
189	198	};
190		pub const lime1: CpuModel = .{
191		.name = "lime1",
192		.llvm_name = "lime1",
	199	pub const wasm_v3_0: CpuModel = .{
	200	.name = "wasm_v3_0",
	201	.llvm_name = null,
193	202	.features = featureSet(&[_]Feature{
194		.bulk_memory_opt,
195		.call_indirect_overlong,
	203	.atomics,
	204	.exception_handling,
196	205	.extended_const,
197		.multivalue,
	206	.fp16,
	207	.gc,
	208	.multimemory,
198	209	.mutable_globals,
199	210	.nontrapping_fptoint,
	211	.relaxed_simd,
200	212	.sign_ext,
	213	.tail_call,
201	214	}),
202	215	};
203		pub const mvp: CpuModel = .{
204		.name = "mvp",
205		.llvm_name = "mvp",
206		.features = featureSet(&[_]Feature{}),
207		};
208	216	};

lib/std/Target/x86.zig+12-4

...	...	@@ -3136,7 +3136,7 @@ pub const cpu = struct {
3136	3136	};
3137	3137	pub const goldmont_plus: CpuModel = .{
3138	3138	.name = "goldmont_plus",
3139		.llvm_name = "goldmont-plus",
	3139	.llvm_name = "goldmont_plus",
3140	3140	.features = featureSet(&[_]Feature{
3141	3141	.@"64bit",
3142	3142	.aes,
...	...	@@ -3163,6 +3163,8 @@ pub const cpu = struct {
3163	3163	.slow_incdec,
3164	3164	.slow_lea,
3165	3165	.slow_two_mem_ops,
	3166	.smap,
	3167	.smep,
3166	3168	.sse4_2,
3167	3169	.use_glm_div_sqrt_costs,
3168	3170	.vzeroupper,
...	...	@@ -3564,7 +3566,7 @@ pub const cpu = struct {
3564	3566	};
3565	3567	pub const icelake_client: CpuModel = .{
3566	3568	.name = "icelake_client",
3567		.llvm_name = "icelake-client",
	3569	.llvm_name = "icelake_client",
3568	3570	.features = featureSet(&[_]Feature{
3569	3571	.@"64bit",
3570	3572	.adx,
...	...	@@ -3615,6 +3617,8 @@ pub const cpu = struct {
3615	3617	.sahf,
3616	3618	.sha,
3617	3619	.slow_pmullq,
	3620	.smap,
	3621	.smep,
3618	3622	.tuning_fast_imm_vector_shift,
3619	3623	.vaes,
3620	3624	.vpclmulqdq,
...	...	@@ -3627,7 +3631,7 @@ pub const cpu = struct {
3627	3631	};
3628	3632	pub const icelake_server: CpuModel = .{
3629	3633	.name = "icelake_server",
3630		.llvm_name = "icelake-server",
	3634	.llvm_name = "icelake_server",
3631	3635	.features = featureSet(&[_]Feature{
3632	3636	.@"64bit",
3633	3637	.adx,
...	...	@@ -3680,6 +3684,8 @@ pub const cpu = struct {
3680	3684	.sahf,
3681	3685	.sha,
3682	3686	.slow_pmullq,
	3687	.smap,
	3688	.smep,
3683	3689	.tuning_fast_imm_vector_shift,
3684	3690	.vaes,
3685	3691	.vpclmulqdq,
...	...	@@ -4872,7 +4878,7 @@ pub const cpu = struct {
4872	4878	};
4873	4879	pub const skylake_avx512: CpuModel = .{
4874	4880	.name = "skylake_avx512",
4875		.llvm_name = "skylake-avx512",
	4881	.llvm_name = "skylake_avx512",
4876	4882	.features = featureSet(&[_]Feature{
4877	4883	.@"64bit",
4878	4884	.adx,
...	...	@@ -4919,6 +4925,8 @@ pub const cpu = struct {
4919	4925	.rdseed,
4920	4926	.sahf,
4921	4927	.slow_3ops_lea,
	4928	.smap,
	4929	.smep,
4922	4930	.tuning_fast_imm_vector_shift,
4923	4931	.vzeroupper,
4924	4932	.x87,

lib/std/Target/xcore.zig+49-8

...	...	@@ -4,7 +4,12 @@ const std = @import("../std.zig");
4	4	const CpuFeature = std.Target.Cpu.Feature;
5	5	const CpuModel = std.Target.Cpu.Model;
6	6
7		pub const Feature = enum {};
	7	pub const Feature = enum {
	8	fpu,
	9	vpu,
	10	xs2,
	11	xs3,
	12	};
8	13
9	14	pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
10	15	pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
...	...	@@ -15,6 +20,32 @@ pub const all_features = blk: {
15	20	const len = @typeInfo(Feature).@"enum".field_names.len;
16	21	std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
17	22	var result: [len]CpuFeature = undefined;
	23	result[@backingInt(Feature.fpu)] = .{
	24	.llvm_name = null,
	25	.description = "Enable single-precision floating point unit",
	26	.dependencies = featureSet(&[_]Feature{
	27	.xs3,
	28	}),
	29	};
	30	result[@backingInt(Feature.vpu)] = .{
	31	.llvm_name = null,
	32	.description = "Enable vector processing unit",
	33	.dependencies = featureSet(&[_]Feature{
	34	.xs3,
	35	}),
	36	};
	37	result[@backingInt(Feature.xs2)] = .{
	38	.llvm_name = null,
	39	.description = "Enable XS2 architecture",
	40	.dependencies = featureSet(&[_]Feature{}),
	41	};
	42	result[@backingInt(Feature.xs3)] = .{
	43	.llvm_name = null,
	44	.description = "Enable XS3 architecture",
	45	.dependencies = featureSet(&[_]Feature{
	46	.xs2,
	47	}),
	48	};
18	49	const ti = @typeInfo(Feature);
19	50	for (&result, 0..) \|*elem, i\| {
20	51	elem.index = i;
...	...	@@ -24,14 +55,24 @@ pub const all_features = blk: {
24	55	};
25	56
26	57	pub const cpu = struct {
27		pub const generic: CpuModel = .{
28		.name = "generic",
29		.llvm_name = "generic",
	58	pub const xs1b: CpuModel = .{
	59	.name = "xs1b",
	60	.llvm_name = null,
30	61	.features = featureSet(&[_]Feature{}),
31	62	};
32		pub const xs1b_generic: CpuModel = .{
33		.name = "xs1b_generic",
34		.llvm_name = "xs1b-generic",
35		.features = featureSet(&[_]Feature{}),
	63	pub const xs2a: CpuModel = .{
	64	.name = "xs2a",
	65	.llvm_name = null,
	66	.features = featureSet(&[_]Feature{
	67	.xs2,
	68	}),
	69	};
	70	pub const xs3a: CpuModel = .{
	71	.name = "xs3a",
	72	.llvm_name = null,
	73	.features = featureSet(&[_]Feature{
	74	.fpu,
	75	.vpu,
	76	}),
36	77	};
37	78	};

src/Type.zig+1-4

...	...	@@ -1302,10 +1302,7 @@ pub fn abiSize(ty: Type, zcu: *const Zcu) u64 {
1302	1302	}
1303	1303
1304	1304	pub fn ptrAbiAlignment(target: *const Target) Alignment {
1305		// The eZ80 has 24-bit pointers, which aren't exact powers of two, tripping
1306		// the assert. The alignment of eZ80 pointers is 1, so we bypass the check.
1307		if (target.cpu.arch == .ez80) return .@"1";
1308		return .fromNonzeroByteUnits(@divExact(target.ptrBitWidth(), 8));
	1305	return .fromNonzeroByteUnits(std.zig.target.intAlignment(target, target.ptrBitWidth()));
1309	1306	}
1310	1307	pub fn ptrAbiSize(target: *const Target) u64 {
1311	1308	return @divExact(target.ptrBitWidth(), 8);

test/c_abi/main.zig+6-6

...	...	@@ -5032,7 +5032,7 @@ extern fn c_vector_6_u8(@Vector(6, u8), usize) void;
5032	5032	extern fn c_test_vector_6_u8() void;
5033	5033
5034	5034	test "@Vector(6, u8)" {
5035		if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
	5035	if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
5036	5036	if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
5037	5037	if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
5038	5038	if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
...	...	@@ -5110,7 +5110,7 @@ extern fn c_vector_12_u8(@Vector(12, u8), usize) void;
5110	5110	extern fn c_test_vector_12_u8() void;
5111	5111
5112	5112	test "@Vector(12, u8)" {
5113		if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
	5113	if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
5114	5114	if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
5115	5115	if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
5116	5116
...	...	@@ -9176,7 +9176,7 @@ extern fn c_vector_3_u16(@Vector(3, u16), usize) void;
9176	9176	extern fn c_test_vector_3_u16() void;
9177	9177
9178	9178	test "@Vector(3, u16)" {
9179		if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
	9179	if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
9180	9180	if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
9181	9181	if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
9182	9182	if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
...	...	@@ -9250,7 +9250,7 @@ extern fn c_vector_6_u16(@Vector(6, u16), usize) void;
9250	9250	extern fn c_test_vector_6_u16() void;
9251	9251
9252	9252	test "@Vector(6, u16)" {
9253		if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
	9253	if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
9254	9254	if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
9255	9255	if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
9256	9256
...	...	@@ -11439,7 +11439,7 @@ extern fn c_vector_3_u32(@Vector(3, u32), usize) void;
11439	11439	extern fn c_test_vector_3_u32() void;
11440	11440
11441	11441	test "@Vector(3, u32)" {
11442		if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
	11442	if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
11443	11443	if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
11444	11444	if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
11445	11445
...	...	@@ -13424,7 +13424,7 @@ extern fn c_vector_3_f32(@Vector(3, f32), usize) void;
13424	13424	extern fn c_test_vector_3_f32() void;
13425	13425
13426	13426	test "@Vector(3, f32)" {
13427		if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
	13427	if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
13428	13428	if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
13429	13429	if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
13430	13430

tools/update_cpu_features.zig+854-348

...	...	@@ -23,7 +23,17 @@ const FeatureOverride = struct {
23	23	extra_deps: []const []const u8 = &.{},
24	24	};
25	25
26		const Cpu = struct {
	26	const ModelOverride = struct {
	27	llvm_name: []const u8,
	28	/// If true, completely omit the CPU; as if it does not exist.
	29	omit: bool = false,
	30	zig_name: ?[]const u8 = null,
	31	desc: ?[]const u8 = null,
	32	omit_deps: []const []const u8 = &.{},
	33	extra_deps: []const []const u8 = &.{},
	34	};
	35
	36	const Model = struct {
27	37	llvm_name: ?[]const u8,
28	38	zig_name: []const u8,
29	39	features: []const []const u8,
...	...	@@ -44,9 +54,9 @@ const ArchTarget = struct {
44	54	td_name: []const u8,
45	55	},
46	56	feature_overrides: []const FeatureOverride = &.{},
47		extra_cpus: []const Cpu = &.{},
48	57	extra_features: []const Feature = &.{},
49		omit_cpus: []const []const u8 = &.{},
	58	model_overrides: []const ModelOverride = &.{},
	59	extra_models: []const Model = &.{},
50	60	branch_quota: ?usize = null,
51	61	};
52	62
...	...	@@ -432,7 +442,15 @@ const targets = [_]ArchTarget{
432	442	.flatten = true,
433	443	},
434	444	},
435		.extra_cpus = &.{
	445	.model_overrides = &.{
	446	.{
	447	// Who thought this alias was a good idea? Upgrade your compiler and suddenly your
	448	// programs SIGILL because this changed meaning. Brilliant.
	449	.llvm_name = "apple-latest",
	450	.omit = true,
	451	},
	452	},
	453	.extra_models = &.{
436	454	.{
437	455	.llvm_name = null,
438	456	.zig_name = "exynos_m1",
...	...	@@ -485,11 +503,6 @@ const targets = [_]ArchTarget{
485	503	},
486	504	},
487	505	},
488		.omit_cpus = &.{
489		// Who thought this alias was a good idea? Upgrade your compiler and suddenly your
490		// programs SIGILL because this changed meaning. Brilliant.
491		"apple-latest",
492		},
493	506	},
494	507	.{
495	508	.zig_name = "alpha",
...	...	@@ -507,7 +520,7 @@ const targets = [_]ArchTarget{
507	520	},
508	521	.{
509	522	.zig_name = "fix",
510		.desc = "Enable floating point move and square root extensions",
	523	.desc = "Enable FPR-to-GPR move and square root extensions",
511	524	.deps = &.{},
512	525	},
513	526	.{
...	...	@@ -516,7 +529,7 @@ const targets = [_]ArchTarget{
516	529	.deps = &.{},
517	530	},
518	531	},
519		.extra_cpus = &.{
	532	.extra_models = &.{
520	533	.{
521	534	.llvm_name = null,
522	535	.zig_name = "ev4",
...	...	@@ -614,169 +627,146 @@ const targets = [_]ArchTarget{
614	627	.branch_quota = 10000,
615	628	.feature_overrides = &.{
616	629	.{
617		.llvm_name = "exynos",
	630	.llvm_name = "a5",
618	631	.flatten = true,
619	632	},
620	633	.{
621		.llvm_name = "cortex-a78",
	634	.llvm_name = "a7",
622	635	.flatten = true,
623	636	},
624	637	.{
625		.llvm_name = "cortex-a78ae",
	638	.llvm_name = "a8",
626	639	.flatten = true,
627	640	},
628	641	.{
629		.llvm_name = "cortex-a710",
	642	.llvm_name = "a9",
630	643	.flatten = true,
631	644	},
632	645	.{
633		.llvm_name = "cortex-m4",
634		.omit_deps = &.{"vfp4d16sp"},
635		},
636		.{
637		.llvm_name = "cortex-m7",
638		.omit_deps = &.{"fp_armv8d16"},
639		},
640		.{
641		.llvm_name = "cortex-m33",
642		.omit_deps = &.{ "fp_armv8d16sp", "dsp" },
643		},
644		.{
645		.llvm_name = "cortex-m35p",
646		.omit_deps = &.{ "fp_armv8d16sp", "dsp" },
647		},
648		.{
649		.llvm_name = "cortex-m55",
650		.omit_deps = &.{ "mve_fp", "fp_armv8d16" },
651		},
652		.{
653		.llvm_name = "cortex-m85",
654		.omit_deps = &.{ "mve_fp", "pacbti", "fp_armv8d16" },
655		},
656		.{
657		.llvm_name = "cortex-x1c",
	646	.llvm_name = "a12",
658	647	.flatten = true,
659	648	},
660	649	.{
661		.llvm_name = "r4",
	650	.llvm_name = "a15",
662	651	.flatten = true,
663	652	},
664	653	.{
665		.llvm_name = "r52plus",
	654	.llvm_name = "a17",
666	655	.flatten = true,
667	656	},
668	657	.{
669		.llvm_name = "r5",
	658	.llvm_name = "a32",
670	659	.flatten = true,
671	660	},
672	661	.{
673		.llvm_name = "r52",
	662	.llvm_name = "a35",
674	663	.flatten = true,
675	664	},
676	665	.{
677		.llvm_name = "r7",
	666	.llvm_name = "a53",
678	667	.flatten = true,
679	668	},
680	669	.{
681		.llvm_name = "m3",
	670	.llvm_name = "a55",
682	671	.flatten = true,
683	672	},
684	673	.{
685		.llvm_name = "m7",
	674	.llvm_name = "a57",
686	675	.flatten = true,
687	676	},
688	677	.{
689		.llvm_name = "krait",
	678	.llvm_name = "a72",
690	679	.flatten = true,
691	680	},
692	681	.{
693		.llvm_name = "kryo",
	682	.llvm_name = "a73",
694	683	.flatten = true,
695	684	},
696	685	.{
697		.llvm_name = "swift",
	686	.llvm_name = "a75",
698	687	.flatten = true,
699	688	},
700	689	.{
701		.llvm_name = "cortex-x1",
	690	.llvm_name = "a76",
702	691	.flatten = true,
703	692	},
704	693	.{
705		.llvm_name = "neoverse-v1",
	694	.llvm_name = "a77",
706	695	.flatten = true,
707	696	},
708	697	.{
709		.llvm_name = "a5",
	698	.llvm_name = "a78c",
710	699	.flatten = true,
711	700	},
712	701	.{
713		.llvm_name = "a7",
	702	.llvm_name = "cortex-a78",
714	703	.flatten = true,
715	704	},
716	705	.{
717		.llvm_name = "a8",
	706	.llvm_name = "cortex-a78ae",
718	707	.flatten = true,
719	708	},
720	709	.{
721		.llvm_name = "a9",
	710	.llvm_name = "cortex-a710",
722	711	.flatten = true,
723	712	},
724	713	.{
725		.llvm_name = "a12",
	714	.llvm_name = "cortex-x1",
726	715	.flatten = true,
727	716	},
728	717	.{
729		.llvm_name = "a15",
	718	.llvm_name = "cortex-x1c",
730	719	.flatten = true,
731	720	},
732	721	.{
733		.llvm_name = "a17",
	722	.llvm_name = "exynos",
734	723	.flatten = true,
735	724	},
736	725	.{
737		.llvm_name = "a32",
	726	.llvm_name = "krait",
738	727	.flatten = true,
739	728	},
740	729	.{
741		.llvm_name = "a35",
	730	.llvm_name = "kryo",
742	731	.flatten = true,
743	732	},
744	733	.{
745		.llvm_name = "a53",
	734	.llvm_name = "m3",
746	735	.flatten = true,
747	736	},
748	737	.{
749		.llvm_name = "a55",
	738	.llvm_name = "m7",
750	739	.flatten = true,
751	740	},
752	741	.{
753		.llvm_name = "a57",
	742	.llvm_name = "neoverse-v1",
754	743	.flatten = true,
755	744	},
756	745	.{
757		.llvm_name = "a72",
	746	.llvm_name = "r4",
758	747	.flatten = true,
759	748	},
760	749	.{
761		.llvm_name = "a73",
	750	.llvm_name = "r5",
762	751	.flatten = true,
763	752	},
764	753	.{
765		.llvm_name = "a75",
	754	.llvm_name = "r7",
766	755	.flatten = true,
767	756	},
768	757	.{
769		.llvm_name = "a76",
	758	.llvm_name = "r52",
770	759	.flatten = true,
771	760	},
772	761	.{
773		.llvm_name = "a77",
	762	.llvm_name = "r52plus",
774	763	.flatten = true,
775	764	},
776	765	.{
777		.llvm_name = "a78c",
	766	.llvm_name = "swift",
778	767	.flatten = true,
779	768	},
	769
780	770	.{
781	771	.llvm_name = "armv2",
782	772	.zig_name = "v2",
...	...	@@ -853,6 +843,7 @@ const targets = [_]ArchTarget{
853	843	.{
854	844	.llvm_name = "armv7-a",
855	845	.zig_name = "v7a",
	846	.omit_deps = &.{"neon"},
856	847	},
857	848	.{
858	849	.llvm_name = "armv7-m",
...	...	@@ -877,58 +868,72 @@ const targets = [_]ArchTarget{
877	868	.{
878	869	.llvm_name = "armv7ve",
879	870	.zig_name = "v7ve",
	871	.omit_deps = &.{"neon"},
880	872	},
881	873	.{
882	874	.llvm_name = "armv8.1-a",
883	875	.zig_name = "v8_1a",
	876	.omit_deps = &.{"crypto"},
884	877	},
885	878	.{
886	879	.llvm_name = "armv8.1-m.main",
887	880	.zig_name = "v8_1m_main",
	881	.omit_deps = &.{"8msecext"},
888	882	},
889	883	.{
890	884	.llvm_name = "armv8.2-a",
891	885	.zig_name = "v8_2a",
	886	.omit_deps = &.{"crypto"},
892	887	},
893	888	.{
894	889	.llvm_name = "armv8.3-a",
895	890	.zig_name = "v8_3a",
	891	.omit_deps = &.{"crypto"},
896	892	},
897	893	.{
898	894	.llvm_name = "armv8.4-a",
899	895	.zig_name = "v8_4a",
	896	.omit_deps = &.{"crypto"},
900	897	},
901	898	.{
902	899	.llvm_name = "armv8.5-a",
903	900	.zig_name = "v8_5a",
	901	.omit_deps = &.{"crypto"},
904	902	},
905	903	.{
906	904	.llvm_name = "armv8.6-a",
907	905	.zig_name = "v8_6a",
	906	.omit_deps = &.{"crypto"},
908	907	},
909	908	.{
910	909	.llvm_name = "armv8.7-a",
911	910	.zig_name = "v8_7a",
	911	.omit_deps = &.{"crypto"},
912	912	},
913	913	.{
914	914	.llvm_name = "armv8.8-a",
915	915	.zig_name = "v8_8a",
	916	.omit_deps = &.{"crypto"},
916	917	},
917	918	.{
918	919	.llvm_name = "armv8.9-a",
919	920	.zig_name = "v8_9a",
	921	.omit_deps = &.{"crypto"},
920	922	},
921	923	.{
922	924	.llvm_name = "armv8-a",
923	925	.zig_name = "v8a",
	926	.omit_deps = &.{"crypto"},
924	927	},
925	928	.{
926	929	.llvm_name = "armv8-m.base",
927	930	.zig_name = "v8m",
	931	.omit_deps = &.{"8msecext"},
928	932	},
929	933	.{
930	934	.llvm_name = "armv8-m.main",
931	935	.zig_name = "v8m_main",
	936	.omit_deps = &.{"8msecext"},
932	937	},
933	938	.{
934	939	.llvm_name = "armv8-r",
...	...	@@ -945,6 +950,7 @@ const targets = [_]ArchTarget{
945	950	.{
946	951	.llvm_name = "armv9.3-a",
947	952	.zig_name = "v9_3a",
	953	.omit_deps = &.{"crypto"},
948	954	},
949	955	.{
950	956	.llvm_name = "armv9.4-a",
...	...	@@ -1087,23 +1093,6 @@ const targets = [_]ArchTarget{
1087	1093	.zig_name = "has_v9_7a",
1088	1094	},
1089	1095	},
1090		.extra_cpus = &.{
1091		.{
1092		.llvm_name = "generic",
1093		.zig_name = "baseline",
1094		.features = &.{"v7a"},
1095		},
1096		.{
1097		.llvm_name = null,
1098		.zig_name = "exynos_m1",
1099		.features = &.{ "v8a", "exynos" },
1100		},
1101		.{
1102		.llvm_name = null,
1103		.zig_name = "exynos_m2",
1104		.features = &.{ "v8a", "exynos" },
1105		},
1106		},
1107	1096	.extra_features = &.{
1108	1097	// LLVM removed support for v2 and v3 but zig wants to support targeting old hardware
1109	1098	.{
...	...	@@ -1127,183 +1116,459 @@ const targets = [_]ArchTarget{
1127	1116	.deps = &.{"strict_align"},
1128	1117	},
1129	1118	},
1130		},
1131		.{
1132		.zig_name = "avr",
1133		.llvm = .{
1134		.name = "AVR",
1135		.td_name = "AVR",
1136		},
1137		},
1138		.{
1139		.zig_name = "bpf",
1140		.llvm = .{
1141		.name = "BPF",
1142		.td_name = "BPF",
1143		},
1144		},
1145		.{
1146		.zig_name = "csky",
1147		.llvm = .{
1148		.name = "CSKY",
1149		.td_name = "CSKY",
1150		},
1151		},
1152		.{
1153		.zig_name = "hexagon",
1154		.llvm = .{
1155		.name = "Hexagon",
1156		.td_name = "Hexagon",
1157		},
1158		},
1159		.{
1160		.zig_name = "hppa",
1161		.llvm = null,
1162		.extra_features = &.{
	1119	.model_overrides = &.{
1163	1120	.{
1164		.zig_name = "64bit",
1165		.desc = "Enable 64-bit PA-RISC 2.0",
1166		.deps = &.{"v2_0"},
	1121	.llvm_name = "cortex-a5",
	1122	.omit_deps = &.{"vfp4"},
1167	1123	},
1168	1124	.{
1169		.zig_name = "max_1",
1170		.desc = "Enable MAX-1 multimedia acceleration extensions",
1171		.deps = &.{},
	1125	.llvm_name = "cortex-a7",
	1126	.omit_deps = &.{"vfp4"},
1172	1127	},
1173	1128	.{
1174		.zig_name = "max_2",
1175		.desc = "Enable MAX-2 multimedia acceleration extensions",
1176		.deps = &.{"max_1"},
	1129	.llvm_name = "cortex-a9",
	1130	.omit_deps = &.{"fp16"},
1177	1131	},
1178	1132	.{
1179		.zig_name = "v1_1",
1180		.desc = "Enable ISA v1.1",
1181		.deps = &.{},
	1133	.llvm_name = "cortex-a12",
	1134	.omit_deps = &.{"vfp4"},
1182	1135	},
1183	1136	.{
1184		.zig_name = "v2_0",
1185		.desc = "Enable ISA v2.0",
1186		.deps = &.{ "max_2", "v1_1" },
	1137	.llvm_name = "cortex-a15",
	1138	.omit_deps = &.{"vfp4"},
1187	1139	},
1188		},
1189		.extra_cpus = &.{
1190	1140	.{
1191		.llvm_name = null,
1192		.zig_name = "ts_1",
1193		.features = &.{},
	1141	.llvm_name = "cortex-a17",
	1142	.omit_deps = &.{"vfp4"},
1194	1143	},
1195	1144	.{
1196		.llvm_name = null,
1197		.zig_name = "ns_1",
1198		.features = &.{},
	1145	.llvm_name = "cortex-a32",
	1146	.omit_deps = &.{"crypto"},
1199	1147	},
1200	1148	.{
1201		.llvm_name = null,
1202		.zig_name = "ns_2",
1203		.features = &.{},
	1149	.llvm_name = "cortex-a35",
	1150	.omit_deps = &.{"crypto"},
1204	1151	},
1205	1152	.{
1206		.llvm_name = null,
1207		.zig_name = "pcx",
1208		.features = &.{},
	1153	.llvm_name = "cortex-a53",
	1154	.omit_deps = &.{"crypto"},
1209	1155	},
1210	1156	.{
1211		.llvm_name = null,
1212		.zig_name = "pa_7000",
1213		.features = &.{
1214		"v1_1",
1215		},
	1157	.llvm_name = "cortex-a57",
	1158	.omit_deps = &.{"crypto"},
1216	1159	},
1217	1160	.{
1218		.llvm_name = null,
1219		.zig_name = "pa_7100",
1220		.features = &.{
1221		"v1_1",
1222		},
	1161	.llvm_name = "cortex-a72",
	1162	.omit_deps = &.{"crypto"},
1223	1163	},
1224	1164	.{
1225		.llvm_name = null,
1226		.zig_name = "pa_7150",
1227		.features = &.{
1228		"v1_1",
1229		},
	1165	.llvm_name = "cortex-a73",
	1166	.omit_deps = &.{"crypto"},
1230	1167	},
1231	1168	.{
1232		.llvm_name = null,
1233		.zig_name = "pa_7100lc",
1234		.features = &.{
1235		"max_1",
1236		"v1_1",
1237		},
	1169	.llvm_name = "cortex-a76",
	1170	.omit_deps = &.{"crypto"},
1238	1171	},
1239	1172	.{
1240		.llvm_name = null,
1241		.zig_name = "pa_7200",
1242		.features = &.{
1243		"v1_1",
1244		},
	1173	.llvm_name = "cortex-a76ae",
	1174	.omit_deps = &.{"crypto"},
1245	1175	},
1246	1176	.{
1247		.llvm_name = null,
1248		.zig_name = "pa_7300lc",
1249		.features = &.{
1250		"max_1",
1251		"v1_1",
1252		},
	1177	.llvm_name = "cortex-a77",
	1178	.omit_deps = &.{"crypto"},
1253	1179	},
1254	1180	.{
1255		.llvm_name = null,
1256		.zig_name = "pa_8000",
1257		.features = &.{
1258		"64bit",
1259		},
	1181	.llvm_name = "cortex-a78",
	1182	.omit_deps = &.{"crypto"},
1260	1183	},
1261	1184	.{
1262		.llvm_name = null,
1263		.zig_name = "pa_8200",
1264		.features = &.{
1265		"64bit",
1266		},
	1185	.llvm_name = "cortex-a78ae",
	1186	.omit_deps = &.{"crypto"},
1267	1187	},
1268	1188	.{
1269		.llvm_name = null,
1270		.zig_name = "pa_8500",
1271		.features = &.{
1272		"64bit",
1273		},
	1189	.llvm_name = "cortex-a78c",
	1190	.omit_deps = &.{"crypto"},
1274	1191	},
1275	1192	.{
1276		.llvm_name = null,
1277		.zig_name = "pa_8600",
1278		.features = &.{
1279		"64bit",
1280		},
	1193	.llvm_name = "cortex-m4",
	1194	.omit_deps = &.{"vfp4d16sp"},
1281	1195	},
1282	1196	.{
1283		.llvm_name = null,
1284		.zig_name = "pa_8700",
1285		.features = &.{
1286		"64bit",
1287		},
	1197	.llvm_name = "cortex-m7",
	1198	.omit_deps = &.{"fp_armv8d16"},
1288	1199	},
1289	1200	.{
1290		.llvm_name = null,
1291		.zig_name = "pa_8800",
1292		.features = &.{
1293		"64bit",
1294		},
	1201	.llvm_name = "cortex-m33",
	1202	.omit_deps = &.{ "dsp", "fp_armv8d16sp" },
1295	1203	},
1296	1204	.{
1297		.llvm_name = null,
1298		.zig_name = "pa_8900",
1299		.features = &.{
1300		"64bit",
1301		},
	1205	.llvm_name = "cortex-m35p",
	1206	.omit_deps = &.{ "dsp", "fp_armv8d16sp" },
1302	1207	},
1303		},
1304		},
1305		.{
1306		.zig_name = "kvx",
	1208	.{
	1209	.llvm_name = "cortex-m52",
	1210	.omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" },
	1211	},
	1212	.{
	1213	.llvm_name = "cortex-m55",
	1214	.omit_deps = &.{ "fp_armv8d16", "mve_fp" },
	1215	},
	1216	.{
	1217	.llvm_name = "cortex-m85",
	1218	.extra_deps = &.{"8msecext"},
	1219	.omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" },
	1220	},
	1221	.{
	1222	.llvm_name = "cortex-r5",
	1223	.omit_deps = &.{"vfp3d16"},
	1224	},
	1225	.{
	1226	.llvm_name = "cortex-r7",
	1227	.omit_deps = &.{ "fp16", "vfp3d16" },
	1228	},
	1229	.{
	1230	.llvm_name = "cortex-r8",
	1231	.omit_deps = &.{ "fp16", "vfp3d16" },
	1232	},
	1233	.{
	1234	.llvm_name = "cortex-r52",
	1235	.omit_deps = &.{ "fp_armv8", "neon" },
	1236	},
	1237	.{
	1238	.llvm_name = "cortex-r52plus",
	1239	.omit_deps = &.{ "fp_armv8", "neon" },
	1240	},
	1241	.{
	1242	.llvm_name = "cortex-x1",
	1243	.omit_deps = &.{"crypto"},
	1244	},
	1245	.{
	1246	.llvm_name = "cortex-x1c",
	1247	.omit_deps = &.{"crypto"},
	1248	},
	1249	.{
	1250	.llvm_name = "krait",
	1251	.extra_deps = &.{"neon"},
	1252	},
	1253	.{
	1254	.llvm_name = "neoverse-n1",
	1255	.omit_deps = &.{"crypto"},
	1256	},
	1257	.{
	1258	.llvm_name = "neoverse-v1",
	1259	.omit_deps = &.{"crypto"},
	1260	},
	1261	.{
	1262	.llvm_name = "star-mc1",
	1263	.omit_deps = &.{ "dsp", "fp_armv8d16sp" },
	1264	},
	1265	.{
	1266	.llvm_name = "star-mc3",
	1267	.omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" },
	1268	},
	1269	.{
	1270	.llvm_name = "swift",
	1271	.extra_deps = &.{"neon"},
	1272	},
	1273	},
	1274	.extra_models = &.{
	1275	.{
	1276	.llvm_name = "generic",
	1277	.zig_name = "baseline",
	1278	.features = &.{ "v7a", "vfp3d16" },
	1279	},
	1280	.{
	1281	.llvm_name = null,
	1282	.zig_name = "exynos_m1",
	1283	.features = &.{ "v8a", "exynos" },
	1284	},
	1285	.{
	1286	.llvm_name = null,
	1287	.zig_name = "exynos_m2",
	1288	.features = &.{ "v8a", "exynos" },
	1289	},
	1290	.{
	1291	.llvm_name = "cortex-a9",
	1292	.zig_name = "kermit",
	1293	.features = &.{
	1294	"avoid_partial_cpsr",
	1295	"expand_fp_mlx",
	1296	"fp16",
	1297	"mp",
	1298	"muxed_units",
	1299	"neon",
	1300	"neon_fpmovs",
	1301	"prefer_vmovsr",
	1302	"ret_addr_stack",
	1303	"trustzone",
	1304	"v7a",
	1305	"vldn_align",
	1306	"vmlx_forwarding",
	1307	"vmlx_hazards",
	1308	},
	1309	},
	1310	},
	1311	},
	1312	.{
	1313	.zig_name = "avr",
	1314	.llvm = .{
	1315	.name = "AVR",
	1316	.td_name = "AVR",
	1317	},
	1318	},
	1319	.{
	1320	.zig_name = "bpf",
	1321	.llvm = .{
	1322	.name = "BPF",
	1323	.td_name = "BPF",
	1324	},
	1325	.feature_overrides = &.{
	1326	.{
	1327	.llvm_name = "dummy",
	1328	.omit = true,
	1329	},
	1330	.{
	1331	.llvm_name = "dwarfris",
	1332	.omit = true,
	1333	},
	1334	},
	1335	},
	1336	.{
	1337	.zig_name = "csky",
	1338	.llvm = .{
	1339	.name = "CSKY",
	1340	.td_name = "CSKY",
	1341	},
	1342	.feature_overrides = &.{
	1343	.{
	1344	.llvm_name = "ccrt",
	1345	.omit = true,
	1346	},
	1347	.{
	1348	.llvm_name = "constpool",
	1349	.omit = true,
	1350	},
	1351	.{
	1352	.llvm_name = "multiple_stld",
	1353	.omit = true,
	1354	},
	1355	.{
	1356	.llvm_name = "nvic",
	1357	.omit = true,
	1358	},
	1359	.{
	1360	.llvm_name = "pushpop",
	1361	.omit = true,
	1362	},
	1363	.{
	1364	.llvm_name = "smart",
	1365	.omit = true,
	1366	},
	1367	.{
	1368	.llvm_name = "soft_tp",
	1369	.omit = true,
	1370	},
	1371	.{
	1372	.llvm_name = "stack_size",
	1373	.omit = true,
	1374	},
	1375
	1376	.{
	1377	.llvm_name = "ck801",
	1378	.flatten = true,
	1379	},
	1380	.{
	1381	.llvm_name = "ck802",
	1382	.flatten = true,
	1383	},
	1384	.{
	1385	.llvm_name = "ck803",
	1386	.flatten = true,
	1387	},
	1388	.{
	1389	.llvm_name = "ck803s",
	1390	.flatten = true,
	1391	},
	1392	.{
	1393	.llvm_name = "ck804",
	1394	.flatten = true,
	1395	},
	1396	.{
	1397	.llvm_name = "ck805",
	1398	.flatten = true,
	1399	},
	1400	.{
	1401	.llvm_name = "ck807",
	1402	.flatten = true,
	1403	},
	1404	.{
	1405	.llvm_name = "ck810",
	1406	.flatten = true,
	1407	},
	1408	.{
	1409	.llvm_name = "ck810v",
	1410	.flatten = true,
	1411	},
	1412	.{
	1413	.llvm_name = "ck860",
	1414	.flatten = true,
	1415	},
	1416	.{
	1417	.llvm_name = "ck860v",
	1418	.flatten = true,
	1419	},
	1420	},
	1421	},
	1422	.{
	1423	.zig_name = "hexagon",
	1424	.llvm = .{
	1425	.name = "Hexagon",
	1426	.td_name = "Hexagon",
	1427	},
	1428	},
	1429	.{
	1430	.zig_name = "hppa",
	1431	.llvm = null,
	1432	.extra_features = &.{
	1433	.{
	1434	.zig_name = "max_1",
	1435	.desc = "Enable MAX-1 multimedia acceleration extensions",
	1436	.deps = &.{},
	1437	},
	1438	.{
	1439	.zig_name = "max_2",
	1440	.desc = "Enable MAX-2 multimedia acceleration extensions",
	1441	.deps = &.{"max_1"},
	1442	},
	1443	.{
	1444	.zig_name = "v1_1",
	1445	.desc = "Enable ISA v1.1",
	1446	.deps = &.{},
	1447	},
	1448	.{
	1449	.zig_name = "v2_0",
	1450	.desc = "Enable ISA v2.0",
	1451	.deps = &.{ "max_2", "v1_1" },
	1452	},
	1453	},
	1454	.extra_models = &.{
	1455	.{
	1456	.llvm_name = null,
	1457	.zig_name = "ts_1",
	1458	.features = &.{},
	1459	},
	1460	.{
	1461	.llvm_name = null,
	1462	.zig_name = "ns_1",
	1463	.features = &.{},
	1464	},
	1465	.{
	1466	.llvm_name = null,
	1467	.zig_name = "ns_2",
	1468	.features = &.{},
	1469	},
	1470	.{
	1471	.llvm_name = null,
	1472	.zig_name = "pcx",
	1473	.features = &.{},
	1474	},
	1475	.{
	1476	.llvm_name = null,
	1477	.zig_name = "pa_7000",
	1478	.features = &.{
	1479	"v1_1",
	1480	},
	1481	},
	1482	.{
	1483	.llvm_name = null,
	1484	.zig_name = "pa_7100",
	1485	.features = &.{
	1486	"v1_1",
	1487	},
	1488	},
	1489	.{
	1490	.llvm_name = null,
	1491	.zig_name = "pa_7150",
	1492	.features = &.{
	1493	"v1_1",
	1494	},
	1495	},
	1496	.{
	1497	.llvm_name = null,
	1498	.zig_name = "pa_7100lc",
	1499	.features = &.{
	1500	"max_1",
	1501	"v1_1",
	1502	},
	1503	},
	1504	.{
	1505	.llvm_name = null,
	1506	.zig_name = "pa_7200",
	1507	.features = &.{
	1508	"v1_1",
	1509	},
	1510	},
	1511	.{
	1512	.llvm_name = null,
	1513	.zig_name = "pa_7300lc",
	1514	.features = &.{
	1515	"max_1",
	1516	"v1_1",
	1517	},
	1518	},
	1519	.{
	1520	.llvm_name = null,
	1521	.zig_name = "pa_8000",
	1522	.features = &.{
	1523	"v2_0",
	1524	},
	1525	},
	1526	.{
	1527	.llvm_name = null,
	1528	.zig_name = "pa_8200",
	1529	.features = &.{
	1530	"v2_0",
	1531	},
	1532	},
	1533	.{
	1534	.llvm_name = null,
	1535	.zig_name = "pa_8500",
	1536	.features = &.{
	1537	"v2_0",
	1538	},
	1539	},
	1540	.{
	1541	.llvm_name = null,
	1542	.zig_name = "pa_8600",
	1543	.features = &.{
	1544	"v2_0",
	1545	},
	1546	},
	1547	.{
	1548	.llvm_name = null,
	1549	.zig_name = "pa_8700",
	1550	.features = &.{
	1551	"v2_0",
	1552	},
	1553	},
	1554	.{
	1555	.llvm_name = null,
	1556	.zig_name = "pa_8800",
	1557	.features = &.{
	1558	"v2_0",
	1559	},
	1560	},
	1561	.{
	1562	.llvm_name = null,
	1563	.zig_name = "pa_8900",
	1564	.features = &.{
	1565	"v2_0",
	1566	},
	1567	},
	1568	},
	1569	},
	1570	.{
	1571	.zig_name = "kvx",
1307	1572	.llvm = null,
1308	1573	.extra_features = &.{
1309	1574	.{
...	...	@@ -1314,7 +1579,7 @@ const targets = [_]ArchTarget{
1314	1579	.{
1315	1580	.zig_name = "v3_2",
1316	1581	.desc = "Enable ISA v3.2",
1317		.deps = &.{"v3_1"},
	1582	.deps = &.{},
1318	1583	},
1319	1584	.{
1320	1585	.zig_name = "v4_1",
...	...	@@ -1322,7 +1587,7 @@ const targets = [_]ArchTarget{
1322	1587	.deps = &.{"v3_2"},
1323	1588	},
1324	1589	},
1325		.extra_cpus = &.{
	1590	.extra_models = &.{
1326	1591	.{
1327	1592	.llvm_name = null,
1328	1593	.zig_name = "coolidge_v1",
...	...	@@ -1352,7 +1617,25 @@ const targets = [_]ArchTarget{
1352	1617	.name = "LoongArch",
1353	1618	.td_name = "LoongArch",
1354	1619	},
1355		.extra_cpus = &.{
	1620	.model_overrides = &.{
	1621	.{
	1622	.llvm_name = "generic",
	1623	.omit = true,
	1624	},
	1625	.{
	1626	.llvm_name = "generic-la64",
	1627	.omit = true,
	1628	},
	1629	.{
	1630	.llvm_name = "loongarch32",
	1631	.omit = true,
	1632	},
	1633	.{
	1634	.llvm_name = "loongarch64",
	1635	.omit = true,
	1636	},
	1637	},
	1638	.extra_models = &.{
1356	1639	.{
1357	1640	.llvm_name = null,
1358	1641	.zig_name = "generic_la64",
...	...	@@ -1403,12 +1686,6 @@ const targets = [_]ArchTarget{
1403	1686	},
1404	1687	},
1405	1688	},
1406		.omit_cpus = &.{
1407		"generic",
1408		"generic-la64",
1409		"loongarch32",
1410		"loongarch64",
1411		},
1412	1689	},
1413	1690	.{
1414	1691	.zig_name = "m68k",
...	...	@@ -1437,7 +1714,7 @@ const targets = [_]ArchTarget{
1437	1714	.deps = &.{},
1438	1715	},
1439	1716	},
1440		.extra_cpus = &.{
	1717	.extra_models = &.{
1441	1718	.{
1442	1719	.llvm_name = null,
1443	1720	.zig_name = "r3000a",
...	...	@@ -1489,7 +1766,13 @@ const targets = [_]ArchTarget{
1489	1766	.omit = true,
1490	1767	},
1491	1768	},
1492		.extra_cpus = &.{
	1769	.model_overrides = &.{
	1770	.{
	1771	.llvm_name = "ppc32",
	1772	.omit = true,
	1773	},
	1774	},
	1775	.extra_models = &.{
1493	1776	.{
1494	1777	.llvm_name = null,
1495	1778	.zig_name = "cell",
...	...	@@ -1525,9 +1808,6 @@ const targets = [_]ArchTarget{
1525	1808	},
1526	1809	},
1527	1810	},
1528		.omit_cpus = &.{
1529		"ppc32",
1530		},
1531	1811	},
1532	1812	.{
1533	1813	.zig_name = "propeller",
...	...	@@ -1539,7 +1819,7 @@ const targets = [_]ArchTarget{
1539	1819	.deps = &.{},
1540	1820	},
1541	1821	},
1542		.extra_cpus = &.{
	1822	.extra_models = &.{
1543	1823	.{
1544	1824	.llvm_name = null,
1545	1825	.zig_name = "p1",
...	...	@@ -1560,7 +1840,7 @@ const targets = [_]ArchTarget{
1560	1840	},
1561	1841	.branch_quota = 2000,
1562	1842	.extra_features = spirv_extra_features,
1563		.extra_cpus = &.{
	1843	.extra_models = &.{
1564	1844	.{
1565	1845	.llvm_name = null,
1566	1846	.zig_name = "vulkan_v1_2",
...	...	@@ -1586,7 +1866,7 @@ const targets = [_]ArchTarget{
1586	1866	.flatten = true,
1587	1867	},
1588	1868	},
1589		.extra_cpus = &.{
	1869	.extra_models = &.{
1590	1870	.{
1591	1871	.llvm_name = null,
1592	1872	.zig_name = "baseline_rv32",
...	...	@@ -1619,6 +1899,36 @@ const targets = [_]ArchTarget{
1619	1899	.name = "VE",
1620	1900	.td_name = "VE",
1621	1901	},
	1902	.extra_features = &.{
	1903	.{
	1904	.zig_name = "ve3",
	1905	.desc = "Enable VE3 instructions",
	1906	.deps = &.{},
	1907	},
	1908	},
	1909	.model_overrides = &.{
	1910	.{
	1911	.llvm_name = "generic",
	1912	.omit = true,
	1913	},
	1914	},
	1915	.extra_models = &.{
	1916	.{
	1917	.llvm_name = null,
	1918	.zig_name = "ve10",
	1919	.features = &.{"vpu"},
	1920	},
	1921	.{
	1922	.llvm_name = null,
	1923	.zig_name = "ve20",
	1924	.features = &.{"vpu"},
	1925	},
	1926	.{
	1927	.llvm_name = null,
	1928	.zig_name = "ve30",
	1929	.features = &.{ "ve3", "vpu" },
	1930	},
	1931	},
1622	1932	},
1623	1933	.{
1624	1934	.zig_name = "wasm",
...	...	@@ -1633,9 +1943,17 @@ const targets = [_]ArchTarget{
1633	1943	.llvm_name = "bulk-memory",
1634	1944	.extra_deps = &.{"bulk_memory_opt"},
1635	1945	},
	1946	.{
	1947	.llvm_name = "f16",
	1948	.extra_deps = &.{"simd128"},
	1949	},
1636	1950	.{
1637	1951	.llvm_name = "reference-types",
1638		.extra_deps = &.{"call_indirect_overlong"},
	1952	.extra_deps = &.{ "bulk_memory", "call_indirect_overlong" },
	1953	},
	1954	.{
	1955	.llvm_name = "relaxed-simd",
	1956	.extra_deps = &.{"simd128"},
1639	1957	},
1640	1958	},
1641	1959	.extra_features = &.{
...	...	@@ -1645,6 +1963,54 @@ const targets = [_]ArchTarget{
1645	1963	.deps = &.{"bulk_memory_opt"},
1646	1964	},
1647	1965	},
	1966	.model_overrides = &.{
	1967	.{
	1968	.llvm_name = "bleeding-edge",
	1969	.omit = true,
	1970	},
	1971	.{
	1972	.llvm_name = "generic",
	1973	.omit = true,
	1974	},
	1975	},
	1976	.extra_models = &.{
	1977	.{
	1978	.llvm_name = null,
	1979	.zig_name = "wasm_v1_0",
	1980	.features = &.{
	1981	"mutable_globals",
	1982	},
	1983	},
	1984	.{
	1985	.llvm_name = null,
	1986	.zig_name = "wasm_v2_0",
	1987	.features = &.{
	1988	"multivalue",
	1989	"mutable_globals",
	1990	"nontrapping_fptoint",
	1991	"reference_types",
	1992	"sign_ext",
	1993	"simd128",
	1994	},
	1995	},
	1996	.{
	1997	.llvm_name = null,
	1998	.zig_name = "wasm_v3_0",
	1999	.features = &.{
	2000	"atomics",
	2001	"exception_handling",
	2002	"extended_const",
	2003	"fp16",
	2004	"gc",
	2005	"multimemory",
	2006	"mutable_globals",
	2007	"nontrapping_fptoint",
	2008	"relaxed_simd",
	2009	"sign_ext",
	2010	"tail_call",
	2011	},
	2012	},
	2013	},
1648	2014	},
1649	2015	.{
1650	2016	.zig_name = "x86",
...	...	@@ -1670,20 +2036,58 @@ const targets = [_]ArchTarget{
1670	2036	.omit = true,
1671	2037	},
1672	2038	.{
1673		.llvm_name = "alderlake",
1674		.extra_deps = &.{ "smap", "smep" },
	2039	.llvm_name = "sse4.2",
	2040	.extra_deps = &.{"crc32"},
1675	2041	},
	2042	},
	2043	.extra_features = &.{
	2044	// Features removed from LLVM
1676	2045	.{
1677		.llvm_name = "amdfam10",
1678		.extra_deps = &.{"3dnowa"},
	2046	.zig_name = "3dnow",
	2047	.desc = "Enable 3DNow! instructions",
	2048	.deps = &.{"mmx"},
1679	2049	},
1680	2050	.{
1681		.llvm_name = "arrowlake",
1682		.extra_deps = &.{ "smap", "smep" },
	2051	.zig_name = "3dnowa",
	2052	.desc = "Enable 3DNow! Athlon instructions",
	2053	.deps = &.{"3dnow"},
1683	2054	},
1684	2055	.{
1685		.llvm_name = "arrowlake-s",
1686		.extra_deps = &.{ "smap", "smep" },
	2056	.zig_name = "avx512er",
	2057	.desc = "Enable AVX-512 Exponential and Reciprocal Instructions",
	2058	.deps = &.{"avx512f"},
	2059	},
	2060	.{
	2061	.zig_name = "avx512pf",
	2062	.desc = "Enable AVX-512 PreFetch Instructions",
	2063	.deps = &.{"avx512f"},
	2064	},
	2065	.{
	2066	.zig_name = "prefetchwt1",
	2067	.desc = "Prefetch with Intent to Write and T1 Hint",
	2068	.deps = &.{},
	2069	},
	2070	// Custom Zig features
	2071	.{
	2072	.zig_name = "bsf_bsr_0_clobbers_result",
	2073	.desc = "BSF/BSR may clobber the lower 32-bits of the result register when the source is zero",
	2074	.deps = &.{},
	2075	},
	2076	.{
	2077	.zig_name = "smap",
	2078	.desc = "Enable Supervisor Mode Access Prevention",
	2079	.deps = &.{},
	2080	},
	2081	.{
	2082	.zig_name = "smep",
	2083	.desc = "Enable Supervisor Mode Execution Prevention",
	2084	.deps = &.{},
	2085	},
	2086	},
	2087	.model_overrides = &.{
	2088	.{
	2089	.llvm_name = "amdfam10",
	2090	.extra_deps = &.{"3dnowa"},
1687	2091	},
1688	2092	.{
1689	2093	.llvm_name = "athlon",
...	...	@@ -1862,8 +2266,16 @@ const targets = [_]ArchTarget{
1862	2266	.extra_deps = &.{"3dnow"},
1863	2267	},
1864	2268	.{
1865		.llvm_name = "sse4.2",
1866		.extra_deps = &.{"crc32"},
	2269	.llvm_name = "alderlake",
	2270	.extra_deps = &.{ "smap", "smep" },
	2271	},
	2272	.{
	2273	.llvm_name = "arrowlake",
	2274	.extra_deps = &.{ "smap", "smep" },
	2275	},
	2276	.{
	2277	.llvm_name = "arrowlake-s",
	2278	.extra_deps = &.{ "smap", "smep" },
1867	2279	},
1868	2280	.{
1869	2281	.llvm_name = "znver1",
...	...	@@ -1885,92 +2297,140 @@ const targets = [_]ArchTarget{
1885	2297	.llvm_name = "znver5",
1886	2298	.extra_deps = &.{ "smap", "smep" },
1887	2299	},
1888		},
1889		.extra_features = &.{
1890		// Features removed from LLVM
	2300
	2301	// LLVM defines a bunch of dumb aliases with foreach loops in X86.td.
1891	2302	.{
1892		.zig_name = "3dnow",
1893		.desc = "Enable 3DNow! instructions",
1894		.deps = &.{"mmx"},
	2303	.llvm_name = "pentium_mmx",
	2304	.omit = true,
1895	2305	},
1896	2306	.{
1897		.zig_name = "3dnowa",
1898		.desc = "Enable 3DNow! Athlon instructions",
1899		.deps = &.{"3dnow"},
	2307	.llvm_name = "pentium_pro",
	2308	.omit = true,
1900	2309	},
1901	2310	.{
1902		.zig_name = "avx512er",
1903		.desc = "Enable AVX-512 Exponential and Reciprocal Instructions",
1904		.deps = &.{"avx512f"},
	2311	.llvm_name = "pentium_ii",
	2312	.omit = true,
1905	2313	},
1906	2314	.{
1907		.zig_name = "avx512pf",
1908		.desc = "Enable AVX-512 PreFetch Instructions",
1909		.deps = &.{"avx512f"},
	2315	.llvm_name = "pentium_3m",
	2316	.omit = true,
1910	2317	},
1911	2318	.{
1912		.zig_name = "prefetchwt1",
1913		.desc = "Prefetch with Intent to Write and T1 Hint",
1914		.deps = &.{},
	2319	.llvm_name = "pentium_iii",
	2320	.omit = true,
1915	2321	},
1916		// Custom Zig features
1917	2322	.{
1918		.zig_name = "bsf_bsr_0_clobbers_result",
1919		.desc = "BSF/BSR may clobber the lower 32-bits of the result register when the source is zero",
1920		.deps = &.{},
	2323	.llvm_name = "pentium_iii_no_xmm_regs",
	2324	.omit = true,
1921	2325	},
1922	2326	.{
1923		.zig_name = "smap",
1924		.desc = "Enable Supervisor Mode Access Prevention",
1925		.deps = &.{},
	2327	.llvm_name = "pentium_m",
	2328	.omit = true,
1926	2329	},
1927	2330	.{
1928		.zig_name = "smep",
1929		.desc = "Enable Supervisor Mode Execution Prevention",
1930		.deps = &.{},
	2331	.llvm_name = "pentium4m",
	2332	.omit = true,
	2333	},
	2334	.{
	2335	.llvm_name = "pentium_4",
	2336	.omit = true,
	2337	},
	2338	.{
	2339	.llvm_name = "pentium_4_sse3",
	2340	.omit = true,
	2341	},
	2342	.{
	2343	.llvm_name = "core_2_duo_ssse3",
	2344	.omit = true,
	2345	},
	2346	.{
	2347	.llvm_name = "core_2_duo_sse4_1",
	2348	.omit = true,
	2349	},
	2350	.{
	2351	.llvm_name = "atom_sse4_2",
	2352	.omit = true,
	2353	},
	2354	.{
	2355	.llvm_name = "goldmont-plus",
	2356	.omit = true,
	2357	},
	2358	.{
	2359	.llvm_name = "core_i7_sse4_2",
	2360	.omit = true,
	2361	},
	2362	.{
	2363	.llvm_name = "core_aes_pclmulqdq",
	2364	.omit = true,
	2365	},
	2366	.{
	2367	.llvm_name = "corei7-avx",
	2368	.omit = true,
	2369	},
	2370	.{
	2371	.llvm_name = "core_2nd_gen_avx",
	2372	.omit = true,
	2373	},
	2374	.{
	2375	.llvm_name = "core-avx-i",
	2376	.omit = true,
	2377	},
	2378	.{
	2379	.llvm_name = "core_3rd_gen_avx",
	2380	.omit = true,
	2381	},
	2382	.{
	2383	.llvm_name = "core-avx2",
	2384	.omit = true,
	2385	},
	2386	.{
	2387	.llvm_name = "core_4th_gen_avx",
	2388	.omit = true,
	2389	},
	2390	.{
	2391	.llvm_name = "core_4th_gen_avx_tsx",
	2392	.omit = true,
	2393	},
	2394	.{
	2395	.llvm_name = "core_5th_gen_avx",
	2396	.omit = true,
	2397	},
	2398	.{
	2399	.llvm_name = "core_5th_gen_avx_tsx",
	2400	.omit = true,
	2401	},
	2402	.{
	2403	.llvm_name = "mic_avx512",
	2404	.omit = true,
	2405	},
	2406	.{
	2407	.llvm_name = "skylake-avx512",
	2408	.omit = true,
	2409	},
	2410	.{
	2411	.llvm_name = "icelake-client",
	2412	.omit = true,
	2413	},
	2414	.{
	2415	.llvm_name = "icelake-server",
	2416	.omit = true,
	2417	},
	2418	.{
	2419	.llvm_name = "graniterapids_d",
	2420	.omit = true,
	2421	},
	2422	.{
	2423	.llvm_name = "arrowlake_s",
	2424	.omit = true,
1931	2425	},
1932	2426	},
1933		.extra_cpus = &.{
	2427	.extra_models = &.{
1934	2428	.{
1935	2429	.llvm_name = null,
1936	2430	.zig_name = "i86",
1937	2431	.features = &.{"16bit_mode"},
1938	2432	},
1939	2433	},
1940		.omit_cpus = &.{
1941		// LLVM defines a bunch of dumb aliases with foreach loops in X86.td.
1942		"pentium_mmx",
1943		"pentium_pro",
1944		"pentium_ii",
1945		"pentium_3m",
1946		"pentium_iii_no_xmm_regs",
1947		"pentium_iii",
1948		"pentium_m",
1949		"pentium4m",
1950		"pentium_4",
1951		"pentium_4_sse3",
1952		"core_2_duo_ssse3",
1953		"core_2_duo_sse4_1",
1954		"atom_sse4_2",
1955		"goldmont_plus",
1956		"core_i7_sse4_2",
1957		"core_aes_pclmulqdq",
1958		"corei7-avx",
1959		"core_2nd_gen_avx",
1960		"core-avx-i",
1961		"core_3rd_gen_avx",
1962		"core-avx2",
1963		"core_4th_gen_avx",
1964		"core_4th_gen_avx_tsx",
1965		"core_5th_gen_avx",
1966		"core_5th_gen_avx_tsx",
1967		"mic_avx512",
1968		"skylake_avx512",
1969		"icelake_client",
1970		"icelake_server",
1971		"graniterapids_d",
1972		"arrowlake_s",
1973		},
1974	2434	},
1975	2435	.{
1976	2436	.zig_name = "xcore",
...	...	@@ -1978,6 +2438,55 @@ const targets = [_]ArchTarget{
1978	2438	.name = "XCore",
1979	2439	.td_name = "XCore",
1980	2440	},
	2441	.extra_features = &.{
	2442	.{
	2443	.zig_name = "xs2",
	2444	.desc = "Enable XS2 architecture",
	2445	.deps = &.{},
	2446	},
	2447	.{
	2448	.zig_name = "xs3",
	2449	.desc = "Enable XS3 architecture",
	2450	.deps = &.{"xs2"},
	2451	},
	2452	.{
	2453	.zig_name = "fpu",
	2454	.desc = "Enable single-precision floating point unit",
	2455	.deps = &.{"xs3"},
	2456	},
	2457	.{
	2458	.zig_name = "vpu",
	2459	.desc = "Enable vector processing unit",
	2460	.deps = &.{"xs3"},
	2461	},
	2462	},
	2463	.model_overrides = &.{
	2464	.{
	2465	.llvm_name = "generic",
	2466	.omit = true,
	2467	},
	2468	.{
	2469	.llvm_name = "xs1b-generic",
	2470	.omit = true,
	2471	},
	2472	},
	2473	.extra_models = &.{
	2474	.{
	2475	.llvm_name = null,
	2476	.zig_name = "xs1b",
	2477	.features = &.{},
	2478	},
	2479	.{
	2480	.llvm_name = null,
	2481	.zig_name = "xs2a",
	2482	.features = &.{"xs2"},
	2483	},
	2484	.{
	2485	.llvm_name = null,
	2486	.zig_name = "xs3a",
	2487	.features = &.{ "fpu", "vpu" },
	2488	},
	2489	},
1981	2490	},
1982	2491	.{
1983	2492	.zig_name = "xtensa",
...	...	@@ -2073,7 +2582,7 @@ fn processOneTargetInner(io: Io, job: Job) !void {
2073	2582
2074	2583	var features_table = std.StringHashMap(Feature).init(arena);
2075	2584	var all_features = std.array_list.Managed(Feature).init(arena);
2076		var all_cpus = std.array_list.Managed(Cpu).init(arena);
	2585	var all_models = std.array_list.Managed(Model).init(arena);
2077	2586
2078	2587	if (target.llvm) \|llvm\| {
2079	2588	const tblgen_progress = progress_node.start("running llvm-tblgen", 0);
...	...	@@ -2133,7 +2642,7 @@ fn processOneTargetInner(io: Io, job: Job) !void {
2133	2642	llvm: []const u8,
2134	2643	zig: []const u8,
2135	2644	};
2136		var cpu_aliases = std.StringHashMap(std.ArrayList(*Alias)).init(arena);
	2645	var model_aliases = std.StringHashMap(std.ArrayList(*Alias)).init(arena);
2137	2646
2138	2647	{
2139	2648	var it = root_map.iterator();
...	...	@@ -2147,7 +2656,7 @@ fn processOneTargetInner(io: Io, job: Job) !void {
2147	2656	const llvm_alias = kv.value_ptr.object.get("Name").?.string;
2148	2657	const llvm_name = kv.value_ptr.object.get("Alias").?.string;
2149	2658
2150		const gop = try cpu_aliases.getOrPut(try llvmNameToZigName(arena, llvm_name));
	2659	const gop = try model_aliases.getOrPut(try llvmNameToZigName(arena, llvm_name));
2151	2660
2152	2661	if (!gop.found_existing) {
2153	2662	gop.value_ptr.* = .empty;
...	...	@@ -2253,28 +2762,25 @@ fn processOneTargetInner(io: Io, job: Job) !void {
2253	2762	if (hasSuperclass(&kv.value_ptr.object, "Processor")) {
2254	2763	const llvm_name = kv.value_ptr.object.get("Name").?.string;
2255	2764	if (llvm_name.len == 0) continue;
2256		const omitted = for (target.omit_cpus) \|omit_cpu_name\| {
2257		if (mem.eql(u8, omit_cpu_name, llvm_name)) break true;
2258		} else false;
2259		if (omitted) continue;
2260	2765
2261	2766	var zig_name = try llvmNameToZigName(arena, llvm_name);
2262	2767	var deps = std.array_list.Managed([]const u8).init(arena);
2263	2768	var omit_deps: []const []const u8 = &.{};
2264	2769	var extra_deps: []const []const u8 = &.{};
2265		for (target.feature_overrides) \|feature_override\| {
2266		if (mem.eql(u8, llvm_name, feature_override.llvm_name)) {
2267		if (feature_override.omit) {
2268		continue;
	2770	const omitted = for (target.model_overrides) \|model_override\| {
	2771	if (mem.eql(u8, llvm_name, model_override.llvm_name)) {
	2772	if (model_override.omit) {
	2773	break true;
2269	2774	}
2270		if (feature_override.zig_name) \|override_name\| {
	2775	if (model_override.zig_name) \|override_name\| {
2271	2776	zig_name = override_name;
2272	2777	}
2273		omit_deps = feature_override.omit_deps;
2274		extra_deps = feature_override.extra_deps;
2275		break;
	2778	omit_deps = model_override.omit_deps;
	2779	extra_deps = model_override.extra_deps;
	2780	break false;
2276	2781	}
2277		}
	2782	} else false;
	2783	if (omitted) continue;
2278	2784	const features = kv.value_ptr.object.get("Features").?.array;
2279	2785	for (features.items) \|feature\| {
2280	2786	const feature_key = feature.object.get("def").?.string;
...	...	@@ -2308,19 +2814,19 @@ fn processOneTargetInner(io: Io, job: Job) !void {
2308	2814	)) orelse continue;
2309	2815	try deps.append(feature_zig_name);
2310	2816	}
2311		try all_cpus.append(.{
	2817	try all_models.append(.{
2312	2818	.llvm_name = llvm_name,
2313	2819	.zig_name = zig_name,
2314	2820	.features = deps.items,
2315	2821	});
2316	2822
2317		if (cpu_aliases.get(zig_name)) \|aliases\| {
	2823	if (model_aliases.get(zig_name)) \|aliases\| {
2318	2824	alias_it: for (aliases.items) \|alias\| {
2319		for (target.omit_cpus) \|omit_cpu_name\| {
2320		if (mem.eql(u8, omit_cpu_name, alias.llvm)) continue :alias_it;
	2825	for (target.model_overrides) \|model_override\| {
	2826	if (mem.eql(u8, alias.llvm, model_override.llvm_name) and model_override.omit) continue :alias_it;
2321	2827	}
2322	2828
2323		try all_cpus.append(.{
	2829	try all_models.append(.{
2324	2830	.llvm_name = alias.llvm,
2325	2831	.zig_name = alias.zig,
2326	2832	.features = deps.items,
...	...	@@ -2338,11 +2844,11 @@ fn processOneTargetInner(io: Io, job: Job) !void {
2338	2844	try features_table.put(extra_feature.zig_name, extra_feature);
2339	2845	try all_features.append(extra_feature);
2340	2846	}
2341		for (target.extra_cpus) \|extra_cpu\| {
2342		try all_cpus.append(extra_cpu);
	2847	for (target.extra_models) \|extra_model\| {
	2848	try all_models.append(extra_model);
2343	2849	}
2344	2850	mem.sort(Feature, all_features.items, {}, featureLessThan);
2345		mem.sort(Cpu, all_cpus.items, {}, cpuLessThan);
	2851	mem.sort(Model, all_models.items, {}, modelLessThan);
2346	2852
2347	2853	const render_progress = progress_node.start("rendering Zig code", 0);
2348	2854
...	...	@@ -2465,29 +2971,29 @@ fn processOneTargetInner(io: Io, job: Job) !void {
2465	2971	\\pub const cpu = struct {
2466	2972	\\
2467	2973	);
2468		for (all_cpus.items) \|cpu\| {
	2974	for (all_models.items) \|model\| {
2469	2975	var deps_set = std.StringHashMap(void).init(arena);
2470		for (cpu.features) \|feature_zig_name\| {
	2976	for (model.features) \|feature_zig_name\| {
2471	2977	try putDep(&deps_set, features_table, feature_zig_name);
2472	2978	}
2473	2979	try pruneFeatures(arena, features_table, &deps_set);
2474		var cpu_features = std.array_list.Managed([]const u8).init(arena);
	2980	var model_features = std.array_list.Managed([]const u8).init(arena);
2475	2981	{
2476	2982	var it = deps_set.keyIterator();
2477	2983	while (it.next()) \|key\| {
2478		try cpu_features.append(key.*);
	2984	try model_features.append(key.*);
2479	2985	}
2480	2986	}
2481		mem.sort([]const u8, cpu_features.items, {}, asciiLessThan);
2482		if (cpu.llvm_name) \|llvm_name\| {
	2987	mem.sort([]const u8, model_features.items, {}, asciiLessThan);
	2988	if (model.llvm_name) \|llvm_name\| {
2483	2989	try w.print(
2484	2990	\\ pub const {f}: CpuModel = .{{
2485	2991	\\ .name = "{f}",
2486	2992	\\ .llvm_name = "{f}",
2487	2993	\\ .features = featureSet(&[_]Feature{{
2488	2994	, .{
2489		std.zig.fmtId(cpu.zig_name),
2490		std.zig.fmtString(cpu.zig_name),
	2995	std.zig.fmtId(model.zig_name),
	2996	std.zig.fmtString(model.zig_name),
2491	2997	std.zig.fmtString(llvm_name),
2492	2998	});
2493	2999	} else {
...	...	@@ -2497,11 +3003,11 @@ fn processOneTargetInner(io: Io, job: Job) !void {
2497	3003	\\ .llvm_name = null,
2498	3004	\\ .features = featureSet(&[_]Feature{{
2499	3005	, .{
2500		std.zig.fmtId(cpu.zig_name),
2501		std.zig.fmtString(cpu.zig_name),
	3006	std.zig.fmtId(model.zig_name),
	3007	std.zig.fmtString(model.zig_name),
2502	3008	});
2503	3009	}
2504		if (cpu_features.items.len == 0) {
	3010	if (model_features.items.len == 0) {
2505	3011	try w.writeAll(
2506	3012	\\}),
2507	3013	\\ };
...	...	@@ -2509,7 +3015,7 @@ fn processOneTargetInner(io: Io, job: Job) !void {
2509	3015	);
2510	3016	} else {
2511	3017	try w.writeAll("\n");
2512		for (cpu_features.items) \|feature_zig_name\| {
	3018	for (model_features.items) \|feature_zig_name\| {
2513	3019	try w.print(" .{f},\n", .{std.zig.fmtIdPU(feature_zig_name)});
2514	3020	}
2515	3021	try w.writeAll(
...	...	@@ -2547,7 +3053,7 @@ fn featureLessThan(_: void, a: Feature, b: Feature) bool {
2547	3053	return std.ascii.lessThanIgnoreCase(a.zig_name, b.zig_name);
2548	3054	}
2549	3055
2550		fn cpuLessThan(_: void, a: Cpu, b: Cpu) bool {
	3056	fn modelLessThan(_: void, a: Model, b: Model) bool {
2551	3057	return std.ascii.lessThanIgnoreCase(a.zig_name, b.zig_name);
2552	3058	}
2553	3059