| author |  Alex Rønne Petersen <alex@alexrp.com> 2024-07-21 14:13:37+02:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2024-07-21 22:38:30+02:00 |
| log | 21cc5a20440e41a0f8b53b5eeac4ba5da55b64bf |
| tree | 15b67e5278531300dfda8f2814e405dc8dc59549 |
| parent | f1e0c35db4167b8cc5a70d2270028287e737fff4 |
| signature |  Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
std.Target: Remove the `shave` arch tag.
This was added as an architecture to LLVM's target triple parser and the Clang
driver in 2015. No backend ever materialized as far as I can see (same for GCC).
In 2016, other code referring to it started using "Myriad" instead. Ultimately,
all code related to it that isn't in the target triple parser was removed. It
seems to be a real product, just... literally no one seems to know anything
about the ISA. I figure after almost a decade with no public ISA documentation
to speak of, and no LLVM backend to reference, it's probably safe to assume that
we're not going to learn much about this ISA, making it useless for Zig.
See: https://github.com/llvm/llvm-project/commit/1b5767f72b5a037ca8f1802d737de97f8d92263d
See: https://github.com/llvm/llvm-project/commit/84a7564b28360843ee9afec5d3823c89623eb6a5
See: https://github.com/llvm/llvm-project/commit/8cfe9d8f2ad3a52ba7fd5841d3939aa810536e166 files changed, 0 insertions(+), 17 deletions(-)
lib- compiler
- aro
- aro
- std
- src
lib/compiler/aro/aro/target.zig-3
| ... | @@ -482,7 +482,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { | ... | @@ -482,7 +482,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { |
| 482 | .nvptx, | 482 | .nvptx, |
| 483 | .spir, | 483 | .spir, |
| 484 | .kalimba, | 484 | .kalimba, |
| 485 | .shave, | ||
| 486 | .lanai, | 485 | .lanai, |
| 487 | .wasm32, | 486 | .wasm32, |
| 488 | .aarch64_32, | 487 | .aarch64_32, |
| ... | @@ -522,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { | ... | @@ -522,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { |
| 522 | .lanai, | 521 | .lanai, |
| 523 | .m68k, | 522 | .m68k, |
| 524 | .msp430, | 523 | .msp430, |
| 525 | .shave, | ||
| 526 | .sparcel, | 524 | .sparcel, |
| 527 | .spu_2, | 525 | .spu_2, |
| 528 | .tce, | 526 | .tce, |
| ... | @@ -628,7 +626,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { | ... | @@ -628,7 +626,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { |
| 628 | .spirv32 => "spirv32", | 626 | .spirv32 => "spirv32", |
| 629 | .spirv64 => "spirv64", | 627 | .spirv64 => "spirv64", |
| 630 | .kalimba => "kalimba", | 628 | .kalimba => "kalimba", |
| 631 | .shave => "shave", | ||
| 632 | .lanai => "lanai", | 629 | .lanai => "lanai", |
| 633 | .wasm32 => "wasm32", | 630 | .wasm32 => "wasm32", |
| 634 | .wasm64 => "wasm64", | 631 | .wasm64 => "wasm64", |
lib/std/Target.zig-8
| ... | @@ -1017,7 +1017,6 @@ pub const Cpu = struct { | ... | @@ -1017,7 +1017,6 @@ pub const Cpu = struct { |
| 1017 | spirv32, | 1017 | spirv32, |
| 1018 | spirv64, | 1018 | spirv64, |
| 1019 | kalimba, | 1019 | kalimba, |
| 1020 | shave, | ||
| 1021 | lanai, | 1020 | lanai, |
| 1022 | wasm32, | 1021 | wasm32, |
| 1023 | wasm64, | 1022 | wasm64, |
| ... | @@ -1154,7 +1153,6 @@ pub const Cpu = struct { | ... | @@ -1154,7 +1153,6 @@ pub const Cpu = struct { |
| 1154 | .nvptx => .NONE, | 1153 | .nvptx => .NONE, |
| 1155 | .spir => .NONE, | 1154 | .spir => .NONE, |
| 1156 | .kalimba => .CSR_KALIMBA, | 1155 | .kalimba => .CSR_KALIMBA, |
| 1157 | .shave => .NONE, | ||
| 1158 | .lanai => .LANAI, | 1156 | .lanai => .LANAI, |
| 1159 | .wasm32 => .NONE, | 1157 | .wasm32 => .NONE, |
| 1160 | .aarch64_32 => .AARCH64, | 1158 | .aarch64_32 => .AARCH64, |
| ... | @@ -1211,7 +1209,6 @@ pub const Cpu = struct { | ... | @@ -1211,7 +1209,6 @@ pub const Cpu = struct { |
| 1211 | .nvptx => .Unknown, | 1209 | .nvptx => .Unknown, |
| 1212 | .spir => .Unknown, | 1210 | .spir => .Unknown, |
| 1213 | .kalimba => .Unknown, | 1211 | .kalimba => .Unknown, |
| 1214 | .shave => .Unknown, | ||
| 1215 | .lanai => .Unknown, | 1212 | .lanai => .Unknown, |
| 1216 | .wasm32 => .Unknown, | 1213 | .wasm32 => .Unknown, |
| 1217 | .aarch64_32 => .ARM64, | 1214 | .aarch64_32 => .ARM64, |
| ... | @@ -1273,7 +1270,6 @@ pub const Cpu = struct { | ... | @@ -1273,7 +1270,6 @@ pub const Cpu = struct { |
| 1273 | .thumb, | 1270 | .thumb, |
| 1274 | .spir, | 1271 | .spir, |
| 1275 | .spir64, | 1272 | .spir64, |
| 1276 | .shave, | ||
| 1277 | .ve, | 1273 | .ve, |
| 1278 | .spu_2, | 1274 | .spu_2, |
| 1279 | // GPU bitness is opaque. For now, assume little endian. | 1275 | // GPU bitness is opaque. For now, assume little endian. |
| ... | @@ -1759,7 +1755,6 @@ pub const DynamicLinker = struct { | ... | @@ -1759,7 +1755,6 @@ pub const DynamicLinker = struct { |
| 1759 | .spir, | 1755 | .spir, |
| 1760 | .spir64, | 1756 | .spir64, |
| 1761 | .kalimba, | 1757 | .kalimba, |
| 1762 | .shave, | ||
| 1763 | .lanai, | 1758 | .lanai, |
| 1764 | .ve, | 1759 | .ve, |
| 1765 | .dxil, | 1760 | .dxil, |
| ... | @@ -1860,7 +1855,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { | ... | @@ -1860,7 +1855,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { |
| 1860 | .nvptx, | 1855 | .nvptx, |
| 1861 | .spir, | 1856 | .spir, |
| 1862 | .kalimba, | 1857 | .kalimba, |
| 1863 | .shave, | ||
| 1864 | .lanai, | 1858 | .lanai, |
| 1865 | .wasm32, | 1859 | .wasm32, |
| 1866 | .aarch64_32, | 1860 | .aarch64_32, |
| ... | @@ -2381,7 +2375,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { | ... | @@ -2381,7 +2375,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { |
| 2381 | .spir, | 2375 | .spir, |
| 2382 | .spirv32, | 2376 | .spirv32, |
| 2383 | .kalimba, | 2377 | .kalimba, |
| 2384 | .shave, | ||
| 2385 | .ve, | 2378 | .ve, |
| 2386 | .spu_2, | 2379 | .spu_2, |
| 2387 | .xtensa, | 2380 | .xtensa, |
| ... | @@ -2493,7 +2486,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { | ... | @@ -2493,7 +2486,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { |
| 2493 | .spir, | 2486 | .spir, |
| 2494 | .spirv32, | 2487 | .spirv32, |
| 2495 | .kalimba, | 2488 | .kalimba, |
| 2496 | .shave, | ||
| 2497 | .ve, | 2489 | .ve, |
| 2498 | .spu_2, | 2490 | .spu_2, |
| 2499 | .xtensa, | 2491 | .xtensa, |
src/Type.zig-1
| ... | @@ -1654,7 +1654,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { | ... | @@ -1654,7 +1654,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { |
| 1654 | .kalimba, | 1654 | .kalimba, |
| 1655 | .spirv, | 1655 | .spirv, |
| 1656 | .spirv32, | 1656 | .spirv32, |
| 1657 | .shave, | ||
| 1658 | .spir64, | 1657 | .spir64, |
| 1659 | .ve, | 1658 | .ve, |
| 1660 | .spirv64, | 1659 | .spirv64, |
src/Zcu.zig-1
| ... | @@ -3258,7 +3258,6 @@ pub fn atomicPtrAlignment( | ... | @@ -3258,7 +3258,6 @@ pub fn atomicPtrAlignment( |
| 3258 | .spir, | 3258 | .spir, |
| 3259 | .kalimba, | 3259 | .kalimba, |
| 3260 | .lanai, | 3260 | .lanai, |
| 3261 | .shave, | ||
| 3262 | .wasm32, | 3261 | .wasm32, |
| 3263 | .csky, | 3262 | .csky, |
| 3264 | .spirv32, | 3263 | .spirv32, |
src/codegen/llvm.zig-3
| ... | @@ -88,7 +88,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { | ... | @@ -88,7 +88,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { |
| 88 | .spirv32 => "spirv32", | 88 | .spirv32 => "spirv32", |
| 89 | .spirv64 => "spirv64", | 89 | .spirv64 => "spirv64", |
| 90 | .kalimba => "kalimba", | 90 | .kalimba => "kalimba", |
| 91 | .shave => "shave", | ||
| 92 | .lanai => "lanai", | 91 | .lanai => "lanai", |
| 93 | .wasm32 => "wasm32", | 92 | .wasm32 => "wasm32", |
| 94 | .wasm64 => "wasm64", | 93 | .wasm64 => "wasm64", |
| ... | @@ -305,7 +304,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { | ... | @@ -305,7 +304,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { |
| 305 | .spirv32 => .spirv32, | 304 | .spirv32 => .spirv32, |
| 306 | .spirv64 => .spirv64, | 305 | .spirv64 => .spirv64, |
| 307 | .kalimba => .kalimba, | 306 | .kalimba => .kalimba, |
| 308 | .shave => .shave, | ||
| 309 | .lanai => .lanai, | 307 | .lanai => .lanai, |
| 310 | .wasm32 => .wasm32, | 308 | .wasm32 => .wasm32, |
| 311 | .wasm64 => .wasm64, | 309 | .wasm64 => .wasm64, |
| ... | @@ -12080,7 +12078,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { | ... | @@ -12080,7 +12078,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { |
| 12080 | // LLVM backends that have no initialization functions. | 12078 | // LLVM backends that have no initialization functions. |
| 12081 | .tce, | 12079 | .tce, |
| 12082 | .tcele, | 12080 | .tcele, |
| 12083 | .shave, | ||
| 12084 | .spir, | 12081 | .spir, |
| 12085 | .spir64, | 12082 | .spir64, |
| 12086 | .spirv, | 12083 | .spirv, |
src/target.zig-1
| ... | @@ -158,7 +158,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { | ... | @@ -158,7 +158,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { |
| 158 | .spirv32, | 158 | .spirv32, |
| 159 | .spirv64, | 159 | .spirv64, |
| 160 | .kalimba, | 160 | .kalimba, |
| 161 | .shave, | ||
| 162 | .lanai, | 161 | .lanai, |
| 163 | .wasm32, | 162 | .wasm32, |
| 164 | .wasm64, | 163 | .wasm64, |