| ... | @@ -55,7 +55,17 @@ static ErrorMsg *exec_add_error_node(CodeGen *codegen, Stage1Zir *exec, AstNode | ... | @@ -55,7 +55,17 @@ static ErrorMsg *exec_add_error_node(CodeGen *codegen, Stage1Zir *exec, AstNode |
| 55 | | 55 | |
| 56 | | 56 | |
| 57 | static bool instr_is_unreachable(IrInstSrc *instruction) { | 57 | static bool instr_is_unreachable(IrInstSrc *instruction) { |
| 58 | return instruction->is_noreturn; | 58 | switch (instruction->id) { |
| | 59 | case IrInstSrcIdCondBr: |
| | 60 | case IrInstSrcIdReturn: |
| | 61 | case IrInstSrcIdBr: |
| | 62 | case IrInstSrcIdUnreachable: |
| | 63 | case IrInstSrcIdSwitchBr: |
| | 64 | case IrInstSrcIdPanic: |
| | 65 | return true; |
| | 66 | default: |
| | 67 | return false; |
| | 68 | } |
| 59 | } | 69 | } |
| 60 | | 70 | |
| 61 | void destroy_instruction_src(IrInstSrc *inst) { | 71 | void destroy_instruction_src(IrInstSrc *inst) { |
| ... | @@ -947,7 +957,6 @@ static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *sour | ... | @@ -947,7 +957,6 @@ static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *sour |
| 947 | Stage1ZirBasicBlock *then_block, Stage1ZirBasicBlock *else_block, IrInstSrc *is_comptime) | 957 | Stage1ZirBasicBlock *then_block, Stage1ZirBasicBlock *else_block, IrInstSrc *is_comptime) |
| 948 | { | 958 | { |
| 949 | IrInstSrcCondBr *inst = ir_build_instruction<IrInstSrcCondBr>(ag, scope, source_node); | 959 | IrInstSrcCondBr *inst = ir_build_instruction<IrInstSrcCondBr>(ag, scope, source_node); |
| 950 | inst->base.is_noreturn = true; | | |
| 951 | inst->condition = condition; | 960 | inst->condition = condition; |
| 952 | inst->then_block = then_block; | 961 | inst->then_block = then_block; |
| 953 | inst->else_block = else_block; | 962 | inst->else_block = else_block; |
| ... | @@ -963,7 +972,6 @@ static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *sour | ... | @@ -963,7 +972,6 @@ static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *sour |
| 963 | | 972 | |
| 964 | static IrInstSrc *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *operand) { | 973 | static IrInstSrc *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *operand) { |
| 965 | IrInstSrcReturn *inst = ir_build_instruction<IrInstSrcReturn>(ag, scope, source_node); | 974 | IrInstSrcReturn *inst = ir_build_instruction<IrInstSrcReturn>(ag, scope, source_node); |
| 966 | inst->base.is_noreturn = true; | | |
| 967 | inst->operand = operand; | 975 | inst->operand = operand; |
| 968 | | 976 | |
| 969 | if (operand != nullptr) ir_ref_instruction(operand, ag->current_basic_block); | 977 | if (operand != nullptr) ir_ref_instruction(operand, ag->current_basic_block); |
| ... | @@ -1303,7 +1311,6 @@ static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_no | ... | @@ -1303,7 +1311,6 @@ static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_no |
| 1303 | Stage1ZirBasicBlock *dest_block, IrInstSrc *is_comptime) | 1311 | Stage1ZirBasicBlock *dest_block, IrInstSrc *is_comptime) |
| 1304 | { | 1312 | { |
| 1305 | IrInstSrcBr *inst = ir_build_instruction<IrInstSrcBr>(ag, scope, source_node); | 1313 | IrInstSrcBr *inst = ir_build_instruction<IrInstSrcBr>(ag, scope, source_node); |
| 1306 | inst->base.is_noreturn = true; | | |
| 1307 | inst->dest_block = dest_block; | 1314 | inst->dest_block = dest_block; |
| 1308 | inst->is_comptime = is_comptime; | 1315 | inst->is_comptime = is_comptime; |
| 1309 | | 1316 | |
| ... | @@ -1418,7 +1425,6 @@ static IrInstSrc *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope, | ... | @@ -1418,7 +1425,6 @@ static IrInstSrc *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope, |
| 1418 | | 1425 | |
| 1419 | static IrInstSrc *ir_build_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { | 1426 | static IrInstSrc *ir_build_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { |
| 1420 | IrInstSrcUnreachable *inst = ir_build_instruction<IrInstSrcUnreachable>(ag, scope, source_node); | 1427 | IrInstSrcUnreachable *inst = ir_build_instruction<IrInstSrcUnreachable>(ag, scope, source_node); |
| 1421 | inst->base.is_noreturn = true; | | |
| 1422 | return &inst->base; | 1428 | return &inst->base; |
| 1423 | } | 1429 | } |
| 1424 | | 1430 | |
| ... | @@ -1718,7 +1724,6 @@ static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, | ... | @@ -1718,7 +1724,6 @@ static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, |
| 1718 | IrInstSrc *is_comptime, IrInstSrc *switch_prongs_void) | 1724 | IrInstSrc *is_comptime, IrInstSrc *switch_prongs_void) |
| 1719 | { | 1725 | { |
| 1720 | IrInstSrcSwitchBr *instruction = ir_build_instruction<IrInstSrcSwitchBr>(ag, scope, source_node); | 1726 | IrInstSrcSwitchBr *instruction = ir_build_instruction<IrInstSrcSwitchBr>(ag, scope, source_node); |
| 1721 | instruction->base.is_noreturn = true; | | |
| 1722 | instruction->target_value = target_value; | 1727 | instruction->target_value = target_value; |
| 1723 | instruction->else_block = else_block; | 1728 | instruction->else_block = else_block; |
| 1724 | instruction->case_count = case_count; | 1729 | instruction->case_count = case_count; |
| ... | @@ -2439,7 +2444,6 @@ static IrInstSrc *ir_build_decl_ref(Stage1AstGen *ag, Scope *scope, AstNode *sou | ... | @@ -2439,7 +2444,6 @@ static IrInstSrc *ir_build_decl_ref(Stage1AstGen *ag, Scope *scope, AstNode *sou |
| 2439 | | 2444 | |
| 2440 | static IrInstSrc *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *msg) { | 2445 | static IrInstSrc *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *msg) { |
| 2441 | IrInstSrcPanic *instruction = ir_build_instruction<IrInstSrcPanic>(ag, scope, source_node); | 2446 | IrInstSrcPanic *instruction = ir_build_instruction<IrInstSrcPanic>(ag, scope, source_node); |
| 2442 | instruction->base.is_noreturn = true; | | |
| 2443 | instruction->msg = msg; | 2447 | instruction->msg = msg; |
| 2444 | | 2448 | |
| 2445 | ir_ref_instruction(msg, ag->current_basic_block); | 2449 | ir_ref_instruction(msg, ag->current_basic_block); |
| ... | @@ -2937,7 +2941,7 @@ static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope | ... | @@ -2937,7 +2941,7 @@ static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope |
| 2937 | if (defer_expr_value == ag->codegen->invalid_inst_src) | 2941 | if (defer_expr_value == ag->codegen->invalid_inst_src) |
| 2938 | return ag->codegen->invalid_inst_src; | 2942 | return ag->codegen->invalid_inst_src; |
| 2939 | | 2943 | |
| 2940 | if (defer_expr_value->is_noreturn) { | 2944 | if (instr_is_unreachable(defer_expr_value)) { |
| 2941 | if (is_noreturn != nullptr) *is_noreturn = true; | 2945 | if (is_noreturn != nullptr) *is_noreturn = true; |
| 2942 | } else { | 2946 | } else { |
| 2943 | ir_build_check_statement_is_void(ag, defer_expr_scope, defer_expr_node, | 2947 | ir_build_check_statement_is_void(ag, defer_expr_scope, defer_expr_node, |