authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 14:07:35+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 22:38:30+02:00
log67a052df81dbd40a49ce07b58e854d56b1def03a
tree906c6c649adee2568f17ea48f37888afcd5d9fd6
parentc825b567b26c475e058e074e5d22af006854fab6
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove `amdil`/`amdil64` arch tags.

This is really obscure and no one is 100% sure what it is. It seems to be old and unused. My suspicion is that it's just an old term for "AMDGPU" before it was upstreamed to LLVM. See: https://github.com/search?q=repo%3Allvm%2Fllvm-project+amdil&type=code

6 files changed, 0 insertions(+), 34 deletions(-)

lib/compiler/aro/aro/target.zig-6
...@@ -480,7 +480,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {...@@ -480,7 +480,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
480 .x86,480 .x86,
481 .xcore,481 .xcore,
482 .nvptx,482 .nvptx,
483 .amdil,
484 .hsail,483 .hsail,
485 .spir,484 .spir,
486 .kalimba,485 .kalimba,
...@@ -496,7 +495,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {...@@ -496,7 +495,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
496495
497 .aarch64 => copy.cpu.arch = .arm,496 .aarch64 => copy.cpu.arch = .arm,
498 .aarch64_be => copy.cpu.arch = .armeb,497 .aarch64_be => copy.cpu.arch = .armeb,
499 .amdil64 => copy.cpu.arch = .amdil,
500 .nvptx64 => copy.cpu.arch = .nvptx,498 .nvptx64 => copy.cpu.arch = .nvptx,
501 .wasm64 => copy.cpu.arch = .wasm32,499 .wasm64 => copy.cpu.arch = .wasm32,
502 .hsail64 => copy.cpu.arch = .hsail,500 .hsail64 => copy.cpu.arch = .hsail,
...@@ -540,7 +538,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {...@@ -540,7 +538,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
540 .amdgcn,538 .amdgcn,
541 .bpfeb,539 .bpfeb,
542 .bpfel,540 .bpfel,
543 .amdil64,
544 .nvptx64,541 .nvptx64,
545 .wasm64,542 .wasm64,
546 .hsail64,543 .hsail64,
...@@ -559,7 +556,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {...@@ -559,7 +556,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
559 => {}, // Already 64 bit556 => {}, // Already 64 bit
560557
561 .aarch64_32 => copy.cpu.arch = .aarch64,558 .aarch64_32 => copy.cpu.arch = .aarch64,
562 .amdil => copy.cpu.arch = .amdil64,
563 .arm => copy.cpu.arch = .aarch64,559 .arm => copy.cpu.arch = .aarch64,
564 .armeb => copy.cpu.arch = .aarch64_be,560 .armeb => copy.cpu.arch = .aarch64_be,
565 .hsail => copy.cpu.arch = .hsail64,561 .hsail => copy.cpu.arch = .hsail64,
...@@ -631,8 +627,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {...@@ -631,8 +627,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
631 .xtensa => "xtensa",627 .xtensa => "xtensa",
632 .nvptx => "nvptx",628 .nvptx => "nvptx",
633 .nvptx64 => "nvptx64",629 .nvptx64 => "nvptx64",
634 .amdil => "amdil",
635 .amdil64 => "amdil64",
636 .hsail => "hsail",630 .hsail => "hsail",
637 .hsail64 => "hsail64",631 .hsail64 => "hsail64",
638 .spir => "spir",632 .spir => "spir",
lib/std/Target.zig-16
...@@ -1011,8 +1011,6 @@ pub const Cpu = struct {...@@ -1011,8 +1011,6 @@ pub const Cpu = struct {
1011 xtensa,1011 xtensa,
1012 nvptx,1012 nvptx,
1013 nvptx64,1013 nvptx64,
1014 amdil,
1015 amdil64,
1016 hsail,1014 hsail,
1017 hsail64,1015 hsail64,
1018 spir,1016 spir,
...@@ -1156,7 +1154,6 @@ pub const Cpu = struct {...@@ -1156,7 +1154,6 @@ pub const Cpu = struct {
1156 .xcore => .XCORE,1154 .xcore => .XCORE,
1157 .xtensa => .XTENSA,1155 .xtensa => .XTENSA,
1158 .nvptx => .NONE,1156 .nvptx => .NONE,
1159 .amdil => .NONE,
1160 .hsail => .NONE,1157 .hsail => .NONE,
1161 .spir => .NONE,1158 .spir => .NONE,
1162 .kalimba => .CSR_KALIMBA,1159 .kalimba => .CSR_KALIMBA,
...@@ -1173,7 +1170,6 @@ pub const Cpu = struct {...@@ -1173,7 +1170,6 @@ pub const Cpu = struct {
1173 .riscv64 => .RISCV,1170 .riscv64 => .RISCV,
1174 .x86_64 => .X86_64,1171 .x86_64 => .X86_64,
1175 .nvptx64 => .NONE,1172 .nvptx64 => .NONE,
1176 .amdil64 => .NONE,
1177 .hsail64 => .NONE,1173 .hsail64 => .NONE,
1178 .spir64 => .NONE,1174 .spir64 => .NONE,
1179 .wasm64 => .NONE,1175 .wasm64 => .NONE,
...@@ -1217,7 +1213,6 @@ pub const Cpu = struct {...@@ -1217,7 +1213,6 @@ pub const Cpu = struct {
1217 .xcore => .Unknown,1213 .xcore => .Unknown,
1218 .xtensa => .Unknown,1214 .xtensa => .Unknown,
1219 .nvptx => .Unknown,1215 .nvptx => .Unknown,
1220 .amdil => .Unknown,
1221 .hsail => .Unknown,1216 .hsail => .Unknown,
1222 .spir => .Unknown,1217 .spir => .Unknown,
1223 .kalimba => .Unknown,1218 .kalimba => .Unknown,
...@@ -1234,7 +1229,6 @@ pub const Cpu = struct {...@@ -1234,7 +1229,6 @@ pub const Cpu = struct {
1234 .riscv64 => .RISCV64,1229 .riscv64 => .RISCV64,
1235 .x86_64 => .X64,1230 .x86_64 => .X64,
1236 .nvptx64 => .Unknown,1231 .nvptx64 => .Unknown,
1237 .amdil64 => .Unknown,
1238 .hsail64 => .Unknown,1232 .hsail64 => .Unknown,
1239 .spir64 => .Unknown,1233 .spir64 => .Unknown,
1240 .wasm64 => .Unknown,1234 .wasm64 => .Unknown,
...@@ -1261,8 +1255,6 @@ pub const Cpu = struct {...@@ -1261,8 +1255,6 @@ pub const Cpu = struct {
1261 .aarch64_32,1255 .aarch64_32,
1262 .aarch64,1256 .aarch64,
1263 .amdgcn,1257 .amdgcn,
1264 .amdil,
1265 .amdil64,
1266 .bpfel,1258 .bpfel,
1267 .csky,1259 .csky,
1268 .xtensa,1260 .xtensa,
...@@ -1772,8 +1764,6 @@ pub const DynamicLinker = struct {...@@ -1772,8 +1764,6 @@ pub const DynamicLinker = struct {
1772 .tce,1764 .tce,
1773 .tcele,1765 .tcele,
1774 .xcore,1766 .xcore,
1775 .amdil,
1776 .amdil64,
1777 .hsail,1767 .hsail,
1778 .hsail64,1768 .hsail64,
1779 .spir,1769 .spir,
...@@ -1878,7 +1868,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {...@@ -1878,7 +1868,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
1878 .x86,1868 .x86,
1879 .xcore,1869 .xcore,
1880 .nvptx,1870 .nvptx,
1881 .amdil,
1882 .hsail,1871 .hsail,
1883 .spir,1872 .spir,
1884 .kalimba,1873 .kalimba,
...@@ -1901,7 +1890,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {...@@ -1901,7 +1890,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
1901 .riscv64,1890 .riscv64,
1902 .x86_64,1891 .x86_64,
1903 .nvptx64,1892 .nvptx64,
1904 .amdil64,
1905 .hsail64,1893 .hsail64,
1906 .spir64,1894 .spir64,
1907 .wasm64,1895 .wasm64,
...@@ -2402,7 +2390,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {...@@ -2402,7 +2390,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
2402 .loongarch32,2390 .loongarch32,
2403 .tce,2391 .tce,
2404 .tcele,2392 .tcele,
2405 .amdil,
2406 .hsail,2393 .hsail,
2407 .spir,2394 .spir,
2408 .spirv32,2395 .spirv32,
...@@ -2415,7 +2402,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {...@@ -2415,7 +2402,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
24152402
2416 .aarch64_32,2403 .aarch64_32,
2417 .amdgcn,2404 .amdgcn,
2418 .amdil64,
2419 .bpfel,2405 .bpfel,
2420 .bpfeb,2406 .bpfeb,
2421 .hexagon,2407 .hexagon,
...@@ -2518,7 +2504,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {...@@ -2518,7 +2504,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
2518 .loongarch32,2504 .loongarch32,
2519 .tce,2505 .tce,
2520 .tcele,2506 .tcele,
2521 .amdil,
2522 .hsail,2507 .hsail,
2523 .spir,2508 .spir,
2524 .spirv32,2509 .spirv32,
...@@ -2537,7 +2522,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {...@@ -2537,7 +2522,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
2537 .thumbeb,2522 .thumbeb,
2538 .aarch64_32,2523 .aarch64_32,
2539 .amdgcn,2524 .amdgcn,
2540 .amdil64,
2541 .bpfel,2525 .bpfel,
2542 .bpfeb,2526 .bpfeb,
2543 .hexagon,2527 .hexagon,
src/Type.zig-2
...@@ -1650,14 +1650,12 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {...@@ -1650,14 +1650,12 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
1650 .m68k,1650 .m68k,
1651 .tce,1651 .tce,
1652 .tcele,1652 .tcele,
1653 .amdil,
1654 .hsail,1653 .hsail,
1655 .spir,1654 .spir,
1656 .kalimba,1655 .kalimba,
1657 .spirv,1656 .spirv,
1658 .spirv32,1657 .spirv32,
1659 .shave,1658 .shave,
1660 .amdil64,
1661 .hsail64,1659 .hsail64,
1662 .spir64,1660 .spir64,
1663 .ve,1661 .ve,
src/Zcu.zig-2
...@@ -3255,7 +3255,6 @@ pub fn atomicPtrAlignment(...@@ -3255,7 +3255,6 @@ pub fn atomicPtrAlignment(
3255 .thumbeb,3255 .thumbeb,
3256 .x86,3256 .x86,
3257 .xcore,3257 .xcore,
3258 .amdil,
3259 .hsail,3258 .hsail,
3260 .spir,3259 .spir,
3261 .kalimba,3260 .kalimba,
...@@ -3280,7 +3279,6 @@ pub fn atomicPtrAlignment(...@@ -3280,7 +3279,6 @@ pub fn atomicPtrAlignment(
3280 .riscv64,3279 .riscv64,
3281 .sparc64,3280 .sparc64,
3282 .s390x,3281 .s390x,
3283 .amdil64,
3284 .hsail64,3282 .hsail64,
3285 .spir64,3283 .spir64,
3286 .wasm64,3284 .wasm64,
src/codegen/llvm.zig-6
...@@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {...@@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
82 .xtensa => "xtensa",82 .xtensa => "xtensa",
83 .nvptx => "nvptx",83 .nvptx => "nvptx",
84 .nvptx64 => "nvptx64",84 .nvptx64 => "nvptx64",
85 .amdil => "amdil",
86 .amdil64 => "amdil64",
87 .hsail => "hsail",85 .hsail => "hsail",
88 .hsail64 => "hsail64",86 .hsail64 => "hsail64",
89 .spir => "spir",87 .spir => "spir",
...@@ -303,8 +301,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {...@@ -303,8 +301,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
303 .xtensa => .xtensa,301 .xtensa => .xtensa,
304 .nvptx => .nvptx,302 .nvptx => .nvptx,
305 .nvptx64 => .nvptx64,303 .nvptx64 => .nvptx64,
306 .amdil => .amdil,
307 .amdil64 => .amdil64,
308 .hsail => .hsail,304 .hsail => .hsail,
309 .hsail64 => .hsail64,305 .hsail64 => .hsail64,
310 .spir => .spir,306 .spir => .spir,
...@@ -12088,8 +12084,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {...@@ -12088,8 +12084,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
12088 // LLVM backends that have no initialization functions.12084 // LLVM backends that have no initialization functions.
12089 .tce,12085 .tce,
12090 .tcele,12086 .tcele,
12091 .amdil,
12092 .amdil64,
12093 .hsail,12087 .hsail,
12094 .hsail64,12088 .hsail64,
12095 .shave,12089 .shave,
src/target.zig-2
...@@ -152,8 +152,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {...@@ -152,8 +152,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
152 .xtensa,152 .xtensa,
153 .nvptx,153 .nvptx,
154 .nvptx64,154 .nvptx64,
155 .amdil,
156 .amdil64,
157 .hsail,155 .hsail,
158 .hsail64,156 .hsail64,
159 .spir,157 .spir,