authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 14:07:35+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 22:38:30+02:00
log67a052df81dbd40a49ce07b58e854d56b1def03a
tree906c6c649adee2568f17ea48f37888afcd5d9fd6
parentc825b567b26c475e058e074e5d22af006854fab6
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove `amdil`/`amdil64` arch tags.

This is really obscure and no one is 100% sure what it is. It seems to be old and unused. My suspicion is that it's just an old term for "AMDGPU" before it was upstreamed to LLVM. See: https://github.com/search?q=repo%3Allvm%2Fllvm-project+amdil&type=code

6 files changed, 0 insertions(+), 34 deletions(-)

lib/compiler/aro/aro/target.zig-6
......@@ -480,7 +480,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
480480 .x86,
481481 .xcore,
482482 .nvptx,
483 .amdil,
484483 .hsail,
485484 .spir,
486485 .kalimba,
......@@ -496,7 +495,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
496495
497496 .aarch64 => copy.cpu.arch = .arm,
498497 .aarch64_be => copy.cpu.arch = .armeb,
499 .amdil64 => copy.cpu.arch = .amdil,
500498 .nvptx64 => copy.cpu.arch = .nvptx,
501499 .wasm64 => copy.cpu.arch = .wasm32,
502500 .hsail64 => copy.cpu.arch = .hsail,
......@@ -540,7 +538,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
540538 .amdgcn,
541539 .bpfeb,
542540 .bpfel,
543 .amdil64,
544541 .nvptx64,
545542 .wasm64,
546543 .hsail64,
......@@ -559,7 +556,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
559556 => {}, // Already 64 bit
560557
561558 .aarch64_32 => copy.cpu.arch = .aarch64,
562 .amdil => copy.cpu.arch = .amdil64,
563559 .arm => copy.cpu.arch = .aarch64,
564560 .armeb => copy.cpu.arch = .aarch64_be,
565561 .hsail => copy.cpu.arch = .hsail64,
......@@ -631,8 +627,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
631627 .xtensa => "xtensa",
632628 .nvptx => "nvptx",
633629 .nvptx64 => "nvptx64",
634 .amdil => "amdil",
635 .amdil64 => "amdil64",
636630 .hsail => "hsail",
637631 .hsail64 => "hsail64",
638632 .spir => "spir",
lib/std/Target.zig-16
......@@ -1011,8 +1011,6 @@ pub const Cpu = struct {
10111011 xtensa,
10121012 nvptx,
10131013 nvptx64,
1014 amdil,
1015 amdil64,
10161014 hsail,
10171015 hsail64,
10181016 spir,
......@@ -1156,7 +1154,6 @@ pub const Cpu = struct {
11561154 .xcore => .XCORE,
11571155 .xtensa => .XTENSA,
11581156 .nvptx => .NONE,
1159 .amdil => .NONE,
11601157 .hsail => .NONE,
11611158 .spir => .NONE,
11621159 .kalimba => .CSR_KALIMBA,
......@@ -1173,7 +1170,6 @@ pub const Cpu = struct {
11731170 .riscv64 => .RISCV,
11741171 .x86_64 => .X86_64,
11751172 .nvptx64 => .NONE,
1176 .amdil64 => .NONE,
11771173 .hsail64 => .NONE,
11781174 .spir64 => .NONE,
11791175 .wasm64 => .NONE,
......@@ -1217,7 +1213,6 @@ pub const Cpu = struct {
12171213 .xcore => .Unknown,
12181214 .xtensa => .Unknown,
12191215 .nvptx => .Unknown,
1220 .amdil => .Unknown,
12211216 .hsail => .Unknown,
12221217 .spir => .Unknown,
12231218 .kalimba => .Unknown,
......@@ -1234,7 +1229,6 @@ pub const Cpu = struct {
12341229 .riscv64 => .RISCV64,
12351230 .x86_64 => .X64,
12361231 .nvptx64 => .Unknown,
1237 .amdil64 => .Unknown,
12381232 .hsail64 => .Unknown,
12391233 .spir64 => .Unknown,
12401234 .wasm64 => .Unknown,
......@@ -1261,8 +1255,6 @@ pub const Cpu = struct {
12611255 .aarch64_32,
12621256 .aarch64,
12631257 .amdgcn,
1264 .amdil,
1265 .amdil64,
12661258 .bpfel,
12671259 .csky,
12681260 .xtensa,
......@@ -1772,8 +1764,6 @@ pub const DynamicLinker = struct {
17721764 .tce,
17731765 .tcele,
17741766 .xcore,
1775 .amdil,
1776 .amdil64,
17771767 .hsail,
17781768 .hsail64,
17791769 .spir,
......@@ -1878,7 +1868,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
18781868 .x86,
18791869 .xcore,
18801870 .nvptx,
1881 .amdil,
18821871 .hsail,
18831872 .spir,
18841873 .kalimba,
......@@ -1901,7 +1890,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
19011890 .riscv64,
19021891 .x86_64,
19031892 .nvptx64,
1904 .amdil64,
19051893 .hsail64,
19061894 .spir64,
19071895 .wasm64,
......@@ -2402,7 +2390,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
24022390 .loongarch32,
24032391 .tce,
24042392 .tcele,
2405 .amdil,
24062393 .hsail,
24072394 .spir,
24082395 .spirv32,
......@@ -2415,7 +2402,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
24152402
24162403 .aarch64_32,
24172404 .amdgcn,
2418 .amdil64,
24192405 .bpfel,
24202406 .bpfeb,
24212407 .hexagon,
......@@ -2518,7 +2504,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
25182504 .loongarch32,
25192505 .tce,
25202506 .tcele,
2521 .amdil,
25222507 .hsail,
25232508 .spir,
25242509 .spirv32,
......@@ -2537,7 +2522,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
25372522 .thumbeb,
25382523 .aarch64_32,
25392524 .amdgcn,
2540 .amdil64,
25412525 .bpfel,
25422526 .bpfeb,
25432527 .hexagon,
src/Type.zig-2
......@@ -1650,14 +1650,12 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
16501650 .m68k,
16511651 .tce,
16521652 .tcele,
1653 .amdil,
16541653 .hsail,
16551654 .spir,
16561655 .kalimba,
16571656 .spirv,
16581657 .spirv32,
16591658 .shave,
1660 .amdil64,
16611659 .hsail64,
16621660 .spir64,
16631661 .ve,
src/Zcu.zig-2
......@@ -3255,7 +3255,6 @@ pub fn atomicPtrAlignment(
32553255 .thumbeb,
32563256 .x86,
32573257 .xcore,
3258 .amdil,
32593258 .hsail,
32603259 .spir,
32613260 .kalimba,
......@@ -3280,7 +3279,6 @@ pub fn atomicPtrAlignment(
32803279 .riscv64,
32813280 .sparc64,
32823281 .s390x,
3283 .amdil64,
32843282 .hsail64,
32853283 .spir64,
32863284 .wasm64,
src/codegen/llvm.zig-6
......@@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
8282 .xtensa => "xtensa",
8383 .nvptx => "nvptx",
8484 .nvptx64 => "nvptx64",
85 .amdil => "amdil",
86 .amdil64 => "amdil64",
8785 .hsail => "hsail",
8886 .hsail64 => "hsail64",
8987 .spir => "spir",
......@@ -303,8 +301,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
303301 .xtensa => .xtensa,
304302 .nvptx => .nvptx,
305303 .nvptx64 => .nvptx64,
306 .amdil => .amdil,
307 .amdil64 => .amdil64,
308304 .hsail => .hsail,
309305 .hsail64 => .hsail64,
310306 .spir => .spir,
......@@ -12088,8 +12084,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1208812084 // LLVM backends that have no initialization functions.
1208912085 .tce,
1209012086 .tcele,
12091 .amdil,
12092 .amdil64,
1209312087 .hsail,
1209412088 .hsail64,
1209512089 .shave,
src/target.zig-2
......@@ -152,8 +152,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
152152 .xtensa,
153153 .nvptx,
154154 .nvptx64,
155 .amdil,
156 .amdil64,
157155 .hsail,
158156 .hsail64,
159157 .spir,