authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 14:04:52+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 22:38:30+02:00
logc825b567b26c475e058e074e5d22af006854fab6
tree8d91c905760ae925e4f05326dfb7b59a9160e75b
parent9848623e62d75507d94f4e4276c5e5c888d99f5d
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove the `r600` arch tag.

These are quite old GPUs, and it is unlikely that Zig will ever be able to target them. See: https://en.wikipedia.org/wiki/Radeon_HD_2000_series

8 files changed, 0 insertions(+), 19 deletions(-)

lib/compiler/aro/aro/target.zig-3
......@@ -470,7 +470,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
470470 .mipsel,
471471 .powerpc,
472472 .powerpcle,
473 .r600,
474473 .riscv32,
475474 .sparc,
476475 .sparcel,
......@@ -527,7 +526,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
527526 .lanai,
528527 .m68k,
529528 .msp430,
530 .r600,
531529 .shave,
532530 .sparcel,
533531 .spu_2,
......@@ -616,7 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
616614 .powerpcle => "powerpcle",
617615 .powerpc64 => "powerpc64",
618616 .powerpc64le => "powerpc64le",
619 .r600 => "r600",
620617 .amdgcn => "amdgcn",
621618 .riscv32 => "riscv32",
622619 .riscv64 => "riscv64",
lib/std/Target.zig-8
......@@ -994,7 +994,6 @@ pub const Cpu = struct {
994994 powerpcle,
995995 powerpc64,
996996 powerpc64le,
997 r600,
998997 amdgcn,
999998 riscv32,
1000999 riscv64,
......@@ -1146,7 +1145,6 @@ pub const Cpu = struct {
11461145 .mips => .MIPS,
11471146 .mipsel => .MIPS_RS3_LE,
11481147 .powerpc, .powerpcle => .PPC,
1149 .r600 => .NONE,
11501148 .riscv32 => .RISCV,
11511149 .sparc => .SPARC,
11521150 .sparcel => .SPARC,
......@@ -1208,7 +1206,6 @@ pub const Cpu = struct {
12081206 .mips => .Unknown,
12091207 .mipsel => .Unknown,
12101208 .powerpc, .powerpcle => .POWERPC,
1211 .r600 => .Unknown,
12121209 .riscv32 => .RISCV32,
12131210 .sparc => .Unknown,
12141211 .sparcel => .Unknown,
......@@ -1282,7 +1279,6 @@ pub const Cpu = struct {
12821279 .tcele,
12831280 .powerpcle,
12841281 .powerpc64le,
1285 .r600,
12861282 .riscv32,
12871283 .riscv64,
12881284 .x86,
......@@ -1772,7 +1768,6 @@ pub const DynamicLinker = struct {
17721768 .hexagon,
17731769 .m68k,
17741770 .msp430,
1775 .r600,
17761771 .amdgcn,
17771772 .tce,
17781773 .tcele,
......@@ -1874,7 +1869,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
18741869 .mipsel,
18751870 .powerpc,
18761871 .powerpcle,
1877 .r600,
18781872 .riscv32,
18791873 .sparcel,
18801874 .tce,
......@@ -2436,7 +2430,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
24362430 .lanai,
24372431 .nvptx,
24382432 .nvptx64,
2439 .r600,
24402433 .s390x,
24412434 .spir64,
24422435 .spirv64,
......@@ -2560,7 +2553,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
25602553 .lanai,
25612554 .nvptx,
25622555 .nvptx64,
2563 .r600,
25642556 .s390x,
25652557 .spir64,
25662558 .spirv64,
src/Type.zig-1
......@@ -1599,7 +1599,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
15991599 .mipsel,
16001600 .powerpc,
16011601 .powerpcle,
1602 .r600,
16031602 .amdgcn,
16041603 .riscv32,
16051604 .sparc,
src/Zcu.zig-1
......@@ -3246,7 +3246,6 @@ pub fn atomicPtrAlignment(
32463246 .nvptx,
32473247 .powerpc,
32483248 .powerpcle,
3249 .r600,
32503249 .riscv32,
32513250 .sparc,
32523251 .sparcel,
src/codegen/llvm.zig-3
......@@ -65,7 +65,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
6565 .powerpcle => "powerpcle",
6666 .powerpc64 => "powerpc64",
6767 .powerpc64le => "powerpc64le",
68 .r600 => "r600",
6968 .amdgcn => "amdgcn",
7069 .riscv32 => "riscv32",
7170 .riscv64 => "riscv64",
......@@ -287,7 +286,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
287286 .powerpcle => .ppcle,
288287 .powerpc64 => .ppc64,
289288 .powerpc64le => .ppc64le,
290 .r600 => .r600,
291289 .amdgcn => .amdgcn,
292290 .riscv32 => .riscv32,
293291 .riscv64 => .riscv64,
......@@ -12090,7 +12088,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1209012088 // LLVM backends that have no initialization functions.
1209112089 .tce,
1209212090 .tcele,
12093 .r600,
1209412091 .amdil,
1209512092 .amdil64,
1209612093 .hsail,
src/target.zig-1
......@@ -135,7 +135,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
135135 .powerpcle,
136136 .powerpc64,
137137 .powerpc64le,
138 .r600,
139138 .amdgcn,
140139 .riscv32,
141140 .riscv64,
test/behavior/align.zig-1
......@@ -94,7 +94,6 @@ test "alignment and size of structs with 128-bit fields" {
9494 .mipsel,
9595 .powerpc,
9696 .powerpcle,
97 .r600,
9897 .amdgcn,
9998 .riscv32,
10099 .sparc,
test/llvm_targets.zig-1
......@@ -76,7 +76,6 @@ const targets = [_]std.Target.Query{
7676 .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .gnu },
7777 .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .musl },
7878 .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .none },
79 //.{ .cpu_arch = .r600, .os_tag = .mesa3d, .abi = .none },
8079 .{ .cpu_arch = .riscv32, .os_tag = .freestanding, .abi = .none },
8180 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .none },
8281 .{ .cpu_arch = .riscv64, .os_tag = .freestanding, .abi = .none },