authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 14:04:52+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 22:38:30+02:00
logc825b567b26c475e058e074e5d22af006854fab6
tree8d91c905760ae925e4f05326dfb7b59a9160e75b
parent9848623e62d75507d94f4e4276c5e5c888d99f5d
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove the `r600` arch tag.

These are quite old GPUs, and it is unlikely that Zig will ever be able to target them. See: https://en.wikipedia.org/wiki/Radeon_HD_2000_series

8 files changed, 0 insertions(+), 19 deletions(-)

lib/compiler/aro/aro/target.zig-3
...@@ -470,7 +470,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {...@@ -470,7 +470,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
470 .mipsel,470 .mipsel,
471 .powerpc,471 .powerpc,
472 .powerpcle,472 .powerpcle,
473 .r600,
474 .riscv32,473 .riscv32,
475 .sparc,474 .sparc,
476 .sparcel,475 .sparcel,
...@@ -527,7 +526,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {...@@ -527,7 +526,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
527 .lanai,526 .lanai,
528 .m68k,527 .m68k,
529 .msp430,528 .msp430,
530 .r600,
531 .shave,529 .shave,
532 .sparcel,530 .sparcel,
533 .spu_2,531 .spu_2,
...@@ -616,7 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {...@@ -616,7 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
616 .powerpcle => "powerpcle",614 .powerpcle => "powerpcle",
617 .powerpc64 => "powerpc64",615 .powerpc64 => "powerpc64",
618 .powerpc64le => "powerpc64le",616 .powerpc64le => "powerpc64le",
619 .r600 => "r600",
620 .amdgcn => "amdgcn",617 .amdgcn => "amdgcn",
621 .riscv32 => "riscv32",618 .riscv32 => "riscv32",
622 .riscv64 => "riscv64",619 .riscv64 => "riscv64",
lib/std/Target.zig-8
...@@ -994,7 +994,6 @@ pub const Cpu = struct {...@@ -994,7 +994,6 @@ pub const Cpu = struct {
994 powerpcle,994 powerpcle,
995 powerpc64,995 powerpc64,
996 powerpc64le,996 powerpc64le,
997 r600,
998 amdgcn,997 amdgcn,
999 riscv32,998 riscv32,
1000 riscv64,999 riscv64,
...@@ -1146,7 +1145,6 @@ pub const Cpu = struct {...@@ -1146,7 +1145,6 @@ pub const Cpu = struct {
1146 .mips => .MIPS,1145 .mips => .MIPS,
1147 .mipsel => .MIPS_RS3_LE,1146 .mipsel => .MIPS_RS3_LE,
1148 .powerpc, .powerpcle => .PPC,1147 .powerpc, .powerpcle => .PPC,
1149 .r600 => .NONE,
1150 .riscv32 => .RISCV,1148 .riscv32 => .RISCV,
1151 .sparc => .SPARC,1149 .sparc => .SPARC,
1152 .sparcel => .SPARC,1150 .sparcel => .SPARC,
...@@ -1208,7 +1206,6 @@ pub const Cpu = struct {...@@ -1208,7 +1206,6 @@ pub const Cpu = struct {
1208 .mips => .Unknown,1206 .mips => .Unknown,
1209 .mipsel => .Unknown,1207 .mipsel => .Unknown,
1210 .powerpc, .powerpcle => .POWERPC,1208 .powerpc, .powerpcle => .POWERPC,
1211 .r600 => .Unknown,
1212 .riscv32 => .RISCV32,1209 .riscv32 => .RISCV32,
1213 .sparc => .Unknown,1210 .sparc => .Unknown,
1214 .sparcel => .Unknown,1211 .sparcel => .Unknown,
...@@ -1282,7 +1279,6 @@ pub const Cpu = struct {...@@ -1282,7 +1279,6 @@ pub const Cpu = struct {
1282 .tcele,1279 .tcele,
1283 .powerpcle,1280 .powerpcle,
1284 .powerpc64le,1281 .powerpc64le,
1285 .r600,
1286 .riscv32,1282 .riscv32,
1287 .riscv64,1283 .riscv64,
1288 .x86,1284 .x86,
...@@ -1772,7 +1768,6 @@ pub const DynamicLinker = struct {...@@ -1772,7 +1768,6 @@ pub const DynamicLinker = struct {
1772 .hexagon,1768 .hexagon,
1773 .m68k,1769 .m68k,
1774 .msp430,1770 .msp430,
1775 .r600,
1776 .amdgcn,1771 .amdgcn,
1777 .tce,1772 .tce,
1778 .tcele,1773 .tcele,
...@@ -1874,7 +1869,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {...@@ -1874,7 +1869,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
1874 .mipsel,1869 .mipsel,
1875 .powerpc,1870 .powerpc,
1876 .powerpcle,1871 .powerpcle,
1877 .r600,
1878 .riscv32,1872 .riscv32,
1879 .sparcel,1873 .sparcel,
1880 .tce,1874 .tce,
...@@ -2436,7 +2430,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {...@@ -2436,7 +2430,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
2436 .lanai,2430 .lanai,
2437 .nvptx,2431 .nvptx,
2438 .nvptx64,2432 .nvptx64,
2439 .r600,
2440 .s390x,2433 .s390x,
2441 .spir64,2434 .spir64,
2442 .spirv64,2435 .spirv64,
...@@ -2560,7 +2553,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {...@@ -2560,7 +2553,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
2560 .lanai,2553 .lanai,
2561 .nvptx,2554 .nvptx,
2562 .nvptx64,2555 .nvptx64,
2563 .r600,
2564 .s390x,2556 .s390x,
2565 .spir64,2557 .spir64,
2566 .spirv64,2558 .spirv64,
src/Type.zig-1
...@@ -1599,7 +1599,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {...@@ -1599,7 +1599,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
1599 .mipsel,1599 .mipsel,
1600 .powerpc,1600 .powerpc,
1601 .powerpcle,1601 .powerpcle,
1602 .r600,
1603 .amdgcn,1602 .amdgcn,
1604 .riscv32,1603 .riscv32,
1605 .sparc,1604 .sparc,
src/Zcu.zig-1
...@@ -3246,7 +3246,6 @@ pub fn atomicPtrAlignment(...@@ -3246,7 +3246,6 @@ pub fn atomicPtrAlignment(
3246 .nvptx,3246 .nvptx,
3247 .powerpc,3247 .powerpc,
3248 .powerpcle,3248 .powerpcle,
3249 .r600,
3250 .riscv32,3249 .riscv32,
3251 .sparc,3250 .sparc,
3252 .sparcel,3251 .sparcel,
src/codegen/llvm.zig-3
...@@ -65,7 +65,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {...@@ -65,7 +65,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
65 .powerpcle => "powerpcle",65 .powerpcle => "powerpcle",
66 .powerpc64 => "powerpc64",66 .powerpc64 => "powerpc64",
67 .powerpc64le => "powerpc64le",67 .powerpc64le => "powerpc64le",
68 .r600 => "r600",
69 .amdgcn => "amdgcn",68 .amdgcn => "amdgcn",
70 .riscv32 => "riscv32",69 .riscv32 => "riscv32",
71 .riscv64 => "riscv64",70 .riscv64 => "riscv64",
...@@ -287,7 +286,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {...@@ -287,7 +286,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
287 .powerpcle => .ppcle,286 .powerpcle => .ppcle,
288 .powerpc64 => .ppc64,287 .powerpc64 => .ppc64,
289 .powerpc64le => .ppc64le,288 .powerpc64le => .ppc64le,
290 .r600 => .r600,
291 .amdgcn => .amdgcn,289 .amdgcn => .amdgcn,
292 .riscv32 => .riscv32,290 .riscv32 => .riscv32,
293 .riscv64 => .riscv64,291 .riscv64 => .riscv64,
...@@ -12090,7 +12088,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {...@@ -12090,7 +12088,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
12090 // LLVM backends that have no initialization functions.12088 // LLVM backends that have no initialization functions.
12091 .tce,12089 .tce,
12092 .tcele,12090 .tcele,
12093 .r600,
12094 .amdil,12091 .amdil,
12095 .amdil64,12092 .amdil64,
12096 .hsail,12093 .hsail,
src/target.zig-1
...@@ -135,7 +135,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {...@@ -135,7 +135,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
135 .powerpcle,135 .powerpcle,
136 .powerpc64,136 .powerpc64,
137 .powerpc64le,137 .powerpc64le,
138 .r600,
139 .amdgcn,138 .amdgcn,
140 .riscv32,139 .riscv32,
141 .riscv64,140 .riscv64,
test/behavior/align.zig-1
...@@ -94,7 +94,6 @@ test "alignment and size of structs with 128-bit fields" {...@@ -94,7 +94,6 @@ test "alignment and size of structs with 128-bit fields" {
94 .mipsel,94 .mipsel,
95 .powerpc,95 .powerpc,
96 .powerpcle,96 .powerpcle,
97 .r600,
98 .amdgcn,97 .amdgcn,
99 .riscv32,98 .riscv32,
100 .sparc,99 .sparc,
test/llvm_targets.zig-1
...@@ -76,7 +76,6 @@ const targets = [_]std.Target.Query{...@@ -76,7 +76,6 @@ const targets = [_]std.Target.Query{
76 .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .gnu },76 .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .gnu },
77 .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .musl },77 .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .musl },
78 .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .none },78 .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .none },
79 //.{ .cpu_arch = .r600, .os_tag = .mesa3d, .abi = .none },
80 .{ .cpu_arch = .riscv32, .os_tag = .freestanding, .abi = .none },79 .{ .cpu_arch = .riscv32, .os_tag = .freestanding, .abi = .none },
81 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .none },80 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .none },
82 .{ .cpu_arch = .riscv64, .os_tag = .freestanding, .abi = .none },81 .{ .cpu_arch = .riscv64, .os_tag = .freestanding, .abi = .none },