authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-06 09:12:10+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-06 10:05:04+02:00
logf04a251e05c3f8bef73421b6bf152902153f55a6
tree1ab3ebef03263a36ac93e28c33b0eaf0e4ec4f35
parent80e52554bbaf2d2f029f860bd59945c477cde630
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.zig.system.freebsd: tiny refactor

1 files changed, 20 insertions(+), 18 deletions(-)

lib/std/zig/system/freebsd.zig+20-18
...@@ -9,28 +9,30 @@ const aarch64 = struct {...@@ -9,28 +9,30 @@ const aarch64 = struct {
9 : [ret] "=r" (-> u64),9 : [ret] "=r" (-> u64),
10 );10 );
11 }11 }
12
13 fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) std.Target.Cpu {
14 const registers = [12]u64{
15 aarch64.mrs("MIDR_EL1"),
16 aarch64.mrs("ID_AA64PFR0_EL1"),
17 aarch64.mrs("ID_AA64PFR1_EL1"),
18 aarch64.mrs("ID_AA64DFR0_EL1"),
19 aarch64.mrs("ID_AA64DFR1_EL1"),
20 aarch64.mrs("ID_AA64AFR0_EL1"),
21 aarch64.mrs("ID_AA64AFR1_EL1"),
22 aarch64.mrs("ID_AA64ISAR0_EL1"),
23 aarch64.mrs("ID_AA64ISAR1_EL1"),
24 aarch64.mrs("ID_AA64MMFR0_EL1"),
25 aarch64.mrs("ID_AA64MMFR1_EL1"),
26 aarch64.mrs("ID_AA64MMFR2_EL1"),
27 };
28
29 return @import("arm.zig").aarch64.detectNativeCpuAndFeatures(arch, registers);
30 }
12};31};
1332
14pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu {33pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu {
15 return switch (native_arch) {34 return switch (native_arch) {
16 .aarch64, .aarch64_be => b: {35 .aarch64 => aarch64.detectNativeCpuAndFeatures(native_arch),
17 const registers = [12]u64{
18 aarch64.mrs("MIDR_EL1"),
19 aarch64.mrs("ID_AA64PFR0_EL1"),
20 aarch64.mrs("ID_AA64PFR1_EL1"),
21 aarch64.mrs("ID_AA64DFR0_EL1"),
22 aarch64.mrs("ID_AA64DFR1_EL1"),
23 aarch64.mrs("ID_AA64AFR0_EL1"),
24 aarch64.mrs("ID_AA64AFR1_EL1"),
25 aarch64.mrs("ID_AA64ISAR0_EL1"),
26 aarch64.mrs("ID_AA64ISAR1_EL1"),
27 aarch64.mrs("ID_AA64MMFR0_EL1"),
28 aarch64.mrs("ID_AA64MMFR1_EL1"),
29 aarch64.mrs("ID_AA64MMFR2_EL1"),
30 };
31
32 break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(native_arch, registers);
33 },
34 else => null,36 else => null,
35 };37 };
36}38}