| ... | ... | @@ -9,28 +9,30 @@ const aarch64 = struct { |
| 9 | 9 | : [ret] "=r" (-> u64), |
| 10 | 10 | ); |
| 11 | 11 | } |
| 12 | |
| 13 | fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) std.Target.Cpu { |
| 14 | const registers = [12]u64{ |
| 15 | aarch64.mrs("MIDR_EL1"), |
| 16 | aarch64.mrs("ID_AA64PFR0_EL1"), |
| 17 | aarch64.mrs("ID_AA64PFR1_EL1"), |
| 18 | aarch64.mrs("ID_AA64DFR0_EL1"), |
| 19 | aarch64.mrs("ID_AA64DFR1_EL1"), |
| 20 | aarch64.mrs("ID_AA64AFR0_EL1"), |
| 21 | aarch64.mrs("ID_AA64AFR1_EL1"), |
| 22 | aarch64.mrs("ID_AA64ISAR0_EL1"), |
| 23 | aarch64.mrs("ID_AA64ISAR1_EL1"), |
| 24 | aarch64.mrs("ID_AA64MMFR0_EL1"), |
| 25 | aarch64.mrs("ID_AA64MMFR1_EL1"), |
| 26 | aarch64.mrs("ID_AA64MMFR2_EL1"), |
| 27 | }; |
| 28 | |
| 29 | return @import("arm.zig").aarch64.detectNativeCpuAndFeatures(arch, registers); |
| 30 | } |
| 12 | 31 | }; |
| 13 | 32 | |
| 14 | 33 | pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu { |
| 15 | 34 | return switch (native_arch) { |
| 16 | | .aarch64, .aarch64_be => b: { |
| 17 | | const registers = [12]u64{ |
| 18 | | aarch64.mrs("MIDR_EL1"), |
| 19 | | aarch64.mrs("ID_AA64PFR0_EL1"), |
| 20 | | aarch64.mrs("ID_AA64PFR1_EL1"), |
| 21 | | aarch64.mrs("ID_AA64DFR0_EL1"), |
| 22 | | aarch64.mrs("ID_AA64DFR1_EL1"), |
| 23 | | aarch64.mrs("ID_AA64AFR0_EL1"), |
| 24 | | aarch64.mrs("ID_AA64AFR1_EL1"), |
| 25 | | aarch64.mrs("ID_AA64ISAR0_EL1"), |
| 26 | | aarch64.mrs("ID_AA64ISAR1_EL1"), |
| 27 | | aarch64.mrs("ID_AA64MMFR0_EL1"), |
| 28 | | aarch64.mrs("ID_AA64MMFR1_EL1"), |
| 29 | | aarch64.mrs("ID_AA64MMFR2_EL1"), |
| 30 | | }; |
| 31 | | |
| 32 | | break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(native_arch, registers); |
| 33 | | }, |
| 35 | .aarch64 => aarch64.detectNativeCpuAndFeatures(native_arch), |
| 34 | 36 | else => null, |
| 35 | 37 | }; |
| 36 | 38 | } |
Alex Rønne Petersen <alex@alexrp.com> 2026-09-06 09:12:10+02:00